/*
** ###################################################################
**     Processors:          MIMXRT798SGAWAR_hifi4
**                          MIMXRT798SGFOA_hifi4
**
**     Compiler:            Xtensa Compiler
**     Reference manual:    iMXRT700RM Rev.2 DraftA, 05/2024
**     Version:             rev. 2.0, 2024-05-28
**     Build:               b240903
**
**     Abstract:
**         Peripheral Access Layer for MIMXRT798S_hifi4
**
**     Copyright 1997-2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2024 NXP
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
**     Revisions:
**     - rev. 1.0 (2022-09-15)
**         Initial version.
**     - rev. 2.0 (2024-05-28)
**         Rev2 DraftA.
**
** ###################################################################
*/

/*!
 * @file MIMXRT798S_hifi4.h
 * @version 2.0
 * @date 2024-05-28
 * @brief Peripheral Access Layer for MIMXRT798S_hifi4
 *
 * Peripheral Access Layer for MIMXRT798S_hifi4
 */

#if !defined(MIMXRT798S_HIFI4_H_)
#define MIMXRT798S_HIFI4_H_                      /**< Symbol preventing repeated inclusion */

/** Memory map major version (memory maps with equal major version number are
 * compatible) */
#define MCU_MEM_MAP_VERSION 0x0200U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U

/* ----------------------------------------------------------------------------
   --
   ---------------------------------------------------------------------------- */

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines
    <strong>IO Type Qualifiers</strong> are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#define     __I     volatile const       /*!< Defines 'read only' permissions */
#define     __O     volatile             /*!< Defines 'write only' permissions */
#define     __IO    volatile             /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

#define __STATIC_INLINE static inline

#define __BKPT(value) do {} while(0)
#define __NOP() do {} while(0)

#include "system_MIMXRT798S_hifi4.h"     /* Device specific configuration file */



/* ----------------------------------------------------------------------------
   -- Interrupt vector numbers
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
 * @{
 */

/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 136                /**< Number of interrupts in the Vector table */

typedef enum IRQn {
  /* Auxiliary constants */
  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */

  /* Core interrupts */
  NonMaskableInt_IRQn          = 0,                /**< SysIRQ, Non Maskable Interrupt */
  Software_IRQn                = 1,                /**< Software triggered Interrupt */
  RtosTimer0_IRQn              = 2,                /**< Internal RTOS Timer0 Interrupt */
  RtosTimer1_IRQn              = 3,                /**< Internal RTOS Timer1 Interrupt */
  Profiling_IRQn               = 4,                /**< Profiling Interrupt */

  /* Device specific interrupts */
  DSP_INT0_SEL0_IRQn           = 5,                /**< Interrupt selected by HIFI4_INTERRUPT0 */
  DSP_INT0_SEL1_IRQn           = 6,                /**< Interrupt selected by HIFI4_INTERRUPT1 */
  DSP_INT0_SEL2_IRQn           = 7,                /**< Interrupt selected by HIFI4_INTERRUPT2 */
  DSP_INT0_SEL3_IRQn           = 8,                /**< Interrupt selected by HIFI4_INTERRUPT3 */
  DSP_INT0_SEL4_IRQn           = 9,                /**< Interrupt selected by HIFI4_INTERRUPT4 */
  DSP_INT0_SEL5_IRQn           = 10,               /**< Interrupt selected by HIFI4_INTERRUPT5 */
  DSP_INT0_SEL6_IRQn           = 11,               /**< Interrupt selected by HIFI4_INTERRUPT6 */
  DSP_INT0_SEL7_IRQn           = 12,               /**< Interrupt selected by HIFI4_INTERRUPT7 */
  DSP_INT0_SEL8_IRQn           = 13,               /**< Interrupt selected by HIFI4_INTERRUPT8 */
  DSP_INT0_SEL9_IRQn           = 14,               /**< Interrupt selected by HIFI4_INTERRUPT9 */
  DSP_INT0_SEL10_IRQn          = 15,               /**< Interrupt selected by HIFI4_INTERRUPT10 */
  DSP_INT0_SEL11_IRQn          = 16,               /**< Interrupt selected by HIFI4_INTERRUPT11 */
  DSP_INT0_SEL12_IRQn          = 17,               /**< Interrupt selected by HIFI4_INTERRUPT12 */
  DSP_INT0_SEL13_IRQn          = 18,               /**< Interrupt selected by HIFI4_INTERRUPT13 */
  DSP_INT0_SEL14_IRQn          = 19,               /**< Interrupt selected by HIFI4_INTERRUPT14 */
  DSP_INT0_SEL15_IRQn          = 20,               /**< Interrupt selected by HIFI4_INTERRUPT15 */
  DSP_INT0_SEL16_IRQn          = 21,               /**< Interrupt selected by HIFI4_INTERRUPT16 */
  DSP_INT0_SEL17_IRQn          = 22,               /**< Interrupt selected by HIFI4_INTERRUPT17 */
  DSP_INT0_SEL18_IRQn          = 23,               /**< Interrupt selected by HIFI4_INTERRUPT18 */
  DSP_INT0_SEL19_IRQn          = 24,               /**< Interrupt selected by HIFI4_INTERRUPT19 */
  DSP_INT0_SEL20_IRQn          = 25,               /**< Interrupt selected by HIFI4_INTERRUPT20 */
  DSP_INT0_SEL21_IRQn          = 26,               /**< Interrupt selected by HIFI4_INTERRUPT21 */
  DSP_INT0_SEL22_IRQn          = 27,               /**< Interrupt selected by HIFI4_INTERRUPT22 */
  DSP_INT0_SEL23_IRQn          = 28,               /**< Interrupt selected by HIFI4_INTERRUPT23 */
  DSP_INT0_SEL24_IRQn          = 29,               /**< Interrupt selected by HIFI4_INTERRUPT24 */
  DSP_INT0_SEL25_IRQn          = 30,               /**< Interrupt selected by HIFI4_INTERRUPT25 */
  DSP_INT0_SEL26_IRQn          = 31,               /**< Interrupt selected by HIFI4_INTERRUPT26 */
  LP_FLEXCOMM0_IRQn            = 32,               /**< LP_FLEXCOMM0 (HIFI4_INTTERRUPTn source IRQ0) */
  LP_FLEXCOMM1_IRQn            = 33,               /**< LP_FLEXCOMM1 (HIFI4_INTTERRUPTn source IRQ1) */
  LP_FLEXCOMM2_IRQn            = 34,               /**< LP_FLEXCOMM2 (HIFI4_INTTERRUPTn source IRQ2) */
  LP_FLEXCOMM3_IRQn            = 35,               /**< LP_FLEXCOMM3 (HIFI4_INTTERRUPTn source IRQ3) */
  LP_FLEXCOMM4_IRQn            = 36,               /**< LP_FLEXCOMM4 (HIFI4_INTTERRUPTn source IRQ4) */
  LP_FLEXCOMM5_IRQn            = 37,               /**< LP_FLEXCOMM5 (HIFI4_INTTERRUPTn source IRQ5) */
  LP_FLEXCOMM6_IRQn            = 38,               /**< LP_FLEXCOMM6 (HIFI4_INTTERRUPTn source IRQ6) */
  LP_FLEXCOMM7_IRQn            = 39,               /**< LP_FLEXCOMM7 (HIFI4_INTTERRUPTn source IRQ7) */
  LP_FLEXCOMM8_IRQn            = 40,               /**< LP_FLEXCOMM8 (HIFI4_INTTERRUPTn source IRQ8) */
  LP_FLEXCOMM9_IRQn            = 41,               /**< LP_FLEXCOMM9 (HIFI4_INTTERRUPTn source IRQ9) */
  LP_FLEXCOMM10_IRQn           = 42,               /**< LP_FLEXCOMM10 (HIFI4_INTTERRUPTn source IRQ10) */
  LP_FLEXCOMM11_IRQn           = 43,               /**< LP_FLEXCOMM11 (HIFI4_INTTERRUPTn source IRQ11) */
  LP_FLEXCOMM12_IRQn           = 44,               /**< LP_FLEXCOMM12 (HIFI4_INTTERRUPTn source IRQ12) */
  LP_FLEXCOMM13_IRQn           = 45,               /**< LP_FLEXCOMM13 (HIFI4_INTTERRUPTn source IRQ13) */
  MU2_MUA_IRQn                 = 46,               /**< MU2_MUA (HIFI4_INTTERRUPTn source IRQ14) */
  MU4_MUB_IRQn                 = 47,               /**< MU4_MUB (HIFI4_INTTERRUPTn source IRQ15) */
  WWDT0_IRQn                   = 48,               /**< WWDT0 (HIFI4_INTTERRUPTn source IRQ16) */
  WWDT1_IRQn                   = 49,               /**< WWDT1 (HIFI4_INTTERRUPTn source IRQ17) */
  UTICK0_IRQn                  = 50,               /**< UTICK0 (HIFI4_INTTERRUPTn source IRQ18) */
  LPSPI14_IRQn                 = 51,               /**< LPSPI14 (HIFI4_INTTERRUPTn source IRQ19) */
  MRT0_IRQn                    = 52,               /**< MRT0 (HIFI4_INTTERRUPTn source IRQ20) */
  OSTIMER_IRQn                 = 53,               /**< OSTIMER (HIFI4_INTTERRUPTn source IRQ21) */
  CTIMER0_IRQn                 = 54,               /**< CTIMER0 (HIFI4_INTTERRUPTn source IRQ22) */
  CTIMER1_IRQn                 = 55,               /**< CTIMER1 (HIFI4_INTTERRUPTn source IRQ23) */
  CTIMER2_IRQn                 = 56,               /**< CTIMER2 (HIFI4_INTTERRUPTn source IRQ24) */
  CTIMER3_IRQn                 = 57,               /**< CTIMER3 (HIFI4_INTTERRUPTn source IRQ25) */
  CTIMER4_IRQn                 = 58,               /**< CTIMER4 (HIFI4_INTTERRUPTn source IRQ26) */
  RTC0_IRQn                    = 59,               /**< RTC0 (HIFI4_INTTERRUPTn source IRQ27) */
  RTC_SS0_IRQn                 = 60,               /**< RTC_SS0 (HIFI4_INTTERRUPTn source IRQ28) */
  I3C0_IRQn                    = 61,               /**< I3C0 (HIFI4_INTTERRUPTn source IRQ29) */
  I3C1_IRQn                    = 62,               /**< I3C1 (HIFI4_INTTERRUPTn source IRQ30) */
  PDM_EVENT_IRQn               = 63,               /**< MICFIL (HIFI4_INTTERRUPTn source IRQ31) */
  PDM_HWVAD_EVENT_IRQn         = 64,               /**< MICFIL HARDWARE (HIFI4_INTTERRUPTn source IRQ32) */
  LCDIF_IRQn                   = 65,               /**< LCDIF (HIFI4_INTTERRUPTn source IRQ33) */
  VGPU_IRQn                    = 66,               /**< VGPU (HIFI4_INTTERRUPTn source IRQ34) */
  EZH_V_IRQn                   = 67,               /**< EZH_V (HIFI4_INTTERRUPTn source IRQ35) */
  FLEXIO_IRQn                  = 68,               /**< FLEXIO (HIFI4_INTTERRUPTn source IRQ36) */
  LPSPI16_IRQn                 = 69,               /**< LPSPI16 (HIFI4_INTTERRUPTn source IRQ37) */
  EDMA0_CH0_IRQn               = 70,               /**< EDMA0_CH0 (HIFI4_INTTERRUPTn source IRQ38) */
  EDMA0_CH1_IRQn               = 71,               /**< EDMA0_CH1 (HIFI4_INTTERRUPTn source IRQ39) */
  EDMA0_CH2_IRQn               = 72,               /**< EDMA0_CH2 (HIFI4_INTTERRUPTn source IRQ40) */
  EDMA0_CH3_IRQn               = 73,               /**< EDMA0_CH3 (HIFI4_INTTERRUPTn source IRQ41) */
  EDMA0_CH4_IRQn               = 74,               /**< EDMA0_CH4 (HIFI4_INTTERRUPTn source IRQ42) */
  EDMA0_CH5_IRQn               = 75,               /**< EDMA0_CH5 (HIFI4_INTTERRUPTn source IRQ43) */
  EDMA0_CH6_IRQn               = 76,               /**< EDMA0_CH6 (HIFI4_INTTERRUPTn source IRQ44) */
  EDMA0_CH7_IRQn               = 77,               /**< EDMA0_CH7 (HIFI4_INTTERRUPTn source IRQ45) */
  EDMA0_CH8_IRQn               = 78,               /**< EDMA0_CH8 (HIFI4_INTTERRUPTn source IRQ46) */
  EDMA0_CH9_IRQn               = 79,               /**< EDMA0_CH9 (HIFI4_INTTERRUPTn source IRQ47) */
  EDMA0_CH10_IRQn              = 80,               /**< EDMA0_CH10 (HIFI4_INTTERRUPTn source IRQ48) */
  EDMA0_CH11_IRQn              = 81,               /**< EDMA0_CH11 (HIFI4_INTTERRUPTn source IRQ49) */
  EDMA0_CH12_IRQn              = 82,               /**< EDMA0_CH12 (HIFI4_INTTERRUPTn source IRQ50) */
  EDMA0_CH13_IRQn              = 83,               /**< EDMA0_CH13 (HIFI4_INTTERRUPTn source IRQ51) */
  EDMA0_CH14_IRQn              = 84,               /**< EDMA0_CH14 (HIFI4_INTTERRUPTn source IRQ52) */
  EDMA0_CH15_IRQn              = 85,               /**< EDMA0_CH15 (HIFI4_INTTERRUPTn source IRQ53) */
  EDMA1_CH0_IRQn               = 86,               /**< EDMA1_CH0 (HIFI4_INTTERRUPTn source IRQ54) */
  EDMA1_CH1_IRQn               = 87,               /**< EDMA1_CH1 (HIFI4_INTTERRUPTn source IRQ55) */
  EDMA1_CH2_IRQn               = 88,               /**< EDMA1_CH2 (HIFI4_INTTERRUPTn source IRQ56) */
  EDMA1_CH3_IRQn               = 89,               /**< EDMA1_CH3 (HIFI4_INTTERRUPTn source IRQ57) */
  EDMA1_CH4_IRQn               = 90,               /**< EDMA1_CH4 (HIFI4_INTTERRUPTn source IRQ58) */
  EDMA1_CH5_IRQn               = 91,               /**< EDMA1_CH5 (HIFI4_INTTERRUPTn source IRQ59) */
  EDMA1_CH6_IRQn               = 92,               /**< EDMA1_CH6 (HIFI4_INTTERRUPTn source IRQ60) */
  EDMA1_CH7_IRQn               = 93,               /**< EDMA1_CH7 (HIFI4_INTTERRUPTn source IRQ61) */
  EDMA1_CH8_IRQn               = 94,               /**< EDMA1_CH8 (HIFI4_INTTERRUPTn source IRQ62) */
  EDMA1_CH9_IRQn               = 95,               /**< EDMA1_CH9 (HIFI4_INTTERRUPTn source IRQ63) */
  EDMA1_CH10_IRQn              = 96,               /**< EDMA1_CH10 (HIFI4_INTTERRUPTn source IRQ64) */
  EDMA1_CH11_IRQn              = 97,               /**< EDMA1_CH11 (HIFI4_INTTERRUPTn source IRQ65) */
  EDMA1_CH12_IRQn              = 98,               /**< EDMA1_CH12 (HIFI4_INTTERRUPTn source IRQ66) */
  EDMA1_CH13_IRQn              = 99,               /**< EDMA1_CH13 (HIFI4_INTTERRUPTn source IRQ67) */
  EDMA1_CH14_IRQn              = 100,              /**< EDMA1_CH14 (HIFI4_INTTERRUPTn source IRQ68) */
  EDMA1_CH15_IRQn              = 101,              /**< EDMA1_CH15 (HIFI4_INTTERRUPTn source IRQ69) */
  GPIO0_CH0_IRQn               = 102,              /**< GPIO0_CH0 (HIFI4_INTTERRUPTn source IRQ70) */
  GPIO0_CH1_IRQn               = 103,              /**< GPIO0_CH1 (HIFI4_INTTERRUPTn source IRQ71) */
  GPIO1_CH0_IRQn               = 104,              /**< GPIO1_CH0 (HIFI4_INTTERRUPTn source IRQ72) */
  GPIO1_CH1_IRQn               = 105,              /**< GPIO1_CH1 (HIFI4_INTTERRUPTn source IRQ73) */
  GPIO2_CH0_IRQn               = 106,              /**< GPIO2_CH0 (HIFI4_INTTERRUPTn source IRQ74) */
  GPIO2_CH1_IRQn               = 107,              /**< GPIO2_CH1 (HIFI4_INTTERRUPTn source IRQ75) */
  GPIO3_CH0_IRQn               = 108,              /**< GPIO3_CH0 (HIFI4_INTTERRUPTn source IRQ76) */
  GPIO3_CH1_IRQn               = 109,              /**< GPIO3_CH1 (HIFI4_INTTERRUPTn source IRQ77) */
  GPIO4_CH0_IRQn               = 110,              /**< GPIO4_CH0 (HIFI4_INTTERRUPTn source IRQ78) */
  GPIO4_CH1_IRQn               = 111,              /**< GPIO4_CH1 (HIFI4_INTTERRUPTn source IRQ79) */
  GPIO5_CH0_IRQn               = 112,              /**< GPIO5_CH0 (HIFI4_INTTERRUPTn source IRQ80) */
  GPIO5_CH1_IRQn               = 113,              /**< GPIO5_CH1 (HIFI4_INTTERRUPTn source IRQ81) */
  GPIO6_CH0_IRQn               = 114,              /**< GPIO6_CH0 (HIFI4_INTTERRUPTn source IRQ82) */
  GPIO6_CH1_IRQn               = 115,              /**< GPIO6_CH1 (HIFI4_INTTERRUPTn source IRQ83) */
  GPIO7_CH0_IRQn               = 116,              /**< GPIO7_CH0 (HIFI4_INTTERRUPTn source IRQ84) */
  GPIO7_CH1_IRQn               = 117,              /**< GPIO7_CH1 (HIFI4_INTTERRUPTn source IRQ85) */
  PIN_INT0_IRQn                = 118,              /**< Pin interrupt0 (HIFI4_INTTERRUPTn source IRQ86) */
  PIN_INT1_IRQn                = 119,              /**< Pin interrupt1 (HIFI4_INTTERRUPTn source IRQ87) */
  PIN_INT2_IRQn                = 120,              /**< Pin interrupt2 (HIFI4_INTTERRUPTn source IRQ88) */
  PIN_INT3_IRQn                = 121,              /**< Pin interrupt3 (HIFI4_INTTERRUPTn source IRQ89) */
  PIN_INT4_IRQn                = 122,              /**< Pin interrupt4 (HIFI4_INTTERRUPTn source IRQ90) */
  PIN_INT5_IRQn                = 123,              /**< Pin interrupt5 (HIFI4_INTTERRUPTn source IRQ91) */
  PIN_INT6_IRQn                = 124,              /**< Pin interrupt6 (HIFI4_INTTERRUPTn source IRQ92) */
  PIN_INT7_IRQn                = 125,              /**< Pin interrupt7 (HIFI4_INTTERRUPTn source IRQ93) */
  SAI0_TX_RX_IRQn              = 126,              /**< SAI0_TX_RX (HIFI4_INTTERRUPTn source IRQ94) */
  SAI1_TX_RX_IRQn              = 127,              /**< SAI1_TX_RX (HIFI4_INTTERRUPTn source IRQ95) */
  SAI2_TX_RX_IRQn              = 128,              /**< SAI2_TX_RX (HIFI4_INTTERRUPTn source IRQ96) */
  XSPI0_IRQn                   = 129,              /**< XSPI0 (HIFI4_INTTERRUPTn source IRQ97) */
  XSPI1_IRQn                   = 130,              /**< XSPI1 (HIFI4_INTTERRUPTn source IRQ98) */
  XSPI2_IRQn                   = 131,              /**< XSPI2 (HIFI4_INTTERRUPTn source IRQ99) */
  JPGDECWRP_IRQn               = 132,              /**< JPGDECWRP (HIFI4_INTTERRUPTn source IRQ100) */
  PNGDEC_IRQn                  = 133,              /**< PNGDEC (HIFI4_INTTERRUPTn source IRQ101) */
  NPU_IRQn                     = 134,              /**< NPU (HIFI4_INTTERRUPTn source IRQ102 */
  PMC0_IRQn                    = 135               /**< PMC0 (HIFI4_INTTERRUPTn source IRQ103) */
} IRQn_Type;

/*!
 * @}
 */ /* end of group Interrupt_vector_numbers */


/* ----------------------------------------------------------------------------
   -- Mapping Information
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Mapping_Information Mapping Information
 * @{
 */

/** Mapping Information */
/*!
 * @addtogroup edma_request
 * @{
 */

/*******************************************************************************
 * Definitions
 ******************************************************************************/

/*!
 * @brief Structure for the DMA hardware request
 *
 * Defines the structure for the DMA hardware request collections.
 */
typedef enum _dma_request_source
{
    kDmaRequestMuxDisabled          = 0U,          /**< Unused DMA request 0 */
    kDmaRequestMuxMicfil            = 1U,          /**< MICFIL FIFO_request */
    kDmaRequestMuxXspi0Rx           = 2U,          /**< XSPI0 Receive */
    kDmaRequestMuxXspi0Tx           = 3U,          /**< XSPI0 Transmit */
    kDmaRequestMuxXspi1Rx           = 4U,          /**< XSPI1 Receive */
    kDmaRequestMuxXspi1Tx           = 5U,          /**< XSPI1 Transmit */
    kDmaRequestMuxXspi2Rx           = 6U,          /**< XSPI2 Receive */
    kDmaRequestMuxXspi2Tx           = 7U,          /**< XSPI2 Transmit */
    kDmaRequestMuxPinInt0           = 8U,          /**< PINT0 INT0 */
    kDmaRequestMuxPinInt1           = 9U,          /**< PINT0 INT1 */
    kDmaRequestMuxPinInt2           = 10U,         /**< PINT0 INT2 */
    kDmaRequestMuxPinInt3           = 11U,         /**< PINT0 INT3 */
    kDmaRequestMuxPinInt4           = 12U,         /**< PINT0 INT4 */
    kDmaRequestMuxPinInt5           = 13U,         /**< PINT0 INT5 */
    kDmaRequestMuxPinInt6           = 14U,         /**< PINT0 INT6 */
    kDmaRequestMuxPinInt7           = 15U,         /**< PINT0 INT7 */
    kDmaRequestMuxCtimer0M0         = 16U,         /**< CTIMER0 Match channel 0 request */
    kDmaRequestMuxCtimer0M1         = 17U,         /**< CTIMER0 Match channel 1 request */
    kDmaRequestMuxCtimer1M0         = 18U,         /**< CTIMER1 Match channel 0 request */
    kDmaRequestMuxCtimer1M1         = 19U,         /**< CTIMER1 Match channel 1 request */
    kDmaRequestMuxCtimer2M0         = 20U,         /**< CTIMER2 Match channel 0 request */
    kDmaRequestMuxCtimer2M1         = 21U,         /**< CTIMER2 Match channel 1 request */
    kDmaRequestMuxCtimer3M0         = 22U,         /**< CTIMER3 Match channel 0 request */
    kDmaRequestMuxCtimer3M1         = 23U,         /**< CTIMER3 Match channel 1 request */
    kDmaRequestMuxCtimer4M0         = 24U,         /**< CTIMER4 Match channel 0 request */
    kDmaRequestMuxCtimer4M1         = 25U,         /**< CTIMER4 Match channel 1 request */
    kDmaRequestMuxSct0Dma0          = 26U,         /**< SCT0 DMA0 */
    kDmaRequestMuxSct0Dma1          = 27U,         /**< SCT0 DMA1 */
    kDmaRequestMuxAdc0FifoARequest  = 28U,         /**< ADC0 FIFO A request */
    kDmaRequestMuxAdc0FifoBRequest  = 29U,         /**< ADC0 FIFO B request */
    kDmaRequestMuxSdAdcFifo0Request = 30U,         /**< SDADC0 FIFO 0 request */
    kDmaRequestMuxSdAdcFifo1Request = 31U,         /**< SDADC0 FIFO 1 request */
    kDmaRequestMuxSdAdcFifo2Request = 32U,         /**< SDADC0 FIFO 2 request */
    kDmaRequestMuxSdAdcFifo3Request = 33U,         /**< SDADC0 FIFO 3 request */
    kDmaRequestMuxCmpDmaRequest     = 34U,         /**< CMP DMA request */
    kDmaRequestMuxItrc0TmprOut0     = 35U,         /**< ITRC0 TMPR_OUT0 */
    kDmaRequestMuxItrc0TmprOut1     = 36U,         /**< ITRC0 TMPR_OUT1 */
    kDmaRequestMuxFlexIO0ShiftRegister0Request = 37U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */
    kDmaRequestMuxFlexIO0ShiftRegister1Request = 38U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */
    kDmaRequestMuxFlexIO0ShiftRegister2Request = 39U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */
    kDmaRequestMuxFlexIO0ShiftRegister3Request = 40U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */
    kDmaRequestMuxFlexIO0ShiftRegister4Request = 41U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */
    kDmaRequestMuxFlexIO0ShiftRegister5Request = 42U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */
    kDmaRequestMuxFlexIO0ShiftRegister6Request = 43U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */
    kDmaRequestMuxFlexIO0ShiftRegister7Request = 44U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */
    kDmaRequestMuxLpFlexcomm0Rx     = 45U,         /**< LP_FLEXCOMM0 Receive request */
    kDmaRequestMuxLpFlexcomm0Tx     = 46U,         /**< LP_FLEXCOMM0 Transmit request */
    kDmaRequestMuxLpFlexcomm1Rx     = 47U,         /**< LP_FLEXCOMM1 Receive request */
    kDmaRequestMuxLpFlexcomm1Tx     = 48U,         /**< LP_FLEXCOMM1 Transmit request */
    kDmaRequestMuxLpFlexcomm2Rx     = 49U,         /**< LP_FLEXCOMM2 Receive request */
    kDmaRequestMuxLpFlexcomm2Tx     = 50U,         /**< LP_FLEXCOMM2 Transmit request */
    kDmaRequestMuxLpFlexcomm3Rx     = 51U,         /**< LP_FLEXCOMM3 Receive request */
    kDmaRequestMuxLpFlexcomm3Tx     = 52U,         /**< LP_FLEXCOMM3 Transmit request */
    kDmaRequestMuxLpFlexcomm4Rx     = 53U,         /**< LP_FLEXCOMM4 Receive request */
    kDmaRequestMuxLpFlexcomm4Tx     = 54U,         /**< LP_FLEXCOMM4 Transmit request */
    kDmaRequestMuxLpFlexcomm5Rx     = 55U,         /**< LP_FLEXCOMM5 Receive request */
    kDmaRequestMuxLpFlexcomm5Tx     = 56U,         /**< LP_FLEXCOMM5 Transmit request */
    kDmaRequestMuxLpFlexcomm6Rx     = 57U,         /**< LP_FLEXCOMM6 Receive request */
    kDmaRequestMuxLpFlexcomm6Tx     = 58U,         /**< LP_FLEXCOMM6 Transmit request */
    kDmaRequestMuxLpFlexcomm7Rx     = 59U,         /**< LP_FLEXCOMM7 Receive request */
    kDmaRequestMuxLpFlexcomm7Tx     = 60U,         /**< LP_FLEXCOMM7 Transmit request */
    kDmaRequestMuxLpFlexcomm8Rx     = 61U,         /**< LP_FLEXCOMM8 Receive request */
    kDmaRequestMuxLpFlexcomm8Tx     = 62U,         /**< LP_FLEXCOMM8 Transmit request */
    kDmaRequestMuxLpFlexcomm9Rx     = 63U,         /**< LP_FLEXCOMM9 Receive request */
    kDmaRequestMuxLpFlexcomm9Tx     = 64U,         /**< LP_FLEXCOMM9 Transmit request */
    kDmaRequestMuxLpFlexcomm10Rx    = 65U,         /**< LP_FLEXCOMM10 Receive request */
    kDmaRequestMuxLpFlexcomm10Tx    = 66U,         /**< LP_FLEXCOMM10 Transmit request */
    kDmaRequestMuxLpFlexcomm11Rx    = 67U,         /**< LP_FLEXCOMM11 Receive request */
    kDmaRequestMuxLpFlexcomm11Tx    = 68U,         /**< LP_FLEXCOMM11 Transmit request */
    kDmaRequestMuxLpFlexcomm12Rx    = 69U,         /**< LP_FLEXCOMM12 Receive request */
    kDmaRequestMuxLpFlexcomm12Tx    = 70U,         /**< LP_FLEXCOMM12 Transmit request */
    kDmaRequestMuxLpFlexcomm13Rx    = 71U,         /**< LP_FLEXCOMM13 Receive request */
    kDmaRequestMuxLpFlexcomm13Tx    = 72U,         /**< LP_FLEXCOMM13 Transmit request */
    kDmaRequestMuxLpspi14Rx         = 73U,         /**< LPSPI14 Receive request */
    kDmaRequestMuxLpspi14Tx         = 74U,         /**< LPSPI14 Transmit request */
    kDmaRequestMuxLpspi16Rx         = 75U,         /**< LPSPI16 Receive request */
    kDmaRequestMuxLpspi16Tx         = 76U,         /**< LPSPI16 Transmit request */
    kDmaRequestMuxI3c0Tx            = 77U,         /**< I3C0 Transmit request */
    kDmaRequestMuxI3c0Rx            = 78U,         /**< I3C0 Receive request */
    kDmaRequestMuxI3c1Tx            = 79U,         /**< I3C1 Transmit request */
    kDmaRequestMuxI3c1Rx            = 80U,         /**< I3C1 Receive request */
    kDmaRequestMuxSai0Rx            = 81U,         /**< SAI0 Receive request */
    kDmaRequestMuxSai0Tx            = 82U,         /**< SAI0 Transmit request */
    kDmaRequestMuxSai1Rx            = 83U,         /**< SAI1 Receive request */
    kDmaRequestMuxSai1Tx            = 84U,         /**< SAI1 Transmit request */
    kDmaRequestMuxSai2Rx            = 85U,         /**< SAI2 Receive request */
    kDmaRequestMuxSai2Tx            = 86U,         /**< SAI2 Transmit request */
    kDmaRequestMuxGpio0PinEventRequest0 = 87U,     /**< GPIO0 Pin event request 0 */
    kDmaRequestMuxGpio0PinEventRequest1 = 88U,     /**< GPIO0 Pin event request 1 */
    kDmaRequestMuxGpio1PinEventRequest0 = 89U,     /**< GPIO1 Pin event request 0 */
    kDmaRequestMuxGpio1PinEventRequest1 = 90U,     /**< GPIO1 Pin event request 1 */
    kDmaRequestMuxGpio2PinEventRequest0 = 91U,     /**< GPIO2 Pin event request 0 */
    kDmaRequestMuxGpio2PinEventRequest1 = 92U,     /**< GPIO2 Pin event request 1 */
    kDmaRequestMuxGpio3PinEventRequest0 = 93U,     /**< GPIO3 Pin event request 0 */
    kDmaRequestMuxGpio3PinEventRequest1 = 94U,     /**< GPIO3 Pin event request 1 */
    kDmaRequestMuxGpio4PinEventRequest0 = 95U,     /**< GPIO4 Pin event request 0 */
    kDmaRequestMuxGpio4PinEventRequest1 = 96U,     /**< GPIO4 Pin event request 1 */
    kDmaRequestMuxGpio5PinEventRequest0 = 97U,     /**< GPIO5 Pin event request 0 */
    kDmaRequestMuxGpio5PinEventRequest1 = 98U,     /**< GPIO5 Pin event request 1 */
    kDmaRequestMuxGpio6PinEventRequest0 = 99U,     /**< GPIO6 Pin event request 0 */
    kDmaRequestMuxGpio6PinEventRequest1 = 100U,    /**< GPIO6 Pin event request 1 */
    kDmaRequestMuxGpio7PinEventRequest0 = 101U,    /**< GPIO7 Pin event request 0 */
    kDmaRequestMuxGpio7PinEventRequest1 = 102U,    /**< GPIO7 Pin event request 1 */
    kDmaRequestMuxLpi2c15Rx         = 103U,        /**< LPI2C15 receive request */
    kDmaRequestMuxLpi2c15Tx         = 104U,        /**< LPI2C15 transmit request */
} dma_request_source_t;

/* @} */


/*!
 * @}
 */ /* end of group Mapping_Information */


/* ----------------------------------------------------------------------------
   -- Device Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 * @{
 */


/*
** Start of section using anonymous unions
*/

#if defined(__XTENSA__)
  /* anonymous unions are enabled by default */
#else
  #error Not supported compiler type
#endif

/* ----------------------------------------------------------------------------
   -- ADC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
 * @{
 */

/** ADC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CTRL;                              /**< Control, offset: 0x10 */
  __IO uint32_t STAT;                              /**< Status, offset: 0x14 */
  __IO uint32_t IE;                                /**< Interrupt Enable, offset: 0x18 */
  __IO uint32_t DE;                                /**< DMA Enable, offset: 0x1C */
  __IO uint32_t CFG;                               /**< Configuration, offset: 0x20 */
  __IO uint32_t PAUSE;                             /**< Pause, offset: 0x24 */
       uint8_t RESERVED_1[12];
  __IO uint32_t SWTRIG;                            /**< Software Trigger, offset: 0x34 */
  __IO uint32_t TSTAT;                             /**< Trigger Status, offset: 0x38 */
       uint8_t RESERVED_2[4];
  __IO uint32_t OFSTRIM16;                         /**< Offset Trim 16 Bits, offset: 0x40 */
  __IO uint32_t OFSTRIM12;                         /**< Offset Trim 12 Bits, offset: 0x44 */
       uint8_t RESERVED_3[88];
  __IO uint32_t TCTRL[2];                          /**< Trigger Control, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_4[56];
  __IO uint32_t FCTRL[2];                          /**< FIFO Control, array offset: 0xE0, array step: 0x4 */
       uint8_t RESERVED_5[8];
  __I  uint32_t GCC[2];                            /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
  __IO uint32_t GCR[2];                            /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
  struct {                                         /* offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDL;                              /**< Command Low Buffer, array offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDH;                              /**< Command High Buffer, array offset: 0x104, array step: 0x8 */
  } CMD[15];
       uint8_t RESERVED_6[136];
  __IO uint32_t CV[4];                             /**< Compare Value, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_7[240];
  __I  uint32_t RESFIFO[2];                        /**< Data Result FIFO, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_8[248];
  __IO uint32_t CAL_GAR[33];                       /**< Calibration General A-Side, array offset: 0x400, array step: 0x4 */
       uint8_t RESERVED_9[124];
  __IO uint32_t CAL_GBR[33];                       /**< Calibration General B-Side, array offset: 0x500, array step: 0x4 */
       uint8_t RESERVED_10[2676];
  __IO uint32_t CFG2;                              /**< Configuration 2, offset: 0xFF8 */
} ADC_Type;

/* ----------------------------------------------------------------------------
   -- ADC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Register_Masks ADC Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define ADC_VERID_RES_MASK                       (0x1U)
#define ADC_VERID_RES_SHIFT                      (0U)
/*! RES - Resolution
 *  0b0..Up to 13-bit differential or 12-bit single-ended resolution
 *  0b1..Up to 16-bit differential or 16-bit single-ended resolution supported
 */
#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)

#define ADC_VERID_DIFFEN_MASK                    (0x2U)
#define ADC_VERID_DIFFEN_SHIFT                   (1U)
/*! DIFFEN - Differential Supported
 *  0b0..Not supported
 *  0b1..Supported
 */
#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)

#define ADC_VERID_MVI_MASK                       (0x8U)
#define ADC_VERID_MVI_SHIFT                      (3U)
/*! MVI - Multi Vref Implemented
 *  0b0..Single VREFH input supported
 *  0b1..Multiple VREFH inputs supported
 */
#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)

#define ADC_VERID_CSW_MASK                       (0x70U)
#define ADC_VERID_CSW_SHIFT                      (4U)
/*! CSW - Channel Scale Width
 *  0b000..Not supported (the CSCALE field not implemented)
 *  0b001..1-bit CSCALE supported
 *  0b110..6-bit CSCALE supported
 */
#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)

#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
 *  0b0..Range control not required
 *  0b1..Range control required
 */
#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)

#define ADC_VERID_IADCKI_MASK                    (0x200U)
#define ADC_VERID_IADCKI_SHIFT                   (9U)
/*! IADCKI - Internal ADC Clock Implemented
 *  0b0..Not implemented
 *  0b1..Implemented
 */
#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)

#define ADC_VERID_CALOFSI_MASK                   (0x400U)
#define ADC_VERID_CALOFSI_SHIFT                  (10U)
/*! CALOFSI - Calibration Function Implemented
 *  0b0..Not implemented
 *  0b1..Implemented
 */
#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)

#define ADC_VERID_NUM_SEC_MASK                   (0x800U)
#define ADC_VERID_NUM_SEC_SHIFT                  (11U)
/*! NUM_SEC - Number of Single-Ended Outputs Supported
 *  0b0..One conversion
 *  0b1..Two conversions
 */
#define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)

#define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
#define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
/*! NUM_FIFO - Number of FIFOs
 *  0b000..N/A
 *  0b001..One
 *  0b010..Two
 *  0b011..Three
 *  0b100..Four
 */
#define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)

#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
#define ADC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)

#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
#define ADC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
/*! TRIG_NUM - Trigger Number */
#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)

#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
/*! FIFOSIZE - Result FIFO Depth
 *  0b00000001..2
 *  0b00000100..4
 *  0b00001000..8
 *  0b00010000..16
 *  0b00100000..32
 *  0b01000000..64
 */
#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)

#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
/*! CV_NUM - Compare Value Number */
#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)

#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
/*! CMD_NUM - Command Buffer Number */
#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
/*! @} */

/*! @name CTRL - Control */
/*! @{ */

#define ADC_CTRL_ADCEN_MASK                      (0x1U)
#define ADC_CTRL_ADCEN_SHIFT                     (0U)
/*! ADCEN - ADC Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)

#define ADC_CTRL_RST_MASK                        (0x2U)
#define ADC_CTRL_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..Do not reset ADC logic
 *  0b1..Reset ADC logic
 */
#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)

#define ADC_CTRL_DOZEN_MASK                      (0x4U)
#define ADC_CTRL_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Enable
 *  0b0..ADC conversions enabled in Low-Power mode
 *  0b1..ADC conversions disabled in Low-Power mode
 */
#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)

#define ADC_CTRL_CAL_REQ_MASK                    (0x8U)
#define ADC_CTRL_CAL_REQ_SHIFT                   (3U)
/*! CAL_REQ - Auto-Calibration Request
 *  0b0..Request for hardware calibration not made
 *  0b1..Request for hardware calibration made
 */
#define ADC_CTRL_CAL_REQ(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)

#define ADC_CTRL_CALOFS_MASK                     (0x10U)
#define ADC_CTRL_CALOFS_SHIFT                    (4U)
/*! CALOFS - Offset Calibration Request
 *  0b0..Disable calibration function
 *  0b1..Request for offset calibration function
 */
#define ADC_CTRL_CALOFS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)

#define ADC_CTRL_CALOFSMODE_MASK                 (0x20U)
#define ADC_CTRL_CALOFSMODE_SHIFT                (5U)
/*! CALOFSMODE - Configure Mode for Offset Calibration Function
 *  0b0..12-bit mode
 *  0b1..16-bit mode
 */
#define ADC_CTRL_CALOFSMODE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFSMODE_SHIFT)) & ADC_CTRL_CALOFSMODE_MASK)

#define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
#define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
/*! RSTFIFO0 - Reset FIFO 0
 *  0b0..No effect
 *  0b1..FIFO 0 is reset
 */
#define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)

#define ADC_CTRL_RSTFIFO1_MASK                   (0x200U)
#define ADC_CTRL_RSTFIFO1_SHIFT                  (9U)
/*! RSTFIFO1 - Reset FIFO 1
 *  0b0..No effect
 *  0b1..FIFO 1 is reset
 */
#define ADC_CTRL_RSTFIFO1(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)

#define ADC_CTRL_CAL_AVGS_MASK                   (0xF0000U)
#define ADC_CTRL_CAL_AVGS_SHIFT                  (16U)
/*! CAL_AVGS - Auto-Calibration Averages
 *  0b0000..Single conversion
 *  0b0001..2
 *  0b0010..4
 *  0b0011..8
 *  0b0100..16
 *  0b0101..32
 *  0b0110..64
 *  0b0111..128
 *  0b1000..256
 *  0b1001..512
 *  0b1010..1024
 */
#define ADC_CTRL_CAL_AVGS(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
/*! @} */

/*! @name STAT - Status */
/*! @{ */

#define ADC_STAT_RDY0_MASK                       (0x1U)
#define ADC_STAT_RDY0_SHIFT                      (0U)
/*! RDY0 - Result FIFO 0 Ready Flag
 *  0b0..Below watermark level
 *  0b1..Above watermark level
 */
#define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)

#define ADC_STAT_FOF0_MASK                       (0x2U)
#define ADC_STAT_FOF0_SHIFT                      (1U)
/*! FOF0 - Result FIFO 0 Overflow Flag
 *  0b0..No result FIFO 0 overflow occurred
 *  0b1..At least one result FIFO 0 overflow occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)

#define ADC_STAT_RDY1_MASK                       (0x4U)
#define ADC_STAT_RDY1_SHIFT                      (2U)
/*! RDY1 - Result FIFO1 Ready Flag
 *  0b0..Below watermark level
 *  0b1..Above watermark level
 */
#define ADC_STAT_RDY1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)

#define ADC_STAT_FOF1_MASK                       (0x8U)
#define ADC_STAT_FOF1_SHIFT                      (3U)
/*! FOF1 - Result FIFO1 Overflow Flag
 *  0b0..No result FIFO1 overflow occurred
 *  0b1..At least one result FIFO1 overflow occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define ADC_STAT_FOF1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)

#define ADC_STAT_TEXC_INT_MASK                   (0x100U)
#define ADC_STAT_TEXC_INT_SHIFT                  (8U)
/*! TEXC_INT - Interrupt Flag for High Priority Trigger Exception
 *  0b0..No trigger exceptions occurred
 *  0b1..Trigger exceptions occurred; acknowledgment is pending
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)

#define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
#define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
/*! TCOMP_INT - Interrupt Flag for Trigger Completion
 *  0b0..Either IE[TCOMP_IE] is 0 or no trigger sequences are complete
 *  0b1..Trigger sequence completed; all data stored in the associated FIFO
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)

#define ADC_STAT_CAL_RDY_MASK                    (0x400U)
#define ADC_STAT_CAL_RDY_SHIFT                   (10U)
/*! CAL_RDY - Calibration Ready
 *  0b0..Calibration is incomplete or not ready
 *  0b1..Calibration complete
 */
#define ADC_STAT_CAL_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)

#define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
#define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
/*! ADC_ACTIVE - ADC Active
 *  0b0..Idle
 *  0b1..Processing a conversion
 */
#define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)

#define ADC_STAT_TRGACT_MASK                     (0x10000U)
#define ADC_STAT_TRGACT_SHIFT                    (16U)
/*! TRGACT - Trigger Active
 *  0b0..Trigger 0
 *  0b1..Trigger 1
 */
#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)

#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
#define ADC_STAT_CMDACT_SHIFT                    (24U)
/*! CMDACT - Command Active
 *  0b0000..No command
 *  0b0001..Command 1
 *  0b0010..Command 2
 *  0b0011-0b1111..Associated command number
 */
#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
/*! @} */

/*! @name IE - Interrupt Enable */
/*! @{ */

#define ADC_IE_FWMIE0_MASK                       (0x1U)
#define ADC_IE_FWMIE0_SHIFT                      (0U)
/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)

#define ADC_IE_FOFIE0_MASK                       (0x2U)
#define ADC_IE_FOFIE0_SHIFT                      (1U)
/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)

#define ADC_IE_FWMIE1_MASK                       (0x4U)
#define ADC_IE_FWMIE1_SHIFT                      (2U)
/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_IE_FWMIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)

#define ADC_IE_FOFIE1_MASK                       (0x8U)
#define ADC_IE_FOFIE1_SHIFT                      (3U)
/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_IE_FOFIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)

#define ADC_IE_TEXC_IE_MASK                      (0x100U)
#define ADC_IE_TEXC_IE_SHIFT                     (8U)
/*! TEXC_IE - Trigger Exception Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)

#define ADC_IE_TCOMP_IE_MASK                     (0x30000U)
#define ADC_IE_TCOMP_IE_SHIFT                    (16U)
/*! TCOMP_IE - Trigger Completion Interrupt Enable
 *  0b00..Disable
 *  0b01..Enable for trigger source 0 only
 *  0b10..Enable for trigger source 1 only
 *  0b11..Enable trigger 0 and trigger 1 completion interrupts for both trigger sources
 */
#define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
/*! @} */

/*! @name DE - DMA Enable */
/*! @{ */

#define ADC_DE_FWMDE0_MASK                       (0x1U)
#define ADC_DE_FWMDE0_SHIFT                      (0U)
/*! FWMDE0 - FIFO 0 Watermark DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)

#define ADC_DE_FWMDE1_MASK                       (0x2U)
#define ADC_DE_FWMDE1_SHIFT                      (1U)
/*! FWMDE1 - FIFO1 Watermark DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_DE_FWMDE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
/*! @} */

/*! @name CFG - Configuration */
/*! @{ */

#define ADC_CFG_TPRICTRL_MASK                    (0x3U)
#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
/*! TPRICTRL - ADC Trigger Priority Control
 *  0b00..Abort the current conversion and start the new command specified by the trigger
 *  0b01..Stop the current command after completing the current conversion
 *  0b10..Complete the current command before servicing the higher-priority trigger
 *  0b11..Reserved
 */
#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)

#define ADC_CFG_REFSEL_MASK                      (0xC0U)
#define ADC_CFG_REFSEL_SHIFT                     (6U)
/*! REFSEL - Voltage Reference Selection
 *  0b00..Option 1 (default)
 *  0b01..Option 2
 *  0b10..Option 3
 *  0b11..Reserved
 */
#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)

#define ADC_CFG_TRES_MASK                        (0x100U)
#define ADC_CFG_TRES_SHIFT                       (8U)
/*! TRES - Trigger Resume Enable
 *  0b0..Do not resume or restart automatically
 *  0b1..Resume or restart automatically
 */
#define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)

#define ADC_CFG_TCMDRES_MASK                     (0x200U)
#define ADC_CFG_TCMDRES_SHIFT                    (9U)
/*! TCMDRES - Trigger Command Resume
 *  0b0..Restart automatically
 *  0b1..Resume command execution
 */
#define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)

#define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
#define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
/*! HPT_EXDI - High Priority Trigger Exception Disable
 *  0b0..Enable
 *  0b1..Disable
 */
#define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)

#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
#define ADC_CFG_PUDLY_SHIFT                      (16U)
/*! PUDLY - Power Up Delay */
#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)

#define ADC_CFG_PWREN_MASK                       (0x10000000U)
#define ADC_CFG_PWREN_SHIFT                      (28U)
/*! PWREN - ADC Analog Pre-Enable
 *  0b0..Not pre-enabled
 *  0b1..Pre-enabled and ready to execute conversions
 */
#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
/*! @} */

/*! @name PAUSE - Pause */
/*! @{ */

#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
/*! PAUSEDLY - Pause Delay */
#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)

#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
/*! PAUSEEN - Pause Option Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
/*! @} */

/*! @name SWTRIG - Software Trigger */
/*! @{ */

#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
/*! SWT0 - Software Trigger 0 Event
 *  0b0..Not generated
 *  0b1..Generated
 */
#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)

#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
/*! SWT1 - Software Trigger 1 Event
 *  0b0..Not generated
 *  0b1..Generated
 */
#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
/*! @} */

/*! @name TSTAT - Trigger Status */
/*! @{ */

#define ADC_TSTAT_TEXC_NUM_MASK                  (0x3U)
#define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
/*! TEXC_NUM - Trigger Exception Number
 *  0b00..No trigger is interrupted (or CFG[TRES] = 1)
 *  0b01..Trigger 0 is interrupted
 *  0b10..Trigger 1 is interrupted
 *  0b11..Trigger 0 and trigger 1 sequences are interrupted
 */
#define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)

#define ADC_TSTAT_TCOMP_FLAG_MASK                (0x30000U)
#define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
/*! TCOMP_FLAG - Trigger Completion Flag
 *  0b00..No trigger is complete (trigger completion interrupts are disabled)
 *  0b01..Trigger 0 is complete (trigger 0 has enabled completion interrupts)
 *  0b10..Trigger 1 is complete (trigger 1 has enabled completion interrupts)
 *  0b11..Trigger 0 and trigger 1 sequences are complete (both triggers have enabled completion interrupts)
 */
#define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
/*! @} */

/*! @name OFSTRIM16 - Offset Trim 16 Bits */
/*! @{ */

#define ADC_OFSTRIM16_OFSTRIM_A_MASK             (0x3FFU)
#define ADC_OFSTRIM16_OFSTRIM_A_SHIFT            (0U)
/*! OFSTRIM_A - Trim for Offset in A-side Converter for 16-bit Conversions */
#define ADC_OFSTRIM16_OFSTRIM_A(x)               (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM16_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM16_OFSTRIM_A_MASK)

#define ADC_OFSTRIM16_OFSTRIM_B_MASK             (0x3FF0000U)
#define ADC_OFSTRIM16_OFSTRIM_B_SHIFT            (16U)
/*! OFSTRIM_B - Trim for Offset in B-side Converter for 16-bit Conversions */
#define ADC_OFSTRIM16_OFSTRIM_B(x)               (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM16_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM16_OFSTRIM_B_MASK)
/*! @} */

/*! @name OFSTRIM12 - Offset Trim 12 Bits */
/*! @{ */

#define ADC_OFSTRIM12_OFSTRIM_A_MASK             (0x3FFU)
#define ADC_OFSTRIM12_OFSTRIM_A_SHIFT            (0U)
/*! OFSTRIM_A - Trim for Offset in A-side Converter for 12-bit Conversions */
#define ADC_OFSTRIM12_OFSTRIM_A(x)               (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM12_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM12_OFSTRIM_A_MASK)

#define ADC_OFSTRIM12_OFSTRIM_B_MASK             (0x3FF0000U)
#define ADC_OFSTRIM12_OFSTRIM_B_SHIFT            (16U)
/*! OFSTRIM_B - Trim for Offset in B-side Converter for 12-bit Conversions */
#define ADC_OFSTRIM12_OFSTRIM_B(x)               (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM12_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM12_OFSTRIM_B_MASK)
/*! @} */

/*! @name TCTRL - Trigger Control */
/*! @{ */

#define ADC_TCTRL_HTEN_MASK                      (0x1U)
#define ADC_TCTRL_HTEN_SHIFT                     (0U)
/*! HTEN - Trigger Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)

#define ADC_TCTRL_FIFO_SEL_A_MASK                (0x2U)
#define ADC_TCTRL_FIFO_SEL_A_SHIFT               (1U)
/*! FIFO_SEL_A - SAR Result Destination for Channel A
 *  0b0..Result written to FIFO 0
 *  0b1..Result written to FIFO 1
 */
#define ADC_TCTRL_FIFO_SEL_A(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)

#define ADC_TCTRL_FIFO_SEL_B_MASK                (0x4U)
#define ADC_TCTRL_FIFO_SEL_B_SHIFT               (2U)
/*! FIFO_SEL_B - SAR Result Destination for Channel B
 *  0b0..Result written to FIFO 0
 *  0b1..Result written to FIFO 1
 */
#define ADC_TCTRL_FIFO_SEL_B(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)

#define ADC_TCTRL_TPRI_MASK                      (0x100U)
#define ADC_TCTRL_TPRI_SHIFT                     (8U)
/*! TPRI - Trigger Priority Setting
 *  0b0..Set to highest priority, level 1
 *  0b1..Set to lower priority, level 2
 */
#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)

#define ADC_TCTRL_RSYNC_MASK                     (0x8000U)
#define ADC_TCTRL_RSYNC_SHIFT                    (15U)
/*! RSYNC - Trigger Resynchronization */
#define ADC_TCTRL_RSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)

#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
#define ADC_TCTRL_TDLY_SHIFT                     (16U)
/*! TDLY - Trigger Delay Select */
#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)

#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
#define ADC_TCTRL_TCMD_SHIFT                     (24U)
/*! TCMD - Trigger Command Select
 *  0b0000..Not a valid selection from the command buffer (trigger event is ignored)
 *  0b0001..CMD1 is executed
 *  0b0010-0b1110..Corresponding CMD is executed
 *  0b1111..CMD15 is executed
 */
#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
/*! @} */

/* The count of ADC_TCTRL */
#define ADC_TCTRL_COUNT                          (2U)

/*! @name FCTRL - FIFO Control */
/*! @{ */

#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
/*! FCOUNT - Result FIFO Counter */
#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)

#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
/*! FWMARK - Watermark Level Selection */
#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
/*! @} */

/* The count of ADC_FCTRL */
#define ADC_FCTRL_COUNT                          (2U)

/*! @name GCC - Gain Calibration Control */
/*! @{ */

#define ADC_GCC_GAIN_CAL_MASK                    (0xFFFFU)
#define ADC_GCC_GAIN_CAL_SHIFT                   (0U)
/*! GAIN_CAL - Gain Calibration Value */
#define ADC_GCC_GAIN_CAL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)

#define ADC_GCC_RDY_MASK                         (0x1000000U)
#define ADC_GCC_RDY_SHIFT                        (24U)
/*! RDY - Hardware Calculated GAIN_CAL Value Ready
 *  0b0..Invalid
 *  0b1..Valid
 */
#define ADC_GCC_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
/*! @} */

/* The count of ADC_GCC */
#define ADC_GCC_COUNT                            (2U)

/*! @name GCR - Gain Calculation Result */
/*! @{ */

#define ADC_GCR_GCALR_MASK                       (0x1FFFFU)
#define ADC_GCR_GCALR_SHIFT                      (0U)
/*! GCALR - Gain Calculation Result */
#define ADC_GCR_GCALR(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)

#define ADC_GCR_RDY_MASK                         (0x1000000U)
#define ADC_GCR_RDY_SHIFT                        (24U)
/*! RDY - Gain Calculation Ready
 *  0b0..Invalid
 *  0b1..Valid
 */
#define ADC_GCR_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
/*! @} */

/* The count of ADC_GCR */
#define ADC_GCR_COUNT                            (2U)

/*! @name CMDL - Command Low Buffer */
/*! @{ */

#define ADC_CMDL_ADCH_MASK                       (0x1FU)
#define ADC_CMDL_ADCH_SHIFT                      (0U)
/*! ADCH - Input Channel Select
 *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair
 *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair
 *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair
 *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair
 *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair
 *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair
 *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair
 */
#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)

#define ADC_CMDL_CTYPE_MASK                      (0x60U)
#define ADC_CMDL_CTYPE_SHIFT                     (5U)
/*! CTYPE - Conversion Type
 *  0b00..Single-ended mode (only the A-side channel is converted)
 *  0b01..Single-ended mode (only the B-side channel is converted)
 *  0b10..Differential mode (A-B)
 *  0b11..Dual-Single-Ended mode (both A-side and B-side channels are converted independently)
 */
#define ADC_CMDL_CTYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)

#define ADC_CMDL_MODE_MASK                       (0x80U)
#define ADC_CMDL_MODE_SHIFT                      (7U)
/*! MODE - Select Resolution of Conversions
 *  0b0..Standard resolution
 *  0b1..High resolution
 */
#define ADC_CMDL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)

#define ADC_CMDL_ALTB_ADCH_MASK                  (0x1F0000U)
#define ADC_CMDL_ALTB_ADCH_SHIFT                 (16U)
/*! ALTB_ADCH - Alternate Channel B Input Channel Select
 *  0b00000..Select CH0B
 *  0b00001..Select CH1B
 *  0b00010..Select CH2B
 *  0b00011..Select CH3B
 *  0b00100-0b11101..Select the corresponding channel CHnB
 *  0b11110..Select CH30B
 *  0b11111..Select CH31B
 */
#define ADC_CMDL_ALTB_ADCH(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK)

#define ADC_CMDL_ALTBEN_MASK                     (0x200000U)
#define ADC_CMDL_ALTBEN_SHIFT                    (21U)
/*! ALTBEN - Alternate Channel B Select Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_CMDL_ALTBEN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK)
/*! @} */

/* The count of ADC_CMDL */
#define ADC_CMDL_COUNT                           (15U)

/*! @name CMDH - Command High Buffer */
/*! @{ */

#define ADC_CMDH_CMPEN_MASK                      (0x3U)
#define ADC_CMDH_CMPEN_SHIFT                     (0U)
/*! CMPEN - Compare Function Enable
 *  0b00..Disable
 *  0b01..Reserved
 *  0b10..Enable; store on true
 *  0b11..Enable; repeat channel acquisition (sample, convert, and compare) until true
 */
#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)

#define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
#define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
/*! WAIT_TRIG - Wait for Trigger Assertion Before Execution
 *  0b0..Execute automatically
 *  0b1..Receive trigger before execution
 */
#define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)

#define ADC_CMDH_LWI_MASK                        (0x80U)
#define ADC_CMDH_LWI_SHIFT                       (7U)
/*! LWI - Loop with Increment
 *  0b0..Disable
 *  0b1..Enable
 */
#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)

#define ADC_CMDH_STS_MASK                        (0x700U)
#define ADC_CMDH_STS_SHIFT                       (8U)
/*! STS - Sample Time Select
 *  0b000..Minimum sample time of 3.5 ADCK cycles
 *  0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles
 *  0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles
 *  0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles
 *  0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles
 *  0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles
 *  0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles
 *  0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles
 */
#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)

#define ADC_CMDH_AVGS_MASK                       (0xF000U)
#define ADC_CMDH_AVGS_SHIFT                      (12U)
/*! AVGS - Hardware Average Select
 *  0b0000..Single conversion
 *  0b0001..2 conversions
 *  0b0010..4 conversions
 *  0b0011..8 conversions
 *  0b0100..16 conversions
 *  0b0101..32 conversions
 *  0b0110..64 conversions
 *  0b0111..128 conversions
 *  0b1000..256 conversions
 *  0b1001..512 conversions
 *  0b1010..1024 conversions
 */
#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)

#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
#define ADC_CMDH_LOOP_SHIFT                      (16U)
/*! LOOP - Loop Count Select
 *  0b0000..Looping not enabled; command executes one time
 *  0b0001..Loop one time; command executes two times
 *  0b0010..Loop two times; command executes three times
 *  0b0011-0b1110..Loop corresponding number of times; command executes LOOP + 1 times
 *  0b1111..Loop 15 times; command executes 16 times
 */
#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)

#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
#define ADC_CMDH_NEXT_SHIFT                      (24U)
/*! NEXT - Next Command Select
 *  0b0000..No next command defined
 *  0b0001..CMD1 command buffer register
 *  0b0010-0b1110..Corresponding CMD command buffer register
 *  0b1111..CMD15 command buffer register
 */
#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
/*! @} */

/* The count of ADC_CMDH */
#define ADC_CMDH_COUNT                           (15U)

/*! @name CV - Compare Value */
/*! @{ */

#define ADC_CV_CVL_MASK                          (0xFFFFU)
#define ADC_CV_CVL_SHIFT                         (0U)
/*! CVL - Compare Value Low */
#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)

#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
#define ADC_CV_CVH_SHIFT                         (16U)
/*! CVH - Compare Value High */
#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
/*! @} */

/* The count of ADC_CV */
#define ADC_CV_COUNT                             (4U)

/*! @name RESFIFO - Data Result FIFO */
/*! @{ */

#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
#define ADC_RESFIFO_D_SHIFT                      (0U)
/*! D - Data Result */
#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)

#define ADC_RESFIFO_TSRC_MASK                    (0x10000U)
#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
/*! TSRC - Trigger Source
 *  0b0..Trigger source 0
 *  0b1..Trigger source 1
 */
#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)

#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
/*! LOOPCNT - Loop Count Value
 *  0b0000..Initial conversion
 *  0b0001..Second conversion
 *  0b0010-0b1110..LOOPCNT + 1 conversion
 *  0b1111..16th conversion
 */
#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)

#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
/*! CMDSRC - Command Buffer Source
 *  0b0000..Not a valid CMDSRC value for a dataword in RESFIFO
 *  0b0001..CMD1
 *  0b0010-0b1110..Corresponding command
 *  0b1111..CMD15
 */
#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)

#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
#define ADC_RESFIFO_VALID_SHIFT                  (31U)
/*! VALID - FIFO Entry is Valid
 *  0b0..Not valid
 *  0b1..Valid
 */
#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
/*! @} */

/* The count of ADC_RESFIFO */
#define ADC_RESFIFO_COUNT                        (2U)

/*! @name CAL_GAR - Calibration General A-Side */
/*! @{ */

#define ADC_CAL_GAR_CAL_GAR_VAL_MASK             (0xFFFFU)
#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT            (0U)
/*! CAL_GAR_VAL - Calibration General A-Side Register Element */
#define ADC_CAL_GAR_CAL_GAR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
/*! @} */

/* The count of ADC_CAL_GAR */
#define ADC_CAL_GAR_COUNT                        (33U)

/*! @name CAL_GBR - Calibration General B-Side */
/*! @{ */

#define ADC_CAL_GBR_CAL_GBR_VAL_MASK             (0xFFFFU)
#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT            (0U)
/*! CAL_GBR_VAL - Calibration General B-Side Register Element */
#define ADC_CAL_GBR_CAL_GBR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
/*! @} */

/* The count of ADC_CAL_GBR */
#define ADC_CAL_GBR_COUNT                        (33U)

/*! @name CFG2 - Configuration 2 */
/*! @{ */

#define ADC_CFG2_JLEFT_MASK                      (0x100U)
#define ADC_CFG2_JLEFT_SHIFT                     (8U)
/*! JLEFT - Justified Left Enable
 *  0b0..Standard format
 *  0b1..Left-justified format
 */
#define ADC_CFG2_JLEFT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_JLEFT_SHIFT)) & ADC_CFG2_JLEFT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ADC_Register_Masks */


/* ADC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ADC0 base address */
  #define ADC0_BASE                                (0x5020C000u)
  /** Peripheral ADC0 base address */
  #define ADC0_BASE_NS                             (0x4020C000u)
  /** Peripheral ADC0 base pointer */
  #define ADC0                                     ((ADC_Type *)ADC0_BASE)
  /** Peripheral ADC0 base pointer */
  #define ADC0_NS                                  ((ADC_Type *)ADC0_BASE_NS)
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS                           { ADC0_BASE }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS                            { ADC0 }
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS_NS                        { ADC0_BASE_NS }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS_NS                         { ADC0_NS }
#else
  /** Peripheral ADC0 base address */
  #define ADC0_BASE                                (0x4020C000u)
  /** Peripheral ADC0 base pointer */
  #define ADC0                                     ((ADC_Type *)ADC0_BASE)
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS                           { ADC0_BASE }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS                            { ADC0 }
#endif

/*!
 * @}
 */ /* end of group ADC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AHBSC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AHBSC0_Peripheral_Access_Layer AHBSC0 Peripheral Access Layer
 * @{
 */

/** AHBSC0 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t ROM_MEM_RULE[4];                   /**< ROM Memory Rule Register, array offset: 0x10, array step: 0x4 */
       uint8_t RESERVED_1[16];
  __IO uint32_t XSPI1_REGION0_MEM_RULE[4];         /**< XSPI1 Region 0 Memory Rule Register, array offset: 0x30, array step: 0x4 */
  struct {                                         /* offset: 0x40, array step: 0x10 */
    __IO uint32_t XSPI1_REGION_MEM_RULE0;            /**< XSPI1 Region 1 Memory Rule Register..XSPI1 Region 4 Memory Rule Register, array offset: 0x40, array step: 0x10 */
         uint8_t RESERVED_0[12];
  } XSPI1_REGION1_4_MEM_RULE[4];
       uint8_t RESERVED_2[16];
  __IO uint32_t XSPI0_REGION0_MEM_RULE[4];         /**< XSPI0 Region 0 Memory Rule, array offset: 0x90, array step: 0x4 */
  struct {                                         /* offset: 0xA0, array step: 0x10 */
    __IO uint32_t XSPI0_REGION_MEM_RULE0;            /**< XSPI0 Region 1 Memory Rule Register..XSPI0 Region 4 Memory Rule Register, array offset: 0xA0, array step: 0x10 */
         uint8_t RESERVED_0[12];
  } XSPI0_REGION1_4_MEM_RULE[4];
       uint8_t RESERVED_3[16];
  __IO uint32_t PKC_RAM_RULE[1];                   /**< PKC RAM Memory Rule Register, array offset: 0xF0, array step: 0x4 */
       uint8_t RESERVED_4[28];
  __IO uint32_t SRAM_0_RULE[4];                    /**< RAM partition 0 Memory Rule Register, array offset: 0x110, array step: 0x4 */
  __IO uint32_t SRAM_1_RULE[4];                    /**< RAM partition 1 Memory Rule Register, array offset: 0x120, array step: 0x4 */
  __IO uint32_t SRAM_2_RULE[4];                    /**< RAM partition 2 Memory Rule Register, array offset: 0x130, array step: 0x4 */
  __IO uint32_t SRAM_3_RULE[4];                    /**< RAM partition 3 Memory Rule Register, array offset: 0x140, array step: 0x4 */
       uint8_t RESERVED_5[16];
  __IO uint32_t SRAM_4_RULE[4];                    /**< RAM partition 4 Memory Rule Register, array offset: 0x160, array step: 0x4 */
  __IO uint32_t SRAM_5_RULE[4];                    /**< RAM partition 5 Memory Rule Register, array offset: 0x170, array step: 0x4 */
       uint8_t RESERVED_6[16];
  __IO uint32_t SRAM_6_RULE[4];                    /**< RAM partition 6 Memory Rule Register, array offset: 0x190, array step: 0x4 */
  __IO uint32_t SRAM_7_RULE[4];                    /**< RAM partition 7 Memory Rule Register, array offset: 0x1A0, array step: 0x4 */
       uint8_t RESERVED_7[16];
  __IO uint32_t SRAM_8_RULE[4];                    /**< RAM partition 8 Memory Rule Register, array offset: 0x1C0, array step: 0x4 */
  __IO uint32_t SRAM_9_RULE[4];                    /**< RAM partition 9 Memory Rule Register, array offset: 0x1D0, array step: 0x4 */
       uint8_t RESERVED_8[16];
  __IO uint32_t SRAM_10_RULE[4];                   /**< RAM partition 10 Memory Rule Register, array offset: 0x1F0, array step: 0x4 */
  __IO uint32_t SRAM_11_RULE[4];                   /**< RAM partition 11 Memory Rule Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_9[16];
  __IO uint32_t SRAM_12_RULE[4];                   /**< RAM partition 12 Memory Rule Register, array offset: 0x220, array step: 0x4 */
  __IO uint32_t SRAM_13_RULE[4];                   /**< RAM partition 13 Memory Rule Register, array offset: 0x230, array step: 0x4 */
       uint8_t RESERVED_10[16];
  __IO uint32_t SRAM_14_RULE[4];                   /**< RAM partition 14 Memory Rule Register, array offset: 0x250, array step: 0x4 */
  __IO uint32_t SRAM_15_RULE[4];                   /**< RAM partition 15 Memory Rule Register, array offset: 0x260, array step: 0x4 */
       uint8_t RESERVED_11[16];
  __IO uint32_t SRAM_16_RULE[4];                   /**< RAM partition 16 Memory Rule Register, array offset: 0x280, array step: 0x4 */
  __IO uint32_t SRAM_17_RULE[4];                   /**< RAM partition 17 Memory Rule Register, array offset: 0x290, array step: 0x4 */
       uint8_t RESERVED_12[16];
  __IO uint32_t SRAM_18_RULE[4];                   /**< RAM partition 18 Memory Rule Register, array offset: 0x2B0, array step: 0x4 */
  __IO uint32_t SRAM_19_RULE[4];                   /**< RAM partition 19 Memory Rule Register, array offset: 0x2C0, array step: 0x4 */
  __IO uint32_t SRAM_20_RULE[4];                   /**< RAM partition 20 Memory Rule Register, array offset: 0x2D0, array step: 0x4 */
  __IO uint32_t SRAM_21_RULE[4];                   /**< RAM partition 21 Memory Rule Register, array offset: 0x2E0, array step: 0x4 */
  __IO uint32_t SRAM_22_RULE[4];                   /**< RAM partition 22 Memory Rule Register, array offset: 0x2F0, array step: 0x4 */
  __IO uint32_t SRAM_23_RULE[4];                   /**< RAM partition 23 Memory Rule Register, array offset: 0x300, array step: 0x4 */
  __IO uint32_t SRAM_24_RULE[4];                   /**< RAM partition 24 Memory Rule Register, array offset: 0x310, array step: 0x4 */
  __IO uint32_t SRAM_25_RULE[4];                   /**< RAM partition 25 Memory Rule Register, array offset: 0x320, array step: 0x4 */
       uint8_t RESERVED_13[16];
  __IO uint32_t SRAM_26_RULE[4];                   /**< RAM partition 26 Memory Rule Register, array offset: 0x340, array step: 0x4 */
  __IO uint32_t SRAM_27_RULE[4];                   /**< RAM partition 27 Memory Rule Register, array offset: 0x350, array step: 0x4 */
  __IO uint32_t SRAM_28_RULE[4];                   /**< RAM partition 28 Memory Rule Register, array offset: 0x360, array step: 0x4 */
  __IO uint32_t SRAM_29_RULE[4];                   /**< RAM partition 29 Memory Rule Register, array offset: 0x370, array step: 0x4 */
       uint8_t RESERVED_14[16];
  __IO uint32_t HIFI4_TCM_RULE[1];                 /**< HIFI4 TCM Memory Rule Register, array offset: 0x390, array step: 0x4 */
       uint8_t RESERVED_15[12];
  __IO uint32_t COMPUTE2MEDIA_RULE;                /**< COMPUTE domain to MEDIA domain Access Rule Register, offset: 0x3A0 */
       uint8_t RESERVED_16[12];
  __IO uint32_t MBUS2PBUS_RULE;                    /**< COMPUTE Pbus domain Rule Register, offset: 0x3B0 */
       uint8_t RESERVED_17[16];
  __IO uint32_t AHB_PERIPHERAL0_SLAVE_RULE1;       /**< AHB Peripheral 0 Slaves Rule Register 1, offset: 0x3C4 */
       uint8_t RESERVED_18[8];
  struct {                                         /* offset: 0x3D0, array step: 0x10 */
    __IO uint32_t AHB_PERIPHERAL0_SLAVE_GPIO_RULE;   /**< AHB Peripheral 0 Slaves GPIO0 Rule Register..AHB Peripheral 0 Slaves GPIO7 Rule Register, array offset: 0x3D0, array step: 0x10 */
         uint8_t RESERVED_0[12];
  } AHB_PERIPHERAL0_SLAVE_GPION_RULE[8];
  __IO uint32_t AHB_PERIPHERAL1_SLAVE_RULE;        /**< AHB Peripheral 1 Slaves Rule Register, offset: 0x450 */
       uint8_t RESERVED_19[12];
  __IO uint32_t AIPS1_BRIDGE_GROUP0_MEM_RULE0;     /**< AIPS1 Bridge Group 0 Memory Rule Register 0, offset: 0x460 */
  __IO uint32_t AIPS1_BRIDGE_GROUP0_MEM_RULE1;     /**< AIPS1 Bridge Group 0 Memory Rule Register 1, offset: 0x464 */
  __IO uint32_t AIPS1_BRIDGE_GROUP0_MEM_RULE2;     /**< AIPS1 Bridge Group 0 Memory Rule Register 2, offset: 0x468 */
       uint8_t RESERVED_20[4];
  __IO uint32_t AIPS1_BRIDGE_GROUP1_MEM_RULE0;     /**< AIPS1 Bridge Group 1 Memory Rule Register 0, offset: 0x470 */
  __IO uint32_t AIPS1_BRIDGE_GROUP1_MEM_RULE1;     /**< AIPS1 Bridge Group 1 Memory Rule Register 1, offset: 0x474 */
       uint8_t RESERVED_21[8];
  __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_RULE0;  /**< AHB Secure Control Peripheral Rule 0, offset: 0x480 */
       uint8_t RESERVED_22[12];
  __IO uint32_t AHB_PERIPHERAL2_SLAVE_RULE0;       /**< AHB Peripheral 2 Slave Rule Register 0, offset: 0x490 */
  __IO uint32_t AHB_PERIPHERAL2_SLAVE_RULE1;       /**< AHB Peripheral 2 Slave Rule Register 1, offset: 0x494 */
       uint8_t RESERVED_23[8];
  __IO uint32_t AIPS0_BRIDGE_GROUP0_MEM_RULE0;     /**< AIPS0 Bridge Group 0 Memory Rule Register 0, offset: 0x4A0 */
  __IO uint32_t AIPS0_BRIDGE_GROUP0_MEM_RULE1;     /**< AIPS0 Bridge Group 0 Memory Rule Register 1, offset: 0x4A4 */
       uint8_t RESERVED_24[8];
  __IO uint32_t AIPS0_BRIDGE_GROUP1_MEM_RULE0;     /**< AIPS0 Bridge Group 1 Memory Rule Register 0, offset: 0x4B0 */
       uint8_t RESERVED_25[28];
  __IO uint32_t APB_SLAVE_GROUP0_RULE0;            /**< APB Bridge Peripheral 0 Rule 0, offset: 0x4D0 */
  __IO uint32_t APB_SLAVE_GROUP0_RULE1;            /**< APB Bridge Peripheral 0 Rule Register 1, offset: 0x4D4 */
  __IO uint32_t APB_SLAVE_GROUP0_RULE2;            /**< APB Bridge Peripheral 0 Rule Register 2, offset: 0x4D8 */
  __IO uint32_t APB_SLAVE_GROUP0_RULE3;            /**< APB Bridge Peripheral 0 Rule Register 3, offset: 0x4DC */
  __IO uint32_t APB_SLAVE_GROUP1_RULE0;            /**< APB Bridge Peripheral 1 Rule Register 0, offset: 0x4E0 */
  __IO uint32_t APB_SLAVE_GROUP1_RULE1;            /**< APB Bridge Peripheral 1 Rule Register 1, offset: 0x4E4 */
  __IO uint32_t APB_SLAVE_GROUP1_RULE2;            /**< APB Bridge Peripheral 1 Rule 2 Register, offset: 0x4E8 */
  __IO uint32_t APB_SLAVE_GROUP1_RULE3;            /**< APB Bridge Peripheral 1 Rule 3 Register, offset: 0x4EC */
  __IO uint32_t SHARED_APB_SLAVE_GROUP0_RULE0;     /**< Shared APB Bridge Peripheral 0 Rule 0, offset: 0x4F0 */
  __IO uint32_t SHARED_APB_SLAVE_GROUP0_RULE1;     /**< Shared APB Bridge Peripheral 0 Rule 1, offset: 0x4F4 */
       uint8_t RESERVED_26[24];
  __IO uint32_t AIPS2_BRIDGE_GROUP0_MEM_RULE0;     /**< AIPS2 Bridge Group 0 Memory Rule Register 0, offset: 0x510 */
  __IO uint32_t AIPS2_BRIDGE_GROUP0_MEM_RULE1;     /**< AIPS2 Bridge Group 0 Memory Rule Register 1, offset: 0x514 */
       uint8_t RESERVED_27[8];
  __IO uint32_t AIPS2_BRIDGE_GROUP1_MEM_RULE0;     /**< AIPS2 Bridge Group 1 Memory Rule Register 0, offset: 0x520 */
       uint8_t RESERVED_28[12];
  __IO uint32_t AHB_SECURE_CTRL_SENSE_RULE0;       /**< Sense Domain AHB Secure Control Peripheral Rule 0, offset: 0x530 */
       uint8_t RESERVED_29[28];
  __IO uint32_t MEDIA_AHB_PERIPHERAL_SLAVE_RULE0;  /**< MEDIA domain AHB peripheral slave, offset: 0x550 */
       uint8_t RESERVED_30[12];
  __IO uint32_t MEDIA_APB_PERIPHERAL_SLAVE_RULE0;  /**< MEDIA domain APB peripheral slave Rule Register, offset: 0x560 */
       uint8_t RESERVED_31[12];
  __IO uint32_t EZHV_SRAM_RULE0;                   /**< EZHV SRAM Memory Rule Register, offset: 0x570 */
       uint8_t RESERVED_32[2188];
  __I  uint32_t SEC_VIO_ADDR[29];                  /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */
       uint8_t RESERVED_33[12];
  __I  uint32_t SEC_VIO_MISC_INFO[29];             /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */
       uint8_t RESERVED_34[12];
  __IO uint32_t SEC_VIO_INFO_VALID;                /**< Security Violation Info Validity for Address, offset: 0xF00 */
       uint8_t RESERVED_35[124];
  __IO uint32_t COMPUTE_ARB0RAM_ACCESS_ENABLE;     /**< Access enable for COMPUTE domain masters to RAM partitions., offset: 0xF80 */
  __IO uint32_t SENSE_ARB0RAM_ACCESS_ENABLE;       /**< Access enable for SENSE domain masters to RAM partitions., offset: 0xF84 */
  __IO uint32_t MEDIA_ARB0RAM_ACCESS_ENABLE;       /**< Access enable for MEDIA domain masters to RAM partitions., offset: 0xF88 */
  __IO uint32_t NPU_ARB0RAM_ACCESS_ENABLE;         /**< Access enable for NPU domain masters to RAM partitions., offset: 0xF8C */
  __IO uint32_t HIFI4_ARB0RAM_ACCESS_ENABLE;       /**< Access enable for HIFI4 to RAM partitions., offset: 0xF90 */
       uint8_t RESERVED_36[60];
  __IO uint32_t MASTER_SEC_LEVEL;                  /**< Master Secure Level, offset: 0xFD0 */
  __IO uint32_t MASTER_SEC_ANTI_POL_REG;           /**< Master Secure Level, offset: 0xFD4 */
       uint8_t RESERVED_37[20];
  __IO uint32_t CPU0_LOCK_REG;                     /**< Miscellaneous CPU0 Control Signals, offset: 0xFEC */
       uint8_t RESERVED_38[8];
  __IO uint32_t MISC_CTRL_DP_REG;                  /**< Secure Control Duplicate, offset: 0xFF8 */
  __IO uint32_t MISC_CTRL_REG;                     /**< Secure Control, offset: 0xFFC */
} AHBSC0_Type;

/* ----------------------------------------------------------------------------
   -- AHBSC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AHBSC0_Register_Masks AHBSC0 Register Masks
 * @{
 */

/*! @name ROM_MEM_RULE - ROM Memory Rule Register */
/*! @{ */

#define AHBSC0_ROM_MEM_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_ROM_MEM_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_ROM_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_ROM_MEM_RULE_RULE0_SHIFT)) & AHBSC0_ROM_MEM_RULE_RULE0_MASK)

#define AHBSC0_ROM_MEM_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_ROM_MEM_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_ROM_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_ROM_MEM_RULE_RULE1_SHIFT)) & AHBSC0_ROM_MEM_RULE_RULE1_MASK)

#define AHBSC0_ROM_MEM_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_ROM_MEM_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_ROM_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_ROM_MEM_RULE_RULE2_SHIFT)) & AHBSC0_ROM_MEM_RULE_RULE2_MASK)

#define AHBSC0_ROM_MEM_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_ROM_MEM_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_ROM_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_ROM_MEM_RULE_RULE3_SHIFT)) & AHBSC0_ROM_MEM_RULE_RULE3_MASK)

#define AHBSC0_ROM_MEM_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_ROM_MEM_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_ROM_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_ROM_MEM_RULE_RULE4_SHIFT)) & AHBSC0_ROM_MEM_RULE_RULE4_MASK)

#define AHBSC0_ROM_MEM_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_ROM_MEM_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_ROM_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_ROM_MEM_RULE_RULE5_SHIFT)) & AHBSC0_ROM_MEM_RULE_RULE5_MASK)

#define AHBSC0_ROM_MEM_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_ROM_MEM_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_ROM_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_ROM_MEM_RULE_RULE6_SHIFT)) & AHBSC0_ROM_MEM_RULE_RULE6_MASK)

#define AHBSC0_ROM_MEM_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_ROM_MEM_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_ROM_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_ROM_MEM_RULE_RULE7_SHIFT)) & AHBSC0_ROM_MEM_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_ROM_MEM_RULE */
#define AHBSC0_ROM_MEM_RULE_COUNT                (4U)

/*! @name XSPI1_REGION0_MEM_RULE - XSPI1 Region 0 Memory Rule Register */
/*! @{ */

#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE0_MASK (0x3U)
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION0_MEM_RULE_RULE0_SHIFT)) & AHBSC0_XSPI1_REGION0_MEM_RULE_RULE0_MASK)

#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE1_MASK (0x30U)
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION0_MEM_RULE_RULE1_SHIFT)) & AHBSC0_XSPI1_REGION0_MEM_RULE_RULE1_MASK)

#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE2_MASK (0x300U)
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE2(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION0_MEM_RULE_RULE2_SHIFT)) & AHBSC0_XSPI1_REGION0_MEM_RULE_RULE2_MASK)

#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE3_MASK (0x3000U)
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE3(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION0_MEM_RULE_RULE3_SHIFT)) & AHBSC0_XSPI1_REGION0_MEM_RULE_RULE3_MASK)

#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE4_MASK (0x30000U)
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE4(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION0_MEM_RULE_RULE4_SHIFT)) & AHBSC0_XSPI1_REGION0_MEM_RULE_RULE4_MASK)

#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE5_MASK (0x300000U)
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE5(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION0_MEM_RULE_RULE5_SHIFT)) & AHBSC0_XSPI1_REGION0_MEM_RULE_RULE5_MASK)

#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE6(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION0_MEM_RULE_RULE6_SHIFT)) & AHBSC0_XSPI1_REGION0_MEM_RULE_RULE6_MASK)

#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_RULE7(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION0_MEM_RULE_RULE7_SHIFT)) & AHBSC0_XSPI1_REGION0_MEM_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_XSPI1_REGION0_MEM_RULE */
#define AHBSC0_XSPI1_REGION0_MEM_RULE_COUNT      (4U)

/*! @name XSPI1_REGION_MEM_RULE0 - XSPI1 Region 1 Memory Rule Register..XSPI1 Region 4 Memory Rule Register */
/*! @{ */

#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE0_MASK (0x3U)
#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION_MEM_RULE0_RULE0_SHIFT)) & AHBSC0_XSPI1_REGION_MEM_RULE0_RULE0_MASK)

#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE1_MASK (0x30U)
#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION_MEM_RULE0_RULE1_SHIFT)) & AHBSC0_XSPI1_REGION_MEM_RULE0_RULE1_MASK)

#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE2_MASK (0x300U)
#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE2(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION_MEM_RULE0_RULE2_SHIFT)) & AHBSC0_XSPI1_REGION_MEM_RULE0_RULE2_MASK)

#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE3_MASK (0x3000U)
#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI1_REGION_MEM_RULE0_RULE3(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI1_REGION_MEM_RULE0_RULE3_SHIFT)) & AHBSC0_XSPI1_REGION_MEM_RULE0_RULE3_MASK)
/*! @} */

/* The count of AHBSC0_XSPI1_REGION_MEM_RULE0 */
#define AHBSC0_XSPI1_REGION_MEM_RULE0_COUNT      (4U)

/*! @name XSPI0_REGION0_MEM_RULE - XSPI0 Region 0 Memory Rule */
/*! @{ */

#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE0_MASK (0x3U)
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION0_MEM_RULE_RULE0_SHIFT)) & AHBSC0_XSPI0_REGION0_MEM_RULE_RULE0_MASK)

#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE1_MASK (0x30U)
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION0_MEM_RULE_RULE1_SHIFT)) & AHBSC0_XSPI0_REGION0_MEM_RULE_RULE1_MASK)

#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE2_MASK (0x300U)
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE2(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION0_MEM_RULE_RULE2_SHIFT)) & AHBSC0_XSPI0_REGION0_MEM_RULE_RULE2_MASK)

#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE3_MASK (0x3000U)
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE3(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION0_MEM_RULE_RULE3_SHIFT)) & AHBSC0_XSPI0_REGION0_MEM_RULE_RULE3_MASK)

#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE4_MASK (0x30000U)
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE4(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION0_MEM_RULE_RULE4_SHIFT)) & AHBSC0_XSPI0_REGION0_MEM_RULE_RULE4_MASK)

#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE5_MASK (0x300000U)
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE5(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION0_MEM_RULE_RULE5_SHIFT)) & AHBSC0_XSPI0_REGION0_MEM_RULE_RULE5_MASK)

#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE6(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION0_MEM_RULE_RULE6_SHIFT)) & AHBSC0_XSPI0_REGION0_MEM_RULE_RULE6_MASK)

#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_RULE7(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION0_MEM_RULE_RULE7_SHIFT)) & AHBSC0_XSPI0_REGION0_MEM_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_XSPI0_REGION0_MEM_RULE */
#define AHBSC0_XSPI0_REGION0_MEM_RULE_COUNT      (4U)

/*! @name XSPI0_REGION_MEM_RULE0 - XSPI0 Region 1 Memory Rule Register..XSPI0 Region 4 Memory Rule Register */
/*! @{ */

#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE0_MASK (0x3U)
#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION_MEM_RULE0_RULE0_SHIFT)) & AHBSC0_XSPI0_REGION_MEM_RULE0_RULE0_MASK)

#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE1_MASK (0x30U)
#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION_MEM_RULE0_RULE1_SHIFT)) & AHBSC0_XSPI0_REGION_MEM_RULE0_RULE1_MASK)

#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE2_MASK (0x300U)
#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE2(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION_MEM_RULE0_RULE2_SHIFT)) & AHBSC0_XSPI0_REGION_MEM_RULE0_RULE2_MASK)

#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE3_MASK (0x3000U)
#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_XSPI0_REGION_MEM_RULE0_RULE3(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_XSPI0_REGION_MEM_RULE0_RULE3_SHIFT)) & AHBSC0_XSPI0_REGION_MEM_RULE0_RULE3_MASK)
/*! @} */

/* The count of AHBSC0_XSPI0_REGION_MEM_RULE0 */
#define AHBSC0_XSPI0_REGION_MEM_RULE0_COUNT      (4U)

/*! @name PKC_RAM_RULE - PKC RAM Memory Rule Register */
/*! @{ */

#define AHBSC0_PKC_RAM_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_PKC_RAM_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_PKC_RAM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_PKC_RAM_RULE_RULE0_SHIFT)) & AHBSC0_PKC_RAM_RULE_RULE0_MASK)

#define AHBSC0_PKC_RAM_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_PKC_RAM_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_PKC_RAM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_PKC_RAM_RULE_RULE1_SHIFT)) & AHBSC0_PKC_RAM_RULE_RULE1_MASK)
/*! @} */

/* The count of AHBSC0_PKC_RAM_RULE */
#define AHBSC0_PKC_RAM_RULE_COUNT                (1U)

/*! @name SRAM_0_RULE - RAM partition 0 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_0_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_0_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_0_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_0_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_0_RULE_RULE0_MASK)

#define AHBSC0_SRAM_0_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_0_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_0_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_0_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_0_RULE_RULE1_MASK)

#define AHBSC0_SRAM_0_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_0_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_0_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_0_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_0_RULE_RULE2_MASK)

#define AHBSC0_SRAM_0_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_0_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_0_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_0_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_0_RULE_RULE3_MASK)

#define AHBSC0_SRAM_0_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_0_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_0_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_0_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_0_RULE_RULE4_MASK)

#define AHBSC0_SRAM_0_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_0_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_0_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_0_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_0_RULE_RULE5_MASK)

#define AHBSC0_SRAM_0_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_0_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_0_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_0_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_0_RULE_RULE6_MASK)

#define AHBSC0_SRAM_0_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_0_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_0_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_0_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_0_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_0_RULE */
#define AHBSC0_SRAM_0_RULE_COUNT                 (4U)

/*! @name SRAM_1_RULE - RAM partition 1 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_1_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_1_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_1_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_1_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_1_RULE_RULE0_MASK)

#define AHBSC0_SRAM_1_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_1_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_1_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_1_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_1_RULE_RULE1_MASK)

#define AHBSC0_SRAM_1_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_1_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_1_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_1_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_1_RULE_RULE2_MASK)

#define AHBSC0_SRAM_1_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_1_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_1_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_1_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_1_RULE_RULE3_MASK)

#define AHBSC0_SRAM_1_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_1_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_1_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_1_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_1_RULE_RULE4_MASK)

#define AHBSC0_SRAM_1_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_1_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_1_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_1_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_1_RULE_RULE5_MASK)

#define AHBSC0_SRAM_1_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_1_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_1_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_1_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_1_RULE_RULE6_MASK)

#define AHBSC0_SRAM_1_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_1_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_1_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_1_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_1_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_1_RULE */
#define AHBSC0_SRAM_1_RULE_COUNT                 (4U)

/*! @name SRAM_2_RULE - RAM partition 2 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_2_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_2_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_2_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_2_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_2_RULE_RULE0_MASK)

#define AHBSC0_SRAM_2_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_2_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_2_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_2_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_2_RULE_RULE1_MASK)

#define AHBSC0_SRAM_2_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_2_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_2_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_2_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_2_RULE_RULE2_MASK)

#define AHBSC0_SRAM_2_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_2_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_2_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_2_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_2_RULE_RULE3_MASK)

#define AHBSC0_SRAM_2_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_2_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_2_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_2_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_2_RULE_RULE4_MASK)

#define AHBSC0_SRAM_2_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_2_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_2_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_2_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_2_RULE_RULE5_MASK)

#define AHBSC0_SRAM_2_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_2_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_2_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_2_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_2_RULE_RULE6_MASK)

#define AHBSC0_SRAM_2_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_2_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_2_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_2_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_2_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_2_RULE */
#define AHBSC0_SRAM_2_RULE_COUNT                 (4U)

/*! @name SRAM_3_RULE - RAM partition 3 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_3_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_3_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_3_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_3_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_3_RULE_RULE0_MASK)

#define AHBSC0_SRAM_3_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_3_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_3_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_3_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_3_RULE_RULE1_MASK)

#define AHBSC0_SRAM_3_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_3_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_3_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_3_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_3_RULE_RULE2_MASK)

#define AHBSC0_SRAM_3_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_3_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_3_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_3_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_3_RULE_RULE3_MASK)

#define AHBSC0_SRAM_3_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_3_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_3_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_3_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_3_RULE_RULE4_MASK)

#define AHBSC0_SRAM_3_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_3_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_3_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_3_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_3_RULE_RULE5_MASK)

#define AHBSC0_SRAM_3_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_3_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_3_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_3_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_3_RULE_RULE6_MASK)

#define AHBSC0_SRAM_3_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_3_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_3_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_3_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_3_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_3_RULE */
#define AHBSC0_SRAM_3_RULE_COUNT                 (4U)

/*! @name SRAM_4_RULE - RAM partition 4 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_4_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_4_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_4_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_4_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_4_RULE_RULE0_MASK)

#define AHBSC0_SRAM_4_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_4_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_4_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_4_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_4_RULE_RULE1_MASK)

#define AHBSC0_SRAM_4_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_4_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_4_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_4_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_4_RULE_RULE2_MASK)

#define AHBSC0_SRAM_4_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_4_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_4_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_4_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_4_RULE_RULE3_MASK)

#define AHBSC0_SRAM_4_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_4_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_4_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_4_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_4_RULE_RULE4_MASK)

#define AHBSC0_SRAM_4_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_4_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_4_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_4_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_4_RULE_RULE5_MASK)

#define AHBSC0_SRAM_4_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_4_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_4_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_4_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_4_RULE_RULE6_MASK)

#define AHBSC0_SRAM_4_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_4_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_4_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_4_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_4_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_4_RULE */
#define AHBSC0_SRAM_4_RULE_COUNT                 (4U)

/*! @name SRAM_5_RULE - RAM partition 5 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_5_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_5_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_5_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_5_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_5_RULE_RULE0_MASK)

#define AHBSC0_SRAM_5_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_5_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_5_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_5_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_5_RULE_RULE1_MASK)

#define AHBSC0_SRAM_5_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_5_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_5_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_5_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_5_RULE_RULE2_MASK)

#define AHBSC0_SRAM_5_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_5_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_5_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_5_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_5_RULE_RULE3_MASK)

#define AHBSC0_SRAM_5_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_5_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_5_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_5_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_5_RULE_RULE4_MASK)

#define AHBSC0_SRAM_5_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_5_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_5_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_5_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_5_RULE_RULE5_MASK)

#define AHBSC0_SRAM_5_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_5_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_5_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_5_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_5_RULE_RULE6_MASK)

#define AHBSC0_SRAM_5_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_5_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_5_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_5_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_5_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_5_RULE */
#define AHBSC0_SRAM_5_RULE_COUNT                 (4U)

/*! @name SRAM_6_RULE - RAM partition 6 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_6_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_6_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_6_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_6_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_6_RULE_RULE0_MASK)

#define AHBSC0_SRAM_6_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_6_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_6_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_6_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_6_RULE_RULE1_MASK)

#define AHBSC0_SRAM_6_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_6_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_6_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_6_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_6_RULE_RULE2_MASK)

#define AHBSC0_SRAM_6_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_6_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_6_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_6_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_6_RULE_RULE3_MASK)

#define AHBSC0_SRAM_6_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_6_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_6_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_6_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_6_RULE_RULE4_MASK)

#define AHBSC0_SRAM_6_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_6_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_6_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_6_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_6_RULE_RULE5_MASK)

#define AHBSC0_SRAM_6_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_6_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_6_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_6_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_6_RULE_RULE6_MASK)

#define AHBSC0_SRAM_6_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_6_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_6_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_6_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_6_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_6_RULE */
#define AHBSC0_SRAM_6_RULE_COUNT                 (4U)

/*! @name SRAM_7_RULE - RAM partition 7 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_7_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_7_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_7_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_7_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_7_RULE_RULE0_MASK)

#define AHBSC0_SRAM_7_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_7_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_7_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_7_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_7_RULE_RULE1_MASK)

#define AHBSC0_SRAM_7_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_7_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_7_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_7_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_7_RULE_RULE2_MASK)

#define AHBSC0_SRAM_7_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_7_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_7_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_7_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_7_RULE_RULE3_MASK)

#define AHBSC0_SRAM_7_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_7_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_7_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_7_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_7_RULE_RULE4_MASK)

#define AHBSC0_SRAM_7_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_7_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_7_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_7_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_7_RULE_RULE5_MASK)

#define AHBSC0_SRAM_7_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_7_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_7_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_7_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_7_RULE_RULE6_MASK)

#define AHBSC0_SRAM_7_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_7_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_7_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_7_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_7_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_7_RULE */
#define AHBSC0_SRAM_7_RULE_COUNT                 (4U)

/*! @name SRAM_8_RULE - RAM partition 8 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_8_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_8_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_8_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_8_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_8_RULE_RULE0_MASK)

#define AHBSC0_SRAM_8_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_8_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_8_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_8_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_8_RULE_RULE1_MASK)

#define AHBSC0_SRAM_8_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_8_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_8_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_8_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_8_RULE_RULE2_MASK)

#define AHBSC0_SRAM_8_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_8_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_8_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_8_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_8_RULE_RULE3_MASK)

#define AHBSC0_SRAM_8_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_8_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_8_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_8_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_8_RULE_RULE4_MASK)

#define AHBSC0_SRAM_8_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_8_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_8_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_8_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_8_RULE_RULE5_MASK)

#define AHBSC0_SRAM_8_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_8_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_8_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_8_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_8_RULE_RULE6_MASK)

#define AHBSC0_SRAM_8_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_8_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_8_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_8_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_8_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_8_RULE */
#define AHBSC0_SRAM_8_RULE_COUNT                 (4U)

/*! @name SRAM_9_RULE - RAM partition 9 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_9_RULE_RULE0_MASK            (0x3U)
#define AHBSC0_SRAM_9_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_9_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_9_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_9_RULE_RULE0_MASK)

#define AHBSC0_SRAM_9_RULE_RULE1_MASK            (0x30U)
#define AHBSC0_SRAM_9_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_9_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_9_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_9_RULE_RULE1_MASK)

#define AHBSC0_SRAM_9_RULE_RULE2_MASK            (0x300U)
#define AHBSC0_SRAM_9_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_9_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_9_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_9_RULE_RULE2_MASK)

#define AHBSC0_SRAM_9_RULE_RULE3_MASK            (0x3000U)
#define AHBSC0_SRAM_9_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_9_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_9_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_9_RULE_RULE3_MASK)

#define AHBSC0_SRAM_9_RULE_RULE4_MASK            (0x30000U)
#define AHBSC0_SRAM_9_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_9_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_9_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_9_RULE_RULE4_MASK)

#define AHBSC0_SRAM_9_RULE_RULE5_MASK            (0x300000U)
#define AHBSC0_SRAM_9_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_9_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_9_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_9_RULE_RULE5_MASK)

#define AHBSC0_SRAM_9_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC0_SRAM_9_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_9_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_9_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_9_RULE_RULE6_MASK)

#define AHBSC0_SRAM_9_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC0_SRAM_9_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_9_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_9_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_9_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_9_RULE */
#define AHBSC0_SRAM_9_RULE_COUNT                 (4U)

/*! @name SRAM_10_RULE - RAM partition 10 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_10_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_10_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_10_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_10_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_10_RULE_RULE0_MASK)

#define AHBSC0_SRAM_10_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_10_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_10_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_10_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_10_RULE_RULE1_MASK)

#define AHBSC0_SRAM_10_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_10_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_10_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_10_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_10_RULE_RULE2_MASK)

#define AHBSC0_SRAM_10_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_10_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_10_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_10_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_10_RULE_RULE3_MASK)

#define AHBSC0_SRAM_10_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_10_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_10_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_10_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_10_RULE_RULE4_MASK)

#define AHBSC0_SRAM_10_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_10_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_10_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_10_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_10_RULE_RULE5_MASK)

#define AHBSC0_SRAM_10_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_10_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_10_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_10_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_10_RULE_RULE6_MASK)

#define AHBSC0_SRAM_10_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_10_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_10_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_10_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_10_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_10_RULE */
#define AHBSC0_SRAM_10_RULE_COUNT                (4U)

/*! @name SRAM_11_RULE - RAM partition 11 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_11_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_11_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_11_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_11_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_11_RULE_RULE0_MASK)

#define AHBSC0_SRAM_11_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_11_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_11_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_11_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_11_RULE_RULE1_MASK)

#define AHBSC0_SRAM_11_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_11_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_11_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_11_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_11_RULE_RULE2_MASK)

#define AHBSC0_SRAM_11_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_11_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_11_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_11_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_11_RULE_RULE3_MASK)

#define AHBSC0_SRAM_11_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_11_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_11_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_11_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_11_RULE_RULE4_MASK)

#define AHBSC0_SRAM_11_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_11_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_11_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_11_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_11_RULE_RULE5_MASK)

#define AHBSC0_SRAM_11_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_11_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_11_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_11_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_11_RULE_RULE6_MASK)

#define AHBSC0_SRAM_11_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_11_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_11_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_11_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_11_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_11_RULE */
#define AHBSC0_SRAM_11_RULE_COUNT                (4U)

/*! @name SRAM_12_RULE - RAM partition 12 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_12_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_12_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_12_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_12_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_12_RULE_RULE0_MASK)

#define AHBSC0_SRAM_12_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_12_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_12_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_12_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_12_RULE_RULE1_MASK)

#define AHBSC0_SRAM_12_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_12_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_12_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_12_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_12_RULE_RULE2_MASK)

#define AHBSC0_SRAM_12_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_12_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_12_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_12_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_12_RULE_RULE3_MASK)

#define AHBSC0_SRAM_12_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_12_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_12_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_12_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_12_RULE_RULE4_MASK)

#define AHBSC0_SRAM_12_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_12_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_12_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_12_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_12_RULE_RULE5_MASK)

#define AHBSC0_SRAM_12_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_12_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_12_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_12_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_12_RULE_RULE6_MASK)

#define AHBSC0_SRAM_12_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_12_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_12_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_12_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_12_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_12_RULE */
#define AHBSC0_SRAM_12_RULE_COUNT                (4U)

/*! @name SRAM_13_RULE - RAM partition 13 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_13_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_13_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_13_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_13_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_13_RULE_RULE0_MASK)

#define AHBSC0_SRAM_13_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_13_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_13_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_13_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_13_RULE_RULE1_MASK)

#define AHBSC0_SRAM_13_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_13_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_13_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_13_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_13_RULE_RULE2_MASK)

#define AHBSC0_SRAM_13_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_13_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_13_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_13_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_13_RULE_RULE3_MASK)

#define AHBSC0_SRAM_13_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_13_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_13_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_13_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_13_RULE_RULE4_MASK)

#define AHBSC0_SRAM_13_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_13_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_13_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_13_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_13_RULE_RULE5_MASK)

#define AHBSC0_SRAM_13_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_13_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_13_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_13_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_13_RULE_RULE6_MASK)

#define AHBSC0_SRAM_13_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_13_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_13_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_13_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_13_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_13_RULE */
#define AHBSC0_SRAM_13_RULE_COUNT                (4U)

/*! @name SRAM_14_RULE - RAM partition 14 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_14_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_14_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_14_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_14_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_14_RULE_RULE0_MASK)

#define AHBSC0_SRAM_14_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_14_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_14_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_14_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_14_RULE_RULE1_MASK)

#define AHBSC0_SRAM_14_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_14_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_14_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_14_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_14_RULE_RULE2_MASK)

#define AHBSC0_SRAM_14_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_14_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_14_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_14_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_14_RULE_RULE3_MASK)

#define AHBSC0_SRAM_14_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_14_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_14_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_14_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_14_RULE_RULE4_MASK)

#define AHBSC0_SRAM_14_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_14_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_14_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_14_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_14_RULE_RULE5_MASK)

#define AHBSC0_SRAM_14_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_14_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_14_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_14_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_14_RULE_RULE6_MASK)

#define AHBSC0_SRAM_14_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_14_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_14_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_14_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_14_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_14_RULE */
#define AHBSC0_SRAM_14_RULE_COUNT                (4U)

/*! @name SRAM_15_RULE - RAM partition 15 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_15_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_15_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_15_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_15_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_15_RULE_RULE0_MASK)

#define AHBSC0_SRAM_15_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_15_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_15_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_15_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_15_RULE_RULE1_MASK)

#define AHBSC0_SRAM_15_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_15_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_15_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_15_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_15_RULE_RULE2_MASK)

#define AHBSC0_SRAM_15_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_15_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_15_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_15_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_15_RULE_RULE3_MASK)

#define AHBSC0_SRAM_15_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_15_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_15_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_15_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_15_RULE_RULE4_MASK)

#define AHBSC0_SRAM_15_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_15_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_15_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_15_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_15_RULE_RULE5_MASK)

#define AHBSC0_SRAM_15_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_15_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_15_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_15_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_15_RULE_RULE6_MASK)

#define AHBSC0_SRAM_15_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_15_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_15_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_15_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_15_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_15_RULE */
#define AHBSC0_SRAM_15_RULE_COUNT                (4U)

/*! @name SRAM_16_RULE - RAM partition 16 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_16_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_16_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_16_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_16_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_16_RULE_RULE0_MASK)

#define AHBSC0_SRAM_16_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_16_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_16_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_16_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_16_RULE_RULE1_MASK)

#define AHBSC0_SRAM_16_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_16_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_16_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_16_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_16_RULE_RULE2_MASK)

#define AHBSC0_SRAM_16_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_16_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_16_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_16_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_16_RULE_RULE3_MASK)

#define AHBSC0_SRAM_16_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_16_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_16_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_16_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_16_RULE_RULE4_MASK)

#define AHBSC0_SRAM_16_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_16_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_16_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_16_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_16_RULE_RULE5_MASK)

#define AHBSC0_SRAM_16_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_16_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_16_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_16_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_16_RULE_RULE6_MASK)

#define AHBSC0_SRAM_16_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_16_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_16_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_16_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_16_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_16_RULE */
#define AHBSC0_SRAM_16_RULE_COUNT                (4U)

/*! @name SRAM_17_RULE - RAM partition 17 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_17_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_17_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_17_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_17_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_17_RULE_RULE0_MASK)

#define AHBSC0_SRAM_17_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_17_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_17_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_17_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_17_RULE_RULE1_MASK)

#define AHBSC0_SRAM_17_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_17_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_17_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_17_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_17_RULE_RULE2_MASK)

#define AHBSC0_SRAM_17_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_17_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_17_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_17_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_17_RULE_RULE3_MASK)

#define AHBSC0_SRAM_17_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_17_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_17_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_17_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_17_RULE_RULE4_MASK)

#define AHBSC0_SRAM_17_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_17_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_17_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_17_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_17_RULE_RULE5_MASK)

#define AHBSC0_SRAM_17_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_17_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_17_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_17_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_17_RULE_RULE6_MASK)

#define AHBSC0_SRAM_17_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_17_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_17_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_17_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_17_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_17_RULE */
#define AHBSC0_SRAM_17_RULE_COUNT                (4U)

/*! @name SRAM_18_RULE - RAM partition 18 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_18_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_18_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_18_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_18_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_18_RULE_RULE0_MASK)

#define AHBSC0_SRAM_18_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_18_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_18_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_18_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_18_RULE_RULE1_MASK)

#define AHBSC0_SRAM_18_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_18_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_18_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_18_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_18_RULE_RULE2_MASK)

#define AHBSC0_SRAM_18_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_18_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_18_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_18_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_18_RULE_RULE3_MASK)

#define AHBSC0_SRAM_18_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_18_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_18_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_18_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_18_RULE_RULE4_MASK)

#define AHBSC0_SRAM_18_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_18_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_18_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_18_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_18_RULE_RULE5_MASK)

#define AHBSC0_SRAM_18_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_18_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_18_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_18_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_18_RULE_RULE6_MASK)

#define AHBSC0_SRAM_18_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_18_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_18_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_18_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_18_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_18_RULE */
#define AHBSC0_SRAM_18_RULE_COUNT                (4U)

/*! @name SRAM_19_RULE - RAM partition 19 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_19_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_19_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_19_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_19_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_19_RULE_RULE0_MASK)

#define AHBSC0_SRAM_19_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_19_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_19_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_19_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_19_RULE_RULE1_MASK)

#define AHBSC0_SRAM_19_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_19_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_19_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_19_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_19_RULE_RULE2_MASK)

#define AHBSC0_SRAM_19_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_19_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_19_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_19_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_19_RULE_RULE3_MASK)

#define AHBSC0_SRAM_19_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_19_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_19_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_19_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_19_RULE_RULE4_MASK)

#define AHBSC0_SRAM_19_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_19_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_19_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_19_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_19_RULE_RULE5_MASK)

#define AHBSC0_SRAM_19_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_19_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_19_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_19_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_19_RULE_RULE6_MASK)

#define AHBSC0_SRAM_19_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_19_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_19_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_19_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_19_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_19_RULE */
#define AHBSC0_SRAM_19_RULE_COUNT                (4U)

/*! @name SRAM_20_RULE - RAM partition 20 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_20_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_20_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_20_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_20_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_20_RULE_RULE0_MASK)

#define AHBSC0_SRAM_20_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_20_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_20_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_20_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_20_RULE_RULE1_MASK)

#define AHBSC0_SRAM_20_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_20_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_20_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_20_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_20_RULE_RULE2_MASK)

#define AHBSC0_SRAM_20_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_20_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_20_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_20_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_20_RULE_RULE3_MASK)

#define AHBSC0_SRAM_20_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_20_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_20_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_20_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_20_RULE_RULE4_MASK)

#define AHBSC0_SRAM_20_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_20_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_20_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_20_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_20_RULE_RULE5_MASK)

#define AHBSC0_SRAM_20_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_20_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_20_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_20_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_20_RULE_RULE6_MASK)

#define AHBSC0_SRAM_20_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_20_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_20_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_20_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_20_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_20_RULE */
#define AHBSC0_SRAM_20_RULE_COUNT                (4U)

/*! @name SRAM_21_RULE - RAM partition 21 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_21_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_21_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_21_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_21_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_21_RULE_RULE0_MASK)

#define AHBSC0_SRAM_21_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_21_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_21_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_21_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_21_RULE_RULE1_MASK)

#define AHBSC0_SRAM_21_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_21_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_21_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_21_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_21_RULE_RULE2_MASK)

#define AHBSC0_SRAM_21_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_21_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_21_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_21_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_21_RULE_RULE3_MASK)

#define AHBSC0_SRAM_21_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_21_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_21_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_21_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_21_RULE_RULE4_MASK)

#define AHBSC0_SRAM_21_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_21_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_21_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_21_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_21_RULE_RULE5_MASK)

#define AHBSC0_SRAM_21_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_21_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_21_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_21_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_21_RULE_RULE6_MASK)

#define AHBSC0_SRAM_21_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_21_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_21_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_21_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_21_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_21_RULE */
#define AHBSC0_SRAM_21_RULE_COUNT                (4U)

/*! @name SRAM_22_RULE - RAM partition 22 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_22_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_22_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_22_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_22_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_22_RULE_RULE0_MASK)

#define AHBSC0_SRAM_22_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_22_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_22_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_22_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_22_RULE_RULE1_MASK)

#define AHBSC0_SRAM_22_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_22_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_22_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_22_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_22_RULE_RULE2_MASK)

#define AHBSC0_SRAM_22_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_22_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_22_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_22_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_22_RULE_RULE3_MASK)

#define AHBSC0_SRAM_22_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_22_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_22_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_22_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_22_RULE_RULE4_MASK)

#define AHBSC0_SRAM_22_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_22_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_22_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_22_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_22_RULE_RULE5_MASK)

#define AHBSC0_SRAM_22_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_22_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_22_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_22_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_22_RULE_RULE6_MASK)

#define AHBSC0_SRAM_22_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_22_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_22_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_22_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_22_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_22_RULE */
#define AHBSC0_SRAM_22_RULE_COUNT                (4U)

/*! @name SRAM_23_RULE - RAM partition 23 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_23_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_23_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_23_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_23_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_23_RULE_RULE0_MASK)

#define AHBSC0_SRAM_23_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_23_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_23_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_23_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_23_RULE_RULE1_MASK)

#define AHBSC0_SRAM_23_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_23_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_23_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_23_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_23_RULE_RULE2_MASK)

#define AHBSC0_SRAM_23_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_23_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_23_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_23_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_23_RULE_RULE3_MASK)

#define AHBSC0_SRAM_23_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_23_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_23_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_23_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_23_RULE_RULE4_MASK)

#define AHBSC0_SRAM_23_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_23_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_23_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_23_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_23_RULE_RULE5_MASK)

#define AHBSC0_SRAM_23_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_23_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_23_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_23_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_23_RULE_RULE6_MASK)

#define AHBSC0_SRAM_23_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_23_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_23_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_23_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_23_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_23_RULE */
#define AHBSC0_SRAM_23_RULE_COUNT                (4U)

/*! @name SRAM_24_RULE - RAM partition 24 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_24_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_24_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_24_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_24_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_24_RULE_RULE0_MASK)

#define AHBSC0_SRAM_24_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_24_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_24_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_24_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_24_RULE_RULE1_MASK)

#define AHBSC0_SRAM_24_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_24_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_24_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_24_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_24_RULE_RULE2_MASK)

#define AHBSC0_SRAM_24_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_24_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_24_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_24_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_24_RULE_RULE3_MASK)

#define AHBSC0_SRAM_24_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_24_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_24_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_24_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_24_RULE_RULE4_MASK)

#define AHBSC0_SRAM_24_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_24_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_24_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_24_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_24_RULE_RULE5_MASK)

#define AHBSC0_SRAM_24_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_24_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_24_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_24_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_24_RULE_RULE6_MASK)

#define AHBSC0_SRAM_24_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_24_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_24_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_24_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_24_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_24_RULE */
#define AHBSC0_SRAM_24_RULE_COUNT                (4U)

/*! @name SRAM_25_RULE - RAM partition 25 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_25_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_25_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_25_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_25_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_25_RULE_RULE0_MASK)

#define AHBSC0_SRAM_25_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_25_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_25_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_25_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_25_RULE_RULE1_MASK)

#define AHBSC0_SRAM_25_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_25_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_25_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_25_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_25_RULE_RULE2_MASK)

#define AHBSC0_SRAM_25_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_25_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_25_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_25_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_25_RULE_RULE3_MASK)

#define AHBSC0_SRAM_25_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_25_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_25_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_25_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_25_RULE_RULE4_MASK)

#define AHBSC0_SRAM_25_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_25_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_25_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_25_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_25_RULE_RULE5_MASK)

#define AHBSC0_SRAM_25_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_25_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_25_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_25_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_25_RULE_RULE6_MASK)

#define AHBSC0_SRAM_25_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_25_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_25_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_25_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_25_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_25_RULE */
#define AHBSC0_SRAM_25_RULE_COUNT                (4U)

/*! @name SRAM_26_RULE - RAM partition 26 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_26_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_26_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_26_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_26_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_26_RULE_RULE0_MASK)

#define AHBSC0_SRAM_26_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_26_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_26_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_26_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_26_RULE_RULE1_MASK)

#define AHBSC0_SRAM_26_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_26_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_26_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_26_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_26_RULE_RULE2_MASK)

#define AHBSC0_SRAM_26_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_26_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_26_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_26_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_26_RULE_RULE3_MASK)

#define AHBSC0_SRAM_26_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_26_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_26_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_26_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_26_RULE_RULE4_MASK)

#define AHBSC0_SRAM_26_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_26_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_26_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_26_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_26_RULE_RULE5_MASK)

#define AHBSC0_SRAM_26_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_26_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_26_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_26_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_26_RULE_RULE6_MASK)

#define AHBSC0_SRAM_26_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_26_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_26_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_26_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_26_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_26_RULE */
#define AHBSC0_SRAM_26_RULE_COUNT                (4U)

/*! @name SRAM_27_RULE - RAM partition 27 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_27_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_27_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_27_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_27_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_27_RULE_RULE0_MASK)

#define AHBSC0_SRAM_27_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_27_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_27_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_27_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_27_RULE_RULE1_MASK)

#define AHBSC0_SRAM_27_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_27_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_27_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_27_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_27_RULE_RULE2_MASK)

#define AHBSC0_SRAM_27_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_27_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_27_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_27_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_27_RULE_RULE3_MASK)

#define AHBSC0_SRAM_27_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_27_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_27_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_27_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_27_RULE_RULE4_MASK)

#define AHBSC0_SRAM_27_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_27_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_27_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_27_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_27_RULE_RULE5_MASK)

#define AHBSC0_SRAM_27_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_27_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_27_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_27_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_27_RULE_RULE6_MASK)

#define AHBSC0_SRAM_27_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_27_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_27_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_27_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_27_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_27_RULE */
#define AHBSC0_SRAM_27_RULE_COUNT                (4U)

/*! @name SRAM_28_RULE - RAM partition 28 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_28_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_28_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_28_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_28_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_28_RULE_RULE0_MASK)

#define AHBSC0_SRAM_28_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_28_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_28_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_28_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_28_RULE_RULE1_MASK)

#define AHBSC0_SRAM_28_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_28_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_28_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_28_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_28_RULE_RULE2_MASK)

#define AHBSC0_SRAM_28_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_28_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_28_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_28_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_28_RULE_RULE3_MASK)

#define AHBSC0_SRAM_28_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_28_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_28_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_28_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_28_RULE_RULE4_MASK)

#define AHBSC0_SRAM_28_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_28_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_28_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_28_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_28_RULE_RULE5_MASK)

#define AHBSC0_SRAM_28_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_28_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_28_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_28_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_28_RULE_RULE6_MASK)

#define AHBSC0_SRAM_28_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_28_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_28_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_28_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_28_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_28_RULE */
#define AHBSC0_SRAM_28_RULE_COUNT                (4U)

/*! @name SRAM_29_RULE - RAM partition 29 Memory Rule Register */
/*! @{ */

#define AHBSC0_SRAM_29_RULE_RULE0_MASK           (0x3U)
#define AHBSC0_SRAM_29_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_29_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_29_RULE_RULE0_SHIFT)) & AHBSC0_SRAM_29_RULE_RULE0_MASK)

#define AHBSC0_SRAM_29_RULE_RULE1_MASK           (0x30U)
#define AHBSC0_SRAM_29_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_29_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_29_RULE_RULE1_SHIFT)) & AHBSC0_SRAM_29_RULE_RULE1_MASK)

#define AHBSC0_SRAM_29_RULE_RULE2_MASK           (0x300U)
#define AHBSC0_SRAM_29_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_29_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_29_RULE_RULE2_SHIFT)) & AHBSC0_SRAM_29_RULE_RULE2_MASK)

#define AHBSC0_SRAM_29_RULE_RULE3_MASK           (0x3000U)
#define AHBSC0_SRAM_29_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_29_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_29_RULE_RULE3_SHIFT)) & AHBSC0_SRAM_29_RULE_RULE3_MASK)

#define AHBSC0_SRAM_29_RULE_RULE4_MASK           (0x30000U)
#define AHBSC0_SRAM_29_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_29_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_29_RULE_RULE4_SHIFT)) & AHBSC0_SRAM_29_RULE_RULE4_MASK)

#define AHBSC0_SRAM_29_RULE_RULE5_MASK           (0x300000U)
#define AHBSC0_SRAM_29_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_29_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_29_RULE_RULE5_SHIFT)) & AHBSC0_SRAM_29_RULE_RULE5_MASK)

#define AHBSC0_SRAM_29_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC0_SRAM_29_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_29_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_29_RULE_RULE6_SHIFT)) & AHBSC0_SRAM_29_RULE_RULE6_MASK)

#define AHBSC0_SRAM_29_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC0_SRAM_29_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SRAM_29_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC0_SRAM_29_RULE_RULE7_SHIFT)) & AHBSC0_SRAM_29_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC0_SRAM_29_RULE */
#define AHBSC0_SRAM_29_RULE_COUNT                (4U)

/*! @name HIFI4_TCM_RULE - HIFI4 TCM Memory Rule Register */
/*! @{ */

#define AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE0_MASK (0x3U)
#define AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE0_SHIFT (0U)
/*! HIFI4_DTCM_RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE0_SHIFT)) & AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE0_MASK)

#define AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE1_MASK (0x30U)
#define AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE1_SHIFT (4U)
/*! HIFI4_DTCM_RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE1_SHIFT)) & AHBSC0_HIFI4_TCM_RULE_HIFI4_DTCM_RULE1_MASK)

#define AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE0_MASK (0x30000U)
#define AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE0_SHIFT (16U)
/*! HIFI4_ITCM_RULE0 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE0_SHIFT)) & AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE0_MASK)

#define AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE1_MASK (0x300000U)
#define AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE1_SHIFT (20U)
/*! HIFI4_ITCM_RULE1 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE1_SHIFT)) & AHBSC0_HIFI4_TCM_RULE_HIFI4_ITCM_RULE1_MASK)
/*! @} */

/* The count of AHBSC0_HIFI4_TCM_RULE */
#define AHBSC0_HIFI4_TCM_RULE_COUNT              (1U)

/*! @name COMPUTE2MEDIA_RULE - COMPUTE domain to MEDIA domain Access Rule Register */
/*! @{ */

#define AHBSC0_COMPUTE2MEDIA_RULE_XSPI2_MASK     (0x3U)
#define AHBSC0_COMPUTE2MEDIA_RULE_XSPI2_SHIFT    (0U)
/*! XSPI2 - XSPI2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_COMPUTE2MEDIA_RULE_XSPI2(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE2MEDIA_RULE_XSPI2_SHIFT)) & AHBSC0_COMPUTE2MEDIA_RULE_XSPI2_MASK)
/*! @} */

/*! @name MBUS2PBUS_RULE - COMPUTE Pbus domain Rule Register */
/*! @{ */

#define AHBSC0_MBUS2PBUS_RULE_PBUS_DOMAIN_MASK   (0x3U)
#define AHBSC0_MBUS2PBUS_RULE_PBUS_DOMAIN_SHIFT  (0U)
/*! PBUS_DOMAIN - COMPUTE Pbus domain
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_MBUS2PBUS_RULE_PBUS_DOMAIN(x)     (((uint32_t)(((uint32_t)(x)) << AHBSC0_MBUS2PBUS_RULE_PBUS_DOMAIN_SHIFT)) & AHBSC0_MBUS2PBUS_RULE_PBUS_DOMAIN_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL0_SLAVE_RULE1 - AHB Peripheral 0 Slaves Rule Register 1 */
/*! @{ */

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM0_MASK (0x3U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM0_SHIFT (0U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM0_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM0_MASK)

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM1_MASK (0x30U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM1_SHIFT (4U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM1_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM1_MASK)

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM2_MASK (0x300U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM2_SHIFT (8U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM2_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM2_MASK)

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM3_MASK (0x3000U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM3_SHIFT (12U)
/*! LP_FLEXCOMM3 - FLEXCOMM3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM3_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_LP_FLEXCOMM3_MASK)

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_SCT0_MASK (0x30000U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_SCT0_SHIFT (16U)
/*! SCT0 - SCT0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_SCT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_SCT0_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_SCT0_MASK)

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG0_MASK (0x300000U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG0_SHIFT (20U)
/*! CDOG0 - CDOG0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG0_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG0_MASK)

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG1_MASK (0x3000000U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG1_SHIFT (24U)
/*! CDOG1 - CDOG1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG1_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG1_MASK)

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG2_MASK (0x30000000U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG2_SHIFT (28U)
/*! CDOG2 - CDOG2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG2_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_RULE1_CDOG2_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL0_SLAVE_GPIO_RULE - AHB Peripheral 0 Slaves GPIO0 Rule Register..AHB Peripheral 0 Slaves GPIO7 Rule Register */
/*! @{ */

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_MASK (0x3U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_SHIFT (0U)
/*! GPIOn - GPIOn
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_MASK)

#define AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_ALIAS_MASK (0x30U)
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_ALIAS_SHIFT (4U)
/*! GPIOn_ALIAS - GPIOn ALIAS
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_ALIAS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_ALIAS_SHIFT)) & AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_GPIOn_ALIAS_MASK)
/*! @} */

/* The count of AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE */
#define AHBSC0_AHB_PERIPHERAL0_SLAVE_GPIO_RULE_COUNT (8U)

/*! @name AHB_PERIPHERAL1_SLAVE_RULE - AHB Peripheral 1 Slaves Rule Register */
/*! @{ */

#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_eDMA1_CH15_MASK (0x300U)
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_eDMA1_CH15_SHIFT (8U)
/*! eDMA1_CH15 - DMA_1_CH15
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_eDMA1_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_eDMA1_CH15_SHIFT)) & AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_eDMA1_CH15_MASK)

#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM4_MASK (0x3000U)
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM4_SHIFT (12U)
/*! FLEXCOMM4 - FLEXCOMM4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM4_SHIFT)) & AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM4_MASK)

#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM5_MASK (0x30000U)
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM5_SHIFT (16U)
/*! FLEXCOMM5 - FLEXCOMM5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM5_SHIFT)) & AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM5_MASK)

#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM6_MASK (0x300000U)
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM6_SHIFT (20U)
/*! FLEXCOMM6 - FLEXCOMM6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM6_SHIFT)) & AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM6_MASK)

#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM7_MASK (0x3000000U)
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM7_SHIFT (24U)
/*! FLEXCOMM7 - FLEXCOMM7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM7_SHIFT)) & AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_FLEXCOMM7_MASK)

#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_NPU_MASK (0x30000000U)
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_NPU_SHIFT (28U)
/*! NPU - NPU
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_NPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_NPU_SHIFT)) & AHBSC0_AHB_PERIPHERAL1_SLAVE_RULE_NPU_MASK)
/*! @} */

/*! @name AIPS1_BRIDGE_GROUP0_MEM_RULE0 - AIPS1 Bridge Group 0 Memory Rule Register 0 */
/*! @{ */

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_MP_MASK (0x3U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_MP_SHIFT (0U)
/*! eDMA0_MP - eDMA0 management
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_MP_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_MP_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH0_MASK (0x30U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH0_SHIFT (4U)
/*! eDMA0_CH0 - eDMA0 channel 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH0_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH0_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH1_MASK (0x300U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH1_SHIFT (8U)
/*! eDMA0_CH1 - eDMA0 channel 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH1_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH1_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH2_MASK (0x3000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH2_SHIFT (12U)
/*! eDMA0_CH2 - eDMA0 channel 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH2_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH2_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH3_MASK (0x30000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH3_SHIFT (16U)
/*! eDMA0_CH3 - eDMA0 channel 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH3_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH3_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH4_MASK (0x300000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH4_SHIFT (20U)
/*! eDMA0_CH4 - eDMA0 channel 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH4_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH4_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH5_MASK (0x3000000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH5_SHIFT (24U)
/*! eDMA0_CH5 - eDMA0 channel 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH5_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH5_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH6_MASK (0x30000000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH6_SHIFT (28U)
/*! eDMA0_CH6 - eDMA0 channel 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH6_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE0_eDMA0_CH6_MASK)
/*! @} */

/*! @name AIPS1_BRIDGE_GROUP0_MEM_RULE1 - AIPS1 Bridge Group 0 Memory Rule Register 1 */
/*! @{ */

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH7_MASK (0x3U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH7_SHIFT (0U)
/*! eDMA0_CH7 - eDMA0 channel 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH7_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH7_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH8_MASK (0x30U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH8_SHIFT (4U)
/*! eDMA0_CH8 - eDMA0 channel 8
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH8_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH8_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH9_MASK (0x300U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH9_SHIFT (8U)
/*! eDMA0_CH9 - eDMA0 channel
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH9_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH9_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH10_MASK (0x3000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH10_SHIFT (12U)
/*! eDMA0_CH10 - eDMA0 channel 10
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH10_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH10_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA_CH11_MASK (0x30000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA_CH11_SHIFT (16U)
/*! eDMA_CH11 - eDMA0 channel 11
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA_CH11_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA_CH11_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH12_MASK (0x300000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH12_SHIFT (20U)
/*! eDMA0_CH12 - eDMA0 channel 12
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH12_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH12_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH13_MASK (0x3000000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH13_SHIFT (24U)
/*! eDMA0_CH13 - eDMA0 channel 13
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH13_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH13_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH14_MASK (0x30000000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH14_SHIFT (28U)
/*! eDMA0_CH14 - DMA0 channel 14
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH14_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE1_eDMA0_CH14_MASK)
/*! @} */

/*! @name AIPS1_BRIDGE_GROUP0_MEM_RULE2 - AIPS1 Bridge Group 0 Memory Rule Register 2 */
/*! @{ */

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_eDMA0_CH15_MASK (0x3U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_eDMA0_CH15_SHIFT (0U)
/*! eDMA0_CH15 - eDMA0 channel 15
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_eDMA0_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_eDMA0_CH15_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_eDMA0_CH15_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_CRC_MASK (0x30U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_CRC_SHIFT (4U)
/*! CRC - CRC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_CRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_CRC_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_CRC_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI0_MASK (0x300U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI0_SHIFT (8U)
/*! SAI0 - SAI0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI0_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI0_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI1_MASK (0x3000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI1_SHIFT (12U)
/*! SAI1 - SAI1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI1_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI1_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI2_MASK (0x30000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI2_SHIFT (16U)
/*! SAI2 - SAI2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI2_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP0_MEM_RULE2_SAI2_MASK)
/*! @} */

/*! @name AIPS1_BRIDGE_GROUP1_MEM_RULE0 - AIPS1 Bridge Group 1 Memory Rule Register 0 */
/*! @{ */

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_MP_MASK (0x3U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_MP_SHIFT (0U)
/*! DMA_1_MP - DMA1 management
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_MP_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_MP_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH0_MASK (0x30U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH0_SHIFT (4U)
/*! DMA_1_CH0 - DMA1 channel 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH0_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH0_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH1_MASK (0x300U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH1_SHIFT (8U)
/*! DMA_1_CH1 - DMA1 channel 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH1_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH1_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH2_MASK (0x3000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH2_SHIFT (12U)
/*! DMA_1_CH2 - DMA1 channel 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH2_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH2_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH3_MASK (0x30000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH3_SHIFT (16U)
/*! DMA_1_CH3 - DMA1 channel 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH3_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH3_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH4_MASK (0x300000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH4_SHIFT (20U)
/*! DMA_1_CH4 - DMA1 channel 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH4_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH4_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH5_MASK (0x3000000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH5_SHIFT (24U)
/*! DMA_1_CH5 - DMA1 channel 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH5_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH5_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH6_MASK (0x30000000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH6_SHIFT (28U)
/*! DMA_1_CH6 - DMA1 channel 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH6_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE0_DMA_1_CH6_MASK)
/*! @} */

/*! @name AIPS1_BRIDGE_GROUP1_MEM_RULE1 - AIPS1 Bridge Group 1 Memory Rule Register 1 */
/*! @{ */

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH7_MASK (0x3U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH7_SHIFT (0U)
/*! DMA_1_CH7 - DMA1 channel 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH7_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH7_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH8_MASK (0x30U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH8_SHIFT (4U)
/*! DMA_1_CH8 - DMA1 channel 8
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH8_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH8_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH9_MASK (0x300U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH9_SHIFT (8U)
/*! DMA_1_CH9 - DMA1 channel 9
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH9_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH9_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH10_MASK (0x3000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH10_SHIFT (12U)
/*! DMA_1_CH10 - DMA1 channel 10
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH10_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH10_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH11_MASK (0x30000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH11_SHIFT (16U)
/*! DMA_1_CH11 - DMA1 channel 11
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH11_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH11_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH12_MASK (0x300000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH12_SHIFT (20U)
/*! DMA_1_CH12 - DMA1 channel 12
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH12_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH12_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH13_MASK (0x3000000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH13_SHIFT (24U)
/*! DMA_1_CH13 - DMA1 channel 13
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH13_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH13_MASK)

#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH14_MASK (0x30000000U)
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH14_SHIFT (28U)
/*! DMA_1_CH14 - DMA1 channel 14
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH14_SHIFT)) & AHBSC0_AIPS1_BRIDGE_GROUP1_MEM_RULE1_DMA_1_CH14_MASK)
/*! @} */

/*! @name AHB_SECURE_CTRL_PERIPHERAL_RULE0 - AHB Secure Control Peripheral Rule 0 */
/*! @{ */

#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK (0x3U)
#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT)) & AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK)

#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK (0x30U)
#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT)) & AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK)

#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK (0x300U)
#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT)) & AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK)

#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK (0x3000U)
#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT)) & AHBSC0_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL2_SLAVE_RULE0 - AHB Peripheral 2 Slave Rule Register 0 */
/*! @{ */

#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_DEBUG_MAILBOX_MASK (0x300U)
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_DEBUG_MAILBOX_SHIFT (8U)
/*! DEBUG_MAILBOX - sw debug mailbox
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_DEBUG_MAILBOX_SHIFT)) & AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_DEBUG_MAILBOX_MASK)

#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM8_MASK (0x3000U)
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM8_SHIFT (12U)
/*! FLEXCOMM8 - FLEXCOMM8
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM8_SHIFT)) & AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM8_MASK)

#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM9_MASK (0x30000U)
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM9_SHIFT (16U)
/*! FLEXCOMM9 - FLEXCOMM9
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM9_SHIFT)) & AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM9_MASK)

#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM10_MASK (0x300000U)
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM10_SHIFT (20U)
/*! FLEXCOMM10 - FLEXCOMM10
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM10_SHIFT)) & AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM10_MASK)

#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM11_MASK (0x3000000U)
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM11_SHIFT (24U)
/*! FLEXCOMM11 - FLEXCOMM11
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM11_SHIFT)) & AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM11_MASK)

#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM12_MASK (0x30000000U)
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM12_SHIFT (28U)
/*! FLEXCOMM12 - FLEXCOMM12
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM12_SHIFT)) & AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE0_FLEXCOMM12_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL2_SLAVE_RULE1 - AHB Peripheral 2 Slave Rule Register 1 */
/*! @{ */

#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE1_FLEXCOMM13_MASK (0x3U)
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE1_FLEXCOMM13_SHIFT (0U)
/*! FLEXCOMM13 - FLEXCOMM13
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE1_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE1_FLEXCOMM13_SHIFT)) & AHBSC0_AHB_PERIPHERAL2_SLAVE_RULE1_FLEXCOMM13_MASK)
/*! @} */

/*! @name AIPS0_BRIDGE_GROUP0_MEM_RULE0 - AIPS0 Bridge Group 0 Memory Rule Register 0 */
/*! @{ */

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI0_MASK (0x30000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI0_SHIFT (16U)
/*! XSPI0 - XSPI0 register
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI0_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI0_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI1_MASK (0x300000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI1_SHIFT (20U)
/*! XSPI1 - XSPI1 register
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI1_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_XSPI1_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_TRNG_MASK (0x30000000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_TRNG_SHIFT (28U)
/*! TRNG - TRNG
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_TRNG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_TRNG_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE0_TRNG_MASK)
/*! @} */

/*! @name AIPS0_BRIDGE_GROUP0_MEM_RULE1 - AIPS0 Bridge Group 0 Memory Rule Register 1 */
/*! @{ */

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_B_MASK (0x3U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_B_SHIFT (0U)
/*! MU4_B - MU4_B
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_B(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_B_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_B_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_A_MASK (0x30U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_A_SHIFT (4U)
/*! MU4_A - MU4_A
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_A(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_A_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_MU4_A_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_SEMA42_4_MASK (0x300U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_SEMA42_4_SHIFT (8U)
/*! SEMA42_4 - SEMA42_4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_SEMA42_4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_SEMA42_4_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_SEMA42_4_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON0_MASK (0x30000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON0_SHIFT (16U)
/*! CMX_PERFMON0 - CMX_PERFMON
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON0_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON0_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON1_MASK (0x300000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON1_SHIFT (20U)
/*! CMX_PERFMON1 - CMX_PERFMON1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON1_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON1_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON2_MASK (0x3000000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON2_SHIFT (24U)
/*! CMX_PERFMON2 - CMX_PERFMON2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON2_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON2_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON3_MASK (0x30000000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON3_SHIFT (28U)
/*! CMX_PERFMON3 - CMX_PERFMON3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON3_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP0_MEM_RULE1_CMX_PERFMON3_MASK)
/*! @} */

/*! @name AIPS0_BRIDGE_GROUP1_MEM_RULE0 - AIPS0 Bridge Group 1 Memory Rule Register 0 */
/*! @{ */

#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_MASK (0x3U)
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_SHIFT (0U)
/*! ELS - ELS
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS1_MASK (0x30U)
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS1_SHIFT (4U)
/*! ELS_ALIAS1 - ELS_ALIAS1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS1_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS1_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS2_MASK (0x300U)
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS2_SHIFT (8U)
/*! ELS_ALIAS2 - ELS_ALIAS2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS2_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS2_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS3_MASK (0x3000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS3_SHIFT (12U)
/*! ELS_ALIAS3 - ELS_ALIAS3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS3_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_ELS_ALIAS3_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_MASK (0x30000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_SHIFT (16U)
/*! PUF - PUF
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS1_MASK (0x300000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS1_SHIFT (20U)
/*! PUF_ALIAS1 - PUF_ALIAS1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS1_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS1_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS2_MASK (0x3000000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS2_SHIFT (24U)
/*! PUF_ALIAS2 - PUF_ALIAS2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS2_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS2_MASK)

#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS3_MASK (0x30000000U)
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS3_SHIFT (28U)
/*! PUF_ALIAS3 - PUF_ALIAS3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS3_SHIFT)) & AHBSC0_AIPS0_BRIDGE_GROUP1_MEM_RULE0_PUF_ALIAS3_MASK)
/*! @} */

/*! @name APB_SLAVE_GROUP0_RULE0 - APB Bridge Peripheral 0 Rule 0 */
/*! @{ */

#define AHBSC0_APB_SLAVE_GROUP0_RULE0_RSTCTL0_MASK (0x3U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_RSTCTL0_SHIFT (0U)
/*! RSTCTL0 - RSTCTL0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_RSTCTL0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE0_RSTCTL0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE0_RSTCTL0_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE0_CLKCTL0_MASK (0x30U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_CLKCTL0_SHIFT (4U)
/*! CLKCTL0 - CLKCTL0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_CLKCTL0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE0_CLKCTL0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE0_CLKCTL0_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE0_SYSCON0_MASK (0x300U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_SYSCON0_SHIFT (8U)
/*! SYSCON0 - SYSCON
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_SYSCON0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE0_SYSCON0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE0_SYSCON0_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE0_SLEEPCON0_MASK (0x3000U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_SLEEPCON0_SHIFT (12U)
/*! SLEEPCON0 - SLEEPCON0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_SLEEPCON0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE0_SLEEPCON0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE0_SLEEPCON0_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE0_IOCON0_MASK (0x30000U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_IOCON0_SHIFT (16U)
/*! IOCON0 - IOCON0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_IOCON0(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE0_IOCON0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE0_IOCON0_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE0_PVTS0_MASK (0x300000U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_PVTS0_SHIFT (20U)
/*! PVTS0 - PVTS0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE0_PVTS0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE0_PVTS0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE0_PVTS0_MASK)
/*! @} */

/*! @name APB_SLAVE_GROUP0_RULE1 - APB Bridge Peripheral 0 Rule Register 1 */
/*! @{ */

#define AHBSC0_APB_SLAVE_GROUP0_RULE1_WWDT0_MASK (0x3000000U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE1_WWDT0_SHIFT (24U)
/*! WWDT0 - WWDT0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE1_WWDT0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE1_WWDT0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE1_WWDT0_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE1_UTICK0_MASK (0x30000000U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE1_UTICK0_SHIFT (28U)
/*! UTICK0 - UTICK0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE1_UTICK0(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE1_UTICK0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE1_UTICK0_MASK)
/*! @} */

/*! @name APB_SLAVE_GROUP0_RULE2 - APB Bridge Peripheral 0 Rule Register 2 */
/*! @{ */

#define AHBSC0_APB_SLAVE_GROUP0_RULE2_PKC_MASK   (0x30U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE2_PKC_SHIFT  (4U)
/*! PKC - PKC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE2_PKC(x)     (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE2_PKC_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE2_PKC_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE2_ITRC_MASK  (0x300U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE2_ITRC_SHIFT (8U)
/*! ITRC - ITRC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE2_ITRC(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE2_ITRC_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE2_ITRC_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET0_MASK (0x3000U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET0_SHIFT (12U)
/*! GDET0 - GDET0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET0_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET1_MASK (0x30000U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET1_SHIFT (16U)
/*! GDET1 - GDET1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET1_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE2_GDET1_MASK)
/*! @} */

/*! @name APB_SLAVE_GROUP0_RULE3 - APB Bridge Peripheral 0 Rule Register 3 */
/*! @{ */

#define AHBSC0_APB_SLAVE_GROUP0_RULE3_OCOTP_MASK (0x3U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE3_OCOTP_SHIFT (0U)
/*! OCOTP - OCOTP
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE3_OCOTP(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE3_OCOTP_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE3_OCOTP_MASK)

#define AHBSC0_APB_SLAVE_GROUP0_RULE3_SAFO_SGI_MASK (0x300U)
#define AHBSC0_APB_SLAVE_GROUP0_RULE3_SAFO_SGI_SHIFT (8U)
/*! SAFO_SGI - SAFO_SGI
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP0_RULE3_SAFO_SGI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP0_RULE3_SAFO_SGI_SHIFT)) & AHBSC0_APB_SLAVE_GROUP0_RULE3_SAFO_SGI_MASK)
/*! @} */

/*! @name APB_SLAVE_GROUP1_RULE0 - APB Bridge Peripheral 1 Rule Register 0 */
/*! @{ */

#define AHBSC0_APB_SLAVE_GROUP1_RULE0_FREQME_MASK (0x3000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE0_FREQME_SHIFT (12U)
/*! FREQME - FREQME
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE0_FREQME(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE0_FREQME_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE0_FREQME_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE0_PINT0_MASK (0x300000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE0_PINT0_SHIFT (20U)
/*! PINT0 - PINT0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE0_PINT0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE0_PINT0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE0_PINT0_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE0_INPUTMUX0_MASK (0x3000000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE0_INPUTMUX0_SHIFT (24U)
/*! INPUTMUX0 - INPUTMUX0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE0_INPUTMUX0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE0_INPUTMUX0_MASK)
/*! @} */

/*! @name APB_SLAVE_GROUP1_RULE1 - APB Bridge Peripheral 1 Rule Register 1 */
/*! @{ */

#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER0_MASK (0x3U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER0_SHIFT (0U)
/*! CTIMER0 - CTIMER0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER0_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER1_MASK (0x30U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER1_SHIFT (4U)
/*! CTIMER1 - CTIMER1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER1_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER1_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER2_MASK (0x300U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER2_SHIFT (8U)
/*! CTIMER2 - CTIMER2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER2_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER2_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER3_MASK (0x3000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER3_SHIFT (12U)
/*! CTIMER3 - CTIMER3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER3_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER3_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER4_MASK (0x30000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER4_SHIFT (16U)
/*! CTIMER4 - CTIMER4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER4_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE1_CTIMER4_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE1_MRT0_MASK  (0x300000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_MRT0_SHIFT (20U)
/*! MRT0 - MRT0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_MRT0(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE1_MRT0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE1_MRT0_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE1_WWDT1_MASK (0x3000000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_WWDT1_SHIFT (24U)
/*! WWDT1 - WWDT1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE1_WWDT1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE1_WWDT1_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE1_WWDT1_MASK)
/*! @} */

/*! @name APB_SLAVE_GROUP1_RULE2 - APB Bridge Peripheral 1 Rule 2 Register */
/*! @{ */

#define AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU0_MASK  (0x3U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU0_SHIFT (0U)
/*! MMU0 - MMU0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU0(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU0_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU1_MASK  (0x30U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU1_SHIFT (4U)
/*! MMU1 - MMU1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU1(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU1_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE2_MMU1_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE0_MASK (0x3000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE0_SHIFT (12U)
/*! XCACHE0 - Cache Control 0 Registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE0_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE1_MASK (0x30000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE1_SHIFT (16U)
/*! XCACHE1 - Cache Control 1 Registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE1_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE1_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE2_MASK (0x300000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE2_SHIFT (20U)
/*! XCACHE2 - Cache Control 2 Registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE2_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE2_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE3_MASK (0x3000000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE3_SHIFT (24U)
/*! XCACHE3 - Cache Control 3 Registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE3_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE2_XCACHE3_MASK)

#define AHBSC0_APB_SLAVE_GROUP1_RULE2_I3C0_MASK  (0x30000000U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_I3C0_SHIFT (28U)
/*! I3C0 - I3C0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE2_I3C0(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE2_I3C0_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE2_I3C0_MASK)
/*! @} */

/*! @name APB_SLAVE_GROUP1_RULE3 - APB Bridge Peripheral 1 Rule 3 Register */
/*! @{ */

#define AHBSC0_APB_SLAVE_GROUP1_RULE3_I3C1_MASK  (0x3U)
#define AHBSC0_APB_SLAVE_GROUP1_RULE3_I3C1_SHIFT (0U)
/*! I3C1 - I3C1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_APB_SLAVE_GROUP1_RULE3_I3C1(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_APB_SLAVE_GROUP1_RULE3_I3C1_SHIFT)) & AHBSC0_APB_SLAVE_GROUP1_RULE3_I3C1_MASK)
/*! @} */

/*! @name SHARED_APB_SLAVE_GROUP0_RULE0 - Shared APB Bridge Peripheral 0 Rule 0 */
/*! @{ */

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3_MASK (0x3U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3_SHIFT (0U)
/*! RSTCTL3 - RSTCTL3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3_MASK (0x30U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3_SHIFT (4U)
/*! CLKCTL3 - CLKCTL3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3_MASK (0x300U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3_SHIFT (8U)
/*! SYSCON3 - SYSCON3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP_MASK (0x3000U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP_SHIFT (12U)
/*! OSC32KNP - OSC32KNP
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1_MASK (0x30000U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1_SHIFT (16U)
/*! IOPCTL1 - IOPCTL1 for sense domain
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2_MASK (0x300000U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2_SHIFT (20U)
/*! CLKCTL2 - Clock for common VDDN
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2_MASK (0x3000000U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2_SHIFT (24U)
/*! SYSCON2 - SYSCON2 for common VDDN
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2_MASK (0x30000000U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2_SHIFT (28U)
/*! RSTCTL2 - RSTCTL2 for common VDDN
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2_MASK)
/*! @} */

/*! @name SHARED_APB_SLAVE_GROUP0_RULE1 - Shared APB Bridge Peripheral 0 Rule 1 */
/*! @{ */

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC0_MASK (0x3U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC0_SHIFT (0U)
/*! RTC0 - RTC0 (compute domain)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC0_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC0_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC1_MASK (0x30U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC1_SHIFT (4U)
/*! RTC1 - RTC1 (sense domain)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC1_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_RTC1_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2_MASK (0x300U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2_SHIFT (8U)
/*! GDET2 - GDET2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2_MASK)

#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3_MASK (0x3000U)
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3_SHIFT (12U)
/*! GDET3 - GDET3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3_SHIFT)) & AHBSC0_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3_MASK)
/*! @} */

/*! @name AIPS2_BRIDGE_GROUP0_MEM_RULE0 - AIPS2 Bridge Group 0 Memory Rule Register 0 */
/*! @{ */

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_A_MASK (0x3U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_A_SHIFT (0U)
/*! MU0_A - MU0_A (M33 port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_A(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_A_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_A_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_A_MASK (0x300U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_A_SHIFT (8U)
/*! MU1_A - MU1_A (M33 port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_A(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_A_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_A_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_A_MASK (0x30000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_A_SHIFT (16U)
/*! MU2_A - MU2_A (HIFI4 port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_A(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_A_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_A_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEMA42_0_MASK (0x3000000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEMA42_0_SHIFT (24U)
/*! SEMA42_0 - SEMA42_0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEMA42_0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEMA42_0_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEMA42_0_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_OSTIMER_MASK (0x30000000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_OSTIMER_SHIFT (28U)
/*! OSTIMER - OSTIMER (M33 port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_OSTIMER_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE0_OSTIMER_MASK)
/*! @} */

/*! @name AIPS2_BRIDGE_GROUP0_MEM_RULE1 - AIPS2 Bridge Group 0 Memory Rule Register 1 */
/*! @{ */

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS1_MASK (0x3U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS1_SHIFT (0U)
/*! OSTIMER_ALIAS1 - OSTIMER ALIAS1 (HIFI4 port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS1_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS1_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0_MASK (0x3000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0_SHIFT (12U)
/*! ACMP0 - ACMP0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0_MASK (0x30000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0_SHIFT (16U)
/*! ADC0 - ADC0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC_MASK (0x300000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC_SHIFT (20U)
/*! SDADC - SDADC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL_MASK (0x3000000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL_SHIFT (24U)
/*! MICFIL - MICFIL
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL_MASK)

#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_PMC0_MASK (0x30000000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_PMC0_SHIFT (28U)
/*! PMC0 - PMC0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_PMC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_PMC0_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP0_MEM_RULE1_PMC0_MASK)
/*! @} */

/*! @name AIPS2_BRIDGE_GROUP1_MEM_RULE0 - AIPS2 Bridge Group 1 Memory Rule Register 0 */
/*! @{ */

#define AHBSC0_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15_MASK (0x3000U)
#define AHBSC0_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15_SHIFT (12U)
/*! LPI2C15 - LPI2C15
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15_SHIFT)) & AHBSC0_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15_MASK)
/*! @} */

/*! @name AHB_SECURE_CTRL_SENSE_RULE0 - Sense Domain AHB Secure Control Peripheral Rule 0 */
/*! @{ */

#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE0_MASK (0x3U)
#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE0_SHIFT)) & AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE0_MASK)

#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE1_MASK (0x30U)
#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE1_SHIFT)) & AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE1_MASK)

#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE2_MASK (0x300U)
#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE2_SHIFT)) & AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE2_MASK)

#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE3_MASK (0x3000U)
#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE3_SHIFT)) & AHBSC0_AHB_SECURE_CTRL_SENSE_RULE0_RULE3_MASK)
/*! @} */

/*! @name MEDIA_AHB_PERIPHERAL_SLAVE_RULE0 - MEDIA domain AHB peripheral slave */
/*! @{ */

#define AHBSC0_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL_MASK (0x3U)
#define AHBSC0_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL_SHIFT (0U)
/*! MEDIA_AHB_PERIPHERAL - MEDIA domain AHB Peripheral Slave Rule Register
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL_SHIFT)) & AHBSC0_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL_MASK)
/*! @} */

/*! @name MEDIA_APB_PERIPHERAL_SLAVE_RULE0 - MEDIA domain APB peripheral slave Rule Register */
/*! @{ */

#define AHBSC0_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL_MASK (0x3U)
#define AHBSC0_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL_SHIFT (0U)
/*! MEDIA_APB_PERIPHERAL - MEDIA domain APB Peripheral Slave
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL_SHIFT)) & AHBSC0_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL_MASK)
/*! @} */

/*! @name EZHV_SRAM_RULE0 - EZHV SRAM Memory Rule Register */
/*! @{ */

#define AHBSC0_EZHV_SRAM_RULE0_EZHV_SRAM_MASK    (0x3U)
#define AHBSC0_EZHV_SRAM_RULE0_EZHV_SRAM_SHIFT   (0U)
/*! EZHV_SRAM - EZHV SRAM
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC0_EZHV_SRAM_RULE0_EZHV_SRAM(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC0_EZHV_SRAM_RULE0_EZHV_SRAM_SHIFT)) & AHBSC0_EZHV_SRAM_RULE0_EZHV_SRAM_MASK)
/*! @} */

/*! @name SEC_VIO_ADDR - Security Violation Address */
/*! @{ */

#define AHBSC0_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK    (0xFFFFFFFFU)
#define AHBSC0_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT   (0U)
/*! SEC_VIO_ADDR - Security violation address for AHB layer a reset value 0 */
#define AHBSC0_SEC_VIO_ADDR_SEC_VIO_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHBSC0_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
/*! @} */

/* The count of AHBSC0_SEC_VIO_ADDR */
#define AHBSC0_SEC_VIO_ADDR_COUNT                (29U)

/*! @name SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */
/*! @{ */

#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator
 *  0b0..Read access
 *  0b1..Write access
 */
#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)

#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access
 *  0b0..Code
 *  0b1..Data
 */
#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)

#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level */
#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)

#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0x1F00U)
#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
/*! SEC_VIO_INFO_MASTER - Security violation master number
 *  0b00000..CPU0 System
 *  0b00001..eDMA0
 *  0b00010..eDMA1
 *  0b00011..ELS
 *  0b00100..HIFI4
 *  0b00101..CPU1 system
 *  0b00110..eDMA2
 *  0b00111..eDMA3
 *  0b01000..HIFI1
 *  0b01001..EZH-V
 *  0b01010..PKC
 *  0b01011..USDHC0
 *  0b01100..USB0
 *  0b01101..GPU
 *  0b01110..ETR
 *  0b01111..DAP
 *  0b10000..CPU0 Code
 *  0b10001..Reserved
 *  0b10010..Reserved
 *  0b10011..Reserved
 *  0b10100..Reserved
 *  0b10101..CPU1 code
 *  0b10110..JPEGDEC
 *  0b10111..PNGDEC
 *  0b11000..Reserved
 *  0b11001..Reserved
 *  0b11010..Reserved
 *  0b11011..USDHC1
 *  0b11100..USB1
 *  0b11101..LCDIF
 *  0b11111..Test port
 */
#define AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHBSC0_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
/*! @} */

/* The count of AHBSC0_SEC_VIO_MISC_INFO */
#define AHBSC0_SEC_VIO_MISC_INFO_COUNT           (29U)

/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */
/*! @{ */

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U)
/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U)
/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U)
/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U)
/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U)
/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U)
/*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U)
/*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID19_MASK (0x80000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID19_SHIFT (19U)
/*! VIO_INFO_VALID19 - Violation information valid flag for AHB port 19
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID19(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID19_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID19_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID20_MASK (0x100000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID20_SHIFT (20U)
/*! VIO_INFO_VALID20 - Violation information valid flag for AHB port 20
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID20(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID20_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID20_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID21_MASK (0x200000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID21_SHIFT (21U)
/*! VIO_INFO_VALID21 - Violation information valid flag for AHB port 21
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID21(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID21_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID21_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID22_MASK (0x400000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID22_SHIFT (22U)
/*! VIO_INFO_VALID22 - Violation information valid flag for AHB port 22
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID22(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID22_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID22_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID23_MASK (0x800000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID23_SHIFT (23U)
/*! VIO_INFO_VALID23 - Violation information valid flag for AHB port 23
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID23(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID23_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID23_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID24_MASK (0x1000000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID24_SHIFT (24U)
/*! VIO_INFO_VALID24 - Violation information valid flag for AHB port 24
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID24(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID24_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID24_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID25_MASK (0x2000000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID25_SHIFT (25U)
/*! VIO_INFO_VALID25 - Violation information valid flag for AHB port 25
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID25(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID25_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID25_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID26_MASK (0x4000000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID26_SHIFT (26U)
/*! VIO_INFO_VALID26 - Violation information valid flag for AHB port 26
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID26(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID26_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID26_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID27_MASK (0x8000000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID27_SHIFT (27U)
/*! VIO_INFO_VALID27 - Violation information valid flag for AHB port 27
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID27(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID27_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID27_MASK)

#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID28_MASK (0x10000000U)
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID28_SHIFT (28U)
/*! VIO_INFO_VALID28 - Violation information valid flag for AHB port 28
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID28(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID28_SHIFT)) & AHBSC0_SEC_VIO_INFO_VALID_VIO_INFO_VALID28_MASK)
/*! @} */

/*! @name COMPUTE_ARB0RAM_ACCESS_ENABLE - Access enable for COMPUTE domain masters to RAM partitions. */
/*! @{ */

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK (0x1000U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT (12U)
/*! RAM_PARTITION_12_ACCESS_EN - Enable access to the Shared RAM partition 12
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK (0x2000U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT (13U)
/*! RAM_PARTITION_13_ACCESS_EN - Enable access to the Shared RAM partition 13
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK (0x4000U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT (14U)
/*! RAM_PARTITION_14_ACCESS_EN - Enable access to the Shared RAM partition 14
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK (0x8000U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT (15U)
/*! RAM_PARTITION_15_ACCESS_EN - Enable access to the Shared RAM partition 15
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK (0x10000U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT (16U)
/*! RAM_PARTITION_16_ACCESS_EN - Enable access to the Shared RAM partition 16
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK)

#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK (0x20000U)
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT (17U)
/*! RAM_PARTITION_17_ACCESS_EN - Enable access to the Shared RAM partition 17
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT)) & AHBSC0_COMPUTE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK)
/*! @} */

/*! @name SENSE_ARB0RAM_ACCESS_ENABLE - Access enable for SENSE domain masters to RAM partitions. */
/*! @{ */

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK (0x1000U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT (12U)
/*! RAM_PARTITION_12_ACCESS_EN - Enable access to the Shared RAM partition 12
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK (0x2000U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT (13U)
/*! RAM_PARTITION_13_ACCESS_EN - Enable access to the Shared RAM partition 13
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK (0x4000U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT (14U)
/*! RAM_PARTITION_14_ACCESS_EN - Enable access to the Shared RAM partition 14
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK (0x8000U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT (15U)
/*! RAM_PARTITION_15_ACCESS_EN - Enable access to the Shared RAM partition 15
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK (0x10000U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT (16U)
/*! RAM_PARTITION_16_ACCESS_EN - Enable access to the Shared RAM partition 16
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK)

#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK (0x20000U)
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT (17U)
/*! RAM_PARTITION_17_ACCESS_EN - Enable access to the Shared RAM partition 17
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT)) & AHBSC0_SENSE_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK)
/*! @} */

/*! @name MEDIA_ARB0RAM_ACCESS_ENABLE - Access enable for MEDIA domain masters to RAM partitions. */
/*! @{ */

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK (0x1000U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT (12U)
/*! RAM_PARTITION_12_ACCESS_EN - Enable access to the Shared RAM partition 12
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK (0x2000U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT (13U)
/*! RAM_PARTITION_13_ACCESS_EN - Enable access to the Shared RAM partition 13
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK (0x4000U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT (14U)
/*! RAM_PARTITION_14_ACCESS_EN - Enable access to the Shared RAM partition 14
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK (0x8000U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT (15U)
/*! RAM_PARTITION_15_ACCESS_EN - Enable access to the Shared RAM partition 15
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK (0x10000U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT (16U)
/*! RAM_PARTITION_16_ACCESS_EN - Enable access to the Shared RAM partition 16
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK)

#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK (0x20000U)
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT (17U)
/*! RAM_PARTITION_17_ACCESS_EN - Enable access to the Shared RAM partition 17
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT)) & AHBSC0_MEDIA_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK)
/*! @} */

/*! @name NPU_ARB0RAM_ACCESS_ENABLE - Access enable for NPU domain masters to RAM partitions. */
/*! @{ */

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK (0x1000U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT (12U)
/*! RAM_PARTITION_12_ACCESS_EN - Enable access to the Shared RAM partition 12
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK (0x2000U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT (13U)
/*! RAM_PARTITION_13_ACCESS_EN - Enable access to the Shared RAM partition 13
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK (0x4000U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT (14U)
/*! RAM_PARTITION_14_ACCESS_EN - Enable access to the Shared RAM partition 14
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK (0x8000U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT (15U)
/*! RAM_PARTITION_15_ACCESS_EN - Enable access to the Shared RAM partition 15
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK (0x10000U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT (16U)
/*! RAM_PARTITION_16_ACCESS_EN - Enable access to the Shared RAM partition 16
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK)

#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK (0x20000U)
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT (17U)
/*! RAM_PARTITION_17_ACCESS_EN - Enable access to the Shared RAM partition 17
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT)) & AHBSC0_NPU_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK)
/*! @} */

/*! @name HIFI4_ARB0RAM_ACCESS_ENABLE - Access enable for HIFI4 to RAM partitions. */
/*! @{ */

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK (0x1000U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT (12U)
/*! RAM_PARTITION_12_ACCESS_EN - Enable access to the Shared RAM partition 12
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_12_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK (0x2000U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT (13U)
/*! RAM_PARTITION_13_ACCESS_EN - Enable access to the Shared RAM partition 13
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_13_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK (0x4000U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT (14U)
/*! RAM_PARTITION_14_ACCESS_EN - Enable access to the Shared RAM partition 14
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_14_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK (0x8000U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT (15U)
/*! RAM_PARTITION_15_ACCESS_EN - Enable access to the Shared RAM partition 15
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_15_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK (0x10000U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT (16U)
/*! RAM_PARTITION_16_ACCESS_EN - Enable access to the Shared RAM partition 16
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_16_ACCESS_EN_MASK)

#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK (0x20000U)
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT (17U)
/*! RAM_PARTITION_17_ACCESS_EN - Enable access to the Shared RAM partition 17
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_SHIFT)) & AHBSC0_HIFI4_ARB0RAM_ACCESS_ENABLE_RAM_PARTITION_17_ACCESS_EN_MASK)
/*! @} */

/*! @name MASTER_SEC_LEVEL - Master Secure Level */
/*! @{ */

#define AHBSC0_MASTER_SEC_LEVEL_HIFI4_MASK       (0x3U)
#define AHBSC0_MASTER_SEC_LEVEL_HIFI4_SHIFT      (0U)
/*! HIFI4 - HIFI4
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC0_MASTER_SEC_LEVEL_HIFI4(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_LEVEL_HIFI4_SHIFT)) & AHBSC0_MASTER_SEC_LEVEL_HIFI4_MASK)

#define AHBSC0_MASTER_SEC_LEVEL_MEDIA_MASK       (0xCU)
#define AHBSC0_MASTER_SEC_LEVEL_MEDIA_SHIFT      (2U)
/*! MEDIA - MEDIA
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC0_MASTER_SEC_LEVEL_MEDIA(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_LEVEL_MEDIA_SHIFT)) & AHBSC0_MASTER_SEC_LEVEL_MEDIA_MASK)

#define AHBSC0_MASTER_SEC_LEVEL_DMA0_MASK        (0x30U)
#define AHBSC0_MASTER_SEC_LEVEL_DMA0_SHIFT       (4U)
/*! DMA0 - DMA0
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC0_MASTER_SEC_LEVEL_DMA0(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_LEVEL_DMA0_SHIFT)) & AHBSC0_MASTER_SEC_LEVEL_DMA0_MASK)

#define AHBSC0_MASTER_SEC_LEVEL_DMA1_MASK        (0xC0U)
#define AHBSC0_MASTER_SEC_LEVEL_DMA1_SHIFT       (6U)
/*! DMA1 - DMA1
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC0_MASTER_SEC_LEVEL_DMA1(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_LEVEL_DMA1_SHIFT)) & AHBSC0_MASTER_SEC_LEVEL_DMA1_MASK)

#define AHBSC0_MASTER_SEC_LEVEL_PKC_MASK         (0x300U)
#define AHBSC0_MASTER_SEC_LEVEL_PKC_SHIFT        (8U)
/*! PKC - PKC
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC0_MASTER_SEC_LEVEL_PKC(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_LEVEL_PKC_SHIFT)) & AHBSC0_MASTER_SEC_LEVEL_PKC_MASK)

#define AHBSC0_MASTER_SEC_LEVEL_ETR_MASK         (0xC00U)
#define AHBSC0_MASTER_SEC_LEVEL_ETR_SHIFT        (10U)
/*! ETR - ETR
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC0_MASTER_SEC_LEVEL_ETR(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_LEVEL_ETR_SHIFT)) & AHBSC0_MASTER_SEC_LEVEL_ETR_MASK)
/*! @} */

/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */
/*! @{ */

#define AHBSC0_MASTER_SEC_ANTI_POL_REG_HIFI4_MASK (0x3U)
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_HIFI4_SHIFT (0U)
/*! HIFI4 - HIFI4
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_HIFI4(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_ANTI_POL_REG_HIFI4_SHIFT)) & AHBSC0_MASTER_SEC_ANTI_POL_REG_HIFI4_MASK)

#define AHBSC0_MASTER_SEC_ANTI_POL_REG_MEDIA_MASK (0xCU)
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_MEDIA_SHIFT (2U)
/*! MEDIA - MEDIA
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_MEDIA(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_ANTI_POL_REG_MEDIA_SHIFT)) & AHBSC0_MASTER_SEC_ANTI_POL_REG_MEDIA_MASK)

#define AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA0_MASK (0x30U)
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT (4U)
/*! DMA0 - DMA0
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT)) & AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA0_MASK)

#define AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA1_MASK (0xC0U)
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT (6U)
/*! DMA1 - DMA1
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT)) & AHBSC0_MASTER_SEC_ANTI_POL_REG_DMA1_MASK)

#define AHBSC0_MASTER_SEC_ANTI_POL_REG_PKC_MASK  (0x300U)
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT (8U)
/*! PKC - PKC
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_PKC(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & AHBSC0_MASTER_SEC_ANTI_POL_REG_PKC_MASK)

#define AHBSC0_MASTER_SEC_ANTI_POL_REG_ETR_MASK  (0xC00U)
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_ETR_SHIFT (10U)
/*! ETR - ETR
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC0_MASTER_SEC_ANTI_POL_REG_ETR(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_MASTER_SEC_ANTI_POL_REG_ETR_SHIFT)) & AHBSC0_MASTER_SEC_ANTI_POL_REG_ETR_MASK)
/*! @} */

/*! @name CPU0_LOCK_REG - Miscellaneous CPU0 Control Signals */
/*! @{ */

#define AHBSC0_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK   (0x3U)
#define AHBSC0_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT  (0U)
/*! LOCK_NS_VTOR - LOCK_NS_VTOR
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCKNSVTOR is 1
 *  0b10..CM33 (CPU0) LOCKNSVTOR is 0
 *  0b11..Reserved
 */
#define AHBSC0_CPU0_LOCK_REG_LOCK_NS_VTOR(x)     (((uint32_t)(((uint32_t)(x)) << AHBSC0_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC0_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)

#define AHBSC0_CPU0_LOCK_REG_LOCK_NS_MPU_MASK    (0xCU)
#define AHBSC0_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT   (2U)
/*! LOCK_NS_MPU - LOCK_NS_MPU
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCK_NS_MPU is 1
 *  0b10..CM33 (CPU0) LOCK_NS_MPU is 0
 *  0b11..Reserved
 */
#define AHBSC0_CPU0_LOCK_REG_LOCK_NS_MPU(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC0_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC0_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)

#define AHBSC0_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
#define AHBSC0_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
/*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1
 *  0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0
 *  0b11..Reserved
 */
#define AHBSC0_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHBSC0_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)

#define AHBSC0_CPU0_LOCK_REG_LOCK_S_MPU_MASK     (0xC0U)
#define AHBSC0_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT    (6U)
/*! LOCK_S_MPU - LOCK_S_MPU
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCK_S_MPU is 1
 *  0b10..CM33 (CPU0) LOCK_S_MPU is 0
 *  0b11..Reserved
 */
#define AHBSC0_CPU0_LOCK_REG_LOCK_S_MPU(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC0_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHBSC0_CPU0_LOCK_REG_LOCK_S_MPU_MASK)

#define AHBSC0_CPU0_LOCK_REG_LOCK_SAU_MASK       (0x300U)
#define AHBSC0_CPU0_LOCK_REG_LOCK_SAU_SHIFT      (8U)
/*! LOCK_SAU - LOCK_SAU
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCK_SAU is 1
 *  0b10..CM33 (CPU0) LOCK_SAU is 0
 *  0b11..Reserved
 */
#define AHBSC0_CPU0_LOCK_REG_LOCK_SAU(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC0_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHBSC0_CPU0_LOCK_REG_LOCK_SAU_MASK)
/*! @} */

/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */
/*! @{ */

#define AHBSC0_MISC_CTRL_DP_REG_WRITE_LOCK_MASK  (0x3U)
#define AHBSC0_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
/*! WRITE_LOCK - Write Lock
 *  0b00..Reserved
 *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
 *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_DP_REG_WRITE_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHBSC0_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)

#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC0_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)

#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC0_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)

#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC0_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)

#define AHBSC0_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define AHBSC0_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
 *  0b00..Reserved
 *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
 *        (interrupt request) will still be asserted and serviced by ISR.
 *  0b10..The violation detected by the secure checker will cause an abort.
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC0_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)

#define AHBSC0_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
#define AHBSC0_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U)
/*! DISABLE_STRICT_MODE - Disable Strict Mode
 *  0b00..AHB master in strict mode
 *  0b01..AHB master in tier mode. Can read and write to memories at same or below level.
 *  0b10..AHB master in strict mode
 *  0b11..AHB master in strict mode
 */
#define AHBSC0_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC0_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK)

#define AHBSC0_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
#define AHBSC0_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
/*! IDAU_ALL_NS - IDAU All Non-Secure
 *  0b00..Reserved
 *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
 *  0b10..IDAU is enabled (restrictive mode)
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_DP_REG_IDAU_ALL_NS(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHBSC0_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
/*! @} */

/*! @name MISC_CTRL_REG - Secure Control */
/*! @{ */

#define AHBSC0_MISC_CTRL_REG_WRITE_LOCK_MASK     (0x3U)
#define AHBSC0_MISC_CTRL_REG_WRITE_LOCK_SHIFT    (0U)
/*! WRITE_LOCK - Write Lock
 *  0b00..Reserved
 *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
 *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_REG_WRITE_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHBSC0_MISC_CTRL_REG_WRITE_LOCK_MASK)

#define AHBSC0_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define AHBSC0_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC0_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)

#define AHBSC0_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define AHBSC0_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC0_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)

#define AHBSC0_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define AHBSC0_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC0_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)

#define AHBSC0_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define AHBSC0_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
 *  0b00..Reserved
 *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
 *        (interrupt request) will still be asserted and serviced by ISR.
 *  0b10..The violation detected by the secure checker will cause an abort.
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC0_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)

#define AHBSC0_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
#define AHBSC0_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U)
/*! DISABLE_STRICT_MODE - Disable Strict Mode
 *  0b00..AHB master in strict mode
 *  0b01..AHB master in tier mode. Can read and write to memories at same or below level.
 *  0b10..AHB master in strict mode
 *  0b11..AHB master in strict mode
 */
#define AHBSC0_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC0_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK)

#define AHBSC0_MISC_CTRL_REG_IDAU_ALL_NS_MASK    (0xC000U)
#define AHBSC0_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT   (14U)
/*! IDAU_ALL_NS - IDAU All Non-Secure
 *  0b00..Reserved
 *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
 *  0b10..IDAU is enabled (restrictive mode)
 *  0b11..Reserved
 */
#define AHBSC0_MISC_CTRL_REG_IDAU_ALL_NS(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC0_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHBSC0_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AHBSC0_Register_Masks */


/* AHBSC0 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral AHBSC0 base address */
  #define AHBSC0_BASE                              (0x5017C000u)
  /** Peripheral AHBSC0 base address */
  #define AHBSC0_BASE_NS                           (0x4017C000u)
  /** Peripheral AHBSC0 base pointer */
  #define AHBSC0                                   ((AHBSC0_Type *)AHBSC0_BASE)
  /** Peripheral AHBSC0 base pointer */
  #define AHBSC0_NS                                ((AHBSC0_Type *)AHBSC0_BASE_NS)
  /** Peripheral AHBSC0_ALIAS1 base address */
  #define AHBSC0_ALIAS1_BASE                       (0x5017D000u)
  /** Peripheral AHBSC0_ALIAS1 base address */
  #define AHBSC0_ALIAS1_BASE_NS                    (0x4017D000u)
  /** Peripheral AHBSC0_ALIAS1 base pointer */
  #define AHBSC0_ALIAS1                            ((AHBSC0_Type *)AHBSC0_ALIAS1_BASE)
  /** Peripheral AHBSC0_ALIAS1 base pointer */
  #define AHBSC0_ALIAS1_NS                         ((AHBSC0_Type *)AHBSC0_ALIAS1_BASE_NS)
  /** Peripheral AHBSC0_ALIAS2 base address */
  #define AHBSC0_ALIAS2_BASE                       (0x5017E000u)
  /** Peripheral AHBSC0_ALIAS2 base address */
  #define AHBSC0_ALIAS2_BASE_NS                    (0x4017E000u)
  /** Peripheral AHBSC0_ALIAS2 base pointer */
  #define AHBSC0_ALIAS2                            ((AHBSC0_Type *)AHBSC0_ALIAS2_BASE)
  /** Peripheral AHBSC0_ALIAS2 base pointer */
  #define AHBSC0_ALIAS2_NS                         ((AHBSC0_Type *)AHBSC0_ALIAS2_BASE_NS)
  /** Peripheral AHBSC0_ALIAS3 base address */
  #define AHBSC0_ALIAS3_BASE                       (0x5017F000u)
  /** Peripheral AHBSC0_ALIAS3 base address */
  #define AHBSC0_ALIAS3_BASE_NS                    (0x4017F000u)
  /** Peripheral AHBSC0_ALIAS3 base pointer */
  #define AHBSC0_ALIAS3                            ((AHBSC0_Type *)AHBSC0_ALIAS3_BASE)
  /** Peripheral AHBSC0_ALIAS3 base pointer */
  #define AHBSC0_ALIAS3_NS                         ((AHBSC0_Type *)AHBSC0_ALIAS3_BASE_NS)
  /** Array initializer of AHBSC0 peripheral base addresses */
  #define AHBSC0_BASE_ADDRS                        { AHBSC0_BASE, AHBSC0_ALIAS1_BASE, AHBSC0_ALIAS2_BASE, AHBSC0_ALIAS3_BASE }
  /** Array initializer of AHBSC0 peripheral base pointers */
  #define AHBSC0_BASE_PTRS                         { AHBSC0, AHBSC0_ALIAS1, AHBSC0_ALIAS2, AHBSC0_ALIAS3 }
  /** Array initializer of AHBSC0 peripheral base addresses */
  #define AHBSC0_BASE_ADDRS_NS                     { AHBSC0_BASE_NS, AHBSC0_ALIAS1_BASE_NS, AHBSC0_ALIAS2_BASE_NS, AHBSC0_ALIAS3_BASE_NS }
  /** Array initializer of AHBSC0 peripheral base pointers */
  #define AHBSC0_BASE_PTRS_NS                      { AHBSC0_NS, AHBSC0_ALIAS1_NS, AHBSC0_ALIAS2_NS, AHBSC0_ALIAS3_NS }
#else
  /** Peripheral AHBSC0 base address */
  #define AHBSC0_BASE                              (0x4017C000u)
  /** Peripheral AHBSC0 base pointer */
  #define AHBSC0                                   ((AHBSC0_Type *)AHBSC0_BASE)
  /** Peripheral AHBSC0_ALIAS1 base address */
  #define AHBSC0_ALIAS1_BASE                       (0x4017D000u)
  /** Peripheral AHBSC0_ALIAS1 base pointer */
  #define AHBSC0_ALIAS1                            ((AHBSC0_Type *)AHBSC0_ALIAS1_BASE)
  /** Peripheral AHBSC0_ALIAS2 base address */
  #define AHBSC0_ALIAS2_BASE                       (0x4017E000u)
  /** Peripheral AHBSC0_ALIAS2 base pointer */
  #define AHBSC0_ALIAS2                            ((AHBSC0_Type *)AHBSC0_ALIAS2_BASE)
  /** Peripheral AHBSC0_ALIAS3 base address */
  #define AHBSC0_ALIAS3_BASE                       (0x4017F000u)
  /** Peripheral AHBSC0_ALIAS3 base pointer */
  #define AHBSC0_ALIAS3                            ((AHBSC0_Type *)AHBSC0_ALIAS3_BASE)
  /** Array initializer of AHBSC0 peripheral base addresses */
  #define AHBSC0_BASE_ADDRS                        { AHBSC0_BASE, AHBSC0_ALIAS1_BASE, AHBSC0_ALIAS2_BASE, AHBSC0_ALIAS3_BASE }
  /** Array initializer of AHBSC0 peripheral base pointers */
  #define AHBSC0_BASE_PTRS                         { AHBSC0, AHBSC0_ALIAS1, AHBSC0_ALIAS2, AHBSC0_ALIAS3 }
#endif

/*!
 * @}
 */ /* end of group AHBSC0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AHBSC3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AHBSC3_Peripheral_Access_Layer AHBSC3 Peripheral Access Layer
 * @{
 */

/** AHBSC3 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t SRAM_0_RULE[4];                    /**< RAM partition 0 Memory Rule Register, array offset: 0x10, array step: 0x4 */
  __IO uint32_t SRAM_1_RULE[4];                    /**< RAM partition 1 Memory Rule Register, array offset: 0x20, array step: 0x4 */
  __IO uint32_t SRAM_2_RULE[4];                    /**< RAM partition 2 Memory Rule Register, array offset: 0x30, array step: 0x4 */
  __IO uint32_t SRAM_3_RULE[4];                    /**< RAM partition 3 Memory Rule Register, array offset: 0x40, array step: 0x4 */
  __IO uint32_t SRAM_4_RULE[4];                    /**< RAM partition 4 Memory Rule Register, array offset: 0x50, array step: 0x4 */
  __IO uint32_t SRAM_5_RULE[4];                    /**< RAM partition 5 Memory Rule Register, array offset: 0x60, array step: 0x4 */
  __IO uint32_t SRAM_6_RULE[4];                    /**< RAM partition 6 Memory Rule Register, array offset: 0x70, array step: 0x4 */
  __IO uint32_t SRAM_7_RULE[4];                    /**< RAM partition 7 Memory Rule Register, array offset: 0x80, array step: 0x4 */
  __IO uint32_t SRAM_8_RULE[4];                    /**< RAM partition 8 Memory Rule Register, array offset: 0x90, array step: 0x4 */
  __IO uint32_t SRAM_9_RULE[4];                    /**< RAM partition 9 Memory Rule Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_1[16];
  __IO uint32_t SRAM_10_RULE[4];                   /**< RAM partition 10 Memory Rule Register, array offset: 0xC0, array step: 0x4 */
  __IO uint32_t SRAM_11_RULE[4];                   /**< RAM partition 11 Memory Rule Register, array offset: 0xD0, array step: 0x4 */
       uint8_t RESERVED_2[16];
  __IO uint32_t SRAM_12_RULE[4];                   /**< RAM partition 12 Memory Rule Register, array offset: 0xF0, array step: 0x4 */
  __IO uint32_t SRAM_13_RULE[4];                   /**< RAM partition 13 Memory Rule Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_3[16];
  __IO uint32_t SRAM_14_RULE[4];                   /**< RAM partition 14 Memory Rule Register, array offset: 0x120, array step: 0x4 */
  __IO uint32_t SRAM_15_RULE[4];                   /**< RAM partition 15 Memory Rule Register, array offset: 0x130, array step: 0x4 */
       uint8_t RESERVED_4[16];
  __IO uint32_t SRAM_16_RULE[4];                   /**< RAM partition 16 Memory Rule Register, array offset: 0x150, array step: 0x4 */
  __IO uint32_t SRAM_17_RULE[4];                   /**< RAM partition 17 Memory Rule Register, array offset: 0x160, array step: 0x4 */
       uint8_t RESERVED_5[16];
  __IO uint32_t SRAM_18_RULE[4];                   /**< RAM partition 18 Memory Rule Register, array offset: 0x180, array step: 0x4 */
  __IO uint32_t SRAM_19_RULE[4];                   /**< RAM partition 19 Memory Rule Register, array offset: 0x190, array step: 0x4 */
  __IO uint32_t SRAM_20_RULE[4];                   /**< RAM partition 20 Memory Rule Register, array offset: 0x1A0, array step: 0x4 */
  __IO uint32_t SRAM_21_RULE[4];                   /**< RAM partition 21 Memory Rule Register, array offset: 0x1B0, array step: 0x4 */
       uint8_t RESERVED_6[16];
  __IO uint32_t SRAM_22_RULE[4];                   /**< RAM partition 22 Memory Rule Register, array offset: 0x1D0, array step: 0x4 */
  __IO uint32_t SRAM_23_RULE[4];                   /**< RAM partition 23 Memory Rule Register, array offset: 0x1E0, array step: 0x4 */
       uint8_t RESERVED_7[16];
  __IO uint32_t SRAM_24_RULE[4];                   /**< RAM partition 24 Memory Rule Register, array offset: 0x200, array step: 0x4 */
  __IO uint32_t SRAM_25_RULE[4];                   /**< RAM partition 25 Memory Rule Register, array offset: 0x210, array step: 0x4 */
       uint8_t RESERVED_8[16];
  __IO uint32_t SRAM_26_RULE[4];                   /**< RAM partition 26 Memory Rule Register, array offset: 0x230, array step: 0x4 */
  __IO uint32_t SRAM_27_RULE[4];                   /**< RAM partition 27 Memory Rule Register, array offset: 0x240, array step: 0x4 */
       uint8_t RESERVED_9[16];
  __IO uint32_t SRAM_28_RULE[4];                   /**< RAM partition 28 Memory Rule Register, array offset: 0x260, array step: 0x4 */
  __IO uint32_t SRAM_29_RULE[4];                   /**< RAM partition 29 Memory Rule Register, array offset: 0x270, array step: 0x4 */
  __IO uint32_t AHB_PERIPHERAL10_SLAVE_RULE0;      /**< AHB Peripheral 10 Slaves Rule Register 0, offset: 0x280 */
  __IO uint32_t AHB_PERIPHERAL10_SLAVE_RULE1;      /**< AHB Peripheral 10 Slaves Rule Register 1, offset: 0x284 */
       uint8_t RESERVED_10[8];
  __IO uint32_t AIPS5_BRIDGE_GROUP0_MEM_RULE0;     /**< AIPS5 Bridge Group 0 Memory Rule Register 0, offset: 0x290 */
  __IO uint32_t AIPS5_BRIDGE_GROUP0_MEM_RULE1;     /**< AIPS5 Bridge Group 0 Memory Rule Register 1, offset: 0x294 */
  __IO uint32_t AIPS5_BRIDGE_GROUP0_MEM_RULE2;     /**< AIPS5 Bridge Group 0 Memory Rule Register 2, offset: 0x298 */
  __IO uint32_t AIPS5_BRIDGE_GROUP0_MEM_RULE3;     /**< AIPS5 Bridge Group 0 Memory Rule Register 3, offset: 0x29C */
  struct {                                         /* offset: 0x2A0, array step: 0x10 */
    __IO uint32_t AHB_PERIPHERAL10_SLAVE_GPIO_RULE;   /**< AHB Peripheral 10 Slaves GPIO8 Rule Register..AHB Peripheral 10 Slaves GPIO10 Rule Register, array offset: 0x2A0, array step: 0x10 */
         uint8_t RESERVED_0[12];
  } AHB_PERIPHERAL10_SLAVE_GPION_RULE[3];
       uint8_t RESERVED_11[16];
  __IO uint32_t AIPS2_BRIDGE_GROUP0_MEM_RULE0;     /**< AIPS2 Bridge Group 0 Memory Rule Register 0, offset: 0x2E0 */
  __IO uint32_t AIPS2_BRIDGE_GROUP0_MEM_RULE1;     /**< AIPS2 Bridge Group 0 Memory Rule Register 1, offset: 0x2E4 */
       uint8_t RESERVED_12[8];
  __IO uint32_t AIPS2_BRIDGE_GROUP1_MEM_RULE0;     /**< AIPS2 Bridge Group 1 Memory Rule Register 0, offset: 0x2F0 */
       uint8_t RESERVED_13[12];
  __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_RULE0;  /**< AHB Secure Control Peripheral Rule 0, offset: 0x300 */
       uint8_t RESERVED_14[44];
  __IO uint32_t SENSE_APB_SLAVE_GROUP0_RULE0;      /**< APB Bridge Peripheral 0 Rule 0, offset: 0x330 */
  __IO uint32_t SENSE_APB_SLAVE_GROUP0_RULE1;      /**< APB Bridge Peripheral 0 Rule Register 1, offset: 0x334 */
  __IO uint32_t SENSE_APB_SLAVE_GROUP0_RULE2;      /**< APB Bridge Peripheral 0 Rule Register 2, offset: 0x338 */
       uint8_t RESERVED_15[4];
  __IO uint32_t SHARED_APB_SLAVE_GROUP0_RULE0;     /**< Shared APB Bridge Peripheral 0 Rule 0, offset: 0x340 */
  __IO uint32_t SHARED_APB_SLAVE_GROUP0_RULE1;     /**< Shared APB Bridge Peripheral 0 Rule 1, offset: 0x344 */
       uint8_t RESERVED_16[8];
  __IO uint32_t SENSE2MEDIA_RULE;                  /**< SENSE domain to MEDIA domain Access Rule Register, offset: 0x350 */
       uint8_t RESERVED_17[12];
  __IO uint32_t MEDIA_AHB_PERIPHERAL_SLAVE_RULE0;  /**< MEDIA domain AHB peripheral slave, offset: 0x360 */
       uint8_t RESERVED_18[12];
  __IO uint32_t MEDIA_APB_PERIPHERAL_SLAVE_RULE0;  /**< MEDIA domain APB peripheral slave Rule Register, offset: 0x370 */
       uint8_t RESERVED_19[12];
  __IO uint32_t EZHV_SRAM_RULE0;                   /**< EZHV SRAM Memory Rule Register, offset: 0x380 */
       uint8_t RESERVED_20[2684];
  __I  uint32_t SEC_VIO_ADDR[17];                  /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */
       uint8_t RESERVED_21[60];
  __I  uint32_t SEC_VIO_MISC_INFO[17];             /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */
       uint8_t RESERVED_22[60];
  __IO uint32_t SEC_VIO_INFO_VALID;                /**< Security Violation Info Validity for Address, offset: 0xF00 */
       uint8_t RESERVED_23[124];
  __IO uint32_t COMPUTE_ARB1RAM_ACCESS_ENABLE;     /**< Access enable for COMPUTE domain masters to RAM partitions., offset: 0xF80 */
  __IO uint32_t SENSE_ARB1RAM_ACCESS_ENABLE;       /**< Access enable for SENSE domain masters to RAM partitions., offset: 0xF84 */
  __IO uint32_t MEDIA_ARB1RAM_ACCESS_ENABLE;       /**< Access enable for MEDIA domain masters to RAM partitions., offset: 0xF88 */
  __IO uint32_t NPU_ARB1RAM_ACCESS_ENABLE;         /**< Access enable for NPU to RAM partitions., offset: 0xF8C */
  __IO uint32_t HIFI4_ARB1RAM_ACCESS_ENABLE;       /**< Access enable for HIFI4 to RAM partitions., offset: 0xF90 */
  __IO uint32_t HIFI1_ARB1RAM_ACCESS_ENABLE;       /**< Access enable for HIFI1 to RAM partitions., offset: 0xF94 */
       uint8_t RESERVED_24[8];
  __IO uint32_t COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE; /**< Access enable for COMPUTE domain masters to common APB peripherals., offset: 0xFA0 */
  __IO uint32_t SENSE_APB_PERIPHERAL_ACCESS_ENABLE; /**< Access enable for SENSE domain masters to common APB peripherals., offset: 0xFA4 */
       uint8_t RESERVED_25[8];
  __IO uint32_t COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE; /**< Access enable for COMPUTE domain masters to common AIPS peripherals., offset: 0xFB0 */
  __IO uint32_t SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE; /**< Access enable for SENSE domain masters to common AIPS peripherals., offset: 0xFB4 */
       uint8_t RESERVED_26[24];
  __IO uint32_t MASTER_SEC_LEVEL;                  /**< Master Secure Level, offset: 0xFD0 */
  __IO uint32_t MASTER_SEC_ANTI_POL_REG;           /**< Master Secure Level, offset: 0xFD4 */
       uint8_t RESERVED_27[20];
  __IO uint32_t CPU1_LOCK_REG;                     /**< Miscellaneous CPU1 Control Signals, offset: 0xFEC */
       uint8_t RESERVED_28[8];
  __IO uint32_t MISC_CTRL_DP_REG;                  /**< Secure Control Duplicate, offset: 0xFF8 */
  __IO uint32_t MISC_CTRL_REG;                     /**< Secure Control, offset: 0xFFC */
} AHBSC3_Type;

/* ----------------------------------------------------------------------------
   -- AHBSC3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AHBSC3_Register_Masks AHBSC3 Register Masks
 * @{
 */

/*! @name SRAM_0_RULE - RAM partition 0 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_0_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_0_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_0_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_0_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_0_RULE_RULE0_MASK)

#define AHBSC3_SRAM_0_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_0_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_0_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_0_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_0_RULE_RULE1_MASK)

#define AHBSC3_SRAM_0_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_0_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_0_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_0_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_0_RULE_RULE2_MASK)

#define AHBSC3_SRAM_0_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_0_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_0_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_0_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_0_RULE_RULE3_MASK)

#define AHBSC3_SRAM_0_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_0_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_0_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_0_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_0_RULE_RULE4_MASK)

#define AHBSC3_SRAM_0_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_0_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_0_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_0_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_0_RULE_RULE5_MASK)

#define AHBSC3_SRAM_0_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_0_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_0_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_0_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_0_RULE_RULE6_MASK)

#define AHBSC3_SRAM_0_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_0_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_0_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_0_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_0_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_0_RULE */
#define AHBSC3_SRAM_0_RULE_COUNT                 (4U)

/*! @name SRAM_1_RULE - RAM partition 1 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_1_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_1_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_1_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_1_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_1_RULE_RULE0_MASK)

#define AHBSC3_SRAM_1_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_1_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_1_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_1_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_1_RULE_RULE1_MASK)

#define AHBSC3_SRAM_1_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_1_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_1_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_1_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_1_RULE_RULE2_MASK)

#define AHBSC3_SRAM_1_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_1_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_1_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_1_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_1_RULE_RULE3_MASK)

#define AHBSC3_SRAM_1_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_1_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_1_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_1_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_1_RULE_RULE4_MASK)

#define AHBSC3_SRAM_1_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_1_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_1_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_1_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_1_RULE_RULE5_MASK)

#define AHBSC3_SRAM_1_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_1_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_1_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_1_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_1_RULE_RULE6_MASK)

#define AHBSC3_SRAM_1_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_1_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_1_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_1_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_1_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_1_RULE */
#define AHBSC3_SRAM_1_RULE_COUNT                 (4U)

/*! @name SRAM_2_RULE - RAM partition 2 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_2_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_2_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_2_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_2_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_2_RULE_RULE0_MASK)

#define AHBSC3_SRAM_2_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_2_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_2_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_2_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_2_RULE_RULE1_MASK)

#define AHBSC3_SRAM_2_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_2_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_2_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_2_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_2_RULE_RULE2_MASK)

#define AHBSC3_SRAM_2_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_2_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_2_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_2_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_2_RULE_RULE3_MASK)

#define AHBSC3_SRAM_2_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_2_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_2_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_2_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_2_RULE_RULE4_MASK)

#define AHBSC3_SRAM_2_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_2_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_2_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_2_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_2_RULE_RULE5_MASK)

#define AHBSC3_SRAM_2_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_2_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_2_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_2_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_2_RULE_RULE6_MASK)

#define AHBSC3_SRAM_2_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_2_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_2_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_2_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_2_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_2_RULE */
#define AHBSC3_SRAM_2_RULE_COUNT                 (4U)

/*! @name SRAM_3_RULE - RAM partition 3 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_3_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_3_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_3_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_3_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_3_RULE_RULE0_MASK)

#define AHBSC3_SRAM_3_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_3_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_3_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_3_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_3_RULE_RULE1_MASK)

#define AHBSC3_SRAM_3_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_3_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_3_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_3_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_3_RULE_RULE2_MASK)

#define AHBSC3_SRAM_3_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_3_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_3_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_3_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_3_RULE_RULE3_MASK)

#define AHBSC3_SRAM_3_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_3_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_3_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_3_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_3_RULE_RULE4_MASK)

#define AHBSC3_SRAM_3_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_3_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_3_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_3_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_3_RULE_RULE5_MASK)

#define AHBSC3_SRAM_3_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_3_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_3_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_3_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_3_RULE_RULE6_MASK)

#define AHBSC3_SRAM_3_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_3_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_3_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_3_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_3_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_3_RULE */
#define AHBSC3_SRAM_3_RULE_COUNT                 (4U)

/*! @name SRAM_4_RULE - RAM partition 4 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_4_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_4_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_4_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_4_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_4_RULE_RULE0_MASK)

#define AHBSC3_SRAM_4_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_4_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_4_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_4_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_4_RULE_RULE1_MASK)

#define AHBSC3_SRAM_4_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_4_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_4_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_4_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_4_RULE_RULE2_MASK)

#define AHBSC3_SRAM_4_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_4_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_4_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_4_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_4_RULE_RULE3_MASK)

#define AHBSC3_SRAM_4_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_4_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_4_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_4_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_4_RULE_RULE4_MASK)

#define AHBSC3_SRAM_4_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_4_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_4_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_4_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_4_RULE_RULE5_MASK)

#define AHBSC3_SRAM_4_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_4_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_4_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_4_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_4_RULE_RULE6_MASK)

#define AHBSC3_SRAM_4_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_4_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_4_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_4_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_4_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_4_RULE */
#define AHBSC3_SRAM_4_RULE_COUNT                 (4U)

/*! @name SRAM_5_RULE - RAM partition 5 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_5_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_5_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_5_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_5_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_5_RULE_RULE0_MASK)

#define AHBSC3_SRAM_5_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_5_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_5_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_5_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_5_RULE_RULE1_MASK)

#define AHBSC3_SRAM_5_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_5_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_5_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_5_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_5_RULE_RULE2_MASK)

#define AHBSC3_SRAM_5_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_5_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_5_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_5_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_5_RULE_RULE3_MASK)

#define AHBSC3_SRAM_5_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_5_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_5_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_5_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_5_RULE_RULE4_MASK)

#define AHBSC3_SRAM_5_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_5_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_5_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_5_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_5_RULE_RULE5_MASK)

#define AHBSC3_SRAM_5_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_5_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_5_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_5_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_5_RULE_RULE6_MASK)

#define AHBSC3_SRAM_5_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_5_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_5_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_5_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_5_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_5_RULE */
#define AHBSC3_SRAM_5_RULE_COUNT                 (4U)

/*! @name SRAM_6_RULE - RAM partition 6 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_6_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_6_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_6_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_6_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_6_RULE_RULE0_MASK)

#define AHBSC3_SRAM_6_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_6_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_6_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_6_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_6_RULE_RULE1_MASK)

#define AHBSC3_SRAM_6_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_6_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_6_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_6_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_6_RULE_RULE2_MASK)

#define AHBSC3_SRAM_6_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_6_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_6_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_6_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_6_RULE_RULE3_MASK)

#define AHBSC3_SRAM_6_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_6_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_6_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_6_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_6_RULE_RULE4_MASK)

#define AHBSC3_SRAM_6_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_6_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_6_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_6_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_6_RULE_RULE5_MASK)

#define AHBSC3_SRAM_6_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_6_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_6_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_6_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_6_RULE_RULE6_MASK)

#define AHBSC3_SRAM_6_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_6_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_6_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_6_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_6_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_6_RULE */
#define AHBSC3_SRAM_6_RULE_COUNT                 (4U)

/*! @name SRAM_7_RULE - RAM partition 7 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_7_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_7_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_7_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_7_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_7_RULE_RULE0_MASK)

#define AHBSC3_SRAM_7_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_7_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_7_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_7_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_7_RULE_RULE1_MASK)

#define AHBSC3_SRAM_7_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_7_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_7_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_7_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_7_RULE_RULE2_MASK)

#define AHBSC3_SRAM_7_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_7_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_7_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_7_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_7_RULE_RULE3_MASK)

#define AHBSC3_SRAM_7_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_7_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_7_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_7_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_7_RULE_RULE4_MASK)

#define AHBSC3_SRAM_7_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_7_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_7_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_7_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_7_RULE_RULE5_MASK)

#define AHBSC3_SRAM_7_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_7_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_7_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_7_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_7_RULE_RULE6_MASK)

#define AHBSC3_SRAM_7_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_7_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_7_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_7_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_7_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_7_RULE */
#define AHBSC3_SRAM_7_RULE_COUNT                 (4U)

/*! @name SRAM_8_RULE - RAM partition 8 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_8_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_8_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_8_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_8_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_8_RULE_RULE0_MASK)

#define AHBSC3_SRAM_8_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_8_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_8_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_8_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_8_RULE_RULE1_MASK)

#define AHBSC3_SRAM_8_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_8_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_8_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_8_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_8_RULE_RULE2_MASK)

#define AHBSC3_SRAM_8_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_8_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_8_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_8_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_8_RULE_RULE3_MASK)

#define AHBSC3_SRAM_8_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_8_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_8_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_8_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_8_RULE_RULE4_MASK)

#define AHBSC3_SRAM_8_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_8_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_8_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_8_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_8_RULE_RULE5_MASK)

#define AHBSC3_SRAM_8_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_8_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_8_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_8_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_8_RULE_RULE6_MASK)

#define AHBSC3_SRAM_8_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_8_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_8_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_8_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_8_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_8_RULE */
#define AHBSC3_SRAM_8_RULE_COUNT                 (4U)

/*! @name SRAM_9_RULE - RAM partition 9 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_9_RULE_RULE0_MASK            (0x3U)
#define AHBSC3_SRAM_9_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_9_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_9_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_9_RULE_RULE0_MASK)

#define AHBSC3_SRAM_9_RULE_RULE1_MASK            (0x30U)
#define AHBSC3_SRAM_9_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_9_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_9_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_9_RULE_RULE1_MASK)

#define AHBSC3_SRAM_9_RULE_RULE2_MASK            (0x300U)
#define AHBSC3_SRAM_9_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_9_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_9_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_9_RULE_RULE2_MASK)

#define AHBSC3_SRAM_9_RULE_RULE3_MASK            (0x3000U)
#define AHBSC3_SRAM_9_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_9_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_9_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_9_RULE_RULE3_MASK)

#define AHBSC3_SRAM_9_RULE_RULE4_MASK            (0x30000U)
#define AHBSC3_SRAM_9_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_9_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_9_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_9_RULE_RULE4_MASK)

#define AHBSC3_SRAM_9_RULE_RULE5_MASK            (0x300000U)
#define AHBSC3_SRAM_9_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_9_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_9_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_9_RULE_RULE5_MASK)

#define AHBSC3_SRAM_9_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC3_SRAM_9_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_9_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_9_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_9_RULE_RULE6_MASK)

#define AHBSC3_SRAM_9_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC3_SRAM_9_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_9_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_9_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_9_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_9_RULE */
#define AHBSC3_SRAM_9_RULE_COUNT                 (4U)

/*! @name SRAM_10_RULE - RAM partition 10 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_10_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_10_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_10_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_10_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_10_RULE_RULE0_MASK)

#define AHBSC3_SRAM_10_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_10_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_10_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_10_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_10_RULE_RULE1_MASK)

#define AHBSC3_SRAM_10_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_10_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_10_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_10_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_10_RULE_RULE2_MASK)

#define AHBSC3_SRAM_10_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_10_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_10_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_10_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_10_RULE_RULE3_MASK)

#define AHBSC3_SRAM_10_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_10_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_10_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_10_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_10_RULE_RULE4_MASK)

#define AHBSC3_SRAM_10_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_10_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_10_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_10_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_10_RULE_RULE5_MASK)

#define AHBSC3_SRAM_10_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_10_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_10_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_10_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_10_RULE_RULE6_MASK)

#define AHBSC3_SRAM_10_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_10_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_10_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_10_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_10_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_10_RULE */
#define AHBSC3_SRAM_10_RULE_COUNT                (4U)

/*! @name SRAM_11_RULE - RAM partition 11 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_11_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_11_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_11_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_11_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_11_RULE_RULE0_MASK)

#define AHBSC3_SRAM_11_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_11_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_11_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_11_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_11_RULE_RULE1_MASK)

#define AHBSC3_SRAM_11_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_11_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_11_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_11_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_11_RULE_RULE2_MASK)

#define AHBSC3_SRAM_11_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_11_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_11_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_11_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_11_RULE_RULE3_MASK)

#define AHBSC3_SRAM_11_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_11_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_11_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_11_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_11_RULE_RULE4_MASK)

#define AHBSC3_SRAM_11_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_11_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_11_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_11_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_11_RULE_RULE5_MASK)

#define AHBSC3_SRAM_11_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_11_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_11_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_11_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_11_RULE_RULE6_MASK)

#define AHBSC3_SRAM_11_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_11_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_11_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_11_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_11_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_11_RULE */
#define AHBSC3_SRAM_11_RULE_COUNT                (4U)

/*! @name SRAM_12_RULE - RAM partition 12 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_12_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_12_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_12_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_12_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_12_RULE_RULE0_MASK)

#define AHBSC3_SRAM_12_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_12_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_12_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_12_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_12_RULE_RULE1_MASK)

#define AHBSC3_SRAM_12_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_12_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_12_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_12_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_12_RULE_RULE2_MASK)

#define AHBSC3_SRAM_12_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_12_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_12_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_12_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_12_RULE_RULE3_MASK)

#define AHBSC3_SRAM_12_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_12_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_12_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_12_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_12_RULE_RULE4_MASK)

#define AHBSC3_SRAM_12_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_12_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_12_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_12_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_12_RULE_RULE5_MASK)

#define AHBSC3_SRAM_12_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_12_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_12_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_12_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_12_RULE_RULE6_MASK)

#define AHBSC3_SRAM_12_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_12_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_12_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_12_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_12_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_12_RULE */
#define AHBSC3_SRAM_12_RULE_COUNT                (4U)

/*! @name SRAM_13_RULE - RAM partition 13 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_13_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_13_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_13_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_13_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_13_RULE_RULE0_MASK)

#define AHBSC3_SRAM_13_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_13_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_13_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_13_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_13_RULE_RULE1_MASK)

#define AHBSC3_SRAM_13_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_13_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_13_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_13_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_13_RULE_RULE2_MASK)

#define AHBSC3_SRAM_13_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_13_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_13_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_13_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_13_RULE_RULE3_MASK)

#define AHBSC3_SRAM_13_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_13_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_13_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_13_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_13_RULE_RULE4_MASK)

#define AHBSC3_SRAM_13_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_13_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_13_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_13_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_13_RULE_RULE5_MASK)

#define AHBSC3_SRAM_13_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_13_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_13_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_13_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_13_RULE_RULE6_MASK)

#define AHBSC3_SRAM_13_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_13_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_13_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_13_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_13_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_13_RULE */
#define AHBSC3_SRAM_13_RULE_COUNT                (4U)

/*! @name SRAM_14_RULE - RAM partition 14 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_14_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_14_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_14_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_14_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_14_RULE_RULE0_MASK)

#define AHBSC3_SRAM_14_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_14_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_14_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_14_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_14_RULE_RULE1_MASK)

#define AHBSC3_SRAM_14_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_14_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_14_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_14_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_14_RULE_RULE2_MASK)

#define AHBSC3_SRAM_14_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_14_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_14_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_14_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_14_RULE_RULE3_MASK)

#define AHBSC3_SRAM_14_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_14_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_14_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_14_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_14_RULE_RULE4_MASK)

#define AHBSC3_SRAM_14_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_14_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_14_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_14_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_14_RULE_RULE5_MASK)

#define AHBSC3_SRAM_14_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_14_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_14_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_14_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_14_RULE_RULE6_MASK)

#define AHBSC3_SRAM_14_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_14_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_14_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_14_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_14_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_14_RULE */
#define AHBSC3_SRAM_14_RULE_COUNT                (4U)

/*! @name SRAM_15_RULE - RAM partition 15 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_15_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_15_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_15_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_15_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_15_RULE_RULE0_MASK)

#define AHBSC3_SRAM_15_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_15_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_15_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_15_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_15_RULE_RULE1_MASK)

#define AHBSC3_SRAM_15_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_15_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_15_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_15_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_15_RULE_RULE2_MASK)

#define AHBSC3_SRAM_15_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_15_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_15_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_15_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_15_RULE_RULE3_MASK)

#define AHBSC3_SRAM_15_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_15_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_15_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_15_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_15_RULE_RULE4_MASK)

#define AHBSC3_SRAM_15_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_15_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_15_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_15_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_15_RULE_RULE5_MASK)

#define AHBSC3_SRAM_15_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_15_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_15_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_15_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_15_RULE_RULE6_MASK)

#define AHBSC3_SRAM_15_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_15_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_15_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_15_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_15_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_15_RULE */
#define AHBSC3_SRAM_15_RULE_COUNT                (4U)

/*! @name SRAM_16_RULE - RAM partition 16 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_16_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_16_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_16_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_16_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_16_RULE_RULE0_MASK)

#define AHBSC3_SRAM_16_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_16_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_16_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_16_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_16_RULE_RULE1_MASK)

#define AHBSC3_SRAM_16_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_16_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_16_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_16_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_16_RULE_RULE2_MASK)

#define AHBSC3_SRAM_16_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_16_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_16_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_16_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_16_RULE_RULE3_MASK)

#define AHBSC3_SRAM_16_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_16_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_16_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_16_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_16_RULE_RULE4_MASK)

#define AHBSC3_SRAM_16_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_16_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_16_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_16_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_16_RULE_RULE5_MASK)

#define AHBSC3_SRAM_16_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_16_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_16_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_16_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_16_RULE_RULE6_MASK)

#define AHBSC3_SRAM_16_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_16_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_16_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_16_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_16_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_16_RULE */
#define AHBSC3_SRAM_16_RULE_COUNT                (4U)

/*! @name SRAM_17_RULE - RAM partition 17 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_17_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_17_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_17_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_17_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_17_RULE_RULE0_MASK)

#define AHBSC3_SRAM_17_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_17_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_17_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_17_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_17_RULE_RULE1_MASK)

#define AHBSC3_SRAM_17_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_17_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_17_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_17_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_17_RULE_RULE2_MASK)

#define AHBSC3_SRAM_17_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_17_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_17_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_17_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_17_RULE_RULE3_MASK)

#define AHBSC3_SRAM_17_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_17_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_17_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_17_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_17_RULE_RULE4_MASK)

#define AHBSC3_SRAM_17_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_17_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_17_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_17_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_17_RULE_RULE5_MASK)

#define AHBSC3_SRAM_17_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_17_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_17_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_17_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_17_RULE_RULE6_MASK)

#define AHBSC3_SRAM_17_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_17_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_17_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_17_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_17_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_17_RULE */
#define AHBSC3_SRAM_17_RULE_COUNT                (4U)

/*! @name SRAM_18_RULE - RAM partition 18 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_18_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_18_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_18_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_18_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_18_RULE_RULE0_MASK)

#define AHBSC3_SRAM_18_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_18_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_18_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_18_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_18_RULE_RULE1_MASK)

#define AHBSC3_SRAM_18_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_18_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_18_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_18_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_18_RULE_RULE2_MASK)

#define AHBSC3_SRAM_18_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_18_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_18_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_18_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_18_RULE_RULE3_MASK)

#define AHBSC3_SRAM_18_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_18_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_18_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_18_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_18_RULE_RULE4_MASK)

#define AHBSC3_SRAM_18_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_18_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_18_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_18_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_18_RULE_RULE5_MASK)

#define AHBSC3_SRAM_18_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_18_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_18_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_18_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_18_RULE_RULE6_MASK)

#define AHBSC3_SRAM_18_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_18_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_18_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_18_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_18_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_18_RULE */
#define AHBSC3_SRAM_18_RULE_COUNT                (4U)

/*! @name SRAM_19_RULE - RAM partition 19 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_19_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_19_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_19_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_19_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_19_RULE_RULE0_MASK)

#define AHBSC3_SRAM_19_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_19_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_19_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_19_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_19_RULE_RULE1_MASK)

#define AHBSC3_SRAM_19_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_19_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_19_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_19_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_19_RULE_RULE2_MASK)

#define AHBSC3_SRAM_19_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_19_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_19_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_19_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_19_RULE_RULE3_MASK)

#define AHBSC3_SRAM_19_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_19_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_19_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_19_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_19_RULE_RULE4_MASK)

#define AHBSC3_SRAM_19_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_19_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_19_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_19_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_19_RULE_RULE5_MASK)

#define AHBSC3_SRAM_19_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_19_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_19_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_19_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_19_RULE_RULE6_MASK)

#define AHBSC3_SRAM_19_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_19_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_19_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_19_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_19_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_19_RULE */
#define AHBSC3_SRAM_19_RULE_COUNT                (4U)

/*! @name SRAM_20_RULE - RAM partition 20 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_20_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_20_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_20_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_20_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_20_RULE_RULE0_MASK)

#define AHBSC3_SRAM_20_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_20_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_20_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_20_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_20_RULE_RULE1_MASK)

#define AHBSC3_SRAM_20_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_20_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_20_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_20_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_20_RULE_RULE2_MASK)

#define AHBSC3_SRAM_20_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_20_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_20_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_20_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_20_RULE_RULE3_MASK)

#define AHBSC3_SRAM_20_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_20_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_20_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_20_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_20_RULE_RULE4_MASK)

#define AHBSC3_SRAM_20_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_20_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_20_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_20_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_20_RULE_RULE5_MASK)

#define AHBSC3_SRAM_20_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_20_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_20_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_20_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_20_RULE_RULE6_MASK)

#define AHBSC3_SRAM_20_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_20_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_20_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_20_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_20_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_20_RULE */
#define AHBSC3_SRAM_20_RULE_COUNT                (4U)

/*! @name SRAM_21_RULE - RAM partition 21 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_21_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_21_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_21_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_21_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_21_RULE_RULE0_MASK)

#define AHBSC3_SRAM_21_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_21_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_21_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_21_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_21_RULE_RULE1_MASK)

#define AHBSC3_SRAM_21_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_21_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_21_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_21_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_21_RULE_RULE2_MASK)

#define AHBSC3_SRAM_21_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_21_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_21_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_21_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_21_RULE_RULE3_MASK)

#define AHBSC3_SRAM_21_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_21_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_21_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_21_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_21_RULE_RULE4_MASK)

#define AHBSC3_SRAM_21_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_21_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_21_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_21_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_21_RULE_RULE5_MASK)

#define AHBSC3_SRAM_21_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_21_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_21_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_21_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_21_RULE_RULE6_MASK)

#define AHBSC3_SRAM_21_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_21_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_21_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_21_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_21_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_21_RULE */
#define AHBSC3_SRAM_21_RULE_COUNT                (4U)

/*! @name SRAM_22_RULE - RAM partition 22 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_22_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_22_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_22_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_22_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_22_RULE_RULE0_MASK)

#define AHBSC3_SRAM_22_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_22_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_22_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_22_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_22_RULE_RULE1_MASK)

#define AHBSC3_SRAM_22_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_22_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_22_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_22_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_22_RULE_RULE2_MASK)

#define AHBSC3_SRAM_22_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_22_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_22_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_22_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_22_RULE_RULE3_MASK)

#define AHBSC3_SRAM_22_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_22_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_22_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_22_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_22_RULE_RULE4_MASK)

#define AHBSC3_SRAM_22_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_22_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_22_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_22_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_22_RULE_RULE5_MASK)

#define AHBSC3_SRAM_22_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_22_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_22_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_22_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_22_RULE_RULE6_MASK)

#define AHBSC3_SRAM_22_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_22_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_22_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_22_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_22_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_22_RULE */
#define AHBSC3_SRAM_22_RULE_COUNT                (4U)

/*! @name SRAM_23_RULE - RAM partition 23 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_23_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_23_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_23_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_23_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_23_RULE_RULE0_MASK)

#define AHBSC3_SRAM_23_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_23_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_23_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_23_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_23_RULE_RULE1_MASK)

#define AHBSC3_SRAM_23_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_23_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_23_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_23_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_23_RULE_RULE2_MASK)

#define AHBSC3_SRAM_23_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_23_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_23_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_23_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_23_RULE_RULE3_MASK)

#define AHBSC3_SRAM_23_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_23_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_23_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_23_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_23_RULE_RULE4_MASK)

#define AHBSC3_SRAM_23_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_23_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_23_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_23_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_23_RULE_RULE5_MASK)

#define AHBSC3_SRAM_23_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_23_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_23_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_23_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_23_RULE_RULE6_MASK)

#define AHBSC3_SRAM_23_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_23_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_23_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_23_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_23_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_23_RULE */
#define AHBSC3_SRAM_23_RULE_COUNT                (4U)

/*! @name SRAM_24_RULE - RAM partition 24 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_24_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_24_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_24_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_24_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_24_RULE_RULE0_MASK)

#define AHBSC3_SRAM_24_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_24_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_24_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_24_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_24_RULE_RULE1_MASK)

#define AHBSC3_SRAM_24_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_24_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_24_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_24_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_24_RULE_RULE2_MASK)

#define AHBSC3_SRAM_24_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_24_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_24_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_24_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_24_RULE_RULE3_MASK)

#define AHBSC3_SRAM_24_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_24_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_24_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_24_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_24_RULE_RULE4_MASK)

#define AHBSC3_SRAM_24_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_24_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_24_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_24_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_24_RULE_RULE5_MASK)

#define AHBSC3_SRAM_24_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_24_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_24_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_24_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_24_RULE_RULE6_MASK)

#define AHBSC3_SRAM_24_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_24_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_24_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_24_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_24_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_24_RULE */
#define AHBSC3_SRAM_24_RULE_COUNT                (4U)

/*! @name SRAM_25_RULE - RAM partition 25 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_25_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_25_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_25_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_25_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_25_RULE_RULE0_MASK)

#define AHBSC3_SRAM_25_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_25_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_25_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_25_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_25_RULE_RULE1_MASK)

#define AHBSC3_SRAM_25_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_25_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_25_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_25_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_25_RULE_RULE2_MASK)

#define AHBSC3_SRAM_25_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_25_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_25_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_25_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_25_RULE_RULE3_MASK)

#define AHBSC3_SRAM_25_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_25_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_25_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_25_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_25_RULE_RULE4_MASK)

#define AHBSC3_SRAM_25_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_25_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_25_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_25_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_25_RULE_RULE5_MASK)

#define AHBSC3_SRAM_25_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_25_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_25_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_25_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_25_RULE_RULE6_MASK)

#define AHBSC3_SRAM_25_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_25_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_25_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_25_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_25_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_25_RULE */
#define AHBSC3_SRAM_25_RULE_COUNT                (4U)

/*! @name SRAM_26_RULE - RAM partition 26 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_26_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_26_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_26_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_26_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_26_RULE_RULE0_MASK)

#define AHBSC3_SRAM_26_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_26_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_26_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_26_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_26_RULE_RULE1_MASK)

#define AHBSC3_SRAM_26_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_26_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_26_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_26_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_26_RULE_RULE2_MASK)

#define AHBSC3_SRAM_26_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_26_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_26_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_26_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_26_RULE_RULE3_MASK)

#define AHBSC3_SRAM_26_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_26_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_26_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_26_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_26_RULE_RULE4_MASK)

#define AHBSC3_SRAM_26_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_26_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_26_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_26_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_26_RULE_RULE5_MASK)

#define AHBSC3_SRAM_26_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_26_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_26_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_26_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_26_RULE_RULE6_MASK)

#define AHBSC3_SRAM_26_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_26_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_26_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_26_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_26_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_26_RULE */
#define AHBSC3_SRAM_26_RULE_COUNT                (4U)

/*! @name SRAM_27_RULE - RAM partition 27 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_27_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_27_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_27_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_27_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_27_RULE_RULE0_MASK)

#define AHBSC3_SRAM_27_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_27_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_27_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_27_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_27_RULE_RULE1_MASK)

#define AHBSC3_SRAM_27_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_27_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_27_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_27_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_27_RULE_RULE2_MASK)

#define AHBSC3_SRAM_27_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_27_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_27_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_27_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_27_RULE_RULE3_MASK)

#define AHBSC3_SRAM_27_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_27_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_27_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_27_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_27_RULE_RULE4_MASK)

#define AHBSC3_SRAM_27_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_27_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_27_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_27_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_27_RULE_RULE5_MASK)

#define AHBSC3_SRAM_27_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_27_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_27_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_27_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_27_RULE_RULE6_MASK)

#define AHBSC3_SRAM_27_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_27_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_27_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_27_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_27_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_27_RULE */
#define AHBSC3_SRAM_27_RULE_COUNT                (4U)

/*! @name SRAM_28_RULE - RAM partition 28 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_28_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_28_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_28_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_28_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_28_RULE_RULE0_MASK)

#define AHBSC3_SRAM_28_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_28_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_28_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_28_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_28_RULE_RULE1_MASK)

#define AHBSC3_SRAM_28_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_28_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_28_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_28_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_28_RULE_RULE2_MASK)

#define AHBSC3_SRAM_28_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_28_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_28_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_28_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_28_RULE_RULE3_MASK)

#define AHBSC3_SRAM_28_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_28_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_28_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_28_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_28_RULE_RULE4_MASK)

#define AHBSC3_SRAM_28_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_28_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_28_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_28_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_28_RULE_RULE5_MASK)

#define AHBSC3_SRAM_28_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_28_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_28_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_28_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_28_RULE_RULE6_MASK)

#define AHBSC3_SRAM_28_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_28_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_28_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_28_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_28_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_28_RULE */
#define AHBSC3_SRAM_28_RULE_COUNT                (4U)

/*! @name SRAM_29_RULE - RAM partition 29 Memory Rule Register */
/*! @{ */

#define AHBSC3_SRAM_29_RULE_RULE0_MASK           (0x3U)
#define AHBSC3_SRAM_29_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_29_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_29_RULE_RULE0_SHIFT)) & AHBSC3_SRAM_29_RULE_RULE0_MASK)

#define AHBSC3_SRAM_29_RULE_RULE1_MASK           (0x30U)
#define AHBSC3_SRAM_29_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_29_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_29_RULE_RULE1_SHIFT)) & AHBSC3_SRAM_29_RULE_RULE1_MASK)

#define AHBSC3_SRAM_29_RULE_RULE2_MASK           (0x300U)
#define AHBSC3_SRAM_29_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_29_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_29_RULE_RULE2_SHIFT)) & AHBSC3_SRAM_29_RULE_RULE2_MASK)

#define AHBSC3_SRAM_29_RULE_RULE3_MASK           (0x3000U)
#define AHBSC3_SRAM_29_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_29_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_29_RULE_RULE3_SHIFT)) & AHBSC3_SRAM_29_RULE_RULE3_MASK)

#define AHBSC3_SRAM_29_RULE_RULE4_MASK           (0x30000U)
#define AHBSC3_SRAM_29_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_29_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_29_RULE_RULE4_SHIFT)) & AHBSC3_SRAM_29_RULE_RULE4_MASK)

#define AHBSC3_SRAM_29_RULE_RULE5_MASK           (0x300000U)
#define AHBSC3_SRAM_29_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_29_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_29_RULE_RULE5_SHIFT)) & AHBSC3_SRAM_29_RULE_RULE5_MASK)

#define AHBSC3_SRAM_29_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC3_SRAM_29_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_29_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_29_RULE_RULE6_SHIFT)) & AHBSC3_SRAM_29_RULE_RULE6_MASK)

#define AHBSC3_SRAM_29_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC3_SRAM_29_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SRAM_29_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC3_SRAM_29_RULE_RULE7_SHIFT)) & AHBSC3_SRAM_29_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC3_SRAM_29_RULE */
#define AHBSC3_SRAM_29_RULE_COUNT                (4U)

/*! @name AHB_PERIPHERAL10_SLAVE_RULE0 - AHB Peripheral 10 Slaves Rule Register 0 */
/*! @{ */

#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM17_MASK (0x30000U)
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM17_SHIFT (16U)
/*! LP_FLEXCOMM17 - LP_FLEXCOMM17
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM17(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM17_SHIFT)) & AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM17_MASK)

#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM18_MASK (0x300000U)
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM18_SHIFT (20U)
/*! LP_FLEXCOMM18 - LP_FLEXCOMM18
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM18(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM18_SHIFT)) & AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM18_MASK)

#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM19_MASK (0x3000000U)
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM19_SHIFT (24U)
/*! LP_FLEXCOMM19 - LP_FLEXCOMM19
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM19(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM19_SHIFT)) & AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM19_MASK)

#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM20_MASK (0x30000000U)
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM20_SHIFT (28U)
/*! LP_FLEXCOMM20 - LP_FLEXCOMM20
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM20(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM20_SHIFT)) & AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE0_LP_FLEXCOMM20_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL10_SLAVE_RULE1 - AHB Peripheral 10 Slaves Rule Register 1 */
/*! @{ */

#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG4_MASK (0x3U)
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG4_SHIFT (0U)
/*! CDOG4 - CDOG4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG4_SHIFT)) & AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG4_MASK)

#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG3_MASK (0x30U)
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG3_SHIFT (4U)
/*! CDOG3 - CDOG3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG3_SHIFT)) & AHBSC3_AHB_PERIPHERAL10_SLAVE_RULE1_CDOG3_MASK)
/*! @} */

/*! @name AIPS5_BRIDGE_GROUP0_MEM_RULE0 - AIPS5 Bridge Group 0 Memory Rule Register 0 */
/*! @{ */

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_MP_MASK (0x3U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_MP_SHIFT (0U)
/*! eDMA2_MP - eDMA2_MP management
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_MP_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_MP_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH0_MASK (0x30U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH0_SHIFT (4U)
/*! eDMA2_CH0 - eDMA2_CH0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH0_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH0_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH1_MASK (0x300U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH1_SHIFT (8U)
/*! eDMA2_CH1 - eDMA2_CH1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH1_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH1_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH2_MASK (0x3000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH2_SHIFT (12U)
/*! eDMA2_CH2 - eDMA2_CH2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH2_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH2_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH3_MASK (0x30000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH3_SHIFT (16U)
/*! eDMA2_CH3 - eDMA2_CH3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH3_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH3_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH4_MASK (0x300000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH4_SHIFT (20U)
/*! eDMA2_CH4 - eDMA2_CH4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH4_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH4_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH5_MASK (0x3000000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH5_SHIFT (24U)
/*! eDMA2_CH5 - eDMA2_CH5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH5_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH5_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH6_MASK (0x30000000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH6_SHIFT (28U)
/*! eDMA2_CH6 - eDMA2_CH6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH6_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE0_eDMA2_CH6_MASK)
/*! @} */

/*! @name AIPS5_BRIDGE_GROUP0_MEM_RULE1 - AIPS5 Bridge Group 0 Memory Rule Register 1 */
/*! @{ */

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE1_eDMA2_CH7_MASK (0x3U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE1_eDMA2_CH7_SHIFT (0U)
/*! eDMA2_CH7 - eDMA2_CH7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE1_eDMA2_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE1_eDMA2_CH7_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE1_eDMA2_CH7_MASK)
/*! @} */

/*! @name AIPS5_BRIDGE_GROUP0_MEM_RULE2 - AIPS5 Bridge Group 0 Memory Rule Register 2 */
/*! @{ */

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_MP_MASK (0x3U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_MP_SHIFT (0U)
/*! DMA_3_MP - DMA1 management
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_MP_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_MP_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH0_MASK (0x30U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH0_SHIFT (4U)
/*! DMA_3_CH0 - DMA1 channel 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH0_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH0_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH1_MASK (0x300U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH1_SHIFT (8U)
/*! DMA_3_CH1 - DMA1 channel 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH1_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH1_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH2_MASK (0x3000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH2_SHIFT (12U)
/*! DMA_3_CH2 - DMA1 channel 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH2_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH2_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH3_MASK (0x30000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH3_SHIFT (16U)
/*! DMA_3_CH3 - DMA1 channel 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH3_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH3_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH4_MASK (0x300000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH4_SHIFT (20U)
/*! DMA_3_CH4 - DMA1 channel 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH4_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH4_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH5_MASK (0x3000000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH5_SHIFT (24U)
/*! DMA_3_CH5 - DMA1 channel 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH5_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH5_MASK)

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH6_MASK (0x30000000U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH6_SHIFT (28U)
/*! DMA_3_CH6 - DMA1 channel 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH6_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE2_DMA_3_CH6_MASK)
/*! @} */

/*! @name AIPS5_BRIDGE_GROUP0_MEM_RULE3 - AIPS5 Bridge Group 0 Memory Rule Register 3 */
/*! @{ */

#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE3_DMA_3_CH7_MASK (0x3U)
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE3_DMA_3_CH7_SHIFT (0U)
/*! DMA_3_CH7 - DMA1 channel 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE3_DMA_3_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE3_DMA_3_CH7_SHIFT)) & AHBSC3_AIPS5_BRIDGE_GROUP0_MEM_RULE3_DMA_3_CH7_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL10_SLAVE_GPIO_RULE - AHB Peripheral 10 Slaves GPIO8 Rule Register..AHB Peripheral 10 Slaves GPIO10 Rule Register */
/*! @{ */

#define AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_MASK (0x3U)
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_SHIFT (0U)
/*! GPIOn - GPIOn_RULE0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_SHIFT)) & AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_MASK)

#define AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_ALIAS_MASK (0x30U)
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_ALIAS_SHIFT (4U)
/*! GPIOn_ALIAS - GPIOn_ALIAS
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_ALIAS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_ALIAS_SHIFT)) & AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_GPIOn_ALIAS_MASK)
/*! @} */

/* The count of AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE */
#define AHBSC3_AHB_PERIPHERAL10_SLAVE_GPIO_RULE_COUNT (3U)

/*! @name AIPS2_BRIDGE_GROUP0_MEM_RULE0 - AIPS2 Bridge Group 0 Memory Rule Register 0 */
/*! @{ */

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_B_MASK (0x30U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_B_SHIFT (4U)
/*! MU0_B - MU0_B (HIFI1 port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_B(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_B_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU0_B_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_B_MASK (0x3000U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_B_SHIFT (12U)
/*! MU1_B - MU1_B (M33_SENSE port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_B(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_B_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU1_B_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_B_MASK (0x300000U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_B_SHIFT (20U)
/*! MU2_B - MU2_B (M33_SENSE port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_B(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_B_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_MU2_B_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEM42_0_MASK (0x3000000U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEM42_0_SHIFT (24U)
/*! SEM42_0 - SEM42_0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEM42_0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEM42_0_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE0_SEM42_0_MASK)
/*! @} */

/*! @name AIPS2_BRIDGE_GROUP0_MEM_RULE1 - AIPS2 Bridge Group 0 Memory Rule Register 1 */
/*! @{ */

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS2_MASK (0x30U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS2_SHIFT (4U)
/*! OSTIMER_ALIAS2 - OSTIMER_ALIAS2 (M33 sense port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS2_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS2_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS3_MASK (0x300U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS3_SHIFT (8U)
/*! OSTIMER_ALIAS3 - OSTIMER_ALIAS3 (HIFI1 sense port)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS3_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_OSTIMER_ALIAS3_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0_MASK (0x3000U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0_SHIFT (12U)
/*! ACMP0 - ACMP0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ACMP0_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0_MASK (0x30000U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0_SHIFT (16U)
/*! ADC0 - ADC0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_ADC0_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC_MASK (0x300000U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC_SHIFT (20U)
/*! SDADC - SDADC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_SDADC_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL_MASK (0x3000000U)
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL_SHIFT (24U)
/*! MICFIL - MICFIL
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP0_MEM_RULE1_MICFIL_MASK)
/*! @} */

/*! @name AIPS2_BRIDGE_GROUP1_MEM_RULE0 - AIPS2 Bridge Group 1 Memory Rule Register 0 */
/*! @{ */

#define AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_PMC1_MASK (0x3U)
#define AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_PMC1_SHIFT (0U)
/*! PMC1 - PMC1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_PMC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_PMC1_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_PMC1_MASK)

#define AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15_MASK (0x3000U)
#define AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15_SHIFT (12U)
/*! LPI2C15 - LPI2C15
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15_SHIFT)) & AHBSC3_AIPS2_BRIDGE_GROUP1_MEM_RULE0_LPI2C15_MASK)
/*! @} */

/*! @name AHB_SECURE_CTRL_PERIPHERAL_RULE0 - AHB Secure Control Peripheral Rule 0 */
/*! @{ */

#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK (0x3U)
#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT)) & AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK)

#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK (0x30U)
#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT)) & AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK)

#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK (0x300U)
#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT)) & AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK)

#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK (0x3000U)
#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT)) & AHBSC3_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK)
/*! @} */

/*! @name SENSE_APB_SLAVE_GROUP0_RULE0 - APB Bridge Peripheral 0 Rule 0 */
/*! @{ */

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_RSTCTL1_MASK (0x3U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_RSTCTL1_SHIFT (0U)
/*! RSTCTL1 - RSTCTL1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_RSTCTL1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_RSTCTL1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_RSTCTL1_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_CLKCTL1_MASK (0x30U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_CLKCTL1_SHIFT (4U)
/*! CLKCTL1 - CLKCTL1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_CLKCTL1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_CLKCTL1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_CLKCTL1_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SYSCON1_MASK (0x300U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SYSCON1_SHIFT (8U)
/*! SYSCON1 - SYSCON1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SYSCON1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SYSCON1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SYSCON1_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PVTS1_MASK (0x3000U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PVTS1_SHIFT (12U)
/*! PVTS1 - PVTS1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PVTS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PVTS1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PVTS1_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SLEEPCON1_MASK (0x30000U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SLEEPCON1_SHIFT (16U)
/*! SLEEPCON1 - SLEEPCON1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SLEEPCON1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SLEEPCON1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_SLEEPCON1_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PINT1_MASK (0x300000U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PINT1_SHIFT (20U)
/*! PINT1 - PINT1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PINT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PINT1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_PINT1_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_INPUTMUX1_MASK (0x3000000U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_INPUTMUX1_SHIFT (24U)
/*! INPUTMUX1 - INPUTMUX1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_INPUTMUX1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_INPUTMUX1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE0_INPUTMUX1_MASK)
/*! @} */

/*! @name SENSE_APB_SLAVE_GROUP0_RULE1 - APB Bridge Peripheral 0 Rule Register 1 */
/*! @{ */

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER5_MASK (0x3U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER5_SHIFT (0U)
/*! CTIMER5 - CTIMER5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER5_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER5_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER6_MASK (0x30U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER6_SHIFT (4U)
/*! CTIMER6 - CTIMER6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER6_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER6_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER7_MASK (0x300U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER7_SHIFT (8U)
/*! CTIMER7 - CTIMER7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER7_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_CTIMER7_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_MRT1_MASK (0x300000U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_MRT1_SHIFT (20U)
/*! MRT1 - MRT1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_MRT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_MRT1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE1_MRT1_MASK)
/*! @} */

/*! @name SENSE_APB_SLAVE_GROUP0_RULE2 - APB Bridge Peripheral 0 Rule Register 2 */
/*! @{ */

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT2_MASK (0x3U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT2_SHIFT (0U)
/*! WWDT2 - WWDT2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT2_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT2_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT3_MASK (0x30U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT3_SHIFT (4U)
/*! WWDT3 - WWDT3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT3_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_WWDT3_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_UTICK1_MASK (0x300U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_UTICK1_SHIFT (8U)
/*! UTICK1 - UTICK1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_UTICK1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_UTICK1_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_UTICK1_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C2_MASK (0x3000000U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C2_SHIFT (24U)
/*! I3C2 - I3C2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C2_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C2_MASK)

#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C3_MASK (0x30000000U)
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C3_SHIFT (28U)
/*! I3C3 - I3C3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C3_SHIFT)) & AHBSC3_SENSE_APB_SLAVE_GROUP0_RULE2_I3C3_MASK)
/*! @} */

/*! @name SHARED_APB_SLAVE_GROUP0_RULE0 - Shared APB Bridge Peripheral 0 Rule 0 */
/*! @{ */

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3_MASK (0x3U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3_SHIFT (0U)
/*! RSTCTL3 - RSTCTL3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL3_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3_MASK (0x30U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3_SHIFT (4U)
/*! CLKCTL3 - CLKCTL3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL3_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3_MASK (0x300U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3_SHIFT (8U)
/*! SYSCON3 - SYSCON3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON3_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP_MASK (0x3000U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP_SHIFT (12U)
/*! OSC32KNP - OSC32KNP
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_OSC32KNP_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1_MASK (0x30000U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1_SHIFT (16U)
/*! IOPCTL1 - IOPCTL1 for sense domain
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_IOPCTL1_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2_MASK (0x300000U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2_SHIFT (20U)
/*! CLKCTL2 - Clock for common VDDN
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_CLKCTL2_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2_MASK (0x3000000U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2_SHIFT (24U)
/*! SYSCON2 - CLKCTL for common VDDN
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_SYSCON2_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2_MASK (0x30000000U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2_SHIFT (28U)
/*! RSTCTL2 - RSTCTL for common VDDN
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE0_RSTCTL2_MASK)
/*! @} */

/*! @name SHARED_APB_SLAVE_GROUP0_RULE1 - Shared APB Bridge Peripheral 0 Rule 1 */
/*! @{ */

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS0_MASK (0x3U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS0_SHIFT (0U)
/*! RTC_SS0 - RTC_SS0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS0_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS0_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS1_MASK (0x30U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS1_SHIFT (4U)
/*! RTC_SS1 - RTC_SS1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS1_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_RTC_SS1_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2_MASK (0x300U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2_SHIFT (8U)
/*! GDET2 - GDET2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET2_MASK)

#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3_MASK (0x3000U)
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3_SHIFT (12U)
/*! GDET3 - GDET3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3_SHIFT)) & AHBSC3_SHARED_APB_SLAVE_GROUP0_RULE1_GDET3_MASK)
/*! @} */

/*! @name SENSE2MEDIA_RULE - SENSE domain to MEDIA domain Access Rule Register */
/*! @{ */

#define AHBSC3_SENSE2MEDIA_RULE_XSPI2_MASK       (0x3U)
#define AHBSC3_SENSE2MEDIA_RULE_XSPI2_SHIFT      (0U)
/*! XSPI2 - XSPI2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_SENSE2MEDIA_RULE_XSPI2(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE2MEDIA_RULE_XSPI2_SHIFT)) & AHBSC3_SENSE2MEDIA_RULE_XSPI2_MASK)
/*! @} */

/*! @name MEDIA_AHB_PERIPHERAL_SLAVE_RULE0 - MEDIA domain AHB peripheral slave */
/*! @{ */

#define AHBSC3_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL_MASK (0x3U)
#define AHBSC3_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL_SHIFT (0U)
/*! MEDIA_AHB_PERIPHERAL - MEDIA domain AHB Peripheral Slave Rule Register
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL_SHIFT)) & AHBSC3_MEDIA_AHB_PERIPHERAL_SLAVE_RULE0_MEDIA_AHB_PERIPHERAL_MASK)
/*! @} */

/*! @name MEDIA_APB_PERIPHERAL_SLAVE_RULE0 - MEDIA domain APB peripheral slave Rule Register */
/*! @{ */

#define AHBSC3_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL_MASK (0x3U)
#define AHBSC3_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL_SHIFT (0U)
/*! MEDIA_APB_PERIPHERAL - MEDIA domain APB Peripheral Slave
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL_SHIFT)) & AHBSC3_MEDIA_APB_PERIPHERAL_SLAVE_RULE0_MEDIA_APB_PERIPHERAL_MASK)
/*! @} */

/*! @name EZHV_SRAM_RULE0 - EZHV SRAM Memory Rule Register */
/*! @{ */

#define AHBSC3_EZHV_SRAM_RULE0_EZHV_SRAM_MASK    (0x3U)
#define AHBSC3_EZHV_SRAM_RULE0_EZHV_SRAM_SHIFT   (0U)
/*! EZHV_SRAM - EZHV SRAM
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC3_EZHV_SRAM_RULE0_EZHV_SRAM(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC3_EZHV_SRAM_RULE0_EZHV_SRAM_SHIFT)) & AHBSC3_EZHV_SRAM_RULE0_EZHV_SRAM_MASK)
/*! @} */

/*! @name SEC_VIO_ADDR - Security Violation Address */
/*! @{ */

#define AHBSC3_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK    (0xFFFFFFFFU)
#define AHBSC3_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT   (0U)
/*! SEC_VIO_ADDR - Security violation address for AHB layer a reset value 0 */
#define AHBSC3_SEC_VIO_ADDR_SEC_VIO_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHBSC3_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
/*! @} */

/* The count of AHBSC3_SEC_VIO_ADDR */
#define AHBSC3_SEC_VIO_ADDR_COUNT                (17U)

/*! @name SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */
/*! @{ */

#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator
 *  0b0..Read access
 *  0b1..Write access
 */
#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)

#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access
 *  0b0..Code
 *  0b1..Data
 */
#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)

#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level */
#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)

#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0x1F00U)
#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
/*! SEC_VIO_INFO_MASTER - Security violation master number
 *  0b00000..CPU0 System
 *  0b00001..eDMA0
 *  0b00010..eDMA1
 *  0b00011..ELS
 *  0b00100..HIFI4
 *  0b00101..CPU1 system
 *  0b00110..eDMA2
 *  0b00111..eDMA3
 *  0b01000..HIFI1
 *  0b01001..EZH-V
 *  0b01010..PKC
 *  0b01011..USDHC0
 *  0b01100..USB0
 *  0b01101..GPU
 *  0b01110..ETR
 *  0b01111..DAP
 *  0b10000..CPU0 Code
 *  0b10001..Reserved
 *  0b10010..Reserved
 *  0b10011..Reserved
 *  0b10100..Reserved
 *  0b10101..CPU1 code
 *  0b10110..JPEGDEC
 *  0b10111..PNGDEC
 *  0b11000..Reserved
 *  0b11001..Reserved
 *  0b11010..Reserved
 *  0b11011..USDHC1
 *  0b11100..USB1
 *  0b11101..LCDIF
 *  0b11110..MTR
 *  0b11111..Test port
 */
#define AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHBSC3_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
/*! @} */

/* The count of AHBSC3_SEC_VIO_MISC_INFO */
#define AHBSC3_SEC_VIO_MISC_INFO_COUNT           (17U)

/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */
/*! @{ */

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U)
/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U)
/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U)
/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U)
/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK)

#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U)
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U)
/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHBSC3_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK)
/*! @} */

/*! @name COMPUTE_ARB1RAM_ACCESS_ENABLE - Access enable for COMPUTE domain masters to RAM partitions. */
/*! @{ */

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC3_COMPUTE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)
/*! @} */

/*! @name SENSE_ARB1RAM_ACCESS_ENABLE - Access enable for SENSE domain masters to RAM partitions. */
/*! @{ */

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC3_SENSE_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)
/*! @} */

/*! @name MEDIA_ARB1RAM_ACCESS_ENABLE - Access enable for MEDIA domain masters to RAM partitions. */
/*! @{ */

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC3_MEDIA_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)
/*! @} */

/*! @name NPU_ARB1RAM_ACCESS_ENABLE - Access enable for NPU to RAM partitions. */
/*! @{ */

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC3_NPU_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)
/*! @} */

/*! @name HIFI4_ARB1RAM_ACCESS_ENABLE - Access enable for HIFI4 to RAM partitions. */
/*! @{ */

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC3_HIFI4_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)
/*! @} */

/*! @name HIFI1_ARB1RAM_ACCESS_ENABLE - Access enable for HIFI1 to RAM partitions. */
/*! @{ */

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK (0x1U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT (0U)
/*! RAM_PARTITION_0_ACCESS_EN - Enable access to the Shared RAM partition 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_0_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK (0x2U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT (1U)
/*! RAM_PARTITION_1_ACCESS_EN - Enable access to the Shared RAM partition 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_1_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK (0x4U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT (2U)
/*! RAM_PARTITION_2_ACCESS_EN - Enable access to the Shared RAM partition 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_2_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK (0x8U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT (3U)
/*! RAM_PARTITION_3_ACCESS_EN - Enable access to the Shared RAM partition 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_3_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK (0x10U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT (4U)
/*! RAM_PARTITION_4_ACCESS_EN - Enable access to the Shared RAM partition 4
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_4_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK (0x20U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT (5U)
/*! RAM_PARTITION_5_ACCESS_EN - Enable access to the Shared RAM partition 5
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_5_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK (0x40U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT (6U)
/*! RAM_PARTITION_6_ACCESS_EN - Enable access to the Shared RAM partition 6
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_6_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK (0x80U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT (7U)
/*! RAM_PARTITION_7_ACCESS_EN - Enable access to the Shared RAM partition 7
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_7_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK (0x100U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT (8U)
/*! RAM_PARTITION_8_ACCESS_EN - Enable access to the Shared RAM partition 8
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_8_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK (0x200U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT (9U)
/*! RAM_PARTITION_9_ACCESS_EN - Enable access to the Shared RAM partition 9
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_9_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK (0x400U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT (10U)
/*! RAM_PARTITION_10_ACCESS_EN - Enable access to the Shared RAM partition 10
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_10_ACCESS_EN_MASK)

#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK (0x800U)
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT (11U)
/*! RAM_PARTITION_11_ACCESS_EN - Enable access to the Shared RAM partition 11
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_SHIFT)) & AHBSC3_HIFI1_ARB1RAM_ACCESS_ENABLE_RAM_PARTITION_11_ACCESS_EN_MASK)
/*! @} */

/*! @name COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE - Access enable for COMPUTE domain masters to common APB peripherals. */
/*! @{ */

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3_MASK (0x1U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3_SHIFT (0U)
/*! RSTCTL3 - Enable access to the common APB peripheral RSTCTL3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3_MASK (0x2U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3_SHIFT (1U)
/*! CLKCTL3 - Enable access to the common APB peripheral CLKCTL3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3_MASK (0x4U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3_SHIFT (2U)
/*! SYSCON3 - Enable access to the common APB peripheral SYSCON3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP_MASK (0x8U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP_SHIFT (3U)
/*! OSC32KNP - Enable access to the common APB peripheral OSC32KNP
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1_MASK (0x10U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1_SHIFT (4U)
/*! IOPCTL1 - Enable access to the common APB peripheral IOPCTL1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2_MASK (0x20U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2_SHIFT (5U)
/*! CLKCTL2 - Enable access to the common APB peripheral CLKCTL2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2_MASK (0x40U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2_SHIFT (6U)
/*! SYSCON2 - Enable access to the common APB peripheral SYSCON2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2_MASK (0x80U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2_SHIFT (7U)
/*! RSTCTL2 - Enable access to the common APB peripheral RSTCTL2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0_MASK (0x100U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0_SHIFT (8U)
/*! RTC0 - Enable access to the common APB peripheral RTC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1_MASK (0x200U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1_SHIFT (9U)
/*! RTC1 - Enable access to the common APB peripheral RTC1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2_MASK (0x400U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2_SHIFT (10U)
/*! GDET2 - Enable access to the common APB peripheral GDET2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2_MASK)

#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3_MASK (0x800U)
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3_SHIFT (11U)
/*! GDET3 - Enable access to the common APB peripheral GDET3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3_SHIFT)) & AHBSC3_COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3_MASK)
/*! @} */

/*! @name SENSE_APB_PERIPHERAL_ACCESS_ENABLE - Access enable for SENSE domain masters to common APB peripherals. */
/*! @{ */

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3_MASK (0x1U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3_SHIFT (0U)
/*! RSTCTL3 - Enable access to the common APB peripheral RSTCTL3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL3_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3_MASK (0x2U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3_SHIFT (1U)
/*! CLKCTL3 - Enable access to the common APB peripheral CLKCTL3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL3_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3_MASK (0x4U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3_SHIFT (2U)
/*! SYSCON3 - Enable access to the common APB peripheral SYSCON3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON3_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP_MASK (0x8U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP_SHIFT (3U)
/*! OSC32KNP - Enable access to the common APB peripheral OSC32KNP
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_OSC32KNP_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1_MASK (0x10U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1_SHIFT (4U)
/*! IOPCTL1 - Enable access to the common APB peripheral IOPCTL1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_IOPCTL1_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2_MASK (0x20U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2_SHIFT (5U)
/*! CLKCTL2 - Enable access to the common APB peripheral CLKCTL2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_CLKCTL2_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2_MASK (0x40U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2_SHIFT (6U)
/*! SYSCON2 - Enable access to the common APB peripheral SYSCON2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_SYSCON2_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2_MASK (0x80U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2_SHIFT (7U)
/*! RSTCTL2 - Enable access to the common APB peripheral RSTCTL2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RSTCTL2_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0_MASK (0x100U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0_SHIFT (8U)
/*! RTC0 - Enable access to the common APB peripheral RTC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC0_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1_MASK (0x200U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1_SHIFT (9U)
/*! RTC1 - Enable access to the common APB peripheral RTC1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_RTC1_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2_MASK (0x400U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2_SHIFT (10U)
/*! GDET2 - Enable access to the common APB peripheral GDET2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET2_MASK)

#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3_MASK (0x800U)
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3_SHIFT (11U)
/*! GDET3 - Enable access to the common APB peripheral GDET3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3_SHIFT)) & AHBSC3_SENSE_APB_PERIPHERAL_ACCESS_ENABLE_GDET3_MASK)
/*! @} */

/*! @name COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE - Access enable for COMPUTE domain masters to common AIPS peripherals. */
/*! @{ */

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_A_MASK (0x1U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_A_SHIFT (0U)
/*! MU0_A - Enable access to MU0_A
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_A(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_A_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_A_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_A_MASK (0x4U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_A_SHIFT (2U)
/*! MU1_A - Enable access to MU1_A
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_A(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_A_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_A_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_A_MASK (0x10U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_A_SHIFT (4U)
/*! MU2_A - Enable access to MU2_A
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_A(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_A_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_A_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0_MASK (0x40U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0_SHIFT (6U)
/*! SEMA42_0 - Enable access to SEMA42_0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_MASK (0x80U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_SHIFT (7U)
/*! OSTIMER - Enable access to OSTIMER
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS1_MASK (0x100U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS1_SHIFT (8U)
/*! OSTIMER_ALIAS1 - Enable access to OSTIMER_ALIAS1
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS1_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS1_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0_MASK (0x800U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0_SHIFT (11U)
/*! ACMP0 - Enable access to ACMP0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0_MASK (0x1000U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0_SHIFT (12U)
/*! ADC0 - Enable access to ADC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC_MASK (0x2000U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC_SHIFT (13U)
/*! SDADC - Enable access to SDADC
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL_MASK (0x4000U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL_SHIFT (14U)
/*! MICFIL - Enable access to MICFIL
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC0_MASK (0x8000U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC0_SHIFT (15U)
/*! PMC0 - Enable access to PMC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC0_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC0_MASK)

#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15_MASK (0x80000U)
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15_SHIFT (19U)
/*! LPI2C15 - Enable access to LPI2C15
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15_SHIFT)) & AHBSC3_COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15_MASK)
/*! @} */

/*! @name SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE - Access enable for SENSE domain masters to common AIPS peripherals. */
/*! @{ */

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_B_MASK (0x2U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_B_SHIFT (1U)
/*! MU0_B - Enable access to MU0_B
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_B(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_B_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU0_B_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_B_MASK (0x8U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_B_SHIFT (3U)
/*! MU1_B - Enable access to MU1_B
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_B(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_B_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU1_B_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_B_MASK (0x20U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_B_SHIFT (5U)
/*! MU2_B - Enable access to MU2_B
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_B(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_B_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MU2_B_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0_MASK (0x40U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0_SHIFT (6U)
/*! SEMA42_0 - Enable access to SEMA42_0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SEMA42_0_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS2_MASK (0x200U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS2_SHIFT (9U)
/*! OSTIMER_ALIAS2 - Enable access to OSTIMER_ALIAS2
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS2_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS2_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS3_MASK (0x400U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS3_SHIFT (10U)
/*! OSTIMER_ALIAS3 - Enable access to OSTIMER_ALIAS3
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS3_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_OSTIMER_ALIAS3_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0_MASK (0x800U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0_SHIFT (11U)
/*! ACMP0 - Enable access to ACMP0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ACMP0_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0_MASK (0x1000U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0_SHIFT (12U)
/*! ADC0 - Enable access to ADC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_ADC0_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC_MASK (0x2000U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC_SHIFT (13U)
/*! SDADC - Enable access to SDADC
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_SDADC_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL_MASK (0x4000U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL_SHIFT (14U)
/*! MICFIL - Enable access to MICFIL
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_MICFIL_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC1_MASK (0x10000U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC1_SHIFT (16U)
/*! PMC1 - Enable access to PMC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC1_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_PMC1_MASK)

#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15_MASK (0x80000U)
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15_SHIFT (19U)
/*! LPI2C15 - Enable access to LPI2C15
 *  0b0..Disable
 *  0b1..Enable
 */
#define AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15_SHIFT)) & AHBSC3_SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE_LPI2C15_MASK)
/*! @} */

/*! @name MASTER_SEC_LEVEL - Master Secure Level */
/*! @{ */

#define AHBSC3_MASTER_SEC_LEVEL_HIFI1_MASK       (0x3U)
#define AHBSC3_MASTER_SEC_LEVEL_HIFI1_SHIFT      (0U)
/*! HIFI1 - HIFI1
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC3_MASTER_SEC_LEVEL_HIFI1(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC3_MASTER_SEC_LEVEL_HIFI1_SHIFT)) & AHBSC3_MASTER_SEC_LEVEL_HIFI1_MASK)

#define AHBSC3_MASTER_SEC_LEVEL_MEDIA_MASK       (0xCU)
#define AHBSC3_MASTER_SEC_LEVEL_MEDIA_SHIFT      (2U)
/*! MEDIA - MEDIA
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC3_MASTER_SEC_LEVEL_MEDIA(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC3_MASTER_SEC_LEVEL_MEDIA_SHIFT)) & AHBSC3_MASTER_SEC_LEVEL_MEDIA_MASK)

#define AHBSC3_MASTER_SEC_LEVEL_DMA2_MASK        (0x30U)
#define AHBSC3_MASTER_SEC_LEVEL_DMA2_SHIFT       (4U)
/*! DMA2 - DMA2
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC3_MASTER_SEC_LEVEL_DMA2(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC3_MASTER_SEC_LEVEL_DMA2_SHIFT)) & AHBSC3_MASTER_SEC_LEVEL_DMA2_MASK)

#define AHBSC3_MASTER_SEC_LEVEL_DMA3_MASK        (0xC0U)
#define AHBSC3_MASTER_SEC_LEVEL_DMA3_SHIFT       (6U)
/*! DMA3 - DMA3
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC3_MASTER_SEC_LEVEL_DMA3(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC3_MASTER_SEC_LEVEL_DMA3_SHIFT)) & AHBSC3_MASTER_SEC_LEVEL_DMA3_MASK)
/*! @} */

/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */
/*! @{ */

#define AHBSC3_MASTER_SEC_ANTI_POL_REG_HIFI1_MASK (0x3U)
#define AHBSC3_MASTER_SEC_ANTI_POL_REG_HIFI1_SHIFT (0U)
/*! HIFI1 - HIFI1
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC3_MASTER_SEC_ANTI_POL_REG_HIFI1(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC3_MASTER_SEC_ANTI_POL_REG_HIFI1_SHIFT)) & AHBSC3_MASTER_SEC_ANTI_POL_REG_HIFI1_MASK)

#define AHBSC3_MASTER_SEC_ANTI_POL_REG_MEDIA_MASK (0xCU)
#define AHBSC3_MASTER_SEC_ANTI_POL_REG_MEDIA_SHIFT (2U)
/*! MEDIA - MEDIA
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC3_MASTER_SEC_ANTI_POL_REG_MEDIA(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC3_MASTER_SEC_ANTI_POL_REG_MEDIA_SHIFT)) & AHBSC3_MASTER_SEC_ANTI_POL_REG_MEDIA_MASK)

#define AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA2_MASK (0x30U)
#define AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA2_SHIFT (4U)
/*! DMA2 - DMA2
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA2(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA2_SHIFT)) & AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA2_MASK)

#define AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA3_MASK (0xC0U)
#define AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA3_SHIFT (6U)
/*! DMA3 - DMA3
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA3(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA3_SHIFT)) & AHBSC3_MASTER_SEC_ANTI_POL_REG_DMA3_MASK)
/*! @} */

/*! @name CPU1_LOCK_REG - Miscellaneous CPU1 Control Signals */
/*! @{ */

#define AHBSC3_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK   (0x3U)
#define AHBSC3_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT  (0U)
/*! LOCK_NS_VTOR - LOCK_NS_VTOR
 *  0b00..Reserved
 *  0b01..CM33 (CPU1) LOCKNSVTOR is 1
 *  0b10..CM33 (CPU1) LOCKNSVTOR is 0
 *  0b11..Reserved
 */
#define AHBSC3_CPU1_LOCK_REG_LOCK_NS_VTOR(x)     (((uint32_t)(((uint32_t)(x)) << AHBSC3_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC3_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK)

#define AHBSC3_CPU1_LOCK_REG_LOCK_NS_MPU_MASK    (0xCU)
#define AHBSC3_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT   (2U)
/*! LOCK_NS_MPU - LOCK_NS_MPU
 *  0b00..Reserved
 *  0b01..CM33 (CPU1) LOCK_NS_MPU is 1
 *  0b10..CM33 (CPU1) LOCK_NS_MPU is 0
 *  0b11..Reserved
 */
#define AHBSC3_CPU1_LOCK_REG_LOCK_NS_MPU(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC3_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC3_CPU1_LOCK_REG_LOCK_NS_MPU_MASK)

#define AHBSC3_CPU1_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
#define AHBSC3_CPU1_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
/*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR
 *  0b00..Reserved
 *  0b01..CM33 (CPU1) LOCK_S_VTAIRCR is 1
 *  0b10..CM33 (CPU1) LOCK_S_VTAIRCR is 0
 *  0b11..Reserved
 */
#define AHBSC3_CPU1_LOCK_REG_LOCK_S_VTAIRCR(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC3_CPU1_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHBSC3_CPU1_LOCK_REG_LOCK_S_VTAIRCR_MASK)

#define AHBSC3_CPU1_LOCK_REG_LOCK_S_MPU_MASK     (0xC0U)
#define AHBSC3_CPU1_LOCK_REG_LOCK_S_MPU_SHIFT    (6U)
/*! LOCK_S_MPU - LOCK_S_MPU
 *  0b00..Reserved
 *  0b01..CM33 (CPU1) LOCK_S_MPU is 1
 *  0b10..CM33 (CPU1) LOCK_S_MPU is 0
 *  0b11..Reserved
 */
#define AHBSC3_CPU1_LOCK_REG_LOCK_S_MPU(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC3_CPU1_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHBSC3_CPU1_LOCK_REG_LOCK_S_MPU_MASK)

#define AHBSC3_CPU1_LOCK_REG_LOCK_SAU_MASK       (0x300U)
#define AHBSC3_CPU1_LOCK_REG_LOCK_SAU_SHIFT      (8U)
/*! LOCK_SAU - LOCK_SAU
 *  0b00..Reserved
 *  0b01..CM33 (CPU1) LOCK_SAU is 1
 *  0b10..CM33 (CPU1) LOCK_SAU is 0
 *  0b11..Reserved
 */
#define AHBSC3_CPU1_LOCK_REG_LOCK_SAU(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC3_CPU1_LOCK_REG_LOCK_SAU_SHIFT)) & AHBSC3_CPU1_LOCK_REG_LOCK_SAU_MASK)
/*! @} */

/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */
/*! @{ */

#define AHBSC3_MISC_CTRL_DP_REG_WRITE_LOCK_MASK  (0x3U)
#define AHBSC3_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
/*! WRITE_LOCK - Write Lock
 *  0b00..Reserved
 *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
 *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_DP_REG_WRITE_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHBSC3_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)

#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC3_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)

#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC3_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)

#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC3_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)

#define AHBSC3_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define AHBSC3_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
 *  0b00..Reserved
 *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
 *        (interrupt request) will still be asserted and serviced by ISR.
 *  0b10..The violation detected by the secure checker will cause an abort.
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC3_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)

#define AHBSC3_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
#define AHBSC3_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U)
/*! DISABLE_STRICT_MODE - Disable Strict Mode
 *  0b00..AHB master in strict mode
 *  0b01..AHB master in tier mode. Can read and write to memories at same or below level.
 *  0b10..AHB master in strict mode
 *  0b11..AHB master in strict mode
 */
#define AHBSC3_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC3_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK)

#define AHBSC3_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
#define AHBSC3_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
/*! IDAU_ALL_NS - IDAU All Non-Secure
 *  0b00..Reserved
 *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
 *  0b10..IDAU is enabled (restrictive mode)
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_DP_REG_IDAU_ALL_NS(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHBSC3_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
/*! @} */

/*! @name MISC_CTRL_REG - Secure Control */
/*! @{ */

#define AHBSC3_MISC_CTRL_REG_WRITE_LOCK_MASK     (0x3U)
#define AHBSC3_MISC_CTRL_REG_WRITE_LOCK_SHIFT    (0U)
/*! WRITE_LOCK - Write Lock
 *  0b00..Reserved
 *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
 *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_REG_WRITE_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHBSC3_MISC_CTRL_REG_WRITE_LOCK_MASK)

#define AHBSC3_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define AHBSC3_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC3_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)

#define AHBSC3_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define AHBSC3_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC3_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)

#define AHBSC3_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define AHBSC3_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC3_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)

#define AHBSC3_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define AHBSC3_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
 *  0b00..Reserved
 *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
 *        (interrupt request) will still be asserted and serviced by ISR.
 *  0b10..The violation detected by the secure checker will cause an abort.
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC3_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)

#define AHBSC3_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
#define AHBSC3_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U)
/*! DISABLE_STRICT_MODE - Disable Strict Mode
 *  0b00..AHB master in strict mode
 *  0b01..AHB master in tier mode. Can read and write to memories at same or below level.
 *  0b10..AHB master in strict mode
 *  0b11..AHB master in strict mode
 */
#define AHBSC3_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC3_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK)

#define AHBSC3_MISC_CTRL_REG_IDAU_ALL_NS_MASK    (0xC000U)
#define AHBSC3_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT   (14U)
/*! IDAU_ALL_NS - IDAU All Non-Secure
 *  0b00..Reserved
 *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
 *  0b10..IDAU is enabled (restrictive mode)
 *  0b11..Reserved
 */
#define AHBSC3_MISC_CTRL_REG_IDAU_ALL_NS(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC3_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHBSC3_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AHBSC3_Register_Masks */


/* AHBSC3 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral AHBSC3 base address */
  #define AHBSC3_BASE                              (0x50220000u)
  /** Peripheral AHBSC3 base address */
  #define AHBSC3_BASE_NS                           (0x40220000u)
  /** Peripheral AHBSC3 base pointer */
  #define AHBSC3                                   ((AHBSC3_Type *)AHBSC3_BASE)
  /** Peripheral AHBSC3 base pointer */
  #define AHBSC3_NS                                ((AHBSC3_Type *)AHBSC3_BASE_NS)
  /** Peripheral AHBSC3_ALIAS1 base address */
  #define AHBSC3_ALIAS1_BASE                       (0x50221000u)
  /** Peripheral AHBSC3_ALIAS1 base address */
  #define AHBSC3_ALIAS1_BASE_NS                    (0x40221000u)
  /** Peripheral AHBSC3_ALIAS1 base pointer */
  #define AHBSC3_ALIAS1                            ((AHBSC3_Type *)AHBSC3_ALIAS1_BASE)
  /** Peripheral AHBSC3_ALIAS1 base pointer */
  #define AHBSC3_ALIAS1_NS                         ((AHBSC3_Type *)AHBSC3_ALIAS1_BASE_NS)
  /** Peripheral AHBSC3_ALIAS2 base address */
  #define AHBSC3_ALIAS2_BASE                       (0x50222000u)
  /** Peripheral AHBSC3_ALIAS2 base address */
  #define AHBSC3_ALIAS2_BASE_NS                    (0x40222000u)
  /** Peripheral AHBSC3_ALIAS2 base pointer */
  #define AHBSC3_ALIAS2                            ((AHBSC3_Type *)AHBSC3_ALIAS2_BASE)
  /** Peripheral AHBSC3_ALIAS2 base pointer */
  #define AHBSC3_ALIAS2_NS                         ((AHBSC3_Type *)AHBSC3_ALIAS2_BASE_NS)
  /** Peripheral AHBSC3_ALIAS3 base address */
  #define AHBSC3_ALIAS3_BASE                       (0x50223000u)
  /** Peripheral AHBSC3_ALIAS3 base address */
  #define AHBSC3_ALIAS3_BASE_NS                    (0x40223000u)
  /** Peripheral AHBSC3_ALIAS3 base pointer */
  #define AHBSC3_ALIAS3                            ((AHBSC3_Type *)AHBSC3_ALIAS3_BASE)
  /** Peripheral AHBSC3_ALIAS3 base pointer */
  #define AHBSC3_ALIAS3_NS                         ((AHBSC3_Type *)AHBSC3_ALIAS3_BASE_NS)
  /** Array initializer of AHBSC3 peripheral base addresses */
  #define AHBSC3_BASE_ADDRS                        { AHBSC3_BASE, AHBSC3_ALIAS1_BASE, AHBSC3_ALIAS2_BASE, AHBSC3_ALIAS3_BASE }
  /** Array initializer of AHBSC3 peripheral base pointers */
  #define AHBSC3_BASE_PTRS                         { AHBSC3, AHBSC3_ALIAS1, AHBSC3_ALIAS2, AHBSC3_ALIAS3 }
  /** Array initializer of AHBSC3 peripheral base addresses */
  #define AHBSC3_BASE_ADDRS_NS                     { AHBSC3_BASE_NS, AHBSC3_ALIAS1_BASE_NS, AHBSC3_ALIAS2_BASE_NS, AHBSC3_ALIAS3_BASE_NS }
  /** Array initializer of AHBSC3 peripheral base pointers */
  #define AHBSC3_BASE_PTRS_NS                      { AHBSC3_NS, AHBSC3_ALIAS1_NS, AHBSC3_ALIAS2_NS, AHBSC3_ALIAS3_NS }
#else
  /** Peripheral AHBSC3 base address */
  #define AHBSC3_BASE                              (0x40220000u)
  /** Peripheral AHBSC3 base pointer */
  #define AHBSC3                                   ((AHBSC3_Type *)AHBSC3_BASE)
  /** Peripheral AHBSC3_ALIAS1 base address */
  #define AHBSC3_ALIAS1_BASE                       (0x40221000u)
  /** Peripheral AHBSC3_ALIAS1 base pointer */
  #define AHBSC3_ALIAS1                            ((AHBSC3_Type *)AHBSC3_ALIAS1_BASE)
  /** Peripheral AHBSC3_ALIAS2 base address */
  #define AHBSC3_ALIAS2_BASE                       (0x40222000u)
  /** Peripheral AHBSC3_ALIAS2 base pointer */
  #define AHBSC3_ALIAS2                            ((AHBSC3_Type *)AHBSC3_ALIAS2_BASE)
  /** Peripheral AHBSC3_ALIAS3 base address */
  #define AHBSC3_ALIAS3_BASE                       (0x40223000u)
  /** Peripheral AHBSC3_ALIAS3 base pointer */
  #define AHBSC3_ALIAS3                            ((AHBSC3_Type *)AHBSC3_ALIAS3_BASE)
  /** Array initializer of AHBSC3 peripheral base addresses */
  #define AHBSC3_BASE_ADDRS                        { AHBSC3_BASE, AHBSC3_ALIAS1_BASE, AHBSC3_ALIAS2_BASE, AHBSC3_ALIAS3_BASE }
  /** Array initializer of AHBSC3 peripheral base pointers */
  #define AHBSC3_BASE_PTRS                         { AHBSC3, AHBSC3_ALIAS1, AHBSC3_ALIAS2, AHBSC3_ALIAS3 }
#endif

/*!
 * @}
 */ /* end of group AHBSC3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AHBSC4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AHBSC4_Peripheral_Access_Layer AHBSC4 Peripheral Access Layer
 * @{
 */

/** AHBSC4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t AHB_PERIPHERAL_SLAVE_P0_SLAVE_RULE0; /**< AHB peripheral 0 Rule Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_RULE0;  /**< AHB Secure Control Peripheral Rule Register 0, offset: 0x10 */
       uint8_t RESERVED_1[12];
  __IO uint32_t AIPS4_BRIDGE_MEM_RULE0;            /**< AIPS4 Bridge Rule Register 0, offset: 0x20 */
  __IO uint32_t AIPS4_BRIDGE_MEM_RULE1;            /**< AIPS4 Bridge Rule Register 1, offset: 0x24 */
       uint8_t RESERVED_2[8];
  __IO uint32_t AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0; /**< AHB peripheral 1 Rule Register, offset: 0x30 */
       uint8_t RESERVED_3[28];
  __IO uint32_t MEDIA_APB_SLAVE_GROUP0_RULE0;      /**< APB Bridge Peripheral 0 Rule 0, offset: 0x50 */
  __IO uint32_t MEDIA_APB_SLAVE_GROUP0_RULE1;      /**< APB Bridge Peripheral 0 Rule Register 1, offset: 0x54 */
       uint8_t RESERVED_4[24];
  __IO uint32_t EZHV_SRAM_RULE[4];                 /**< EZHV SRAM Rule Register, array offset: 0x70, array step: 0x4 */
  __IO uint32_t SRAM_0_RULE[4];                    /**< RAM partition 0 Memory Rule Register, array offset: 0x80, array step: 0x4 */
  __IO uint32_t SRAM_1_RULE[4];                    /**< RAM partition 1 Memory Rule Register, array offset: 0x90, array step: 0x4 */
  __IO uint32_t SRAM_2_RULE[4];                    /**< RAM partition 2 Memory Rule Register, array offset: 0xA0, array step: 0x4 */
  __IO uint32_t SRAM_3_RULE[4];                    /**< RAM partition 3 Memory Rule Register, array offset: 0xB0, array step: 0x4 */
  __IO uint32_t SRAM_4_RULE[4];                    /**< RAM partition 4 Memory Rule Register, array offset: 0xC0, array step: 0x4 */
  __IO uint32_t SRAM_5_RULE[4];                    /**< RAM partition 5 Memory Rule Register, array offset: 0xD0, array step: 0x4 */
  __IO uint32_t SRAM_6_RULE[4];                    /**< RAM partition 6 Memory Rule Register, array offset: 0xE0, array step: 0x4 */
  __IO uint32_t SRAM_7_RULE[4];                    /**< RAM partition 7 Memory Rule Register, array offset: 0xF0, array step: 0x4 */
  __IO uint32_t SRAM_8_RULE[4];                    /**< RAM partition 8 Memory Rule Register, array offset: 0x100, array step: 0x4 */
  __IO uint32_t SRAM_9_RULE[4];                    /**< RAM partition 9 Memory Rule Register, array offset: 0x110, array step: 0x4 */
  __IO uint32_t SRAM_10_RULE[4];                   /**< RAM partition 10 Memory Rule Register, array offset: 0x120, array step: 0x4 */
  __IO uint32_t SRAM_11_RULE[4];                   /**< RAM partition 11 Memory Rule Register, array offset: 0x130, array step: 0x4 */
  __IO uint32_t SRAM_12_RULE[4];                   /**< RAM partition 12 Memory Rule Register, array offset: 0x140, array step: 0x4 */
  __IO uint32_t SRAM_13_RULE[4];                   /**< RAM partition 13 Memory Rule Register, array offset: 0x150, array step: 0x4 */
  __IO uint32_t SRAM_14_RULE[4];                   /**< RAM partition 14 Memory Rule Register, array offset: 0x160, array step: 0x4 */
  __IO uint32_t SRAM_15_RULE[4];                   /**< RAM partition 15 Memory Rule Register, array offset: 0x170, array step: 0x4 */
  __IO uint32_t SRAM_16_RULE[4];                   /**< RAM partition 16 Memory Rule Register, array offset: 0x180, array step: 0x4 */
  __IO uint32_t SRAM_17_RULE[4];                   /**< RAM partition 17 Memory Rule Register, array offset: 0x190, array step: 0x4 */
  __IO uint32_t SRAM_18_RULE[4];                   /**< RAM partition 18 Memory Rule Register, array offset: 0x1A0, array step: 0x4 */
  __IO uint32_t SRAM_19_RULE[4];                   /**< RAM partition 19 Memory Rule Register, array offset: 0x1B0, array step: 0x4 */
  __IO uint32_t SRAM_20_RULE[4];                   /**< RAM partition 20 Memory Rule Register, array offset: 0x1C0, array step: 0x4 */
  __IO uint32_t SRAM_21_RULE[4];                   /**< RAM partition 21 Memory Rule Register, array offset: 0x1D0, array step: 0x4 */
  __IO uint32_t SRAM_22_RULE[4];                   /**< RAM partition 22 Memory Rule Register, array offset: 0x1E0, array step: 0x4 */
  __IO uint32_t SRAM_23_RULE[4];                   /**< RAM partition 23 Memory Rule Register, array offset: 0x1F0, array step: 0x4 */
  __IO uint32_t SRAM_24_RULE[4];                   /**< RAM partition 24 Memory Rule Register, array offset: 0x200, array step: 0x4 */
  __IO uint32_t SRAM_25_RULE[4];                   /**< RAM partition 25 Memory Rule Register, array offset: 0x210, array step: 0x4 */
  __IO uint32_t SRAM_26_RULE[4];                   /**< RAM partition 26 Memory Rule Register, array offset: 0x220, array step: 0x4 */
  __IO uint32_t SRAM_27_RULE[4];                   /**< RAM partition 27 Memory Rule Register, array offset: 0x230, array step: 0x4 */
  __IO uint32_t SRAM_28_RULE[4];                   /**< RAM partition 28 Memory Rule Register, array offset: 0x240, array step: 0x4 */
  __IO uint32_t SRAM_29_RULE[4];                   /**< RAM partition 29 Memory Rule Register, array offset: 0x250, array step: 0x4 */
  __IO uint32_t XSPI2_REGION0_MEM_RULE[4];         /**< XSPI2 Region0 Memory Rule Register, array offset: 0x260, array step: 0x4 */
  struct {                                         /* offset: 0x270, array step: 0x10 */
    __IO uint32_t XSPI2_REGION_MEM_RULE0;            /**< XSPI2 Region 1 Memory Rule Register..XSPI2 Region 5 Memory Rule Register, array offset: 0x270, array step: 0x10 */
         uint8_t RESERVED_0[12];
  } XSPI2_REGION1_5_MEM_RULE[5];
       uint8_t RESERVED_5[2880];
  __I  uint32_t SEC_VIO_ADDR[13];                  /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */
       uint8_t RESERVED_6[76];
  __I  uint32_t SEC_VIO_MISC_INFO[13];             /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */
       uint8_t RESERVED_7[76];
  __IO uint32_t SEC_VIO_INFO_VALID;                /**< Security Violation Info Validity for Address, offset: 0xF00 */
       uint8_t RESERVED_8[204];
  __IO uint32_t MASTER_SEC_LEVEL;                  /**< Master Secure Level, offset: 0xFD0 */
  __IO uint32_t MASTER_SEC_ANTI_POL_REG;           /**< Master Secure Level, offset: 0xFD4 */
       uint8_t RESERVED_9[32];
  __IO uint32_t MISC_CTRL_DP_REG;                  /**< Secure Control Duplicate, offset: 0xFF8 */
  __IO uint32_t MISC_CTRL_REG;                     /**< Secure Control, offset: 0xFFC */
} AHBSC4_Type;

/* ----------------------------------------------------------------------------
   -- AHBSC4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AHBSC4_Register_Masks AHBSC4 Register Masks
 * @{
 */

/*! @name AHB_PERIPHERAL_SLAVE_P0_SLAVE_RULE0 - AHB peripheral 0 Rule Register */
/*! @{ */

#define AHBSC4_AHB_PERIPHERAL_SLAVE_P0_SLAVE_RULE0_LPSPI16_MASK (0x30U)
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P0_SLAVE_RULE0_LPSPI16_SHIFT (4U)
/*! LPSPI16 - LPSPI16
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P0_SLAVE_RULE0_LPSPI16(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_PERIPHERAL_SLAVE_P0_SLAVE_RULE0_LPSPI16_SHIFT)) & AHBSC4_AHB_PERIPHERAL_SLAVE_P0_SLAVE_RULE0_LPSPI16_MASK)
/*! @} */

/*! @name AHB_SECURE_CTRL_PERIPHERAL_RULE0 - AHB Secure Control Peripheral Rule Register 0 */
/*! @{ */

#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK (0x3U)
#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT)) & AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK)

#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK (0x30U)
#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT)) & AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK)

#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK (0x300U)
#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT)) & AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK)

#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK (0x3000U)
#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT)) & AHBSC4_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK)
/*! @} */

/*! @name AIPS4_BRIDGE_MEM_RULE0 - AIPS4 Bridge Rule Register 0 */
/*! @{ */

#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_XSPI2_MASK (0x30U)
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_XSPI2_SHIFT (4U)
/*! XSPI2 - XSPI2 registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_XSPI2(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_AIPS4_BRIDGE_MEM_RULE0_XSPI2_SHIFT)) & AHBSC4_AIPS4_BRIDGE_MEM_RULE0_XSPI2_MASK)

#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC0_MASK (0x300U)
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC0_SHIFT (8U)
/*! USDHC0 - USDHC0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC0(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC0_SHIFT)) & AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC0_MASK)

#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC1_MASK (0x3000U)
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC1_SHIFT (12U)
/*! USDHC1 - USDHC1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC1(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC1_SHIFT)) & AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USDHC1_MASK)

#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USBPHY_MASK (0x30000U)
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USBPHY_SHIFT (16U)
/*! USBPHY - USBPHY registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USBPHY(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USBPHY_SHIFT)) & AHBSC4_AIPS4_BRIDGE_MEM_RULE0_USBPHY_MASK)

#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_FLEXIO_MASK (0x3000000U)
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_FLEXIO_SHIFT (24U)
/*! FLEXIO - FLEXIO registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_FLEXIO(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC4_AIPS4_BRIDGE_MEM_RULE0_FLEXIO_SHIFT)) & AHBSC4_AIPS4_BRIDGE_MEM_RULE0_FLEXIO_MASK)

#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_MIPI_DSI_HOST_MASK (0x30000000U)
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_MIPI_DSI_HOST_SHIFT (28U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Host Controller
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE0_MIPI_DSI_HOST(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AIPS4_BRIDGE_MEM_RULE0_MIPI_DSI_HOST_SHIFT)) & AHBSC4_AIPS4_BRIDGE_MEM_RULE0_MIPI_DSI_HOST_MASK)
/*! @} */

/*! @name AIPS4_BRIDGE_MEM_RULE1 - AIPS4 Bridge Rule Register 1 */
/*! @{ */

#define AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB0_MASK  (0x3U)
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB0_SHIFT (0U)
/*! USB0 - USB0 registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB0(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB0_SHIFT)) & AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB0_MASK)

#define AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB1_MASK  (0x30U)
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB1_SHIFT (4U)
/*! USB1 - USB1 registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB1(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB1_SHIFT)) & AHBSC4_AIPS4_BRIDGE_MEM_RULE1_USB1_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0 - AHB peripheral 1 Rule Register */
/*! @{ */

#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LCDIF_MASK (0x3U)
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LCDIF_SHIFT (0U)
/*! LCDIF - LCDIF
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LCDIF_SHIFT)) & AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LCDIF_MASK)

#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LPSPI14_MASK (0x30U)
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LPSPI14_SHIFT (4U)
/*! LPSPI14 - LPSPI14
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LPSPI14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LPSPI14_SHIFT)) & AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_LPSPI14_MASK)

#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_VGPU_MASK (0x3000U)
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_VGPU_SHIFT (12U)
/*! VGPU - VGPU
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_VGPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_VGPU_SHIFT)) & AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_VGPU_MASK)

#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_NIC_MEDIA1_AXI_SWITCH_MASK (0x30000U)
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_NIC_MEDIA1_AXI_SWITCH_SHIFT (16U)
/*! NIC_MEDIA1_AXI_SWITCH - NIC_MEDIA1(AXI_SWITCH)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_NIC_MEDIA1_AXI_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_NIC_MEDIA1_AXI_SWITCH_SHIFT)) & AHBSC4_AHB_PERIPHERAL_SLAVE_P1_SLAVE_RULE0_NIC_MEDIA1_AXI_SWITCH_MASK)
/*! @} */

/*! @name MEDIA_APB_SLAVE_GROUP0_RULE0 - APB Bridge Peripheral 0 Rule 0 */
/*! @{ */

#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_RSTCTL4_MASK (0x3U)
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_RSTCTL4_SHIFT (0U)
/*! RSTCTL4 - RSTCTL4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_RSTCTL4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_RSTCTL4_SHIFT)) & AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_RSTCTL4_MASK)

#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_CLKCTL4_MASK (0x30U)
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_CLKCTL4_SHIFT (4U)
/*! CLKCTL4 - CLKCTL4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_CLKCTL4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_CLKCTL4_SHIFT)) & AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_CLKCTL4_MASK)

#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_SYSCON4_MASK (0x300U)
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_SYSCON4_SHIFT (8U)
/*! SYSCON4 - SYSCON4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_SYSCON4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_SYSCON4_SHIFT)) & AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_SYSCON4_MASK)

#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_IOPCTL2_MASK (0x300000U)
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_IOPCTL2_SHIFT (20U)
/*! IOPCTL2 - IOPCTL2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_IOPCTL2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_IOPCTL2_SHIFT)) & AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_IOPCTL2_MASK)

#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_JPEGDEC_MASK (0x3000000U)
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_JPEGDEC_SHIFT (24U)
/*! JPEGDEC - JPEGDEC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_JPEGDEC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_JPEGDEC_SHIFT)) & AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_JPEGDEC_MASK)

#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_PNGDEC_MASK (0x30000000U)
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_PNGDEC_SHIFT (28U)
/*! PNGDEC - JPEG
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_PNGDEC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_PNGDEC_SHIFT)) & AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE0_PNGDEC_MASK)
/*! @} */

/*! @name MEDIA_APB_SLAVE_GROUP0_RULE1 - APB Bridge Peripheral 0 Rule Register 1 */
/*! @{ */

#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE1_MMU2_MASK (0x3U)
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE1_MMU2_SHIFT (0U)
/*! MMU2 - MMU2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE1_MMU2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE1_MMU2_SHIFT)) & AHBSC4_MEDIA_APB_SLAVE_GROUP0_RULE1_MMU2_MASK)
/*! @} */

/*! @name EZHV_SRAM_RULE - EZHV SRAM Rule Register */
/*! @{ */

#define AHBSC4_EZHV_SRAM_RULE_RULE0_MASK         (0x3U)
#define AHBSC4_EZHV_SRAM_RULE_RULE0_SHIFT        (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_EZHV_SRAM_RULE_RULE0(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_EZHV_SRAM_RULE_RULE0_SHIFT)) & AHBSC4_EZHV_SRAM_RULE_RULE0_MASK)

#define AHBSC4_EZHV_SRAM_RULE_RULE1_MASK         (0x30U)
#define AHBSC4_EZHV_SRAM_RULE_RULE1_SHIFT        (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_EZHV_SRAM_RULE_RULE1(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_EZHV_SRAM_RULE_RULE1_SHIFT)) & AHBSC4_EZHV_SRAM_RULE_RULE1_MASK)

#define AHBSC4_EZHV_SRAM_RULE_RULE2_MASK         (0x300U)
#define AHBSC4_EZHV_SRAM_RULE_RULE2_SHIFT        (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_EZHV_SRAM_RULE_RULE2(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_EZHV_SRAM_RULE_RULE2_SHIFT)) & AHBSC4_EZHV_SRAM_RULE_RULE2_MASK)

#define AHBSC4_EZHV_SRAM_RULE_RULE3_MASK         (0x3000U)
#define AHBSC4_EZHV_SRAM_RULE_RULE3_SHIFT        (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_EZHV_SRAM_RULE_RULE3(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_EZHV_SRAM_RULE_RULE3_SHIFT)) & AHBSC4_EZHV_SRAM_RULE_RULE3_MASK)

#define AHBSC4_EZHV_SRAM_RULE_RULE4_MASK         (0x30000U)
#define AHBSC4_EZHV_SRAM_RULE_RULE4_SHIFT        (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_EZHV_SRAM_RULE_RULE4(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_EZHV_SRAM_RULE_RULE4_SHIFT)) & AHBSC4_EZHV_SRAM_RULE_RULE4_MASK)

#define AHBSC4_EZHV_SRAM_RULE_RULE5_MASK         (0x300000U)
#define AHBSC4_EZHV_SRAM_RULE_RULE5_SHIFT        (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_EZHV_SRAM_RULE_RULE5(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_EZHV_SRAM_RULE_RULE5_SHIFT)) & AHBSC4_EZHV_SRAM_RULE_RULE5_MASK)

#define AHBSC4_EZHV_SRAM_RULE_RULE6_MASK         (0x3000000U)
#define AHBSC4_EZHV_SRAM_RULE_RULE6_SHIFT        (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_EZHV_SRAM_RULE_RULE6(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_EZHV_SRAM_RULE_RULE6_SHIFT)) & AHBSC4_EZHV_SRAM_RULE_RULE6_MASK)

#define AHBSC4_EZHV_SRAM_RULE_RULE7_MASK         (0x30000000U)
#define AHBSC4_EZHV_SRAM_RULE_RULE7_SHIFT        (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_EZHV_SRAM_RULE_RULE7(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_EZHV_SRAM_RULE_RULE7_SHIFT)) & AHBSC4_EZHV_SRAM_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_EZHV_SRAM_RULE */
#define AHBSC4_EZHV_SRAM_RULE_COUNT              (4U)

/*! @name SRAM_0_RULE - RAM partition 0 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_0_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_0_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_0_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_0_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_0_RULE_RULE0_MASK)

#define AHBSC4_SRAM_0_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_0_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_0_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_0_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_0_RULE_RULE1_MASK)

#define AHBSC4_SRAM_0_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_0_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_0_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_0_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_0_RULE_RULE2_MASK)

#define AHBSC4_SRAM_0_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_0_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_0_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_0_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_0_RULE_RULE3_MASK)

#define AHBSC4_SRAM_0_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_0_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_0_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_0_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_0_RULE_RULE4_MASK)

#define AHBSC4_SRAM_0_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_0_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_0_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_0_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_0_RULE_RULE5_MASK)

#define AHBSC4_SRAM_0_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_0_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_0_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_0_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_0_RULE_RULE6_MASK)

#define AHBSC4_SRAM_0_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_0_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_0_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_0_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_0_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_0_RULE */
#define AHBSC4_SRAM_0_RULE_COUNT                 (4U)

/*! @name SRAM_1_RULE - RAM partition 1 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_1_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_1_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_1_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_1_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_1_RULE_RULE0_MASK)

#define AHBSC4_SRAM_1_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_1_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_1_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_1_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_1_RULE_RULE1_MASK)

#define AHBSC4_SRAM_1_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_1_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_1_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_1_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_1_RULE_RULE2_MASK)

#define AHBSC4_SRAM_1_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_1_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_1_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_1_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_1_RULE_RULE3_MASK)

#define AHBSC4_SRAM_1_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_1_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_1_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_1_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_1_RULE_RULE4_MASK)

#define AHBSC4_SRAM_1_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_1_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_1_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_1_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_1_RULE_RULE5_MASK)

#define AHBSC4_SRAM_1_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_1_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_1_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_1_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_1_RULE_RULE6_MASK)

#define AHBSC4_SRAM_1_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_1_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_1_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_1_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_1_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_1_RULE */
#define AHBSC4_SRAM_1_RULE_COUNT                 (4U)

/*! @name SRAM_2_RULE - RAM partition 2 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_2_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_2_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_2_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_2_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_2_RULE_RULE0_MASK)

#define AHBSC4_SRAM_2_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_2_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_2_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_2_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_2_RULE_RULE1_MASK)

#define AHBSC4_SRAM_2_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_2_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_2_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_2_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_2_RULE_RULE2_MASK)

#define AHBSC4_SRAM_2_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_2_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_2_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_2_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_2_RULE_RULE3_MASK)

#define AHBSC4_SRAM_2_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_2_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_2_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_2_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_2_RULE_RULE4_MASK)

#define AHBSC4_SRAM_2_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_2_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_2_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_2_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_2_RULE_RULE5_MASK)

#define AHBSC4_SRAM_2_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_2_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_2_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_2_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_2_RULE_RULE6_MASK)

#define AHBSC4_SRAM_2_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_2_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_2_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_2_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_2_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_2_RULE */
#define AHBSC4_SRAM_2_RULE_COUNT                 (4U)

/*! @name SRAM_3_RULE - RAM partition 3 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_3_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_3_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_3_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_3_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_3_RULE_RULE0_MASK)

#define AHBSC4_SRAM_3_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_3_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_3_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_3_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_3_RULE_RULE1_MASK)

#define AHBSC4_SRAM_3_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_3_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_3_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_3_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_3_RULE_RULE2_MASK)

#define AHBSC4_SRAM_3_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_3_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_3_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_3_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_3_RULE_RULE3_MASK)

#define AHBSC4_SRAM_3_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_3_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_3_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_3_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_3_RULE_RULE4_MASK)

#define AHBSC4_SRAM_3_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_3_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_3_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_3_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_3_RULE_RULE5_MASK)

#define AHBSC4_SRAM_3_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_3_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_3_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_3_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_3_RULE_RULE6_MASK)

#define AHBSC4_SRAM_3_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_3_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_3_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_3_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_3_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_3_RULE */
#define AHBSC4_SRAM_3_RULE_COUNT                 (4U)

/*! @name SRAM_4_RULE - RAM partition 4 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_4_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_4_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_4_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_4_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_4_RULE_RULE0_MASK)

#define AHBSC4_SRAM_4_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_4_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_4_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_4_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_4_RULE_RULE1_MASK)

#define AHBSC4_SRAM_4_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_4_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_4_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_4_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_4_RULE_RULE2_MASK)

#define AHBSC4_SRAM_4_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_4_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_4_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_4_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_4_RULE_RULE3_MASK)

#define AHBSC4_SRAM_4_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_4_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_4_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_4_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_4_RULE_RULE4_MASK)

#define AHBSC4_SRAM_4_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_4_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_4_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_4_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_4_RULE_RULE5_MASK)

#define AHBSC4_SRAM_4_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_4_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_4_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_4_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_4_RULE_RULE6_MASK)

#define AHBSC4_SRAM_4_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_4_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_4_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_4_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_4_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_4_RULE */
#define AHBSC4_SRAM_4_RULE_COUNT                 (4U)

/*! @name SRAM_5_RULE - RAM partition 5 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_5_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_5_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_5_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_5_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_5_RULE_RULE0_MASK)

#define AHBSC4_SRAM_5_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_5_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_5_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_5_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_5_RULE_RULE1_MASK)

#define AHBSC4_SRAM_5_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_5_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_5_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_5_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_5_RULE_RULE2_MASK)

#define AHBSC4_SRAM_5_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_5_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_5_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_5_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_5_RULE_RULE3_MASK)

#define AHBSC4_SRAM_5_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_5_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_5_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_5_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_5_RULE_RULE4_MASK)

#define AHBSC4_SRAM_5_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_5_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_5_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_5_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_5_RULE_RULE5_MASK)

#define AHBSC4_SRAM_5_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_5_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_5_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_5_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_5_RULE_RULE6_MASK)

#define AHBSC4_SRAM_5_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_5_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_5_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_5_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_5_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_5_RULE */
#define AHBSC4_SRAM_5_RULE_COUNT                 (4U)

/*! @name SRAM_6_RULE - RAM partition 6 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_6_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_6_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_6_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_6_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_6_RULE_RULE0_MASK)

#define AHBSC4_SRAM_6_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_6_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_6_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_6_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_6_RULE_RULE1_MASK)

#define AHBSC4_SRAM_6_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_6_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_6_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_6_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_6_RULE_RULE2_MASK)

#define AHBSC4_SRAM_6_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_6_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_6_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_6_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_6_RULE_RULE3_MASK)

#define AHBSC4_SRAM_6_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_6_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_6_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_6_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_6_RULE_RULE4_MASK)

#define AHBSC4_SRAM_6_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_6_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_6_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_6_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_6_RULE_RULE5_MASK)

#define AHBSC4_SRAM_6_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_6_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_6_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_6_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_6_RULE_RULE6_MASK)

#define AHBSC4_SRAM_6_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_6_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_6_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_6_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_6_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_6_RULE */
#define AHBSC4_SRAM_6_RULE_COUNT                 (4U)

/*! @name SRAM_7_RULE - RAM partition 7 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_7_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_7_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_7_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_7_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_7_RULE_RULE0_MASK)

#define AHBSC4_SRAM_7_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_7_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_7_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_7_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_7_RULE_RULE1_MASK)

#define AHBSC4_SRAM_7_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_7_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_7_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_7_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_7_RULE_RULE2_MASK)

#define AHBSC4_SRAM_7_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_7_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_7_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_7_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_7_RULE_RULE3_MASK)

#define AHBSC4_SRAM_7_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_7_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_7_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_7_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_7_RULE_RULE4_MASK)

#define AHBSC4_SRAM_7_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_7_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_7_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_7_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_7_RULE_RULE5_MASK)

#define AHBSC4_SRAM_7_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_7_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_7_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_7_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_7_RULE_RULE6_MASK)

#define AHBSC4_SRAM_7_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_7_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_7_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_7_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_7_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_7_RULE */
#define AHBSC4_SRAM_7_RULE_COUNT                 (4U)

/*! @name SRAM_8_RULE - RAM partition 8 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_8_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_8_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_8_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_8_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_8_RULE_RULE0_MASK)

#define AHBSC4_SRAM_8_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_8_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_8_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_8_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_8_RULE_RULE1_MASK)

#define AHBSC4_SRAM_8_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_8_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_8_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_8_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_8_RULE_RULE2_MASK)

#define AHBSC4_SRAM_8_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_8_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_8_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_8_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_8_RULE_RULE3_MASK)

#define AHBSC4_SRAM_8_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_8_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_8_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_8_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_8_RULE_RULE4_MASK)

#define AHBSC4_SRAM_8_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_8_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_8_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_8_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_8_RULE_RULE5_MASK)

#define AHBSC4_SRAM_8_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_8_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_8_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_8_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_8_RULE_RULE6_MASK)

#define AHBSC4_SRAM_8_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_8_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_8_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_8_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_8_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_8_RULE */
#define AHBSC4_SRAM_8_RULE_COUNT                 (4U)

/*! @name SRAM_9_RULE - RAM partition 9 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_9_RULE_RULE0_MASK            (0x3U)
#define AHBSC4_SRAM_9_RULE_RULE0_SHIFT           (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_9_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_9_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_9_RULE_RULE0_MASK)

#define AHBSC4_SRAM_9_RULE_RULE1_MASK            (0x30U)
#define AHBSC4_SRAM_9_RULE_RULE1_SHIFT           (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_9_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_9_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_9_RULE_RULE1_MASK)

#define AHBSC4_SRAM_9_RULE_RULE2_MASK            (0x300U)
#define AHBSC4_SRAM_9_RULE_RULE2_SHIFT           (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_9_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_9_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_9_RULE_RULE2_MASK)

#define AHBSC4_SRAM_9_RULE_RULE3_MASK            (0x3000U)
#define AHBSC4_SRAM_9_RULE_RULE3_SHIFT           (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_9_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_9_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_9_RULE_RULE3_MASK)

#define AHBSC4_SRAM_9_RULE_RULE4_MASK            (0x30000U)
#define AHBSC4_SRAM_9_RULE_RULE4_SHIFT           (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_9_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_9_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_9_RULE_RULE4_MASK)

#define AHBSC4_SRAM_9_RULE_RULE5_MASK            (0x300000U)
#define AHBSC4_SRAM_9_RULE_RULE5_SHIFT           (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_9_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_9_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_9_RULE_RULE5_MASK)

#define AHBSC4_SRAM_9_RULE_RULE6_MASK            (0x3000000U)
#define AHBSC4_SRAM_9_RULE_RULE6_SHIFT           (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_9_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_9_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_9_RULE_RULE6_MASK)

#define AHBSC4_SRAM_9_RULE_RULE7_MASK            (0x30000000U)
#define AHBSC4_SRAM_9_RULE_RULE7_SHIFT           (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_9_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_9_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_9_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_9_RULE */
#define AHBSC4_SRAM_9_RULE_COUNT                 (4U)

/*! @name SRAM_10_RULE - RAM partition 10 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_10_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_10_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_10_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_10_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_10_RULE_RULE0_MASK)

#define AHBSC4_SRAM_10_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_10_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_10_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_10_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_10_RULE_RULE1_MASK)

#define AHBSC4_SRAM_10_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_10_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_10_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_10_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_10_RULE_RULE2_MASK)

#define AHBSC4_SRAM_10_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_10_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_10_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_10_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_10_RULE_RULE3_MASK)

#define AHBSC4_SRAM_10_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_10_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_10_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_10_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_10_RULE_RULE4_MASK)

#define AHBSC4_SRAM_10_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_10_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_10_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_10_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_10_RULE_RULE5_MASK)

#define AHBSC4_SRAM_10_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_10_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_10_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_10_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_10_RULE_RULE6_MASK)

#define AHBSC4_SRAM_10_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_10_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_10_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_10_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_10_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_10_RULE */
#define AHBSC4_SRAM_10_RULE_COUNT                (4U)

/*! @name SRAM_11_RULE - RAM partition 11 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_11_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_11_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_11_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_11_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_11_RULE_RULE0_MASK)

#define AHBSC4_SRAM_11_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_11_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_11_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_11_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_11_RULE_RULE1_MASK)

#define AHBSC4_SRAM_11_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_11_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_11_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_11_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_11_RULE_RULE2_MASK)

#define AHBSC4_SRAM_11_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_11_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_11_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_11_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_11_RULE_RULE3_MASK)

#define AHBSC4_SRAM_11_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_11_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_11_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_11_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_11_RULE_RULE4_MASK)

#define AHBSC4_SRAM_11_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_11_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_11_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_11_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_11_RULE_RULE5_MASK)

#define AHBSC4_SRAM_11_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_11_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_11_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_11_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_11_RULE_RULE6_MASK)

#define AHBSC4_SRAM_11_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_11_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_11_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_11_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_11_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_11_RULE */
#define AHBSC4_SRAM_11_RULE_COUNT                (4U)

/*! @name SRAM_12_RULE - RAM partition 12 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_12_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_12_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_12_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_12_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_12_RULE_RULE0_MASK)

#define AHBSC4_SRAM_12_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_12_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_12_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_12_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_12_RULE_RULE1_MASK)

#define AHBSC4_SRAM_12_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_12_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_12_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_12_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_12_RULE_RULE2_MASK)

#define AHBSC4_SRAM_12_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_12_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_12_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_12_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_12_RULE_RULE3_MASK)

#define AHBSC4_SRAM_12_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_12_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_12_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_12_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_12_RULE_RULE4_MASK)

#define AHBSC4_SRAM_12_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_12_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_12_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_12_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_12_RULE_RULE5_MASK)

#define AHBSC4_SRAM_12_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_12_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_12_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_12_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_12_RULE_RULE6_MASK)

#define AHBSC4_SRAM_12_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_12_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_12_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_12_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_12_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_12_RULE */
#define AHBSC4_SRAM_12_RULE_COUNT                (4U)

/*! @name SRAM_13_RULE - RAM partition 13 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_13_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_13_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_13_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_13_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_13_RULE_RULE0_MASK)

#define AHBSC4_SRAM_13_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_13_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_13_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_13_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_13_RULE_RULE1_MASK)

#define AHBSC4_SRAM_13_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_13_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_13_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_13_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_13_RULE_RULE2_MASK)

#define AHBSC4_SRAM_13_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_13_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_13_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_13_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_13_RULE_RULE3_MASK)

#define AHBSC4_SRAM_13_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_13_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_13_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_13_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_13_RULE_RULE4_MASK)

#define AHBSC4_SRAM_13_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_13_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_13_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_13_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_13_RULE_RULE5_MASK)

#define AHBSC4_SRAM_13_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_13_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_13_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_13_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_13_RULE_RULE6_MASK)

#define AHBSC4_SRAM_13_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_13_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_13_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_13_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_13_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_13_RULE */
#define AHBSC4_SRAM_13_RULE_COUNT                (4U)

/*! @name SRAM_14_RULE - RAM partition 14 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_14_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_14_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_14_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_14_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_14_RULE_RULE0_MASK)

#define AHBSC4_SRAM_14_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_14_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_14_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_14_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_14_RULE_RULE1_MASK)

#define AHBSC4_SRAM_14_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_14_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_14_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_14_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_14_RULE_RULE2_MASK)

#define AHBSC4_SRAM_14_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_14_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_14_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_14_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_14_RULE_RULE3_MASK)

#define AHBSC4_SRAM_14_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_14_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_14_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_14_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_14_RULE_RULE4_MASK)

#define AHBSC4_SRAM_14_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_14_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_14_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_14_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_14_RULE_RULE5_MASK)

#define AHBSC4_SRAM_14_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_14_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_14_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_14_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_14_RULE_RULE6_MASK)

#define AHBSC4_SRAM_14_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_14_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_14_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_14_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_14_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_14_RULE */
#define AHBSC4_SRAM_14_RULE_COUNT                (4U)

/*! @name SRAM_15_RULE - RAM partition 15 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_15_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_15_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_15_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_15_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_15_RULE_RULE0_MASK)

#define AHBSC4_SRAM_15_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_15_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_15_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_15_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_15_RULE_RULE1_MASK)

#define AHBSC4_SRAM_15_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_15_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_15_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_15_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_15_RULE_RULE2_MASK)

#define AHBSC4_SRAM_15_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_15_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_15_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_15_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_15_RULE_RULE3_MASK)

#define AHBSC4_SRAM_15_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_15_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_15_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_15_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_15_RULE_RULE4_MASK)

#define AHBSC4_SRAM_15_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_15_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_15_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_15_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_15_RULE_RULE5_MASK)

#define AHBSC4_SRAM_15_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_15_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_15_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_15_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_15_RULE_RULE6_MASK)

#define AHBSC4_SRAM_15_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_15_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_15_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_15_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_15_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_15_RULE */
#define AHBSC4_SRAM_15_RULE_COUNT                (4U)

/*! @name SRAM_16_RULE - RAM partition 16 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_16_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_16_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_16_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_16_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_16_RULE_RULE0_MASK)

#define AHBSC4_SRAM_16_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_16_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_16_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_16_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_16_RULE_RULE1_MASK)

#define AHBSC4_SRAM_16_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_16_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_16_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_16_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_16_RULE_RULE2_MASK)

#define AHBSC4_SRAM_16_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_16_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_16_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_16_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_16_RULE_RULE3_MASK)

#define AHBSC4_SRAM_16_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_16_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_16_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_16_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_16_RULE_RULE4_MASK)

#define AHBSC4_SRAM_16_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_16_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_16_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_16_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_16_RULE_RULE5_MASK)

#define AHBSC4_SRAM_16_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_16_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_16_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_16_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_16_RULE_RULE6_MASK)

#define AHBSC4_SRAM_16_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_16_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_16_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_16_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_16_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_16_RULE */
#define AHBSC4_SRAM_16_RULE_COUNT                (4U)

/*! @name SRAM_17_RULE - RAM partition 17 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_17_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_17_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_17_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_17_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_17_RULE_RULE0_MASK)

#define AHBSC4_SRAM_17_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_17_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_17_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_17_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_17_RULE_RULE1_MASK)

#define AHBSC4_SRAM_17_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_17_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_17_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_17_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_17_RULE_RULE2_MASK)

#define AHBSC4_SRAM_17_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_17_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_17_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_17_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_17_RULE_RULE3_MASK)

#define AHBSC4_SRAM_17_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_17_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_17_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_17_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_17_RULE_RULE4_MASK)

#define AHBSC4_SRAM_17_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_17_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_17_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_17_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_17_RULE_RULE5_MASK)

#define AHBSC4_SRAM_17_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_17_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_17_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_17_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_17_RULE_RULE6_MASK)

#define AHBSC4_SRAM_17_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_17_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_17_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_17_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_17_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_17_RULE */
#define AHBSC4_SRAM_17_RULE_COUNT                (4U)

/*! @name SRAM_18_RULE - RAM partition 18 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_18_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_18_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_18_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_18_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_18_RULE_RULE0_MASK)

#define AHBSC4_SRAM_18_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_18_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_18_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_18_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_18_RULE_RULE1_MASK)

#define AHBSC4_SRAM_18_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_18_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_18_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_18_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_18_RULE_RULE2_MASK)

#define AHBSC4_SRAM_18_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_18_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_18_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_18_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_18_RULE_RULE3_MASK)

#define AHBSC4_SRAM_18_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_18_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_18_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_18_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_18_RULE_RULE4_MASK)

#define AHBSC4_SRAM_18_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_18_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_18_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_18_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_18_RULE_RULE5_MASK)

#define AHBSC4_SRAM_18_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_18_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_18_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_18_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_18_RULE_RULE6_MASK)

#define AHBSC4_SRAM_18_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_18_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_18_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_18_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_18_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_18_RULE */
#define AHBSC4_SRAM_18_RULE_COUNT                (4U)

/*! @name SRAM_19_RULE - RAM partition 19 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_19_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_19_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_19_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_19_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_19_RULE_RULE0_MASK)

#define AHBSC4_SRAM_19_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_19_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_19_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_19_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_19_RULE_RULE1_MASK)

#define AHBSC4_SRAM_19_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_19_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_19_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_19_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_19_RULE_RULE2_MASK)

#define AHBSC4_SRAM_19_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_19_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_19_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_19_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_19_RULE_RULE3_MASK)

#define AHBSC4_SRAM_19_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_19_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_19_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_19_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_19_RULE_RULE4_MASK)

#define AHBSC4_SRAM_19_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_19_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_19_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_19_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_19_RULE_RULE5_MASK)

#define AHBSC4_SRAM_19_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_19_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_19_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_19_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_19_RULE_RULE6_MASK)

#define AHBSC4_SRAM_19_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_19_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_19_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_19_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_19_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_19_RULE */
#define AHBSC4_SRAM_19_RULE_COUNT                (4U)

/*! @name SRAM_20_RULE - RAM partition 20 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_20_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_20_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_20_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_20_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_20_RULE_RULE0_MASK)

#define AHBSC4_SRAM_20_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_20_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_20_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_20_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_20_RULE_RULE1_MASK)

#define AHBSC4_SRAM_20_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_20_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_20_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_20_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_20_RULE_RULE2_MASK)

#define AHBSC4_SRAM_20_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_20_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_20_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_20_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_20_RULE_RULE3_MASK)

#define AHBSC4_SRAM_20_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_20_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_20_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_20_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_20_RULE_RULE4_MASK)

#define AHBSC4_SRAM_20_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_20_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_20_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_20_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_20_RULE_RULE5_MASK)

#define AHBSC4_SRAM_20_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_20_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_20_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_20_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_20_RULE_RULE6_MASK)

#define AHBSC4_SRAM_20_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_20_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_20_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_20_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_20_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_20_RULE */
#define AHBSC4_SRAM_20_RULE_COUNT                (4U)

/*! @name SRAM_21_RULE - RAM partition 21 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_21_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_21_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_21_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_21_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_21_RULE_RULE0_MASK)

#define AHBSC4_SRAM_21_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_21_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_21_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_21_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_21_RULE_RULE1_MASK)

#define AHBSC4_SRAM_21_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_21_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_21_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_21_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_21_RULE_RULE2_MASK)

#define AHBSC4_SRAM_21_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_21_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_21_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_21_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_21_RULE_RULE3_MASK)

#define AHBSC4_SRAM_21_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_21_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_21_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_21_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_21_RULE_RULE4_MASK)

#define AHBSC4_SRAM_21_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_21_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_21_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_21_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_21_RULE_RULE5_MASK)

#define AHBSC4_SRAM_21_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_21_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_21_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_21_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_21_RULE_RULE6_MASK)

#define AHBSC4_SRAM_21_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_21_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_21_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_21_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_21_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_21_RULE */
#define AHBSC4_SRAM_21_RULE_COUNT                (4U)

/*! @name SRAM_22_RULE - RAM partition 22 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_22_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_22_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_22_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_22_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_22_RULE_RULE0_MASK)

#define AHBSC4_SRAM_22_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_22_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_22_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_22_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_22_RULE_RULE1_MASK)

#define AHBSC4_SRAM_22_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_22_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_22_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_22_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_22_RULE_RULE2_MASK)

#define AHBSC4_SRAM_22_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_22_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_22_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_22_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_22_RULE_RULE3_MASK)

#define AHBSC4_SRAM_22_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_22_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_22_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_22_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_22_RULE_RULE4_MASK)

#define AHBSC4_SRAM_22_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_22_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_22_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_22_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_22_RULE_RULE5_MASK)

#define AHBSC4_SRAM_22_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_22_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_22_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_22_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_22_RULE_RULE6_MASK)

#define AHBSC4_SRAM_22_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_22_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_22_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_22_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_22_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_22_RULE */
#define AHBSC4_SRAM_22_RULE_COUNT                (4U)

/*! @name SRAM_23_RULE - RAM partition 23 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_23_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_23_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_23_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_23_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_23_RULE_RULE0_MASK)

#define AHBSC4_SRAM_23_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_23_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_23_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_23_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_23_RULE_RULE1_MASK)

#define AHBSC4_SRAM_23_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_23_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_23_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_23_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_23_RULE_RULE2_MASK)

#define AHBSC4_SRAM_23_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_23_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_23_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_23_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_23_RULE_RULE3_MASK)

#define AHBSC4_SRAM_23_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_23_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_23_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_23_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_23_RULE_RULE4_MASK)

#define AHBSC4_SRAM_23_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_23_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_23_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_23_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_23_RULE_RULE5_MASK)

#define AHBSC4_SRAM_23_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_23_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_23_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_23_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_23_RULE_RULE6_MASK)

#define AHBSC4_SRAM_23_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_23_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_23_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_23_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_23_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_23_RULE */
#define AHBSC4_SRAM_23_RULE_COUNT                (4U)

/*! @name SRAM_24_RULE - RAM partition 24 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_24_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_24_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_24_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_24_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_24_RULE_RULE0_MASK)

#define AHBSC4_SRAM_24_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_24_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_24_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_24_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_24_RULE_RULE1_MASK)

#define AHBSC4_SRAM_24_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_24_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_24_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_24_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_24_RULE_RULE2_MASK)

#define AHBSC4_SRAM_24_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_24_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_24_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_24_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_24_RULE_RULE3_MASK)

#define AHBSC4_SRAM_24_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_24_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_24_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_24_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_24_RULE_RULE4_MASK)

#define AHBSC4_SRAM_24_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_24_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_24_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_24_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_24_RULE_RULE5_MASK)

#define AHBSC4_SRAM_24_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_24_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_24_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_24_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_24_RULE_RULE6_MASK)

#define AHBSC4_SRAM_24_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_24_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_24_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_24_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_24_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_24_RULE */
#define AHBSC4_SRAM_24_RULE_COUNT                (4U)

/*! @name SRAM_25_RULE - RAM partition 25 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_25_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_25_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_25_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_25_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_25_RULE_RULE0_MASK)

#define AHBSC4_SRAM_25_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_25_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_25_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_25_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_25_RULE_RULE1_MASK)

#define AHBSC4_SRAM_25_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_25_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_25_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_25_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_25_RULE_RULE2_MASK)

#define AHBSC4_SRAM_25_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_25_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_25_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_25_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_25_RULE_RULE3_MASK)

#define AHBSC4_SRAM_25_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_25_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_25_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_25_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_25_RULE_RULE4_MASK)

#define AHBSC4_SRAM_25_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_25_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_25_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_25_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_25_RULE_RULE5_MASK)

#define AHBSC4_SRAM_25_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_25_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_25_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_25_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_25_RULE_RULE6_MASK)

#define AHBSC4_SRAM_25_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_25_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_25_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_25_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_25_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_25_RULE */
#define AHBSC4_SRAM_25_RULE_COUNT                (4U)

/*! @name SRAM_26_RULE - RAM partition 26 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_26_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_26_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_26_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_26_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_26_RULE_RULE0_MASK)

#define AHBSC4_SRAM_26_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_26_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_26_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_26_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_26_RULE_RULE1_MASK)

#define AHBSC4_SRAM_26_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_26_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_26_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_26_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_26_RULE_RULE2_MASK)

#define AHBSC4_SRAM_26_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_26_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_26_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_26_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_26_RULE_RULE3_MASK)

#define AHBSC4_SRAM_26_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_26_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_26_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_26_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_26_RULE_RULE4_MASK)

#define AHBSC4_SRAM_26_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_26_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_26_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_26_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_26_RULE_RULE5_MASK)

#define AHBSC4_SRAM_26_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_26_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_26_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_26_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_26_RULE_RULE6_MASK)

#define AHBSC4_SRAM_26_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_26_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_26_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_26_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_26_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_26_RULE */
#define AHBSC4_SRAM_26_RULE_COUNT                (4U)

/*! @name SRAM_27_RULE - RAM partition 27 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_27_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_27_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_27_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_27_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_27_RULE_RULE0_MASK)

#define AHBSC4_SRAM_27_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_27_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_27_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_27_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_27_RULE_RULE1_MASK)

#define AHBSC4_SRAM_27_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_27_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_27_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_27_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_27_RULE_RULE2_MASK)

#define AHBSC4_SRAM_27_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_27_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_27_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_27_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_27_RULE_RULE3_MASK)

#define AHBSC4_SRAM_27_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_27_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_27_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_27_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_27_RULE_RULE4_MASK)

#define AHBSC4_SRAM_27_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_27_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_27_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_27_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_27_RULE_RULE5_MASK)

#define AHBSC4_SRAM_27_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_27_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_27_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_27_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_27_RULE_RULE6_MASK)

#define AHBSC4_SRAM_27_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_27_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_27_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_27_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_27_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_27_RULE */
#define AHBSC4_SRAM_27_RULE_COUNT                (4U)

/*! @name SRAM_28_RULE - RAM partition 28 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_28_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_28_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_28_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_28_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_28_RULE_RULE0_MASK)

#define AHBSC4_SRAM_28_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_28_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_28_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_28_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_28_RULE_RULE1_MASK)

#define AHBSC4_SRAM_28_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_28_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_28_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_28_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_28_RULE_RULE2_MASK)

#define AHBSC4_SRAM_28_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_28_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_28_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_28_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_28_RULE_RULE3_MASK)

#define AHBSC4_SRAM_28_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_28_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_28_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_28_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_28_RULE_RULE4_MASK)

#define AHBSC4_SRAM_28_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_28_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_28_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_28_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_28_RULE_RULE5_MASK)

#define AHBSC4_SRAM_28_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_28_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_28_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_28_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_28_RULE_RULE6_MASK)

#define AHBSC4_SRAM_28_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_28_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_28_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_28_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_28_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_28_RULE */
#define AHBSC4_SRAM_28_RULE_COUNT                (4U)

/*! @name SRAM_29_RULE - RAM partition 29 Memory Rule Register */
/*! @{ */

#define AHBSC4_SRAM_29_RULE_RULE0_MASK           (0x3U)
#define AHBSC4_SRAM_29_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_29_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_29_RULE_RULE0_SHIFT)) & AHBSC4_SRAM_29_RULE_RULE0_MASK)

#define AHBSC4_SRAM_29_RULE_RULE1_MASK           (0x30U)
#define AHBSC4_SRAM_29_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_29_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_29_RULE_RULE1_SHIFT)) & AHBSC4_SRAM_29_RULE_RULE1_MASK)

#define AHBSC4_SRAM_29_RULE_RULE2_MASK           (0x300U)
#define AHBSC4_SRAM_29_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_29_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_29_RULE_RULE2_SHIFT)) & AHBSC4_SRAM_29_RULE_RULE2_MASK)

#define AHBSC4_SRAM_29_RULE_RULE3_MASK           (0x3000U)
#define AHBSC4_SRAM_29_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_29_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_29_RULE_RULE3_SHIFT)) & AHBSC4_SRAM_29_RULE_RULE3_MASK)

#define AHBSC4_SRAM_29_RULE_RULE4_MASK           (0x30000U)
#define AHBSC4_SRAM_29_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_29_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_29_RULE_RULE4_SHIFT)) & AHBSC4_SRAM_29_RULE_RULE4_MASK)

#define AHBSC4_SRAM_29_RULE_RULE5_MASK           (0x300000U)
#define AHBSC4_SRAM_29_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_29_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_29_RULE_RULE5_SHIFT)) & AHBSC4_SRAM_29_RULE_RULE5_MASK)

#define AHBSC4_SRAM_29_RULE_RULE6_MASK           (0x3000000U)
#define AHBSC4_SRAM_29_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_29_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_29_RULE_RULE6_SHIFT)) & AHBSC4_SRAM_29_RULE_RULE6_MASK)

#define AHBSC4_SRAM_29_RULE_RULE7_MASK           (0x30000000U)
#define AHBSC4_SRAM_29_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_SRAM_29_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC4_SRAM_29_RULE_RULE7_SHIFT)) & AHBSC4_SRAM_29_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_SRAM_29_RULE */
#define AHBSC4_SRAM_29_RULE_COUNT                (4U)

/*! @name XSPI2_REGION0_MEM_RULE - XSPI2 Region0 Memory Rule Register */
/*! @{ */

#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE0_MASK (0x3U)
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION0_MEM_RULE_RULE0_SHIFT)) & AHBSC4_XSPI2_REGION0_MEM_RULE_RULE0_MASK)

#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE1_MASK (0x30U)
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION0_MEM_RULE_RULE1_SHIFT)) & AHBSC4_XSPI2_REGION0_MEM_RULE_RULE1_MASK)

#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE2_MASK (0x300U)
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE2(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION0_MEM_RULE_RULE2_SHIFT)) & AHBSC4_XSPI2_REGION0_MEM_RULE_RULE2_MASK)

#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE3_MASK (0x3000U)
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE3(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION0_MEM_RULE_RULE3_SHIFT)) & AHBSC4_XSPI2_REGION0_MEM_RULE_RULE3_MASK)

#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE4_MASK (0x30000U)
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE4(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION0_MEM_RULE_RULE4_SHIFT)) & AHBSC4_XSPI2_REGION0_MEM_RULE_RULE4_MASK)

#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE5_MASK (0x300000U)
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE5(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION0_MEM_RULE_RULE5_SHIFT)) & AHBSC4_XSPI2_REGION0_MEM_RULE_RULE5_MASK)

#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE6(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION0_MEM_RULE_RULE6_SHIFT)) & AHBSC4_XSPI2_REGION0_MEM_RULE_RULE6_MASK)

#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_RULE7(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION0_MEM_RULE_RULE7_SHIFT)) & AHBSC4_XSPI2_REGION0_MEM_RULE_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_XSPI2_REGION0_MEM_RULE */
#define AHBSC4_XSPI2_REGION0_MEM_RULE_COUNT      (4U)

/*! @name XSPI2_REGION_MEM_RULE0 - XSPI2 Region 1 Memory Rule Register..XSPI2 Region 5 Memory Rule Register */
/*! @{ */

#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE0_MASK (0x3U)
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION_MEM_RULE0_RULE0_SHIFT)) & AHBSC4_XSPI2_REGION_MEM_RULE0_RULE0_MASK)

#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE1_MASK (0x30U)
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION_MEM_RULE0_RULE1_SHIFT)) & AHBSC4_XSPI2_REGION_MEM_RULE0_RULE1_MASK)

#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE2_MASK (0x300U)
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE2(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION_MEM_RULE0_RULE2_SHIFT)) & AHBSC4_XSPI2_REGION_MEM_RULE0_RULE2_MASK)

#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE3_MASK (0x3000U)
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE3(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION_MEM_RULE0_RULE3_SHIFT)) & AHBSC4_XSPI2_REGION_MEM_RULE0_RULE3_MASK)

#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE4_MASK (0x30000U)
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE4_SHIFT (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE4(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION_MEM_RULE0_RULE4_SHIFT)) & AHBSC4_XSPI2_REGION_MEM_RULE0_RULE4_MASK)

#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE5_MASK (0x300000U)
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE5_SHIFT (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE5(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION_MEM_RULE0_RULE5_SHIFT)) & AHBSC4_XSPI2_REGION_MEM_RULE0_RULE5_MASK)

#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE6_MASK (0x3000000U)
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE6_SHIFT (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE6(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION_MEM_RULE0_RULE6_SHIFT)) & AHBSC4_XSPI2_REGION_MEM_RULE0_RULE6_MASK)

#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE7_MASK (0x30000000U)
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE7_SHIFT (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_RULE7(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_XSPI2_REGION_MEM_RULE0_RULE7_SHIFT)) & AHBSC4_XSPI2_REGION_MEM_RULE0_RULE7_MASK)
/*! @} */

/* The count of AHBSC4_XSPI2_REGION_MEM_RULE0 */
#define AHBSC4_XSPI2_REGION_MEM_RULE0_COUNT      (5U)

/*! @name SEC_VIO_ADDR - Security Violation Address */
/*! @{ */

#define AHBSC4_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK    (0xFFFFFFFFU)
#define AHBSC4_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT   (0U)
/*! SEC_VIO_ADDR - Security violation address for AHB layer a reset value 0 */
#define AHBSC4_SEC_VIO_ADDR_SEC_VIO_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHBSC4_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
/*! @} */

/* The count of AHBSC4_SEC_VIO_ADDR */
#define AHBSC4_SEC_VIO_ADDR_COUNT                (13U)

/*! @name SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */
/*! @{ */

#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator
 *  0b0..Read access
 *  0b1..Write access
 */
#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)

#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access
 *  0b0..Code
 *  0b1..Data
 */
#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)

#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level */
#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)

#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0x1F00U)
#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
/*! SEC_VIO_INFO_MASTER - Security violation master number
 *  0b00000..CPU0 System
 *  0b00001..eDMA0
 *  0b00010..eDMA1
 *  0b00011..ELS
 *  0b00100..HIFI4
 *  0b00101..CPU1 system
 *  0b00110..eDMA2
 *  0b00111..eDMA3
 *  0b01000..HIFI1
 *  0b01001..EZH-V
 *  0b01010..PKC
 *  0b01011..USDHC0
 *  0b01100..USB0
 *  0b01101..GPU
 *  0b01110..ETR
 *  0b01111..DAP
 *  0b10000..CPU0 Code
 *  0b10001..Reserved
 *  0b10010..Reserved
 *  0b10011..Reserved
 *  0b10100..Reserved
 *  0b10101..CPU1 code
 *  0b10110..JPEGDEC
 *  0b10111..PNGDEC
 *  0b11000..Reserved
 *  0b11001..Reserved
 *  0b11010..Reserved
 *  0b11011..USDHC1
 *  0b11100..USB1
 *  0b11101..LCDIF
 *  0b11110..MTR
 *  0b11111..Test port
 */
#define AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHBSC4_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
/*! @} */

/* The count of AHBSC4_SEC_VIO_MISC_INFO */
#define AHBSC4_SEC_VIO_MISC_INFO_COUNT           (13U)

/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */
/*! @{ */

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)

#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U)
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U)
/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12
 *  0b0..Not valid
 *  0b1..Valid
 */
#define AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHBSC4_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK)
/*! @} */

/*! @name MASTER_SEC_LEVEL - Master Secure Level */
/*! @{ */

#define AHBSC4_MASTER_SEC_LEVEL_EZHV_MASK        (0x3U)
#define AHBSC4_MASTER_SEC_LEVEL_EZHV_SHIFT       (0U)
/*! EZHV - EZHV
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_EZHV(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_EZHV_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_EZHV_MASK)

#define AHBSC4_MASTER_SEC_LEVEL_SDHC0_MASK       (0xCU)
#define AHBSC4_MASTER_SEC_LEVEL_SDHC0_SHIFT      (2U)
/*! SDHC0 - SDHC0
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_SDHC0(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_SDHC0_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_SDHC0_MASK)

#define AHBSC4_MASTER_SEC_LEVEL_SDHC1_MASK       (0x30U)
#define AHBSC4_MASTER_SEC_LEVEL_SDHC1_SHIFT      (4U)
/*! SDHC1 - SDHC1
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_SDHC1(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_SDHC1_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_SDHC1_MASK)

#define AHBSC4_MASTER_SEC_LEVEL_USB0_MASK        (0xC0U)
#define AHBSC4_MASTER_SEC_LEVEL_USB0_SHIFT       (6U)
/*! USB0 - USB0
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_USB0(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_USB0_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_USB0_MASK)

#define AHBSC4_MASTER_SEC_LEVEL_USB1_MASK        (0x300U)
#define AHBSC4_MASTER_SEC_LEVEL_USB1_SHIFT       (8U)
/*! USB1 - USB1
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_USB1(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_USB1_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_USB1_MASK)

#define AHBSC4_MASTER_SEC_LEVEL_LCDIF_MASK       (0xC00U)
#define AHBSC4_MASTER_SEC_LEVEL_LCDIF_SHIFT      (10U)
/*! LCDIF - LCDIF
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_LCDIF(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_LCDIF_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_LCDIF_MASK)

#define AHBSC4_MASTER_SEC_LEVEL_GPU_MASK         (0x3000U)
#define AHBSC4_MASTER_SEC_LEVEL_GPU_SHIFT        (12U)
/*! GPU - GPU
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_GPU(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_GPU_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_GPU_MASK)

#define AHBSC4_MASTER_SEC_LEVEL_JPEG_MASK        (0xC000U)
#define AHBSC4_MASTER_SEC_LEVEL_JPEG_SHIFT       (14U)
/*! JPEG - JPEG
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_JPEG(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_JPEG_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_JPEG_MASK)

#define AHBSC4_MASTER_SEC_LEVEL_PNG_MASK         (0x30000U)
#define AHBSC4_MASTER_SEC_LEVEL_PNG_SHIFT        (16U)
/*! PNG - PNG
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define AHBSC4_MASTER_SEC_LEVEL_PNG(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_LEVEL_PNG_SHIFT)) & AHBSC4_MASTER_SEC_LEVEL_PNG_MASK)
/*! @} */

/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */
/*! @{ */

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_EZHV_MASK (0x3U)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_EZHV_SHIFT (0U)
/*! EZHV - EZHV
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_EZHV(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_EZHV_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_EZHV_MASK)

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC0_MASK (0xCU)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC0_SHIFT (2U)
/*! SDHC0 - SDHC0
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC0(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC0_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC0_MASK)

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC1_MASK (0x30U)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC1_SHIFT (4U)
/*! SDHC1 - SDHC1
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC1(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC1_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_SDHC1_MASK)

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_USB0_MASK (0xC0U)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_USB0_SHIFT (6U)
/*! USB0 - USB0
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_USB0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_USB0_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_USB0_MASK)

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_USB1_MASK (0x300U)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_USB1_SHIFT (8U)
/*! USB1 - USB1
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_USB1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_USB1_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_USB1_MASK)

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_LCDIF_MASK (0xC00U)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_LCDIF_SHIFT (10U)
/*! LCDIF - LCDIF
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_LCDIF(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_LCDIF_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_LCDIF_MASK)

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_GPU_MASK  (0x3000U)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_GPU_SHIFT (12U)
/*! GPU - GPU
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_GPU(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_GPU_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_GPU_MASK)

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_JPEG_MASK (0xC000U)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_JPEG_SHIFT (14U)
/*! JPEG - JPEG
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_JPEG(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_JPEG_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_JPEG_MASK)

#define AHBSC4_MASTER_SEC_ANTI_POL_REG_PNG_MASK  (0x30000U)
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_PNG_SHIFT (16U)
/*! PNG - PNG
 *  0b00..Secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b11..Non-secure and non-privileged Master
 */
#define AHBSC4_MASTER_SEC_ANTI_POL_REG_PNG(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC4_MASTER_SEC_ANTI_POL_REG_PNG_SHIFT)) & AHBSC4_MASTER_SEC_ANTI_POL_REG_PNG_MASK)
/*! @} */

/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */
/*! @{ */

#define AHBSC4_MISC_CTRL_DP_REG_WRITE_LOCK_MASK  (0x3U)
#define AHBSC4_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
/*! WRITE_LOCK - Write Lock
 *  0b00..Reserved
 *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
 *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_DP_REG_WRITE_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHBSC4_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)

#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC4_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)

#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC4_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)

#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC4_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)

#define AHBSC4_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define AHBSC4_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
 *  0b00..Reserved
 *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
 *        (interrupt request) will still be asserted and serviced by ISR.
 *  0b10..The violation detected by the secure checker will cause an abort.
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC4_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)

#define AHBSC4_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
#define AHBSC4_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U)
/*! DISABLE_STRICT_MODE - Disable Strict Mode
 *  0b00..AHB master in strict mode
 *  0b01..AHB master in tier mode. Can read and write to memories at same or below level.
 *  0b10..AHB master in strict mode
 *  0b11..AHB master in strict mode
 */
#define AHBSC4_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC4_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK)

#define AHBSC4_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
#define AHBSC4_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
/*! IDAU_ALL_NS - IDAU All Non-Secure
 *  0b00..Reserved
 *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
 *  0b10..IDAU is enabled (restrictive mode)
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_DP_REG_IDAU_ALL_NS(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHBSC4_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
/*! @} */

/*! @name MISC_CTRL_REG - Secure Control */
/*! @{ */

#define AHBSC4_MISC_CTRL_REG_WRITE_LOCK_MASK     (0x3U)
#define AHBSC4_MISC_CTRL_REG_WRITE_LOCK_SHIFT    (0U)
/*! WRITE_LOCK - Write Lock
 *  0b00..Reserved
 *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
 *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_REG_WRITE_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHBSC4_MISC_CTRL_REG_WRITE_LOCK_MASK)

#define AHBSC4_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define AHBSC4_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC4_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)

#define AHBSC4_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define AHBSC4_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC4_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)

#define AHBSC4_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define AHBSC4_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC4_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)

#define AHBSC4_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define AHBSC4_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
 *  0b00..Reserved
 *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
 *        (interrupt request) will still be asserted and serviced by ISR.
 *  0b10..The violation detected by the secure checker will cause an abort.
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC4_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)

#define AHBSC4_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
#define AHBSC4_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U)
/*! DISABLE_STRICT_MODE - Disable Strict Mode
 *  0b00..AHB master in strict mode
 *  0b01..AHB master in tier mode. Can read and write to memories at same or below level.
 *  0b10..AHB master in strict mode
 *  0b11..AHB master in strict mode
 */
#define AHBSC4_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC4_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK)

#define AHBSC4_MISC_CTRL_REG_IDAU_ALL_NS_MASK    (0xC000U)
#define AHBSC4_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT   (14U)
/*! IDAU_ALL_NS - IDAU All Non-Secure
 *  0b00..Reserved
 *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
 *  0b10..IDAU is enabled (restrictive mode)
 *  0b11..Reserved
 */
#define AHBSC4_MISC_CTRL_REG_IDAU_ALL_NS(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC4_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHBSC4_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AHBSC4_Register_Masks */


/* AHBSC4 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral AHBSC4 base address */
  #define AHBSC4_BASE                              (0x50400000u)
  /** Peripheral AHBSC4 base address */
  #define AHBSC4_BASE_NS                           (0x40400000u)
  /** Peripheral AHBSC4 base pointer */
  #define AHBSC4                                   ((AHBSC4_Type *)AHBSC4_BASE)
  /** Peripheral AHBSC4 base pointer */
  #define AHBSC4_NS                                ((AHBSC4_Type *)AHBSC4_BASE_NS)
  /** Peripheral AHBSC4_ALIAS1 base address */
  #define AHBSC4_ALIAS1_BASE                       (0x50401000u)
  /** Peripheral AHBSC4_ALIAS1 base address */
  #define AHBSC4_ALIAS1_BASE_NS                    (0x40401000u)
  /** Peripheral AHBSC4_ALIAS1 base pointer */
  #define AHBSC4_ALIAS1                            ((AHBSC4_Type *)AHBSC4_ALIAS1_BASE)
  /** Peripheral AHBSC4_ALIAS1 base pointer */
  #define AHBSC4_ALIAS1_NS                         ((AHBSC4_Type *)AHBSC4_ALIAS1_BASE_NS)
  /** Peripheral AHBSC4_ALIAS2 base address */
  #define AHBSC4_ALIAS2_BASE                       (0x50402000u)
  /** Peripheral AHBSC4_ALIAS2 base address */
  #define AHBSC4_ALIAS2_BASE_NS                    (0x40402000u)
  /** Peripheral AHBSC4_ALIAS2 base pointer */
  #define AHBSC4_ALIAS2                            ((AHBSC4_Type *)AHBSC4_ALIAS2_BASE)
  /** Peripheral AHBSC4_ALIAS2 base pointer */
  #define AHBSC4_ALIAS2_NS                         ((AHBSC4_Type *)AHBSC4_ALIAS2_BASE_NS)
  /** Peripheral AHBSC4_ALIAS3 base address */
  #define AHBSC4_ALIAS3_BASE                       (0x50403000u)
  /** Peripheral AHBSC4_ALIAS3 base address */
  #define AHBSC4_ALIAS3_BASE_NS                    (0x40403000u)
  /** Peripheral AHBSC4_ALIAS3 base pointer */
  #define AHBSC4_ALIAS3                            ((AHBSC4_Type *)AHBSC4_ALIAS3_BASE)
  /** Peripheral AHBSC4_ALIAS3 base pointer */
  #define AHBSC4_ALIAS3_NS                         ((AHBSC4_Type *)AHBSC4_ALIAS3_BASE_NS)
  /** Array initializer of AHBSC4 peripheral base addresses */
  #define AHBSC4_BASE_ADDRS                        { AHBSC4_BASE, AHBSC4_ALIAS1_BASE, AHBSC4_ALIAS2_BASE, AHBSC4_ALIAS3_BASE }
  /** Array initializer of AHBSC4 peripheral base pointers */
  #define AHBSC4_BASE_PTRS                         { AHBSC4, AHBSC4_ALIAS1, AHBSC4_ALIAS2, AHBSC4_ALIAS3 }
  /** Array initializer of AHBSC4 peripheral base addresses */
  #define AHBSC4_BASE_ADDRS_NS                     { AHBSC4_BASE_NS, AHBSC4_ALIAS1_BASE_NS, AHBSC4_ALIAS2_BASE_NS, AHBSC4_ALIAS3_BASE_NS }
  /** Array initializer of AHBSC4 peripheral base pointers */
  #define AHBSC4_BASE_PTRS_NS                      { AHBSC4_NS, AHBSC4_ALIAS1_NS, AHBSC4_ALIAS2_NS, AHBSC4_ALIAS3_NS }
#else
  /** Peripheral AHBSC4 base address */
  #define AHBSC4_BASE                              (0x40400000u)
  /** Peripheral AHBSC4 base pointer */
  #define AHBSC4                                   ((AHBSC4_Type *)AHBSC4_BASE)
  /** Peripheral AHBSC4_ALIAS1 base address */
  #define AHBSC4_ALIAS1_BASE                       (0x40401000u)
  /** Peripheral AHBSC4_ALIAS1 base pointer */
  #define AHBSC4_ALIAS1                            ((AHBSC4_Type *)AHBSC4_ALIAS1_BASE)
  /** Peripheral AHBSC4_ALIAS2 base address */
  #define AHBSC4_ALIAS2_BASE                       (0x40402000u)
  /** Peripheral AHBSC4_ALIAS2 base pointer */
  #define AHBSC4_ALIAS2                            ((AHBSC4_Type *)AHBSC4_ALIAS2_BASE)
  /** Peripheral AHBSC4_ALIAS3 base address */
  #define AHBSC4_ALIAS3_BASE                       (0x40403000u)
  /** Peripheral AHBSC4_ALIAS3 base pointer */
  #define AHBSC4_ALIAS3                            ((AHBSC4_Type *)AHBSC4_ALIAS3_BASE)
  /** Array initializer of AHBSC4 peripheral base addresses */
  #define AHBSC4_BASE_ADDRS                        { AHBSC4_BASE, AHBSC4_ALIAS1_BASE, AHBSC4_ALIAS2_BASE, AHBSC4_ALIAS3_BASE }
  /** Array initializer of AHBSC4 peripheral base pointers */
  #define AHBSC4_BASE_PTRS                         { AHBSC4, AHBSC4_ALIAS1, AHBSC4_ALIAS2, AHBSC4_ALIAS3 }
#endif

/*!
 * @}
 */ /* end of group AHBSC4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CACHE64_CTRL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer
 * @{
 */

/** CACHE64_CTRL - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[2048];
  __IO uint32_t CCR;                               /**< Cache Control, offset: 0x800 */
  __IO uint32_t CLCR;                              /**< Cache Line Control, offset: 0x804 */
  __IO uint32_t CSAR;                              /**< Cache Search Address, offset: 0x808 */
  __IO uint32_t CCVR;                              /**< Cache Read/Write Value, offset: 0x80C */
} CACHE64_CTRL_Type;

/* ----------------------------------------------------------------------------
   -- CACHE64_CTRL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks
 * @{
 */

/*! @name CCR - Cache Control */
/*! @{ */

#define CACHE64_CTRL_CCR_ENCACHE_MASK            (0x1U)
#define CACHE64_CTRL_CCR_ENCACHE_SHIFT           (0U)
/*! ENCACHE - Cache Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define CACHE64_CTRL_CCR_ENCACHE(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK)

#define CACHE64_CTRL_CCR_FRCWT_MASK              (0x4U)
#define CACHE64_CTRL_CCR_FRCWT_SHIFT             (2U)
/*! FRCWT - Force Write Through Mode
 *  0b0..Does not force
 *  0b1..Force
 */
#define CACHE64_CTRL_CCR_FRCWT(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCWT_SHIFT)) & CACHE64_CTRL_CCR_FRCWT_MASK)

#define CACHE64_CTRL_CCR_FRCNOALLC_MASK          (0x8U)
#define CACHE64_CTRL_CCR_FRCNOALLC_SHIFT         (3U)
/*! FRCNOALLC - Forces No Allocation On Cache Misses
 *  0b0..Allocation on cache misses
 *  0b1..Forces no allocation on cache misses (FRCWT must be asserted)
 */
#define CACHE64_CTRL_CCR_FRCNOALLC(x)            (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCNOALLC_SHIFT)) & CACHE64_CTRL_CCR_FRCNOALLC_MASK)

#define CACHE64_CTRL_CCR_INVW0_MASK              (0x1000000U)
#define CACHE64_CTRL_CCR_INVW0_SHIFT             (24U)
/*! INVW0 - Invalidate Way 0
 *  0b0..No operation
 *  0b1..Invalidates all lines in way 0
 */
#define CACHE64_CTRL_CCR_INVW0(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK)

#define CACHE64_CTRL_CCR_PUSHW0_MASK             (0x2000000U)
#define CACHE64_CTRL_CCR_PUSHW0_SHIFT            (25U)
/*! PUSHW0 - Push Way 0
 *  0b0..No operation
 *  0b1..Push all modified lines in way 0
 */
#define CACHE64_CTRL_CCR_PUSHW0(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK)

#define CACHE64_CTRL_CCR_INVW1_MASK              (0x4000000U)
#define CACHE64_CTRL_CCR_INVW1_SHIFT             (26U)
/*! INVW1 - Invalidate Way 1
 *  0b0..No operation
 *  0b1..Invalidates all lines in way 1
 */
#define CACHE64_CTRL_CCR_INVW1(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)

#define CACHE64_CTRL_CCR_PUSHW1_MASK             (0x8000000U)
#define CACHE64_CTRL_CCR_PUSHW1_SHIFT            (27U)
/*! PUSHW1 - Push Way 1
 *  0b0..No operation
 *  0b1..Push all modified lines in way 1
 */
#define CACHE64_CTRL_CCR_PUSHW1(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK)

#define CACHE64_CTRL_CCR_GO_MASK                 (0x80000000U)
#define CACHE64_CTRL_CCR_GO_SHIFT                (31U)
/*! GO - Initiate Cache Command
 *  0b0..Write: no effect; Read: no cache command active
 *  0b1..Write: initiates cache command; Read: cache command active
 */
#define CACHE64_CTRL_CCR_GO(x)                   (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
/*! @} */

/*! @name CLCR - Cache Line Control */
/*! @{ */

#define CACHE64_CTRL_CLCR_LGO_MASK               (0x1U)
#define CACHE64_CTRL_CLCR_LGO_SHIFT              (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect; Read: no line command active
 *  0b1..Write: initiate line command; Read: line command active
 */
#define CACHE64_CTRL_CLCR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)

#define CACHE64_CTRL_CLCR_CACHEADDR_MASK         (0x3FFCU)
#define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT        (2U)
/*! CACHEADDR - Cache Address */
#define CACHE64_CTRL_CLCR_CACHEADDR(x)           (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK)

#define CACHE64_CTRL_CLCR_WSEL_MASK              (0x4000U)
#define CACHE64_CTRL_CLCR_WSEL_SHIFT             (14U)
/*! WSEL - Way Select
 *  0b0..Way 0
 *  0b1..Way 1
 */
#define CACHE64_CTRL_CLCR_WSEL(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK)

#define CACHE64_CTRL_CLCR_TDSEL_MASK             (0x10000U)
#define CACHE64_CTRL_CLCR_TDSEL_SHIFT            (16U)
/*! TDSEL - Tag Or Data Select
 *  0b0..Data
 *  0b1..Tag
 */
#define CACHE64_CTRL_CLCR_TDSEL(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK)

#define CACHE64_CTRL_CLCR_LCIVB_MASK             (0x100000U)
#define CACHE64_CTRL_CLCR_LCIVB_SHIFT            (20U)
/*! LCIVB - Line Command Initial Valid Bit
 *  0b0..Initial state 0
 *  0b1..Initial state 1
 */
#define CACHE64_CTRL_CLCR_LCIVB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK)

#define CACHE64_CTRL_CLCR_LCIMB_MASK             (0x200000U)
#define CACHE64_CTRL_CLCR_LCIMB_SHIFT            (21U)
/*! LCIMB - Line Command Initial Modified Bit
 *  0b0..Initial state 0
 *  0b1..Initial state 1
 */
#define CACHE64_CTRL_CLCR_LCIMB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK)

#define CACHE64_CTRL_CLCR_LCWAY_MASK             (0x400000U)
#define CACHE64_CTRL_CLCR_LCWAY_SHIFT            (22U)
/*! LCWAY - Line Command Way
 *  0b0..Way 0
 *  0b1..Way 1
 */
#define CACHE64_CTRL_CLCR_LCWAY(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK)

#define CACHE64_CTRL_CLCR_LCMD_MASK              (0x3000000U)
#define CACHE64_CTRL_CLCR_LCMD_SHIFT             (24U)
/*! LCMD - Line Command
 *  0b00..Search and read or write
 *  0b01..Invalidate
 *  0b10..Push
 *  0b11..Clear
 */
#define CACHE64_CTRL_CLCR_LCMD(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK)

#define CACHE64_CTRL_CLCR_LADSEL_MASK            (0x4000000U)
#define CACHE64_CTRL_CLCR_LADSEL_SHIFT           (26U)
/*! LADSEL - Line Address Select
 *  0b0..Cache
 *  0b1..Physical
 */
#define CACHE64_CTRL_CLCR_LADSEL(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)

#define CACHE64_CTRL_CLCR_LACC_MASK              (0x8000000U)
#define CACHE64_CTRL_CLCR_LACC_SHIFT             (27U)
/*! LACC - Line Access Type
 *  0b0..Read
 *  0b1..Write
 */
#define CACHE64_CTRL_CLCR_LACC(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/*! @} */

/*! @name CSAR - Cache Search Address */
/*! @{ */

#define CACHE64_CTRL_CSAR_LGO_MASK               (0x1U)
#define CACHE64_CTRL_CSAR_LGO_SHIFT              (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect; Read: no line command active
 *  0b1..Write: initiate line command; Read: line command active
 */
#define CACHE64_CTRL_CSAR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK)

#define CACHE64_CTRL_CSAR_PHYADDR_MASK           (0xFFFFFFFEU)
#define CACHE64_CTRL_CSAR_PHYADDR_SHIFT          (1U)
/*! PHYADDR - Physical Address */
#define CACHE64_CTRL_CSAR_PHYADDR(x)             (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR_MASK)
/*! @} */

/*! @name CCVR - Cache Read/Write Value */
/*! @{ */

#define CACHE64_CTRL_CCVR_DATA_MASK              (0xFFFFFFFFU)
#define CACHE64_CTRL_CCVR_DATA_SHIFT             (0U)
/*! DATA - Cache Read/Write Data */
#define CACHE64_CTRL_CCVR_DATA(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CACHE64_CTRL_Register_Masks */


/* CACHE64_CTRL - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CACHE64_CTRL0 base address */
  #define CACHE64_CTRL0_BASE                       (0x50035000u)
  /** Peripheral CACHE64_CTRL0 base address */
  #define CACHE64_CTRL0_BASE_NS                    (0x40035000u)
  /** Peripheral CACHE64_CTRL0 base pointer */
  #define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
  /** Peripheral CACHE64_CTRL0 base pointer */
  #define CACHE64_CTRL0_NS                         ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS)
  /** Peripheral CACHE64_CTRL1 base address */
  #define CACHE64_CTRL1_BASE                       (0x50036000u)
  /** Peripheral CACHE64_CTRL1 base address */
  #define CACHE64_CTRL1_BASE_NS                    (0x40036000u)
  /** Peripheral CACHE64_CTRL1 base pointer */
  #define CACHE64_CTRL1                            ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE)
  /** Peripheral CACHE64_CTRL1 base pointer */
  #define CACHE64_CTRL1_NS                         ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE_NS)
  /** Array initializer of CACHE64_CTRL peripheral base addresses */
  #define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
  /** Array initializer of CACHE64_CTRL peripheral base pointers */
  #define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0, CACHE64_CTRL1 }
  /** Array initializer of CACHE64_CTRL peripheral base addresses */
  #define CACHE64_CTRL_BASE_ADDRS_NS               { CACHE64_CTRL0_BASE_NS, CACHE64_CTRL1_BASE_NS }
  /** Array initializer of CACHE64_CTRL peripheral base pointers */
  #define CACHE64_CTRL_BASE_PTRS_NS                { CACHE64_CTRL0_NS, CACHE64_CTRL1_NS }
#else
  /** Peripheral CACHE64_CTRL0 base address */
  #define CACHE64_CTRL0_BASE                       (0x40035000u)
  /** Peripheral CACHE64_CTRL0 base pointer */
  #define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
  /** Peripheral CACHE64_CTRL1 base address */
  #define CACHE64_CTRL1_BASE                       (0x40036000u)
  /** Peripheral CACHE64_CTRL1 base pointer */
  #define CACHE64_CTRL1                            ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE)
  /** Array initializer of CACHE64_CTRL peripheral base addresses */
  #define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
  /** Array initializer of CACHE64_CTRL peripheral base pointers */
  #define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0, CACHE64_CTRL1 }
#endif

/*!
 * @}
 */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CACHE64_POLSEL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer
 * @{
 */

/** CACHE64_POLSEL - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[20];
  __IO uint32_t REG0_TOP;                          /**< Region 0 Top Boundary, offset: 0x14 */
  __IO uint32_t REG1_TOP;                          /**< Region 1 Top Boundary, offset: 0x18 */
  __IO uint32_t POLSEL;                            /**< Policy Select, offset: 0x1C */
} CACHE64_POLSEL_Type;

/* ----------------------------------------------------------------------------
   -- CACHE64_POLSEL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks
 * @{
 */

/*! @name REG0_TOP - Region 0 Top Boundary */
/*! @{ */

#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK    (0x7FFFC00U)
#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT   (10U)
/*! REG0_TOP - Upper Limit Of Region 0 */
#define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK)
/*! @} */

/*! @name REG1_TOP - Region 1 Top Boundary */
/*! @{ */

#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK    (0x7FFFC00U)
#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT   (10U)
/*! REG1_TOP - Upper Limit Of Region 1 */
#define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK)
/*! @} */

/*! @name POLSEL - Policy Select */
/*! @{ */

#define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK   (0x3U)
#define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT  (0U)
/*! REG0_POLICY - Policy Select For Region 0
 *  0b00..Noncacheable
 *  0b01..Write-through
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG0_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK)

#define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK   (0xCU)
#define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT  (2U)
/*! REG1_POLICY - Policy Select For Region 1
 *  0b00..Noncacheable
 *  0b01..Write-through
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG1_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK)

#define CACHE64_POLSEL_POLSEL_REG2_POLICY_MASK   (0x30U)
#define CACHE64_POLSEL_POLSEL_REG2_POLICY_SHIFT  (4U)
/*! REG2_POLICY - Policy Select For Region 2
 *  0b00..Noncacheable
 *  0b01..Write-through
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG2_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG2_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG2_POLICY_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CACHE64_POLSEL_Register_Masks */


/* CACHE64_POLSEL - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CACHE64_POLSEL0 base address */
  #define CACHE64_POLSEL0_BASE                     (0x50035000u)
  /** Peripheral CACHE64_POLSEL0 base address */
  #define CACHE64_POLSEL0_BASE_NS                  (0x40035000u)
  /** Peripheral CACHE64_POLSEL0 base pointer */
  #define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
  /** Peripheral CACHE64_POLSEL0 base pointer */
  #define CACHE64_POLSEL0_NS                       ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS)
  /** Peripheral CACHE64_POLSEL1 base address */
  #define CACHE64_POLSEL1_BASE                     (0x50036000u)
  /** Peripheral CACHE64_POLSEL1 base address */
  #define CACHE64_POLSEL1_BASE_NS                  (0x40036000u)
  /** Peripheral CACHE64_POLSEL1 base pointer */
  #define CACHE64_POLSEL1                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE)
  /** Peripheral CACHE64_POLSEL1 base pointer */
  #define CACHE64_POLSEL1_NS                       ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE_NS)
  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
  #define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE, CACHE64_POLSEL1_BASE }
  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
  #define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0, CACHE64_POLSEL1 }
  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
  #define CACHE64_POLSEL_BASE_ADDRS_NS             { CACHE64_POLSEL0_BASE_NS, CACHE64_POLSEL1_BASE_NS }
  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
  #define CACHE64_POLSEL_BASE_PTRS_NS              { CACHE64_POLSEL0_NS, CACHE64_POLSEL1_NS }
#else
  /** Peripheral CACHE64_POLSEL0 base address */
  #define CACHE64_POLSEL0_BASE                     (0x40035000u)
  /** Peripheral CACHE64_POLSEL0 base pointer */
  #define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
  /** Peripheral CACHE64_POLSEL1 base address */
  #define CACHE64_POLSEL1_BASE                     (0x40036000u)
  /** Peripheral CACHE64_POLSEL1 base pointer */
  #define CACHE64_POLSEL1                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE)
  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
  #define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE, CACHE64_POLSEL1_BASE }
  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
  #define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0, CACHE64_POLSEL1 }
#endif

/*!
 * @}
 */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CDOG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
 * @{
 */

/** CDOG - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONTROL;                           /**< Control Register, offset: 0x0 */
  __IO uint32_t RELOAD;                            /**< Instruction Timer Reload Register, offset: 0x4 */
  __I  uint32_t INSTRUCTION_TIMER;                 /**< Instruction Timer Register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __I  uint32_t STATUS;                            /**< Status 1 Register, offset: 0x10 */
  __I  uint32_t STATUS2;                           /**< Status 2 Register, offset: 0x14 */
  __IO uint32_t FLAGS;                             /**< Flags Register, offset: 0x18 */
  __IO uint32_t PERSISTENT;                        /**< Persistent Data Storage Register, offset: 0x1C */
  __O  uint32_t START;                             /**< START Command Register, offset: 0x20 */
  __O  uint32_t STOP;                              /**< STOP Command Register, offset: 0x24 */
  __O  uint32_t RESTART;                           /**< RESTART Command Register, offset: 0x28 */
  __O  uint32_t ADD;                               /**< ADD Command Register, offset: 0x2C */
  __O  uint32_t ADD1;                              /**< ADD1 Command Register, offset: 0x30 */
  __O  uint32_t ADD16;                             /**< ADD16 Command Register, offset: 0x34 */
  __O  uint32_t ADD256;                            /**< ADD256 Command Register, offset: 0x38 */
  __O  uint32_t SUB;                               /**< SUB Command Register, offset: 0x3C */
  __O  uint32_t SUB1;                              /**< SUB1 Command Register, offset: 0x40 */
  __O  uint32_t SUB16;                             /**< SUB16 Command Register, offset: 0x44 */
  __O  uint32_t SUB256;                            /**< SUB256 Command Register, offset: 0x48 */
  __O  uint32_t ASSERT16;                          /**< ASSERT16 Command Register, offset: 0x4C */
} CDOG_Type;

/* ----------------------------------------------------------------------------
   -- CDOG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CDOG_Register_Masks CDOG Register Masks
 * @{
 */

/*! @name CONTROL - Control Register */
/*! @{ */

#define CDOG_CONTROL_LOCK_CTRL_MASK              (0x3U)
#define CDOG_CONTROL_LOCK_CTRL_SHIFT             (0U)
/*! LOCK_CTRL - Lock control
 *  0b01..Locked
 *  0b10..Unlocked
 */
#define CDOG_CONTROL_LOCK_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)

#define CDOG_CONTROL_TIMEOUT_CTRL_MASK           (0x1CU)
#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT          (2U)
/*! TIMEOUT_CTRL - TIMEOUT fault control
 *  0b100..Disable both reset and interrupt
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 */
#define CDOG_CONTROL_TIMEOUT_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)

#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK        (0xE0U)
#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT       (5U)
/*! MISCOMPARE_CTRL - MISCOMPARE fault control
 *  0b100..Disable both reset and interrupt
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 */
#define CDOG_CONTROL_MISCOMPARE_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)

#define CDOG_CONTROL_SEQUENCE_CTRL_MASK          (0x700U)
#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT         (8U)
/*! SEQUENCE_CTRL - SEQUENCE fault control
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 *  0b100..Disable both reset and interrupt
 */
#define CDOG_CONTROL_SEQUENCE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)

#define CDOG_CONTROL_STATE_CTRL_MASK             (0x1C000U)
#define CDOG_CONTROL_STATE_CTRL_SHIFT            (14U)
/*! STATE_CTRL - STATE fault control
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 *  0b100..Disable both reset and interrupt
 */
#define CDOG_CONTROL_STATE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)

#define CDOG_CONTROL_ADDRESS_CTRL_MASK           (0xE0000U)
#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT          (17U)
/*! ADDRESS_CTRL - ADDRESS fault control
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 *  0b100..Disable both reset and interrupt
 */
#define CDOG_CONTROL_ADDRESS_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)

#define CDOG_CONTROL_IRQ_PAUSE_MASK              (0x30000000U)
#define CDOG_CONTROL_IRQ_PAUSE_SHIFT             (28U)
/*! IRQ_PAUSE - IRQ pause control
 *  0b01..Keep the timer running
 *  0b10..Stop the timer
 */
#define CDOG_CONTROL_IRQ_PAUSE(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)

#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK        (0xC0000000U)
#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT       (30U)
/*! DEBUG_HALT_CTRL - DEBUG_HALT control
 *  0b01..Keep the timer running
 *  0b10..Stop the timer
 */
#define CDOG_CONTROL_DEBUG_HALT_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
/*! @} */

/*! @name RELOAD - Instruction Timer Reload Register */
/*! @{ */

#define CDOG_RELOAD_RLOAD_MASK                   (0xFFFFFFFFU)
#define CDOG_RELOAD_RLOAD_SHIFT                  (0U)
/*! RLOAD - Instruction Timer reload value */
#define CDOG_RELOAD_RLOAD(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
/*! @} */

/*! @name INSTRUCTION_TIMER - Instruction Timer Register */
/*! @{ */

#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK       (0xFFFFFFFFU)
#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT      (0U)
/*! INSTIM - Current value of the Instruction Timer */
#define CDOG_INSTRUCTION_TIMER_INSTIM(x)         (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
/*! @} */

/*! @name STATUS - Status 1 Register */
/*! @{ */

#define CDOG_STATUS_NUMTOF_MASK                  (0xFFU)
#define CDOG_STATUS_NUMTOF_SHIFT                 (0U)
/*! NUMTOF - Number of TIMEOUT faults (FLAGS[TIMEOUT_FLAG]) since the last POR */
#define CDOG_STATUS_NUMTOF(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)

#define CDOG_STATUS_NUMMISCOMPF_MASK             (0xFF00U)
#define CDOG_STATUS_NUMMISCOMPF_SHIFT            (8U)
/*! NUMMISCOMPF - Number of MISCOMPARE faults (FLAGS[MISCOMPARE_FLAG]) since the last POR */
#define CDOG_STATUS_NUMMISCOMPF(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)

#define CDOG_STATUS_NUMILSEQF_MASK               (0xFF0000U)
#define CDOG_STATUS_NUMILSEQF_SHIFT              (16U)
/*! NUMILSEQF - Number of SEQUENCE faults (FLAGS[SEQUENCE_FLAG]) since the last POR */
#define CDOG_STATUS_NUMILSEQF(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)

#define CDOG_STATUS_CURST_MASK                   (0xF0000000U)
#define CDOG_STATUS_CURST_SHIFT                  (28U)
/*! CURST - Current State */
#define CDOG_STATUS_CURST(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
/*! @} */

/*! @name STATUS2 - Status 2 Register */
/*! @{ */

#define CDOG_STATUS2_NUMCNTF_MASK                (0xFFU)
#define CDOG_STATUS2_NUMCNTF_SHIFT               (0U)
/*! NUMCNTF - Number of CONTROL faults (FLAGS[CONTROL_FLAG]) since the last POR */
#define CDOG_STATUS2_NUMCNTF(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)

#define CDOG_STATUS2_NUMILLSTF_MASK              (0xFF00U)
#define CDOG_STATUS2_NUMILLSTF_SHIFT             (8U)
/*! NUMILLSTF - Number of STATE faults (FLAGS[STATE_FLAG]) since the last POR */
#define CDOG_STATUS2_NUMILLSTF(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)

#define CDOG_STATUS2_NUMILLA_MASK                (0xFF0000U)
#define CDOG_STATUS2_NUMILLA_SHIFT               (16U)
/*! NUMILLA - Number of ADDRESS faults (FLAGS[ADDR_FLAG]) since the last POR */
#define CDOG_STATUS2_NUMILLA(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
/*! @} */

/*! @name FLAGS - Flags Register */
/*! @{ */

#define CDOG_FLAGS_TO_FLAG_MASK                  (0x1U)
#define CDOG_FLAGS_TO_FLAG_SHIFT                 (0U)
/*! TO_FLAG - TIMEOUT fault flag
 *  0b0..A TIMEOUT fault has not occurred
 *  0b1..A TIMEOUT fault has occurred
 */
#define CDOG_FLAGS_TO_FLAG(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)

#define CDOG_FLAGS_MISCOM_FLAG_MASK              (0x2U)
#define CDOG_FLAGS_MISCOM_FLAG_SHIFT             (1U)
/*! MISCOM_FLAG - MISCOMPARE fault flag
 *  0b0..A MISCOMPARE fault has not occurred
 *  0b1..A MISCOMPARE fault has occurred
 */
#define CDOG_FLAGS_MISCOM_FLAG(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)

#define CDOG_FLAGS_SEQ_FLAG_MASK                 (0x4U)
#define CDOG_FLAGS_SEQ_FLAG_SHIFT                (2U)
/*! SEQ_FLAG - SEQUENCE fault flag
 *  0b0..A SEQUENCE fault has not occurred
 *  0b1..A SEQUENCE fault has occurred
 */
#define CDOG_FLAGS_SEQ_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)

#define CDOG_FLAGS_CNT_FLAG_MASK                 (0x8U)
#define CDOG_FLAGS_CNT_FLAG_SHIFT                (3U)
/*! CNT_FLAG - CONTROL fault flag
 *  0b0..A CONTROL fault has not occurred
 *  0b1..A CONTROL fault has occurred
 */
#define CDOG_FLAGS_CNT_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)

#define CDOG_FLAGS_STATE_FLAG_MASK               (0x10U)
#define CDOG_FLAGS_STATE_FLAG_SHIFT              (4U)
/*! STATE_FLAG - STATE fault flag
 *  0b0..A STATE fault has not occurred
 *  0b1..A STATE fault has occurred
 */
#define CDOG_FLAGS_STATE_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)

#define CDOG_FLAGS_ADDR_FLAG_MASK                (0x20U)
#define CDOG_FLAGS_ADDR_FLAG_SHIFT               (5U)
/*! ADDR_FLAG - ADDRESS fault flag
 *  0b0..An ADDRESS fault has not occurred
 *  0b1..An ADDRESS fault has occurred
 */
#define CDOG_FLAGS_ADDR_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)

#define CDOG_FLAGS_POR_FLAG_MASK                 (0x10000U)
#define CDOG_FLAGS_POR_FLAG_SHIFT                (16U)
/*! POR_FLAG - Power-on reset flag
 *  0b0..A Power-on reset event has not occurred
 *  0b1..A Power-on reset event has occurred
 */
#define CDOG_FLAGS_POR_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
/*! @} */

/*! @name PERSISTENT - Persistent Data Storage Register */
/*! @{ */

#define CDOG_PERSISTENT_PERSIS_MASK              (0xFFFFFFFFU)
#define CDOG_PERSISTENT_PERSIS_SHIFT             (0U)
/*! PERSIS - Persistent Storage */
#define CDOG_PERSISTENT_PERSIS(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
/*! @} */

/*! @name START - START Command Register */
/*! @{ */

#define CDOG_START_STRT_MASK                     (0xFFFFFFFFU)
#define CDOG_START_STRT_SHIFT                    (0U)
/*! STRT - Start command */
#define CDOG_START_STRT(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
/*! @} */

/*! @name STOP - STOP Command Register */
/*! @{ */

#define CDOG_STOP_STP_MASK                       (0xFFFFFFFFU)
#define CDOG_STOP_STP_SHIFT                      (0U)
/*! STP - Stop command */
#define CDOG_STOP_STP(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
/*! @} */

/*! @name RESTART - RESTART Command Register */
/*! @{ */

#define CDOG_RESTART_RSTRT_MASK                  (0xFFFFFFFFU)
#define CDOG_RESTART_RSTRT_SHIFT                 (0U)
/*! RSTRT - Restart command */
#define CDOG_RESTART_RSTRT(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
/*! @} */

/*! @name ADD - ADD Command Register */
/*! @{ */

#define CDOG_ADD_AD_MASK                         (0xFFFFFFFFU)
#define CDOG_ADD_AD_SHIFT                        (0U)
/*! AD - ADD Write Value */
#define CDOG_ADD_AD(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
/*! @} */

/*! @name ADD1 - ADD1 Command Register */
/*! @{ */

#define CDOG_ADD1_AD1_MASK                       (0xFFFFFFFFU)
#define CDOG_ADD1_AD1_SHIFT                      (0U)
/*! AD1 - ADD 1 */
#define CDOG_ADD1_AD1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
/*! @} */

/*! @name ADD16 - ADD16 Command Register */
/*! @{ */

#define CDOG_ADD16_AD16_MASK                     (0xFFFFFFFFU)
#define CDOG_ADD16_AD16_SHIFT                    (0U)
/*! AD16 - ADD 16 */
#define CDOG_ADD16_AD16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
/*! @} */

/*! @name ADD256 - ADD256 Command Register */
/*! @{ */

#define CDOG_ADD256_AD256_MASK                   (0xFFFFFFFFU)
#define CDOG_ADD256_AD256_SHIFT                  (0U)
/*! AD256 - ADD 256 */
#define CDOG_ADD256_AD256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
/*! @} */

/*! @name SUB - SUB Command Register */
/*! @{ */

#define CDOG_SUB_SB_MASK                         (0xFFFFFFFFU)
#define CDOG_SUB_SB_SHIFT                        (0U)
/*! SB - Subtract Write Value */
#define CDOG_SUB_SB(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK)
/*! @} */

/*! @name SUB1 - SUB1 Command Register */
/*! @{ */

#define CDOG_SUB1_SB1_MASK                       (0xFFFFFFFFU)
#define CDOG_SUB1_SB1_SHIFT                      (0U)
/*! SB1 - Subtract 1 */
#define CDOG_SUB1_SB1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK)
/*! @} */

/*! @name SUB16 - SUB16 Command Register */
/*! @{ */

#define CDOG_SUB16_SB16_MASK                     (0xFFFFFFFFU)
#define CDOG_SUB16_SB16_SHIFT                    (0U)
/*! SB16 - Subtract 16 */
#define CDOG_SUB16_SB16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
/*! @} */

/*! @name SUB256 - SUB256 Command Register */
/*! @{ */

#define CDOG_SUB256_SB256_MASK                   (0xFFFFFFFFU)
#define CDOG_SUB256_SB256_SHIFT                  (0U)
/*! SB256 - Subtract 256 */
#define CDOG_SUB256_SB256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
/*! @} */

/*! @name ASSERT16 - ASSERT16 Command Register */
/*! @{ */

#define CDOG_ASSERT16_AST16_MASK                 (0xFFFFFFFFU)
#define CDOG_ASSERT16_AST16_SHIFT                (0U)
/*! AST16 - ASSERT16 Command */
#define CDOG_ASSERT16_AST16(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CDOG_Register_Masks */


/* CDOG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CDOG0 base address */
  #define CDOG0_BASE                               (0x50115000u)
  /** Peripheral CDOG0 base address */
  #define CDOG0_BASE_NS                            (0x40115000u)
  /** Peripheral CDOG0 base pointer */
  #define CDOG0                                    ((CDOG_Type *)CDOG0_BASE)
  /** Peripheral CDOG0 base pointer */
  #define CDOG0_NS                                 ((CDOG_Type *)CDOG0_BASE_NS)
  /** Peripheral CDOG1 base address */
  #define CDOG1_BASE                               (0x50116000u)
  /** Peripheral CDOG1 base address */
  #define CDOG1_BASE_NS                            (0x40116000u)
  /** Peripheral CDOG1 base pointer */
  #define CDOG1                                    ((CDOG_Type *)CDOG1_BASE)
  /** Peripheral CDOG1 base pointer */
  #define CDOG1_NS                                 ((CDOG_Type *)CDOG1_BASE_NS)
  /** Peripheral CDOG2 base address */
  #define CDOG2_BASE                               (0x50117000u)
  /** Peripheral CDOG2 base address */
  #define CDOG2_BASE_NS                            (0x40117000u)
  /** Peripheral CDOG2 base pointer */
  #define CDOG2                                    ((CDOG_Type *)CDOG2_BASE)
  /** Peripheral CDOG2 base pointer */
  #define CDOG2_NS                                 ((CDOG_Type *)CDOG2_BASE_NS)
  /** Array initializer of CDOG peripheral base addresses */
  #define CDOG_BASE_ADDRS                          { CDOG0_BASE, CDOG1_BASE, CDOG2_BASE }
  /** Array initializer of CDOG peripheral base pointers */
  #define CDOG_BASE_PTRS                           { CDOG0, CDOG1, CDOG2 }
  /** Array initializer of CDOG peripheral base addresses */
  #define CDOG_BASE_ADDRS_NS                       { CDOG0_BASE_NS, CDOG1_BASE_NS, CDOG2_BASE_NS }
  /** Array initializer of CDOG peripheral base pointers */
  #define CDOG_BASE_PTRS_NS                        { CDOG0_NS, CDOG1_NS, CDOG2_NS }
#else
  /** Peripheral CDOG0 base address */
  #define CDOG0_BASE                               (0x40115000u)
  /** Peripheral CDOG0 base pointer */
  #define CDOG0                                    ((CDOG_Type *)CDOG0_BASE)
  /** Peripheral CDOG1 base address */
  #define CDOG1_BASE                               (0x40116000u)
  /** Peripheral CDOG1 base pointer */
  #define CDOG1                                    ((CDOG_Type *)CDOG1_BASE)
  /** Peripheral CDOG2 base address */
  #define CDOG2_BASE                               (0x40117000u)
  /** Peripheral CDOG2 base pointer */
  #define CDOG2                                    ((CDOG_Type *)CDOG2_BASE)
  /** Array initializer of CDOG peripheral base addresses */
  #define CDOG_BASE_ADDRS                          { CDOG0_BASE, CDOG1_BASE, CDOG2_BASE }
  /** Array initializer of CDOG peripheral base pointers */
  #define CDOG_BASE_PTRS                           { CDOG0, CDOG1, CDOG2 }
#endif

/*!
 * @}
 */ /* end of group CDOG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CLKCTL0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL0_Peripheral_Access_Layer CLKCTL0 Peripheral Access Layer
 * @{
 */

/** CLKCTL0 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PSCCTL0;                           /**< VDD2_COMP Peripheral Clock Control 0, offset: 0x10 */
  __IO uint32_t PSCCTL1;                           /**< VDD2_COMP Peripheral Clock Control 1, offset: 0x14 */
  __IO uint32_t PSCCTL2;                           /**< VDD2_COMP Peripheral Clock Control 2, offset: 0x18 */
  __IO uint32_t PSCCTL3;                           /**< VDD2_COMP Peripheral Clock Control 3, offset: 0x1C */
  __IO uint32_t PSCCTL4;                           /**< VDD2_COMP Peripheral Clock Control 4, offset: 0x20 */
  __IO uint32_t PSCCTL5;                           /**< VDD2_COMP Peripheral Clock Control 5, offset: 0x24 */
       uint8_t RESERVED_1[24];
  __IO uint32_t PSCCTL0_SET;                       /**< VDD2_COMP Peripheral Clock Control 0 Set, offset: 0x40 */
  __IO uint32_t PSCCTL1_SET;                       /**< VDD2_COMP Peripheral Clock Control 1 Set, offset: 0x44 */
  __IO uint32_t PSCCTL2_SET;                       /**< VDD2_COMP Peripheral Clock Control 2 Set, offset: 0x48 */
  __IO uint32_t PSCCTL3_SET;                       /**< VDD2_COMP Peripheral Clock Control 3 Set, offset: 0x4C */
  __IO uint32_t PSCCTL4_SET;                       /**< VDD2_COMP Peripheral Clock Control 4 Set, offset: 0x50 */
  __IO uint32_t PSCCTL5_SET;                       /**< VDD2_COMP Peripheral Clock Control 5 Set, offset: 0x54 */
       uint8_t RESERVED_2[24];
  __IO uint32_t PSCCTL0_CLR;                       /**< VDD2_COMP Peripheral Clock Control 0 Clear, offset: 0x70 */
  __IO uint32_t PSCCTL1_CLR;                       /**< VDD2_COMP Peripheral Clock Control 1 Clear, offset: 0x74 */
  __IO uint32_t PSCCTL2_CLR;                       /**< VDD2_COMP Peripheral Clock Control 2 Clear, offset: 0x78 */
  __IO uint32_t PSCCTL3_CLR;                       /**< VDD2_COMP Peripheral Clock Control 3 Clear, offset: 0x7C */
  __IO uint32_t PSCCTL4_CLR;                       /**< VDD2_COMP Peripheral Clock Control 4 Clear, offset: 0x80 */
  __IO uint32_t PSCCTL5_CLR;                       /**< VDD2_COMP Peripheral Clock Control 5 Clear, offset: 0x84 */
       uint8_t RESERVED_3[8];
  __IO uint32_t ONE_SRC_CLKSLICE_ENABLE;           /**< One Source Clock Slice Enable, offset: 0x90 */
       uint8_t RESERVED_4[132];
  __I  uint32_t FRO01CLKSTATUS;                    /**< FRO_TUNER0 and FRO_TUNER1 Clock Status, offset: 0x118 */
       uint8_t RESERVED_5[12];
  __IO uint32_t FRO0MAXDOMAINEN;                   /**< FRO0MAX Clock Domain Enable, offset: 0x128 */
       uint8_t RESERVED_6[724];
  __IO uint32_t MAINCLKDIV;                        /**< VDD2_COMP Main Clock Divider, offset: 0x400 */
       uint8_t RESERVED_7[28];
  __IO uint32_t CMPTBASECLKSEL;                    /**< VDD2_COMP Base Clock Select Source, offset: 0x420 */
  __IO uint32_t DSPBASECLKSEL;                     /**< VDD2_DSP Base Clock Select Source, offset: 0x424 */
  __IO uint32_t VDD2COMBASECLKSEL;                 /**< VDD2_COM Base Clock Select Source, offset: 0x428 */
       uint8_t RESERVED_8[8];
  __IO uint32_t MAINCLKSEL;                        /**< VDD2_COMP Main Clock Source Select, offset: 0x434 */
       uint8_t RESERVED_9[8];
  __IO uint32_t DSPCPUCLKDIV;                      /**< VDD2_DSP Clock Divider, offset: 0x440 */
  __IO uint32_t DSPCPUCLKSEL;                      /**< VDD2_DSP Clock Select Source, offset: 0x444 */
       uint8_t RESERVED_10[8];
  __IO uint32_t RAMCLKSEL;                         /**< RAM Clock Select Source, offset: 0x450 */
       uint8_t RESERVED_11[8];
  __IO uint32_t RAMCLKDIV;                         /**< RAM Clock Divider, offset: 0x45C */
       uint8_t RESERVED_12[256];
  __IO uint32_t TPIUFCLKSEL;                       /**< TPIU (TRACE_RT700) Functional Clock Select Source, offset: 0x560 */
  __IO uint32_t TPIUCLKDIV;                        /**< TPIU (TRACE_RT700) Functional Clock Divider, offset: 0x564 */
       uint8_t RESERVED_13[152];
  __IO uint32_t XSPI0FCLKSEL;                      /**< XSPI0 Functional Clock Source Select, offset: 0x600 */
  __IO uint32_t XSPI0FCLKDIV;                      /**< XSPI0 Functional Clock Divider, offset: 0x604 */
       uint8_t RESERVED_14[24];
  __IO uint32_t XSPI1FCLKSEL;                      /**< XSPI1 Functional Clock Select Source, offset: 0x620 */
  __IO uint32_t XSPI1FCLKDIV;                      /**< XSPI1 Functional Clock Divider, offset: 0x624 */
       uint8_t RESERVED_15[24];
  __IO uint32_t SCTFCLKSEL;                        /**< SCT Functional Clock Source Select, offset: 0x640 */
  __IO uint32_t SCTFCLKDIV;                        /**< SCT Functional Clock Divider, offset: 0x644 */
       uint8_t RESERVED_16[184];
  __IO uint32_t UTICK0FCLKSEL;                     /**< UTICK0 Functional Clock Select Source, offset: 0x700 */
  __IO uint32_t UTICK0FCLKDIV;                     /**< UTICK0 Functional Clock Divider, offset: 0x704 */
       uint8_t RESERVED_17[24];
  __IO uint32_t WWDT0FCLKSEL;                      /**< WWDT0 Functional Clock Source Select, offset: 0x720 */
       uint8_t RESERVED_18[28];
  __IO uint32_t WWDT1FCLKSEL;                      /**< WWDT1 Functional Clock Source Select, offset: 0x740 */
       uint8_t RESERVED_19[28];
  __IO uint32_t SYSTICKFCLKSEL;                    /**< SYSTICK Functional Clock Source Select, offset: 0x760 */
  __IO uint32_t SYSTICKFCLKDIV;                    /**< SYSTICK Functional Clock Divider, offset: 0x764 */
       uint8_t RESERVED_20[152];
  struct {                                         /* offset: 0x800, array step: 0x20 */
    __IO uint32_t FCCLKSEL;                          /**< LP_FLEXCOMM 0 to 13 Clock Source 0 Select..LP_FLEXCOMM 0 to 13 Clock Source 3 Select, array offset: 0x800, array step: 0x20, valid indices: [0-3] */
    __IO uint32_t FCCLKDIV;                          /**< LP_FLEXCOMM 0 to 13 Clock Source 0 Divider..LP_FLEXCOMM 0 to 13 Clock Source 3 Divider, array offset: 0x804, array step: 0x20, valid indices: [0-3] */
    __IO uint32_t FCFCLKSEL;                         /**< LP_FLEXCOMM0 Clock Source Select..LP_FLEXCOMM13 Clock Source Select, array offset: 0x808, array step: 0x20 */
         uint8_t RESERVED_0[20];
  } FLEXCOMM[14];
       uint8_t RESERVED_21[8];
  __IO uint32_t SAI012FCLKSEL;                     /**< SAI0, SAI1 and SAI2 Clock Source Select, offset: 0x9C8 */
  __IO uint32_t SAI012CLKDIV;                      /**< SAI0, SAI1 and SAI2 Functional Clock Divider, offset: 0x9CC */
       uint8_t RESERVED_22[48];
  __IO uint32_t CTIMERCLKDIV[5];                   /**< CTIMER0 Functional Clock Divider..CTIMER4 Functional Clock Divider, array offset: 0xA00, array step: 0x4 */
       uint8_t RESERVED_23[140];
  __IO uint32_t CTIMERFCLKSEL[5];                  /**< CTIMER0 Functional Clock Source Select..CTIMER4 Functional Clock Source Select, array offset: 0xAA0, array step: 0x4 */
       uint8_t RESERVED_24[12];
  __IO uint32_t TRNGFCLKSEL;                       /**< TRNG Functional Clock Source Select, offset: 0xAC0 */
  __IO uint32_t TRNGFCLKDIV;                       /**< TRNG FCLK Clock Divider, offset: 0xAC4 */
       uint8_t RESERVED_25[56];
  __IO uint32_t I3C01FCLKSEL;                      /**< I3C0 and I3C1 Functional Clock Source Select, offset: 0xB00 */
  __IO uint32_t I3C01PCLKSEL;                      /**< I3C0 and I3C1 P-CLK Source Select, offset: 0xB04 */
  __IO uint32_t I3C01PCLKDIV;                      /**< I3C0 and I3C1 P-CLK Divider, offset: 0xB08 */
       uint8_t RESERVED_26[4];
  __IO uint32_t I3C01FCLKDIV;                      /**< I3C0 and I3C1 Functional Clock Divider, offset: 0xB10 */
       uint8_t RESERVED_27[12];
  __IO uint32_t CLKOUTCLKSEL;                      /**< CLKOUT_VDD2 Clock Select Source, offset: 0xB20 */
  __IO uint32_t CLKOUTCLKDIV;                      /**< CLKOUT_VDD2 Clock Divider, offset: 0xB24 */
       uint8_t RESERVED_28[8];
  __IO uint32_t AUDIOVDD2CLKSEL;                   /**< VDD2_COMP Audio Clock Source Select, offset: 0xB30 */
} CLKCTL0_Type;

/* ----------------------------------------------------------------------------
   -- CLKCTL0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL0_Register_Masks CLKCTL0 Register Masks
 * @{
 */

/*! @name PSCCTL0 - VDD2_COMP Peripheral Clock Control 0 */
/*! @{ */

#define CLKCTL0_PSCCTL0_CODE_CACHE_MASK          (0x2U)
#define CLKCTL0_PSCCTL0_CODE_CACHE_SHIFT         (1U)
/*! CODE_CACHE - Code Cache Clock (XCACHE 1)
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_CODE_CACHE(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CODE_CACHE_SHIFT)) & CLKCTL0_PSCCTL0_CODE_CACHE_MASK)

#define CLKCTL0_PSCCTL0_SYSTEM_CACHE_MASK        (0x4U)
#define CLKCTL0_PSCCTL0_SYSTEM_CACHE_SHIFT       (2U)
/*! SYSTEM_CACHE - System Cache Clock (XCACHE 0)
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SYSTEM_CACHE(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SYSTEM_CACHE_SHIFT)) & CLKCTL0_PSCCTL0_SYSTEM_CACHE_MASK)

#define CLKCTL0_PSCCTL0_VDD2_OTP0_MASK           (0x20U)
#define CLKCTL0_PSCCTL0_VDD2_OTP0_SHIFT          (5U)
/*! VDD2_OTP0 - VDD2_OTP_CTRL0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_VDD2_OTP0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_VDD2_OTP0_SHIFT)) & CLKCTL0_PSCCTL0_VDD2_OTP0_MASK)

#define CLKCTL0_PSCCTL0_SLEEPCON0_MASK           (0x1000U)
#define CLKCTL0_PSCCTL0_SLEEPCON0_SHIFT          (12U)
/*! SLEEPCON0 - SLEEPCON0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SLEEPCON0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SLEEPCON0_SHIFT)) & CLKCTL0_PSCCTL0_SLEEPCON0_MASK)

#define CLKCTL0_PSCCTL0_SYSCON0_MASK             (0x2000U)
#define CLKCTL0_PSCCTL0_SYSCON0_SHIFT            (13U)
/*! SYSCON0 - SYSCON0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SYSCON0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SYSCON0_SHIFT)) & CLKCTL0_PSCCTL0_SYSCON0_MASK)

#define CLKCTL0_PSCCTL0_GLIKEY0_MASK             (0x4000U)
#define CLKCTL0_PSCCTL0_GLIKEY0_SHIFT            (14U)
/*! GLIKEY0 - GLIKEY0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_GLIKEY0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_GLIKEY0_SHIFT)) & CLKCTL0_PSCCTL0_GLIKEY0_MASK)

#define CLKCTL0_PSCCTL0_GLIKEY3_MASK             (0x8000U)
#define CLKCTL0_PSCCTL0_GLIKEY3_SHIFT            (15U)
/*! GLIKEY3 - GLIKEY3 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_GLIKEY3(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_GLIKEY3_SHIFT)) & CLKCTL0_PSCCTL0_GLIKEY3_MASK)
/*! @} */

/*! @name PSCCTL1 - VDD2_COMP Peripheral Clock Control 1 */
/*! @{ */

#define CLKCTL0_PSCCTL1_TPIU_TRACE_CLKIN_MASK    (0x4U)
#define CLKCTL0_PSCCTL1_TPIU_TRACE_CLKIN_SHIFT   (2U)
/*! TPIU_TRACE_CLKIN - TPIU_TRACE_CLKIN (TRACE_RT700) Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_TPIU_TRACE_CLKIN(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_TPIU_TRACE_CLKIN_SHIFT)) & CLKCTL0_PSCCTL1_TPIU_TRACE_CLKIN_MASK)

#define CLKCTL0_PSCCTL1_SWO_TRACECLKIN_MASK      (0x8U)
#define CLKCTL0_PSCCTL1_SWO_TRACECLKIN_SHIFT     (3U)
/*! SWO_TRACECLKIN - SWO_TRACECLKIN (TRACE_RT700) Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_SWO_TRACECLKIN(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SWO_TRACECLKIN_SHIFT)) & CLKCTL0_PSCCTL1_SWO_TRACECLKIN_MASK)

#define CLKCTL0_PSCCTL1_TSCLK_MASK               (0x10U)
#define CLKCTL0_PSCCTL1_TSCLK_SHIFT              (4U)
/*! TSCLK - TS (TRACE_RT700) Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_TSCLK(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_TSCLK_SHIFT)) & CLKCTL0_PSCCTL1_TSCLK_MASK)

#define CLKCTL0_PSCCTL1_EDMA0_MASK               (0x20U)
#define CLKCTL0_PSCCTL1_EDMA0_SHIFT              (5U)
/*! eDMA0 - eDMA0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_EDMA0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_EDMA0_SHIFT)) & CLKCTL0_PSCCTL1_EDMA0_MASK)

#define CLKCTL0_PSCCTL1_EDMA1_MASK               (0x40U)
#define CLKCTL0_PSCCTL1_EDMA1_SHIFT              (6U)
/*! eDMA1 - eDMA1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_EDMA1(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_EDMA1_SHIFT)) & CLKCTL0_PSCCTL1_EDMA1_MASK)

#define CLKCTL0_PSCCTL1_PKC_RAM_CTRL_MASK        (0x80U)
#define CLKCTL0_PSCCTL1_PKC_RAM_CTRL_SHIFT       (7U)
/*! PKC_RAM_CTRl - RAM Control Clock of PKC
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_PKC_RAM_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_PKC_RAM_CTRL_SHIFT)) & CLKCTL0_PSCCTL1_PKC_RAM_CTRL_MASK)

#define CLKCTL0_PSCCTL1_PKC_MASK                 (0x100U)
#define CLKCTL0_PSCCTL1_PKC_SHIFT                (8U)
/*! PKC - PKC Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_PKC(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_PKC_SHIFT)) & CLKCTL0_PSCCTL1_PKC_MASK)

#define CLKCTL0_PSCCTL1_ROMCP_MASK               (0x200U)
#define CLKCTL0_PSCCTL1_ROMCP_SHIFT              (9U)
/*! ROMCP - ROMCP Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_ROMCP(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_ROMCP_SHIFT)) & CLKCTL0_PSCCTL1_ROMCP_MASK)

#define CLKCTL0_PSCCTL1_XSPI0_MASK               (0x400U)
#define CLKCTL0_PSCCTL1_XSPI0_SHIFT              (10U)
/*! XSPI0 - XSPI0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_XSPI0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_XSPI0_SHIFT)) & CLKCTL0_PSCCTL1_XSPI0_MASK)

#define CLKCTL0_PSCCTL1_XSPI1_MASK               (0x800U)
#define CLKCTL0_PSCCTL1_XSPI1_SHIFT              (11U)
/*! XSPI1 - XSPI1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_XSPI1(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_XSPI1_MASK)

#define CLKCTL0_PSCCTL1_CACHE64_0_MASK           (0x1000U)
#define CLKCTL0_PSCCTL1_CACHE64_0_SHIFT          (12U)
/*! CACHE64_0 - CACHE64_0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_CACHE64_0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CACHE64_0_SHIFT)) & CLKCTL0_PSCCTL1_CACHE64_0_MASK)

#define CLKCTL0_PSCCTL1_CACHE64_1_MASK           (0x2000U)
#define CLKCTL0_PSCCTL1_CACHE64_1_SHIFT          (13U)
/*! CACHE64_1 - CACHE64_1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_CACHE64_1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CACHE64_1_SHIFT)) & CLKCTL0_PSCCTL1_CACHE64_1_MASK)

#define CLKCTL0_PSCCTL1_QK_SUBSYS_MASK           (0x4000U)
#define CLKCTL0_PSCCTL1_QK_SUBSYS_SHIFT          (14U)
/*! QK_SUBSYS - QK SUBSYS (PUF_CTRL) Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_QK_SUBSYS(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_QK_SUBSYS_SHIFT)) & CLKCTL0_PSCCTL1_QK_SUBSYS_MASK)

#define CLKCTL0_PSCCTL1_MMU0_MASK                (0x10000U)
#define CLKCTL0_PSCCTL1_MMU0_SHIFT               (16U)
/*! MMU0 - MMU0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_MMU0(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_MMU0_SHIFT)) & CLKCTL0_PSCCTL1_MMU0_MASK)

#define CLKCTL0_PSCCTL1_MMU1_MASK                (0x20000U)
#define CLKCTL0_PSCCTL1_MMU1_SHIFT               (17U)
/*! MMU1 - MMU1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_MMU1(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_MMU1_SHIFT)) & CLKCTL0_PSCCTL1_MMU1_MASK)

#define CLKCTL0_PSCCTL1_GPIO0_MASK               (0x40000U)
#define CLKCTL0_PSCCTL1_GPIO0_SHIFT              (18U)
/*! GPIO0 - GPIO0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_GPIO0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GPIO0_SHIFT)) & CLKCTL0_PSCCTL1_GPIO0_MASK)

#define CLKCTL0_PSCCTL1_GPIO1_MASK               (0x80000U)
#define CLKCTL0_PSCCTL1_GPIO1_SHIFT              (19U)
/*! GPIO1 - GPIO1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_GPIO1(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GPIO1_SHIFT)) & CLKCTL0_PSCCTL1_GPIO1_MASK)

#define CLKCTL0_PSCCTL1_GPIO2_MASK               (0x100000U)
#define CLKCTL0_PSCCTL1_GPIO2_SHIFT              (20U)
/*! GPIO2 - GPIO2 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_GPIO2(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GPIO2_SHIFT)) & CLKCTL0_PSCCTL1_GPIO2_MASK)

#define CLKCTL0_PSCCTL1_GPIO3_MASK               (0x200000U)
#define CLKCTL0_PSCCTL1_GPIO3_SHIFT              (21U)
/*! GPIO3 - GPIO3 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_GPIO3(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GPIO3_SHIFT)) & CLKCTL0_PSCCTL1_GPIO3_MASK)

#define CLKCTL0_PSCCTL1_GPIO4_MASK               (0x400000U)
#define CLKCTL0_PSCCTL1_GPIO4_SHIFT              (22U)
/*! GPIO4 - GPIO4 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_GPIO4(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GPIO4_SHIFT)) & CLKCTL0_PSCCTL1_GPIO4_MASK)

#define CLKCTL0_PSCCTL1_GPIO5_MASK               (0x800000U)
#define CLKCTL0_PSCCTL1_GPIO5_SHIFT              (23U)
/*! GPIO5 - GPIO5 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_GPIO5(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GPIO5_SHIFT)) & CLKCTL0_PSCCTL1_GPIO5_MASK)

#define CLKCTL0_PSCCTL1_GPIO6_MASK               (0x1000000U)
#define CLKCTL0_PSCCTL1_GPIO6_SHIFT              (24U)
/*! GPIO6 - GPIO6 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_GPIO6(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GPIO6_SHIFT)) & CLKCTL0_PSCCTL1_GPIO6_MASK)

#define CLKCTL0_PSCCTL1_GPIO7_MASK               (0x2000000U)
#define CLKCTL0_PSCCTL1_GPIO7_SHIFT              (25U)
/*! GPIO7 - GPIO7 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_GPIO7(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GPIO7_SHIFT)) & CLKCTL0_PSCCTL1_GPIO7_MASK)

#define CLKCTL0_PSCCTL1_SCT0_MASK                (0x4000000U)
#define CLKCTL0_PSCCTL1_SCT0_SHIFT               (26U)
/*! SCT0 - SCT0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_SCT0(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SCT0_SHIFT)) & CLKCTL0_PSCCTL1_SCT0_MASK)

#define CLKCTL0_PSCCTL1_CDOG0_MASK               (0x8000000U)
#define CLKCTL0_PSCCTL1_CDOG0_SHIFT              (27U)
/*! CDOG0 - CDOG0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_CDOG0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG0_SHIFT)) & CLKCTL0_PSCCTL1_CDOG0_MASK)

#define CLKCTL0_PSCCTL1_CDOG1_MASK               (0x10000000U)
#define CLKCTL0_PSCCTL1_CDOG1_SHIFT              (28U)
/*! CDOG1 - CDOG1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_CDOG1(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG1_SHIFT)) & CLKCTL0_PSCCTL1_CDOG1_MASK)

#define CLKCTL0_PSCCTL1_CDOG2_MASK               (0x20000000U)
#define CLKCTL0_PSCCTL1_CDOG2_SHIFT              (29U)
/*! CDOG2 - CDOG2 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_CDOG2(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CDOG2_MASK)

#define CLKCTL0_PSCCTL1_LP_FLEXCOMM0_MASK        (0x40000000U)
#define CLKCTL0_PSCCTL1_LP_FLEXCOMM0_SHIFT       (30U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_LP_FLEXCOMM0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_LP_FLEXCOMM0_SHIFT)) & CLKCTL0_PSCCTL1_LP_FLEXCOMM0_MASK)

#define CLKCTL0_PSCCTL1_LP_FLEXCOMM1_MASK        (0x80000000U)
#define CLKCTL0_PSCCTL1_LP_FLEXCOMM1_SHIFT       (31U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_PSCCTL1_LP_FLEXCOMM1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_LP_FLEXCOMM1_SHIFT)) & CLKCTL0_PSCCTL1_LP_FLEXCOMM1_MASK)
/*! @} */

/*! @name PSCCTL2 - VDD2_COMP Peripheral Clock Control 2 */
/*! @{ */

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM2_MASK        (0x1U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM2_SHIFT       (0U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM2(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM2_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM2_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM3_MASK        (0x2U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM3_SHIFT       (1U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM3(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM3_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM3_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM4_MASK        (0x4U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM4_SHIFT       (2U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM4(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM4_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM4_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM5_MASK        (0x8U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM5_SHIFT       (3U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM5(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM5_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM5_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM6_MASK        (0x10U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM6_SHIFT       (4U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM6(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM6_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM6_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM7_MASK        (0x20U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM7_SHIFT       (5U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM7(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM7_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM7_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM8_MASK        (0x40U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM8_SHIFT       (6U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM8(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM8_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM8_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM9_MASK        (0x80U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM9_SHIFT       (7U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM9(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM9_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM9_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM10_MASK       (0x100U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM10_SHIFT      (8U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM10(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM10_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM10_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM11_MASK       (0x200U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM11_SHIFT      (9U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM11(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM11_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM11_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM12_MASK       (0x400U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM12_SHIFT      (10U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM12(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM12_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM12_MASK)

#define CLKCTL0_PSCCTL2_LP_FLEXCOMM13_MASK       (0x800U)
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM13_SHIFT      (11U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_LP_FLEXCOMM13(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LP_FLEXCOMM13_SHIFT)) & CLKCTL0_PSCCTL2_LP_FLEXCOMM13_MASK)

#define CLKCTL0_PSCCTL2_SAI0_MASK                (0x2000U)
#define CLKCTL0_PSCCTL2_SAI0_SHIFT               (13U)
/*! SAI0 - SAI0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SAI0(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SAI0_SHIFT)) & CLKCTL0_PSCCTL2_SAI0_MASK)

#define CLKCTL0_PSCCTL2_SAI1_MASK                (0x4000U)
#define CLKCTL0_PSCCTL2_SAI1_SHIFT               (14U)
/*! SAI1 - SAI1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SAI1(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SAI1_SHIFT)) & CLKCTL0_PSCCTL2_SAI1_MASK)

#define CLKCTL0_PSCCTL2_SAI2_MASK                (0x8000U)
#define CLKCTL0_PSCCTL2_SAI2_SHIFT               (15U)
/*! SAI2 - SAI2 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SAI2(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_SAI2_MASK)

#define CLKCTL0_PSCCTL2_I3C0_MASK                (0x10000U)
#define CLKCTL0_PSCCTL2_I3C0_SHIFT               (16U)
/*! I3C0 - I3C0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_I3C0(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_I3C0_SHIFT)) & CLKCTL0_PSCCTL2_I3C0_MASK)

#define CLKCTL0_PSCCTL2_I3C1_MASK                (0x20000U)
#define CLKCTL0_PSCCTL2_I3C1_SHIFT               (17U)
/*! I3C1 - I3C1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_I3C1(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_I3C1_MASK)

#define CLKCTL0_PSCCTL2_CRC0_MASK                (0x40000U)
#define CLKCTL0_PSCCTL2_CRC0_SHIFT               (18U)
/*! CRC0 - CRC0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_CRC0(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CRC0_SHIFT)) & CLKCTL0_PSCCTL2_CRC0_MASK)

#define CLKCTL0_PSCCTL2_WWDT0_MASK               (0x80000U)
#define CLKCTL0_PSCCTL2_WWDT0_SHIFT              (19U)
/*! WWDT0 - WWDT0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_WWDT0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_WWDT0_SHIFT)) & CLKCTL0_PSCCTL2_WWDT0_MASK)

#define CLKCTL0_PSCCTL2_WWDT1_MASK               (0x100000U)
#define CLKCTL0_PSCCTL2_WWDT1_SHIFT              (20U)
/*! WWDT1 - WWDT1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_WWDT1(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_WWDT1_SHIFT)) & CLKCTL0_PSCCTL2_WWDT1_MASK)

#define CLKCTL0_PSCCTL2_CTIMER0_MASK             (0x200000U)
#define CLKCTL0_PSCCTL2_CTIMER0_SHIFT            (21U)
/*! CTIMER0 - CTIMER0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_CTIMER0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CTIMER0_SHIFT)) & CLKCTL0_PSCCTL2_CTIMER0_MASK)

#define CLKCTL0_PSCCTL2_CTIMER1_MASK             (0x400000U)
#define CLKCTL0_PSCCTL2_CTIMER1_SHIFT            (22U)
/*! CTIMER1 - CTIMER1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_CTIMER1(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CTIMER1_SHIFT)) & CLKCTL0_PSCCTL2_CTIMER1_MASK)

#define CLKCTL0_PSCCTL2_CTIMER2_MASK             (0x800000U)
#define CLKCTL0_PSCCTL2_CTIMER2_SHIFT            (23U)
/*! CTIMER2 - CTIMER2 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_CTIMER2(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CTIMER2_SHIFT)) & CLKCTL0_PSCCTL2_CTIMER2_MASK)

#define CLKCTL0_PSCCTL2_CTIMER3_MASK             (0x1000000U)
#define CLKCTL0_PSCCTL2_CTIMER3_SHIFT            (24U)
/*! CTIMER3 - CTIMER3 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_CTIMER3(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CTIMER3_SHIFT)) & CLKCTL0_PSCCTL2_CTIMER3_MASK)

#define CLKCTL0_PSCCTL2_CTIMER4_MASK             (0x2000000U)
#define CLKCTL0_PSCCTL2_CTIMER4_SHIFT            (25U)
/*! CTIMER4 - CTIMER4 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_CTIMER4(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CTIMER4_SHIFT)) & CLKCTL0_PSCCTL2_CTIMER4_MASK)

#define CLKCTL0_PSCCTL2_MRT0_MASK                (0x4000000U)
#define CLKCTL0_PSCCTL2_MRT0_SHIFT               (26U)
/*! MRT0 - MRT0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_MRT0(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_MRT0_SHIFT)) & CLKCTL0_PSCCTL2_MRT0_MASK)

#define CLKCTL0_PSCCTL2_UTICK0_MASK              (0x8000000U)
#define CLKCTL0_PSCCTL2_UTICK0_SHIFT             (27U)
/*! UTICK0 - UTICK0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_UTICK0(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_UTICK0_SHIFT)) & CLKCTL0_PSCCTL2_UTICK0_MASK)

#define CLKCTL0_PSCCTL2_SEMA42_4_MASK            (0x40000000U)
#define CLKCTL0_PSCCTL2_SEMA42_4_SHIFT           (30U)
/*! SEMA42_4 - SEMA42_4 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SEMA42_4(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SEMA42_4_SHIFT)) & CLKCTL0_PSCCTL2_SEMA42_4_MASK)

#define CLKCTL0_PSCCTL2_MU4_MASK                 (0x80000000U)
#define CLKCTL0_PSCCTL2_MU4_SHIFT                (31U)
/*! MU4 - MU4 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_MU4(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_MU4_SHIFT)) & CLKCTL0_PSCCTL2_MU4_MASK)
/*! @} */

/*! @name PSCCTL3 - VDD2_COMP Peripheral Clock Control 3 */
/*! @{ */

#define CLKCTL0_PSCCTL3_PINT0_MASK               (0x20U)
#define CLKCTL0_PSCCTL3_PINT0_SHIFT              (5U)
/*! PINT0 - PINT0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_PINT0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_PINT0_SHIFT)) & CLKCTL0_PSCCTL3_PINT0_MASK)

#define CLKCTL0_PSCCTL3_FREQME0_MASK             (0x100U)
#define CLKCTL0_PSCCTL3_FREQME0_SHIFT            (8U)
/*! FREQME0 - FREQME0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_FREQME0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_FREQME0_SHIFT)) & CLKCTL0_PSCCTL3_FREQME0_MASK)

#define CLKCTL0_PSCCTL3_INPUTMUX0_MASK           (0x400U)
#define CLKCTL0_PSCCTL3_INPUTMUX0_SHIFT          (10U)
/*! INPUTMUX0 - INPUTMUX0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_INPUTMUX0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_INPUTMUX0_SHIFT)) & CLKCTL0_PSCCTL3_INPUTMUX0_MASK)

#define CLKCTL0_PSCCTL3_SAFO_SGI_MASK            (0x1000U)
#define CLKCTL0_PSCCTL3_SAFO_SGI_SHIFT           (12U)
/*! SAFO_SGI - SAFO_SGI Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SAFO_SGI(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SAFO_SGI_SHIFT)) & CLKCTL0_PSCCTL3_SAFO_SGI_MASK)

#define CLKCTL0_PSCCTL3_TRACE_MASK               (0x2000U)
#define CLKCTL0_PSCCTL3_TRACE_SHIFT              (13U)
/*! TRACE - TRACE_RT700 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_TRACE(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_TRACE_SHIFT)) & CLKCTL0_PSCCTL3_TRACE_MASK)

#define CLKCTL0_PSCCTL3_PRINCE0_MASK             (0x8000U)
#define CLKCTL0_PSCCTL3_PRINCE0_SHIFT            (15U)
/*! PRINCE0 - PRINCE0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_PRINCE0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_PRINCE0_SHIFT)) & CLKCTL0_PSCCTL3_PRINCE0_MASK)

#define CLKCTL0_PSCCTL3_PRINCE1_MASK             (0x10000U)
#define CLKCTL0_PSCCTL3_PRINCE1_SHIFT            (16U)
/*! PRINCE1 - PRINCE1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_PRINCE1(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_PRINCE1_SHIFT)) & CLKCTL0_PSCCTL3_PRINCE1_MASK)

#define CLKCTL0_PSCCTL3_XSPI1_PRINCE_XEX_MASK    (0x20000U)
#define CLKCTL0_PSCCTL3_XSPI1_PRINCE_XEX_SHIFT   (17U)
/*! XSPI1_PRINCE_XEX - XSPI1 PRINCE_XEX Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_XSPI1_PRINCE_XEX(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_XSPI1_PRINCE_XEX_SHIFT)) & CLKCTL0_PSCCTL3_XSPI1_PRINCE_XEX_MASK)

#define CLKCTL0_PSCCTL3_CMX_PERFMON0_MASK        (0x40000U)
#define CLKCTL0_PSCCTL3_CMX_PERFMON0_SHIFT       (18U)
/*! CMX_PERFMON0 - CMX_PERFMON0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_CMX_PERFMON0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CMX_PERFMON0_SHIFT)) & CLKCTL0_PSCCTL3_CMX_PERFMON0_MASK)

#define CLKCTL0_PSCCTL3_CMX_PERFMON1_MASK        (0x80000U)
#define CLKCTL0_PSCCTL3_CMX_PERFMON1_SHIFT       (19U)
/*! CMX_PERFMON1 - CMX_PERFMON1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_CMX_PERFMON1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CMX_PERFMON1_SHIFT)) & CLKCTL0_PSCCTL3_CMX_PERFMON1_MASK)
/*! @} */

/*! @name PSCCTL4 - VDD2_COMP Peripheral Clock Control 4 */
/*! @{ */

#define CLKCTL0_PSCCTL4_HIFI4_MASK               (0x1U)
#define CLKCTL0_PSCCTL4_HIFI4_SHIFT              (0U)
/*! HiFi4 - HiFi4 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL4_HIFI4(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL4_HIFI4_SHIFT)) & CLKCTL0_PSCCTL4_HIFI4_MASK)
/*! @} */

/*! @name PSCCTL5 - VDD2_COMP Peripheral Clock Control 5 */
/*! @{ */

#define CLKCTL0_PSCCTL5_NPU0_MASK                (0x1U)
#define CLKCTL0_PSCCTL5_NPU0_SHIFT               (0U)
/*! NPU0 - NPU0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_NPU0(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_NPU0_SHIFT)) & CLKCTL0_PSCCTL5_NPU0_MASK)

#define CLKCTL0_PSCCTL5_COMP_ACCESS_RAM_ARBITER1_MASK (0x4U)
#define CLKCTL0_PSCCTL5_COMP_ACCESS_RAM_ARBITER1_SHIFT (2U)
/*! COMP_ACCESS_RAM_ARBITER1 - VDD2_COMP Access RAM Arbiter1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_COMP_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_COMP_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL0_PSCCTL5_COMP_ACCESS_RAM_ARBITER1_MASK)

#define CLKCTL0_PSCCTL5_IOPCTL0_MASK             (0x8U)
#define CLKCTL0_PSCCTL5_IOPCTL0_SHIFT            (3U)
/*! IOPCTL0 - IOPCTL0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_IOPCTL0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_IOPCTL0_SHIFT)) & CLKCTL0_PSCCTL5_IOPCTL0_MASK)

#define CLKCTL0_PSCCTL5_HIFI4_ACCESS_RAM_ARBITER1_MASK (0x10U)
#define CLKCTL0_PSCCTL5_HIFI4_ACCESS_RAM_ARBITER1_SHIFT (4U)
/*! HiFi4_ACCESS_RAM_ARBITER1 - HiFi4 Access RAM Arbiter1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_HIFI4_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_HIFI4_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL0_PSCCTL5_HIFI4_ACCESS_RAM_ARBITER1_MASK)

#define CLKCTL0_PSCCTL5_MEDIA_ACCESS_RAM_ARBITER0_MASK (0x20U)
#define CLKCTL0_PSCCTL5_MEDIA_ACCESS_RAM_ARBITER0_SHIFT (5U)
/*! MEDIA_ACCESS_RAM_ARBITER0 - VDD2_Media Access RAM Arbiter 0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_MEDIA_ACCESS_RAM_ARBITER0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_MEDIA_ACCESS_RAM_ARBITER0_SHIFT)) & CLKCTL0_PSCCTL5_MEDIA_ACCESS_RAM_ARBITER0_MASK)
/*! @} */

/*! @name PSCCTL0_SET - VDD2_COMP Peripheral Clock Control 0 Set */
/*! @{ */

#define CLKCTL0_PSCCTL0_SET_CODE_CACHE_MASK      (0x2U)
#define CLKCTL0_PSCCTL0_SET_CODE_CACHE_SHIFT     (1U)
/*! CODE_CACHE - XCACHE1 (Code Cache) Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SET_CODE_CACHE(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_CODE_CACHE_SHIFT)) & CLKCTL0_PSCCTL0_SET_CODE_CACHE_MASK)

#define CLKCTL0_PSCCTL0_SET_SYSTEM_CACHE_MASK    (0x4U)
#define CLKCTL0_PSCCTL0_SET_SYSTEM_CACHE_SHIFT   (2U)
/*! SYSTEM_CACHE - XCACHE0 (System Cache) Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SET_SYSTEM_CACHE(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SYSTEM_CACHE_SHIFT)) & CLKCTL0_PSCCTL0_SET_SYSTEM_CACHE_MASK)

#define CLKCTL0_PSCCTL0_SET_VDD2_OTP0_MASK       (0x20U)
#define CLKCTL0_PSCCTL0_SET_VDD2_OTP0_SHIFT      (5U)
/*! VDD2_OTP0 - VDD2_OTP_CTRL0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SET_VDD2_OTP0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_VDD2_OTP0_SHIFT)) & CLKCTL0_PSCCTL0_SET_VDD2_OTP0_MASK)

#define CLKCTL0_PSCCTL0_SET_SLEEPCON0_MASK       (0x1000U)
#define CLKCTL0_PSCCTL0_SET_SLEEPCON0_SHIFT      (12U)
/*! SLEEPCON0 - SLEEPCON0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SET_SLEEPCON0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SLEEPCON0_SHIFT)) & CLKCTL0_PSCCTL0_SET_SLEEPCON0_MASK)

#define CLKCTL0_PSCCTL0_SET_SYSCON0_MASK         (0x2000U)
#define CLKCTL0_PSCCTL0_SET_SYSCON0_SHIFT        (13U)
/*! SYSCON0 - SYSCON0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SET_SYSCON0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SYSCON0_SHIFT)) & CLKCTL0_PSCCTL0_SET_SYSCON0_MASK)

#define CLKCTL0_PSCCTL0_SET_GLIKEY0_MASK         (0x4000U)
#define CLKCTL0_PSCCTL0_SET_GLIKEY0_SHIFT        (14U)
/*! GLIKEY0 - GLIKEY0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SET_GLIKEY0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_GLIKEY0_SHIFT)) & CLKCTL0_PSCCTL0_SET_GLIKEY0_MASK)

#define CLKCTL0_PSCCTL0_SET_GLIKEY3_MASK         (0x8000U)
#define CLKCTL0_PSCCTL0_SET_GLIKEY3_SHIFT        (15U)
/*! GLIKEY3 - GLIKEY3 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL0_SET_GLIKEY3(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_GLIKEY3_SHIFT)) & CLKCTL0_PSCCTL0_SET_GLIKEY3_MASK)
/*! @} */

/*! @name PSCCTL1_SET - VDD2_COMP Peripheral Clock Control 1 Set */
/*! @{ */

#define CLKCTL0_PSCCTL1_SET_TPIU_TRACE_CLKIN_MASK (0x4U)
#define CLKCTL0_PSCCTL1_SET_TPIU_TRACE_CLKIN_SHIFT (2U)
/*! TPIU_TRACE_CLKIN - TPIU_TRACE_CLKIN (TRACE_RT700) Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_TPIU_TRACE_CLKIN(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_TPIU_TRACE_CLKIN_SHIFT)) & CLKCTL0_PSCCTL1_SET_TPIU_TRACE_CLKIN_MASK)

#define CLKCTL0_PSCCTL1_SET_SWO_TRACECLKIN_MASK  (0x8U)
#define CLKCTL0_PSCCTL1_SET_SWO_TRACECLKIN_SHIFT (3U)
/*! SWO_TRACECLKIN - SWO TRACECLKIN (TRACE_RT700) Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_SWO_TRACECLKIN(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SWO_TRACECLKIN_SHIFT)) & CLKCTL0_PSCCTL1_SET_SWO_TRACECLKIN_MASK)

#define CLKCTL0_PSCCTL1_SET_TSCLK_MASK           (0x10U)
#define CLKCTL0_PSCCTL1_SET_TSCLK_SHIFT          (4U)
/*! TSCLK - TS (TRACE_RT700) Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_TSCLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_TSCLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_TSCLK_MASK)

#define CLKCTL0_PSCCTL1_SET_EDMA0_MASK           (0x20U)
#define CLKCTL0_PSCCTL1_SET_EDMA0_SHIFT          (5U)
/*! eDMA0 - eDMA0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_EDMA0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_EDMA0_SHIFT)) & CLKCTL0_PSCCTL1_SET_EDMA0_MASK)

#define CLKCTL0_PSCCTL1_SET_EDMA1_MASK           (0x40U)
#define CLKCTL0_PSCCTL1_SET_EDMA1_SHIFT          (6U)
/*! eDMA1 - eDMA1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_EDMA1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_EDMA1_SHIFT)) & CLKCTL0_PSCCTL1_SET_EDMA1_MASK)

#define CLKCTL0_PSCCTL1_SET_PKC_RAM_CTRL_MASK    (0x80U)
#define CLKCTL0_PSCCTL1_SET_PKC_RAM_CTRL_SHIFT   (7U)
/*! PKC_RAM_CTRl - RAM Control Clock of PKC
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_PKC_RAM_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_PKC_RAM_CTRL_SHIFT)) & CLKCTL0_PSCCTL1_SET_PKC_RAM_CTRL_MASK)

#define CLKCTL0_PSCCTL1_SET_PKC_MASK             (0x100U)
#define CLKCTL0_PSCCTL1_SET_PKC_SHIFT            (8U)
/*! PKC - PKC Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_PKC(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_PKC_SHIFT)) & CLKCTL0_PSCCTL1_SET_PKC_MASK)

#define CLKCTL0_PSCCTL1_SET_ROMCP_MASK           (0x200U)
#define CLKCTL0_PSCCTL1_SET_ROMCP_SHIFT          (9U)
/*! ROMCP - ROMCP Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_ROMCP(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_ROMCP_SHIFT)) & CLKCTL0_PSCCTL1_SET_ROMCP_MASK)

#define CLKCTL0_PSCCTL1_SET_XSPI0_MASK           (0x400U)
#define CLKCTL0_PSCCTL1_SET_XSPI0_SHIFT          (10U)
/*! XSPI0 - XSPI0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_XSPI0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI0_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI0_MASK)

#define CLKCTL0_PSCCTL1_SET_XSPI1_MASK           (0x800U)
#define CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT          (11U)
/*! XSPI1 - XSPI1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_XSPI1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI1_MASK)

#define CLKCTL0_PSCCTL1_SET_CACHE64_0_MASK       (0x1000U)
#define CLKCTL0_PSCCTL1_SET_CACHE64_0_SHIFT      (12U)
/*! CACHE64_0 - CACHE64_0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_CACHE64_0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_CACHE64_0_SHIFT)) & CLKCTL0_PSCCTL1_SET_CACHE64_0_MASK)

#define CLKCTL0_PSCCTL1_SET_CACHE64_1_MASK       (0x2000U)
#define CLKCTL0_PSCCTL1_SET_CACHE64_1_SHIFT      (13U)
/*! CACHE64_1 - CACHE64_1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_CACHE64_1(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_CACHE64_1_SHIFT)) & CLKCTL0_PSCCTL1_SET_CACHE64_1_MASK)

#define CLKCTL0_PSCCTL1_SET_QK_SUBSYS_MASK       (0x4000U)
#define CLKCTL0_PSCCTL1_SET_QK_SUBSYS_SHIFT      (14U)
/*! QK_SUBSYS - QK_SUBSYS (PUF_CTRL) Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_QK_SUBSYS(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_QK_SUBSYS_SHIFT)) & CLKCTL0_PSCCTL1_SET_QK_SUBSYS_MASK)

#define CLKCTL0_PSCCTL1_SET_MMU0_MASK            (0x10000U)
#define CLKCTL0_PSCCTL1_SET_MMU0_SHIFT           (16U)
/*! MMU0 - MMU0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_MMU0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_MMU0_SHIFT)) & CLKCTL0_PSCCTL1_SET_MMU0_MASK)

#define CLKCTL0_PSCCTL1_SET_MMU1_MASK            (0x20000U)
#define CLKCTL0_PSCCTL1_SET_MMU1_SHIFT           (17U)
/*! MMU1 - MMU1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_MMU1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_MMU1_SHIFT)) & CLKCTL0_PSCCTL1_SET_MMU1_MASK)

#define CLKCTL0_PSCCTL1_SET_GPIO0_MASK           (0x40000U)
#define CLKCTL0_PSCCTL1_SET_GPIO0_SHIFT          (18U)
/*! GPIO0 - GPIO0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_GPIO0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GPIO0_SHIFT)) & CLKCTL0_PSCCTL1_SET_GPIO0_MASK)

#define CLKCTL0_PSCCTL1_SET_GPIO1_MASK           (0x80000U)
#define CLKCTL0_PSCCTL1_SET_GPIO1_SHIFT          (19U)
/*! GPIO1 - GPIO1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_GPIO1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GPIO1_SHIFT)) & CLKCTL0_PSCCTL1_SET_GPIO1_MASK)

#define CLKCTL0_PSCCTL1_SET_GPIO2_MASK           (0x100000U)
#define CLKCTL0_PSCCTL1_SET_GPIO2_SHIFT          (20U)
/*! GPIO2 - GPIO2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_GPIO2(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GPIO2_SHIFT)) & CLKCTL0_PSCCTL1_SET_GPIO2_MASK)

#define CLKCTL0_PSCCTL1_SET_GPIO3_MASK           (0x200000U)
#define CLKCTL0_PSCCTL1_SET_GPIO3_SHIFT          (21U)
/*! GPIO3 - GPIO3 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_GPIO3(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GPIO3_SHIFT)) & CLKCTL0_PSCCTL1_SET_GPIO3_MASK)

#define CLKCTL0_PSCCTL1_SET_GPIO4_MASK           (0x400000U)
#define CLKCTL0_PSCCTL1_SET_GPIO4_SHIFT          (22U)
/*! GPIO4 - GPIO4 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_GPIO4(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GPIO4_SHIFT)) & CLKCTL0_PSCCTL1_SET_GPIO4_MASK)

#define CLKCTL0_PSCCTL1_SET_GPIO5_MASK           (0x800000U)
#define CLKCTL0_PSCCTL1_SET_GPIO5_SHIFT          (23U)
/*! GPIO5 - GPIO5 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_GPIO5(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GPIO5_SHIFT)) & CLKCTL0_PSCCTL1_SET_GPIO5_MASK)

#define CLKCTL0_PSCCTL1_SET_GPIO6_MASK           (0x1000000U)
#define CLKCTL0_PSCCTL1_SET_GPIO6_SHIFT          (24U)
/*! GPIO6 - GPIO6 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_GPIO6(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GPIO6_SHIFT)) & CLKCTL0_PSCCTL1_SET_GPIO6_MASK)

#define CLKCTL0_PSCCTL1_SET_GPIO7_MASK           (0x2000000U)
#define CLKCTL0_PSCCTL1_SET_GPIO7_SHIFT          (25U)
/*! GPIO7 - GPIO7 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_GPIO7(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GPIO7_SHIFT)) & CLKCTL0_PSCCTL1_SET_GPIO7_MASK)

#define CLKCTL0_PSCCTL1_SET_SCT0_MASK            (0x4000000U)
#define CLKCTL0_PSCCTL1_SET_SCT0_SHIFT           (26U)
/*! SCT0 - SCT0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_SCT0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SCT0_SHIFT)) & CLKCTL0_PSCCTL1_SET_SCT0_MASK)

#define CLKCTL0_PSCCTL1_SET_CDOG0_MASK           (0x8000000U)
#define CLKCTL0_PSCCTL1_SET_CDOG0_SHIFT          (27U)
/*! CDOG0 - CDOG0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_CDOG0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_CDOG0_SHIFT)) & CLKCTL0_PSCCTL1_SET_CDOG0_MASK)

#define CLKCTL0_PSCCTL1_SET_CDOG1_MASK           (0x10000000U)
#define CLKCTL0_PSCCTL1_SET_CDOG1_SHIFT          (28U)
/*! CDOG1 - CDOG1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_CDOG1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_CDOG1_SHIFT)) & CLKCTL0_PSCCTL1_SET_CDOG1_MASK)

#define CLKCTL0_PSCCTL1_SET_CDOG2_MASK           (0x20000000U)
#define CLKCTL0_PSCCTL1_SET_CDOG2_SHIFT          (29U)
/*! CDOG2 - CDOG2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_CDOG2(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_SET_CDOG2_MASK)

#define CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM0_MASK    (0x40000000U)
#define CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM0_SHIFT   (30U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM0_SHIFT)) & CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM0_MASK)

#define CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM1_MASK    (0x80000000U)
#define CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM1_SHIFT   (31U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM1_SHIFT)) & CLKCTL0_PSCCTL1_SET_LP_FLEXCOMM1_MASK)
/*! @} */

/*! @name PSCCTL2_SET - VDD2_COMP Peripheral Clock Control 2 Set */
/*! @{ */

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM2_MASK    (0x1U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM2_SHIFT   (0U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM2(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM2_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM2_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM3_MASK    (0x2U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM3_SHIFT   (1U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM3(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM3_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM3_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM4_MASK    (0x4U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM4_SHIFT   (2U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM4(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM4_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM4_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM5_MASK    (0x8U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM5_SHIFT   (3U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM5(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM5_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM5_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM6_MASK    (0x10U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM6_SHIFT   (4U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM6(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM6_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM6_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM7_MASK    (0x20U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM7_SHIFT   (5U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM7(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM7_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM7_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM8_MASK    (0x40U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM8_SHIFT   (6U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM8(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM8_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM8_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM9_MASK    (0x80U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM9_SHIFT   (7U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM9(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM9_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM9_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM10_MASK   (0x100U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM10_SHIFT  (8U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM10(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM10_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM10_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM11_MASK   (0x200U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM11_SHIFT  (9U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM11(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM11_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM11_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM12_MASK   (0x400U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM12_SHIFT  (10U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM12(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM12_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM12_MASK)

#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM13_MASK   (0x800U)
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM13_SHIFT  (11U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM13(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM13_SHIFT)) & CLKCTL0_PSCCTL2_SET_LP_FLEXCOMM13_MASK)

#define CLKCTL0_PSCCTL2_SET_SAI0_MASK            (0x2000U)
#define CLKCTL0_PSCCTL2_SET_SAI0_SHIFT           (13U)
/*! SAI0 - SAI0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_SAI0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_SAI0_SHIFT)) & CLKCTL0_PSCCTL2_SET_SAI0_MASK)

#define CLKCTL0_PSCCTL2_SET_SAI1_MASK            (0x4000U)
#define CLKCTL0_PSCCTL2_SET_SAI1_SHIFT           (14U)
/*! SAI1 - SAI1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_SAI1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_SAI1_SHIFT)) & CLKCTL0_PSCCTL2_SET_SAI1_MASK)

#define CLKCTL0_PSCCTL2_SET_SAI2_MASK            (0x8000U)
#define CLKCTL0_PSCCTL2_SET_SAI2_SHIFT           (15U)
/*! SAI2 - SAI2 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_SAI2(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_SET_SAI2_MASK)

#define CLKCTL0_PSCCTL2_SET_I3C0_MASK            (0x10000U)
#define CLKCTL0_PSCCTL2_SET_I3C0_SHIFT           (16U)
/*! I3C0 - I3C0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_I3C0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C0_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C0_MASK)

#define CLKCTL0_PSCCTL2_SET_I3C1_MASK            (0x20000U)
#define CLKCTL0_PSCCTL2_SET_I3C1_SHIFT           (17U)
/*! I3C1 - I3C1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_I3C1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C1_MASK)

#define CLKCTL0_PSCCTL2_SET_CRC0_MASK            (0x40000U)
#define CLKCTL0_PSCCTL2_SET_CRC0_SHIFT           (18U)
/*! CRC0 - CRC0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_CRC0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_CRC0_SHIFT)) & CLKCTL0_PSCCTL2_SET_CRC0_MASK)

#define CLKCTL0_PSCCTL2_SET_WWDT0_MASK           (0x80000U)
#define CLKCTL0_PSCCTL2_SET_WWDT0_SHIFT          (19U)
/*! WWDT0 - WWDT0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_WWDT0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_WWDT0_SHIFT)) & CLKCTL0_PSCCTL2_SET_WWDT0_MASK)

#define CLKCTL0_PSCCTL2_SET_WWDT1_MASK           (0x100000U)
#define CLKCTL0_PSCCTL2_SET_WWDT1_SHIFT          (20U)
/*! WWDT1 - WWDT1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_WWDT1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_WWDT1_SHIFT)) & CLKCTL0_PSCCTL2_SET_WWDT1_MASK)

#define CLKCTL0_PSCCTL2_SET_CTIMER0_MASK         (0x200000U)
#define CLKCTL0_PSCCTL2_SET_CTIMER0_SHIFT        (21U)
/*! CTIMER0 - CTIMER0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_CTIMER0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_CTIMER0_SHIFT)) & CLKCTL0_PSCCTL2_SET_CTIMER0_MASK)

#define CLKCTL0_PSCCTL2_SET_CTIMER1_MASK         (0x400000U)
#define CLKCTL0_PSCCTL2_SET_CTIMER1_SHIFT        (22U)
/*! CTIMER1 - CTIMER1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_CTIMER1(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_CTIMER1_SHIFT)) & CLKCTL0_PSCCTL2_SET_CTIMER1_MASK)

#define CLKCTL0_PSCCTL2_SET_CTIMER2_MASK         (0x800000U)
#define CLKCTL0_PSCCTL2_SET_CTIMER2_SHIFT        (23U)
/*! CTIMER2 - CTIMER2 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_CTIMER2(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_CTIMER2_SHIFT)) & CLKCTL0_PSCCTL2_SET_CTIMER2_MASK)

#define CLKCTL0_PSCCTL2_SET_CTIMER3_MASK         (0x1000000U)
#define CLKCTL0_PSCCTL2_SET_CTIMER3_SHIFT        (24U)
/*! CTIMER3 - CTIMER3 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_CTIMER3(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_CTIMER3_SHIFT)) & CLKCTL0_PSCCTL2_SET_CTIMER3_MASK)

#define CLKCTL0_PSCCTL2_SET_CTIMER4_MASK         (0x2000000U)
#define CLKCTL0_PSCCTL2_SET_CTIMER4_SHIFT        (25U)
/*! CTIMER4 - CTIMER4 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_CTIMER4(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_CTIMER4_SHIFT)) & CLKCTL0_PSCCTL2_SET_CTIMER4_MASK)

#define CLKCTL0_PSCCTL2_SET_MRT0_MASK            (0x4000000U)
#define CLKCTL0_PSCCTL2_SET_MRT0_SHIFT           (26U)
/*! MRT0 - MRT0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_MRT0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_MRT0_SHIFT)) & CLKCTL0_PSCCTL2_SET_MRT0_MASK)

#define CLKCTL0_PSCCTL2_SET_UTICK0_MASK          (0x8000000U)
#define CLKCTL0_PSCCTL2_SET_UTICK0_SHIFT         (27U)
/*! UTICK0 - UTICK0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_UTICK0(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_UTICK0_SHIFT)) & CLKCTL0_PSCCTL2_SET_UTICK0_MASK)

#define CLKCTL0_PSCCTL2_SET_SEMA42_4_MASK        (0x40000000U)
#define CLKCTL0_PSCCTL2_SET_SEMA42_4_SHIFT       (30U)
/*! SEMA42_4 - SEMA42_4 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_SEMA42_4(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_SEMA42_4_SHIFT)) & CLKCTL0_PSCCTL2_SET_SEMA42_4_MASK)

#define CLKCTL0_PSCCTL2_SET_MU4_MASK             (0x80000000U)
#define CLKCTL0_PSCCTL2_SET_MU4_SHIFT            (31U)
/*! MU4 - MU4 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL2_SET_MU4(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_MU4_SHIFT)) & CLKCTL0_PSCCTL2_SET_MU4_MASK)
/*! @} */

/*! @name PSCCTL3_SET - VDD2_COMP Peripheral Clock Control 3 Set */
/*! @{ */

#define CLKCTL0_PSCCTL3_SET_PINT0_MASK           (0x20U)
#define CLKCTL0_PSCCTL3_SET_PINT0_SHIFT          (5U)
/*! PINT0 - PINT0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_PINT0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_PINT0_SHIFT)) & CLKCTL0_PSCCTL3_SET_PINT0_MASK)

#define CLKCTL0_PSCCTL3_SET_FREQME0_MASK         (0x100U)
#define CLKCTL0_PSCCTL3_SET_FREQME0_SHIFT        (8U)
/*! FREQME0 - FREQME0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_FREQME0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_FREQME0_SHIFT)) & CLKCTL0_PSCCTL3_SET_FREQME0_MASK)

#define CLKCTL0_PSCCTL3_SET_INPUTMUX0_MASK       (0x400U)
#define CLKCTL0_PSCCTL3_SET_INPUTMUX0_SHIFT      (10U)
/*! INPUTMUX0 - INPUTMUX0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_INPUTMUX0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_INPUTMUX0_SHIFT)) & CLKCTL0_PSCCTL3_SET_INPUTMUX0_MASK)

#define CLKCTL0_PSCCTL3_SET_SAFO_SGI_MASK        (0x1000U)
#define CLKCTL0_PSCCTL3_SET_SAFO_SGI_SHIFT       (12U)
/*! SAFO_SGI - SAFO_SGI Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_SAFO_SGI(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_SAFO_SGI_SHIFT)) & CLKCTL0_PSCCTL3_SET_SAFO_SGI_MASK)

#define CLKCTL0_PSCCTL3_SET_TRACE_MASK           (0x2000U)
#define CLKCTL0_PSCCTL3_SET_TRACE_SHIFT          (13U)
/*! TRACE - TRACE_RT700 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_TRACE(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_TRACE_SHIFT)) & CLKCTL0_PSCCTL3_SET_TRACE_MASK)

#define CLKCTL0_PSCCTL3_SET_PRINCE0_MASK         (0x8000U)
#define CLKCTL0_PSCCTL3_SET_PRINCE0_SHIFT        (15U)
/*! PRINCE0 - PRINCE0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_PRINCE0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_PRINCE0_SHIFT)) & CLKCTL0_PSCCTL3_SET_PRINCE0_MASK)

#define CLKCTL0_PSCCTL3_SET_PRINCE1_MASK         (0x10000U)
#define CLKCTL0_PSCCTL3_SET_PRINCE1_SHIFT        (16U)
/*! PRINCE1 - PRINCE1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_PRINCE1(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_PRINCE1_SHIFT)) & CLKCTL0_PSCCTL3_SET_PRINCE1_MASK)

#define CLKCTL0_PSCCTL3_SET_XSPI1_PRINCE_XEX_MASK (0x20000U)
#define CLKCTL0_PSCCTL3_SET_XSPI1_PRINCE_XEX_SHIFT (17U)
/*! XSPI1_PRINCE_XEX - XSPI1_PRINCE XEX Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_XSPI1_PRINCE_XEX(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_XSPI1_PRINCE_XEX_SHIFT)) & CLKCTL0_PSCCTL3_SET_XSPI1_PRINCE_XEX_MASK)

#define CLKCTL0_PSCCTL3_SET_CMX_PERFMON0_MASK    (0x40000U)
#define CLKCTL0_PSCCTL3_SET_CMX_PERFMON0_SHIFT   (18U)
/*! CMX_PERFMON0 - CMX_PERFMON0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_CMX_PERFMON0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_CMX_PERFMON0_SHIFT)) & CLKCTL0_PSCCTL3_SET_CMX_PERFMON0_MASK)

#define CLKCTL0_PSCCTL3_SET_CMX_PERFMON1_MASK    (0x80000U)
#define CLKCTL0_PSCCTL3_SET_CMX_PERFMON1_SHIFT   (19U)
/*! CMX_PERFMON1 - CMX_PERFMON1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL3_SET_CMX_PERFMON1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_CMX_PERFMON1_SHIFT)) & CLKCTL0_PSCCTL3_SET_CMX_PERFMON1_MASK)
/*! @} */

/*! @name PSCCTL4_SET - VDD2_COMP Peripheral Clock Control 4 Set */
/*! @{ */

#define CLKCTL0_PSCCTL4_SET_HIFI4_MASK           (0x1U)
#define CLKCTL0_PSCCTL4_SET_HIFI4_SHIFT          (0U)
/*! HiFi4 - HiFi4 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL4_SET_HIFI4(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL4_SET_HIFI4_SHIFT)) & CLKCTL0_PSCCTL4_SET_HIFI4_MASK)
/*! @} */

/*! @name PSCCTL5_SET - VDD2_COMP Peripheral Clock Control 5 Set */
/*! @{ */

#define CLKCTL0_PSCCTL5_SET_NPU0_MASK            (0x1U)
#define CLKCTL0_PSCCTL5_SET_NPU0_SHIFT           (0U)
/*! NPU0 - NPU0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_SET_NPU0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_SET_NPU0_SHIFT)) & CLKCTL0_PSCCTL5_SET_NPU0_MASK)

#define CLKCTL0_PSCCTL5_SET_COMP_ACCESS_RAM_ARBITER1_MASK (0x4U)
#define CLKCTL0_PSCCTL5_SET_COMP_ACCESS_RAM_ARBITER1_SHIFT (2U)
/*! COMP_ACCESS_RAM_ARBITER1 - VDD2_COMP Access RAM Arbiter1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_SET_COMP_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_SET_COMP_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL0_PSCCTL5_SET_COMP_ACCESS_RAM_ARBITER1_MASK)

#define CLKCTL0_PSCCTL5_SET_IOPCTL0_MASK         (0x8U)
#define CLKCTL0_PSCCTL5_SET_IOPCTL0_SHIFT        (3U)
/*! IOPCTL0 - IOPCTL0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_SET_IOPCTL0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_SET_IOPCTL0_SHIFT)) & CLKCTL0_PSCCTL5_SET_IOPCTL0_MASK)

#define CLKCTL0_PSCCTL5_SET_HIFI4_ACCESS_RAM_ARBITER1_MASK (0x10U)
#define CLKCTL0_PSCCTL5_SET_HIFI4_ACCESS_RAM_ARBITER1_SHIFT (4U)
/*! HiFi4_ACCESS_RAM_ARBITER1 - HiFi4 Access RAM Arbiter1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_SET_HIFI4_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_SET_HIFI4_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL0_PSCCTL5_SET_HIFI4_ACCESS_RAM_ARBITER1_MASK)

#define CLKCTL0_PSCCTL5_SET_MEDIA_ACCESS_RAM_ARBITER0_MASK (0x20U)
#define CLKCTL0_PSCCTL5_SET_MEDIA_ACCESS_RAM_ARBITER0_SHIFT (5U)
/*! MEDIA_ACCESS_RAM_ARBITER0 - VDD2_Media Access RAM Arbiter 0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL0_PSCCTL5_SET_MEDIA_ACCESS_RAM_ARBITER0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_SET_MEDIA_ACCESS_RAM_ARBITER0_SHIFT)) & CLKCTL0_PSCCTL5_SET_MEDIA_ACCESS_RAM_ARBITER0_MASK)
/*! @} */

/*! @name PSCCTL0_CLR - VDD2_COMP Peripheral Clock Control 0 Clear */
/*! @{ */

#define CLKCTL0_PSCCTL0_CLR_CODE_CACHE_MASK      (0x2U)
#define CLKCTL0_PSCCTL0_CLR_CODE_CACHE_SHIFT     (1U)
/*! CODE_CACHE - CODE CACHE (XCACHE1) Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL0_CLR_CODE_CACHE(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_CODE_CACHE_SHIFT)) & CLKCTL0_PSCCTL0_CLR_CODE_CACHE_MASK)

#define CLKCTL0_PSCCTL0_CLR_SYSTEM_CACHE_MASK    (0x4U)
#define CLKCTL0_PSCCTL0_CLR_SYSTEM_CACHE_SHIFT   (2U)
/*! SYSTEM_CACHE - SYSTEM CACHE (XCACHE0)Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL0_CLR_SYSTEM_CACHE(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SYSTEM_CACHE_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SYSTEM_CACHE_MASK)

#define CLKCTL0_PSCCTL0_CLR_VDD2_OTP0_MASK       (0x20U)
#define CLKCTL0_PSCCTL0_CLR_VDD2_OTP0_SHIFT      (5U)
/*! VDD2_OTP0 - VDD2_OTP_CTRL0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL0_CLR_VDD2_OTP0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_VDD2_OTP0_SHIFT)) & CLKCTL0_PSCCTL0_CLR_VDD2_OTP0_MASK)

#define CLKCTL0_PSCCTL0_CLR_SLEEPCON0_MASK       (0x1000U)
#define CLKCTL0_PSCCTL0_CLR_SLEEPCON0_SHIFT      (12U)
/*! SLEEPCON0 - SLEEPCON0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL0_CLR_SLEEPCON0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SLEEPCON0_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SLEEPCON0_MASK)

#define CLKCTL0_PSCCTL0_CLR_SYSCON0_MASK         (0x2000U)
#define CLKCTL0_PSCCTL0_CLR_SYSCON0_SHIFT        (13U)
/*! SYSCON0 - SYSCON0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL0_CLR_SYSCON0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SYSCON0_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SYSCON0_MASK)

#define CLKCTL0_PSCCTL0_CLR_GLIKEY0_MASK         (0x4000U)
#define CLKCTL0_PSCCTL0_CLR_GLIKEY0_SHIFT        (14U)
/*! GLIKEY0 - GLIKEY0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL0_CLR_GLIKEY0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_GLIKEY0_SHIFT)) & CLKCTL0_PSCCTL0_CLR_GLIKEY0_MASK)

#define CLKCTL0_PSCCTL0_CLR_GLIKEY3_MASK         (0x8000U)
#define CLKCTL0_PSCCTL0_CLR_GLIKEY3_SHIFT        (15U)
/*! GLIKEY3 - GLIKEY3 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL0_CLR_GLIKEY3(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_GLIKEY3_SHIFT)) & CLKCTL0_PSCCTL0_CLR_GLIKEY3_MASK)
/*! @} */

/*! @name PSCCTL1_CLR - VDD2_COMP Peripheral Clock Control 1 Clear */
/*! @{ */

#define CLKCTL0_PSCCTL1_CLR_TPIU_TRACE_CLKIN_MASK (0x4U)
#define CLKCTL0_PSCCTL1_CLR_TPIU_TRACE_CLKIN_SHIFT (2U)
/*! TPIU_TRACE_CLKIN - TPIU TRACE_CLKIN (TRACE_RT700)Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_TPIU_TRACE_CLKIN(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_TPIU_TRACE_CLKIN_SHIFT)) & CLKCTL0_PSCCTL1_CLR_TPIU_TRACE_CLKIN_MASK)

#define CLKCTL0_PSCCTL1_CLR_SWO_TRACECLKIN_MASK  (0x8U)
#define CLKCTL0_PSCCTL1_CLR_SWO_TRACECLKIN_SHIFT (3U)
/*! SWO_TRACECLKIN - SWO TRACECLKIN (TRACE_RT700) Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_SWO_TRACECLKIN(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SWO_TRACECLKIN_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SWO_TRACECLKIN_MASK)

#define CLKCTL0_PSCCTL1_CLR_TSCLK_MASK           (0x10U)
#define CLKCTL0_PSCCTL1_CLR_TSCLK_SHIFT          (4U)
/*! TSCLK - TS (TRACE_RT700) Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_TSCLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_TSCLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_TSCLK_MASK)

#define CLKCTL0_PSCCTL1_CLR_EDMA0_MASK           (0x20U)
#define CLKCTL0_PSCCTL1_CLR_EDMA0_SHIFT          (5U)
/*! eDMA0 - eDMA0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_EDMA0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_EDMA0_SHIFT)) & CLKCTL0_PSCCTL1_CLR_EDMA0_MASK)

#define CLKCTL0_PSCCTL1_CLR_EDMA1_MASK           (0x40U)
#define CLKCTL0_PSCCTL1_CLR_EDMA1_SHIFT          (6U)
/*! eDMA1 - eDMA1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_EDMA1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_EDMA1_SHIFT)) & CLKCTL0_PSCCTL1_CLR_EDMA1_MASK)

#define CLKCTL0_PSCCTL1_CLR_PKC_RAM_CTRL_MASK    (0x80U)
#define CLKCTL0_PSCCTL1_CLR_PKC_RAM_CTRL_SHIFT   (7U)
/*! PKC_RAM_CTRl - RAM CTRl Clock of PKC
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_PKC_RAM_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_PKC_RAM_CTRL_SHIFT)) & CLKCTL0_PSCCTL1_CLR_PKC_RAM_CTRL_MASK)

#define CLKCTL0_PSCCTL1_CLR_PKC_MASK             (0x100U)
#define CLKCTL0_PSCCTL1_CLR_PKC_SHIFT            (8U)
/*! PKC - PKC Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_PKC(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_PKC_SHIFT)) & CLKCTL0_PSCCTL1_CLR_PKC_MASK)

#define CLKCTL0_PSCCTL1_CLR_ROMCP_MASK           (0x200U)
#define CLKCTL0_PSCCTL1_CLR_ROMCP_SHIFT          (9U)
/*! ROMCP - ROMCP Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_ROMCP(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_ROMCP_SHIFT)) & CLKCTL0_PSCCTL1_CLR_ROMCP_MASK)

#define CLKCTL0_PSCCTL1_CLR_XSPI0_MASK           (0x400U)
#define CLKCTL0_PSCCTL1_CLR_XSPI0_SHIFT          (10U)
/*! XSPI0 - XSPI0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_XSPI0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_XSPI0_SHIFT)) & CLKCTL0_PSCCTL1_CLR_XSPI0_MASK)

#define CLKCTL0_PSCCTL1_CLR_XSPI1_MASK           (0x800U)
#define CLKCTL0_PSCCTL1_CLR_XSPI1_SHIFT          (11U)
/*! XSPI1 - XSPI1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_XSPI1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_CLR_XSPI1_MASK)

#define CLKCTL0_PSCCTL1_CLR_CACHE64_0_MASK       (0x1000U)
#define CLKCTL0_PSCCTL1_CLR_CACHE64_0_SHIFT      (12U)
/*! CACHE64_0 - CACHE64_0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_CACHE64_0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_CACHE64_0_SHIFT)) & CLKCTL0_PSCCTL1_CLR_CACHE64_0_MASK)

#define CLKCTL0_PSCCTL1_CLR_CACHE64_1_MASK       (0x2000U)
#define CLKCTL0_PSCCTL1_CLR_CACHE64_1_SHIFT      (13U)
/*! CACHE64_1 - CACHE64_1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_CACHE64_1(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_CACHE64_1_SHIFT)) & CLKCTL0_PSCCTL1_CLR_CACHE64_1_MASK)

#define CLKCTL0_PSCCTL1_CLR_QK_SUBSYS_MASK       (0x4000U)
#define CLKCTL0_PSCCTL1_CLR_QK_SUBSYS_SHIFT      (14U)
/*! QK_SUBSYS - QK_SUBSYS (PUF_CTRL) Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_QK_SUBSYS(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_QK_SUBSYS_SHIFT)) & CLKCTL0_PSCCTL1_CLR_QK_SUBSYS_MASK)

#define CLKCTL0_PSCCTL1_CLR_MMU0_MASK            (0x10000U)
#define CLKCTL0_PSCCTL1_CLR_MMU0_SHIFT           (16U)
/*! MMU0 - MMU0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_MMU0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_MMU0_SHIFT)) & CLKCTL0_PSCCTL1_CLR_MMU0_MASK)

#define CLKCTL0_PSCCTL1_CLR_MMU1_MASK            (0x20000U)
#define CLKCTL0_PSCCTL1_CLR_MMU1_SHIFT           (17U)
/*! MMU1 - MMU1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_MMU1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_MMU1_SHIFT)) & CLKCTL0_PSCCTL1_CLR_MMU1_MASK)

#define CLKCTL0_PSCCTL1_CLR_GPIO0_MASK           (0x40000U)
#define CLKCTL0_PSCCTL1_CLR_GPIO0_SHIFT          (18U)
/*! GPIO0 - GPIO0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_GPIO0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GPIO0_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GPIO0_MASK)

#define CLKCTL0_PSCCTL1_CLR_GPIO1_MASK           (0x80000U)
#define CLKCTL0_PSCCTL1_CLR_GPIO1_SHIFT          (19U)
/*! GPIO1 - GPIO1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_GPIO1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GPIO1_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GPIO1_MASK)

#define CLKCTL0_PSCCTL1_CLR_GPIO2_MASK           (0x100000U)
#define CLKCTL0_PSCCTL1_CLR_GPIO2_SHIFT          (20U)
/*! GPIO2 - GPIO2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_GPIO2(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GPIO2_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GPIO2_MASK)

#define CLKCTL0_PSCCTL1_CLR_GPIO3_MASK           (0x200000U)
#define CLKCTL0_PSCCTL1_CLR_GPIO3_SHIFT          (21U)
/*! GPIO3 - GPIO3 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_GPIO3(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GPIO3_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GPIO3_MASK)

#define CLKCTL0_PSCCTL1_CLR_GPIO4_MASK           (0x400000U)
#define CLKCTL0_PSCCTL1_CLR_GPIO4_SHIFT          (22U)
/*! GPIO4 - GPIO4 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_GPIO4(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GPIO4_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GPIO4_MASK)

#define CLKCTL0_PSCCTL1_CLR_GPIO5_MASK           (0x800000U)
#define CLKCTL0_PSCCTL1_CLR_GPIO5_SHIFT          (23U)
/*! GPIO5 - GPIO5 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_GPIO5(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GPIO5_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GPIO5_MASK)

#define CLKCTL0_PSCCTL1_CLR_GPIO6_MASK           (0x1000000U)
#define CLKCTL0_PSCCTL1_CLR_GPIO6_SHIFT          (24U)
/*! GPIO6 - GPIO6 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_GPIO6(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GPIO6_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GPIO6_MASK)

#define CLKCTL0_PSCCTL1_CLR_GPIO7_MASK           (0x2000000U)
#define CLKCTL0_PSCCTL1_CLR_GPIO7_SHIFT          (25U)
/*! GPIO7 - GPIO7 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_GPIO7(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GPIO7_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GPIO7_MASK)

#define CLKCTL0_PSCCTL1_CLR_SCT0_MASK            (0x4000000U)
#define CLKCTL0_PSCCTL1_CLR_SCT0_SHIFT           (26U)
/*! SCT0 - SCT0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_SCT0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SCT0_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SCT0_MASK)

#define CLKCTL0_PSCCTL1_CLR_CDOG0_MASK           (0x8000000U)
#define CLKCTL0_PSCCTL1_CLR_CDOG0_SHIFT          (27U)
/*! CDOG0 - CDOG0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_CDOG0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_CDOG0_SHIFT)) & CLKCTL0_PSCCTL1_CLR_CDOG0_MASK)

#define CLKCTL0_PSCCTL1_CLR_CDOG1_MASK           (0x10000000U)
#define CLKCTL0_PSCCTL1_CLR_CDOG1_SHIFT          (28U)
/*! CDOG1 - CDOG1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_CDOG1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_CDOG1_SHIFT)) & CLKCTL0_PSCCTL1_CLR_CDOG1_MASK)

#define CLKCTL0_PSCCTL1_CLR_CDOG2_MASK           (0x20000000U)
#define CLKCTL0_PSCCTL1_CLR_CDOG2_SHIFT          (29U)
/*! CDOG2 - CDOG2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_CDOG2(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CLR_CDOG2_MASK)

#define CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM0_MASK    (0x40000000U)
#define CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM0_SHIFT   (30U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM0_SHIFT)) & CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM0_MASK)

#define CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM1_MASK    (0x80000000U)
#define CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM1_SHIFT   (31U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM1_SHIFT)) & CLKCTL0_PSCCTL1_CLR_LP_FLEXCOMM1_MASK)
/*! @} */

/*! @name PSCCTL2_CLR - VDD2_COMP Peripheral Clock Control 2 Clear */
/*! @{ */

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM2_MASK    (0x1U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM2_SHIFT   (0U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM2(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM2_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM3_MASK    (0x2U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM3_SHIFT   (1U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM3(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM3_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM3_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM4_MASK    (0x4U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM4_SHIFT   (2U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM4(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM4_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM4_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM5_MASK    (0x8U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM5_SHIFT   (3U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM5(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM5_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM5_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM6_MASK    (0x10U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM6_SHIFT   (4U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM6(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM6_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM6_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM7_MASK    (0x20U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM7_SHIFT   (5U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM7(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM7_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM7_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM8_MASK    (0x40U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM8_SHIFT   (6U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM8(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM8_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM8_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM9_MASK    (0x80U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM9_SHIFT   (7U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM9(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM9_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM9_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM10_MASK   (0x100U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM10_SHIFT  (8U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM10(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM10_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM10_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM11_MASK   (0x200U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM11_SHIFT  (9U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM11(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM11_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM11_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM12_MASK   (0x400U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM12_SHIFT  (10U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM12(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM12_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM12_MASK)

#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM13_MASK   (0x800U)
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM13_SHIFT  (11U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM13(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM13_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LP_FLEXCOMM13_MASK)

#define CLKCTL0_PSCCTL2_CLR_SAI0_MASK            (0x2000U)
#define CLKCTL0_PSCCTL2_CLR_SAI0_SHIFT           (13U)
/*! SAI0 - SAI0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_SAI0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI0_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI0_MASK)

#define CLKCTL0_PSCCTL2_CLR_SAI1_MASK            (0x4000U)
#define CLKCTL0_PSCCTL2_CLR_SAI1_SHIFT           (14U)
/*! SAI1 - SAI1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_SAI1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI1_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI1_MASK)

#define CLKCTL0_PSCCTL2_CLR_SAI2_MASK            (0x8000U)
#define CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT           (15U)
/*! SAI2 - SAI2 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_SAI2(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI2_MASK)

#define CLKCTL0_PSCCTL2_CLR_I3C0_MASK            (0x10000U)
#define CLKCTL0_PSCCTL2_CLR_I3C0_SHIFT           (16U)
/*! I3C0 - I3C0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_I3C0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_I3C0_SHIFT)) & CLKCTL0_PSCCTL2_CLR_I3C0_MASK)

#define CLKCTL0_PSCCTL2_CLR_I3C1_MASK            (0x20000U)
#define CLKCTL0_PSCCTL2_CLR_I3C1_SHIFT           (17U)
/*! I3C1 - I3C1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_I3C1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_CLR_I3C1_MASK)

#define CLKCTL0_PSCCTL2_CLR_CRC0_MASK            (0x40000U)
#define CLKCTL0_PSCCTL2_CLR_CRC0_SHIFT           (18U)
/*! CRC0 - CRC0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_CRC0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_CRC0_SHIFT)) & CLKCTL0_PSCCTL2_CLR_CRC0_MASK)

#define CLKCTL0_PSCCTL2_CLR_WWDT0_MASK           (0x80000U)
#define CLKCTL0_PSCCTL2_CLR_WWDT0_SHIFT          (19U)
/*! WWDT0 - WWDT0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_WWDT0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_WWDT0_SHIFT)) & CLKCTL0_PSCCTL2_CLR_WWDT0_MASK)

#define CLKCTL0_PSCCTL2_CLR_WWDT1_MASK           (0x100000U)
#define CLKCTL0_PSCCTL2_CLR_WWDT1_SHIFT          (20U)
/*! WWDT1 - WWDT1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_WWDT1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_WWDT1_SHIFT)) & CLKCTL0_PSCCTL2_CLR_WWDT1_MASK)

#define CLKCTL0_PSCCTL2_CLR_CTIMER0_MASK         (0x200000U)
#define CLKCTL0_PSCCTL2_CLR_CTIMER0_SHIFT        (21U)
/*! CTIMER0 - CTIMER0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_CTIMER0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_CTIMER0_SHIFT)) & CLKCTL0_PSCCTL2_CLR_CTIMER0_MASK)

#define CLKCTL0_PSCCTL2_CLR_CTIMER1_MASK         (0x400000U)
#define CLKCTL0_PSCCTL2_CLR_CTIMER1_SHIFT        (22U)
/*! CTIMER1 - CTIMER1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_CTIMER1(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_CTIMER1_SHIFT)) & CLKCTL0_PSCCTL2_CLR_CTIMER1_MASK)

#define CLKCTL0_PSCCTL2_CLR_CTIMER2_MASK         (0x800000U)
#define CLKCTL0_PSCCTL2_CLR_CTIMER2_SHIFT        (23U)
/*! CTIMER2 - CTIMER2 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_CTIMER2(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_CTIMER2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_CTIMER2_MASK)

#define CLKCTL0_PSCCTL2_CLR_CTIMER3_MASK         (0x1000000U)
#define CLKCTL0_PSCCTL2_CLR_CTIMER3_SHIFT        (24U)
/*! CTIMER3 - CTIMER3 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_CTIMER3(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_CTIMER3_SHIFT)) & CLKCTL0_PSCCTL2_CLR_CTIMER3_MASK)

#define CLKCTL0_PSCCTL2_CLR_CTIMER4_MASK         (0x2000000U)
#define CLKCTL0_PSCCTL2_CLR_CTIMER4_SHIFT        (25U)
/*! CTIMER4 - CTIMER4 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_CTIMER4(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_CTIMER4_SHIFT)) & CLKCTL0_PSCCTL2_CLR_CTIMER4_MASK)

#define CLKCTL0_PSCCTL2_CLR_MRT0_MASK            (0x4000000U)
#define CLKCTL0_PSCCTL2_CLR_MRT0_SHIFT           (26U)
/*! MRT0 - MRT0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_MRT0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_MRT0_SHIFT)) & CLKCTL0_PSCCTL2_CLR_MRT0_MASK)

#define CLKCTL0_PSCCTL2_CLR_UTICK0_MASK          (0x8000000U)
#define CLKCTL0_PSCCTL2_CLR_UTICK0_SHIFT         (27U)
/*! UTICK0 - UTICK0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_UTICK0(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_UTICK0_SHIFT)) & CLKCTL0_PSCCTL2_CLR_UTICK0_MASK)

#define CLKCTL0_PSCCTL2_CLR_SEMA42_4_MASK        (0x40000000U)
#define CLKCTL0_PSCCTL2_CLR_SEMA42_4_SHIFT       (30U)
/*! SEMA42_4 - SEMA42_4 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_SEMA42_4(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SEMA42_4_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SEMA42_4_MASK)

#define CLKCTL0_PSCCTL2_CLR_MU4_MASK             (0x80000000U)
#define CLKCTL0_PSCCTL2_CLR_MU4_SHIFT            (31U)
/*! MU4 - MU4 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL2_CLR_MU4(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_MU4_SHIFT)) & CLKCTL0_PSCCTL2_CLR_MU4_MASK)
/*! @} */

/*! @name PSCCTL3_CLR - VDD2_COMP Peripheral Clock Control 3 Clear */
/*! @{ */

#define CLKCTL0_PSCCTL3_CLR_PINT0_MASK           (0x20U)
#define CLKCTL0_PSCCTL3_CLR_PINT0_SHIFT          (5U)
/*! PINT0 - PINT0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_PINT0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_PINT0_SHIFT)) & CLKCTL0_PSCCTL3_CLR_PINT0_MASK)

#define CLKCTL0_PSCCTL3_CLR_FREQME0_MASK         (0x100U)
#define CLKCTL0_PSCCTL3_CLR_FREQME0_SHIFT        (8U)
/*! FREQME0 - FREQME0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_FREQME0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_FREQME0_SHIFT)) & CLKCTL0_PSCCTL3_CLR_FREQME0_MASK)

#define CLKCTL0_PSCCTL3_CLR_INPUTMUX0_MASK       (0x400U)
#define CLKCTL0_PSCCTL3_CLR_INPUTMUX0_SHIFT      (10U)
/*! INPUTMUX0 - INPUTMUX0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_INPUTMUX0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_INPUTMUX0_SHIFT)) & CLKCTL0_PSCCTL3_CLR_INPUTMUX0_MASK)

#define CLKCTL0_PSCCTL3_CLR_SAFO_SGI_MASK        (0x1000U)
#define CLKCTL0_PSCCTL3_CLR_SAFO_SGI_SHIFT       (12U)
/*! SAFO_SGI - SAFO_SGI Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_SAFO_SGI(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_SAFO_SGI_SHIFT)) & CLKCTL0_PSCCTL3_CLR_SAFO_SGI_MASK)

#define CLKCTL0_PSCCTL3_CLR_TRACE_MASK           (0x2000U)
#define CLKCTL0_PSCCTL3_CLR_TRACE_SHIFT          (13U)
/*! TRACE - TRACE Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_TRACE(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_TRACE_SHIFT)) & CLKCTL0_PSCCTL3_CLR_TRACE_MASK)

#define CLKCTL0_PSCCTL3_CLR_PRINCE0_MASK         (0x8000U)
#define CLKCTL0_PSCCTL3_CLR_PRINCE0_SHIFT        (15U)
/*! PRINCE0 - PRINCE0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_PRINCE0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_PRINCE0_SHIFT)) & CLKCTL0_PSCCTL3_CLR_PRINCE0_MASK)

#define CLKCTL0_PSCCTL3_CLR_PRINCE1_MASK         (0x10000U)
#define CLKCTL0_PSCCTL3_CLR_PRINCE1_SHIFT        (16U)
/*! PRINCE1 - PRINCE1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_PRINCE1(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_PRINCE1_SHIFT)) & CLKCTL0_PSCCTL3_CLR_PRINCE1_MASK)

#define CLKCTL0_PSCCTL3_CLR_XSPI1_PRINCE_XEX_MASK (0x20000U)
#define CLKCTL0_PSCCTL3_CLR_XSPI1_PRINCE_XEX_SHIFT (17U)
/*! XSPI1_PRINCE_XEX - XSPI1 PRINCE_XEX Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_XSPI1_PRINCE_XEX(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_XSPI1_PRINCE_XEX_SHIFT)) & CLKCTL0_PSCCTL3_CLR_XSPI1_PRINCE_XEX_MASK)

#define CLKCTL0_PSCCTL3_CLR_CMX_PERFMON0_MASK    (0x40000U)
#define CLKCTL0_PSCCTL3_CLR_CMX_PERFMON0_SHIFT   (18U)
/*! CMX_PERFMON0 - CMX_PERFMON0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_CMX_PERFMON0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_CMX_PERFMON0_SHIFT)) & CLKCTL0_PSCCTL3_CLR_CMX_PERFMON0_MASK)

#define CLKCTL0_PSCCTL3_CLR_CMX_PERFMON1_MASK    (0x80000U)
#define CLKCTL0_PSCCTL3_CLR_CMX_PERFMON1_SHIFT   (19U)
/*! CMX_PERFMON1 - CMX_PERFMON1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL3_CLR_CMX_PERFMON1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_CMX_PERFMON1_SHIFT)) & CLKCTL0_PSCCTL3_CLR_CMX_PERFMON1_MASK)
/*! @} */

/*! @name PSCCTL4_CLR - VDD2_COMP Peripheral Clock Control 4 Clear */
/*! @{ */

#define CLKCTL0_PSCCTL4_CLR_HIFI4_MASK           (0x1U)
#define CLKCTL0_PSCCTL4_CLR_HIFI4_SHIFT          (0U)
/*! HiFi4 - HiFi4 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL4_CLR_HIFI4(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL4_CLR_HIFI4_SHIFT)) & CLKCTL0_PSCCTL4_CLR_HIFI4_MASK)
/*! @} */

/*! @name PSCCTL5_CLR - VDD2_COMP Peripheral Clock Control 5 Clear */
/*! @{ */

#define CLKCTL0_PSCCTL5_CLR_NPU0_MASK            (0x1U)
#define CLKCTL0_PSCCTL5_CLR_NPU0_SHIFT           (0U)
/*! NPU0 - NPU0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL5_CLR_NPU0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_CLR_NPU0_SHIFT)) & CLKCTL0_PSCCTL5_CLR_NPU0_MASK)

#define CLKCTL0_PSCCTL5_CLR_COMP_ACCESS_RAM_ARBITER1_MASK (0x4U)
#define CLKCTL0_PSCCTL5_CLR_COMP_ACCESS_RAM_ARBITER1_SHIFT (2U)
/*! COMP_ACCESS_RAM_ARBITER1 - VDD2_COMP Access RAM Arbiter1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL5_CLR_COMP_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_CLR_COMP_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL0_PSCCTL5_CLR_COMP_ACCESS_RAM_ARBITER1_MASK)

#define CLKCTL0_PSCCTL5_CLR_IOPCTL0_MASK         (0x8U)
#define CLKCTL0_PSCCTL5_CLR_IOPCTL0_SHIFT        (3U)
/*! IOPCTL0 - IOPCTL0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL5_CLR_IOPCTL0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_CLR_IOPCTL0_SHIFT)) & CLKCTL0_PSCCTL5_CLR_IOPCTL0_MASK)

#define CLKCTL0_PSCCTL5_CLR_HIFI4_ACCESS_RAM_ARBITER1_MASK (0x10U)
#define CLKCTL0_PSCCTL5_CLR_HIFI4_ACCESS_RAM_ARBITER1_SHIFT (4U)
/*! HiFi4_ACCESS_RAM_ARBITER1 - HiFi4 Access RAM Arbiter1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL5_CLR_HIFI4_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_CLR_HIFI4_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL0_PSCCTL5_CLR_HIFI4_ACCESS_RAM_ARBITER1_MASK)

#define CLKCTL0_PSCCTL5_CLR_MEDIA_ACCESS_RAM_ARBITER0_MASK (0x20U)
#define CLKCTL0_PSCCTL5_CLR_MEDIA_ACCESS_RAM_ARBITER0_SHIFT (5U)
/*! MEDIA_ACCESS_RAM_ARBITER0 - VDD2_Media Access RAM Arbiter0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL0_PSCCTL5_CLR_MEDIA_ACCESS_RAM_ARBITER0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL5_CLR_MEDIA_ACCESS_RAM_ARBITER0_SHIFT)) & CLKCTL0_PSCCTL5_CLR_MEDIA_ACCESS_RAM_ARBITER0_MASK)
/*! @} */

/*! @name ONE_SRC_CLKSLICE_ENABLE - One Source Clock Slice Enable */
/*! @{ */

#define CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET0_FCLK_EN_MASK (0x1U)
#define CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET0_FCLK_EN_SHIFT (0U)
/*! dGDET0_FCLK_EN - dGDET0 Functional Clock Enable
 *  0b0..Gates dGDET0 functional clock.
 *  0b1..Enables dGDET0 functional clock.
 */
#define CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET0_FCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET0_FCLK_EN_SHIFT)) & CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET0_FCLK_EN_MASK)

#define CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET1_FCLK_EN_MASK (0x2U)
#define CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET1_FCLK_EN_SHIFT (1U)
/*! dGDET1_FCLK_EN - dGDET1 Functional Clock Enable
 *  0b0..Gates dGDET1 functional clock. This clock's source is dfro1_div8. Make sure dfro1_div8 is active before enabling GDET1_FCLK
 *  0b1..Enables dGDET1 functional clock.
 */
#define CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET1_FCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET1_FCLK_EN_SHIFT)) & CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET1_FCLK_EN_MASK)
/*! @} */

/*! @name FRO01CLKSTATUS - FRO_TUNER0 and FRO_TUNER1 Clock Status */
/*! @{ */

#define CLKCTL0_FRO01CLKSTATUS_FRO1_CLK_OK_MASK  (0x1U)
#define CLKCTL0_FRO01CLKSTATUS_FRO1_CLK_OK_SHIFT (0U)
/*! FRO1_CLK_OK - FRO_TUNER1 Clock OK
 *  0b0..FRO_TUNER1 clock has not yet reached its final frequency.
 *  0b1..FRO_TUNER1 clock has reached its final frequency.
 */
#define CLKCTL0_FRO01CLKSTATUS_FRO1_CLK_OK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO01CLKSTATUS_FRO1_CLK_OK_SHIFT)) & CLKCTL0_FRO01CLKSTATUS_FRO1_CLK_OK_MASK)

#define CLKCTL0_FRO01CLKSTATUS_FRO0_CLK_OK_MASK  (0x2U)
#define CLKCTL0_FRO01CLKSTATUS_FRO0_CLK_OK_SHIFT (1U)
/*! FRO0_CLK_OK - FRO_TUNER0 Clock OK
 *  0b0..FRO_TUNER0 clock has not yet reached its final frequency.
 *  0b1..FRO_TUNER0 clock has reached its final frequency.
 */
#define CLKCTL0_FRO01CLKSTATUS_FRO0_CLK_OK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO01CLKSTATUS_FRO0_CLK_OK_SHIFT)) & CLKCTL0_FRO01CLKSTATUS_FRO0_CLK_OK_MASK)
/*! @} */

/*! @name FRO0MAXDOMAINEN - FRO0MAX Clock Domain Enable */
/*! @{ */

#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_CMPT_MASK (0x1U)
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_CMPT_SHIFT (0U)
/*! FRO0MAX_OF_CMPT - fro0_max Clock of VDD2_COMP
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_CMPT_SHIFT)) & CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_CMPT_MASK)

#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_SENSE_MASK (0x2U)
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_SENSE_SHIFT (1U)
/*! FRO0MAX_OF_SENSE - fro0_max Clock of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_SENSE_SHIFT)) & CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_SENSE_MASK)

#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_DSP_MASK (0x4U)
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_DSP_SHIFT (2U)
/*! FRO0MAX_OF_VDD2_DSP - fro0_max Clock of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_DSP_SHIFT)) & CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_DSP_MASK)

#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MD2_MASK (0x8U)
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MD2_SHIFT (3U)
/*! FRO0MAX_OF_MD2 - fro0_max Clock of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MD2_SHIFT)) & CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MD2_MASK)

#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MDN_MASK (0x10U)
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MDN_SHIFT (4U)
/*! FRO0MAX_OF_MDN - fro0_max Clock of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MDN_SHIFT)) & CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_MDN_MASK)

#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_COM_MASK (0x20U)
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_COM_SHIFT (5U)
/*! FRO0MAX_OF_VDD2_COM - fro0_max Clock of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_COM_SHIFT)) & CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_VDD2_COM_MASK)

#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_COMN_MASK (0x40U)
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_COMN_SHIFT (6U)
/*! FRO0MAX_OF_COMN - fro0_max Clock of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_COMN_SHIFT)) & CLKCTL0_FRO0MAXDOMAINEN_FRO0MAX_OF_COMN_MASK)
/*! @} */

/*! @name MAINCLKDIV - VDD2_COMP Main Clock Divider */
/*! @{ */

#define CLKCTL0_MAINCLKDIV_DIV_MASK              (0xFFU)
#define CLKCTL0_MAINCLKDIV_DIV_SHIFT             (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_MAINCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKDIV_DIV_SHIFT)) & CLKCTL0_MAINCLKDIV_DIV_MASK)

#define CLKCTL0_MAINCLKDIV_BUSY_MASK             (0x10000000U)
#define CLKCTL0_MAINCLKDIV_BUSY_SHIFT            (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_MAINCLKDIV_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKDIV_BUSY_SHIFT)) & CLKCTL0_MAINCLKDIV_BUSY_MASK)

#define CLKCTL0_MAINCLKDIV_REQFLAG_MASK          (0x80000000U)
#define CLKCTL0_MAINCLKDIV_REQFLAG_SHIFT         (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_MAINCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_MAINCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name CMPTBASECLKSEL - VDD2_COMP Base Clock Select Source */
/*! @{ */

#define CLKCTL0_CMPTBASECLKSEL_SEL_MASK          (0x3U)
#define CLKCTL0_CMPTBASECLKSEL_SEL_SHIFT         (0U)
/*! SEL - VDD2_COMP Base Clock Select Source
 *  0b00..fro1_div3
 *  0b01..fro1_max
 *  0b10..fro0_div3
 *  0b11..1m_lposc
 */
#define CLKCTL0_CMPTBASECLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CMPTBASECLKSEL_SEL_SHIFT)) & CLKCTL0_CMPTBASECLKSEL_SEL_MASK)
/*! @} */

/*! @name DSPBASECLKSEL - VDD2_DSP Base Clock Select Source */
/*! @{ */

#define CLKCTL0_DSPBASECLKSEL_SEL_MASK           (0x3U)
#define CLKCTL0_DSPBASECLKSEL_SEL_SHIFT          (0U)
/*! SEL - VDD2_DSP Base Clock Select Source
 *  0b00..fro1_div3
 *  0b01..fro1_max
 *  0b10..fro0_div3
 *  0b11..1m_lposc
 */
#define CLKCTL0_DSPBASECLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPBASECLKSEL_SEL_SHIFT)) & CLKCTL0_DSPBASECLKSEL_SEL_MASK)
/*! @} */

/*! @name VDD2COMBASECLKSEL - VDD2_COM Base Clock Select Source */
/*! @{ */

#define CLKCTL0_VDD2COMBASECLKSEL_SEL_MASK       (0x3U)
#define CLKCTL0_VDD2COMBASECLKSEL_SEL_SHIFT      (0U)
/*! SEL - VDD2_COM Base Clock Select Source
 *  0b00..fro1_div3
 *  0b01..fro1_max
 *  0b10..fro0_div3
 *  0b11..1m_lposc
 */
#define CLKCTL0_VDD2COMBASECLKSEL_SEL(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_VDD2COMBASECLKSEL_SEL_SHIFT)) & CLKCTL0_VDD2COMBASECLKSEL_SEL_MASK)
/*! @} */

/*! @name MAINCLKSEL - VDD2_COMP Main Clock Source Select */
/*! @{ */

#define CLKCTL0_MAINCLKSEL_SEL_MASK              (0x3U)
#define CLKCTL0_MAINCLKSEL_SEL_SHIFT             (0U)
/*! SEL - VDD2_COMP Main Clock Select Source
 *  0b00..baseclk_cmpt
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..audio_pll_pfd1
 */
#define CLKCTL0_MAINCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKSEL_SEL_SHIFT)) & CLKCTL0_MAINCLKSEL_SEL_MASK)
/*! @} */

/*! @name DSPCPUCLKDIV - VDD2_DSP Clock Divider */
/*! @{ */

#define CLKCTL0_DSPCPUCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_DSPCPUCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_DSPCPUCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPCPUCLKDIV_DIV_SHIFT)) & CLKCTL0_DSPCPUCLKDIV_DIV_MASK)

#define CLKCTL0_DSPCPUCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL0_DSPCPUCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_DSPCPUCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPCPUCLKDIV_BUSY_SHIFT)) & CLKCTL0_DSPCPUCLKDIV_BUSY_MASK)

#define CLKCTL0_DSPCPUCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_DSPCPUCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_DSPCPUCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPCPUCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DSPCPUCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DSPCPUCLKSEL - VDD2_DSP Clock Select Source */
/*! @{ */

#define CLKCTL0_DSPCPUCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL0_DSPCPUCLKSEL_SEL_SHIFT           (0U)
/*! SEL - VDD2_DSP Clock Select Source
 *  0b00..baseclk_dsp
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..main_pll_pfd1
 */
#define CLKCTL0_DSPCPUCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPCPUCLKSEL_SEL_SHIFT)) & CLKCTL0_DSPCPUCLKSEL_SEL_MASK)

#define CLKCTL0_DSPCPUCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL0_DSPCPUCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates output of clock mux.
 *  0b1..Enables output of clock mux.
 */
#define CLKCTL0_DSPCPUCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPCPUCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_DSPCPUCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name RAMCLKSEL - RAM Clock Select Source */
/*! @{ */

#define CLKCTL0_RAMCLKSEL_SEL_MASK               (0x3U)
#define CLKCTL0_RAMCLKSEL_SEL_SHIFT              (0U)
/*! SEL - RAM Clock Select Source
 *  0b00..baseclk_com2
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..fro1_max
 */
#define CLKCTL0_RAMCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_RAMCLKSEL_SEL_SHIFT)) & CLKCTL0_RAMCLKSEL_SEL_MASK)
/*! @} */

/*! @name RAMCLKDIV - RAM Clock Divider */
/*! @{ */

#define CLKCTL0_RAMCLKDIV_DIV_MASK               (0xFFU)
#define CLKCTL0_RAMCLKDIV_DIV_SHIFT              (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_RAMCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_RAMCLKDIV_DIV_SHIFT)) & CLKCTL0_RAMCLKDIV_DIV_MASK)

#define CLKCTL0_RAMCLKDIV_BUSY_MASK              (0x10000000U)
#define CLKCTL0_RAMCLKDIV_BUSY_SHIFT             (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_RAMCLKDIV_BUSY(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_RAMCLKDIV_BUSY_SHIFT)) & CLKCTL0_RAMCLKDIV_BUSY_MASK)

#define CLKCTL0_RAMCLKDIV_REQFLAG_MASK           (0x80000000U)
#define CLKCTL0_RAMCLKDIV_REQFLAG_SHIFT          (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_RAMCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_RAMCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_RAMCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name TPIUFCLKSEL - TPIU (TRACE_RT700) Functional Clock Select Source */
/*! @{ */

#define CLKCTL0_TPIUFCLKSEL_SEL_MASK             (0x3U)
#define CLKCTL0_TPIUFCLKSEL_SEL_SHIFT            (0U)
/*! SEL - TPIU (TRACE_RT700) Clock Select Source
 *  0b00..baseclk_cmpt
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..fro0_div6
 */
#define CLKCTL0_TPIUFCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TPIUFCLKSEL_SEL_SHIFT)) & CLKCTL0_TPIUFCLKSEL_SEL_MASK)

#define CLKCTL0_TPIUFCLKSEL_SEL_EN_MASK          (0x4U)
#define CLKCTL0_TPIUFCLKSEL_SEL_EN_SHIFT         (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for TPIU clock.
 *  0b1..Enables mux output for TPIU clock.
 */
#define CLKCTL0_TPIUFCLKSEL_SEL_EN(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TPIUFCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_TPIUFCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name TPIUCLKDIV - TPIU (TRACE_RT700) Functional Clock Divider */
/*! @{ */

#define CLKCTL0_TPIUCLKDIV_DIV_MASK              (0xFFU)
#define CLKCTL0_TPIUCLKDIV_DIV_SHIFT             (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_TPIUCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TPIUCLKDIV_DIV_SHIFT)) & CLKCTL0_TPIUCLKDIV_DIV_MASK)

#define CLKCTL0_TPIUCLKDIV_BUSY_MASK             (0x10000000U)
#define CLKCTL0_TPIUCLKDIV_BUSY_SHIFT            (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_TPIUCLKDIV_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TPIUCLKDIV_BUSY_SHIFT)) & CLKCTL0_TPIUCLKDIV_BUSY_MASK)

#define CLKCTL0_TPIUCLKDIV_RESET_MASK            (0x20000000U)
#define CLKCTL0_TPIUCLKDIV_RESET_SHIFT           (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL0_TPIUCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TPIUCLKDIV_RESET_SHIFT)) & CLKCTL0_TPIUCLKDIV_RESET_MASK)

#define CLKCTL0_TPIUCLKDIV_HALT_MASK             (0x40000000U)
#define CLKCTL0_TPIUCLKDIV_HALT_SHIFT            (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_TPIUCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TPIUCLKDIV_HALT_SHIFT)) & CLKCTL0_TPIUCLKDIV_HALT_MASK)

#define CLKCTL0_TPIUCLKDIV_REQFLAG_MASK          (0x80000000U)
#define CLKCTL0_TPIUCLKDIV_REQFLAG_SHIFT         (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_TPIUCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TPIUCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_TPIUCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name XSPI0FCLKSEL - XSPI0 Functional Clock Source Select */
/*! @{ */

#define CLKCTL0_XSPI0FCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL0_XSPI0FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - XSPI0 Functional Clock Source Select
 *  0b00..baseclk_comn
 *  0b01..audio_pll_pfd0
 *  0b10..fro0_max
 *  0b11..main_pll_pfd1
 */
#define CLKCTL0_XSPI0FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI0FCLKSEL_SEL_SHIFT)) & CLKCTL0_XSPI0FCLKSEL_SEL_MASK)

#define CLKCTL0_XSPI0FCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL0_XSPI0FCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for XSPI0 clock.
 *  0b1..Enables mux output for XSPI0 clock.
 */
#define CLKCTL0_XSPI0FCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI0FCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_XSPI0FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name XSPI0FCLKDIV - XSPI0 Functional Clock Divider */
/*! @{ */

#define CLKCTL0_XSPI0FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_XSPI0FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_XSPI0FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI0FCLKDIV_DIV_SHIFT)) & CLKCTL0_XSPI0FCLKDIV_DIV_MASK)

#define CLKCTL0_XSPI0FCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL0_XSPI0FCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_XSPI0FCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI0FCLKDIV_BUSY_SHIFT)) & CLKCTL0_XSPI0FCLKDIV_BUSY_MASK)

#define CLKCTL0_XSPI0FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_XSPI0FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_XSPI0FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_XSPI0FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name XSPI1FCLKSEL - XSPI1 Functional Clock Select Source */
/*! @{ */

#define CLKCTL0_XSPI1FCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL0_XSPI1FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b00..baseclk_comn
 *  0b01..audio_pll_pfd1
 *  0b10..fro0_max
 *  0b11..main_pll_pfd2
 */
#define CLKCTL0_XSPI1FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI1FCLKSEL_SEL_SHIFT)) & CLKCTL0_XSPI1FCLKSEL_SEL_MASK)

#define CLKCTL0_XSPI1FCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL0_XSPI1FCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for XSPI1 clock.
 *  0b1..Enables mux output for XSPI1 clock.
 */
#define CLKCTL0_XSPI1FCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI1FCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_XSPI1FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name XSPI1FCLKDIV - XSPI1 Functional Clock Divider */
/*! @{ */

#define CLKCTL0_XSPI1FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_XSPI1FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_XSPI1FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI1FCLKDIV_DIV_SHIFT)) & CLKCTL0_XSPI1FCLKDIV_DIV_MASK)

#define CLKCTL0_XSPI1FCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL0_XSPI1FCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_XSPI1FCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI1FCLKDIV_BUSY_SHIFT)) & CLKCTL0_XSPI1FCLKDIV_BUSY_MASK)

#define CLKCTL0_XSPI1FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_XSPI1FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_XSPI1FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_XSPI1FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_XSPI1FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SCTFCLKSEL - SCT Functional Clock Source Select */
/*! @{ */

#define CLKCTL0_SCTFCLKSEL_SEL_MASK              (0x3U)
#define CLKCTL0_SCTFCLKSEL_SEL_SHIFT             (0U)
/*! SEL - SCT Functional Clock Source Select
 *  0b00..baseclk_cmpt
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..fro0_div6
 */
#define CLKCTL0_SCTFCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKSEL_SEL_SHIFT)) & CLKCTL0_SCTFCLKSEL_SEL_MASK)

#define CLKCTL0_SCTFCLKSEL_SEL_EN_MASK           (0x4U)
#define CLKCTL0_SCTFCLKSEL_SEL_EN_SHIFT          (2U)
/*! SEL_EN - Enable Clock Mux Output
 *  0b0..Gates mux output for SCT clock.
 *  0b1..Enables mux output for SCT clock.
 */
#define CLKCTL0_SCTFCLKSEL_SEL_EN(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_SCTFCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name SCTFCLKDIV - SCT Functional Clock Divider */
/*! @{ */

#define CLKCTL0_SCTFCLKDIV_DIV_MASK              (0xFFU)
#define CLKCTL0_SCTFCLKDIV_DIV_SHIFT             (0U)
/*! DIV - Clock Divider Value Selection */
#define CLKCTL0_SCTFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_DIV_SHIFT)) & CLKCTL0_SCTFCLKDIV_DIV_MASK)

#define CLKCTL0_SCTFCLKDIV_BUSY_MASK             (0x10000000U)
#define CLKCTL0_SCTFCLKDIV_BUSY_SHIFT            (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_SCTFCLKDIV_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_BUSY_SHIFT)) & CLKCTL0_SCTFCLKDIV_BUSY_MASK)

#define CLKCTL0_SCTFCLKDIV_RESET_MASK            (0x20000000U)
#define CLKCTL0_SCTFCLKDIV_RESET_SHIFT           (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Reset the divider counter
 */
#define CLKCTL0_SCTFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_RESET_SHIFT)) & CLKCTL0_SCTFCLKDIV_RESET_MASK)

#define CLKCTL0_SCTFCLKDIV_HALT_MASK             (0x40000000U)
#define CLKCTL0_SCTFCLKDIV_HALT_SHIFT            (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_SCTFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_HALT_SHIFT)) & CLKCTL0_SCTFCLKDIV_HALT_MASK)

#define CLKCTL0_SCTFCLKDIV_REQFLAG_MASK          (0x80000000U)
#define CLKCTL0_SCTFCLKDIV_REQFLAG_SHIFT         (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_SCTFCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SCTFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name UTICK0FCLKSEL - UTICK0 Functional Clock Select Source */
/*! @{ */

#define CLKCTL0_UTICK0FCLKSEL_SEL_MASK           (0x3U)
#define CLKCTL0_UTICK0FCLKSEL_SEL_SHIFT          (0U)
/*! SEL - Select Clock Source
 *  0b00..baseclk_cmpt
 *  0b01..1m_lposc
 *  0b10..fro0_max
 *  0b11..fro1_div2
 */
#define CLKCTL0_UTICK0FCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICK0FCLKSEL_SEL_SHIFT)) & CLKCTL0_UTICK0FCLKSEL_SEL_MASK)

#define CLKCTL0_UTICK0FCLKSEL_SEL_EN_MASK        (0x4U)
#define CLKCTL0_UTICK0FCLKSEL_SEL_EN_SHIFT       (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for UTICK0 clock.
 *  0b1..Enables mux output for UTICK0 clock.
 */
#define CLKCTL0_UTICK0FCLKSEL_SEL_EN(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICK0FCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_UTICK0FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name UTICK0FCLKDIV - UTICK0 Functional Clock Divider */
/*! @{ */

#define CLKCTL0_UTICK0FCLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL0_UTICK0FCLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_UTICK0FCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICK0FCLKDIV_DIV_SHIFT)) & CLKCTL0_UTICK0FCLKDIV_DIV_MASK)

#define CLKCTL0_UTICK0FCLKDIV_BUSY_MASK          (0x10000000U)
#define CLKCTL0_UTICK0FCLKDIV_BUSY_SHIFT         (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_UTICK0FCLKDIV_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICK0FCLKDIV_BUSY_SHIFT)) & CLKCTL0_UTICK0FCLKDIV_BUSY_MASK)

#define CLKCTL0_UTICK0FCLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL0_UTICK0FCLKDIV_RESET_SHIFT        (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL0_UTICK0FCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICK0FCLKDIV_RESET_SHIFT)) & CLKCTL0_UTICK0FCLKDIV_RESET_MASK)

#define CLKCTL0_UTICK0FCLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL0_UTICK0FCLKDIV_HALT_SHIFT         (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_UTICK0FCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICK0FCLKDIV_HALT_SHIFT)) & CLKCTL0_UTICK0FCLKDIV_HALT_MASK)

#define CLKCTL0_UTICK0FCLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL0_UTICK0FCLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_UTICK0FCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICK0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_UTICK0FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name WWDT0FCLKSEL - WWDT0 Functional Clock Source Select */
/*! @{ */

#define CLKCTL0_WWDT0FCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL0_WWDT0FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b00..1m_lposc
 *  0b01..Reserved
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define CLKCTL0_WWDT0FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_WWDT0FCLKSEL_SEL_SHIFT)) & CLKCTL0_WWDT0FCLKSEL_SEL_MASK)

#define CLKCTL0_WWDT0FCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL0_WWDT0FCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Enable Clock Mux Output
 *  0b0..Gates mux output for WWDT0 clock.
 *  0b1..Enables mux output for WWDT0 clock.
 */
#define CLKCTL0_WWDT0FCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_WWDT0FCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_WWDT0FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name WWDT1FCLKSEL - WWDT1 Functional Clock Source Select */
/*! @{ */

#define CLKCTL0_WWDT1FCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL0_WWDT1FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - WWDT1 Functional Clock Source Select
 *  0b00..1m_lposc
 *  0b01..Reserved
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define CLKCTL0_WWDT1FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_WWDT1FCLKSEL_SEL_SHIFT)) & CLKCTL0_WWDT1FCLKSEL_SEL_MASK)

#define CLKCTL0_WWDT1FCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL0_WWDT1FCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Enable Clock Mux Output
 *  0b0..Gates mux output for WWDT1 clock.
 *  0b1..Enables mux output for WWDT1 clock.
 */
#define CLKCTL0_WWDT1FCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_WWDT1FCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_WWDT1FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name SYSTICKFCLKSEL - SYSTICK Functional Clock Source Select */
/*! @{ */

#define CLKCTL0_SYSTICKFCLKSEL_SEL_MASK          (0x3U)
#define CLKCTL0_SYSTICKFCLKSEL_SEL_SHIFT         (0U)
/*! SEL - Select Clock Source for SYSTICK
 *  0b00..baseclk_cmpt
 *  0b01..1m_lposc
 *  0b10..wake32k_clk (switch to other clock source before VDD2_COMP enters into the Deep Sleep Retention mode.)
 *  0b11..osc_clk
 */
#define CLKCTL0_SYSTICKFCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKSEL_SEL_SHIFT)) & CLKCTL0_SYSTICKFCLKSEL_SEL_MASK)

#define CLKCTL0_SYSTICKFCLKSEL_SEL_EN_MASK       (0x4U)
#define CLKCTL0_SYSTICKFCLKSEL_SEL_EN_SHIFT      (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for SYSTICK clock.
 *  0b1..Enables mux output for SYSTICK clock.
 */
#define CLKCTL0_SYSTICKFCLKSEL_SEL_EN(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_SYSTICKFCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name SYSTICKFCLKDIV - SYSTICK Functional Clock Divider */
/*! @{ */

#define CLKCTL0_SYSTICKFCLKDIV_DIV_MASK          (0xFFU)
#define CLKCTL0_SYSTICKFCLKDIV_DIV_SHIFT         (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_SYSTICKFCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_DIV_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_DIV_MASK)

#define CLKCTL0_SYSTICKFCLKDIV_BUSY_MASK         (0x10000000U)
#define CLKCTL0_SYSTICKFCLKDIV_BUSY_SHIFT        (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_SYSTICKFCLKDIV_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_BUSY_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_BUSY_MASK)

#define CLKCTL0_SYSTICKFCLKDIV_RESET_MASK        (0x20000000U)
#define CLKCTL0_SYSTICKFCLKDIV_RESET_SHIFT       (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL0_SYSTICKFCLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_RESET_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_RESET_MASK)

#define CLKCTL0_SYSTICKFCLKDIV_HALT_MASK         (0x40000000U)
#define CLKCTL0_SYSTICKFCLKDIV_HALT_SHIFT        (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_SYSTICKFCLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_HALT_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_HALT_MASK)

#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG_MASK      (0x80000000U)
#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG_SHIFT     (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name FCCLKSEL - LP_FLEXCOMM 0 to 13 Clock Source 0 Select..LP_FLEXCOMM 0 to 13 Clock Source 3 Select */
/*! @{ */

#define CLKCTL0_FCCLKSEL_SEL_MASK                (0x3U)
#define CLKCTL0_FCCLKSEL_SEL_SHIFT               (0U)
/*! SEL - LP_FLEXCOMM 0 to 13 Source Clock 3 Select
 *  0b00..baseclk_cmpt
 *  0b01..fro0_max
 *  0b10..main_pll_pfd3
 *  0b11..osc_clk
 */
#define CLKCTL0_FCCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCCLKSEL_SEL_SHIFT)) & CLKCTL0_FCCLKSEL_SEL_MASK)

#define CLKCTL0_FCCLKSEL_SEL_EN_MASK             (0x4U)
#define CLKCTL0_FCCLKSEL_SEL_EN_SHIFT            (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for FC clock 0.
 *  0b1..Enables mux output for FC clock 0.
 */
#define CLKCTL0_FCCLKSEL_SEL_EN(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_FCCLKSEL_SEL_EN_MASK)
/*! @} */

/* The count of CLKCTL0_FCCLKSEL */
#define CLKCTL0_FCCLKSEL_COUNT                   (14U)

/*! @name FCCLKDIV - LP_FLEXCOMM 0 to 13 Clock Source 0 Divider..LP_FLEXCOMM 0 to 13 Clock Source 3 Divider */
/*! @{ */

#define CLKCTL0_FCCLKDIV_DIV_MASK                (0xFFU)
#define CLKCTL0_FCCLKDIV_DIV_SHIFT               (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_FCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCCLKDIV_DIV_SHIFT)) & CLKCTL0_FCCLKDIV_DIV_MASK)

#define CLKCTL0_FCCLKDIV_BUSY_MASK               (0x10000000U)
#define CLKCTL0_FCCLKDIV_BUSY_SHIFT              (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_FCCLKDIV_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCCLKDIV_BUSY_SHIFT)) & CLKCTL0_FCCLKDIV_BUSY_MASK)

#define CLKCTL0_FCCLKDIV_RESET_MASK              (0x20000000U)
#define CLKCTL0_FCCLKDIV_RESET_SHIFT             (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL0_FCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCCLKDIV_RESET_SHIFT)) & CLKCTL0_FCCLKDIV_RESET_MASK)

#define CLKCTL0_FCCLKDIV_HALT_MASK               (0x40000000U)
#define CLKCTL0_FCCLKDIV_HALT_SHIFT              (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_FCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCCLKDIV_HALT_SHIFT)) & CLKCTL0_FCCLKDIV_HALT_MASK)

#define CLKCTL0_FCCLKDIV_REQFLAG_MASK            (0x80000000U)
#define CLKCTL0_FCCLKDIV_REQFLAG_SHIFT           (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_FCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_FCCLKDIV_REQFLAG_MASK)
/*! @} */

/* The count of CLKCTL0_FCCLKDIV */
#define CLKCTL0_FCCLKDIV_COUNT                   (14U)

/*! @name FCFCLKSEL - LP_FLEXCOMM0 Clock Source Select..LP_FLEXCOMM13 Clock Source Select */
/*! @{ */

#define CLKCTL0_FCFCLKSEL_SEL_MASK               (0x3U)
#define CLKCTL0_FCFCLKSEL_SEL_SHIFT              (0U)
/*! SEL - LP_FLEXCOMM Functional Clock Source Select
 *  0b00..fcclk0
 *  0b01..fcclk1
 *  0b10..fcclk2
 *  0b11..fcclk3
 */
#define CLKCTL0_FCFCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCFCLKSEL_SEL_SHIFT)) & CLKCTL0_FCFCLKSEL_SEL_MASK)

#define CLKCTL0_FCFCLKSEL_SEL_EN_MASK            (0x4U)
#define CLKCTL0_FCFCLKSEL_SEL_EN_SHIFT           (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for LP_FLEXCOMM10 clock.
 *  0b1..Enables mux output for LP_FLEXCOMM10 clock.
 */
#define CLKCTL0_FCFCLKSEL_SEL_EN(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FCFCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_FCFCLKSEL_SEL_EN_MASK)
/*! @} */

/* The count of CLKCTL0_FCFCLKSEL */
#define CLKCTL0_FCFCLKSEL_COUNT                  (14U)

/*! @name SAI012FCLKSEL - SAI0, SAI1 and SAI2 Clock Source Select */
/*! @{ */

#define CLKCTL0_SAI012FCLKSEL_SEL_MASK           (0x3U)
#define CLKCTL0_SAI012FCLKSEL_SEL_SHIFT          (0U)
/*! SEL - SAI0, SAI1 and SAI2 Clock Source Select
 *  0b00..baseclk_cmpt
 *  0b01..fro2_div8
 *  0b10..fro0_max
 *  0b11..audio_clk_cmpt
 */
#define CLKCTL0_SAI012FCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SAI012FCLKSEL_SEL_SHIFT)) & CLKCTL0_SAI012FCLKSEL_SEL_MASK)

#define CLKCTL0_SAI012FCLKSEL_SEL_EN_MASK        (0x4U)
#define CLKCTL0_SAI012FCLKSEL_SEL_EN_SHIFT       (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for SAI0, SAI1 and SAI2 clocks.
 *  0b1..Enables mux output for SAI0, SAI1 and SAI2 clocks.
 */
#define CLKCTL0_SAI012FCLKSEL_SEL_EN(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SAI012FCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_SAI012FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name SAI012CLKDIV - SAI0, SAI1 and SAI2 Functional Clock Divider */
/*! @{ */

#define CLKCTL0_SAI012CLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_SAI012CLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_SAI012CLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SAI012CLKDIV_DIV_SHIFT)) & CLKCTL0_SAI012CLKDIV_DIV_MASK)

#define CLKCTL0_SAI012CLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL0_SAI012CLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_SAI012CLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SAI012CLKDIV_BUSY_SHIFT)) & CLKCTL0_SAI012CLKDIV_BUSY_MASK)

#define CLKCTL0_SAI012CLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_SAI012CLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Reset the divider counter.
 */
#define CLKCTL0_SAI012CLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SAI012CLKDIV_RESET_SHIFT)) & CLKCTL0_SAI012CLKDIV_RESET_MASK)

#define CLKCTL0_SAI012CLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_SAI012CLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_SAI012CLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SAI012CLKDIV_HALT_SHIFT)) & CLKCTL0_SAI012CLKDIV_HALT_MASK)

#define CLKCTL0_SAI012CLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_SAI012CLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_SAI012CLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SAI012CLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SAI012CLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name CTIMERCLKDIV - CTIMER0 Functional Clock Divider..CTIMER4 Functional Clock Divider */
/*! @{ */

#define CLKCTL0_CTIMERCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_CTIMERCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_CTIMERCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CTIMERCLKDIV_DIV_SHIFT)) & CLKCTL0_CTIMERCLKDIV_DIV_MASK)

#define CLKCTL0_CTIMERCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL0_CTIMERCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_CTIMERCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CTIMERCLKDIV_BUSY_SHIFT)) & CLKCTL0_CTIMERCLKDIV_BUSY_MASK)

#define CLKCTL0_CTIMERCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_CTIMERCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL0_CTIMERCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CTIMERCLKDIV_RESET_SHIFT)) & CLKCTL0_CTIMERCLKDIV_RESET_MASK)

#define CLKCTL0_CTIMERCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_CTIMERCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_CTIMERCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CTIMERCLKDIV_HALT_SHIFT)) & CLKCTL0_CTIMERCLKDIV_HALT_MASK)

#define CLKCTL0_CTIMERCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_CTIMERCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_CTIMERCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CTIMERCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_CTIMERCLKDIV_REQFLAG_MASK)
/*! @} */

/* The count of CLKCTL0_CTIMERCLKDIV */
#define CLKCTL0_CTIMERCLKDIV_COUNT               (5U)

/*! @name CTIMERFCLKSEL - CTIMER0 Functional Clock Source Select..CTIMER4 Functional Clock Source Select */
/*! @{ */

#define CLKCTL0_CTIMERFCLKSEL_SEL_MASK           (0x3U)
#define CLKCTL0_CTIMERFCLKSEL_SEL_SHIFT          (0U)
/*! SEL - CTIMER4 Functional Clock Source Select
 *  0b00..baseclk_cmpt
 *  0b01..audio_clk_cmpt
 *  0b10..fro0_max
 *  0b11..wake32k_clk
 */
#define CLKCTL0_CTIMERFCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CTIMERFCLKSEL_SEL_SHIFT)) & CLKCTL0_CTIMERFCLKSEL_SEL_MASK)

#define CLKCTL0_CTIMERFCLKSEL_SEL_EN_MASK        (0x4U)
#define CLKCTL0_CTIMERFCLKSEL_SEL_EN_SHIFT       (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for CTIMER0 clock.
 *  0b1..Enables mux output for CTIMER0 clock.
 */
#define CLKCTL0_CTIMERFCLKSEL_SEL_EN(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CTIMERFCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_CTIMERFCLKSEL_SEL_EN_MASK)
/*! @} */

/* The count of CLKCTL0_CTIMERFCLKSEL */
#define CLKCTL0_CTIMERFCLKSEL_COUNT              (5U)

/*! @name TRNGFCLKSEL - TRNG Functional Clock Source Select */
/*! @{ */

#define CLKCTL0_TRNGFCLKSEL_SEL_MASK             (0x3U)
#define CLKCTL0_TRNGFCLKSEL_SEL_SHIFT            (0U)
/*! SEL - TRNG Functional Clock Source Select
 *  0b00..baseclk_cmpt
 *  0b01..fro1_div2
 *  0b10..fro1_div8
 *  0b11..fro1_div3
 */
#define CLKCTL0_TRNGFCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TRNGFCLKSEL_SEL_SHIFT)) & CLKCTL0_TRNGFCLKSEL_SEL_MASK)

#define CLKCTL0_TRNGFCLKSEL_SEL_EN_MASK          (0x4U)
#define CLKCTL0_TRNGFCLKSEL_SEL_EN_SHIFT         (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for TRNG clock.
 *  0b1..Enables mux output for TRNG clock.
 */
#define CLKCTL0_TRNGFCLKSEL_SEL_EN(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TRNGFCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_TRNGFCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name TRNGFCLKDIV - TRNG FCLK Clock Divider */
/*! @{ */

#define CLKCTL0_TRNGFCLKDIV_DIV_MASK             (0xFFU)
#define CLKCTL0_TRNGFCLKDIV_DIV_SHIFT            (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_TRNGFCLKDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TRNGFCLKDIV_DIV_SHIFT)) & CLKCTL0_TRNGFCLKDIV_DIV_MASK)

#define CLKCTL0_TRNGFCLKDIV_BUSY_MASK            (0x10000000U)
#define CLKCTL0_TRNGFCLKDIV_BUSY_SHIFT           (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_TRNGFCLKDIV_BUSY(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TRNGFCLKDIV_BUSY_SHIFT)) & CLKCTL0_TRNGFCLKDIV_BUSY_MASK)

#define CLKCTL0_TRNGFCLKDIV_RESET_MASK           (0x20000000U)
#define CLKCTL0_TRNGFCLKDIV_RESET_SHIFT          (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL0_TRNGFCLKDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TRNGFCLKDIV_RESET_SHIFT)) & CLKCTL0_TRNGFCLKDIV_RESET_MASK)

#define CLKCTL0_TRNGFCLKDIV_HALT_MASK            (0x40000000U)
#define CLKCTL0_TRNGFCLKDIV_HALT_SHIFT           (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_TRNGFCLKDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TRNGFCLKDIV_HALT_SHIFT)) & CLKCTL0_TRNGFCLKDIV_HALT_MASK)

#define CLKCTL0_TRNGFCLKDIV_REQFLAG_MASK         (0x80000000U)
#define CLKCTL0_TRNGFCLKDIV_REQFLAG_SHIFT        (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_TRNGFCLKDIV_REQFLAG(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_TRNGFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_TRNGFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name I3C01FCLKSEL - I3C0 and I3C1 Functional Clock Source Select */
/*! @{ */

#define CLKCTL0_I3C01FCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL0_I3C01FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - I3C0 and I3C1 Functional Clock Source Select
 *  0b00..baseclk_cmpt
 *  0b01..fro0_max
 *  0b10..fro1_div8
 *  0b11..osc_clk
 */
#define CLKCTL0_I3C01FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01FCLKSEL_SEL_SHIFT)) & CLKCTL0_I3C01FCLKSEL_SEL_MASK)

#define CLKCTL0_I3C01FCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL0_I3C01FCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Enable Clock Mux Output
 *  0b0..Gates mux output for I3C0 and I3C1 clocks.
 *  0b1..Enables mux output for I3C0 and I3C1 clocks.
 */
#define CLKCTL0_I3C01FCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01FCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_I3C01FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name I3C01PCLKSEL - I3C0 and I3C1 P-CLK Source Select */
/*! @{ */

#define CLKCTL0_I3C01PCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL0_I3C01PCLKSEL_SEL_SHIFT           (0U)
/*! SEL - I3C0 and I3C1 P-CLK Source Select
 *  0b00..baseclk_cmpt
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..fro1_max
 */
#define CLKCTL0_I3C01PCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01PCLKSEL_SEL_SHIFT)) & CLKCTL0_I3C01PCLKSEL_SEL_MASK)

#define CLKCTL0_I3C01PCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL0_I3C01PCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for I3C0 and I3C1 P-CLK.
 *  0b1..Enables mux output for I3C0 and I3C1 P-CLK.
 */
#define CLKCTL0_I3C01PCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01PCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_I3C01PCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name I3C01PCLKDIV - I3C0 and I3C1 P-CLK Divider */
/*! @{ */

#define CLKCTL0_I3C01PCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_I3C01PCLKDIV_DIV_SHIFT           (0U)
/*! DIV - I3C0, I3C1 Clock Divider Value */
#define CLKCTL0_I3C01PCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01PCLKDIV_DIV_SHIFT)) & CLKCTL0_I3C01PCLKDIV_DIV_MASK)

#define CLKCTL0_I3C01PCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL0_I3C01PCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_I3C01PCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01PCLKDIV_BUSY_SHIFT)) & CLKCTL0_I3C01PCLKDIV_BUSY_MASK)

#define CLKCTL0_I3C01PCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_I3C01PCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL0_I3C01PCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01PCLKDIV_RESET_SHIFT)) & CLKCTL0_I3C01PCLKDIV_RESET_MASK)

#define CLKCTL0_I3C01PCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_I3C01PCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_I3C01PCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01PCLKDIV_HALT_SHIFT)) & CLKCTL0_I3C01PCLKDIV_HALT_MASK)

#define CLKCTL0_I3C01PCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_I3C01PCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The Divider change has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL0_I3C01PCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01PCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_I3C01PCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name I3C01FCLKDIV - I3C0 and I3C1 Functional Clock Divider */
/*! @{ */

#define CLKCTL0_I3C01FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_I3C01FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - I3C0 and I3C1 Clock Divider Value */
#define CLKCTL0_I3C01FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01FCLKDIV_DIV_SHIFT)) & CLKCTL0_I3C01FCLKDIV_DIV_MASK)

#define CLKCTL0_I3C01FCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL0_I3C01FCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_I3C01FCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01FCLKDIV_BUSY_SHIFT)) & CLKCTL0_I3C01FCLKDIV_BUSY_MASK)

#define CLKCTL0_I3C01FCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_I3C01FCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset Divider Counter
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL0_I3C01FCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01FCLKDIV_RESET_SHIFT)) & CLKCTL0_I3C01FCLKDIV_RESET_MASK)

#define CLKCTL0_I3C01FCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_I3C01FCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_I3C01FCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01FCLKDIV_HALT_SHIFT)) & CLKCTL0_I3C01FCLKDIV_HALT_MASK)

#define CLKCTL0_I3C01FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_I3C01FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change has been finished.
 *  0b1..The change is being made to the divider counter.
 */
#define CLKCTL0_I3C01FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_I3C01FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_I3C01FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name CLKOUTCLKSEL - CLKOUT_VDD2 Clock Select Source */
/*! @{ */

#define CLKCTL0_CLKOUTCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL0_CLKOUTCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b00..baseclk_com2
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..fro1_max
 */
#define CLKCTL0_CLKOUTCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CLKOUTCLKSEL_SEL_SHIFT)) & CLKCTL0_CLKOUTCLKSEL_SEL_MASK)

#define CLKCTL0_CLKOUTCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL0_CLKOUTCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Enable Clock Mux Output
 *  0b0..Gates mux output for CLKOUT_VDD2 clock.
 *  0b1..Enables mux output for CLKOUT_VDD2 clock.
 */
#define CLKCTL0_CLKOUTCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CLKOUTCLKSEL_SEL_EN_SHIFT)) & CLKCTL0_CLKOUTCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name CLKOUTCLKDIV - CLKOUT_VDD2 Clock Divider */
/*! @{ */

#define CLKCTL0_CLKOUTCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_CLKOUTCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL0_CLKOUTCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CLKOUTCLKDIV_DIV_SHIFT)) & CLKCTL0_CLKOUTCLKDIV_DIV_MASK)

#define CLKCTL0_CLKOUTCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL0_CLKOUTCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT_VDD2 is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_CLKOUTCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CLKOUTCLKDIV_BUSY_SHIFT)) & CLKCTL0_CLKOUTCLKDIV_BUSY_MASK)

#define CLKCTL0_CLKOUTCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_CLKOUTCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_CLKOUTCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CLKOUTCLKDIV_RESET_SHIFT)) & CLKCTL0_CLKOUTCLKDIV_RESET_MASK)

#define CLKCTL0_CLKOUTCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_CLKOUTCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt Divider Counter
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL0_CLKOUTCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CLKOUTCLKDIV_HALT_SHIFT)) & CLKCTL0_CLKOUTCLKDIV_HALT_MASK)

#define CLKCTL0_CLKOUTCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_CLKOUTCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL0_CLKOUTCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CLKOUTCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_CLKOUTCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name AUDIOVDD2CLKSEL - VDD2_COMP Audio Clock Source Select */
/*! @{ */

#define CLKCTL0_AUDIOVDD2CLKSEL_SEL_MASK         (0x3U)
#define CLKCTL0_AUDIOVDD2CLKSEL_SEL_SHIFT        (0U)
/*! SEL - Clock Source Select
 *  0b00..mclk_in
 *  0b01..osc_clk
 *  0b10..fro2_div8
 *  0b11..audio_pll_pfd3
 */
#define CLKCTL0_AUDIOVDD2CLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUDIOVDD2CLKSEL_SEL_SHIFT)) & CLKCTL0_AUDIOVDD2CLKSEL_SEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CLKCTL0_Register_Masks */


/* CLKCTL0 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CLKCTL0 base address */
  #define CLKCTL0_BASE                             (0x50001000u)
  /** Peripheral CLKCTL0 base address */
  #define CLKCTL0_BASE_NS                          (0x40001000u)
  /** Peripheral CLKCTL0 base pointer */
  #define CLKCTL0                                  ((CLKCTL0_Type *)CLKCTL0_BASE)
  /** Peripheral CLKCTL0 base pointer */
  #define CLKCTL0_NS                               ((CLKCTL0_Type *)CLKCTL0_BASE_NS)
  /** Array initializer of CLKCTL0 peripheral base addresses */
  #define CLKCTL0_BASE_ADDRS                       { CLKCTL0_BASE }
  /** Array initializer of CLKCTL0 peripheral base pointers */
  #define CLKCTL0_BASE_PTRS                        { CLKCTL0 }
  /** Array initializer of CLKCTL0 peripheral base addresses */
  #define CLKCTL0_BASE_ADDRS_NS                    { CLKCTL0_BASE_NS }
  /** Array initializer of CLKCTL0 peripheral base pointers */
  #define CLKCTL0_BASE_PTRS_NS                     { CLKCTL0_NS }
#else
  /** Peripheral CLKCTL0 base address */
  #define CLKCTL0_BASE                             (0x40001000u)
  /** Peripheral CLKCTL0 base pointer */
  #define CLKCTL0                                  ((CLKCTL0_Type *)CLKCTL0_BASE)
  /** Array initializer of CLKCTL0 peripheral base addresses */
  #define CLKCTL0_BASE_ADDRS                       { CLKCTL0_BASE }
  /** Array initializer of CLKCTL0 peripheral base pointers */
  #define CLKCTL0_BASE_PTRS                        { CLKCTL0 }
#endif

/*!
 * @}
 */ /* end of group CLKCTL0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CLKCTL2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL2_Peripheral_Access_Layer CLKCTL2 Peripheral Access Layer
 * @{
 */

/** CLKCTL2 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PSCCTL0;                           /**< VDDN_COM Peripheral clock 0, offset: 0x10 */
       uint8_t RESERVED_1[44];
  __IO uint32_t PSCCTL0_SET;                       /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x40 */
       uint8_t RESERVED_2[44];
  __IO uint32_t PSCCTL0_CLR;                       /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0x70 */
       uint8_t RESERVED_3[48];
  __IO uint32_t COMMONVDDNCLKSEL;                  /**< VDDN_COM Clock Source Select, offset: 0xA4 */
       uint8_t RESERVED_4[4];
  __IO uint32_t COMMONVDDNCLKDIV;                  /**< VDDN_COM Clock Divider, offset: 0xAC */
       uint8_t RESERVED_5[80];
  __IO uint32_t SYSOSCCTL0;                        /**< XTAL Oscillator Control 0, offset: 0x100 */
       uint8_t RESERVED_6[4];
  __IO uint32_t SYSOSCBYPASS;                      /**< OSC Bypass Clock Source Select, offset: 0x108 */
  __IO uint32_t USBCLKSRC24MCLKSEL;                /**< USB0 Clock Source Select, offset: 0x10C */
  __IO uint32_t COMNBASECLKSEL;                    /**< VDDN_COM Base Clock Source Select, offset: 0x110 */
       uint8_t RESERVED_7[8];
  __IO uint32_t EUSBCLKSRC24MCLKSEL;               /**< USB1 (eUSB) Clock Source Select, offset: 0x11C */
       uint8_t RESERVED_8[224];
  __IO uint32_t MAINPLL0CLKSEL;                    /**< Main PLL0 Clock Source Select, offset: 0x200 */
  __IO uint32_t MAINPLL0CTL0;                      /**< Main PLL0 Control 0, offset: 0x204 */
       uint8_t RESERVED_9[4];
  __IO uint32_t MAINPLL0LOCKTIMEDIV2;              /**< Main PLL0 Lock Time Div2, offset: 0x20C */
  __IO uint32_t MAINPLL0NUM;                       /**< Main PLL0 Numerator, offset: 0x210 */
  __IO uint32_t MAINPLL0DENOM;                     /**< Main PLL0 Denominator, offset: 0x214 */
  __IO uint32_t MAINPLL0PFD;                       /**< Main PLL0 PFD, offset: 0x218 */
       uint8_t RESERVED_10[4];
  __IO uint32_t MAINPLL0PFDDOMAINEN;               /**< Main PLL0 PFD Clock Domain Enable, offset: 0x220 */
       uint8_t RESERVED_11[476];
  __IO uint32_t AUDIOPLL0CLKSEL;                   /**< Audio PLL0 Clock Source Select, offset: 0x400 */
  __IO uint32_t AUDIOPLL0CTL0;                     /**< Audio PLL0 Control 0, offset: 0x404 */
       uint8_t RESERVED_12[4];
  __IO uint32_t AUDIOPLL0LOCKTIMEDIV2;             /**< Audio PLL0 Lock Time Divide-by-2, offset: 0x40C */
  __IO uint32_t AUDIOPLL0NUM;                      /**< Audio PLL0 Numerator, offset: 0x410 */
  __IO uint32_t AUDIOPLL0DENOM;                    /**< Audio PLL0 Denominator, offset: 0x414 */
  __IO uint32_t AUDIOPLL0PFD;                      /**< Audio PLL0 PFD, offset: 0x418 */
       uint8_t RESERVED_13[4];
  __IO uint32_t AUDIOPLL0PFDDOMAINEN;              /**< Audio PLL0 PFD Clock Enable, offset: 0x420 */
  __IO uint32_t AUDIOPLL0VCODOMAINEN;              /**< Audio PLL0 VCO Clock Enable, offset: 0x424 */
       uint8_t RESERVED_14[472];
  __IO uint32_t CKIL_32K_GATE;                     /**< CKIL 32kHz Clock Gate, offset: 0x600 */
} CLKCTL2_Type;

/* ----------------------------------------------------------------------------
   -- CLKCTL2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL2_Register_Masks CLKCTL2 Register Masks
 * @{
 */

/*! @name PSCCTL0 - VDDN_COM Peripheral clock 0 */
/*! @{ */

#define CLKCTL2_PSCCTL0_SYSCON2_MASK             (0x8U)
#define CLKCTL2_PSCCTL0_SYSCON2_SHIFT            (3U)
/*! SYSCON2 - SYSCON2 clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_PSCCTL0_SYSCON2(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL2_PSCCTL0_SYSCON2_SHIFT)) & CLKCTL2_PSCCTL0_SYSCON2_MASK)

#define CLKCTL2_PSCCTL0_IOPCTL2_MASK             (0x10U)
#define CLKCTL2_PSCCTL0_IOPCTL2_SHIFT            (4U)
/*! IOPCTL2 - IOPCTL2 clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_PSCCTL0_IOPCTL2(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL2_PSCCTL0_IOPCTL2_SHIFT)) & CLKCTL2_PSCCTL0_IOPCTL2_MASK)
/*! @} */

/*! @name PSCCTL0_SET - VDDN_COM Peripheral Clock 0 Set */
/*! @{ */

#define CLKCTL2_PSCCTL0_SET_SYSCON2_MASK         (0x8U)
#define CLKCTL2_PSCCTL0_SET_SYSCON2_SHIFT        (3U)
/*! SYSCON2 - SYSCON2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL2_PSCCTL0_SET_SYSCON2(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL2_PSCCTL0_SET_SYSCON2_SHIFT)) & CLKCTL2_PSCCTL0_SET_SYSCON2_MASK)

#define CLKCTL2_PSCCTL0_SET_IOPCTL2_MASK         (0x10U)
#define CLKCTL2_PSCCTL0_SET_IOPCTL2_SHIFT        (4U)
/*! IOPCTL2 - IOPCTL2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL2_PSCCTL0_SET_IOPCTL2(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL2_PSCCTL0_SET_IOPCTL2_SHIFT)) & CLKCTL2_PSCCTL0_SET_IOPCTL2_MASK)
/*! @} */

/*! @name PSCCTL0_CLR - VDDN_COM Peripheral Clock 0 Clear */
/*! @{ */

#define CLKCTL2_PSCCTL0_CLR_SYSCON2_MASK         (0x8U)
#define CLKCTL2_PSCCTL0_CLR_SYSCON2_SHIFT        (3U)
/*! SYSCON2 - SYSCON2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL2_PSCCTL0_CLR_SYSCON2(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL2_PSCCTL0_CLR_SYSCON2_SHIFT)) & CLKCTL2_PSCCTL0_CLR_SYSCON2_MASK)

#define CLKCTL2_PSCCTL0_CLR_IOPCTL2_MASK         (0x10U)
#define CLKCTL2_PSCCTL0_CLR_IOPCTL2_SHIFT        (4U)
/*! IOPCTL2 - IOPCTL2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL2_PSCCTL0_CLR_IOPCTL2(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL2_PSCCTL0_CLR_IOPCTL2_SHIFT)) & CLKCTL2_PSCCTL0_CLR_IOPCTL2_MASK)
/*! @} */

/*! @name COMMONVDDNCLKSEL - VDDN_COM Clock Source Select */
/*! @{ */

#define CLKCTL2_COMMONVDDNCLKSEL_SEL_MASK        (0x3U)
#define CLKCTL2_COMMONVDDNCLKSEL_SEL_SHIFT       (0U)
/*! SEL - VDDN_COM Clock Source Select
 *  0b00..baseclk_comn
 *  0b01..main_pll_pfd3
 *  0b10..fro1_max
 *  0b11..osc_clk
 */
#define CLKCTL2_COMMONVDDNCLKSEL_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL2_COMMONVDDNCLKSEL_SEL_SHIFT)) & CLKCTL2_COMMONVDDNCLKSEL_SEL_MASK)
/*! @} */

/*! @name COMMONVDDNCLKDIV - VDDN_COM Clock Divider */
/*! @{ */

#define CLKCTL2_COMMONVDDNCLKDIV_DIV_MASK        (0xFFU)
#define CLKCTL2_COMMONVDDNCLKDIV_DIV_SHIFT       (0U)
/*! DIV - Clock Divider Value Selection */
#define CLKCTL2_COMMONVDDNCLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL2_COMMONVDDNCLKDIV_DIV_SHIFT)) & CLKCTL2_COMMONVDDNCLKDIV_DIV_MASK)

#define CLKCTL2_COMMONVDDNCLKDIV_BUSY_MASK       (0x10000000U)
#define CLKCTL2_COMMONVDDNCLKDIV_BUSY_SHIFT      (28U)
/*! BUSY - Busy Flag
 *  0b0..The clkout is outputed with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL2_COMMONVDDNCLKDIV_BUSY(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL2_COMMONVDDNCLKDIV_BUSY_SHIFT)) & CLKCTL2_COMMONVDDNCLKDIV_BUSY_MASK)

#define CLKCTL2_COMMONVDDNCLKDIV_REQFLAG_MASK    (0x80000000U)
#define CLKCTL2_COMMONVDDNCLKDIV_REQFLAG_SHIFT   (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL2_COMMONVDDNCLKDIV_REQFLAG(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_COMMONVDDNCLKDIV_REQFLAG_SHIFT)) & CLKCTL2_COMMONVDDNCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SYSOSCCTL0 - XTAL Oscillator Control 0 */
/*! @{ */

#define CLKCTL2_SYSOSCCTL0_LP_ENABLE_MASK        (0x1U)
#define CLKCTL2_SYSOSCCTL0_LP_ENABLE_SHIFT       (0U)
/*! LP_ENABLE - Low Power Mode Enable
 *  0b0..Enables High Gain mode (HP)
 *  0b1..Enables Low Power mode (LP)
 */
#define CLKCTL2_SYSOSCCTL0_LP_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL2_SYSOSCCTL0_LP_ENABLE_SHIFT)) & CLKCTL2_SYSOSCCTL0_LP_ENABLE_MASK)

#define CLKCTL2_SYSOSCCTL0_BYPASS_ENABLE_MASK    (0x2U)
#define CLKCTL2_SYSOSCCTL0_BYPASS_ENABLE_SHIFT   (1U)
/*! BYPASS_ENABLE - Bypass Enable
 *  0b0..Enables normal mode.
 *  0b1..Enables bypass mode. In this mode a clock can be directly inputted into the XTALIN pin.
 */
#define CLKCTL2_SYSOSCCTL0_BYPASS_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_SYSOSCCTL0_BYPASS_ENABLE_SHIFT)) & CLKCTL2_SYSOSCCTL0_BYPASS_ENABLE_MASK)
/*! @} */

/*! @name SYSOSCBYPASS - OSC Bypass Clock Source Select */
/*! @{ */

#define CLKCTL2_SYSOSCBYPASS_SEL_MASK            (0x3U)
#define CLKCTL2_SYSOSCBYPASS_SEL_SHIFT           (0U)
/*! SEL - SYSOSC Bypass Clock Select Source
 *  0b00..osc_out
 *  0b01..CLKIN
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define CLKCTL2_SYSOSCBYPASS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL2_SYSOSCBYPASS_SEL_SHIFT)) & CLKCTL2_SYSOSCBYPASS_SEL_MASK)
/*! @} */

/*! @name USBCLKSRC24MCLKSEL - USB0 Clock Source Select */
/*! @{ */

#define CLKCTL2_USBCLKSRC24MCLKSEL_SEL_MASK      (0x3U)
#define CLKCTL2_USBCLKSRC24MCLKSEL_SEL_SHIFT     (0U)
/*! SEL - USB0 24M Input Clock Select Source
 *  0b00..osc_clk
 *  0b01..fro_div8
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define CLKCTL2_USBCLKSRC24MCLKSEL_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL2_USBCLKSRC24MCLKSEL_SEL_SHIFT)) & CLKCTL2_USBCLKSRC24MCLKSEL_SEL_MASK)
/*! @} */

/*! @name COMNBASECLKSEL - VDDN_COM Base Clock Source Select */
/*! @{ */

#define CLKCTL2_COMNBASECLKSEL_SEL_MASK          (0x3U)
#define CLKCTL2_COMNBASECLKSEL_SEL_SHIFT         (0U)
/*! SEL - Common Base Clock Source Select
 *  0b00..fro1_div3
 *  0b01..fro1_max
 *  0b10..fro0_div3
 *  0b11..1m_lposc
 */
#define CLKCTL2_COMNBASECLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL2_COMNBASECLKSEL_SEL_SHIFT)) & CLKCTL2_COMNBASECLKSEL_SEL_MASK)
/*! @} */

/*! @name EUSBCLKSRC24MCLKSEL - USB1 (eUSB) Clock Source Select */
/*! @{ */

#define CLKCTL2_EUSBCLKSRC24MCLKSEL_SEL_MASK     (0x3U)
#define CLKCTL2_EUSBCLKSRC24MCLKSEL_SEL_SHIFT    (0U)
/*! SEL - 24M USB1 (eUSB) Input Clock Source
 *  0b00..osc_clk
 *  0b01..fro1_div8
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define CLKCTL2_EUSBCLKSRC24MCLKSEL_SEL(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL2_EUSBCLKSRC24MCLKSEL_SEL_SHIFT)) & CLKCTL2_EUSBCLKSRC24MCLKSEL_SEL_MASK)
/*! @} */

/*! @name MAINPLL0CLKSEL - Main PLL0 Clock Source Select */
/*! @{ */

#define CLKCTL2_MAINPLL0CLKSEL_SEL_MASK          (0x3U)
#define CLKCTL2_MAINPLL0CLKSEL_SEL_SHIFT         (0U)
/*! SEL - Main PLL0 Clock Select Source
 *  0b00..fro1_div8
 *  0b01..osc_clk
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define CLKCTL2_MAINPLL0CLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0CLKSEL_SEL_SHIFT)) & CLKCTL2_MAINPLL0CLKSEL_SEL_MASK)
/*! @} */

/*! @name MAINPLL0CTL0 - Main PLL0 Control 0 */
/*! @{ */

#define CLKCTL2_MAINPLL0CTL0_BYPASS_MASK         (0x1U)
#define CLKCTL2_MAINPLL0CTL0_BYPASS_SHIFT        (0U)
/*! BYPASS - MAINPLL0 BYPASS
 *  0b0..PFD outputs are PFD-programmed clocks.
 *  0b1..Bypass mode: PFD outputs are sourced directly from the reference input clock.
 */
#define CLKCTL2_MAINPLL0CTL0_BYPASS(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0CTL0_BYPASS_SHIFT)) & CLKCTL2_MAINPLL0CTL0_BYPASS_MASK)

#define CLKCTL2_MAINPLL0CTL0_RESET_MASK          (0x2U)
#define CLKCTL2_MAINPLL0CTL0_RESET_SHIFT         (1U)
/*! RESET - MAINPLL0 Reset
 *  0b0..MAINPLL0 reset is removed.
 *  0b1..MAINPLL0 is placed into reset.
 */
#define CLKCTL2_MAINPLL0CTL0_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0CTL0_RESET_SHIFT)) & CLKCTL2_MAINPLL0CTL0_RESET_MASK)

#define CLKCTL2_MAINPLL0CTL0_HOLD_RING_OFF_ENA_MASK (0x2000U)
#define CLKCTL2_MAINPLL0CTL0_HOLD_RING_OFF_ENA_SHIFT (13U)
/*! HOLD_RING_OFF_ENA - Hold Ring Off Control
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_MAINPLL0CTL0_HOLD_RING_OFF_ENA(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0CTL0_HOLD_RING_OFF_ENA_SHIFT)) & CLKCTL2_MAINPLL0CTL0_HOLD_RING_OFF_ENA_MASK)

#define CLKCTL2_MAINPLL0CTL0_MULT_MASK           (0xFF0000U)
#define CLKCTL2_MAINPLL0CTL0_MULT_SHIFT          (16U)
/*! MULT - Multiplication Factor
 *  0b00010000..Divide by 16
 *  0b00010001..Divided by 17
 *  0b00010010..Divided by 18
 *  0b00010011..Divided by 19
 *  0b00010100..Divided by 20
 *  0b00010101..Divided by 21
 *  0b00010110..Divided by 22
 */
#define CLKCTL2_MAINPLL0CTL0_MULT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0CTL0_MULT_SHIFT)) & CLKCTL2_MAINPLL0CTL0_MULT_MASK)
/*! @} */

/*! @name MAINPLL0LOCKTIMEDIV2 - Main PLL0 Lock Time Div2 */
/*! @{ */

#define CLKCTL2_MAINPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK (0xFFFFU)
#define CLKCTL2_MAINPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT (0U)
/*! LOCKTIMEDIV2 - MAINPLL0 Lock Time Divide-by-2 */
#define CLKCTL2_MAINPLL0LOCKTIMEDIV2_LOCKTIMEDIV2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT)) & CLKCTL2_MAINPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK)
/*! @} */

/*! @name MAINPLL0NUM - Main PLL0 Numerator */
/*! @{ */

#define CLKCTL2_MAINPLL0NUM_NUM_MASK             (0x3FFFFFFFU)
#define CLKCTL2_MAINPLL0NUM_NUM_SHIFT            (0U)
/*! NUM - Numerator */
#define CLKCTL2_MAINPLL0NUM_NUM(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0NUM_NUM_SHIFT)) & CLKCTL2_MAINPLL0NUM_NUM_MASK)
/*! @} */

/*! @name MAINPLL0DENOM - Main PLL0 Denominator */
/*! @{ */

#define CLKCTL2_MAINPLL0DENOM_DENOM_MASK         (0x3FFFFFFFU)
#define CLKCTL2_MAINPLL0DENOM_DENOM_SHIFT        (0U)
/*! DENOM - Denominator */
#define CLKCTL2_MAINPLL0DENOM_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0DENOM_DENOM_SHIFT)) & CLKCTL2_MAINPLL0DENOM_DENOM_MASK)
/*! @} */

/*! @name MAINPLL0PFD - Main PLL0 PFD */
/*! @{ */

#define CLKCTL2_MAINPLL0PFD_PFD0_MASK            (0x3FU)
#define CLKCTL2_MAINPLL0PFD_PFD0_SHIFT           (0U)
/*! PFD0 - PLL Fractional Divider 0 */
#define CLKCTL2_MAINPLL0PFD_PFD0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD0_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD0_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD0_CLKRDY_MASK     (0x40U)
#define CLKCTL2_MAINPLL0PFD_PFD0_CLKRDY_SHIFT    (6U)
/*! PFD0_CLKRDY - PFD0 Clock Ready
 *  0b0..PFD0 clock is not ready.
 *  0b1..PFD0 clock is ready.
 */
#define CLKCTL2_MAINPLL0PFD_PFD0_CLKRDY(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD0_CLKRDY_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD0_CLKRDY_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD0_CLKGATE_MASK    (0x80U)
#define CLKCTL2_MAINPLL0PFD_PFD0_CLKGATE_SHIFT   (7U)
/*! PFD0_CLKGATE - PFD0 Clock Gate
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_MAINPLL0PFD_PFD0_CLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD0_CLKGATE_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD0_CLKGATE_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD1_MASK            (0x3F00U)
#define CLKCTL2_MAINPLL0PFD_PFD1_SHIFT           (8U)
/*! PFD1 - PLL Fractional Divider 1 */
#define CLKCTL2_MAINPLL0PFD_PFD1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD1_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD1_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD1_CLKRDY_MASK     (0x4000U)
#define CLKCTL2_MAINPLL0PFD_PFD1_CLKRDY_SHIFT    (14U)
/*! PFD1_CLKRDY - PFD1 Clock Ready
 *  0b0..PFD1 clock is not ready.
 *  0b1..PFD1 clock is ready.
 */
#define CLKCTL2_MAINPLL0PFD_PFD1_CLKRDY(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD1_CLKRDY_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD1_CLKRDY_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD1_CLKGATE_MASK    (0x8000U)
#define CLKCTL2_MAINPLL0PFD_PFD1_CLKGATE_SHIFT   (15U)
/*! PFD1_CLKGATE - PFD1 Clock Gate
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_MAINPLL0PFD_PFD1_CLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD1_CLKGATE_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD1_CLKGATE_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD2_MASK            (0x3F0000U)
#define CLKCTL2_MAINPLL0PFD_PFD2_SHIFT           (16U)
/*! PFD2 - PLL Fractional Divider 2 */
#define CLKCTL2_MAINPLL0PFD_PFD2(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD2_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD2_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD2_CLKRDY_MASK     (0x400000U)
#define CLKCTL2_MAINPLL0PFD_PFD2_CLKRDY_SHIFT    (22U)
/*! PFD2_CLKRDY - PFD2 Clock Ready
 *  0b0..PFD2 clock is not ready.
 *  0b1..PFD2 clock is ready.
 */
#define CLKCTL2_MAINPLL0PFD_PFD2_CLKRDY(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD2_CLKRDY_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD2_CLKRDY_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD2_CLKGATE_MASK    (0x800000U)
#define CLKCTL2_MAINPLL0PFD_PFD2_CLKGATE_SHIFT   (23U)
/*! PFD2_CLKGATE - PFD2 Clock Gate
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_MAINPLL0PFD_PFD2_CLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD2_CLKGATE_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD2_CLKGATE_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD3_MASK            (0x3F000000U)
#define CLKCTL2_MAINPLL0PFD_PFD3_SHIFT           (24U)
/*! PFD3 - PLL Fractional Divider 3 */
#define CLKCTL2_MAINPLL0PFD_PFD3(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD3_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD3_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD3_CLKRDY_MASK     (0x40000000U)
#define CLKCTL2_MAINPLL0PFD_PFD3_CLKRDY_SHIFT    (30U)
/*! PFD3_CLKRDY - PFD3 Clock Ready
 *  0b0..PFD3 clock is not ready.
 *  0b1..PFD3 clock is ready.
 */
#define CLKCTL2_MAINPLL0PFD_PFD3_CLKRDY(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD3_CLKRDY_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD3_CLKRDY_MASK)

#define CLKCTL2_MAINPLL0PFD_PFD3_CLKGATE_MASK    (0x80000000U)
#define CLKCTL2_MAINPLL0PFD_PFD3_CLKGATE_SHIFT   (31U)
/*! PFD3_CLKGATE - PFD3 Clock Gate
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_MAINPLL0PFD_PFD3_CLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFD_PFD3_CLKGATE_SHIFT)) & CLKCTL2_MAINPLL0PFD_PFD3_CLKGATE_MASK)
/*! @} */

/*! @name MAINPLL0PFDDOMAINEN - Main PLL0 PFD Clock Domain Enable */
/*! @{ */

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_CMPT_MASK (0x1U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_CMPT_SHIFT (0U)
/*! PFD0_OF_CMPT - PFD0 of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_CMPT_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_CMPT_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE_MASK (0x2U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE_SHIFT (1U)
/*! PFD0_OF_VDD1_SENSE - PFD0 of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP_MASK (0x4U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP_SHIFT (2U)
/*! PFD0_OF_VDD2_DSP - PFD0 of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MD2_MASK (0x8U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MD2_SHIFT (3U)
/*! PFD0_OF_MD2 - PFD0 of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MD2_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MD2_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MDN_MASK (0x10U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MDN_SHIFT (4U)
/*! PFD0_OF_MDN - PFD0 of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MDN_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_MDN_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM_MASK (0x20U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM_SHIFT (5U)
/*! PFD0_OF_VDD2_COM - PFD0 of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_COMN_MASK (0x40U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_COMN_SHIFT (6U)
/*! PFD0_OF_COMN - PFD0 of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_COMN_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD0_OF_COMN_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_CMPT_MASK (0x100U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_CMPT_SHIFT (8U)
/*! PFD1_OF_CMPT - PFD1 of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_CMPT_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_CMPT_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE_MASK (0x200U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE_SHIFT (9U)
/*! PFD1_OF_VDD1_SENSE - PFD1 of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP_MASK (0x400U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP_SHIFT (10U)
/*! PFD1_OF_VDD2_DSP - PFD1 of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MD2_MASK (0x800U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MD2_SHIFT (11U)
/*! PFD1_OF_MD2 - PFD1 of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MD2_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MD2_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MDN_MASK (0x1000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MDN_SHIFT (12U)
/*! PFD1_OF_MDN - PFD1 of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MDN_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_MDN_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM_MASK (0x2000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM_SHIFT (13U)
/*! PFD1_OF_VDD2_COM - PFD1 of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_COMN_MASK (0x4000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_COMN_SHIFT (14U)
/*! PFD1_OF_COMN - PFD1 of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_COMN_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD1_OF_COMN_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_CMPT_MASK (0x10000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_CMPT_SHIFT (16U)
/*! PFD2_OF_CMPT - PFD2 of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_CMPT_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_CMPT_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE_MASK (0x20000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE_SHIFT (17U)
/*! PFD2_OF_VDD1_SENSE - PFD2 of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP_MASK (0x40000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP_SHIFT (18U)
/*! PFD2_OF_VDD2_DSP - PFD2 of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MD2_MASK (0x80000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MD2_SHIFT (19U)
/*! PFD2_OF_MD2 - PFD2 of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MD2_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MD2_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MDN_MASK (0x100000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MDN_SHIFT (20U)
/*! PFD2_OF_MDN - PFD2 of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MDN_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_MDN_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM_MASK (0x200000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM_SHIFT (21U)
/*! PFD2_OF_VDD2_COM - PFD2 of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_COMN_MASK (0x400000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_COMN_SHIFT (22U)
/*! PFD2_OF_COMN - PFD2 of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_COMN_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD2_OF_COMN_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_CMPT_MASK (0x1000000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_CMPT_SHIFT (24U)
/*! PFD3_OF_CMPT - PFD3 of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_CMPT_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_CMPT_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE_MASK (0x2000000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE_SHIFT (25U)
/*! PFD3_OF_VDD1_SENSE - PFD3 of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP_MASK (0x4000000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP_SHIFT (26U)
/*! PFD3_OF_VDD2_DSP - PFD3 of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MD2_MASK (0x8000000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MD2_SHIFT (27U)
/*! PFD3_OF_MD2 - PFD3 of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MD2_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MD2_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MDN_MASK (0x10000000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MDN_SHIFT (28U)
/*! PFD3_OF_MDN - PFD3 of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MDN_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_MDN_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM_MASK (0x20000000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM_SHIFT (29U)
/*! PFD3_OF_VDD2_COM - PFD3 of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM_MASK)

#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_COMN_MASK (0x40000000U)
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_COMN_SHIFT (30U)
/*! PFD3_OF_COMN - PFD3 of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_COMN_SHIFT)) & CLKCTL2_MAINPLL0PFDDOMAINEN_PFD3_OF_COMN_MASK)
/*! @} */

/*! @name AUDIOPLL0CLKSEL - Audio PLL0 Clock Source Select */
/*! @{ */

#define CLKCTL2_AUDIOPLL0CLKSEL_SEL_MASK         (0x3U)
#define CLKCTL2_AUDIOPLL0CLKSEL_SEL_SHIFT        (0U)
/*! SEL - Audio PLL0 Clock Source Select
 *  0b00..fro1_div8
 *  0b01..osc_clk (User-Selectable)
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define CLKCTL2_AUDIOPLL0CLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0CLKSEL_SEL_SHIFT)) & CLKCTL2_AUDIOPLL0CLKSEL_SEL_MASK)
/*! @} */

/*! @name AUDIOPLL0CTL0 - Audio PLL0 Control 0 */
/*! @{ */

#define CLKCTL2_AUDIOPLL0CTL0_BYPASS_MASK        (0x1U)
#define CLKCTL2_AUDIOPLL0CTL0_BYPASS_SHIFT       (0U)
/*! BYPASS - Bypass Mode
 *  0b0..PFD outputs are PFD-programmed clocks.
 *  0b1..Bypass mode. PFD outputs are sourced directly from the reference input clock.
 */
#define CLKCTL2_AUDIOPLL0CTL0_BYPASS(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0CTL0_BYPASS_SHIFT)) & CLKCTL2_AUDIOPLL0CTL0_BYPASS_MASK)

#define CLKCTL2_AUDIOPLL0CTL0_RESET_MASK         (0x2U)
#define CLKCTL2_AUDIOPLL0CTL0_RESET_SHIFT        (1U)
/*! RESET - AUDIOPLL0 Reset
 *  0b0..Audio PLL0 reset is removed.
 *  0b1..Audio PLL0 is placed into reset.
 */
#define CLKCTL2_AUDIOPLL0CTL0_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0CTL0_RESET_SHIFT)) & CLKCTL2_AUDIOPLL0CTL0_RESET_MASK)

#define CLKCTL2_AUDIOPLL0CTL0_HOLD_RING_OFF_ENA_MASK (0x2000U)
#define CLKCTL2_AUDIOPLL0CTL0_HOLD_RING_OFF_ENA_SHIFT (13U)
/*! HOLD_RING_OFF_ENA - Hold Ring Off Control
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_AUDIOPLL0CTL0_HOLD_RING_OFF_ENA(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0CTL0_HOLD_RING_OFF_ENA_SHIFT)) & CLKCTL2_AUDIOPLL0CTL0_HOLD_RING_OFF_ENA_MASK)

#define CLKCTL2_AUDIOPLL0CTL0_MULT_MASK          (0xFF0000U)
#define CLKCTL2_AUDIOPLL0CTL0_MULT_SHIFT         (16U)
/*! MULT - Multiplication Factor
 *  0b00010000..Divided by 16
 *  0b00010001..Divided by 17
 *  0b00010010..Divided by 18
 *  0b00010011..Divided by 19
 *  0b00010100..Divided by 20
 *  0b00010101..Divided by 21
 *  0b00010110..Divided by 22
 */
#define CLKCTL2_AUDIOPLL0CTL0_MULT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0CTL0_MULT_SHIFT)) & CLKCTL2_AUDIOPLL0CTL0_MULT_MASK)

#define CLKCTL2_AUDIOPLL0CTL0_VCO_OUT_ENABLE_MASK (0x1000000U)
#define CLKCTL2_AUDIOPLL0CTL0_VCO_OUT_ENABLE_SHIFT (24U)
/*! VCO_OUT_ENABLE - VCO Output Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_AUDIOPLL0CTL0_VCO_OUT_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0CTL0_VCO_OUT_ENABLE_SHIFT)) & CLKCTL2_AUDIOPLL0CTL0_VCO_OUT_ENABLE_MASK)
/*! @} */

/*! @name AUDIOPLL0LOCKTIMEDIV2 - Audio PLL0 Lock Time Divide-by-2 */
/*! @{ */

#define CLKCTL2_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK (0xFFFFU)
#define CLKCTL2_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT (0U)
/*! LOCKTIMEDIV2 - AUDIOPLL0 Lock Time Divide-by-2 */
#define CLKCTL2_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT)) & CLKCTL2_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK)
/*! @} */

/*! @name AUDIOPLL0NUM - Audio PLL0 Numerator */
/*! @{ */

#define CLKCTL2_AUDIOPLL0NUM_NUM_MASK            (0x3FFFFFFFU)
#define CLKCTL2_AUDIOPLL0NUM_NUM_SHIFT           (0U)
/*! NUM - Numerator */
#define CLKCTL2_AUDIOPLL0NUM_NUM(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0NUM_NUM_SHIFT)) & CLKCTL2_AUDIOPLL0NUM_NUM_MASK)
/*! @} */

/*! @name AUDIOPLL0DENOM - Audio PLL0 Denominator */
/*! @{ */

#define CLKCTL2_AUDIOPLL0DENOM_DENOM_MASK        (0x3FFFFFFFU)
#define CLKCTL2_AUDIOPLL0DENOM_DENOM_SHIFT       (0U)
/*! DENOM - Denominator */
#define CLKCTL2_AUDIOPLL0DENOM_DENOM(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0DENOM_DENOM_SHIFT)) & CLKCTL2_AUDIOPLL0DENOM_DENOM_MASK)
/*! @} */

/*! @name AUDIOPLL0PFD - Audio PLL0 PFD */
/*! @{ */

#define CLKCTL2_AUDIOPLL0PFD_PFD0_MASK           (0x3FU)
#define CLKCTL2_AUDIOPLL0PFD_PFD0_SHIFT          (0U)
/*! PFD0 - PLL Fractional Divider 0 */
#define CLKCTL2_AUDIOPLL0PFD_PFD0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD0_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD0_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD0_CLKRDY_MASK    (0x40U)
#define CLKCTL2_AUDIOPLL0PFD_PFD0_CLKRDY_SHIFT   (6U)
/*! PFD0_CLKRDY - PFD0 Clock Ready Status Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define CLKCTL2_AUDIOPLL0PFD_PFD0_CLKRDY(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD0_CLKRDY_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD0_CLKRDY_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_MASK   (0x80U)
#define CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_SHIFT  (7U)
/*! PFD0_CLKGATE - PFD0 Clock Gate
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD1_MASK           (0x3F00U)
#define CLKCTL2_AUDIOPLL0PFD_PFD1_SHIFT          (8U)
/*! PFD1 - PLL Fractional Divider 1 */
#define CLKCTL2_AUDIOPLL0PFD_PFD1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD1_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD1_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD1_CLKRDY_MASK    (0x4000U)
#define CLKCTL2_AUDIOPLL0PFD_PFD1_CLKRDY_SHIFT   (14U)
/*! PFD1_CLKRDY - PFD1 Clock Ready Status Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define CLKCTL2_AUDIOPLL0PFD_PFD1_CLKRDY(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD1_CLKRDY_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD1_CLKRDY_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD1_CLKGATE_MASK   (0x8000U)
#define CLKCTL2_AUDIOPLL0PFD_PFD1_CLKGATE_SHIFT  (15U)
/*! PFD1_CLKGATE - PFD1 Clock Gate
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_AUDIOPLL0PFD_PFD1_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD1_CLKGATE_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD1_CLKGATE_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD2_MASK           (0x3F0000U)
#define CLKCTL2_AUDIOPLL0PFD_PFD2_SHIFT          (16U)
/*! PFD2 - PLL Fractional Divider 2 */
#define CLKCTL2_AUDIOPLL0PFD_PFD2(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD2_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD2_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD2_CLKRDY_MASK    (0x400000U)
#define CLKCTL2_AUDIOPLL0PFD_PFD2_CLKRDY_SHIFT   (22U)
/*! PFD2_CLKRDY - PFD2 Clock Ready Status Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define CLKCTL2_AUDIOPLL0PFD_PFD2_CLKRDY(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD2_CLKRDY_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD2_CLKRDY_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD2_CLKGATE_MASK   (0x800000U)
#define CLKCTL2_AUDIOPLL0PFD_PFD2_CLKGATE_SHIFT  (23U)
/*! PFD2_CLKGATE - PFD2 Clock Gate
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_AUDIOPLL0PFD_PFD2_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD2_CLKGATE_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD2_CLKGATE_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD3_MASK           (0x3F000000U)
#define CLKCTL2_AUDIOPLL0PFD_PFD3_SHIFT          (24U)
/*! PFD3 - PLL Fractional Divider 3 */
#define CLKCTL2_AUDIOPLL0PFD_PFD3(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD3_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD3_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD3_CLKRDY_MASK    (0x40000000U)
#define CLKCTL2_AUDIOPLL0PFD_PFD3_CLKRDY_SHIFT   (30U)
/*! PFD3_CLKRDY - PFD3 Clock Ready Status Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define CLKCTL2_AUDIOPLL0PFD_PFD3_CLKRDY(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD3_CLKRDY_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD3_CLKRDY_MASK)

#define CLKCTL2_AUDIOPLL0PFD_PFD3_CLKGATE_MASK   (0x80000000U)
#define CLKCTL2_AUDIOPLL0PFD_PFD3_CLKGATE_SHIFT  (31U)
/*! PFD3_CLKGATE - PFD3 Clock Gate
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL2_AUDIOPLL0PFD_PFD3_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFD_PFD3_CLKGATE_SHIFT)) & CLKCTL2_AUDIOPLL0PFD_PFD3_CLKGATE_MASK)
/*! @} */

/*! @name AUDIOPLL0PFDDOMAINEN - Audio PLL0 PFD Clock Enable */
/*! @{ */

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_CMPT_MASK (0x1U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_CMPT_SHIFT (0U)
/*! PFD0_OF_CMPT - PFD0 of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_CMPT_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_CMPT_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE_MASK (0x2U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE_SHIFT (1U)
/*! PFD0_OF_VDD1_SENSE - PFD0 of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD1_SENSE_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP_MASK (0x4U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP_SHIFT (2U)
/*! PFD0_OF_VDD2_DSP - PFD0 of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_DSP_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MD2_MASK (0x8U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MD2_SHIFT (3U)
/*! PFD0_OF_MD2 - PFD0 of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MD2_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MD2_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MDN_MASK (0x10U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MDN_SHIFT (4U)
/*! PFD0_OF_MDN - PFD0 of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MDN_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_MDN_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM_MASK (0x20U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM_SHIFT (5U)
/*! PFD0_OF_VDD2_COM - PFD0 of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_VDD2_COM_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_COMN_MASK (0x40U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_COMN_SHIFT (6U)
/*! PFD0_OF_COMN - PFD0 of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_COMN_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD0_OF_COMN_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_CMPT_MASK (0x100U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_CMPT_SHIFT (8U)
/*! PFD1_OF_CMPT - PFD1 of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_CMPT_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_CMPT_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE_MASK (0x200U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE_SHIFT (9U)
/*! PFD1_OF_VDD1_SENSE - PFD1 of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD1_SENSE_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP_MASK (0x400U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP_SHIFT (10U)
/*! PFD1_OF_VDD2_DSP - PFD1 of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_DSP_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MD2_MASK (0x800U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MD2_SHIFT (11U)
/*! PFD1_OF_MD2 - PFD1 of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MD2_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MD2_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MDN_MASK (0x1000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MDN_SHIFT (12U)
/*! PFD1_OF_MDN - PFD1 of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MDN_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_MDN_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM_MASK (0x2000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM_SHIFT (13U)
/*! PFD1_OF_VDD2_COM - PFD1 of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_VDD2_COM_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_COMN_MASK (0x4000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_COMN_SHIFT (14U)
/*! PFD1_OF_COMN - PFD1 of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_COMN_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD1_OF_COMN_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_CMPT_MASK (0x10000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_CMPT_SHIFT (16U)
/*! PFD2_OF_CMPT - PFD2 of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_CMPT_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_CMPT_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE_MASK (0x20000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE_SHIFT (17U)
/*! PFD2_OF_VDD1_SENSE - PFD2 of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD1_SENSE_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP_MASK (0x40000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP_SHIFT (18U)
/*! PFD2_OF_VDD2_DSP - PFD2 of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_DSP_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MD2_MASK (0x80000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MD2_SHIFT (19U)
/*! PFD2_OF_MD2 - PFD2 of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MD2_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MD2_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MDN_MASK (0x100000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MDN_SHIFT (20U)
/*! PFD2_OF_MDN - PFD2 of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MDN_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_MDN_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM_MASK (0x200000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM_SHIFT (21U)
/*! PFD2_OF_VDD2_COM - PFD2 of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_VDD2_COM_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_COMN_MASK (0x400000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_COMN_SHIFT (22U)
/*! PFD2_OF_COMN - PFD2 of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_COMN_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD2_OF_COMN_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_CMPT_MASK (0x1000000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_CMPT_SHIFT (24U)
/*! PFD3_OF_CMPT - PFD3 of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_CMPT_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_CMPT_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE_MASK (0x2000000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE_SHIFT (25U)
/*! PFD3_OF_VDD1_SENSE - PFD3 of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD1_SENSE_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP_MASK (0x4000000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP_SHIFT (26U)
/*! PFD3_OF_VDD2_DSP - PFD3 of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_DSP_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MD2_MASK (0x8000000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MD2_SHIFT (27U)
/*! PFD3_OF_MD2 - PFD3 of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MD2_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MD2_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MDN_MASK (0x10000000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MDN_SHIFT (28U)
/*! PFD3_OF_MDN - PFD3 of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MDN_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_MDN_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM_MASK (0x20000000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM_SHIFT (29U)
/*! PFD3_OF_VDD2_COM - PFD3 of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_VDD2_COM_MASK)

#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_COMN_MASK (0x40000000U)
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_COMN_SHIFT (30U)
/*! PFD3_OF_COMN - PFD3 of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_COMN_SHIFT)) & CLKCTL2_AUDIOPLL0PFDDOMAINEN_PFD3_OF_COMN_MASK)
/*! @} */

/*! @name AUDIOPLL0VCODOMAINEN - Audio PLL0 VCO Clock Enable */
/*! @{ */

#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_CMPT_MASK (0x1U)
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_CMPT_SHIFT (0U)
/*! VCO_OF_CMPT - VCO of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_CMPT_SHIFT)) & CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_CMPT_MASK)

#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD1_SENSE_MASK (0x2U)
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD1_SENSE_SHIFT (1U)
/*! VCO_OF_VDD1_SENSE - VCO of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD1_SENSE_SHIFT)) & CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD1_SENSE_MASK)

#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_DSP_MASK (0x4U)
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_DSP_SHIFT (2U)
/*! VCO_OF_VDD2_DSP - VCO of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_DSP_SHIFT)) & CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_DSP_MASK)

#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MD2_MASK (0x8U)
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MD2_SHIFT (3U)
/*! VCO_OF_MD2 - VCO of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MD2_SHIFT)) & CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MD2_MASK)

#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MDN_MASK (0x10U)
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MDN_SHIFT (4U)
/*! VCO_OF_MDN - VCO of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MDN_SHIFT)) & CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_MDN_MASK)

#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_COM_MASK (0x20U)
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_COM_SHIFT (5U)
/*! VCO_OF_VDD2_COM - VCO of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_COM_SHIFT)) & CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_VDD2_COM_MASK)

#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_COMN_MASK (0x40U)
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_COMN_SHIFT (6U)
/*! VCO_OF_COMN - VCO of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_COMN_SHIFT)) & CLKCTL2_AUDIOPLL0VCODOMAINEN_VCO_OF_COMN_MASK)
/*! @} */

/*! @name CKIL_32K_GATE - CKIL 32kHz Clock Gate */
/*! @{ */

#define CLKCTL2_CKIL_32K_GATE_CKIL_32K_EN_MASK   (0x1U)
#define CLKCTL2_CKIL_32K_GATE_CKIL_32K_EN_SHIFT  (0U)
/*! CKIL_32K_EN - CKIL 32 kHz Clock Enable
 *  0b0..Gates CKIL 32 kHz clock. You need to read GATED_FLAG field with the value of 1b to confirm the clock is already gated before going ahead.
 *  0b1..Enables CKIL 32 kHz clock.
 */
#define CLKCTL2_CKIL_32K_GATE_CKIL_32K_EN(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL2_CKIL_32K_GATE_CKIL_32K_EN_SHIFT)) & CLKCTL2_CKIL_32K_GATE_CKIL_32K_EN_MASK)

#define CLKCTL2_CKIL_32K_GATE_GATED_FLAG_MASK    (0x2U)
#define CLKCTL2_CKIL_32K_GATE_GATED_FLAG_SHIFT   (1U)
/*! GATED_FLAG - Gated Flag
 *  0b0..The CKIL 32 kHz clock is not gated.
 *  0b1..The CKIL 32 kHz clock is gated.
 */
#define CLKCTL2_CKIL_32K_GATE_GATED_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL2_CKIL_32K_GATE_GATED_FLAG_SHIFT)) & CLKCTL2_CKIL_32K_GATE_GATED_FLAG_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CLKCTL2_Register_Masks */


/* CLKCTL2 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CLKCTL2 base address */
  #define CLKCTL2_BASE                             (0x50065000u)
  /** Peripheral CLKCTL2 base address */
  #define CLKCTL2_BASE_NS                          (0x40065000u)
  /** Peripheral CLKCTL2 base pointer */
  #define CLKCTL2                                  ((CLKCTL2_Type *)CLKCTL2_BASE)
  /** Peripheral CLKCTL2 base pointer */
  #define CLKCTL2_NS                               ((CLKCTL2_Type *)CLKCTL2_BASE_NS)
  /** Array initializer of CLKCTL2 peripheral base addresses */
  #define CLKCTL2_BASE_ADDRS                       { CLKCTL2_BASE }
  /** Array initializer of CLKCTL2 peripheral base pointers */
  #define CLKCTL2_BASE_PTRS                        { CLKCTL2 }
  /** Array initializer of CLKCTL2 peripheral base addresses */
  #define CLKCTL2_BASE_ADDRS_NS                    { CLKCTL2_BASE_NS }
  /** Array initializer of CLKCTL2 peripheral base pointers */
  #define CLKCTL2_BASE_PTRS_NS                     { CLKCTL2_NS }
#else
  /** Peripheral CLKCTL2 base address */
  #define CLKCTL2_BASE                             (0x40065000u)
  /** Peripheral CLKCTL2 base pointer */
  #define CLKCTL2                                  ((CLKCTL2_Type *)CLKCTL2_BASE)
  /** Array initializer of CLKCTL2 peripheral base addresses */
  #define CLKCTL2_BASE_ADDRS                       { CLKCTL2_BASE }
  /** Array initializer of CLKCTL2 peripheral base pointers */
  #define CLKCTL2_BASE_PTRS                        { CLKCTL2 }
#endif

/*!
 * @}
 */ /* end of group CLKCTL2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CLKCTL3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL3_Peripheral_Access_Layer CLKCTL3 Peripheral Access Layer
 * @{
 */

/** CLKCTL3 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PSCCTL0_COMP;                      /**< VDD1_SENSE Peripheral Clock Control 0, offset: 0x10 */
       uint8_t RESERVED_1[44];
  __IO uint32_t PSCCTL0_COMP_SET;                  /**< VDD1_SENSE Peripheral Clock Control 0 Set, offset: 0x40 */
       uint8_t RESERVED_2[44];
  __IO uint32_t PSCCTL0_COMP_CLR;                  /**< VDD1_SENSE Peripheral Clock Control 0 Clear, offset: 0x70 */
       uint8_t RESERVED_3[28];
  __IO uint32_t ONE_SRC_CLKSLICE_ENABLE_COMP;      /**< One Source Clock Slice Enable for VDD2_COMP CPU, offset: 0x90 */
       uint8_t RESERVED_4[380];
  __I  uint32_t LPOSCCTL0;                         /**< Low Power Oscillator Control 0, offset: 0x210 */
  __IO uint32_t SENSEBASECLKSEL;                   /**< VDD1_SENSE Base Clock Select Source, offset: 0x214 */
       uint8_t RESERVED_5[120];
  __I  uint32_t FRO2CLKSTATUS;                     /**< FRO_TUNER2 Clock Status, offset: 0x290 */
       uint8_t RESERVED_6[4];
  __IO uint32_t FRO2MAXDOMAINEN;                   /**< FRO2MAX Clock Domain Enable, offset: 0x298 */
       uint8_t RESERVED_7[356];
  __IO uint32_t SENSEMAINCLKDIV;                   /**< VDD1_SENSE Main Clock Divider, offset: 0x400 */
       uint8_t RESERVED_8[48];
  __IO uint32_t MAINCLKSEL;                        /**< VDD1_SENSE Main Clock Source Select, offset: 0x434 */
       uint8_t RESERVED_9[24];
  __IO uint32_t SENSERAMCLKSEL;                    /**< VDD1_SENSE RAM Clock Source Select, offset: 0x450 */
       uint8_t RESERVED_10[8];
  __IO uint32_t SENSERAMCLKDIV;                    /**< VDD1_SENSE RAM Clock Divider, offset: 0x45C */
       uint8_t RESERVED_11[32];
  __IO uint32_t OSTIMERFCLKSEL;                    /**< OSTIMER Functional Clock Source Select, offset: 0x480 */
  __IO uint32_t OSTIMERFCLKDIV;                    /**< OSTIMER Functional Clock Divider, offset: 0x484 */
       uint8_t RESERVED_12[376];
  __IO uint32_t SDADCFCLKSEL;                      /**< SDADC Functional Clock Source Select, offset: 0x600 */
  __IO uint32_t SDADCFCLKDIV;                      /**< SDADC Functional Clock Divider, offset: 0x604 */
       uint8_t RESERVED_13[24];
  __IO uint32_t SARADCFCLKSEL;                     /**< ADC0 (SARADC) Functional Clock Source Select, offset: 0x620 */
  __IO uint32_t SARADCFCLKDIV;                     /**< ADC0 (SARADC) Functional Clock Divider, offset: 0x624 */
       uint8_t RESERVED_14[296];
  __IO uint32_t WAKE32KCLKSEL;                     /**< Wake 32 kHZ Clock Source Select, offset: 0x750 */
  __IO uint32_t WAKE32KCLKDIV;                     /**< Wake 32kHZ Clock Divider, offset: 0x754 */
       uint8_t RESERVED_15[40];
  __IO uint32_t MICFILFCLKSEL;                     /**< MICFIL Functional Clock Source Select, offset: 0x780 */
  __IO uint32_t MICFILFCLKDIV;                     /**< MICFIL Functional Clock Divider, offset: 0x784 */
  __IO uint32_t LPI2C15FCLKSEL;                    /**< LPI2C15 Functional Clock Source Select, offset: 0x788 */
  __IO uint32_t LPI2C15FCLKDIV;                    /**< LPI2C15 Functional Clock Divider, offset: 0x78C */
       uint8_t RESERVED_16[112];
  __IO uint32_t CLKOUTCLKSEL;                      /**< CLKOUT_VDD1 Clock Source Select, offset: 0x800 */
  __IO uint32_t CLKOUTCLKDIV;                      /**< CLKOUT_VDD1 Clock Divider, offset: 0x804 */
       uint8_t RESERVED_17[8];
  __IO uint32_t PSCCTL0_SENS;                      /**< VDD1_SENSE Peripheral Clock Control 0, offset: 0x810 */
       uint8_t RESERVED_18[44];
  __IO uint32_t PSCCTL0_SENS_SET;                  /**< VDD1_SENSE Peripheral Clock Control 0 Set, offset: 0x840 */
       uint8_t RESERVED_19[44];
  __IO uint32_t PSCCTL0_SENS_CLR;                  /**< VDD1_SENSE Peripheral Clock Control 0 Clear, offset: 0x870 */
       uint8_t RESERVED_20[28];
  __IO uint32_t ONE_SRC_CLKSLICE_ENABLE_SENSE;     /**< One Source Clock Slice Enable for VDD1_SENSE CPU, offset: 0x890 */
} CLKCTL3_Type;

/* ----------------------------------------------------------------------------
   -- CLKCTL3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL3_Register_Masks CLKCTL3 Register Masks
 * @{
 */

/*! @name PSCCTL0_COMP - VDD1_SENSE Peripheral Clock Control 0 */
/*! @{ */

#define CLKCTL3_PSCCTL0_COMP_CPU1_MASK           (0x1U)
#define CLKCTL3_PSCCTL0_COMP_CPU1_SHIFT          (0U)
/*! CPU1 - CPU1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_CPU1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CPU1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CPU1_MASK)

#define CLKCTL3_PSCCTL0_COMP_MU0_MASK            (0x10U)
#define CLKCTL3_PSCCTL0_COMP_MU0_SHIFT           (4U)
/*! MU0 - MU0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_MU0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_MU0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_MU0_MASK)

#define CLKCTL3_PSCCTL0_COMP_MU1_MASK            (0x20U)
#define CLKCTL3_PSCCTL0_COMP_MU1_SHIFT           (5U)
/*! MU1 - MU1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_MU1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_MU1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_MU1_MASK)

#define CLKCTL3_PSCCTL0_COMP_MU2_MASK            (0x40U)
#define CLKCTL3_PSCCTL0_COMP_MU2_SHIFT           (6U)
/*! MU2 - MU2 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_MU2(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_MU2_SHIFT)) & CLKCTL3_PSCCTL0_COMP_MU2_MASK)

#define CLKCTL3_PSCCTL0_COMP_OSTIMER_MASK        (0x80U)
#define CLKCTL3_PSCCTL0_COMP_OSTIMER_SHIFT       (7U)
/*! OSTIMER - OSTIMER Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_OSTIMER(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_OSTIMER_SHIFT)) & CLKCTL3_PSCCTL0_COMP_OSTIMER_MASK)

#define CLKCTL3_PSCCTL0_COMP_SEMA42_0_MASK       (0x100U)
#define CLKCTL3_PSCCTL0_COMP_SEMA42_0_SHIFT      (8U)
/*! SEMA42_0 - SEMA42_0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SEMA42_0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SEMA42_0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SEMA42_0_MASK)

#define CLKCTL3_PSCCTL0_COMP_SDADC0_MASK         (0x200U)
#define CLKCTL3_PSCCTL0_COMP_SDADC0_SHIFT        (9U)
/*! SDADC0 - SDADC0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SDADC0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SDADC0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SDADC0_MASK)

#define CLKCTL3_PSCCTL0_COMP_SARADC0_MASK        (0x400U)
#define CLKCTL3_PSCCTL0_COMP_SARADC0_SHIFT       (10U)
/*! SARADC0 - ADC0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SARADC0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SARADC0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SARADC0_MASK)

#define CLKCTL3_PSCCTL0_COMP_ACMP0_MASK          (0x800U)
#define CLKCTL3_PSCCTL0_COMP_ACMP0_SHIFT         (11U)
/*! ACMP0 - ACMP0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_ACMP0(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_ACMP0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_ACMP0_MASK)

#define CLKCTL3_PSCCTL0_COMP_MICFIL_MASK         (0x1000U)
#define CLKCTL3_PSCCTL0_COMP_MICFIL_SHIFT        (12U)
/*! MICFIL - MICFIL Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_MICFIL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_MICFIL_SHIFT)) & CLKCTL3_PSCCTL0_COMP_MICFIL_MASK)

#define CLKCTL3_PSCCTL0_COMP_GLIKEY4_MASK        (0x2000U)
#define CLKCTL3_PSCCTL0_COMP_GLIKEY4_SHIFT       (13U)
/*! GLIKEY4 - GLIKEY4 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_GLIKEY4(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_GLIKEY4_SHIFT)) & CLKCTL3_PSCCTL0_COMP_GLIKEY4_MASK)

#define CLKCTL3_PSCCTL0_COMP_DBG_RT700_MASK      (0x100000U)
#define CLKCTL3_PSCCTL0_COMP_DBG_RT700_SHIFT     (20U)
/*! DBG_RT700 - DBG_RT700 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_DBG_RT700(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_DBG_RT700_SHIFT)) & CLKCTL3_PSCCTL0_COMP_DBG_RT700_MASK)

#define CLKCTL3_PSCCTL0_COMP_SYSCON3_MASK        (0x200000U)
#define CLKCTL3_PSCCTL0_COMP_SYSCON3_SHIFT       (21U)
/*! SYSCON3 - SYSCON3 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SYSCON3(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SYSCON3_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SYSCON3_MASK)

#define CLKCTL3_PSCCTL0_COMP_IOPCTL1_MASK        (0x400000U)
#define CLKCTL3_PSCCTL0_COMP_IOPCTL1_SHIFT       (22U)
/*! IOPCTL1 - IOPCTL1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_IOPCTL1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_IOPCTL1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_IOPCTL1_MASK)

#define CLKCTL3_PSCCTL0_COMP_GLIKEY1_MASK        (0x800000U)
#define CLKCTL3_PSCCTL0_COMP_GLIKEY1_SHIFT       (23U)
/*! GLIKEY1 - GLIKEY1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_GLIKEY1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_GLIKEY1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_GLIKEY1_MASK)

#define CLKCTL3_PSCCTL0_COMP_LPI2C15_MASK        (0x1000000U)
#define CLKCTL3_PSCCTL0_COMP_LPI2C15_SHIFT       (24U)
/*! LPI2C15 - LPI2C15 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_LPI2C15(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_LPI2C15_SHIFT)) & CLKCTL3_PSCCTL0_COMP_LPI2C15_MASK)

#define CLKCTL3_PSCCTL0_COMP_MEDIA_ACCESS_RAM_ARBITER1_MASK (0x2000000U)
#define CLKCTL3_PSCCTL0_COMP_MEDIA_ACCESS_RAM_ARBITER1_SHIFT (25U)
/*! MEDIA_ACCESS_RAM_ARBITER1 - Media Access RAM Arbiter1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_MEDIA_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_MEDIA_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_MEDIA_ACCESS_RAM_ARBITER1_MASK)
/*! @} */

/*! @name PSCCTL0_COMP_SET - VDD1_SENSE Peripheral Clock Control 0 Set */
/*! @{ */

#define CLKCTL3_PSCCTL0_COMP_SET_CPU1_MASK       (0x1U)
#define CLKCTL3_PSCCTL0_COMP_SET_CPU1_SHIFT      (0U)
/*! CPU1 - CPU1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_CPU1(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_CPU1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_CPU1_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_MU0_MASK        (0x10U)
#define CLKCTL3_PSCCTL0_COMP_SET_MU0_SHIFT       (4U)
/*! MU0 - MU0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_MU0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_MU0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_MU0_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_MU1_MASK        (0x20U)
#define CLKCTL3_PSCCTL0_COMP_SET_MU1_SHIFT       (5U)
/*! MU1 - MU1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_MU1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_MU1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_MU1_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_MU2_MASK        (0x40U)
#define CLKCTL3_PSCCTL0_COMP_SET_MU2_SHIFT       (6U)
/*! MU2 - MU2 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_MU2(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_MU2_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_MU2_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_OSTIMER_MASK    (0x80U)
#define CLKCTL3_PSCCTL0_COMP_SET_OSTIMER_SHIFT   (7U)
/*! OSTIMER - OSTIMER Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_OSTIMER(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_OSTIMER_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_OSTIMER_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_SEMA42_0_MASK   (0x100U)
#define CLKCTL3_PSCCTL0_COMP_SET_SEMA42_0_SHIFT  (8U)
/*! SEMA42_0 - SEMA42_0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_SEMA42_0(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_SEMA42_0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_SEMA42_0_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_SDADC0_MASK     (0x200U)
#define CLKCTL3_PSCCTL0_COMP_SET_SDADC0_SHIFT    (9U)
/*! SDADC0 - SDADC0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_SDADC0(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_SDADC0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_SDADC0_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_SARADC0_MASK    (0x400U)
#define CLKCTL3_PSCCTL0_COMP_SET_SARADC0_SHIFT   (10U)
/*! SARADC0 - ADC0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_SARADC0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_SARADC0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_SARADC0_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_ACMP0_MASK      (0x800U)
#define CLKCTL3_PSCCTL0_COMP_SET_ACMP0_SHIFT     (11U)
/*! ACMP0 - ACMP0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_ACMP0(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_ACMP0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_ACMP0_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_MICFIL_MASK     (0x1000U)
#define CLKCTL3_PSCCTL0_COMP_SET_MICFIL_SHIFT    (12U)
/*! MICFIL - MICFIL Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_MICFIL(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_MICFIL_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_MICFIL_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_GLIKEY4_MASK    (0x2000U)
#define CLKCTL3_PSCCTL0_COMP_SET_GLIKEY4_SHIFT   (13U)
/*! GLIKEY4 - GLIKEY4 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_GLIKEY4(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_GLIKEY4_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_GLIKEY4_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_DBG_RT700_MASK  (0x100000U)
#define CLKCTL3_PSCCTL0_COMP_SET_DBG_RT700_SHIFT (20U)
/*! DBG_RT700 - DBG_RT700 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_DBG_RT700(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_DBG_RT700_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_DBG_RT700_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_SYSCON3_MASK    (0x200000U)
#define CLKCTL3_PSCCTL0_COMP_SET_SYSCON3_SHIFT   (21U)
/*! SYSCON3 - SYSCON3 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_SYSCON3(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_SYSCON3_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_SYSCON3_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_IOPCTL1_MASK    (0x400000U)
#define CLKCTL3_PSCCTL0_COMP_SET_IOPCTL1_SHIFT   (22U)
/*! IOPCTL1 - IOPCTL1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_IOPCTL1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_IOPCTL1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_IOPCTL1_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_GLIKEY1_MASK    (0x800000U)
#define CLKCTL3_PSCCTL0_COMP_SET_GLIKEY1_SHIFT   (23U)
/*! GLIKEY1 - GLIKEY1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_COMP_SET_GLIKEY1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_GLIKEY1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_GLIKEY1_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_LPI2C15_MASK    (0x1000000U)
#define CLKCTL3_PSCCTL0_COMP_SET_LPI2C15_SHIFT   (24U)
/*! LPI2C15 - LPI2C15 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL3_PSCCTL0_COMP_SET_LPI2C15(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_LPI2C15_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_LPI2C15_MASK)

#define CLKCTL3_PSCCTL0_COMP_SET_MEDIA_ACCESS_RAM_ARBITER1_MASK (0x2000000U)
#define CLKCTL3_PSCCTL0_COMP_SET_MEDIA_ACCESS_RAM_ARBITER1_SHIFT (25U)
/*! MEDIA_ACCESS_RAM_ARBITER1 - Media Access RAM Arbiter1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL3_PSCCTL0_COMP_SET_MEDIA_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_SET_MEDIA_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_SET_MEDIA_ACCESS_RAM_ARBITER1_MASK)
/*! @} */

/*! @name PSCCTL0_COMP_CLR - VDD1_SENSE Peripheral Clock Control 0 Clear */
/*! @{ */

#define CLKCTL3_PSCCTL0_COMP_CLR_CPU1_MASK       (0x1U)
#define CLKCTL3_PSCCTL0_COMP_CLR_CPU1_SHIFT      (0U)
/*! CPU1 - CPU1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_CPU1(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_CPU1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_CPU1_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_MU0_MASK        (0x10U)
#define CLKCTL3_PSCCTL0_COMP_CLR_MU0_SHIFT       (4U)
/*! MU0 - MU0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_MU0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_MU0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_MU0_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_MU1_MASK        (0x20U)
#define CLKCTL3_PSCCTL0_COMP_CLR_MU1_SHIFT       (5U)
/*! MU1 - MU1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_MU1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_MU1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_MU1_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_MU2_MASK        (0x40U)
#define CLKCTL3_PSCCTL0_COMP_CLR_MU2_SHIFT       (6U)
/*! MU2 - MU2 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_MU2(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_MU2_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_MU2_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_OSTIMER_MASK    (0x80U)
#define CLKCTL3_PSCCTL0_COMP_CLR_OSTIMER_SHIFT   (7U)
/*! OSTIMER - OSTIMER Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_OSTIMER(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_OSTIMER_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_OSTIMER_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_SEMA42_0_MASK   (0x100U)
#define CLKCTL3_PSCCTL0_COMP_CLR_SEMA42_0_SHIFT  (8U)
/*! SEMA42_0 - SEMA42_0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_SEMA42_0(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_SEMA42_0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_SEMA42_0_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_SDADC0_MASK     (0x200U)
#define CLKCTL3_PSCCTL0_COMP_CLR_SDADC0_SHIFT    (9U)
/*! SDADC0 - SDADC0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_SDADC0(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_SDADC0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_SDADC0_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_SARADC0_MASK    (0x400U)
#define CLKCTL3_PSCCTL0_COMP_CLR_SARADC0_SHIFT   (10U)
/*! SARADC0 - ADC0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_SARADC0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_SARADC0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_SARADC0_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_ACMP0_MASK      (0x800U)
#define CLKCTL3_PSCCTL0_COMP_CLR_ACMP0_SHIFT     (11U)
/*! ACMP0 - ACMP0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_ACMP0(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_ACMP0_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_ACMP0_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_MICFIL_MASK     (0x1000U)
#define CLKCTL3_PSCCTL0_COMP_CLR_MICFIL_SHIFT    (12U)
/*! MICFIL - MICFIL Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_MICFIL(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_MICFIL_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_MICFIL_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY4_MASK    (0x2000U)
#define CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY4_SHIFT   (13U)
/*! GLIKEY4 - GLIKEY4 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY4(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY4_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY4_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_DBG_RT700_MASK  (0x100000U)
#define CLKCTL3_PSCCTL0_COMP_CLR_DBG_RT700_SHIFT (20U)
/*! DBG_RT700 - DBG_RT700 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_DBG_RT700(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_DBG_RT700_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_DBG_RT700_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_SYSCON3_MASK    (0x200000U)
#define CLKCTL3_PSCCTL0_COMP_CLR_SYSCON3_SHIFT   (21U)
/*! SYSCON3 - SYSCON3 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_SYSCON3(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_SYSCON3_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_SYSCON3_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_IOPCTL1_MASK    (0x400000U)
#define CLKCTL3_PSCCTL0_COMP_CLR_IOPCTL1_SHIFT   (22U)
/*! IOPCTL1 - IOPCTL1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_IOPCTL1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_IOPCTL1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_IOPCTL1_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY1_MASK    (0x800000U)
#define CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY1_SHIFT   (23U)
/*! GLIKEY1 - GLIKEY1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_GLIKEY1_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_LPI2C15_MASK    (0x1000000U)
#define CLKCTL3_PSCCTL0_COMP_CLR_LPI2C15_SHIFT   (24U)
/*! LPI2C15 - LPI2C15 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_LPI2C15(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_LPI2C15_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_LPI2C15_MASK)

#define CLKCTL3_PSCCTL0_COMP_CLR_MEDIA_ACCESS_RAM_ARBITER1_MASK (0x2000000U)
#define CLKCTL3_PSCCTL0_COMP_CLR_MEDIA_ACCESS_RAM_ARBITER1_SHIFT (25U)
/*! MEDIA_ACCESS_RAM_ARBITER1 - Media Access RAM Arbiter1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL3_PSCCTL0_COMP_CLR_MEDIA_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_COMP_CLR_MEDIA_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL3_PSCCTL0_COMP_CLR_MEDIA_ACCESS_RAM_ARBITER1_MASK)
/*! @} */

/*! @name ONE_SRC_CLKSLICE_ENABLE_COMP - One Source Clock Slice Enable for VDD2_COMP CPU */
/*! @{ */

#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_RTC_FCLK_EN_MASK (0x1U)
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_RTC_FCLK_EN_SHIFT (0U)
/*! RTC_FCLK_EN - RTC Functional Clock Gating Enable
 *  0b0..Gates RTC functional clock.
 *  0b1..Enables RTC functional clock.
 */
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_RTC_FCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_RTC_FCLK_EN_SHIFT)) & CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_RTC_FCLK_EN_MASK)

#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET2_FCLK_EN_MASK (0x2U)
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET2_FCLK_EN_SHIFT (1U)
/*! dGDET2_FCLK_EN - dGDET2 Functional Clock Gating Enable
 *  0b0..Gates dGDET2 functional clock.
 *  0b1..Enables dGDET2 functional clock.
 */
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET2_FCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET2_FCLK_EN_SHIFT)) & CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET2_FCLK_EN_MASK)

#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET3_FCLK_EN_MASK (0x4U)
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET3_FCLK_EN_SHIFT (2U)
/*! dGDET3_FCLK_EN - dGDET3 Functional Clock Gating Enable
 *  0b0..Gates dGDET3 functional clock.
 *  0b1..Enables dGDET3 functional clock.
 */
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET3_FCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET3_FCLK_EN_SHIFT)) & CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_COMP_DGDET3_FCLK_EN_MASK)
/*! @} */

/*! @name LPOSCCTL0 - Low Power Oscillator Control 0 */
/*! @{ */

#define CLKCTL3_LPOSCCTL0_CLKRDY_MASK            (0x80000000U)
#define CLKCTL3_LPOSCCTL0_CLKRDY_SHIFT           (31U)
/*! CLKRDY - LPOSC Clock Ready
 *  0b0..LPOSC clock is not ready.
 *  0b1..LPOSC clock is ready.
 */
#define CLKCTL3_LPOSCCTL0_CLKRDY(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_LPOSCCTL0_CLKRDY_SHIFT)) & CLKCTL3_LPOSCCTL0_CLKRDY_MASK)
/*! @} */

/*! @name SENSEBASECLKSEL - VDD1_SENSE Base Clock Select Source */
/*! @{ */

#define CLKCTL3_SENSEBASECLKSEL_SEL_MASK         (0x3U)
#define CLKCTL3_SENSEBASECLKSEL_SEL_SHIFT        (0U)
/*! SEL - Clock Source Selection
 *  0b00..fro1_div3
 *  0b01..fro1_max
 *  0b10..fro2_div3
 *  0b11..1m_lposc
 */
#define CLKCTL3_SENSEBASECLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSEBASECLKSEL_SEL_SHIFT)) & CLKCTL3_SENSEBASECLKSEL_SEL_MASK)
/*! @} */

/*! @name FRO2CLKSTATUS - FRO_TUNER2 Clock Status */
/*! @{ */

#define CLKCTL3_FRO2CLKSTATUS_CLK_OK_MASK        (0x1U)
#define CLKCTL3_FRO2CLKSTATUS_CLK_OK_SHIFT       (0U)
/*! CLK_OK - FRO_TUNER2 Clock OK
 *  0b0..FRO_TUNER2 clock has not yet reached its final frequency.
 *  0b1..FRO_TUNER2 clock has reached its final frequency.
 */
#define CLKCTL3_FRO2CLKSTATUS_CLK_OK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_FRO2CLKSTATUS_CLK_OK_SHIFT)) & CLKCTL3_FRO2CLKSTATUS_CLK_OK_MASK)
/*! @} */

/*! @name FRO2MAXDOMAINEN - FRO2MAX Clock Domain Enable */
/*! @{ */

#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_CMPT_MASK (0x1U)
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_CMPT_SHIFT (0U)
/*! FRO2MAX_OF_CMPT - Enable fro2_max Clock Control of VDD2_COMP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_CMPT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_CMPT_SHIFT)) & CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_CMPT_MASK)

#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_SENSE_MASK (0x2U)
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_SENSE_SHIFT (1U)
/*! FRO2MAX_OF_SENSE - Enable fro2_max Clock Control of VDD1_SENSE Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_SENSE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_SENSE_SHIFT)) & CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_SENSE_MASK)

#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_DSP_MASK (0x4U)
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_DSP_SHIFT (2U)
/*! FRO2MAX_OF_VDD2_DSP - Enable fro2_max Clock Control of VDD2_DSP Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_DSP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_DSP_SHIFT)) & CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_DSP_MASK)

#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MD2_MASK (0x8U)
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MD2_SHIFT (3U)
/*! FRO2MAX_OF_MD2 - Enable fro2_max Clock Control of VDD2_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MD2_SHIFT)) & CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MD2_MASK)

#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MDN_MASK (0x10U)
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MDN_SHIFT (4U)
/*! FRO2MAX_OF_MDN - Enable fro2_max Clock Control of VDDN_MEDIA Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MDN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MDN_SHIFT)) & CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_MDN_MASK)

#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_COM_MASK (0x20U)
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_COM_SHIFT (5U)
/*! FRO2MAX_OF_VDD2_COM - Enable fro2_max Clock Control of VDD2_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_COM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_COM_SHIFT)) & CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_VDD2_COM_MASK)

#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_COMN_MASK (0x40U)
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_COMN_SHIFT (6U)
/*! FRO2MAX_OF_COMN - Enable fro2_max Clock Control of VDDN_COM Domain
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_COMN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_COMN_SHIFT)) & CLKCTL3_FRO2MAXDOMAINEN_FRO2MAX_OF_COMN_MASK)
/*! @} */

/*! @name SENSEMAINCLKDIV - VDD1_SENSE Main Clock Divider */
/*! @{ */

#define CLKCTL3_SENSEMAINCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL3_SENSEMAINCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL3_SENSEMAINCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSEMAINCLKDIV_DIV_SHIFT)) & CLKCTL3_SENSEMAINCLKDIV_DIV_MASK)

#define CLKCTL3_SENSEMAINCLKDIV_BUSY_MASK        (0x10000000U)
#define CLKCTL3_SENSEMAINCLKDIV_BUSY_SHIFT       (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_SENSEMAINCLKDIV_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSEMAINCLKDIV_BUSY_SHIFT)) & CLKCTL3_SENSEMAINCLKDIV_BUSY_MASK)

#define CLKCTL3_SENSEMAINCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL3_SENSEMAINCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL3_SENSEMAINCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSEMAINCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_SENSEMAINCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name MAINCLKSEL - VDD1_SENSE Main Clock Source Select */
/*! @{ */

#define CLKCTL3_MAINCLKSEL_SEL_MASK              (0x3U)
#define CLKCTL3_MAINCLKSEL_SEL_SHIFT             (0U)
/*! SEL - VDD1_SENSE Main Clock Source Select
 *  0b00..baseclk_sense
 *  0b01..fro2_max
 *  0b10..audio_pll_pfd3
 *  0b11..fro1_max
 */
#define CLKCTL3_MAINCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL3_MAINCLKSEL_SEL_SHIFT)) & CLKCTL3_MAINCLKSEL_SEL_MASK)
/*! @} */

/*! @name SENSERAMCLKSEL - VDD1_SENSE RAM Clock Source Select */
/*! @{ */

#define CLKCTL3_SENSERAMCLKSEL_SEL_MASK          (0x3U)
#define CLKCTL3_SENSERAMCLKSEL_SEL_SHIFT         (0U)
/*! SEL - VDD1_SENSE RAM Clock Source Select
 *  0b00..baseclk_sense
 *  0b01..fro2_max
 *  0b10..audio_pll_pfd2
 *  0b11..fro1_max
 */
#define CLKCTL3_SENSERAMCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSERAMCLKSEL_SEL_SHIFT)) & CLKCTL3_SENSERAMCLKSEL_SEL_MASK)
/*! @} */

/*! @name SENSERAMCLKDIV - VDD1_SENSE RAM Clock Divider */
/*! @{ */

#define CLKCTL3_SENSERAMCLKDIV_DIV_MASK          (0xFFU)
#define CLKCTL3_SENSERAMCLKDIV_DIV_SHIFT         (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL3_SENSERAMCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSERAMCLKDIV_DIV_SHIFT)) & CLKCTL3_SENSERAMCLKDIV_DIV_MASK)

#define CLKCTL3_SENSERAMCLKDIV_BUSY_MASK         (0x10000000U)
#define CLKCTL3_SENSERAMCLKDIV_BUSY_SHIFT        (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_SENSERAMCLKDIV_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSERAMCLKDIV_BUSY_SHIFT)) & CLKCTL3_SENSERAMCLKDIV_BUSY_MASK)

#define CLKCTL3_SENSERAMCLKDIV_REQFLAG_MASK      (0x80000000U)
#define CLKCTL3_SENSERAMCLKDIV_REQFLAG_SHIFT     (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_SENSERAMCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSERAMCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_SENSERAMCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name OSTIMERFCLKSEL - OSTIMER Functional Clock Source Select */
/*! @{ */

#define CLKCTL3_OSTIMERFCLKSEL_SEL_MASK          (0x3U)
#define CLKCTL3_OSTIMERFCLKSEL_SEL_SHIFT         (0U)
/*! SEL - Clock Source Select
 *  0b00..baseclk_sense
 *  0b01..wake32k_clk
 *  0b10..1m_lposc
 *  0b11..osc_clk
 */
#define CLKCTL3_OSTIMERFCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_OSTIMERFCLKSEL_SEL_SHIFT)) & CLKCTL3_OSTIMERFCLKSEL_SEL_MASK)

#define CLKCTL3_OSTIMERFCLKSEL_SEL_EN_MASK       (0x4U)
#define CLKCTL3_OSTIMERFCLKSEL_SEL_EN_SHIFT      (2U)
/*! SEL_EN - Clock MUX Output Enable
 *  0b0..Gates output of clock mux.
 *  0b1..Enables output of clock mux.
 */
#define CLKCTL3_OSTIMERFCLKSEL_SEL_EN(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_OSTIMERFCLKSEL_SEL_EN_SHIFT)) & CLKCTL3_OSTIMERFCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name OSTIMERFCLKDIV - OSTIMER Functional Clock Divider */
/*! @{ */

#define CLKCTL3_OSTIMERFCLKDIV_DIV_MASK          (0xFFU)
#define CLKCTL3_OSTIMERFCLKDIV_DIV_SHIFT         (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL3_OSTIMERFCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_OSTIMERFCLKDIV_DIV_SHIFT)) & CLKCTL3_OSTIMERFCLKDIV_DIV_MASK)

#define CLKCTL3_OSTIMERFCLKDIV_BUSY_MASK         (0x10000000U)
#define CLKCTL3_OSTIMERFCLKDIV_BUSY_SHIFT        (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_OSTIMERFCLKDIV_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_OSTIMERFCLKDIV_BUSY_SHIFT)) & CLKCTL3_OSTIMERFCLKDIV_BUSY_MASK)

#define CLKCTL3_OSTIMERFCLKDIV_RESET_MASK        (0x20000000U)
#define CLKCTL3_OSTIMERFCLKDIV_RESET_SHIFT       (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL3_OSTIMERFCLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_OSTIMERFCLKDIV_RESET_SHIFT)) & CLKCTL3_OSTIMERFCLKDIV_RESET_MASK)

#define CLKCTL3_OSTIMERFCLKDIV_HALT_MASK         (0x40000000U)
#define CLKCTL3_OSTIMERFCLKDIV_HALT_SHIFT        (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL3_OSTIMERFCLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_OSTIMERFCLKDIV_HALT_SHIFT)) & CLKCTL3_OSTIMERFCLKDIV_HALT_MASK)

#define CLKCTL3_OSTIMERFCLKDIV_REQFLAG_MASK      (0x80000000U)
#define CLKCTL3_OSTIMERFCLKDIV_REQFLAG_SHIFT     (31U)
/*! REQFLAG - Request Flag
 *  0b0..The divider change has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_OSTIMERFCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_OSTIMERFCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_OSTIMERFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SDADCFCLKSEL - SDADC Functional Clock Source Select */
/*! @{ */

#define CLKCTL3_SDADCFCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL3_SDADCFCLKSEL_SEL_SHIFT           (0U)
/*! SEL - SDADC Functional Clock Source Select
 *  0b00..baseclk_sense
 *  0b01..fro2_div8
 *  0b10..audio_pll_vco
 *  0b11..audio_clk
 */
#define CLKCTL3_SDADCFCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SDADCFCLKSEL_SEL_SHIFT)) & CLKCTL3_SDADCFCLKSEL_SEL_MASK)

#define CLKCTL3_SDADCFCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL3_SDADCFCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock MUX Output Enable
 *  0b0..Gates output of clock mux.
 *  0b1..Enables output of clock mux.
 */
#define CLKCTL3_SDADCFCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SDADCFCLKSEL_SEL_EN_SHIFT)) & CLKCTL3_SDADCFCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name SDADCFCLKDIV - SDADC Functional Clock Divider */
/*! @{ */

#define CLKCTL3_SDADCFCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL3_SDADCFCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Selection */
#define CLKCTL3_SDADCFCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SDADCFCLKDIV_DIV_SHIFT)) & CLKCTL3_SDADCFCLKDIV_DIV_MASK)

#define CLKCTL3_SDADCFCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL3_SDADCFCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_SDADCFCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SDADCFCLKDIV_BUSY_SHIFT)) & CLKCTL3_SDADCFCLKDIV_BUSY_MASK)

#define CLKCTL3_SDADCFCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL3_SDADCFCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL3_SDADCFCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SDADCFCLKDIV_RESET_SHIFT)) & CLKCTL3_SDADCFCLKDIV_RESET_MASK)

#define CLKCTL3_SDADCFCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL3_SDADCFCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL3_SDADCFCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SDADCFCLKDIV_HALT_SHIFT)) & CLKCTL3_SDADCFCLKDIV_HALT_MASK)

#define CLKCTL3_SDADCFCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL3_SDADCFCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_SDADCFCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SDADCFCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_SDADCFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SARADCFCLKSEL - ADC0 (SARADC) Functional Clock Source Select */
/*! @{ */

#define CLKCTL3_SARADCFCLKSEL_SEL_MASK           (0x3U)
#define CLKCTL3_SARADCFCLKSEL_SEL_SHIFT          (0U)
/*! SEL - Clock Source Select
 *  0b00..baseclk_sense
 *  0b01..main_pll_pfd1
 *  0b10..fro2_max
 *  0b11..osc_clk
 */
#define CLKCTL3_SARADCFCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SARADCFCLKSEL_SEL_SHIFT)) & CLKCTL3_SARADCFCLKSEL_SEL_MASK)

#define CLKCTL3_SARADCFCLKSEL_SEL_EN_MASK        (0x4U)
#define CLKCTL3_SARADCFCLKSEL_SEL_EN_SHIFT       (2U)
/*! SEL_EN - Clock MUX Output Enable
 *  0b0..Gates output of clock mux.
 *  0b1..Enables output of clock mux.
 */
#define CLKCTL3_SARADCFCLKSEL_SEL_EN(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SARADCFCLKSEL_SEL_EN_SHIFT)) & CLKCTL3_SARADCFCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name SARADCFCLKDIV - ADC0 (SARADC) Functional Clock Divider */
/*! @{ */

#define CLKCTL3_SARADCFCLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL3_SARADCFCLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock Divider Value Selection */
#define CLKCTL3_SARADCFCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SARADCFCLKDIV_DIV_SHIFT)) & CLKCTL3_SARADCFCLKDIV_DIV_MASK)

#define CLKCTL3_SARADCFCLKDIV_BUSY_MASK          (0x10000000U)
#define CLKCTL3_SARADCFCLKDIV_BUSY_SHIFT         (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_SARADCFCLKDIV_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SARADCFCLKDIV_BUSY_SHIFT)) & CLKCTL3_SARADCFCLKDIV_BUSY_MASK)

#define CLKCTL3_SARADCFCLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL3_SARADCFCLKDIV_RESET_SHIFT        (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL3_SARADCFCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SARADCFCLKDIV_RESET_SHIFT)) & CLKCTL3_SARADCFCLKDIV_RESET_MASK)

#define CLKCTL3_SARADCFCLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL3_SARADCFCLKDIV_HALT_SHIFT         (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL3_SARADCFCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SARADCFCLKDIV_HALT_SHIFT)) & CLKCTL3_SARADCFCLKDIV_HALT_MASK)

#define CLKCTL3_SARADCFCLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL3_SARADCFCLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_SARADCFCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SARADCFCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_SARADCFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name WAKE32KCLKSEL - Wake 32 kHZ Clock Source Select */
/*! @{ */

#define CLKCTL3_WAKE32KCLKSEL_SEL_MASK           (0x3U)
#define CLKCTL3_WAKE32KCLKSEL_SEL_SHIFT          (0U)
/*! SEL - Clock Source Select
 *  0b00..osc_32k
 *  0b01..lp_32k (1m_lposc clock divided by 32)
 *  0b10..Reserved
 *  0b11..Tied to logic 0. This may be selected to reduce power when no output is needed.
 */
#define CLKCTL3_WAKE32KCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKSEL_SEL_SHIFT)) & CLKCTL3_WAKE32KCLKSEL_SEL_MASK)
/*! @} */

/*! @name WAKE32KCLKDIV - Wake 32kHZ Clock Divider */
/*! @{ */

#define CLKCTL3_WAKE32KCLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL3_WAKE32KCLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL3_WAKE32KCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_DIV_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_DIV_MASK)

#define CLKCTL3_WAKE32KCLKDIV_BUSY_MASK          (0x10000000U)
#define CLKCTL3_WAKE32KCLKDIV_BUSY_SHIFT         (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_WAKE32KCLKDIV_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_BUSY_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_BUSY_MASK)

#define CLKCTL3_WAKE32KCLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL3_WAKE32KCLKDIV_RESET_SHIFT        (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL3_WAKE32KCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_RESET_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_RESET_MASK)

#define CLKCTL3_WAKE32KCLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL3_WAKE32KCLKDIV_HALT_SHIFT         (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL3_WAKE32KCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_HALT_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_HALT_MASK)

#define CLKCTL3_WAKE32KCLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL3_WAKE32KCLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_WAKE32KCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name MICFILFCLKSEL - MICFIL Functional Clock Source Select */
/*! @{ */

#define CLKCTL3_MICFILFCLKSEL_SEL_MASK           (0x3U)
#define CLKCTL3_MICFILFCLKSEL_SEL_SHIFT          (0U)
/*! SEL - Clock Source Select
 *  0b00..baseclk_sense
 *  0b01..audio_pll_pfd3
 *  0b10..fro2_max
 *  0b11..audio_clk
 */
#define CLKCTL3_MICFILFCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_MICFILFCLKSEL_SEL_SHIFT)) & CLKCTL3_MICFILFCLKSEL_SEL_MASK)

#define CLKCTL3_MICFILFCLKSEL_SEL_EN_MASK        (0x4U)
#define CLKCTL3_MICFILFCLKSEL_SEL_EN_SHIFT       (2U)
/*! SEL_EN - Clock MUX Output Enable
 *  0b0..Gates output of clock mux.
 *  0b1..Enables output of clock mux.
 */
#define CLKCTL3_MICFILFCLKSEL_SEL_EN(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_MICFILFCLKSEL_SEL_EN_SHIFT)) & CLKCTL3_MICFILFCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name MICFILFCLKDIV - MICFIL Functional Clock Divider */
/*! @{ */

#define CLKCTL3_MICFILFCLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL3_MICFILFCLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock Divider Value */
#define CLKCTL3_MICFILFCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_MICFILFCLKDIV_DIV_SHIFT)) & CLKCTL3_MICFILFCLKDIV_DIV_MASK)

#define CLKCTL3_MICFILFCLKDIV_BUSY_MASK          (0x10000000U)
#define CLKCTL3_MICFILFCLKDIV_BUSY_SHIFT         (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_MICFILFCLKDIV_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_MICFILFCLKDIV_BUSY_SHIFT)) & CLKCTL3_MICFILFCLKDIV_BUSY_MASK)

#define CLKCTL3_MICFILFCLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL3_MICFILFCLKDIV_RESET_SHIFT        (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL3_MICFILFCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_MICFILFCLKDIV_RESET_SHIFT)) & CLKCTL3_MICFILFCLKDIV_RESET_MASK)

#define CLKCTL3_MICFILFCLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL3_MICFILFCLKDIV_HALT_SHIFT         (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL3_MICFILFCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_MICFILFCLKDIV_HALT_SHIFT)) & CLKCTL3_MICFILFCLKDIV_HALT_MASK)

#define CLKCTL3_MICFILFCLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL3_MICFILFCLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Request Flag
 *  0b0..The divider change has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_MICFILFCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_MICFILFCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_MICFILFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name LPI2C15FCLKSEL - LPI2C15 Functional Clock Source Select */
/*! @{ */

#define CLKCTL3_LPI2C15FCLKSEL_SEL_MASK          (0x3U)
#define CLKCTL3_LPI2C15FCLKSEL_SEL_SHIFT         (0U)
/*! SEL - LPI2C15 Clock Source Select
 *  0b00..baseclk_sense
 *  0b01..fro1_max
 *  0b10..fro1_div2
 *  0b11..fro2_max
 */
#define CLKCTL3_LPI2C15FCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_LPI2C15FCLKSEL_SEL_SHIFT)) & CLKCTL3_LPI2C15FCLKSEL_SEL_MASK)

#define CLKCTL3_LPI2C15FCLKSEL_SEL_EN_MASK       (0x4U)
#define CLKCTL3_LPI2C15FCLKSEL_SEL_EN_SHIFT      (2U)
/*! SEL_EN - Clock MUX Output Enable
 *  0b0..Gates output of clock mux.
 *  0b1..Enables output of clock mux.
 */
#define CLKCTL3_LPI2C15FCLKSEL_SEL_EN(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_LPI2C15FCLKSEL_SEL_EN_SHIFT)) & CLKCTL3_LPI2C15FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name LPI2C15FCLKDIV - LPI2C15 Functional Clock Divider */
/*! @{ */

#define CLKCTL3_LPI2C15FCLKDIV_DIV_MASK          (0xFFU)
#define CLKCTL3_LPI2C15FCLKDIV_DIV_SHIFT         (0U)
/*! DIV - LPI2C15 Clock Divider Value */
#define CLKCTL3_LPI2C15FCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_LPI2C15FCLKDIV_DIV_SHIFT)) & CLKCTL3_LPI2C15FCLKDIV_DIV_MASK)

#define CLKCTL3_LPI2C15FCLKDIV_BUSY_MASK         (0x10000000U)
#define CLKCTL3_LPI2C15FCLKDIV_BUSY_SHIFT        (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_LPI2C15FCLKDIV_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_LPI2C15FCLKDIV_BUSY_SHIFT)) & CLKCTL3_LPI2C15FCLKDIV_BUSY_MASK)

#define CLKCTL3_LPI2C15FCLKDIV_RESET_MASK        (0x20000000U)
#define CLKCTL3_LPI2C15FCLKDIV_RESET_SHIFT       (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL3_LPI2C15FCLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_LPI2C15FCLKDIV_RESET_SHIFT)) & CLKCTL3_LPI2C15FCLKDIV_RESET_MASK)

#define CLKCTL3_LPI2C15FCLKDIV_HALT_MASK         (0x40000000U)
#define CLKCTL3_LPI2C15FCLKDIV_HALT_SHIFT        (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL3_LPI2C15FCLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_LPI2C15FCLKDIV_HALT_SHIFT)) & CLKCTL3_LPI2C15FCLKDIV_HALT_MASK)

#define CLKCTL3_LPI2C15FCLKDIV_REQFLAG_MASK      (0x80000000U)
#define CLKCTL3_LPI2C15FCLKDIV_REQFLAG_SHIFT     (31U)
/*! REQFLAG - Request Flag
 *  0b0..The Divider change has been finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value is being changed.
 */
#define CLKCTL3_LPI2C15FCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_LPI2C15FCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_LPI2C15FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name CLKOUTCLKSEL - CLKOUT_VDD1 Clock Source Select */
/*! @{ */

#define CLKCTL3_CLKOUTCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL3_CLKOUTCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Clock Source Select
 *  0b00..baseclk_sense
 *  0b01..audio_pll_pfd3
 *  0b10..fro2_max
 *  0b11..fro1_max
 */
#define CLKCTL3_CLKOUTCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_CLKOUTCLKSEL_SEL_SHIFT)) & CLKCTL3_CLKOUTCLKSEL_SEL_MASK)

#define CLKCTL3_CLKOUTCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL3_CLKOUTCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates output of clock mux.
 *  0b1..Enables output of clock mux.
 */
#define CLKCTL3_CLKOUTCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_CLKOUTCLKSEL_SEL_EN_SHIFT)) & CLKCTL3_CLKOUTCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name CLKOUTCLKDIV - CLKOUT_VDD1 Clock Divider */
/*! @{ */

#define CLKCTL3_CLKOUTCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL3_CLKOUTCLKDIV_DIV_SHIFT           (0U)
/*! DIV - CLKOUT_VDD1 Clock Divider */
#define CLKCTL3_CLKOUTCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_CLKOUTCLKDIV_DIV_SHIFT)) & CLKCTL3_CLKOUTCLKDIV_DIV_MASK)

#define CLKCTL3_CLKOUTCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL3_CLKOUTCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT_VDD1 is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_CLKOUTCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_CLKOUTCLKDIV_BUSY_SHIFT)) & CLKCTL3_CLKOUTCLKDIV_BUSY_MASK)

#define CLKCTL3_CLKOUTCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL3_CLKOUTCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Divider Counter Reset
 */
#define CLKCTL3_CLKOUTCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_CLKOUTCLKDIV_RESET_SHIFT)) & CLKCTL3_CLKOUTCLKDIV_RESET_MASK)

#define CLKCTL3_CLKOUTCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL3_CLKOUTCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL3_CLKOUTCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL3_CLKOUTCLKDIV_HALT_SHIFT)) & CLKCTL3_CLKOUTCLKDIV_HALT_MASK)

#define CLKCTL3_CLKOUTCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL3_CLKOUTCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL3_CLKOUTCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_CLKOUTCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_CLKOUTCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name PSCCTL0_SENS - VDD1_SENSE Peripheral Clock Control 0 */
/*! @{ */

#define CLKCTL3_PSCCTL0_SENS_MU0_MASK            (0x10U)
#define CLKCTL3_PSCCTL0_SENS_MU0_SHIFT           (4U)
/*! MU0 - MU0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_MU0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_MU0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_MU0_MASK)

#define CLKCTL3_PSCCTL0_SENS_MU1_MASK            (0x20U)
#define CLKCTL3_PSCCTL0_SENS_MU1_SHIFT           (5U)
/*! MU1 - MU1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_MU1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_MU1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_MU1_MASK)

#define CLKCTL3_PSCCTL0_SENS_MU2_MASK            (0x40U)
#define CLKCTL3_PSCCTL0_SENS_MU2_SHIFT           (6U)
/*! MU2 - MU2 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_MU2(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_MU2_SHIFT)) & CLKCTL3_PSCCTL0_SENS_MU2_MASK)

#define CLKCTL3_PSCCTL0_SENS_OSTIMER_MASK        (0x80U)
#define CLKCTL3_PSCCTL0_SENS_OSTIMER_SHIFT       (7U)
/*! OSTIMER - OSTIMER Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_OSTIMER(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_OSTIMER_SHIFT)) & CLKCTL3_PSCCTL0_SENS_OSTIMER_MASK)

#define CLKCTL3_PSCCTL0_SENS_SEMA42_0_MASK       (0x100U)
#define CLKCTL3_PSCCTL0_SENS_SEMA42_0_SHIFT      (8U)
/*! SEMA42_0 - SEMA42_0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SEMA42_0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SEMA42_0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SEMA42_0_MASK)

#define CLKCTL3_PSCCTL0_SENS_SDADC0_MASK         (0x200U)
#define CLKCTL3_PSCCTL0_SENS_SDADC0_SHIFT        (9U)
/*! SDADC0 - SDADC0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SDADC0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SDADC0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SDADC0_MASK)

#define CLKCTL3_PSCCTL0_SENS_SARADC0_MASK        (0x400U)
#define CLKCTL3_PSCCTL0_SENS_SARADC0_SHIFT       (10U)
/*! SARADC0 - ADC0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SARADC0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SARADC0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SARADC0_MASK)

#define CLKCTL3_PSCCTL0_SENS_ACMP0_MASK          (0x800U)
#define CLKCTL3_PSCCTL0_SENS_ACMP0_SHIFT         (11U)
/*! ACMP0 - ACMP0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_ACMP0(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_ACMP0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_ACMP0_MASK)

#define CLKCTL3_PSCCTL0_SENS_MICFIL_MASK         (0x1000U)
#define CLKCTL3_PSCCTL0_SENS_MICFIL_SHIFT        (12U)
/*! MICFIL - MICFIL Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_MICFIL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_MICFIL_SHIFT)) & CLKCTL3_PSCCTL0_SENS_MICFIL_MASK)

#define CLKCTL3_PSCCTL0_SENS_GLIKEY4_MASK        (0x2000U)
#define CLKCTL3_PSCCTL0_SENS_GLIKEY4_SHIFT       (13U)
/*! GLIKEY4 - GLIKEY4 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_GLIKEY4(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_GLIKEY4_SHIFT)) & CLKCTL3_PSCCTL0_SENS_GLIKEY4_MASK)

#define CLKCTL3_PSCCTL0_SENS_DBG_RT700_MASK      (0x100000U)
#define CLKCTL3_PSCCTL0_SENS_DBG_RT700_SHIFT     (20U)
/*! DBG_RT700 - DBG_RT700 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_DBG_RT700(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_DBG_RT700_SHIFT)) & CLKCTL3_PSCCTL0_SENS_DBG_RT700_MASK)

#define CLKCTL3_PSCCTL0_SENS_SYSCON3_MASK        (0x200000U)
#define CLKCTL3_PSCCTL0_SENS_SYSCON3_SHIFT       (21U)
/*! SYSCON3 - SYSCON3 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SYSCON3(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SYSCON3_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SYSCON3_MASK)

#define CLKCTL3_PSCCTL0_SENS_IOPCTL1_MASK        (0x400000U)
#define CLKCTL3_PSCCTL0_SENS_IOPCTL1_SHIFT       (22U)
/*! IOPCTL1 - IOPCTL1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_IOPCTL1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_IOPCTL1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_IOPCTL1_MASK)

#define CLKCTL3_PSCCTL0_SENS_GLIKEY1_MASK        (0x800000U)
#define CLKCTL3_PSCCTL0_SENS_GLIKEY1_SHIFT       (23U)
/*! GLIKEY1 - GLIKEY1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_GLIKEY1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_GLIKEY1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_GLIKEY1_MASK)

#define CLKCTL3_PSCCTL0_SENS_LPI2C15_MASK        (0x1000000U)
#define CLKCTL3_PSCCTL0_SENS_LPI2C15_SHIFT       (24U)
/*! LPI2C15 - LPI2C15 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_LPI2C15(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_LPI2C15_SHIFT)) & CLKCTL3_PSCCTL0_SENS_LPI2C15_MASK)

#define CLKCTL3_PSCCTL0_SENS_MEDIA_ACCESS_RAM_ARBITER1_MASK (0x2000000U)
#define CLKCTL3_PSCCTL0_SENS_MEDIA_ACCESS_RAM_ARBITER1_SHIFT (25U)
/*! MEDIA_ACCESS_RAM_ARBITER1 - Media Access RAM Arbiter1 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_MEDIA_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_MEDIA_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_MEDIA_ACCESS_RAM_ARBITER1_MASK)
/*! @} */

/*! @name PSCCTL0_SENS_SET - VDD1_SENSE Peripheral Clock Control 0 Set */
/*! @{ */

#define CLKCTL3_PSCCTL0_SENS_SET_CPU1_MASK       (0x1U)
#define CLKCTL3_PSCCTL0_SENS_SET_CPU1_SHIFT      (0U)
/*! CPU1 - CPU1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_CPU1(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_CPU1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_CPU1_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_MU0_MASK        (0x10U)
#define CLKCTL3_PSCCTL0_SENS_SET_MU0_SHIFT       (4U)
/*! MU0 - MU0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_MU0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_MU0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_MU0_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_MU1_MASK        (0x20U)
#define CLKCTL3_PSCCTL0_SENS_SET_MU1_SHIFT       (5U)
/*! MU1 - MU1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_MU1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_MU1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_MU1_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_MU2_MASK        (0x40U)
#define CLKCTL3_PSCCTL0_SENS_SET_MU2_SHIFT       (6U)
/*! MU2 - MU2 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_MU2(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_MU2_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_MU2_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_OSTIMER_MASK    (0x80U)
#define CLKCTL3_PSCCTL0_SENS_SET_OSTIMER_SHIFT   (7U)
/*! OSTIMER - OSTIMER Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_OSTIMER(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_OSTIMER_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_OSTIMER_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_SEMA42_0_MASK   (0x100U)
#define CLKCTL3_PSCCTL0_SENS_SET_SEMA42_0_SHIFT  (8U)
/*! SEMA42_0 - SEMA42_0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_SEMA42_0(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_SEMA42_0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_SEMA42_0_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_SDADC0_MASK     (0x200U)
#define CLKCTL3_PSCCTL0_SENS_SET_SDADC0_SHIFT    (9U)
/*! SDADC0 - SDADC0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_SDADC0(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_SDADC0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_SDADC0_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_SARADC0_MASK    (0x400U)
#define CLKCTL3_PSCCTL0_SENS_SET_SARADC0_SHIFT   (10U)
/*! SARADC0 - ADC0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_SARADC0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_SARADC0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_SARADC0_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_ACMP0_MASK      (0x800U)
#define CLKCTL3_PSCCTL0_SENS_SET_ACMP0_SHIFT     (11U)
/*! ACMP0 - ACMP0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_ACMP0(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_ACMP0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_ACMP0_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_MICFIL_MASK     (0x1000U)
#define CLKCTL3_PSCCTL0_SENS_SET_MICFIL_SHIFT    (12U)
/*! MICFIL - MICFIL Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_MICFIL(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_MICFIL_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_MICFIL_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_GLIKEY4_MASK    (0x2000U)
#define CLKCTL3_PSCCTL0_SENS_SET_GLIKEY4_SHIFT   (13U)
/*! GLIKEY4 - GLIKEY4 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_GLIKEY4(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_GLIKEY4_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_GLIKEY4_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_DBG_RT700_MASK  (0x100000U)
#define CLKCTL3_PSCCTL0_SENS_SET_DBG_RT700_SHIFT (20U)
/*! DBG_RT700 - DBG_RT700 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_DBG_RT700(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_DBG_RT700_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_DBG_RT700_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_SYSCON3_MASK    (0x200000U)
#define CLKCTL3_PSCCTL0_SENS_SET_SYSCON3_SHIFT   (21U)
/*! SYSCON3 - SYSCON3 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_SYSCON3(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_SYSCON3_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_SYSCON3_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_IOPCTL1_MASK    (0x400000U)
#define CLKCTL3_PSCCTL0_SENS_SET_IOPCTL1_SHIFT   (22U)
/*! IOPCTL1 - IOPCTL1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_IOPCTL1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_IOPCTL1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_IOPCTL1_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_GLIKEY1_MASK    (0x800000U)
#define CLKCTL3_PSCCTL0_SENS_SET_GLIKEY1_SHIFT   (23U)
/*! GLIKEY1 - GLIKEY1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL3_PSCCTL0_SENS_SET_GLIKEY1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_GLIKEY1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_GLIKEY1_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_LPI2C15_MASK    (0x1000000U)
#define CLKCTL3_PSCCTL0_SENS_SET_LPI2C15_SHIFT   (24U)
/*! LPI2C15 - LPI2C15 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL3_PSCCTL0_SENS_SET_LPI2C15(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_LPI2C15_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_LPI2C15_MASK)

#define CLKCTL3_PSCCTL0_SENS_SET_MEDIA_ACESS_RAM_ARBITER1_MASK (0x2000000U)
#define CLKCTL3_PSCCTL0_SENS_SET_MEDIA_ACESS_RAM_ARBITER1_SHIFT (25U)
/*! MEDIA_ACESS_RAM_ARBITER1 - Media Access RAM Arbiter1 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL3_PSCCTL0_SENS_SET_MEDIA_ACESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_SET_MEDIA_ACESS_RAM_ARBITER1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_SET_MEDIA_ACESS_RAM_ARBITER1_MASK)
/*! @} */

/*! @name PSCCTL0_SENS_CLR - VDD1_SENSE Peripheral Clock Control 0 Clear */
/*! @{ */

#define CLKCTL3_PSCCTL0_SENS_CLR_CPU1_MASK       (0x1U)
#define CLKCTL3_PSCCTL0_SENS_CLR_CPU1_SHIFT      (0U)
/*! CPU1 - CPU1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_CPU1(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_CPU1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_CPU1_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_MU0_MASK        (0x10U)
#define CLKCTL3_PSCCTL0_SENS_CLR_MU0_SHIFT       (4U)
/*! MU0 - MU0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_MU0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_MU0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_MU0_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_MU1_MASK        (0x20U)
#define CLKCTL3_PSCCTL0_SENS_CLR_MU1_SHIFT       (5U)
/*! MU1 - MU1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_MU1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_MU1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_MU1_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_MU2_MASK        (0x40U)
#define CLKCTL3_PSCCTL0_SENS_CLR_MU2_SHIFT       (6U)
/*! MU2 - MU2 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_MU2(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_MU2_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_MU2_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_OSTIMER_MASK    (0x80U)
#define CLKCTL3_PSCCTL0_SENS_CLR_OSTIMER_SHIFT   (7U)
/*! OSTIMER - OSTIMER Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_OSTIMER(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_OSTIMER_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_OSTIMER_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_SEMA42_0_MASK   (0x100U)
#define CLKCTL3_PSCCTL0_SENS_CLR_SEMA42_0_SHIFT  (8U)
/*! SEMA42_0 - SEMA42_0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_SEMA42_0(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_SEMA42_0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_SEMA42_0_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_SDADC0_MASK     (0x200U)
#define CLKCTL3_PSCCTL0_SENS_CLR_SDADC0_SHIFT    (9U)
/*! SDADC0 - SDADC0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_SDADC0(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_SDADC0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_SDADC0_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_SARADC0_MASK    (0x400U)
#define CLKCTL3_PSCCTL0_SENS_CLR_SARADC0_SHIFT   (10U)
/*! SARADC0 - ADC0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_SARADC0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_SARADC0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_SARADC0_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_ACMP0_MASK      (0x800U)
#define CLKCTL3_PSCCTL0_SENS_CLR_ACMP0_SHIFT     (11U)
/*! ACMP0 - ACMP0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_ACMP0(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_ACMP0_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_ACMP0_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_MICFIL_MASK     (0x1000U)
#define CLKCTL3_PSCCTL0_SENS_CLR_MICFIL_SHIFT    (12U)
/*! MICFIL - MICFIL Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_MICFIL(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_MICFIL_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_MICFIL_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY4_MASK    (0x2000U)
#define CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY4_SHIFT   (13U)
/*! GLIKEY4 - GLIKEY4 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY4(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY4_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY4_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_DBG_RT700_MASK  (0x100000U)
#define CLKCTL3_PSCCTL0_SENS_CLR_DBG_RT700_SHIFT (20U)
/*! DBG_RT700 - DBG_RT700 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_DBG_RT700(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_DBG_RT700_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_DBG_RT700_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_SYSCON3_MASK    (0x200000U)
#define CLKCTL3_PSCCTL0_SENS_CLR_SYSCON3_SHIFT   (21U)
/*! SYSCON3 - SYSCON3 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_SYSCON3(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_SYSCON3_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_SYSCON3_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_IOPCTL1_MASK    (0x400000U)
#define CLKCTL3_PSCCTL0_SENS_CLR_IOPCTL1_SHIFT   (22U)
/*! IOPCTL1 - IOPCTL1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_IOPCTL1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_IOPCTL1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_IOPCTL1_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY1_MASK    (0x800000U)
#define CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY1_SHIFT   (23U)
/*! GLIKEY1 - GLIKEY1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_GLIKEY1_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_LPI2C15_MASK    (0x1000000U)
#define CLKCTL3_PSCCTL0_SENS_CLR_LPI2C15_SHIFT   (24U)
/*! LPI2C15 - LPI2C15 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_LPI2C15(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_LPI2C15_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_LPI2C15_MASK)

#define CLKCTL3_PSCCTL0_SENS_CLR_MEDIA_ACCESS_RAM_ARBITER1_MASK (0x2000000U)
#define CLKCTL3_PSCCTL0_SENS_CLR_MEDIA_ACCESS_RAM_ARBITER1_SHIFT (25U)
/*! MEDIA_ACCESS_RAM_ARBITER1 - Media Access RAM Arbiter1 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL3_PSCCTL0_SENS_CLR_MEDIA_ACCESS_RAM_ARBITER1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_PSCCTL0_SENS_CLR_MEDIA_ACCESS_RAM_ARBITER1_SHIFT)) & CLKCTL3_PSCCTL0_SENS_CLR_MEDIA_ACCESS_RAM_ARBITER1_MASK)
/*! @} */

/*! @name ONE_SRC_CLKSLICE_ENABLE_SENSE - One Source Clock Slice Enable for VDD1_SENSE CPU */
/*! @{ */

#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_RTC_FCLK_EN_MASK (0x1U)
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_RTC_FCLK_EN_SHIFT (0U)
/*! RTC_FCLK_EN - RTC Functional Clock Gating Enable
 *  0b0..Gates RTC functional clock.
 *  0b1..Enables RTC functional clock.
 */
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_RTC_FCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_RTC_FCLK_EN_SHIFT)) & CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_RTC_FCLK_EN_MASK)

#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET2_FCLK_EN_MASK (0x2U)
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET2_FCLK_EN_SHIFT (1U)
/*! dGDET2_FCLK_EN - dGDET2 Functional Clock Enable
 *  0b0..Gates dGDET2 functional clock.
 *  0b1..Enables dGDET2 functional clock.
 */
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET2_FCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET2_FCLK_EN_SHIFT)) & CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET2_FCLK_EN_MASK)

#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET3_FCLK_EN_MASK (0x4U)
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET3_FCLK_EN_SHIFT (2U)
/*! dGDET3_FCLK_EN - dGDET3 Functional Clock Enable
 *  0b0..Gates dGDET3 functional clock.
 *  0b1..Enables dGDET3 functional clock.
 */
#define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET3_FCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET3_FCLK_EN_SHIFT)) & CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET3_FCLK_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CLKCTL3_Register_Masks */


/* CLKCTL3 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CLKCTL3 base address */
  #define CLKCTL3_BASE                             (0x50061000u)
  /** Peripheral CLKCTL3 base address */
  #define CLKCTL3_BASE_NS                          (0x40061000u)
  /** Peripheral CLKCTL3 base pointer */
  #define CLKCTL3                                  ((CLKCTL3_Type *)CLKCTL3_BASE)
  /** Peripheral CLKCTL3 base pointer */
  #define CLKCTL3_NS                               ((CLKCTL3_Type *)CLKCTL3_BASE_NS)
  /** Array initializer of CLKCTL3 peripheral base addresses */
  #define CLKCTL3_BASE_ADDRS                       { CLKCTL3_BASE }
  /** Array initializer of CLKCTL3 peripheral base pointers */
  #define CLKCTL3_BASE_PTRS                        { CLKCTL3 }
  /** Array initializer of CLKCTL3 peripheral base addresses */
  #define CLKCTL3_BASE_ADDRS_NS                    { CLKCTL3_BASE_NS }
  /** Array initializer of CLKCTL3 peripheral base pointers */
  #define CLKCTL3_BASE_PTRS_NS                     { CLKCTL3_NS }
#else
  /** Peripheral CLKCTL3 base address */
  #define CLKCTL3_BASE                             (0x40061000u)
  /** Peripheral CLKCTL3 base pointer */
  #define CLKCTL3                                  ((CLKCTL3_Type *)CLKCTL3_BASE)
  /** Array initializer of CLKCTL3 peripheral base addresses */
  #define CLKCTL3_BASE_ADDRS                       { CLKCTL3_BASE }
  /** Array initializer of CLKCTL3 peripheral base pointers */
  #define CLKCTL3_BASE_PTRS                        { CLKCTL3 }
#endif

/*!
 * @}
 */ /* end of group CLKCTL3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CLKCTL4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL4_Peripheral_Access_Layer CLKCTL4 Peripheral Access Layer
 * @{
 */

/** CLKCTL4 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PSCCTL0_MEDIA;                     /**< VDD2_COMP Media Peripheral Clock Control 0, offset: 0x10 */
  __IO uint32_t PSCCTL1_MEDIA;                     /**< VDD2_COMP Media Peripheral Clock Control 1, offset: 0x14 */
       uint8_t RESERVED_1[40];
  __IO uint32_t PSCCTL0_MEDIA_SET;                 /**< VDD2_COMP Media Peripheral Clock Control 0 Set, offset: 0x40 */
  __IO uint32_t PSCCTL1_MEDIA_SET;                 /**< VDD2_COMP Media Peripheral Clock Control 1 Set, offset: 0x44 */
       uint8_t RESERVED_2[40];
  __IO uint32_t PSCCTL0_MEDIA_CLR;                 /**< VDD2_COMP Media Peripheral Clock Control 0 Clear, offset: 0x70 */
  __IO uint32_t PSCCTL1_MEDIA_CLR;                 /**< VDD2_COMP Media Peripheral Clock Control 1 Clear, offset: 0x74 */
       uint8_t RESERVED_3[24];
  __IO uint32_t ONE_SRC_CLKSLICE_ENABLE;           /**< One Source Clock Slice Enable for VDD2_COMP Core, offset: 0x90 */
       uint8_t RESERVED_4[16];
  __IO uint32_t MEDIAVDDNCLKSEL;                   /**< VDDN_MEDIA Clock Source Select, offset: 0xA4 */
       uint8_t RESERVED_5[4];
  __IO uint32_t MEDIAVDDNCLKDIV;                   /**< VDDN_MEDIA Clock Divider, offset: 0xAC */
       uint8_t RESERVED_6[84];
  __IO uint32_t MEDIAMAINCLKSEL;                   /**< Media Main Clock Source Select, offset: 0x104 */
       uint8_t RESERVED_7[4];
  __IO uint32_t MEDIAMAINCLKDIV;                   /**< Media Main Clock Divider, offset: 0x10C */
  __IO uint32_t MDNBASECLKSEL;                     /**< VDDN_MEDIA Base Clock Source Select, offset: 0x110 */
  __IO uint32_t MD2BASECLKSEL;                     /**< VDD2_MEDIA Base Clock Source Select, offset: 0x114 */
       uint8_t RESERVED_8[232];
  __IO uint32_t XSPI2FCLKSEL;                      /**< XSPI2 Functional Clock Source Select, offset: 0x200 */
  __IO uint32_t XSPI2FCLKDIV;                      /**< XSPI2 Functional Clock Divider, offset: 0x204 */
       uint8_t RESERVED_9[24];
  __IO uint32_t USBFCLKSEL;                        /**< USB0 Functional Clock Source Select, offset: 0x220 */
       uint8_t RESERVED_10[28];
  __IO uint32_t EUSBFCLKSEL;                       /**< USB1 (eUSB) Functional Clock Source Select, offset: 0x240 */
       uint8_t RESERVED_11[28];
  __IO uint32_t SDIO0FCLKSEL;                      /**< SDIO0 Functional Clock Source Select, offset: 0x260 */
  __IO uint32_t SDIO0FCLKDIV;                      /**< SDIO0 Functional Clock Divider, offset: 0x264 */
       uint8_t RESERVED_12[24];
  __IO uint32_t SDIO1FCLKSEL;                      /**< SDIO1 Functional Clock Source Select, offset: 0x280 */
  __IO uint32_t SDIO1FCLKDIV;                      /**< SDIO1 Functional Clock Divider, offset: 0x284 */
       uint8_t RESERVED_13[120];
  __IO uint32_t DPHYCLKSEL;                        /**< MIPI_DSI_Host PHY Clock Source Select, offset: 0x300 */
  __IO uint32_t DPHYCLKDIV;                        /**< MIPI_DSI_Host PHY Clock Divider, offset: 0x304 */
  __IO uint32_t DPHYESCCLKSEL;                     /**< MIPI_DSI_Host DPHY Escape Mode Clock Source Select, offset: 0x308 */
  __IO uint32_t DPHYESCRXCLKDIV;                   /**< MIPI_DSI_Host DPHY Escape Mode Receive Clock Divider, offset: 0x30C */
  __IO uint32_t DPHYESCTXCLKDIV;                   /**< MIPI_DSI_Host DPHY Escape Mode Transmit Clock Divider, offset: 0x310 */
       uint8_t RESERVED_14[12];
  __IO uint32_t VGPUCLKSEL;                        /**< VGPU Clock Source Select, offset: 0x320 */
  __IO uint32_t VGPUCLKDIV;                        /**< VGPU Clock Divider, offset: 0x324 */
  __IO uint32_t LPSPI14CLKSEL;                     /**< LPSPI14 Clock Source Select, offset: 0x328 */
  __IO uint32_t LPSPI14CLKDIV;                     /**< LPSPI14 Clock Divider, offset: 0x32C */
  __IO uint32_t LPSPI16CLKSEL;                     /**< LPSPI16 Clock Source Select, offset: 0x330 */
  __IO uint32_t LPSPI16CLKDIV;                     /**< LPSPI16 Clock Divider, offset: 0x334 */
  __IO uint32_t FLEXIOCLKSEL;                      /**< FLEXIO Clock Source Select, offset: 0x338 */
  __IO uint32_t FLEXIOCLKDIV;                      /**< FLEXIO Clock Divider, offset: 0x33C */
  __IO uint32_t LCDIFPIXELCLKSEL;                  /**< LCDIF Pixel Clock Source Select, offset: 0x340 */
  __IO uint32_t LCDIFPIXELCLKDIV;                  /**< LCDIF Pixel Clock Divider, offset: 0x344 */
       uint8_t RESERVED_15[952];
  __IO uint32_t LOWFREQCLKDIV;                     /**< Low frequency Clock Divider, offset: 0x700 */
       uint8_t RESERVED_16[268];
  __IO uint32_t PSCCTL0_SENS;                      /**< VDD1_SENSE Media Peripheral Clock Control 0, offset: 0x810 */
  __IO uint32_t PSCCTL1_SENS;                      /**< VDD1_SENSE Media Peripheral Clock Control 1, offset: 0x814 */
       uint8_t RESERVED_17[40];
  __IO uint32_t PSCCTL0_SENS_SET;                  /**< VDD1_SENSE Media Peripheral Clock Control 0 Set, offset: 0x840 */
  __IO uint32_t PSCCTL1_SENS_SET;                  /**< VDD1_SENSE Media Peripheral Clock Control 1 Set, offset: 0x844 */
       uint8_t RESERVED_18[40];
  __IO uint32_t PSCCTL0_SENS_CLR;                  /**< VDD1_SENSE Media Peripheral Clock Control 0 Clear, offset: 0x870 */
  __IO uint32_t PSCCTL1_SENS_CLR;                  /**< VDD1_SENSE Media Peripheral Clock Control 1 Clear, offset: 0x874 */
       uint8_t RESERVED_19[24];
  __IO uint32_t ONE_SRC_CLKSLICE_ENABLE_SENSE;     /**< One Source Clock Slice Enable for VDD1_SENSE Core, offset: 0x890 */
} CLKCTL4_Type;

/* ----------------------------------------------------------------------------
   -- CLKCTL4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL4_Register_Masks CLKCTL4 Register Masks
 * @{
 */

/*! @name PSCCTL0_MEDIA - VDD2_COMP Media Peripheral Clock Control 0 */
/*! @{ */

#define CLKCTL4_PSCCTL0_MEDIA_VGPU_MASK          (0x4U)
#define CLKCTL4_PSCCTL0_MEDIA_VGPU_SHIFT         (2U)
/*! VGPU - VGPU Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_VGPU(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_VGPU_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_VGPU_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_MIPI_DSI_HOST_MASK (0x10U)
#define CLKCTL4_PSCCTL0_MEDIA_MIPI_DSI_HOST_SHIFT (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_MIPI_DSI_HOST(x)   (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_MIPI_DSI_HOST_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_MIPI_DSI_HOST_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_LPSPI16_MASK       (0x20U)
#define CLKCTL4_PSCCTL0_MEDIA_LPSPI16_SHIFT      (5U)
/*! LPSPI16 - LPSPT16 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_LPSPI16(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_LPSPI16_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_LPSPI16_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_LPSPI14_MASK       (0x40U)
#define CLKCTL4_PSCCTL0_MEDIA_LPSPI14_SHIFT      (6U)
/*! LPSPI14 - LPSPI14 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_LPSPI14(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_LPSPI14_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_LPSPI14_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_XSPI2_MASK         (0x100U)
#define CLKCTL4_PSCCTL0_MEDIA_XSPI2_SHIFT        (8U)
/*! XSPI2 - XSPI2 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_XSPI2(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_XSPI2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_XSPI2_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_MMU2_MASK          (0x800U)
#define CLKCTL4_PSCCTL0_MEDIA_MMU2_SHIFT         (11U)
/*! MMU2 - MMU2 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_MMU2(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_MMU2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_MMU2_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_GLIKEY5_MASK       (0x2000U)
#define CLKCTL4_PSCCTL0_MEDIA_GLIKEY5_SHIFT      (13U)
/*! GLIKEY5 - GLIKEY5 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_GLIKEY5(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_GLIKEY5_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_GLIKEY5_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_FLEXIO0_MASK       (0x8000U)
#define CLKCTL4_PSCCTL0_MEDIA_FLEXIO0_SHIFT      (15U)
/*! FLEXIO0 - FLEXIO0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_FLEXIO0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_FLEXIO0_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_FLEXIO0_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_LCDIF_MASK         (0x400000U)
#define CLKCTL4_PSCCTL0_MEDIA_LCDIF_SHIFT        (22U)
/*! LCDIF - LCDIF Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_LCDIF(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_LCDIF_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_LCDIF_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SYSCON4_MASK       (0x800000U)
#define CLKCTL4_PSCCTL0_MEDIA_SYSCON4_SHIFT      (23U)
/*! SYSCON4 - SYSCON4 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_SYSCON4(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SYSCON4_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SYSCON4_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_JPEGDEC_MASK       (0x1000000U)
#define CLKCTL4_PSCCTL0_MEDIA_JPEGDEC_SHIFT      (24U)
/*! JPEGDEC - JPEGDEC Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_JPEGDEC(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_JPEGDEC_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_JPEGDEC_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_PNGDEC_MASK        (0x2000000U)
#define CLKCTL4_PSCCTL0_MEDIA_PNGDEC_SHIFT       (25U)
/*! PNGDEC - PNGDEC Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_PNGDEC(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_PNGDEC_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_PNGDEC_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_EZHV_MASK          (0x4000000U)
#define CLKCTL4_PSCCTL0_MEDIA_EZHV_SHIFT         (26U)
/*! EZHV - EZHV Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_EZHV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_EZHV_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_EZHV_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_AXBS_EZH_MASK      (0x10000000U)
#define CLKCTL4_PSCCTL0_MEDIA_AXBS_EZH_SHIFT     (28U)
/*! AXBS_EZH - AXBS for EZHV Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_AXBS_EZH(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_AXBS_EZH_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_AXBS_EZH_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_GLIKEY2_MASK       (0x20000000U)
#define CLKCTL4_PSCCTL0_MEDIA_GLIKEY2_SHIFT      (29U)
/*! GLIKEY2 - GLIKEY2 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_MEDIA_GLIKEY2(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_GLIKEY2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_GLIKEY2_MASK)
/*! @} */

/*! @name PSCCTL1_MEDIA - VDD2_COMP Media Peripheral Clock Control 1 */
/*! @{ */

#define CLKCTL4_PSCCTL1_MEDIA_USB0_MASK          (0x1U)
#define CLKCTL4_PSCCTL1_MEDIA_USB0_SHIFT         (0U)
/*! USB0 - USB0 and USBPHY0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_MEDIA_USB0(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_USB0_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_USB0_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_USB1_MASK          (0x4U)
#define CLKCTL4_PSCCTL1_MEDIA_USB1_SHIFT         (2U)
/*! USB1 - USB1 and eUSBPHY Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_MEDIA_USB1(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_USB1_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_USB1_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_USDHC0_MASK        (0x10U)
#define CLKCTL4_PSCCTL1_MEDIA_USDHC0_SHIFT       (4U)
/*! uSDHC0 - uSDHC0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_MEDIA_USDHC0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_USDHC0_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_USDHC0_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_USDHC1_MASK        (0x20U)
#define CLKCTL4_PSCCTL1_MEDIA_USDHC1_SHIFT       (5U)
/*! uSDHC1 - uSDHC1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_MEDIA_USDHC1(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_USDHC1_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_USDHC1_MASK)
/*! @} */

/*! @name PSCCTL0_MEDIA_SET - VDD2_COMP Media Peripheral Clock Control 0 Set */
/*! @{ */

#define CLKCTL4_PSCCTL0_MEDIA_SET_VGPU_MASK      (0x4U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_VGPU_SHIFT     (2U)
/*! VGPU - VGPU Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_VGPU(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_VGPU_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_VGPU_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_MIPI_DSI_HOST_MASK (0x10U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_MIPI_DSI_HOST_SHIFT (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_MIPI_DSI_HOST(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_MIPI_DSI_HOST_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_MIPI_DSI_HOST_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI16_MASK   (0x20U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI16_SHIFT  (5U)
/*! LPSPI16 - LPSPI16 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI16(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI16_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI16_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI14_MASK   (0x40U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI14_SHIFT  (6U)
/*! LPSPI14 - LPSPI14 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI14(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI14_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_LPSPI14_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_XSPI2_MASK     (0x100U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_XSPI2_SHIFT    (8U)
/*! XSPI2 - XSPI2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_XSPI2(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_XSPI2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_XSPI2_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_MMU2_MASK      (0x800U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_MMU2_SHIFT     (11U)
/*! MMU2 - MMU2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_MMU2(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_MMU2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_MMU2_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY5_MASK   (0x2000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY5_SHIFT  (13U)
/*! GLIKEY5 - GLIKEY5 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY5(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY5_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY5_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_FLEXIO0_MASK   (0x8000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_FLEXIO0_SHIFT  (15U)
/*! FLEXIO0 - FLEXIO0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_FLEXIO0(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_FLEXIO0_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_FLEXIO0_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_LCDIF_MASK     (0x400000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_LCDIF_SHIFT    (22U)
/*! LCDIF - LCDIF Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_LCDIF(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_LCDIF_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_LCDIF_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_SYSCON4_MASK   (0x800000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_SYSCON4_SHIFT  (23U)
/*! SYSCON4 - SYSCON4 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_SYSCON4(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_SYSCON4_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_SYSCON4_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_JPEGDEC_MASK   (0x1000000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_JPEGDEC_SHIFT  (24U)
/*! JPEGDEC - JPEGDEC Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_JPEGDEC(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_JPEGDEC_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_JPEGDEC_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_PNGDEC_MASK    (0x2000000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_PNGDEC_SHIFT   (25U)
/*! PNGDEC - PNGDEC Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_PNGDEC(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_PNGDEC_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_PNGDEC_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_EZHV_MASK      (0x4000000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_EZHV_SHIFT     (26U)
/*! EZHV - EZHV Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_EZHV(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_EZHV_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_EZHV_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_AXBS_EZH_MASK  (0x10000000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_AXBS_EZH_SHIFT (28U)
/*! AXBS_EZH - AXBS for EZHV Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_AXBS_EZH(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_AXBS_EZH_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_AXBS_EZH_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY2_MASK   (0x20000000U)
#define CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY2_SHIFT  (29U)
/*! GLIKEY2 - GLIKEY2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY2(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_SET_GLIKEY2_MASK)
/*! @} */

/*! @name PSCCTL1_MEDIA_SET - VDD2_COMP Media Peripheral Clock Control 1 Set */
/*! @{ */

#define CLKCTL4_PSCCTL1_MEDIA_SET_USB0_MASK      (0x1U)
#define CLKCTL4_PSCCTL1_MEDIA_SET_USB0_SHIFT     (0U)
/*! USB0 - USB0 and USBPHY0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_MEDIA_SET_USB0(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_SET_USB0_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_SET_USB0_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_SET_USB1_MASK      (0x4U)
#define CLKCTL4_PSCCTL1_MEDIA_SET_USB1_SHIFT     (2U)
/*! USB1 - USB1 and eUSBPHY Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_MEDIA_SET_USB1(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_SET_USB1_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_SET_USB1_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_SET_USDHC0_MASK    (0x10U)
#define CLKCTL4_PSCCTL1_MEDIA_SET_USDHC0_SHIFT   (4U)
/*! uSDHC0 - uSDHC0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_MEDIA_SET_USDHC0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_SET_USDHC0_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_SET_USDHC0_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_SET_USDHC1_MASK    (0x20U)
#define CLKCTL4_PSCCTL1_MEDIA_SET_USDHC1_SHIFT   (5U)
/*! uSDHC1 - uSDHC1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_MEDIA_SET_USDHC1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_SET_USDHC1_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_SET_USDHC1_MASK)
/*! @} */

/*! @name PSCCTL0_MEDIA_CLR - VDD2_COMP Media Peripheral Clock Control 0 Clear */
/*! @{ */

#define CLKCTL4_PSCCTL0_MEDIA_CLR_VGPU_MASK      (0x4U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_VGPU_SHIFT     (2U)
/*! VGPU - VGPU Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_VGPU(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_VGPU_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_VGPU_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_MIPI_DSI_HOST_MASK (0x10U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_MIPI_DSI_HOST_SHIFT (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_MIPI_DSI_HOST(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_MIPI_DSI_HOST_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_MIPI_DSI_HOST_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI16_MASK   (0x20U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI16_SHIFT  (5U)
/*! LPSPI16 - LPSPI16 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI16(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI16_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI16_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI14_MASK   (0x40U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI14_SHIFT  (6U)
/*! LPSPI14 - LPSPI14 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI14(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI14_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_LPSPI14_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_XSPI2_MASK     (0x100U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_XSPI2_SHIFT    (8U)
/*! XSPI2 - XSPI2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_XSPI2(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_XSPI2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_XSPI2_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_MMU2_MASK      (0x800U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_MMU2_SHIFT     (11U)
/*! MMU2 - MMU2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_MMU2(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_MMU2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_MMU2_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY5_MASK   (0x2000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY5_SHIFT  (13U)
/*! GLIKEY5 - GLIKEY5 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY5(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY5_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY5_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_FLEXIO0_MASK   (0x8000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_FLEXIO0_SHIFT  (15U)
/*! FLEXIO0 - FLEXIO0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_FLEXIO0(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_FLEXIO0_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_FLEXIO0_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_LCDIF_MASK     (0x400000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_LCDIF_SHIFT    (22U)
/*! LCDIF - LCDIF Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_LCDIF(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_LCDIF_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_LCDIF_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_SYSCON4_MASK   (0x800000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_SYSCON4_SHIFT  (23U)
/*! SYSCON4 - SYSCON4 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_SYSCON4(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_SYSCON4_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_SYSCON4_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_JPEGDEC_MASK   (0x1000000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_JPEGDEC_SHIFT  (24U)
/*! JPEGDEC - JPEGDEC Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_JPEGDEC(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_JPEGDEC_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_JPEGDEC_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_PNGDEC_MASK    (0x2000000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_PNGDEC_SHIFT   (25U)
/*! PNGDEC - PNG Decoder Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_PNGDEC(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_PNGDEC_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_PNGDEC_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_EZHV_MASK      (0x4000000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_EZHV_SHIFT     (26U)
/*! EZHV - EZHV Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_EZHV(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_EZHV_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_EZHV_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_AXBS_EZH_MASK  (0x10000000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_AXBS_EZH_SHIFT (28U)
/*! AXBS_EZH - AXBS_EZHV Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_AXBS_EZH(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_AXBS_EZH_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_AXBS_EZH_MASK)

#define CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY2_MASK   (0x20000000U)
#define CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY2_SHIFT  (29U)
/*! GLIKEY2 - GLIKEY2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY2(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY2_SHIFT)) & CLKCTL4_PSCCTL0_MEDIA_CLR_GLIKEY2_MASK)
/*! @} */

/*! @name PSCCTL1_MEDIA_CLR - VDD2_COMP Media Peripheral Clock Control 1 Clear */
/*! @{ */

#define CLKCTL4_PSCCTL1_MEDIA_CLR_USB0_MASK      (0x1U)
#define CLKCTL4_PSCCTL1_MEDIA_CLR_USB0_SHIFT     (0U)
/*! USB0 - USB0 and USBPHY0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL4_PSCCTL1_MEDIA_CLR_USB0(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_CLR_USB0_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_CLR_USB0_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_CLR_USB1_MASK      (0x4U)
#define CLKCTL4_PSCCTL1_MEDIA_CLR_USB1_SHIFT     (2U)
/*! USB1 - USB1 and eUSBPHY Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL4_PSCCTL1_MEDIA_CLR_USB1(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_CLR_USB1_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_CLR_USB1_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC0_MASK    (0x10U)
#define CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC0_SHIFT   (4U)
/*! uSDHC0 - uSDHC0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC0_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC0_MASK)

#define CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC1_MASK    (0x20U)
#define CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC1_SHIFT   (5U)
/*! uSDHC1 - uSDHC1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC1(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC1_SHIFT)) & CLKCTL4_PSCCTL1_MEDIA_CLR_USDHC1_MASK)
/*! @} */

/*! @name ONE_SRC_CLKSLICE_ENABLE - One Source Clock Slice Enable for VDD2_COMP Core */
/*! @{ */

#define CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_USBPHY_REFCLK_EN_MASK (0x1U)
#define CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_USBPHY_REFCLK_EN_SHIFT (0U)
/*! USBPHY_REFCLK_EN - USBPHY0 Reference Clock
 *  0b0..Gates USBPHY0 reference clock.
 *  0b1..Enables USBPHY0 reference clock.
 */
#define CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_USBPHY_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_USBPHY_REFCLK_EN_SHIFT)) & CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_USBPHY_REFCLK_EN_MASK)
/*! @} */

/*! @name MEDIAVDDNCLKSEL - VDDN_MEDIA Clock Source Select */
/*! @{ */

#define CLKCTL4_MEDIAVDDNCLKSEL_SEL_MASK         (0x3U)
#define CLKCTL4_MEDIAVDDNCLKSEL_SEL_SHIFT        (0U)
/*! SEL - VDDN Clock Source Select
 *  0b00..baseclk_mdn
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..main_pll_pfd2
 */
#define CLKCTL4_MEDIAVDDNCLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MEDIAVDDNCLKSEL_SEL_SHIFT)) & CLKCTL4_MEDIAVDDNCLKSEL_SEL_MASK)
/*! @} */

/*! @name MEDIAVDDNCLKDIV - VDDN_MEDIA Clock Divider */
/*! @{ */

#define CLKCTL4_MEDIAVDDNCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL4_MEDIAVDDNCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_MEDIAVDDNCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MEDIAVDDNCLKDIV_DIV_SHIFT)) & CLKCTL4_MEDIAVDDNCLKDIV_DIV_MASK)

#define CLKCTL4_MEDIAVDDNCLKDIV_BUSY_MASK        (0x10000000U)
#define CLKCTL4_MEDIAVDDNCLKDIV_BUSY_SHIFT       (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_MEDIAVDDNCLKDIV_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MEDIAVDDNCLKDIV_BUSY_SHIFT)) & CLKCTL4_MEDIAVDDNCLKDIV_BUSY_MASK)

#define CLKCTL4_MEDIAVDDNCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL4_MEDIAVDDNCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_MEDIAVDDNCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MEDIAVDDNCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_MEDIAVDDNCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name MEDIAMAINCLKSEL - Media Main Clock Source Select */
/*! @{ */

#define CLKCTL4_MEDIAMAINCLKSEL_SEL_MASK         (0x3U)
#define CLKCTL4_MEDIAMAINCLKSEL_SEL_SHIFT        (0U)
/*! SEL - Media Main Clock Source Select
 *  0b00..baseclk_md2
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..main_pll_pfd2
 */
#define CLKCTL4_MEDIAMAINCLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MEDIAMAINCLKSEL_SEL_SHIFT)) & CLKCTL4_MEDIAMAINCLKSEL_SEL_MASK)
/*! @} */

/*! @name MEDIAMAINCLKDIV - Media Main Clock Divider */
/*! @{ */

#define CLKCTL4_MEDIAMAINCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL4_MEDIAMAINCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_MEDIAMAINCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MEDIAMAINCLKDIV_DIV_SHIFT)) & CLKCTL4_MEDIAMAINCLKDIV_DIV_MASK)

#define CLKCTL4_MEDIAMAINCLKDIV_BUSY_MASK        (0x10000000U)
#define CLKCTL4_MEDIAMAINCLKDIV_BUSY_SHIFT       (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_MEDIAMAINCLKDIV_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MEDIAMAINCLKDIV_BUSY_SHIFT)) & CLKCTL4_MEDIAMAINCLKDIV_BUSY_MASK)

#define CLKCTL4_MEDIAMAINCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL4_MEDIAMAINCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_MEDIAMAINCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MEDIAMAINCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_MEDIAMAINCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name MDNBASECLKSEL - VDDN_MEDIA Base Clock Source Select */
/*! @{ */

#define CLKCTL4_MDNBASECLKSEL_SEL_MASK           (0x3U)
#define CLKCTL4_MDNBASECLKSEL_SEL_SHIFT          (0U)
/*! SEL - VDDN_MEDIA Base Clock Source Select
 *  0b00..fro1_div3
 *  0b01..fro1_max
 *  0b10..fro0_div3
 *  0b11..1m_lposc
 */
#define CLKCTL4_MDNBASECLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MDNBASECLKSEL_SEL_SHIFT)) & CLKCTL4_MDNBASECLKSEL_SEL_MASK)
/*! @} */

/*! @name MD2BASECLKSEL - VDD2_MEDIA Base Clock Source Select */
/*! @{ */

#define CLKCTL4_MD2BASECLKSEL_SEL_MASK           (0x3U)
#define CLKCTL4_MD2BASECLKSEL_SEL_SHIFT          (0U)
/*! SEL - Media VDD2 Base Clock Source Select
 *  0b00..fro1_div3
 *  0b01..fro1_max
 *  0b10..fro0_div3
 *  0b11..1m_lposc
 */
#define CLKCTL4_MD2BASECLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_MD2BASECLKSEL_SEL_SHIFT)) & CLKCTL4_MD2BASECLKSEL_SEL_MASK)
/*! @} */

/*! @name XSPI2FCLKSEL - XSPI2 Functional Clock Source Select */
/*! @{ */

#define CLKCTL4_XSPI2FCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL4_XSPI2FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - XSPI2 Clock Source Select
 *  0b00..baseclk_comn
 *  0b01..audio_pll_pfd1
 *  0b10..fro0_max
 *  0b11..main_pll_pfd3
 */
#define CLKCTL4_XSPI2FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_XSPI2FCLKSEL_SEL_SHIFT)) & CLKCTL4_XSPI2FCLKSEL_SEL_MASK)

#define CLKCTL4_XSPI2FCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL4_XSPI2FCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for XSPI2 clock.
 *  0b1..Enables mux output for XSPI2 clock.
 */
#define CLKCTL4_XSPI2FCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_XSPI2FCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_XSPI2FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name XSPI2FCLKDIV - XSPI2 Functional Clock Divider */
/*! @{ */

#define CLKCTL4_XSPI2FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL4_XSPI2FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_XSPI2FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_XSPI2FCLKDIV_DIV_SHIFT)) & CLKCTL4_XSPI2FCLKDIV_DIV_MASK)

#define CLKCTL4_XSPI2FCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL4_XSPI2FCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_XSPI2FCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_XSPI2FCLKDIV_BUSY_SHIFT)) & CLKCTL4_XSPI2FCLKDIV_BUSY_MASK)

#define CLKCTL4_XSPI2FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL4_XSPI2FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_XSPI2FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_XSPI2FCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_XSPI2FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name USBFCLKSEL - USB0 Functional Clock Source Select */
/*! @{ */

#define CLKCTL4_USBFCLKSEL_SEL_MASK              (0x3U)
#define CLKCTL4_USBFCLKSEL_SEL_SHIFT             (0U)
/*! SEL - Clock Source Select
 *  0b00..wake32k_clk
 *  0b01..1m_lposc
 *  0b10..osc_clk_usb
 *  0b11..Reserved
 */
#define CLKCTL4_USBFCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL4_USBFCLKSEL_SEL_SHIFT)) & CLKCTL4_USBFCLKSEL_SEL_MASK)

#define CLKCTL4_USBFCLKSEL_SEL_EN_MASK           (0x4U)
#define CLKCTL4_USBFCLKSEL_SEL_EN_SHIFT          (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates USB0 clock. It is necessary to read back bit3 with the value of 1 to confirm the clock is already gated then go ahead.
 *  0b1..Enables USB0 clock.
 */
#define CLKCTL4_USBFCLKSEL_SEL_EN(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_USBFCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_USBFCLKSEL_SEL_EN_MASK)

#define CLKCTL4_USBFCLKSEL_GATED_FLAG_MASK       (0x8U)
#define CLKCTL4_USBFCLKSEL_GATED_FLAG_SHIFT      (3U)
/*! GATED_FLAG - Gate Flag
 *  0b0..The USB0 fclk is not gated.
 *  0b1..The USB0 fclk is gated.
 */
#define CLKCTL4_USBFCLKSEL_GATED_FLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_USBFCLKSEL_GATED_FLAG_SHIFT)) & CLKCTL4_USBFCLKSEL_GATED_FLAG_MASK)
/*! @} */

/*! @name EUSBFCLKSEL - USB1 (eUSB) Functional Clock Source Select */
/*! @{ */

#define CLKCTL4_EUSBFCLKSEL_SEL_MASK             (0x3U)
#define CLKCTL4_EUSBFCLKSEL_SEL_SHIFT            (0U)
/*! SEL - USB1 Clock Source Select
 *  0b00..wake32k_clk
 *  0b01..1m_lposc
 *  0b10..osc_clk_eusb
 *  0b11..Reserved
 */
#define CLKCTL4_EUSBFCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL4_EUSBFCLKSEL_SEL_SHIFT)) & CLKCTL4_EUSBFCLKSEL_SEL_MASK)

#define CLKCTL4_EUSBFCLKSEL_SEL_EN_MASK          (0x4U)
#define CLKCTL4_EUSBFCLKSEL_SEL_EN_SHIFT         (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for USB1 functional clock. It is necessary to read back bit3 with the value of 1 to
 *       confirm the clock is already gated then go ahead.
 *  0b1..Enables mux output for USB1 functional clock.
 */
#define CLKCTL4_EUSBFCLKSEL_SEL_EN(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_EUSBFCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_EUSBFCLKSEL_SEL_EN_MASK)

#define CLKCTL4_EUSBFCLKSEL_GATED_FLAG_MASK      (0x8U)
#define CLKCTL4_EUSBFCLKSEL_GATED_FLAG_SHIFT     (3U)
/*! GATED_FLAG - Gate Flag
 *  0b0..The USB1 functional clock is not gated.
 *  0b1..The USB1 functional clock is gated.
 */
#define CLKCTL4_EUSBFCLKSEL_GATED_FLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_EUSBFCLKSEL_GATED_FLAG_SHIFT)) & CLKCTL4_EUSBFCLKSEL_GATED_FLAG_MASK)
/*! @} */

/*! @name SDIO0FCLKSEL - SDIO0 Functional Clock Source Select */
/*! @{ */

#define CLKCTL4_SDIO0FCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL4_SDIO0FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - SDIO0 Functional Clock Source Select
 *  0b00..baseclk_mdn
 *  0b01..audio_pll_pfd0
 *  0b10..fro0_max
 *  0b11..main_pll_pfd2
 */
#define CLKCTL4_SDIO0FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO0FCLKSEL_SEL_SHIFT)) & CLKCTL4_SDIO0FCLKSEL_SEL_MASK)

#define CLKCTL4_SDIO0FCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL4_SDIO0FCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for SD/MMC/SDIO interface 0 clock.
 *  0b1..Enables mux output for SD/MMC/SDIO interface 0 clock.
 */
#define CLKCTL4_SDIO0FCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO0FCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_SDIO0FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name SDIO0FCLKDIV - SDIO0 Functional Clock Divider */
/*! @{ */

#define CLKCTL4_SDIO0FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL4_SDIO0FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_SDIO0FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO0FCLKDIV_DIV_SHIFT)) & CLKCTL4_SDIO0FCLKDIV_DIV_MASK)

#define CLKCTL4_SDIO0FCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL4_SDIO0FCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_SDIO0FCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO0FCLKDIV_BUSY_SHIFT)) & CLKCTL4_SDIO0FCLKDIV_BUSY_MASK)

#define CLKCTL4_SDIO0FCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL4_SDIO0FCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Divider counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_SDIO0FCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO0FCLKDIV_RESET_SHIFT)) & CLKCTL4_SDIO0FCLKDIV_RESET_MASK)

#define CLKCTL4_SDIO0FCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL4_SDIO0FCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_SDIO0FCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO0FCLKDIV_HALT_SHIFT)) & CLKCTL4_SDIO0FCLKDIV_HALT_MASK)

#define CLKCTL4_SDIO0FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL4_SDIO0FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_SDIO0FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_SDIO0FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SDIO1FCLKSEL - SDIO1 Functional Clock Source Select */
/*! @{ */

#define CLKCTL4_SDIO1FCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL4_SDIO1FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - SDIO1 Clock Source Select
 *  0b00..VDDN_MEDIA base clock
 *  0b01..Audio PLL PFD0 clock
 *  0b10..fro0_max
 *  0b11..Main PLL PFD1 clock
 */
#define CLKCTL4_SDIO1FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO1FCLKSEL_SEL_SHIFT)) & CLKCTL4_SDIO1FCLKSEL_SEL_MASK)

#define CLKCTL4_SDIO1FCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL4_SDIO1FCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for SD/MMC/SDIO interface 1 clock.
 *  0b1..Enables mux output for SD/MMC/SDIO interface 1 clock.
 */
#define CLKCTL4_SDIO1FCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO1FCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_SDIO1FCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name SDIO1FCLKDIV - SDIO1 Functional Clock Divider */
/*! @{ */

#define CLKCTL4_SDIO1FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL4_SDIO1FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_SDIO1FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO1FCLKDIV_DIV_SHIFT)) & CLKCTL4_SDIO1FCLKDIV_DIV_MASK)

#define CLKCTL4_SDIO1FCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL4_SDIO1FCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_SDIO1FCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO1FCLKDIV_BUSY_SHIFT)) & CLKCTL4_SDIO1FCLKDIV_BUSY_MASK)

#define CLKCTL4_SDIO1FCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL4_SDIO1FCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_SDIO1FCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO1FCLKDIV_RESET_SHIFT)) & CLKCTL4_SDIO1FCLKDIV_RESET_MASK)

#define CLKCTL4_SDIO1FCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL4_SDIO1FCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_SDIO1FCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO1FCLKDIV_HALT_SHIFT)) & CLKCTL4_SDIO1FCLKDIV_HALT_MASK)

#define CLKCTL4_SDIO1FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL4_SDIO1FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_SDIO1FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_SDIO1FCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_SDIO1FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DPHYCLKSEL - MIPI_DSI_Host PHY Clock Source Select */
/*! @{ */

#define CLKCTL4_DPHYCLKSEL_SEL_MASK              (0x3U)
#define CLKCTL4_DPHYCLKSEL_SEL_SHIFT             (0U)
/*! SEL - MIPI_DSI_Host PHY Clock Source Select
 *  0b00..baseclk_md2
 *  0b01..Reserved
 *  0b10..fro0_max
 *  0b11..audio_pll_pfd2
 */
#define CLKCTL4_DPHYCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYCLKSEL_SEL_SHIFT)) & CLKCTL4_DPHYCLKSEL_SEL_MASK)

#define CLKCTL4_DPHYCLKSEL_SEL_EN_MASK           (0x4U)
#define CLKCTL4_DPHYCLKSEL_SEL_EN_SHIFT          (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for MIPI_DSI_Host PHY clock.
 *  0b1..Enables mux output for MIPI_DSI_Host PHY clock.
 */
#define CLKCTL4_DPHYCLKSEL_SEL_EN(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_DPHYCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name DPHYCLKDIV - MIPI_DSI_Host PHY Clock Divider */
/*! @{ */

#define CLKCTL4_DPHYCLKDIV_DIV_MASK              (0xFFU)
#define CLKCTL4_DPHYCLKDIV_DIV_SHIFT             (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_DPHYCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYCLKDIV_DIV_SHIFT)) & CLKCTL4_DPHYCLKDIV_DIV_MASK)

#define CLKCTL4_DPHYCLKDIV_BUSY_MASK             (0x10000000U)
#define CLKCTL4_DPHYCLKDIV_BUSY_SHIFT            (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_DPHYCLKDIV_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYCLKDIV_BUSY_SHIFT)) & CLKCTL4_DPHYCLKDIV_BUSY_MASK)

#define CLKCTL4_DPHYCLKDIV_RESET_MASK            (0x20000000U)
#define CLKCTL4_DPHYCLKDIV_RESET_SHIFT           (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_DPHYCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYCLKDIV_RESET_SHIFT)) & CLKCTL4_DPHYCLKDIV_RESET_MASK)

#define CLKCTL4_DPHYCLKDIV_HALT_MASK             (0x40000000U)
#define CLKCTL4_DPHYCLKDIV_HALT_SHIFT            (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_DPHYCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYCLKDIV_HALT_SHIFT)) & CLKCTL4_DPHYCLKDIV_HALT_MASK)

#define CLKCTL4_DPHYCLKDIV_REQFLAG_MASK          (0x80000000U)
#define CLKCTL4_DPHYCLKDIV_REQFLAG_SHIFT         (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_DPHYCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_DPHYCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DPHYESCCLKSEL - MIPI_DSI_Host DPHY Escape Mode Clock Source Select */
/*! @{ */

#define CLKCTL4_DPHYESCCLKSEL_SEL_MASK           (0x3U)
#define CLKCTL4_DPHYESCCLKSEL_SEL_SHIFT          (0U)
/*! SEL - Clock Source Select
 *  0b00..baseclk_md2
 *  0b01..main_pll_pfd1
 *  0b10..fro0_max
 *  0b11..audio_pll_pfd2
 */
#define CLKCTL4_DPHYESCCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCCLKSEL_SEL_SHIFT)) & CLKCTL4_DPHYESCCLKSEL_SEL_MASK)

#define CLKCTL4_DPHYESCCLKSEL_SEL_EN_MASK        (0x4U)
#define CLKCTL4_DPHYESCCLKSEL_SEL_EN_SHIFT       (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for MIPI_DSI_Host DPHY clock.
 *  0b1..Enables mux output for MIPI_DSI_Host DPHY clock.
 */
#define CLKCTL4_DPHYESCCLKSEL_SEL_EN(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_DPHYESCCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name DPHYESCRXCLKDIV - MIPI_DSI_Host DPHY Escape Mode Receive Clock Divider */
/*! @{ */

#define CLKCTL4_DPHYESCRXCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL4_DPHYESCRXCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_DPHYESCRXCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCRXCLKDIV_DIV_SHIFT)) & CLKCTL4_DPHYESCRXCLKDIV_DIV_MASK)

#define CLKCTL4_DPHYESCRXCLKDIV_BUSY_MASK        (0x10000000U)
#define CLKCTL4_DPHYESCRXCLKDIV_BUSY_SHIFT       (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_DPHYESCRXCLKDIV_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCRXCLKDIV_BUSY_SHIFT)) & CLKCTL4_DPHYESCRXCLKDIV_BUSY_MASK)

#define CLKCTL4_DPHYESCRXCLKDIV_RESET_MASK       (0x20000000U)
#define CLKCTL4_DPHYESCRXCLKDIV_RESET_SHIFT      (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_DPHYESCRXCLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCRXCLKDIV_RESET_SHIFT)) & CLKCTL4_DPHYESCRXCLKDIV_RESET_MASK)

#define CLKCTL4_DPHYESCRXCLKDIV_HALT_MASK        (0x40000000U)
#define CLKCTL4_DPHYESCRXCLKDIV_HALT_SHIFT       (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_DPHYESCRXCLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCRXCLKDIV_HALT_SHIFT)) & CLKCTL4_DPHYESCRXCLKDIV_HALT_MASK)

#define CLKCTL4_DPHYESCRXCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL4_DPHYESCRXCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_DPHYESCRXCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCRXCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_DPHYESCRXCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DPHYESCTXCLKDIV - MIPI_DSI_Host DPHY Escape Mode Transmit Clock Divider */
/*! @{ */

#define CLKCTL4_DPHYESCTXCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL4_DPHYESCTXCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_DPHYESCTXCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCTXCLKDIV_DIV_SHIFT)) & CLKCTL4_DPHYESCTXCLKDIV_DIV_MASK)

#define CLKCTL4_DPHYESCTXCLKDIV_BUSY_MASK        (0x10000000U)
#define CLKCTL4_DPHYESCTXCLKDIV_BUSY_SHIFT       (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_DPHYESCTXCLKDIV_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCTXCLKDIV_BUSY_SHIFT)) & CLKCTL4_DPHYESCTXCLKDIV_BUSY_MASK)

#define CLKCTL4_DPHYESCTXCLKDIV_RESET_MASK       (0x20000000U)
#define CLKCTL4_DPHYESCTXCLKDIV_RESET_SHIFT      (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_DPHYESCTXCLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCTXCLKDIV_RESET_SHIFT)) & CLKCTL4_DPHYESCTXCLKDIV_RESET_MASK)

#define CLKCTL4_DPHYESCTXCLKDIV_HALT_MASK        (0x40000000U)
#define CLKCTL4_DPHYESCTXCLKDIV_HALT_SHIFT       (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_DPHYESCTXCLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCTXCLKDIV_HALT_SHIFT)) & CLKCTL4_DPHYESCTXCLKDIV_HALT_MASK)

#define CLKCTL4_DPHYESCTXCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL4_DPHYESCTXCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_DPHYESCTXCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_DPHYESCTXCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_DPHYESCTXCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name VGPUCLKSEL - VGPU Clock Source Select */
/*! @{ */

#define CLKCTL4_VGPUCLKSEL_SEL_MASK              (0x3U)
#define CLKCTL4_VGPUCLKSEL_SEL_SHIFT             (0U)
/*! SEL - VGPU Clock Source Select
 *  0b00..baseclk_md2
 *  0b01..main_pll_pfd0
 *  0b10..fro0_max
 *  0b11..main_pll_pfd2
 */
#define CLKCTL4_VGPUCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL4_VGPUCLKSEL_SEL_SHIFT)) & CLKCTL4_VGPUCLKSEL_SEL_MASK)

#define CLKCTL4_VGPUCLKSEL_SEL_EN_MASK           (0x4U)
#define CLKCTL4_VGPUCLKSEL_SEL_EN_SHIFT          (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for VGPU clock.
 *  0b1..Enables mux output for VGPU clock.
 */
#define CLKCTL4_VGPUCLKSEL_SEL_EN(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_VGPUCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_VGPUCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name VGPUCLKDIV - VGPU Clock Divider */
/*! @{ */

#define CLKCTL4_VGPUCLKDIV_DIV_MASK              (0xFFU)
#define CLKCTL4_VGPUCLKDIV_DIV_SHIFT             (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_VGPUCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL4_VGPUCLKDIV_DIV_SHIFT)) & CLKCTL4_VGPUCLKDIV_DIV_MASK)

#define CLKCTL4_VGPUCLKDIV_BUSY_MASK             (0x10000000U)
#define CLKCTL4_VGPUCLKDIV_BUSY_SHIFT            (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_VGPUCLKDIV_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL4_VGPUCLKDIV_BUSY_SHIFT)) & CLKCTL4_VGPUCLKDIV_BUSY_MASK)

#define CLKCTL4_VGPUCLKDIV_RESET_MASK            (0x20000000U)
#define CLKCTL4_VGPUCLKDIV_RESET_SHIFT           (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_VGPUCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_VGPUCLKDIV_RESET_SHIFT)) & CLKCTL4_VGPUCLKDIV_RESET_MASK)

#define CLKCTL4_VGPUCLKDIV_HALT_MASK             (0x40000000U)
#define CLKCTL4_VGPUCLKDIV_HALT_SHIFT            (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_VGPUCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL4_VGPUCLKDIV_HALT_SHIFT)) & CLKCTL4_VGPUCLKDIV_HALT_MASK)

#define CLKCTL4_VGPUCLKDIV_REQFLAG_MASK          (0x80000000U)
#define CLKCTL4_VGPUCLKDIV_REQFLAG_SHIFT         (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_VGPUCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_VGPUCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_VGPUCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name LPSPI14CLKSEL - LPSPI14 Clock Source Select */
/*! @{ */

#define CLKCTL4_LPSPI14CLKSEL_SEL_MASK           (0x3U)
#define CLKCTL4_LPSPI14CLKSEL_SEL_SHIFT          (0U)
/*! SEL - Clock Source Select
 *  0b00..baseclk_md2
 *  0b01..fro0_max
 *  0b10..main_pll_pfd0
 *  0b11..fro1_max
 */
#define CLKCTL4_LPSPI14CLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI14CLKSEL_SEL_SHIFT)) & CLKCTL4_LPSPI14CLKSEL_SEL_MASK)

#define CLKCTL4_LPSPI14CLKSEL_SEL_EN_MASK        (0x4U)
#define CLKCTL4_LPSPI14CLKSEL_SEL_EN_SHIFT       (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for LPSPI14 clock.
 *  0b1..Enables mux output for LPSPI14 clock.
 */
#define CLKCTL4_LPSPI14CLKSEL_SEL_EN(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI14CLKSEL_SEL_EN_SHIFT)) & CLKCTL4_LPSPI14CLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name LPSPI14CLKDIV - LPSPI14 Clock Divider */
/*! @{ */

#define CLKCTL4_LPSPI14CLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL4_LPSPI14CLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_LPSPI14CLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI14CLKDIV_DIV_SHIFT)) & CLKCTL4_LPSPI14CLKDIV_DIV_MASK)

#define CLKCTL4_LPSPI14CLKDIV_BUSY_MASK          (0x10000000U)
#define CLKCTL4_LPSPI14CLKDIV_BUSY_SHIFT         (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_LPSPI14CLKDIV_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI14CLKDIV_BUSY_SHIFT)) & CLKCTL4_LPSPI14CLKDIV_BUSY_MASK)

#define CLKCTL4_LPSPI14CLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL4_LPSPI14CLKDIV_RESET_SHIFT        (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_LPSPI14CLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI14CLKDIV_RESET_SHIFT)) & CLKCTL4_LPSPI14CLKDIV_RESET_MASK)

#define CLKCTL4_LPSPI14CLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL4_LPSPI14CLKDIV_HALT_SHIFT         (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_LPSPI14CLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI14CLKDIV_HALT_SHIFT)) & CLKCTL4_LPSPI14CLKDIV_HALT_MASK)

#define CLKCTL4_LPSPI14CLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL4_LPSPI14CLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_LPSPI14CLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI14CLKDIV_REQFLAG_SHIFT)) & CLKCTL4_LPSPI14CLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name LPSPI16CLKSEL - LPSPI16 Clock Source Select */
/*! @{ */

#define CLKCTL4_LPSPI16CLKSEL_SEL_MASK           (0x3U)
#define CLKCTL4_LPSPI16CLKSEL_SEL_SHIFT          (0U)
/*! SEL - LPSPI16 Clock Source Select
 *  0b00..baseclk_md2
 *  0b01..fro0_max
 *  0b10..main_pll_pfd0
 *  0b11..fro1_max
 */
#define CLKCTL4_LPSPI16CLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI16CLKSEL_SEL_SHIFT)) & CLKCTL4_LPSPI16CLKSEL_SEL_MASK)

#define CLKCTL4_LPSPI16CLKSEL_SEL_EN_MASK        (0x4U)
#define CLKCTL4_LPSPI16CLKSEL_SEL_EN_SHIFT       (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for LPSPI16 clock.
 *  0b1..Enables mux output for LPSPI16 clock.
 */
#define CLKCTL4_LPSPI16CLKSEL_SEL_EN(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI16CLKSEL_SEL_EN_SHIFT)) & CLKCTL4_LPSPI16CLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name LPSPI16CLKDIV - LPSPI16 Clock Divider */
/*! @{ */

#define CLKCTL4_LPSPI16CLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL4_LPSPI16CLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_LPSPI16CLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI16CLKDIV_DIV_SHIFT)) & CLKCTL4_LPSPI16CLKDIV_DIV_MASK)

#define CLKCTL4_LPSPI16CLKDIV_BUSY_MASK          (0x10000000U)
#define CLKCTL4_LPSPI16CLKDIV_BUSY_SHIFT         (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_LPSPI16CLKDIV_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI16CLKDIV_BUSY_SHIFT)) & CLKCTL4_LPSPI16CLKDIV_BUSY_MASK)

#define CLKCTL4_LPSPI16CLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL4_LPSPI16CLKDIV_RESET_SHIFT        (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_LPSPI16CLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI16CLKDIV_RESET_SHIFT)) & CLKCTL4_LPSPI16CLKDIV_RESET_MASK)

#define CLKCTL4_LPSPI16CLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL4_LPSPI16CLKDIV_HALT_SHIFT         (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_LPSPI16CLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI16CLKDIV_HALT_SHIFT)) & CLKCTL4_LPSPI16CLKDIV_HALT_MASK)

#define CLKCTL4_LPSPI16CLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL4_LPSPI16CLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_LPSPI16CLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LPSPI16CLKDIV_REQFLAG_SHIFT)) & CLKCTL4_LPSPI16CLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name FLEXIOCLKSEL - FLEXIO Clock Source Select */
/*! @{ */

#define CLKCTL4_FLEXIOCLKSEL_SEL_MASK            (0x3U)
#define CLKCTL4_FLEXIOCLKSEL_SEL_SHIFT           (0U)
/*! SEL - FLEXIO Clock Source Select
 *  0b00..baseclk_md2
 *  0b01..fro0_max
 *  0b10..fro1_max
 *  0b11..main_pll_pfd3
 */
#define CLKCTL4_FLEXIOCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_FLEXIOCLKSEL_SEL_SHIFT)) & CLKCTL4_FLEXIOCLKSEL_SEL_MASK)

#define CLKCTL4_FLEXIOCLKSEL_SEL_EN_MASK         (0x4U)
#define CLKCTL4_FLEXIOCLKSEL_SEL_EN_SHIFT        (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for FLEXIO clock.
 *  0b1..Enables mux output for FLEXIO clock.
 */
#define CLKCTL4_FLEXIOCLKSEL_SEL_EN(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_FLEXIOCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_FLEXIOCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name FLEXIOCLKDIV - FLEXIO Clock Divider */
/*! @{ */

#define CLKCTL4_FLEXIOCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL4_FLEXIOCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_FLEXIOCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL4_FLEXIOCLKDIV_DIV_SHIFT)) & CLKCTL4_FLEXIOCLKDIV_DIV_MASK)

#define CLKCTL4_FLEXIOCLKDIV_BUSY_MASK           (0x10000000U)
#define CLKCTL4_FLEXIOCLKDIV_BUSY_SHIFT          (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_FLEXIOCLKDIV_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_FLEXIOCLKDIV_BUSY_SHIFT)) & CLKCTL4_FLEXIOCLKDIV_BUSY_MASK)

#define CLKCTL4_FLEXIOCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL4_FLEXIOCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_FLEXIOCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_FLEXIOCLKDIV_RESET_SHIFT)) & CLKCTL4_FLEXIOCLKDIV_RESET_MASK)

#define CLKCTL4_FLEXIOCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL4_FLEXIOCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_FLEXIOCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_FLEXIOCLKDIV_HALT_SHIFT)) & CLKCTL4_FLEXIOCLKDIV_HALT_MASK)

#define CLKCTL4_FLEXIOCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL4_FLEXIOCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_FLEXIOCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_FLEXIOCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_FLEXIOCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name LCDIFPIXELCLKSEL - LCDIF Pixel Clock Source Select */
/*! @{ */

#define CLKCTL4_LCDIFPIXELCLKSEL_SEL_MASK        (0x3U)
#define CLKCTL4_LCDIFPIXELCLKSEL_SEL_SHIFT       (0U)
/*! SEL - LCDIF Pixel Clock Source Select
 *  0b00..baseclk_md2
 *  0b01..main_pll_pfd2
 *  0b10..fro0_max
 *  0b11..audio_pll_pfd1
 */
#define CLKCTL4_LCDIFPIXELCLKSEL_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LCDIFPIXELCLKSEL_SEL_SHIFT)) & CLKCTL4_LCDIFPIXELCLKSEL_SEL_MASK)

#define CLKCTL4_LCDIFPIXELCLKSEL_SEL_EN_MASK     (0x4U)
#define CLKCTL4_LCDIFPIXELCLKSEL_SEL_EN_SHIFT    (2U)
/*! SEL_EN - Clock Mux Output Enable
 *  0b0..Gates mux output for LCDIF clock.
 *  0b1..Enables mux output for LCDIF clock.
 */
#define CLKCTL4_LCDIFPIXELCLKSEL_SEL_EN(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LCDIFPIXELCLKSEL_SEL_EN_SHIFT)) & CLKCTL4_LCDIFPIXELCLKSEL_SEL_EN_MASK)
/*! @} */

/*! @name LCDIFPIXELCLKDIV - LCDIF Pixel Clock Divider */
/*! @{ */

#define CLKCTL4_LCDIFPIXELCLKDIV_DIV_MASK        (0xFFU)
#define CLKCTL4_LCDIFPIXELCLKDIV_DIV_SHIFT       (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_LCDIFPIXELCLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LCDIFPIXELCLKDIV_DIV_SHIFT)) & CLKCTL4_LCDIFPIXELCLKDIV_DIV_MASK)

#define CLKCTL4_LCDIFPIXELCLKDIV_BUSY_MASK       (0x10000000U)
#define CLKCTL4_LCDIFPIXELCLKDIV_BUSY_SHIFT      (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_LCDIFPIXELCLKDIV_BUSY(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LCDIFPIXELCLKDIV_BUSY_SHIFT)) & CLKCTL4_LCDIFPIXELCLKDIV_BUSY_MASK)

#define CLKCTL4_LCDIFPIXELCLKDIV_RESET_MASK      (0x20000000U)
#define CLKCTL4_LCDIFPIXELCLKDIV_RESET_SHIFT     (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_LCDIFPIXELCLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LCDIFPIXELCLKDIV_RESET_SHIFT)) & CLKCTL4_LCDIFPIXELCLKDIV_RESET_MASK)

#define CLKCTL4_LCDIFPIXELCLKDIV_HALT_MASK       (0x40000000U)
#define CLKCTL4_LCDIFPIXELCLKDIV_HALT_SHIFT      (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_LCDIFPIXELCLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LCDIFPIXELCLKDIV_HALT_SHIFT)) & CLKCTL4_LCDIFPIXELCLKDIV_HALT_MASK)

#define CLKCTL4_LCDIFPIXELCLKDIV_REQFLAG_MASK    (0x80000000U)
#define CLKCTL4_LCDIFPIXELCLKDIV_REQFLAG_SHIFT   (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_LCDIFPIXELCLKDIV_REQFLAG(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LCDIFPIXELCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_LCDIFPIXELCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name LOWFREQCLKDIV - Low frequency Clock Divider */
/*! @{ */

#define CLKCTL4_LOWFREQCLKDIV_DIV_MASK           (0xFFFFU)
#define CLKCTL4_LOWFREQCLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock Divider Value Select */
#define CLKCTL4_LOWFREQCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LOWFREQCLKDIV_DIV_SHIFT)) & CLKCTL4_LOWFREQCLKDIV_DIV_MASK)

#define CLKCTL4_LOWFREQCLKDIV_BUSY_MASK          (0x10000000U)
#define CLKCTL4_LOWFREQCLKDIV_BUSY_SHIFT         (28U)
/*! BUSY - Busy Flag
 *  0b0..The CLKOUT is outputted with the new divider value.
 *  0b1..A change is being made to the divider value.
 */
#define CLKCTL4_LOWFREQCLKDIV_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LOWFREQCLKDIV_BUSY_SHIFT)) & CLKCTL4_LOWFREQCLKDIV_BUSY_MASK)

#define CLKCTL4_LOWFREQCLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL4_LOWFREQCLKDIV_RESET_SHIFT        (29U)
/*! RESET - Divider Counter Reset
 *  0b0..No effect
 *  0b1..Resets the divider counter.
 */
#define CLKCTL4_LOWFREQCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LOWFREQCLKDIV_RESET_SHIFT)) & CLKCTL4_LOWFREQCLKDIV_RESET_MASK)

#define CLKCTL4_LOWFREQCLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL4_LOWFREQCLKDIV_HALT_SHIFT         (30U)
/*! HALT - Divider Counter Halt
 *  0b0..No effect
 *  0b1..Halts (stops) the divider counter.
 */
#define CLKCTL4_LOWFREQCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LOWFREQCLKDIV_HALT_SHIFT)) & CLKCTL4_LOWFREQCLKDIV_HALT_MASK)

#define CLKCTL4_LOWFREQCLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL4_LOWFREQCLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Request Flag
 *  0b0..The change to the divider value has been finished.
 *  0b1..The change is being made to the divider value.
 */
#define CLKCTL4_LOWFREQCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_LOWFREQCLKDIV_REQFLAG_SHIFT)) & CLKCTL4_LOWFREQCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name PSCCTL0_SENS - VDD1_SENSE Media Peripheral Clock Control 0 */
/*! @{ */

#define CLKCTL4_PSCCTL0_SENS_VGPU_MASK           (0x4U)
#define CLKCTL4_PSCCTL0_SENS_VGPU_SHIFT          (2U)
/*! VGPU - VGPU Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_VGPU(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_VGPU_SHIFT)) & CLKCTL4_PSCCTL0_SENS_VGPU_MASK)

#define CLKCTL4_PSCCTL0_SENS_MIPI_DSI_HOST_MASK  (0x10U)
#define CLKCTL4_PSCCTL0_SENS_MIPI_DSI_HOST_SHIFT (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_MIPI_DSI_HOST(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_MIPI_DSI_HOST_SHIFT)) & CLKCTL4_PSCCTL0_SENS_MIPI_DSI_HOST_MASK)

#define CLKCTL4_PSCCTL0_SENS_LPSPI16_MASK        (0x20U)
#define CLKCTL4_PSCCTL0_SENS_LPSPI16_SHIFT       (5U)
/*! LPSPI16 - LPSPT16 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_LPSPI16(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_LPSPI16_SHIFT)) & CLKCTL4_PSCCTL0_SENS_LPSPI16_MASK)

#define CLKCTL4_PSCCTL0_SENS_LPSPI14_MASK        (0x40U)
#define CLKCTL4_PSCCTL0_SENS_LPSPI14_SHIFT       (6U)
/*! LPSPI14 - LPSPI14 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_LPSPI14(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_LPSPI14_SHIFT)) & CLKCTL4_PSCCTL0_SENS_LPSPI14_MASK)

#define CLKCTL4_PSCCTL0_SENS_XSPI2_MASK          (0x100U)
#define CLKCTL4_PSCCTL0_SENS_XSPI2_SHIFT         (8U)
/*! XSPI2 - XSPI2 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_XSPI2(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_XSPI2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_XSPI2_MASK)

#define CLKCTL4_PSCCTL0_SENS_MMU2_MASK           (0x800U)
#define CLKCTL4_PSCCTL0_SENS_MMU2_SHIFT          (11U)
/*! MMU2 - MMU2 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_MMU2(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_MMU2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_MMU2_MASK)

#define CLKCTL4_PSCCTL0_SENS_GLIKEY5_MASK        (0x2000U)
#define CLKCTL4_PSCCTL0_SENS_GLIKEY5_SHIFT       (13U)
/*! GLIKEY5 - GLIKEY5 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_GLIKEY5(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_GLIKEY5_SHIFT)) & CLKCTL4_PSCCTL0_SENS_GLIKEY5_MASK)

#define CLKCTL4_PSCCTL0_SENS_FLEXIO0_MASK        (0x8000U)
#define CLKCTL4_PSCCTL0_SENS_FLEXIO0_SHIFT       (15U)
/*! FLEXIO0 - FLEXIO0 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_FLEXIO0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_FLEXIO0_SHIFT)) & CLKCTL4_PSCCTL0_SENS_FLEXIO0_MASK)

#define CLKCTL4_PSCCTL0_SENS_LCDIF_MASK          (0x400000U)
#define CLKCTL4_PSCCTL0_SENS_LCDIF_SHIFT         (22U)
/*! LCDIF - LCDIF Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_LCDIF(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_LCDIF_SHIFT)) & CLKCTL4_PSCCTL0_SENS_LCDIF_MASK)

#define CLKCTL4_PSCCTL0_SENS_SYSCON4_MASK        (0x800000U)
#define CLKCTL4_PSCCTL0_SENS_SYSCON4_SHIFT       (23U)
/*! SYSCON4 - SYSCON4 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_SYSCON4(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SYSCON4_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SYSCON4_MASK)

#define CLKCTL4_PSCCTL0_SENS_JPEGDEC_MASK        (0x1000000U)
#define CLKCTL4_PSCCTL0_SENS_JPEGDEC_SHIFT       (24U)
/*! JPEGDEC - JPEGDEC Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_JPEGDEC(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_JPEGDEC_SHIFT)) & CLKCTL4_PSCCTL0_SENS_JPEGDEC_MASK)

#define CLKCTL4_PSCCTL0_SENS_PNGDEC_MASK         (0x2000000U)
#define CLKCTL4_PSCCTL0_SENS_PNGDEC_SHIFT        (25U)
/*! PNGDEC - PNGDEC Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_PNGDEC(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_PNGDEC_SHIFT)) & CLKCTL4_PSCCTL0_SENS_PNGDEC_MASK)

#define CLKCTL4_PSCCTL0_SENS_EZHV_MASK           (0x4000000U)
#define CLKCTL4_PSCCTL0_SENS_EZHV_SHIFT          (26U)
/*! EZHV - EZHV Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_EZHV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_EZHV_SHIFT)) & CLKCTL4_PSCCTL0_SENS_EZHV_MASK)

#define CLKCTL4_PSCCTL0_SENS_AXBS_EZH_MASK       (0x10000000U)
#define CLKCTL4_PSCCTL0_SENS_AXBS_EZH_SHIFT      (28U)
/*! AXBS_EZH - AXBS for EZHV Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_AXBS_EZH(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_AXBS_EZH_SHIFT)) & CLKCTL4_PSCCTL0_SENS_AXBS_EZH_MASK)

#define CLKCTL4_PSCCTL0_SENS_GLIKEY2_MASK        (0x20000000U)
#define CLKCTL4_PSCCTL0_SENS_GLIKEY2_SHIFT       (29U)
/*! GLIKEY2 - GLIKEY2 Clock
 *  0b1..Enable
 *  0b0..Disable
 */
#define CLKCTL4_PSCCTL0_SENS_GLIKEY2(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_GLIKEY2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_GLIKEY2_MASK)
/*! @} */

/*! @name PSCCTL1_SENS - VDD1_SENSE Media Peripheral Clock Control 1 */
/*! @{ */

#define CLKCTL4_PSCCTL1_SENS_USB0_MASK           (0x1U)
#define CLKCTL4_PSCCTL1_SENS_USB0_SHIFT          (0U)
/*! USB0 - USB0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_SENS_USB0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_USB0_SHIFT)) & CLKCTL4_PSCCTL1_SENS_USB0_MASK)

#define CLKCTL4_PSCCTL1_SENS_USB1_MASK           (0x4U)
#define CLKCTL4_PSCCTL1_SENS_USB1_SHIFT          (2U)
/*! USB1 - USB1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_SENS_USB1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_USB1_SHIFT)) & CLKCTL4_PSCCTL1_SENS_USB1_MASK)

#define CLKCTL4_PSCCTL1_SENS_USDHC0_MASK         (0x10U)
#define CLKCTL4_PSCCTL1_SENS_USDHC0_SHIFT        (4U)
/*! uSDHC0 - uSDHC0 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_SENS_USDHC0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_USDHC0_SHIFT)) & CLKCTL4_PSCCTL1_SENS_USDHC0_MASK)

#define CLKCTL4_PSCCTL1_SENS_USDHC1_MASK         (0x20U)
#define CLKCTL4_PSCCTL1_SENS_USDHC1_SHIFT        (5U)
/*! uSDHC1 - uSDHC1 Clock
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_SENS_USDHC1(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_USDHC1_SHIFT)) & CLKCTL4_PSCCTL1_SENS_USDHC1_MASK)
/*! @} */

/*! @name PSCCTL0_SENS_SET - VDD1_SENSE Media Peripheral Clock Control 0 Set */
/*! @{ */

#define CLKCTL4_PSCCTL0_SENS_SET_VGPU_MASK       (0x4U)
#define CLKCTL4_PSCCTL0_SENS_SET_VGPU_SHIFT      (2U)
/*! VGPU - VGPU Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_VGPU(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_VGPU_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_VGPU_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_MIPI_DSI_HOST_MASK (0x10U)
#define CLKCTL4_PSCCTL0_SENS_SET_MIPI_DSI_HOST_SHIFT (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_MIPI_DSI_HOST(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_MIPI_DSI_HOST_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_MIPI_DSI_HOST_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_LPSPI16_MASK    (0x20U)
#define CLKCTL4_PSCCTL0_SENS_SET_LPSPI16_SHIFT   (5U)
/*! LPSPI16 - LPSPI16 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_LPSPI16(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_LPSPI16_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_LPSPI16_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_LPSPI14_MASK    (0x40U)
#define CLKCTL4_PSCCTL0_SENS_SET_LPSPI14_SHIFT   (6U)
/*! LPSPI14 - LPSPI14 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_LPSPI14(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_LPSPI14_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_LPSPI14_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_XSPI2_MASK      (0x100U)
#define CLKCTL4_PSCCTL0_SENS_SET_XSPI2_SHIFT     (8U)
/*! XSPI2 - XSPI2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_XSPI2(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_XSPI2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_XSPI2_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_MMU2_MASK       (0x800U)
#define CLKCTL4_PSCCTL0_SENS_SET_MMU2_SHIFT      (11U)
/*! MMU2 - MMU2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_MMU2(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_MMU2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_MMU2_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_GLIKEY5_MASK    (0x2000U)
#define CLKCTL4_PSCCTL0_SENS_SET_GLIKEY5_SHIFT   (13U)
/*! GLIKEY5 - GLIKEY5 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_GLIKEY5(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_GLIKEY5_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_GLIKEY5_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_FLEXIO0_MASK    (0x8000U)
#define CLKCTL4_PSCCTL0_SENS_SET_FLEXIO0_SHIFT   (15U)
/*! FLEXIO0 - FLEXIO0 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_FLEXIO0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_FLEXIO0_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_FLEXIO0_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_LCDIF_MASK      (0x400000U)
#define CLKCTL4_PSCCTL0_SENS_SET_LCDIF_SHIFT     (22U)
/*! LCDIF - LCDIF Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_LCDIF(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_LCDIF_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_LCDIF_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_SYSCON4_MASK    (0x800000U)
#define CLKCTL4_PSCCTL0_SENS_SET_SYSCON4_SHIFT   (23U)
/*! SYSCON4 - SYSCON4 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_SYSCON4(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_SYSCON4_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_SYSCON4_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_JPEGDEC_MASK    (0x1000000U)
#define CLKCTL4_PSCCTL0_SENS_SET_JPEGDEC_SHIFT   (24U)
/*! JPEGDEC - JPEGDEC Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_JPEGDEC(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_JPEGDEC_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_JPEGDEC_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_PNGDEC_MASK     (0x2000000U)
#define CLKCTL4_PSCCTL0_SENS_SET_PNGDEC_SHIFT    (25U)
/*! PNGDEC - PNGDEC Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_PNGDEC(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_PNGDEC_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_PNGDEC_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_EZHV_MASK       (0x4000000U)
#define CLKCTL4_PSCCTL0_SENS_SET_EZHV_SHIFT      (26U)
/*! EZHV - EZHV Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_EZHV(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_EZHV_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_EZHV_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_AXBS_EZH_MASK   (0x10000000U)
#define CLKCTL4_PSCCTL0_SENS_SET_AXBS_EZH_SHIFT  (28U)
/*! AXBS_EZH - AXBS for EZHV Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_AXBS_EZH(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_AXBS_EZH_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_AXBS_EZH_MASK)

#define CLKCTL4_PSCCTL0_SENS_SET_GLIKEY2_MASK    (0x20000000U)
#define CLKCTL4_PSCCTL0_SENS_SET_GLIKEY2_SHIFT   (29U)
/*! GLIKEY2 - GLIKEY2 Clock
 *  0b1..Enable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_SET_GLIKEY2(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_SET_GLIKEY2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_SET_GLIKEY2_MASK)
/*! @} */

/*! @name PSCCTL1_SENS_SET - VDD1_SENSE Media Peripheral Clock Control 1 Set */
/*! @{ */

#define CLKCTL4_PSCCTL1_SENS_SET_USB0_MASK       (0x1U)
#define CLKCTL4_PSCCTL1_SENS_SET_USB0_SHIFT      (0U)
/*! USB0 - USB0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_SENS_SET_USB0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_SET_USB0_SHIFT)) & CLKCTL4_PSCCTL1_SENS_SET_USB0_MASK)

#define CLKCTL4_PSCCTL1_SENS_SET_USB1_MASK       (0x4U)
#define CLKCTL4_PSCCTL1_SENS_SET_USB1_SHIFT      (2U)
/*! USB1 - USB1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_SENS_SET_USB1(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_SET_USB1_SHIFT)) & CLKCTL4_PSCCTL1_SENS_SET_USB1_MASK)

#define CLKCTL4_PSCCTL1_SENS_SET_USDHC0_MASK     (0x10U)
#define CLKCTL4_PSCCTL1_SENS_SET_USDHC0_SHIFT    (4U)
/*! uSDHC0 - uSDHC0 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_SENS_SET_USDHC0(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_SET_USDHC0_SHIFT)) & CLKCTL4_PSCCTL1_SENS_SET_USDHC0_MASK)

#define CLKCTL4_PSCCTL1_SENS_SET_USDHC1_MASK     (0x20U)
#define CLKCTL4_PSCCTL1_SENS_SET_USDHC1_SHIFT    (5U)
/*! uSDHC1 - uSDHC1 Clock
 *  0b0..No effect
 *  0b1..Enable
 */
#define CLKCTL4_PSCCTL1_SENS_SET_USDHC1(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_SET_USDHC1_SHIFT)) & CLKCTL4_PSCCTL1_SENS_SET_USDHC1_MASK)
/*! @} */

/*! @name PSCCTL0_SENS_CLR - VDD1_SENSE Media Peripheral Clock Control 0 Clear */
/*! @{ */

#define CLKCTL4_PSCCTL0_SENS_CLR_VGPU_MASK       (0x4U)
#define CLKCTL4_PSCCTL0_SENS_CLR_VGPU_SHIFT      (2U)
/*! VGPU - VGPU Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_VGPU(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_VGPU_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_VGPU_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_MIPI_DSI_HOST_MASK (0x10U)
#define CLKCTL4_PSCCTL0_SENS_CLR_MIPI_DSI_HOST_SHIFT (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_MIPI_DSI_HOST(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_MIPI_DSI_HOST_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_MIPI_DSI_HOST_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_LPSPI16_MASK    (0x20U)
#define CLKCTL4_PSCCTL0_SENS_CLR_LPSPI16_SHIFT   (5U)
/*! LPSPI16 - LPSPI16 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_LPSPI16(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_LPSPI16_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_LPSPI16_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_LPSPI14_MASK    (0x40U)
#define CLKCTL4_PSCCTL0_SENS_CLR_LPSPI14_SHIFT   (6U)
/*! LPSPI14 - LPSPI14 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_LPSPI14(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_LPSPI14_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_LPSPI14_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_XSPI2_MASK      (0x100U)
#define CLKCTL4_PSCCTL0_SENS_CLR_XSPI2_SHIFT     (8U)
/*! XSPI2 - XSPI2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_XSPI2(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_XSPI2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_XSPI2_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_MMU2_MASK       (0x800U)
#define CLKCTL4_PSCCTL0_SENS_CLR_MMU2_SHIFT      (11U)
/*! MMU2 - MMU2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_MMU2(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_MMU2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_MMU2_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY5_MASK    (0x2000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY5_SHIFT   (13U)
/*! GLIKEY5 - GLIKEY5 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY5(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY5_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY5_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_FLEXIO0_MASK    (0x8000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_FLEXIO0_SHIFT   (15U)
/*! FLEXIO0 - FLEXIO0 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_FLEXIO0(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_FLEXIO0_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_FLEXIO0_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_LCDIF_MASK      (0x400000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_LCDIF_SHIFT     (22U)
/*! LCDIF - LCDIF Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_LCDIF(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_LCDIF_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_LCDIF_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_SYSCON4_MASK    (0x800000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_SYSCON4_SHIFT   (23U)
/*! SYSCON4 - SYSCON4 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_SYSCON4(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_SYSCON4_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_SYSCON4_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_JPEGDEC_MASK    (0x1000000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_JPEGDEC_SHIFT   (24U)
/*! JPEGDEC - JPEGDEC Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_JPEGDEC(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_JPEGDEC_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_JPEGDEC_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_PNGDEC_MASK     (0x2000000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_PNGDEC_SHIFT    (25U)
/*! PNGDEC - PNG Decoder Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_PNGDEC(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_PNGDEC_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_PNGDEC_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_EZHV_MASK       (0x4000000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_EZHV_SHIFT      (26U)
/*! EZHV - EZHV Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_EZHV(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_EZHV_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_EZHV_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_AXBS_EZH_MASK   (0x10000000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_AXBS_EZH_SHIFT  (28U)
/*! AXBS_EZH - AXBS_EZHV Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_AXBS_EZH(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_AXBS_EZH_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_AXBS_EZH_MASK)

#define CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY2_MASK    (0x20000000U)
#define CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY2_SHIFT   (29U)
/*! GLIKEY2 - GLIKEY2 Clock
 *  0b1..Disable
 *  0b0..No effect
 */
#define CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY2(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY2_SHIFT)) & CLKCTL4_PSCCTL0_SENS_CLR_GLIKEY2_MASK)
/*! @} */

/*! @name PSCCTL1_SENS_CLR - VDD1_SENSE Media Peripheral Clock Control 1 Clear */
/*! @{ */

#define CLKCTL4_PSCCTL1_SENS_CLR_USB0_MASK       (0x1U)
#define CLKCTL4_PSCCTL1_SENS_CLR_USB0_SHIFT      (0U)
/*! USB0 - USB0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL4_PSCCTL1_SENS_CLR_USB0(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_CLR_USB0_SHIFT)) & CLKCTL4_PSCCTL1_SENS_CLR_USB0_MASK)

#define CLKCTL4_PSCCTL1_SENS_CLR_USB1_MASK       (0x4U)
#define CLKCTL4_PSCCTL1_SENS_CLR_USB1_SHIFT      (2U)
/*! USB1 - USB1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL4_PSCCTL1_SENS_CLR_USB1(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_CLR_USB1_SHIFT)) & CLKCTL4_PSCCTL1_SENS_CLR_USB1_MASK)

#define CLKCTL4_PSCCTL1_SENS_CLR_USDHC0_MASK     (0x10U)
#define CLKCTL4_PSCCTL1_SENS_CLR_USDHC0_SHIFT    (4U)
/*! uSDHC0 - uSDHC0 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL4_PSCCTL1_SENS_CLR_USDHC0(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_CLR_USDHC0_SHIFT)) & CLKCTL4_PSCCTL1_SENS_CLR_USDHC0_MASK)

#define CLKCTL4_PSCCTL1_SENS_CLR_USDHC1_MASK     (0x20U)
#define CLKCTL4_PSCCTL1_SENS_CLR_USDHC1_SHIFT    (5U)
/*! uSDHC1 - uSDHC1 Clock
 *  0b0..No effect
 *  0b1..Disable
 */
#define CLKCTL4_PSCCTL1_SENS_CLR_USDHC1(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL4_PSCCTL1_SENS_CLR_USDHC1_SHIFT)) & CLKCTL4_PSCCTL1_SENS_CLR_USDHC1_MASK)
/*! @} */

/*! @name ONE_SRC_CLKSLICE_ENABLE_SENSE - One Source Clock Slice Enable for VDD1_SENSE Core */
/*! @{ */

#define CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_SENSE_USBPHY_REFCLK_EN_MASK (0x1U)
#define CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_SENSE_USBPHY_REFCLK_EN_SHIFT (0U)
/*! USBPHY_REFCLK_EN - USBPHY0 Reference Clock
 *  0b0..Gates USBPHY0 reference clock.
 *  0b1..Enables USBPHY0 reference clock.
 */
#define CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_SENSE_USBPHY_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_SENSE_USBPHY_REFCLK_EN_SHIFT)) & CLKCTL4_ONE_SRC_CLKSLICE_ENABLE_SENSE_USBPHY_REFCLK_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CLKCTL4_Register_Masks */


/* CLKCTL4 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CLKCTL4 base address */
  #define CLKCTL4_BASE                             (0x500A1000u)
  /** Peripheral CLKCTL4 base address */
  #define CLKCTL4_BASE_NS                          (0x400A1000u)
  /** Peripheral CLKCTL4 base pointer */
  #define CLKCTL4                                  ((CLKCTL4_Type *)CLKCTL4_BASE)
  /** Peripheral CLKCTL4 base pointer */
  #define CLKCTL4_NS                               ((CLKCTL4_Type *)CLKCTL4_BASE_NS)
  /** Array initializer of CLKCTL4 peripheral base addresses */
  #define CLKCTL4_BASE_ADDRS                       { CLKCTL4_BASE }
  /** Array initializer of CLKCTL4 peripheral base pointers */
  #define CLKCTL4_BASE_PTRS                        { CLKCTL4 }
  /** Array initializer of CLKCTL4 peripheral base addresses */
  #define CLKCTL4_BASE_ADDRS_NS                    { CLKCTL4_BASE_NS }
  /** Array initializer of CLKCTL4 peripheral base pointers */
  #define CLKCTL4_BASE_PTRS_NS                     { CLKCTL4_NS }
#else
  /** Peripheral CLKCTL4 base address */
  #define CLKCTL4_BASE                             (0x400A1000u)
  /** Peripheral CLKCTL4 base pointer */
  #define CLKCTL4                                  ((CLKCTL4_Type *)CLKCTL4_BASE)
  /** Array initializer of CLKCTL4 peripheral base addresses */
  #define CLKCTL4_BASE_ADDRS                       { CLKCTL4_BASE }
  /** Array initializer of CLKCTL4 peripheral base pointers */
  #define CLKCTL4_BASE_PTRS                        { CLKCTL4 }
#endif

/*!
 * @}
 */ /* end of group CLKCTL4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CMP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
 * @{
 */

/** CMP - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t C0;                                /**< CMP Control 0, offset: 0x8 */
  __IO uint32_t C1;                                /**< CMP Control 1, offset: 0xC */
       uint8_t RESERVED_0[4];
  __IO uint32_t C3;                                /**< CMP Control 3, offset: 0x14 */
} CMP_Type;

/* ----------------------------------------------------------------------------
   -- CMP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMP_Register_Masks CMP Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define CMP_VERID_FEATURE_MASK                   (0xFFFFU)
#define CMP_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number */
#define CMP_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)

#define CMP_VERID_MINOR_MASK                     (0xFF0000U)
#define CMP_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define CMP_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)

#define CMP_VERID_MAJOR_MASK                     (0xFF000000U)
#define CMP_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define CMP_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define CMP_PARAM_PARAM_MASK                     (0xFFFFFFFFU)
#define CMP_PARAM_PARAM_SHIFT                    (0U)
/*! PARAM - Parameters */
#define CMP_PARAM_PARAM(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
/*! @} */

/*! @name C0 - CMP Control 0 */
/*! @{ */

#define CMP_C0_HYSTCTR_MASK                      (0x3U)
#define CMP_C0_HYSTCTR_SHIFT                     (0U)
/*! HYSTCTR - Comparator Hard Block Hysteresis Control
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define CMP_C0_HYSTCTR(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)

#define CMP_C0_FILTER_CNT_MASK                   (0x70U)
#define CMP_C0_FILTER_CNT_SHIFT                  (4U)
/*! FILTER_CNT - Filter Sample Count
 *  0b000..Filter is disabled
 *  0b001..One consecutive sample
 *  0b010..Two consecutive samples
 *  0b011..Three consecutive samples
 *  0b100..Four consecutive samples
 *  0b101..Five consecutive samples
 *  0b110..Six consecutive samples
 *  0b111..Seven consecutive samples
 */
#define CMP_C0_FILTER_CNT(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)

#define CMP_C0_EN_MASK                           (0x100U)
#define CMP_C0_EN_SHIFT                          (8U)
/*! EN - Analog Comparator Module Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C0_EN(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)

#define CMP_C0_OPE_MASK                          (0x200U)
#define CMP_C0_OPE_SHIFT                         (9U)
/*! OPE - Comparator Output Pin Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C0_OPE(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)

#define CMP_C0_COS_MASK                          (0x400U)
#define CMP_C0_COS_SHIFT                         (10U)
/*! COS - Comparator Output Select
 *  0b0..COUT
 *  0b1..COUTA
 */
#define CMP_C0_COS(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)

#define CMP_C0_INVT_MASK                         (0x800U)
#define CMP_C0_INVT_SHIFT                        (11U)
/*! INVT - Comparator Invert
 *  0b0..Do not invert
 *  0b1..Invert
 */
#define CMP_C0_INVT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)

#define CMP_C0_PMODE_MASK                        (0x1000U)
#define CMP_C0_PMODE_SHIFT                       (12U)
/*! PMODE - Power Mode Select
 *  0b0..Low-speed (LS)
 *  0b1..High-speed (HS)
 */
#define CMP_C0_PMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)

#define CMP_C0_FPR_MASK                          (0xFF0000U)
#define CMP_C0_FPR_SHIFT                         (16U)
/*! FPR - Filter Sample Period */
#define CMP_C0_FPR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)

#define CMP_C0_COUT_MASK                         (0x1000000U)
#define CMP_C0_COUT_SHIFT                        (24U)
/*! COUT - Analog Comparator Output */
#define CMP_C0_COUT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)

#define CMP_C0_CFF_MASK                          (0x2000000U)
#define CMP_C0_CFF_SHIFT                         (25U)
/*! CFF - Analog Comparator Flag Falling
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define CMP_C0_CFF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)

#define CMP_C0_CFR_MASK                          (0x4000000U)
#define CMP_C0_CFR_SHIFT                         (26U)
/*! CFR - Analog Comparator Flag Rising
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define CMP_C0_CFR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)

#define CMP_C0_IEF_MASK                          (0x8000000U)
#define CMP_C0_IEF_SHIFT                         (27U)
/*! IEF - Comparator Interrupt Enable Falling
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C0_IEF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)

#define CMP_C0_IER_MASK                          (0x10000000U)
#define CMP_C0_IER_SHIFT                         (28U)
/*! IER - Comparator Interrupt Enable Rising
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C0_IER(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)

#define CMP_C0_DMAEN_MASK                        (0x40000000U)
#define CMP_C0_DMAEN_SHIFT                       (30U)
/*! DMAEN - DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C0_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)

#define CMP_C0_LINKEN_MASK                       (0x80000000U)
#define CMP_C0_LINKEN_SHIFT                      (31U)
/*! LINKEN - CMP to DAC Link Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C0_LINKEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
/*! @} */

/*! @name C1 - CMP Control 1 */
/*! @{ */

#define CMP_C1_VOSEL_MASK                        (0xFFU)
#define CMP_C1_VOSEL_SHIFT                       (0U)
/*! VOSEL - DAC Output Voltage Select */
#define CMP_C1_VOSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)

#define CMP_C1_DMODE_MASK                        (0x100U)
#define CMP_C1_DMODE_SHIFT                       (8U)
/*! DMODE - DAC Mode Select
 *  0b0..Low-Speed and Low-Power mode
 *  0b1..High-Speed and High-Power mode
 */
#define CMP_C1_DMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)

#define CMP_C1_VRSEL_MASK                        (0x200U)
#define CMP_C1_VRSEL_SHIFT                       (9U)
/*! VRSEL - Supply Voltage Reference Source Select
 *  0b0..Vin1
 *  0b1..Vin2
 */
#define CMP_C1_VRSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)

#define CMP_C1_DACEN_MASK                        (0x400U)
#define CMP_C1_DACEN_SHIFT                       (10U)
/*! DACEN - DAC Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C1_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)

#define CMP_C1_MSEL_MASK                         (0x7000000U)
#define CMP_C1_MSEL_SHIFT                        (24U)
/*! MSEL - Minus Input MUX Control
 *  0b000..Internal negative input 0 for minus channel (internal minus input)
 *  0b001..External input 1 for minus channel (INA_1P8[1])
 *  0b010..External input 2 for minus channel (INA_1P8[2])
 *  0b011..External input 3 for minus channel (INA_1P8[3])
 *  0b100..External input 4 for minus channel (INA_1P8[4])
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Internal 8-bit DAC output
 */
#define CMP_C1_MSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)

#define CMP_C1_PSEL_MASK                         (0x70000000U)
#define CMP_C1_PSEL_SHIFT                        (28U)
/*! PSEL - Plus Input MUX Control
 *  0b000..Internal positive input 0 for plus channel (internal plus input)
 *  0b001..External input 1 for plus channel (INA_1P8[1])
 *  0b010..External input 2 for plus channel (INA_1P8[2])
 *  0b011..External input 3 for plus channel (INA_1P8[3])
 *  0b100..External input 4 for plus channel (INA_1P8[4])
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Internal 8-bit DAC output
 */
#define CMP_C1_PSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
/*! @} */

/*! @name C3 - CMP Control 3 */
/*! @{ */

#define CMP_C3_NCHCTEN_MASK                      (0x1000000U)
#define CMP_C3_NCHCTEN_SHIFT                     (24U)
/*! NCHCTEN - Negative Channel Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C3_NCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)

#define CMP_C3_PCHCTEN_MASK                      (0x10000000U)
#define CMP_C3_PCHCTEN_SHIFT                     (28U)
/*! PCHCTEN - Positive Channel Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CMP_C3_PCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CMP_Register_Masks */


/* CMP - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ACMP0 base address */
  #define ACMP0_BASE                               (0x5020B000u)
  /** Peripheral ACMP0 base address */
  #define ACMP0_BASE_NS                            (0x4020B000u)
  /** Peripheral ACMP0 base pointer */
  #define ACMP0                                    ((CMP_Type *)ACMP0_BASE)
  /** Peripheral ACMP0 base pointer */
  #define ACMP0_NS                                 ((CMP_Type *)ACMP0_BASE_NS)
  /** Array initializer of CMP peripheral base addresses */
  #define CMP_BASE_ADDRS                           { ACMP0_BASE }
  /** Array initializer of CMP peripheral base pointers */
  #define CMP_BASE_PTRS                            { ACMP0 }
  /** Array initializer of CMP peripheral base addresses */
  #define CMP_BASE_ADDRS_NS                        { ACMP0_BASE_NS }
  /** Array initializer of CMP peripheral base pointers */
  #define CMP_BASE_PTRS_NS                         { ACMP0_NS }
#else
  /** Peripheral ACMP0 base address */
  #define ACMP0_BASE                               (0x4020B000u)
  /** Peripheral ACMP0 base pointer */
  #define ACMP0                                    ((CMP_Type *)ACMP0_BASE)
  /** Array initializer of CMP peripheral base addresses */
  #define CMP_BASE_ADDRS                           { ACMP0_BASE }
  /** Array initializer of CMP peripheral base pointers */
  #define CMP_BASE_PTRS                            { ACMP0 }
#endif

/*!
 * @}
 */ /* end of group CMP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
 * @{
 */

/** CRC - Register Layout Typedef */
typedef struct {
  union {                                          /* offset: 0x0 */
    struct {                                         /* offset: 0x0 */
      __IO uint8_t DATALL;                             /**< CRC_DATALL register, offset: 0x0 */
      __IO uint8_t DATALU;                             /**< CRC_DATALU register, offset: 0x1 */
      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register, offset: 0x2 */
      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register, offset: 0x3 */
    } ACCESS8BIT;
    struct {                                         /* offset: 0x0 */
      __IO uint16_t DATAL;                             /**< CRC_DATAL register, offset: 0x0 */
      __IO uint16_t DATAH;                             /**< CRC_DATAH register, offset: 0x2 */
    } ACCESS16BIT;
    __IO uint32_t DATA;                              /**< Data, offset: 0x0 */
  };
  union {                                          /* offset: 0x4 */
    struct {                                         /* offset: 0x4 */
      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register, offset: 0x4 */
      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register, offset: 0x5 */
      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register, offset: 0x6 */
      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register, offset: 0x7 */
    } GPOLY_ACCESS8BIT;
    struct {                                         /* offset: 0x4 */
      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register, offset: 0x4 */
      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register, offset: 0x6 */
    } GPOLY_ACCESS16BIT;
    __IO uint32_t GPOLY;                             /**< Polynomial, offset: 0x4 */
  };
  union {                                          /* offset: 0x8 */
    struct {                                         /* offset: 0x8 */
           uint8_t RESERVED_0[3];
      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register, offset: 0xB */
    } CTRL_ACCESS8BIT;
    __IO uint32_t CTRL;                              /**< Control, offset: 0x8 */
  };
} CRC_Type;

/* ----------------------------------------------------------------------------
   -- CRC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CRC_Register_Masks CRC Register Masks
 * @{
 */

/*! @name DATALL - CRC_DATALL register */
/*! @{ */

#define CRC_DATALL_DATALL_MASK                   (0xFFU)
#define CRC_DATALL_DATALL_SHIFT                  (0U)
#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
/*! @} */

/*! @name DATALU - CRC_DATALU register */
/*! @{ */

#define CRC_DATALU_DATALU_MASK                   (0xFFU)
#define CRC_DATALU_DATALU_SHIFT                  (0U)
#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
/*! @} */

/*! @name DATAHL - CRC_DATAHL register */
/*! @{ */

#define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
#define CRC_DATAHL_DATAHL_SHIFT                  (0U)
#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
/*! @} */

/*! @name DATAHU - CRC_DATAHU register */
/*! @{ */

#define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
#define CRC_DATAHU_DATAHU_SHIFT                  (0U)
#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
/*! @} */

/*! @name DATAL - CRC_DATAL register */
/*! @{ */

#define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
#define CRC_DATAL_DATAL_SHIFT                    (0U)
#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
/*! @} */

/*! @name DATAH - CRC_DATAH register */
/*! @{ */

#define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
#define CRC_DATAH_DATAH_SHIFT                    (0U)
#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
/*! @} */

/*! @name DATA - Data */
/*! @{ */

#define CRC_DATA_LL_MASK                         (0xFFU)
#define CRC_DATA_LL_SHIFT                        (0U)
/*! LL - Lower Part of Low Byte */
#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)

#define CRC_DATA_LU_MASK                         (0xFF00U)
#define CRC_DATA_LU_SHIFT                        (8U)
/*! LU - Upper Part of Low Byte */
#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)

#define CRC_DATA_HL_MASK                         (0xFF0000U)
#define CRC_DATA_HL_SHIFT                        (16U)
/*! HL - Lower Part of High Byte */
#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)

#define CRC_DATA_HU_MASK                         (0xFF000000U)
#define CRC_DATA_HU_SHIFT                        (24U)
/*! HU - Upper Part of High Byte */
#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
/*! @} */

/*! @name GPOLYLL - CRC_GPOLYLL register */
/*! @{ */

#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
/*! @} */

/*! @name GPOLYLU - CRC_GPOLYLU register */
/*! @{ */

#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
/*! @} */

/*! @name GPOLYHL - CRC_GPOLYHL register */
/*! @{ */

#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
/*! @} */

/*! @name GPOLYHU - CRC_GPOLYHU register */
/*! @{ */

#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
/*! @} */

/*! @name GPOLYL - CRC_GPOLYL register */
/*! @{ */

#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
/*! @} */

/*! @name GPOLYH - CRC_GPOLYH register */
/*! @{ */

#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
/*! @} */

/*! @name GPOLY - Polynomial */
/*! @{ */

#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
#define CRC_GPOLY_LOW_SHIFT                      (0U)
/*! LOW - Low Half-Word */
#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)

#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
#define CRC_GPOLY_HIGH_SHIFT                     (16U)
/*! HIGH - High Half-Word */
#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
/*! @} */

/*! @name CTRLHU - CRC_CTRLHU register */
/*! @{ */

#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
/*! TCRC - TCRC
 *  0b0..16 bits
 *  0b1..32 bits
 */
#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)

#define CRC_CTRLHU_WAS_MASK                      (0x2U)
#define CRC_CTRLHU_WAS_SHIFT                     (1U)
/*! WAS - Write as Seed
 *  0b0..Data values
 *  0b1..Seed values
 */
#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)

#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
/*! FXOR - Complement Read of CRC Data Register
 *  0b0..Disables XOR on reading data.
 *  0b1..Inverts or complements the read value of the CRC Data.
 */
#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)

#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
/*! TOTR - Transpose Type for Read
 *  0b00..No transposition
 *  0b01..Bits in bytes are transposed, but bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed, no bits in a byte are transposed.
 */
#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)

#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
#define CRC_CTRLHU_TOT_SHIFT                     (6U)
/*! TOT - Transpose Type for Write
 *  0b00..No transposition
 *  0b01..Bits in bytes are transposed, but bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed, no bits in a byte are transposed.
 */
#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
/*! @} */

/*! @name CTRL - Control */
/*! @{ */

#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
#define CRC_CTRL_TCRC_SHIFT                      (24U)
/*! TCRC - TCRC
 *  0b0..16 bits
 *  0b1..32 bits
 */
#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)

#define CRC_CTRL_WAS_MASK                        (0x2000000U)
#define CRC_CTRL_WAS_SHIFT                       (25U)
/*! WAS - Write as Seed
 *  0b0..Data values
 *  0b1..Seed values
 */
#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)

#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
#define CRC_CTRL_FXOR_SHIFT                      (26U)
/*! FXOR - Complement Read of CRC Data Register
 *  0b0..Disables XOR on reading data.
 *  0b1..Inverts or complements the read value of the CRC Data.
 */
#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)

#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
#define CRC_CTRL_TOTR_SHIFT                      (28U)
/*! TOTR - Transpose Type for Read
 *  0b00..No transposition
 *  0b01..Bits in bytes are transposed, but bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed, no bits in a byte are transposed.
 */
#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)

#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
#define CRC_CTRL_TOT_SHIFT                       (30U)
/*! TOT - Transpose Type for Write
 *  0b00..No transposition
 *  0b01..Bits in bytes are transposed, but bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed, no bits in a byte are transposed.
 */
#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CRC_Register_Masks */


/* CRC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CRC base address */
  #define CRC_BASE                                 (0x50151000u)
  /** Peripheral CRC base address */
  #define CRC_BASE_NS                              (0x40151000u)
  /** Peripheral CRC base pointer */
  #define CRC                                      ((CRC_Type *)CRC_BASE)
  /** Peripheral CRC base pointer */
  #define CRC_NS                                   ((CRC_Type *)CRC_BASE_NS)
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS                           { CRC_BASE }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS                            { CRC }
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS_NS                        { CRC_BASE_NS }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS_NS                         { CRC_NS }
#else
  /** Peripheral CRC base address */
  #define CRC_BASE                                 (0x40151000u)
  /** Peripheral CRC base pointer */
  #define CRC                                      ((CRC_Type *)CRC_BASE)
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS                           { CRC_BASE }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS                            { CRC }
#endif

/*!
 * @}
 */ /* end of group CRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CTIMER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
 * @{
 */

/** CTIMER - Register Layout Typedef */
typedef struct {
  __IO uint32_t IR;                                /**< Interrupt, offset: 0x0 */
  __IO uint32_t TCR;                               /**< Timer Control, offset: 0x4 */
  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
  __IO uint32_t PR;                                /**< Prescale, offset: 0xC */
  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
  __IO uint32_t MCR;                               /**< Match Control, offset: 0x14 */
  __IO uint32_t MR[4];                             /**< Match, array offset: 0x18, array step: 0x4 */
  __IO uint32_t CCR;                               /**< Capture Control, offset: 0x28 */
  __I  uint32_t CR[4];                             /**< Capture, array offset: 0x2C, array step: 0x4 */
  __IO uint32_t EMR;                               /**< External Match, offset: 0x3C */
       uint8_t RESERVED_0[48];
  __IO uint32_t CTCR;                              /**< Count Control, offset: 0x70 */
  __IO uint32_t PWMC;                              /**< PWM Control, offset: 0x74 */
  __IO uint32_t MSR[4];                            /**< Match Shadow, array offset: 0x78, array step: 0x4 */
} CTIMER_Type;

/* ----------------------------------------------------------------------------
   -- CTIMER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
 * @{
 */

/*! @name IR - Interrupt */
/*! @{ */

#define CTIMER_IR_MR0INT_MASK                    (0x1U)
#define CTIMER_IR_MR0INT_SHIFT                   (0U)
/*! MR0INT - Interrupt Flag for Match Channel 0 Event */
#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)

#define CTIMER_IR_MR1INT_MASK                    (0x2U)
#define CTIMER_IR_MR1INT_SHIFT                   (1U)
/*! MR1INT - Interrupt Flag for Match Channel 1 Event */
#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)

#define CTIMER_IR_MR2INT_MASK                    (0x4U)
#define CTIMER_IR_MR2INT_SHIFT                   (2U)
/*! MR2INT - Interrupt Flag for Match Channel 2 Event */
#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)

#define CTIMER_IR_MR3INT_MASK                    (0x8U)
#define CTIMER_IR_MR3INT_SHIFT                   (3U)
/*! MR3INT - Interrupt Flag for Match Channel 3 Event */
#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)

#define CTIMER_IR_CR0INT_MASK                    (0x10U)
#define CTIMER_IR_CR0INT_SHIFT                   (4U)
/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */
#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)

#define CTIMER_IR_CR1INT_MASK                    (0x20U)
#define CTIMER_IR_CR1INT_SHIFT                   (5U)
/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */
#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)

#define CTIMER_IR_CR2INT_MASK                    (0x40U)
#define CTIMER_IR_CR2INT_SHIFT                   (6U)
/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */
#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)

#define CTIMER_IR_CR3INT_MASK                    (0x80U)
#define CTIMER_IR_CR3INT_SHIFT                   (7U)
/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */
#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
/*! @} */

/*! @name TCR - Timer Control */
/*! @{ */

#define CTIMER_TCR_CEN_MASK                      (0x1U)
#define CTIMER_TCR_CEN_SHIFT                     (0U)
/*! CEN - Counter Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)

#define CTIMER_TCR_CRST_MASK                     (0x2U)
#define CTIMER_TCR_CRST_SHIFT                    (1U)
/*! CRST - Counter Reset Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)

#define CTIMER_TCR_AGCEN_MASK                    (0x10U)
#define CTIMER_TCR_AGCEN_SHIFT                   (4U)
/*! AGCEN - Allow Global Count Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CTIMER_TCR_AGCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK)

#define CTIMER_TCR_ATCEN_MASK                    (0x20U)
#define CTIMER_TCR_ATCEN_SHIFT                   (5U)
/*! ATCEN - Allow Trigger Count Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define CTIMER_TCR_ATCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK)
/*! @} */

/*! @name TC - Timer Counter */
/*! @{ */

#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_TC_TCVAL_SHIFT                    (0U)
/*! TCVAL - Timer Counter Value */
#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
/*! @} */

/*! @name PR - Prescale */
/*! @{ */

#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_PR_PRVAL_SHIFT                    (0U)
/*! PRVAL - Prescale Reload Value */
#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
/*! @} */

/*! @name PC - Prescale Counter */
/*! @{ */

#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_PC_PCVAL_SHIFT                    (0U)
/*! PCVAL - Prescale Counter Value */
#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
/*! @} */

/*! @name MCR - Match Control */
/*! @{ */

#define CTIMER_MCR_MR0I_MASK                     (0x1U)
#define CTIMER_MCR_MR0I_SHIFT                    (0U)
/*! MR0I - Interrupt on MR0
 *  0b0..Does not generate
 *  0b1..Generates
 */
#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)

#define CTIMER_MCR_MR0R_MASK                     (0x2U)
#define CTIMER_MCR_MR0R_SHIFT                    (1U)
/*! MR0R - Reset on MR0
 *  0b0..Does not reset
 *  0b1..Resets
 */
#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)

#define CTIMER_MCR_MR0S_MASK                     (0x4U)
#define CTIMER_MCR_MR0S_SHIFT                    (2U)
/*! MR0S - Stop on MR0
 *  0b0..Does not stop
 *  0b1..Stops
 */
#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)

#define CTIMER_MCR_MR1I_MASK                     (0x8U)
#define CTIMER_MCR_MR1I_SHIFT                    (3U)
/*! MR1I - Interrupt on MR1
 *  0b0..Does not generate
 *  0b1..Generates
 */
#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)

#define CTIMER_MCR_MR1R_MASK                     (0x10U)
#define CTIMER_MCR_MR1R_SHIFT                    (4U)
/*! MR1R - Reset on MR1
 *  0b0..Does not reset
 *  0b1..Resets
 */
#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)

#define CTIMER_MCR_MR1S_MASK                     (0x20U)
#define CTIMER_MCR_MR1S_SHIFT                    (5U)
/*! MR1S - Stop on MR1
 *  0b0..Does not stop
 *  0b1..Stops
 */
#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)

#define CTIMER_MCR_MR2I_MASK                     (0x40U)
#define CTIMER_MCR_MR2I_SHIFT                    (6U)
/*! MR2I - Interrupt on MR2
 *  0b0..Does not generate
 *  0b1..Generates
 */
#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)

#define CTIMER_MCR_MR2R_MASK                     (0x80U)
#define CTIMER_MCR_MR2R_SHIFT                    (7U)
/*! MR2R - Reset on MR2
 *  0b0..Does not reset
 *  0b1..Resets
 */
#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)

#define CTIMER_MCR_MR2S_MASK                     (0x100U)
#define CTIMER_MCR_MR2S_SHIFT                    (8U)
/*! MR2S - Stop on MR2
 *  0b0..Does not stop
 *  0b1..Stops
 */
#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)

#define CTIMER_MCR_MR3I_MASK                     (0x200U)
#define CTIMER_MCR_MR3I_SHIFT                    (9U)
/*! MR3I - Interrupt on MR3
 *  0b0..Does not generate
 *  0b1..Generates
 */
#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)

#define CTIMER_MCR_MR3R_MASK                     (0x400U)
#define CTIMER_MCR_MR3R_SHIFT                    (10U)
/*! MR3R - Reset on MR3
 *  0b0..Does not reset
 *  0b1..Resets
 */
#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)

#define CTIMER_MCR_MR3S_MASK                     (0x800U)
#define CTIMER_MCR_MR3S_SHIFT                    (11U)
/*! MR3S - Stop on MR3
 *  0b0..Does not stop
 *  0b1..Stops
 */
#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)

#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
/*! MR0RL - Reload MR
 *  0b0..Does not reload
 *  0b1..Reloads
 */
#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)

#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
/*! MR1RL - Reload MR
 *  0b0..Does not reload
 *  0b1..Reloads
 */
#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)

#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
/*! MR2RL - Reload MR
 *  0b0..Does not reload
 *  0b1..Reloads
 */
#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)

#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
/*! MR3RL - Reload MR
 *  0b0..Does not reload
 *  0b1..Reloads
 */
#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
/*! @} */

/*! @name MR - Match */
/*! @{ */

#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
#define CTIMER_MR_MATCH_SHIFT                    (0U)
/*! MATCH - Timer Counter Match Value */
#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
/*! @} */

/* The count of CTIMER_MR */
#define CTIMER_MR_COUNT                          (4U)

/*! @name CCR - Capture Control */
/*! @{ */

#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
/*! CAP0RE - Rising Edge of Capture Channel 0
 *  0b0..Does not load
 *  0b1..Loads
 */
#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)

#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
/*! CAP0FE - Falling Edge of Capture Channel 0
 *  0b0..Does not load
 *  0b1..Loads
 */
#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)

#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
/*! CAP0I - Generate Interrupt on Channel 0 Capture Event
 *  0b0..Does not generate
 *  0b1..Generates
 */
#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)

#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
/*! CAP1RE - Rising Edge of Capture Channel 1
 *  0b0..Does not load
 *  0b1..Loads
 */
#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)

#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
/*! CAP1FE - Falling Edge of Capture Channel 1
 *  0b0..Does not load
 *  0b1..Loads
 */
#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)

#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
/*! CAP1I - Generate Interrupt on Channel 1 Capture Event
 *  0b0..Does not generates
 *  0b1..Generates
 */
#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)

#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
/*! CAP2RE - Rising Edge of Capture Channel 2
 *  0b0..Does not load
 *  0b1..Loads
 */
#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)

#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
/*! CAP2FE - Falling Edge of Capture Channel 2
 *  0b0..Does not load
 *  0b1..Loads
 */
#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)

#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
/*! CAP2I - Generate Interrupt on Channel 2 Capture Event
 *  0b0..Does not generate
 *  0b1..Generates
 */
#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)

#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
/*! CAP3RE - Rising Edge of Capture Channel 3
 *  0b0..Does not load
 *  0b1..Loads
 */
#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)

#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
/*! CAP3FE - Falling Edge of Capture Channel 3
 *  0b0..Does not load
 *  0b1..Loads
 */
#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)

#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
/*! CAP3I - Generate Interrupt on Channel 3 Capture Event
 *  0b0..Does not generate
 *  0b1..Generates
 */
#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
/*! @} */

/*! @name CR - Capture */
/*! @{ */

#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
#define CTIMER_CR_CAP_SHIFT                      (0U)
/*! CAP - Timer Counter Capture Value */
#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
/*! @} */

/* The count of CTIMER_CR */
#define CTIMER_CR_COUNT                          (4U)

/*! @name EMR - External Match */
/*! @{ */

#define CTIMER_EMR_EM0_MASK                      (0x1U)
#define CTIMER_EMR_EM0_SHIFT                     (0U)
/*! EM0 - External Match 0
 *  0b0..Low
 *  0b1..High
 */
#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)

#define CTIMER_EMR_EM1_MASK                      (0x2U)
#define CTIMER_EMR_EM1_SHIFT                     (1U)
/*! EM1 - External Match 1
 *  0b0..Low
 *  0b1..High
 */
#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)

#define CTIMER_EMR_EM2_MASK                      (0x4U)
#define CTIMER_EMR_EM2_SHIFT                     (2U)
/*! EM2 - External Match 2
 *  0b0..Low
 *  0b1..High
 */
#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)

#define CTIMER_EMR_EM3_MASK                      (0x8U)
#define CTIMER_EMR_EM3_SHIFT                     (3U)
/*! EM3 - External Match 3
 *  0b0..Low
 *  0b1..High
 */
#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)

#define CTIMER_EMR_EMC0_MASK                     (0x30U)
#define CTIMER_EMR_EMC0_SHIFT                    (4U)
/*! EMC0 - External Match Control 0
 *  0b00..Does nothing
 *  0b01..Goes low
 *  0b10..Goes high
 *  0b11..Toggles
 */
#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)

#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
#define CTIMER_EMR_EMC1_SHIFT                    (6U)
/*! EMC1 - External Match Control 1
 *  0b00..Does nothing
 *  0b01..Goes low
 *  0b10..Goes high
 *  0b11..Toggles
 */
#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)

#define CTIMER_EMR_EMC2_MASK                     (0x300U)
#define CTIMER_EMR_EMC2_SHIFT                    (8U)
/*! EMC2 - External Match Control 2
 *  0b00..Does nothing
 *  0b01..Goes low
 *  0b10..Goes high
 *  0b11..Toggles
 */
#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)

#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
#define CTIMER_EMR_EMC3_SHIFT                    (10U)
/*! EMC3 - External Match Control 3
 *  0b00..Does nothing
 *  0b01..Goes low
 *  0b10..Goes high
 *  0b11..Toggles
 */
#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
/*! @} */

/*! @name CTCR - Count Control */
/*! @{ */

#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
/*! CTMODE - Counter Timer Mode
 *  0b00..Timer mode
 *  0b01..Counter mode rising edge
 *  0b10..Counter mode falling edge
 *  0b11..Counter mode dual edge
 */
#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)

#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
/*! CINSEL - Count Input Select
 *  0b00..Channel 0, CAPn[0] for CTIMERn
 *  0b01..Channel 1, CAPn[1] for CTIMERn
 *  0b10..Channel 2, CAPn[2] for CTIMERn
 *  0b11..Channel 3, CAPn[3] for CTIMERn
 */
#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)

#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
/*! ENCC - Capture Channel Enable */
#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)

#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
/*! SELCC - Edge Select
 *  0b000..Capture channel 0 rising edge
 *  0b001..Capture channel 0 falling edge
 *  0b010..Capture channel 1 rising edge
 *  0b011..Capture channel 1 falling edge
 *  0b100..Capture channel 2 rising edge
 *  0b101..Capture channel 2 falling edge
 *  0b110..Capture channel 3 rising edge
 *  0b111..Capture channel 3 falling edge
 */
#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
/*! @} */

/*! @name PWMC - PWM Control */
/*! @{ */

#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
/*! PWMEN0 - PWM Mode Enable for Channel 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)

#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
/*! PWMEN1 - PWM Mode Enable for Channel 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)

#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
/*! PWMEN2 - PWM Mode Enable for Channel 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)

#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
/*! PWMEN3 - PWM Mode Enable for Channel 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
/*! @} */

/*! @name MSR - Match Shadow */
/*! @{ */

#define CTIMER_MSR_MATCH_SHADOW_MASK             (0xFFFFFFFFU)
#define CTIMER_MSR_MATCH_SHADOW_SHIFT            (0U)
/*! MATCH_SHADOW - Timer Counter Match Shadow Value */
#define CTIMER_MSR_MATCH_SHADOW(x)               (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
/*! @} */

/* The count of CTIMER_MSR */
#define CTIMER_MSR_COUNT                         (4U)


/*!
 * @}
 */ /* end of group CTIMER_Register_Masks */


/* CTIMER - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CTIMER0 base address */
  #define CTIMER0_BASE                             (0x50028000u)
  /** Peripheral CTIMER0 base address */
  #define CTIMER0_BASE_NS                          (0x40028000u)
  /** Peripheral CTIMER0 base pointer */
  #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
  /** Peripheral CTIMER0 base pointer */
  #define CTIMER0_NS                               ((CTIMER_Type *)CTIMER0_BASE_NS)
  /** Peripheral CTIMER1 base address */
  #define CTIMER1_BASE                             (0x50029000u)
  /** Peripheral CTIMER1 base address */
  #define CTIMER1_BASE_NS                          (0x40029000u)
  /** Peripheral CTIMER1 base pointer */
  #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
  /** Peripheral CTIMER1 base pointer */
  #define CTIMER1_NS                               ((CTIMER_Type *)CTIMER1_BASE_NS)
  /** Peripheral CTIMER2 base address */
  #define CTIMER2_BASE                             (0x5002A000u)
  /** Peripheral CTIMER2 base address */
  #define CTIMER2_BASE_NS                          (0x4002A000u)
  /** Peripheral CTIMER2 base pointer */
  #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
  /** Peripheral CTIMER2 base pointer */
  #define CTIMER2_NS                               ((CTIMER_Type *)CTIMER2_BASE_NS)
  /** Peripheral CTIMER3 base address */
  #define CTIMER3_BASE                             (0x5002B000u)
  /** Peripheral CTIMER3 base address */
  #define CTIMER3_BASE_NS                          (0x4002B000u)
  /** Peripheral CTIMER3 base pointer */
  #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
  /** Peripheral CTIMER3 base pointer */
  #define CTIMER3_NS                               ((CTIMER_Type *)CTIMER3_BASE_NS)
  /** Peripheral CTIMER4 base address */
  #define CTIMER4_BASE                             (0x5002C000u)
  /** Peripheral CTIMER4 base address */
  #define CTIMER4_BASE_NS                          (0x4002C000u)
  /** Peripheral CTIMER4 base pointer */
  #define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
  /** Peripheral CTIMER4 base pointer */
  #define CTIMER4_NS                               ((CTIMER_Type *)CTIMER4_BASE_NS)
  /** Array initializer of CTIMER peripheral base addresses */
  #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
  /** Array initializer of CTIMER peripheral base pointers */
  #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
  /** Array initializer of CTIMER peripheral base addresses */
  #define CTIMER_BASE_ADDRS_NS                     { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS }
  /** Array initializer of CTIMER peripheral base pointers */
  #define CTIMER_BASE_PTRS_NS                      { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS }
#else
  /** Peripheral CTIMER0 base address */
  #define CTIMER0_BASE                             (0x40028000u)
  /** Peripheral CTIMER0 base pointer */
  #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
  /** Peripheral CTIMER1 base address */
  #define CTIMER1_BASE                             (0x40029000u)
  /** Peripheral CTIMER1 base pointer */
  #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
  /** Peripheral CTIMER2 base address */
  #define CTIMER2_BASE                             (0x4002A000u)
  /** Peripheral CTIMER2 base pointer */
  #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
  /** Peripheral CTIMER3 base address */
  #define CTIMER3_BASE                             (0x4002B000u)
  /** Peripheral CTIMER3 base pointer */
  #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
  /** Peripheral CTIMER4 base address */
  #define CTIMER4_BASE                             (0x4002C000u)
  /** Peripheral CTIMER4 base pointer */
  #define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
  /** Array initializer of CTIMER peripheral base addresses */
  #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
  /** Array initializer of CTIMER peripheral base pointers */
  #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
#endif
/** Interrupt vectors for the CTIMER peripheral type */
#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }

/*!
 * @}
 */ /* end of group CTIMER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DEBUG_MAILBOX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DEBUG_MAILBOX_Peripheral_Access_Layer DEBUG_MAILBOX Peripheral Access Layer
 * @{
 */

/** DEBUG_MAILBOX - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSW;                               /**< Command and Status Word, offset: 0x0 */
  __IO uint32_t REQUEST;                           /**< Request Value, offset: 0x4 */
  __IO uint32_t RETURN;                            /**< Return Value, offset: 0x8 */
       uint8_t RESERVED_0[240];
  __I  uint32_t ID;                                /**< Identification, offset: 0xFC */
} DEBUG_MAILBOX_Type;

/* ----------------------------------------------------------------------------
   -- DEBUG_MAILBOX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DEBUG_MAILBOX_Register_Masks DEBUG_MAILBOX Register Masks
 * @{
 */

/*! @name CSW - Command and Status Word */
/*! @{ */

#define DEBUG_MAILBOX_CSW_RESYNCH_REQ_MASK       (0x1U)
#define DEBUG_MAILBOX_CSW_RESYNCH_REQ_SHIFT      (0U)
/*! RESYNCH_REQ - Resynchronization Request
 *  0b0..No request
 *  0b1..Request for resynchronization
 */
#define DEBUG_MAILBOX_CSW_RESYNCH_REQ(x)         (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUG_MAILBOX_CSW_RESYNCH_REQ_MASK)

#define DEBUG_MAILBOX_CSW_REQ_PENDING_MASK       (0x2U)
#define DEBUG_MAILBOX_CSW_REQ_PENDING_SHIFT      (1U)
/*! REQ_PENDING - Request Pending
 *  0b0..No request pending
 *  0b1..Request for resynchronization pending
 */
#define DEBUG_MAILBOX_CSW_REQ_PENDING(x)         (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUG_MAILBOX_CSW_REQ_PENDING_MASK)

#define DEBUG_MAILBOX_CSW_DBG_OR_ERR_MASK        (0x4U)
#define DEBUG_MAILBOX_CSW_DBG_OR_ERR_SHIFT       (2U)
/*! DBG_OR_ERR - DBGMB Overrun Error
 *  0b0..No overrun
 *  0b1..Overrun occurred
 */
#define DEBUG_MAILBOX_CSW_DBG_OR_ERR(x)          (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUG_MAILBOX_CSW_DBG_OR_ERR_MASK)

#define DEBUG_MAILBOX_CSW_AHB_OR_ERR_MASK        (0x8U)
#define DEBUG_MAILBOX_CSW_AHB_OR_ERR_SHIFT       (3U)
/*! AHB_OR_ERR - AHB Overrun Error
 *  0b0..No overrun
 *  0b1..Overrun occurred
 */
#define DEBUG_MAILBOX_CSW_AHB_OR_ERR(x)          (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUG_MAILBOX_CSW_AHB_OR_ERR_MASK)

#define DEBUG_MAILBOX_CSW_SOFT_RESET_MASK        (0x10U)
#define DEBUG_MAILBOX_CSW_SOFT_RESET_SHIFT       (4U)
/*! SOFT_RESET - Soft Reset
 *  0b0..No effect
 *  0b1..Reset
 */
#define DEBUG_MAILBOX_CSW_SOFT_RESET(x)          (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUG_MAILBOX_CSW_SOFT_RESET_MASK)

#define DEBUG_MAILBOX_CSW_CHIP_RESET_REQ_MASK    (0x20U)
#define DEBUG_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT   (5U)
/*! CHIP_RESET_REQ - Chip Reset Request
 *  0b0..No effect
 *  0b1..Reset
 */
#define DEBUG_MAILBOX_CSW_CHIP_RESET_REQ(x)      (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUG_MAILBOX_CSW_CHIP_RESET_REQ_MASK)
/*! @} */

/*! @name REQUEST - Request Value */
/*! @{ */

#define DEBUG_MAILBOX_REQUEST_REQUEST_MASK       (0xFFFFFFFFU)
#define DEBUG_MAILBOX_REQUEST_REQUEST_SHIFT      (0U)
/*! REQUEST - Request Value */
#define DEBUG_MAILBOX_REQUEST_REQUEST(x)         (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUG_MAILBOX_REQUEST_REQUEST_MASK)
/*! @} */

/*! @name RETURN - Return Value */
/*! @{ */

#define DEBUG_MAILBOX_RETURN_RET_MASK            (0xFFFFFFFFU)
#define DEBUG_MAILBOX_RETURN_RET_SHIFT           (0U)
/*! RET - Return Value */
#define DEBUG_MAILBOX_RETURN_RET(x)              (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_RETURN_RET_SHIFT)) & DEBUG_MAILBOX_RETURN_RET_MASK)
/*! @} */

/*! @name ID - Identification */
/*! @{ */

#define DEBUG_MAILBOX_ID_ID_MASK                 (0xFFFFFFFFU)
#define DEBUG_MAILBOX_ID_ID_SHIFT                (0U)
/*! ID - Identification Value */
#define DEBUG_MAILBOX_ID_ID(x)                   (((uint32_t)(((uint32_t)(x)) << DEBUG_MAILBOX_ID_ID_SHIFT)) & DEBUG_MAILBOX_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DEBUG_MAILBOX_Register_Masks */


/* DEBUG_MAILBOX - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral DEBUG_MAILBOX base address */
  #define DEBUG_MAILBOX_BASE                       (0x50198000u)
  /** Peripheral DEBUG_MAILBOX base address */
  #define DEBUG_MAILBOX_BASE_NS                    (0x40198000u)
  /** Peripheral DEBUG_MAILBOX base pointer */
  #define DEBUG_MAILBOX                            ((DEBUG_MAILBOX_Type *)DEBUG_MAILBOX_BASE)
  /** Peripheral DEBUG_MAILBOX base pointer */
  #define DEBUG_MAILBOX_NS                         ((DEBUG_MAILBOX_Type *)DEBUG_MAILBOX_BASE_NS)
  /** Array initializer of DEBUG_MAILBOX peripheral base addresses */
  #define DEBUG_MAILBOX_BASE_ADDRS                 { DEBUG_MAILBOX_BASE }
  /** Array initializer of DEBUG_MAILBOX peripheral base pointers */
  #define DEBUG_MAILBOX_BASE_PTRS                  { DEBUG_MAILBOX }
  /** Array initializer of DEBUG_MAILBOX peripheral base addresses */
  #define DEBUG_MAILBOX_BASE_ADDRS_NS              { DEBUG_MAILBOX_BASE_NS }
  /** Array initializer of DEBUG_MAILBOX peripheral base pointers */
  #define DEBUG_MAILBOX_BASE_PTRS_NS               { DEBUG_MAILBOX_NS }
#else
  /** Peripheral DEBUG_MAILBOX base address */
  #define DEBUG_MAILBOX_BASE                       (0x40198000u)
  /** Peripheral DEBUG_MAILBOX base pointer */
  #define DEBUG_MAILBOX                            ((DEBUG_MAILBOX_Type *)DEBUG_MAILBOX_BASE)
  /** Array initializer of DEBUG_MAILBOX peripheral base addresses */
  #define DEBUG_MAILBOX_BASE_ADDRS                 { DEBUG_MAILBOX_BASE }
  /** Array initializer of DEBUG_MAILBOX peripheral base pointers */
  #define DEBUG_MAILBOX_BASE_PTRS                  { DEBUG_MAILBOX }
#endif

/*!
 * @}
 */ /* end of group DEBUG_MAILBOX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
 * @{
 */

/** DMA - Register Layout Typedef */
typedef struct {
  __IO uint32_t MP_CSR;                            /**< Management Page Control, offset: 0x0 */
  __I  uint32_t MP_ES;                             /**< Management Page Error Status, offset: 0x4 */
  __I  uint32_t MP_INT;                            /**< Management Page Interrupt Request Status, offset: 0x8 */
  __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status, offset: 0xC */
       uint8_t RESERVED_0[240];
  __IO uint32_t CH_GRPRI[16];                      /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[3776];
  struct {                                         /* offset: 0x1000, array step: 0x1000 */
    __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */
    __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */
    __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */
    __IO uint32_t CH_SBR;                            /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */
    __IO uint32_t CH_PRI;                            /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */
    __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */
         uint8_t RESERVED_0[8];
    __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */
    __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */
    __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */
    union {                                          /* offset: 0x1028, array step: 0x1000 */
      __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
      __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
    };
    __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */
    __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */
    __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */
    union {                                          /* offset: 0x1036, array step: 0x1000 */
      __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */
      __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */
    };
    __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */
    __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */
    union {                                          /* offset: 0x103E, array step: 0x1000 */
      __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */
      __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */
    };
         uint8_t RESERVED_1[4032];
  } CH[16];
} DMA_Type;

/* ----------------------------------------------------------------------------
   -- DMA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Register_Masks DMA Register Masks
 * @{
 */

/*! @name MP_CSR - Management Page Control */
/*! @{ */

#define DMA_MP_CSR_EDBG_MASK                     (0x2U)
#define DMA_MP_CSR_EDBG_SHIFT                    (1U)
/*! EDBG - Enable Debug
 *  0b0..Debug mode disabled
 *  0b1..Debug mode is enabled.
 */
#define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)

#define DMA_MP_CSR_ERCA_MASK                     (0x4U)
#define DMA_MP_CSR_ERCA_SHIFT                    (2U)
/*! ERCA - Enable Round Robin Channel Arbitration
 *  0b0..Round-robin channel arbitration disabled
 *  0b1..Round-robin channel arbitration enabled
 */
#define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)

#define DMA_MP_CSR_HAE_MASK                      (0x10U)
#define DMA_MP_CSR_HAE_SHIFT                     (4U)
/*! HAE - Halt After Error
 *  0b0..Normal operation
 *  0b1..Any error causes the HALT field to be set to 1
 */
#define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)

#define DMA_MP_CSR_HALT_MASK                     (0x20U)
#define DMA_MP_CSR_HALT_SHIFT                    (5U)
/*! HALT - Halt DMA Operations
 *  0b0..Normal operation
 *  0b1..Stall the start of any new channels
 */
#define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)

#define DMA_MP_CSR_GCLC_MASK                     (0x40U)
#define DMA_MP_CSR_GCLC_SHIFT                    (6U)
/*! GCLC - Global Channel Linking Control
 *  0b0..Channel linking disabled for all channels
 *  0b1..Channel linking available and controlled by each channel's link settings
 */
#define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)

#define DMA_MP_CSR_GMRC_MASK                     (0x80U)
#define DMA_MP_CSR_GMRC_SHIFT                    (7U)
/*! GMRC - Global Master ID Replication Control
 *  0b0..Master ID replication disabled for all channels
 *  0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
 */
#define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)

#define DMA_MP_CSR_ECX_MASK                      (0x100U)
#define DMA_MP_CSR_ECX_SHIFT                     (8U)
/*! ECX - Cancel Transfer With Error
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer
 */
#define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)

#define DMA_MP_CSR_CX_MASK                       (0x200U)
#define DMA_MP_CSR_CX_SHIFT                      (9U)
/*! CX - Cancel Transfer
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer
 */
#define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)

#define DMA_MP_CSR_ACTIVE_ID_MASK                (0xF000000U)
#define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
/*! ACTIVE_ID - Active Channel ID */
#define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)

#define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
#define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
/*! ACTIVE - DMA Active Status
 *  0b0..eDMA is idle
 *  0b1..eDMA is executing a channel
 */
#define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
/*! @} */

/*! @name MP_ES - Management Page Error Status */
/*! @{ */

#define DMA_MP_ES_DBE_MASK                       (0x1U)
#define DMA_MP_ES_DBE_SHIFT                      (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..Last recorded error was a bus error on a destination write
 */
#define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)

#define DMA_MP_ES_SBE_MASK                       (0x2U)
#define DMA_MP_ES_SBE_SHIFT                      (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..Last recorded error was a bus error on a source read
 */
#define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)

#define DMA_MP_ES_SGE_MASK                       (0x4U)
#define DMA_MP_ES_SGE_SHIFT                      (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
 */
#define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)

#define DMA_MP_ES_NCE_MASK                       (0x8U)
#define DMA_MP_ES_NCE_SHIFT                      (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
 */
#define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)

#define DMA_MP_ES_DOE_MASK                       (0x10U)
#define DMA_MP_ES_DOE_SHIFT                      (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
 */
#define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)

#define DMA_MP_ES_DAE_MASK                       (0x20U)
#define DMA_MP_ES_DAE_SHIFT                      (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
 */
#define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)

#define DMA_MP_ES_SOE_MASK                       (0x40U)
#define DMA_MP_ES_SOE_SHIFT                      (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
 */
#define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)

#define DMA_MP_ES_SAE_MASK                       (0x80U)
#define DMA_MP_ES_SAE_SHIFT                      (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
 */
#define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)

#define DMA_MP_ES_ECX_MASK                       (0x100U)
#define DMA_MP_ES_ECX_SHIFT                      (8U)
/*! ECX - Transfer Canceled
 *  0b0..No canceled transfers
 *  0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
 */
#define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)

#define DMA_MP_ES_ERRCHN_MASK                    (0xF000000U)
#define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
/*! ERRCHN - Error Channel Number or Canceled Channel Number */
#define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)

#define DMA_MP_ES_VLD_MASK                       (0x80000000U)
#define DMA_MP_ES_VLD_SHIFT                      (31U)
/*! VLD - Valid
 *  0b0..No CHn_ES[ERR] fields are set to 1
 *  0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared
 */
#define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
/*! @} */

/*! @name MP_INT - Management Page Interrupt Request Status */
/*! @{ */

#define DMA_MP_INT_INT_MASK                      (0xFFFFU)
#define DMA_MP_INT_INT_SHIFT                     (0U)
/*! INT - Interrupt Request Status */
#define DMA_MP_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
/*! @} */

/*! @name MP_HRS - Management Page Hardware Request Status */
/*! @{ */

#define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
#define DMA_MP_HRS_HRS_SHIFT                     (0U)
/*! HRS - Hardware Request Status */
#define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
/*! @} */

/*! @name CH_GRPRI - Channel Arbitration Group */
/*! @{ */

#define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
#define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
/*! GRPRI - Arbitration Group For Channel n */
#define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
/*! @} */

/* The count of DMA_CH_GRPRI */
#define DMA_CH_GRPRI_COUNT                       (16U)

/*! @name CH_CSR - Channel Control and Status */
/*! @{ */

#define DMA_CH_CSR_ERQ_MASK                      (0x1U)
#define DMA_CH_CSR_ERQ_SHIFT                     (0U)
/*! ERQ - Enable DMA Request
 *  0b0..DMA hardware request signal for corresponding channel disabled
 *  0b1..DMA hardware request signal for corresponding channel enabled
 */
#define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)

#define DMA_CH_CSR_EARQ_MASK                     (0x2U)
#define DMA_CH_CSR_EARQ_SHIFT                    (1U)
/*! EARQ - Enable Asynchronous DMA Request
 *  0b0..Disable asynchronous DMA request for the channel
 *  0b1..Enable asynchronous DMA request for the channel
 */
#define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)

#define DMA_CH_CSR_EEI_MASK                      (0x4U)
#define DMA_CH_CSR_EEI_SHIFT                     (2U)
/*! EEI - Enable Error Interrupt
 *  0b0..Error signal for corresponding channel does not generate error interrupt
 *  0b1..Assertion of error signal for corresponding channel generates error interrupt request
 */
#define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)

#define DMA_CH_CSR_EBW_MASK                      (0x8U)
#define DMA_CH_CSR_EBW_SHIFT                     (3U)
/*! EBW - Enable Buffered Writes
 *  0b0..Buffered writes on system bus disabled
 *  0b1..Buffered writes on system bus enabled
 */
#define DMA_CH_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)

#define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
#define DMA_CH_CSR_DONE_SHIFT                    (30U)
/*! DONE - Channel Done */
#define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)

#define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
#define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
/*! ACTIVE - Channel Active */
#define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
/*! @} */

/* The count of DMA_CH_CSR */
#define DMA_CH_CSR_COUNT                         (16U)

/*! @name CH_ES - Channel Error Status */
/*! @{ */

#define DMA_CH_ES_DBE_MASK                       (0x1U)
#define DMA_CH_ES_DBE_SHIFT                      (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..Last recorded error was bus error on destination write
 */
#define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)

#define DMA_CH_ES_SBE_MASK                       (0x2U)
#define DMA_CH_ES_SBE_SHIFT                      (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..Last recorded error was bus error on source read
 */
#define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)

#define DMA_CH_ES_SGE_MASK                       (0x4U)
#define DMA_CH_ES_SGE_SHIFT                      (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
 */
#define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)

#define DMA_CH_ES_NCE_MASK                       (0x8U)
#define DMA_CH_ES_NCE_SHIFT                      (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
 */
#define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)

#define DMA_CH_ES_DOE_MASK                       (0x10U)
#define DMA_CH_ES_DOE_SHIFT                      (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
 */
#define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)

#define DMA_CH_ES_DAE_MASK                       (0x20U)
#define DMA_CH_ES_DAE_SHIFT                      (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
 */
#define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)

#define DMA_CH_ES_SOE_MASK                       (0x40U)
#define DMA_CH_ES_SOE_SHIFT                      (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
 */
#define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)

#define DMA_CH_ES_SAE_MASK                       (0x80U)
#define DMA_CH_ES_SAE_SHIFT                      (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
 */
#define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)

#define DMA_CH_ES_ERR_MASK                       (0x80000000U)
#define DMA_CH_ES_ERR_SHIFT                      (31U)
/*! ERR - Error In Channel
 *  0b0..An error in this channel has not occurred
 *  0b1..An error in this channel has occurred
 */
#define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
/*! @} */

/* The count of DMA_CH_ES */
#define DMA_CH_ES_COUNT                          (16U)

/*! @name CH_INT - Channel Interrupt Status */
/*! @{ */

#define DMA_CH_INT_INT_MASK                      (0x1U)
#define DMA_CH_INT_INT_SHIFT                     (0U)
/*! INT - Interrupt Request
 *  0b0..Interrupt request for corresponding channel cleared
 *  0b1..Interrupt request for corresponding channel active
 */
#define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/*! @} */

/* The count of DMA_CH_INT */
#define DMA_CH_INT_COUNT                         (16U)

/*! @name CH_SBR - Channel System Bus */
/*! @{ */

#define DMA_CH_SBR_MID_MASK                      (0x1FU)
#define DMA_CH_SBR_MID_SHIFT                     (0U)
/*! MID - Master ID */
#define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)

#define DMA_CH_SBR_SEC_MASK                      (0x4000U)
#define DMA_CH_SBR_SEC_SHIFT                     (14U)
/*! SEC - Security Level
 *  0b0..Nonsecure protection level for DMA transfers
 *  0b1..Secure protection level for DMA transfers
 */
#define DMA_CH_SBR_SEC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK)

#define DMA_CH_SBR_PAL_MASK                      (0x8000U)
#define DMA_CH_SBR_PAL_SHIFT                     (15U)
/*! PAL - Privileged Access Level
 *  0b0..User protection level for DMA transfers
 *  0b1..Privileged protection level for DMA transfers
 */
#define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)

#define DMA_CH_SBR_EMI_MASK                      (0x10000U)
#define DMA_CH_SBR_EMI_SHIFT                     (16U)
/*! EMI - Enable Master ID Replication
 *  0b0..Master ID replication is disabled
 *  0b1..Master ID replication is enabled
 */
#define DMA_CH_SBR_EMI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)
/*! @} */

/* The count of DMA_CH_SBR */
#define DMA_CH_SBR_COUNT                         (16U)

/*! @name CH_PRI - Channel Priority */
/*! @{ */

#define DMA_CH_PRI_APL_MASK                      (0x7U)
#define DMA_CH_PRI_APL_SHIFT                     (0U)
/*! APL - Arbitration Priority Level */
#define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)

#define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
#define DMA_CH_PRI_DPA_SHIFT                     (30U)
/*! DPA - Disable Preempt Ability
 *  0b0..Channel can suspend a lower-priority channel
 *  0b1..Channel cannot suspend any other channel, regardless of channel priority
 */
#define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)

#define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
#define DMA_CH_PRI_ECP_SHIFT                     (31U)
/*! ECP - Enable Channel Preemption
 *  0b0..Channel cannot be suspended by a higher-priority channel's service request
 *  0b1..Channel can be temporarily suspended by a higher-priority channel's service request
 */
#define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
/*! @} */

/* The count of DMA_CH_PRI */
#define DMA_CH_PRI_COUNT                         (16U)

/*! @name CH_MUX - Channel Multiplexor Configuration */
/*! @{ */

#define DMA_CH_MUX_SRC_MASK                      (0x7FU)
#define DMA_CH_MUX_SRC_SHIFT                     (0U)
/*! SRC - Service Request Source */
#define DMA_CH_MUX_SRC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
/*! @} */

/* The count of DMA_CH_MUX */
#define DMA_CH_MUX_COUNT                         (16U)

/*! @name TCD_SADDR - TCD Source Address */
/*! @{ */

#define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
#define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
/*! SADDR - Source Address */
#define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
/*! @} */

/* The count of DMA_TCD_SADDR */
#define DMA_TCD_SADDR_COUNT                      (16U)

/*! @name TCD_SOFF - TCD Signed Source Address Offset */
/*! @{ */

#define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
#define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
/*! SOFF - Source Address Signed Offset */
#define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
/*! @} */

/* The count of DMA_TCD_SOFF */
#define DMA_TCD_SOFF_COUNT                       (16U)

/*! @name TCD_ATTR - TCD Transfer Attributes */
/*! @{ */

#define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
#define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
/*! DSIZE - Destination Data Transfer Size */
#define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)

#define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
#define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
/*! DMOD - Destination Address Modulo */
#define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)

#define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
#define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
/*! SSIZE - Source Data Transfer Size
 *  0b000..8-bit
 *  0b001..16-bit
 *  0b010..32-bit
 *  0b011..64-bit
 *  0b100..16-byte
 *  0b101..32-byte
 *  0b110..64-byte
 *  0b111..
 */
#define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)

#define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
#define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
/*! SMOD - Source Address Modulo
 *  0b00000..Source address modulo feature disabled
 *  0b00001..Source address modulo feature enabled for any non-zero value [1-31]
 */
#define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
/*! @} */

/* The count of DMA_TCD_ATTR */
#define DMA_TCD_ATTR_COUNT                       (16U)

/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
/*! @{ */

#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request */
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)

#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to DADDR
 *  0b1..Minor loop offset applied to DADDR
 */
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)

#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to SADDR
 *  0b1..Minor loop offset applied to SADDR
 */
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
/*! @} */

/* The count of DMA_TCD_NBYTES_MLOFFNO */
#define DMA_TCD_NBYTES_MLOFFNO_COUNT             (16U)

/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
/*! @{ */

#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request */
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
/*! MLOFF - Minor Loop Offset */
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to DADDR
 *  0b1..Minor loop offset applied to DADDR
 */
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to SADDR
 *  0b1..Minor loop offset applied to SADDR
 */
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
/*! @} */

/* The count of DMA_TCD_NBYTES_MLOFFYES */
#define DMA_TCD_NBYTES_MLOFFYES_COUNT            (16U)

/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
/*! @{ */

#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
#define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
/*! @} */

/* The count of DMA_TCD_SLAST_SDA */
#define DMA_TCD_SLAST_SDA_COUNT                  (16U)

/*! @name TCD_DADDR - TCD Destination Address */
/*! @{ */

#define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
#define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
/*! DADDR - Destination Address */
#define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
/*! @} */

/* The count of DMA_TCD_DADDR */
#define DMA_TCD_DADDR_COUNT                      (16U)

/*! @name TCD_DOFF - TCD Signed Destination Address Offset */
/*! @{ */

#define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
#define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
/*! DOFF - Destination Address Signed Offset */
#define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
/*! @} */

/* The count of DMA_TCD_DOFF */
#define DMA_TCD_DOFF_COUNT                       (16U)

/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */

#define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
/*! CITER - Current Major Iteration Count */
#define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)

#define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_CITER_ELINKNO */
#define DMA_TCD_CITER_ELINKNO_COUNT              (16U)

/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */

#define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
/*! CITER - Current Major Iteration Count */
#define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)

#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0x1E00U)
#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
/*! LINKCH - Minor Loop Link Channel Number */
#define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)

#define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_CITER_ELINKYES */
#define DMA_TCD_CITER_ELINKYES_COUNT             (16U)

/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
/*! @{ */

#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
#define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
/*! @} */

/* The count of DMA_TCD_DLAST_SGA */
#define DMA_TCD_DLAST_SGA_COUNT                  (16U)

/*! @name TCD_CSR - TCD Control and Status */
/*! @{ */

#define DMA_TCD_CSR_START_MASK                   (0x1U)
#define DMA_TCD_CSR_START_SHIFT                  (0U)
/*! START - Channel Start
 *  0b0..Channel not explicitly started
 *  0b1..Channel explicitly started via a software-initiated service request
 */
#define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)

#define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
#define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
/*! INTMAJOR - Enable Interrupt If Major count complete
 *  0b0..End-of-major loop interrupt disabled
 *  0b1..End-of-major loop interrupt enabled
 */
#define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)

#define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
#define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
/*! INTHALF - Enable Interrupt If Major Counter Half-complete
 *  0b0..Halfway point interrupt disabled
 *  0b1..Halfway point interrupt enabled
 */
#define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)

#define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
#define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
/*! DREQ - Disable Request
 *  0b0..No operation
 *  0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
 */
#define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)

#define DMA_TCD_CSR_ESG_MASK                     (0x10U)
#define DMA_TCD_CSR_ESG_SHIFT                    (4U)
/*! ESG - Enable Scatter/Gather Processing
 *  0b0..Current channel's TCD is normal format
 *  0b1..Current channel's TCD specifies scatter/gather format.
 */
#define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)

#define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
#define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
/*! MAJORELINK - Enable Link When Major Loop Complete
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)

#define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
#define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
/*! EEOP - Enable End-Of-Packet Processing
 *  0b0..End-of-packet operation disabled
 *  0b1..End-of-packet hardware input signal enabled
 */
#define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)

#define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
#define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
/*! ESDA - Enable Store Destination Address
 *  0b0..Ability to store destination address to system memory disabled
 *  0b1..Ability to store destination address to system memory enabled
 */
#define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)

#define DMA_TCD_CSR_MAJORLINKCH_MASK             (0xF00U)
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
/*! MAJORLINKCH - Major Loop Link Channel Number */
#define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)

#define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
#define DMA_TCD_CSR_BWC_SHIFT                    (14U)
/*! BWC - Bandwidth Control
 *  0b00..No eDMA engine stalls
 *  0b01..
 *  0b10..eDMA engine stalls for 4 cycles after each R/W
 *  0b11..eDMA engine stalls for 8 cycles after each R/W
 */
#define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
/*! @} */

/* The count of DMA_TCD_CSR */
#define DMA_TCD_CSR_COUNT                        (16U)

/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */

#define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
/*! BITER - Starting Major Iteration Count */
#define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)

#define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
/*! ELINK - Enables Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_BITER_ELINKNO */
#define DMA_TCD_BITER_ELINKNO_COUNT              (16U)

/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */

#define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
/*! BITER - Starting Major Iteration Count */
#define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)

#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0x1E00U)
#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
/*! LINKCH - Link Channel Number */
#define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)

#define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_BITER_ELINKYES */
#define DMA_TCD_BITER_ELINKYES_COUNT             (16U)


/*!
 * @}
 */ /* end of group DMA_Register_Masks */


/* DMA - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral DMA0 base address */
  #define DMA0_BASE                                (0x50140000u)
  /** Peripheral DMA0 base address */
  #define DMA0_BASE_NS                             (0x40140000u)
  /** Peripheral DMA0 base pointer */
  #define DMA0                                     ((DMA_Type *)DMA0_BASE)
  /** Peripheral DMA0 base pointer */
  #define DMA0_NS                                  ((DMA_Type *)DMA0_BASE_NS)
  /** Peripheral DMA1 base address */
  #define DMA1_BASE                                (0x50160000u)
  /** Peripheral DMA1 base address */
  #define DMA1_BASE_NS                             (0x40160000u)
  /** Peripheral DMA1 base pointer */
  #define DMA1                                     ((DMA_Type *)DMA1_BASE)
  /** Peripheral DMA1 base pointer */
  #define DMA1_NS                                  ((DMA_Type *)DMA1_BASE_NS)
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS                            { DMA0, DMA1 }
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS_NS                        { DMA0_BASE_NS, DMA1_BASE_NS }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS_NS                         { DMA0_NS, DMA1_NS }
#else
  /** Peripheral DMA0 base address */
  #define DMA0_BASE                                (0x40140000u)
  /** Peripheral DMA0 base pointer */
  #define DMA0                                     ((DMA_Type *)DMA0_BASE)
  /** Peripheral DMA1 base address */
  #define DMA1_BASE                                (0x40160000u)
  /** Peripheral DMA1 base pointer */
  #define DMA1                                     ((DMA_Type *)DMA1_BASE)
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS                            { DMA0, DMA1 }
#endif

/*!
 * @}
 */ /* end of group DMA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ELS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ELS_Peripheral_Access_Layer ELS Peripheral Access Layer
 * @{
 */

/** ELS - Register Layout Typedef */
typedef struct {
  __I  uint32_t ELS_STATUS;                        /**< Status Register, offset: 0x0 */
  __IO uint32_t ELS_CTRL;                          /**< Control Register, offset: 0x4 */
  __IO uint32_t ELS_CMDCFG0;                       /**< Command Configuration, offset: 0x8 */
  __IO uint32_t ELS_CFG;                           /**< Configuration Register, offset: 0xC */
  __IO uint32_t ELS_KIDX0;                         /**< Keystore Index 0 Register, offset: 0x10 */
  __IO uint32_t ELS_KIDX1;                         /**< Keystore Index 1 Register, offset: 0x14 */
  __IO uint32_t ELS_KPROPIN;                       /**< Key Properties Request Register, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t ELS_DMA_SRC0;                      /**< DMA Source 0 Register, offset: 0x20 */
  __IO uint32_t ELS_DMA_SRC0_LEN;                  /**< DMA Source 0 Length Register, offset: 0x24 */
  __IO uint32_t ELS_DMA_SRC1;                      /**< DMA Source 1 Register, offset: 0x28 */
       uint8_t RESERVED_1[4];
  __IO uint32_t ELS_DMA_SRC2;                      /**< DMA Source 2 Register, offset: 0x30 */
  __IO uint32_t ELS_DMA_SRC2_LEN;                  /**< DMA Source 2 Length Register, offset: 0x34 */
  __IO uint32_t ELS_DMA_RES0;                      /**< DMA Result 0 Register, offset: 0x38 */
  __IO uint32_t ELS_DMA_RES0_LEN;                  /**< DMA Result 0 Size Register, offset: 0x3C */
  __IO uint32_t ELS_INT_ENABLE;                    /**< Interrupt Enable Register, offset: 0x40 */
  __O  uint32_t ELS_INT_STATUS_CLR;                /**< Interrupt Status Clear Register, offset: 0x44 */
  __O  uint32_t ELS_INT_STATUS_SET;                /**< Interrupt Status Set Register, offset: 0x48 */
  __I  uint32_t ELS_ERR_STATUS;                    /**< Error Status Register, offset: 0x4C */
  __O  uint32_t ELS_ERR_STATUS_CLR;                /**< Error Status Clear Register, offset: 0x50 */
  __I  uint32_t ELS_VERSION;                       /**< Version Register, offset: 0x54 */
  __I  uint32_t ELS_CONFIG;                        /**< ELS CONFIG, offset: 0x58 */
  __I  uint32_t ELS_PRNG_DATOUT;                   /**< PRNG SW Read Out Register, offset: 0x5C */
  __IO uint32_t ELS_CMDCRC_CTRL;                   /**< CRC Configuration Register, offset: 0x60 */
  __I  uint32_t ELS_CMDCRC;                        /**< Command CRC Value Register, offset: 0x64 */
  __IO uint32_t ELS_SESSION_ID;                    /**< Session ID Register, offset: 0x68 */
       uint8_t RESERVED_2[4];
  __I  uint32_t ELS_DMA_FIN_ADDR;                  /**< Final DMA Address Register, offset: 0x70 */
  __IO uint32_t ELS_MASTER_ID;                     /**< Master ID Register, offset: 0x74 */
  __IO uint32_t ELS_KIDX2;                         /**< Keystore Index 2 Register, offset: 0x78 */
       uint8_t RESERVED_3[132];
  __I  uint32_t ELS_SHA2_STATUS;                   /**< SHA2 Status Register, offset: 0x100 */
  __IO uint32_t ELS_SHA2_CTRL;                     /**< SHA2 Control Register, offset: 0x104 */
  __IO uint32_t ELS_SHA2_DIN;                      /**< SHA_DATA IN 0 Register, offset: 0x108 */
  __I  uint32_t ELS_SHA2_DOUT0;                    /**< SHA_DATA Out 0 Register, offset: 0x10C */
  __I  uint32_t ELS_SHA2_DOUT1;                    /**< SHA_DATA Out 1 Register, offset: 0x110 */
  __I  uint32_t ELS_SHA2_DOUT2;                    /**< SHA_DATA Out 2 Register, offset: 0x114 */
  __I  uint32_t ELS_SHA2_DOUT3;                    /**< SHA_DATA Out 3 Register, offset: 0x118 */
  __I  uint32_t ELS_SHA2_DOUT4;                    /**< SHA_DATA Out 4 Register, offset: 0x11C */
  __I  uint32_t ELS_SHA2_DOUT5;                    /**< SHA_DATA Out 5 Register, offset: 0x120 */
  __I  uint32_t ELS_SHA2_DOUT6;                    /**< SHA_DATA Out 6 Register, offset: 0x124 */
  __I  uint32_t ELS_SHA2_DOUT7;                    /**< SHA_DATA Out 7 Register, offset: 0x128 */
  __I  uint32_t ELS_SHA2_DOUT8;                    /**< SHA_DATA Out 8 Register, offset: 0x12C */
  __I  uint32_t ELS_SHA2_DOUT9;                    /**< SHA_DATA Out 9 Register, offset: 0x130 */
  __I  uint32_t ELS_SHA2_DOUT10;                   /**< SHA_DATA Out 10 Register, offset: 0x134 */
  __I  uint32_t ELS_SHA2_DOUT11;                   /**< SHA_DATA Out 11 Register, offset: 0x138 */
  __I  uint32_t ELS_SHA2_DOUT12;                   /**< SHA_DATA Out 12 Register, offset: 0x13C */
  __I  uint32_t ELS_SHA2_DOUT13;                   /**< SHA_DATA Out 13 Register, offset: 0x140 */
  __I  uint32_t ELS_SHA2_DOUT14;                   /**< SHA_DATA Out 14 Register, offset: 0x144 */
  __I  uint32_t ELS_SHA2_DOUT15;                   /**< SHA_DATA Out 15 Register, offset: 0x148 */
       uint8_t RESERVED_4[4];
  __I  uint32_t ELS_KS0;                           /**< Status Register, offset: 0x150 */
  __I  uint32_t ELS_KS1;                           /**< Status Register, offset: 0x154 */
  __I  uint32_t ELS_KS2;                           /**< Status Register, offset: 0x158 */
  __I  uint32_t ELS_KS3;                           /**< Status Register, offset: 0x15C */
  __I  uint32_t ELS_KS4;                           /**< Status Register, offset: 0x160 */
  __I  uint32_t ELS_KS5;                           /**< Status Register, offset: 0x164 */
  __I  uint32_t ELS_KS6;                           /**< Status Register, offset: 0x168 */
  __I  uint32_t ELS_KS7;                           /**< Status Register, offset: 0x16C */
  __I  uint32_t ELS_KS8;                           /**< Status Register, offset: 0x170 */
  __I  uint32_t ELS_KS9;                           /**< Status Register, offset: 0x174 */
  __I  uint32_t ELS_KS10;                          /**< Status Register, offset: 0x178 */
  __I  uint32_t ELS_KS11;                          /**< Status Register, offset: 0x17C */
  __I  uint32_t ELS_KS12;                          /**< Status Register, offset: 0x180 */
  __I  uint32_t ELS_KS13;                          /**< Status Register, offset: 0x184 */
  __I  uint32_t ELS_KS14;                          /**< Status Register, offset: 0x188 */
  __I  uint32_t ELS_KS15;                          /**< Status Register, offset: 0x18C */
  __I  uint32_t ELS_KS16;                          /**< Status Register, offset: 0x190 */
  __I  uint32_t ELS_KS17;                          /**< Status Register, offset: 0x194 */
  __I  uint32_t ELS_KS18;                          /**< Status Register, offset: 0x198 */
  __I  uint32_t ELS_KS19;                          /**< Status Register, offset: 0x19C */
       uint8_t RESERVED_5[4];
  __IO uint32_t RESERVED_LA4;                      /**< Reserved LA4, offset: 0x1A4 */
  __IO uint32_t RESERVED_LA8;                      /**< Reserved LA8, offset: 0x1A8 */
} ELS_Type;

/* ----------------------------------------------------------------------------
   -- ELS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ELS_Register_Masks ELS Register Masks
 * @{
 */

/*! @name ELS_STATUS - Status Register */
/*! @{ */

#define ELS_ELS_STATUS_ELS_BUSY_MASK             (0x1U)
#define ELS_ELS_STATUS_ELS_BUSY_SHIFT            (0U)
/*! ELS_BUSY
 *  0b0..Crypto sequence not executing
 *  0b1..Crypto sequence executing
 */
#define ELS_ELS_STATUS_ELS_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ELS_BUSY_SHIFT)) & ELS_ELS_STATUS_ELS_BUSY_MASK)

#define ELS_ELS_STATUS_ELS_IRQ_MASK              (0x2U)
#define ELS_ELS_STATUS_ELS_IRQ_SHIFT             (1U)
/*! ELS_IRQ
 *  0b0..No active interrupt
 *  0b1..Active interrupt
 */
#define ELS_ELS_STATUS_ELS_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ELS_IRQ_SHIFT)) & ELS_ELS_STATUS_ELS_IRQ_MASK)

#define ELS_ELS_STATUS_ELS_ERR_MASK              (0x4U)
#define ELS_ELS_STATUS_ELS_ERR_SHIFT             (2U)
/*! ELS_ERR
 *  0b0..Internal error not detected
 *  0b1..Internal error detected
 */
#define ELS_ELS_STATUS_ELS_ERR(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ELS_ERR_SHIFT)) & ELS_ELS_STATUS_ELS_ERR_MASK)

#define ELS_ELS_STATUS_PRNG_RDY_MASK             (0x8U)
#define ELS_ELS_STATUS_PRNG_RDY_SHIFT            (3U)
/*! PRNG_RDY
 *  0b0..Internal PRNG not ready
 *  0b1..Internal PRNG ready
 */
#define ELS_ELS_STATUS_PRNG_RDY(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_PRNG_RDY_SHIFT)) & ELS_ELS_STATUS_PRNG_RDY_MASK)

#define ELS_ELS_STATUS_ECDSA_VFY_STATUS_MASK     (0x30U)
#define ELS_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT    (4U)
/*! ECDSA_VFY_STATUS
 *  0b00..No verify run
 *  0b01..Signature verify failed
 *  0b10..Signature verify passed
 *  0b11..Invalid, Error
 */
#define ELS_ELS_STATUS_ECDSA_VFY_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & ELS_ELS_STATUS_ECDSA_VFY_STATUS_MASK)

#define ELS_ELS_STATUS_PPROT_MASK                (0xC0U)
#define ELS_ELS_STATUS_PPROT_SHIFT               (6U)
/*! PPROT
 *  0b00..Secure, non-privileged
 *  0b01..Secure, privileged
 *  0b10..Non-secure, non-privileged
 *  0b11..Non-secure, privileged
 */
#define ELS_ELS_STATUS_PPROT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_PPROT_SHIFT)) & ELS_ELS_STATUS_PPROT_MASK)

#define ELS_ELS_STATUS_DRBG_ENT_LVL_MASK         (0x300U)
#define ELS_ELS_STATUS_DRBG_ENT_LVL_SHIFT        (8U)
/*! DRBG_ENT_LVL
 *  0b00..NONE
 *  0b01..LOW, DRBG generates random numbers of low quality entropy
 *  0b10..HIGH, DRBG generates random numbers of high quality entropy
 *  0b11..RFU, Reserved for Future Use
 */
#define ELS_ELS_STATUS_DRBG_ENT_LVL(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & ELS_ELS_STATUS_DRBG_ENT_LVL_MASK)

#define ELS_ELS_STATUS_DTRNG_BUSY_MASK           (0x400U)
#define ELS_ELS_STATUS_DTRNG_BUSY_SHIFT          (10U)
/*! DTRNG_BUSY
 *  0b0..Not gathering entropy
 *  0b1..Gathering entropy
 */
#define ELS_ELS_STATUS_DTRNG_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_DTRNG_BUSY_SHIFT)) & ELS_ELS_STATUS_DTRNG_BUSY_MASK)

#define ELS_ELS_STATUS_ELS_LOCKED_MASK           (0x10000U)
#define ELS_ELS_STATUS_ELS_LOCKED_SHIFT          (16U)
/*! ELS_LOCKED
 *  0b0..Not locked by master
 *  0b1..Locked by master
 */
#define ELS_ELS_STATUS_ELS_LOCKED(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ELS_LOCKED_SHIFT)) & ELS_ELS_STATUS_ELS_LOCKED_MASK)

#define ELS_ELS_STATUS_RESERVED17_MASK           (0x20000U)
#define ELS_ELS_STATUS_RESERVED17_SHIFT          (17U)
/*! reserved17 - reserved */
#define ELS_ELS_STATUS_RESERVED17(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_RESERVED17_SHIFT)) & ELS_ELS_STATUS_RESERVED17_MASK)

#define ELS_ELS_STATUS_RESERVED31_MASK           (0xFFFC0000U)
#define ELS_ELS_STATUS_RESERVED31_SHIFT          (18U)
/*! reserved31 - reserved */
#define ELS_ELS_STATUS_RESERVED31(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_RESERVED31_SHIFT)) & ELS_ELS_STATUS_RESERVED31_MASK)
/*! @} */

/*! @name ELS_CTRL - Control Register */
/*! @{ */

#define ELS_ELS_CTRL_ELS_EN_MASK                 (0x1U)
#define ELS_ELS_CTRL_ELS_EN_SHIFT                (0U)
/*! ELS_EN
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ELS_ELS_CTRL_ELS_EN(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_ELS_EN_SHIFT)) & ELS_ELS_CTRL_ELS_EN_MASK)

#define ELS_ELS_CTRL_ELS_START_MASK              (0x2U)
#define ELS_ELS_CTRL_ELS_START_SHIFT             (1U)
#define ELS_ELS_CTRL_ELS_START(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_ELS_START_SHIFT)) & ELS_ELS_CTRL_ELS_START_MASK)

#define ELS_ELS_CTRL_ELS_RESET_MASK              (0x4U)
#define ELS_ELS_CTRL_ELS_RESET_SHIFT             (2U)
#define ELS_ELS_CTRL_ELS_RESET(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_ELS_RESET_SHIFT)) & ELS_ELS_CTRL_ELS_RESET_MASK)

#define ELS_ELS_CTRL_ELS_CMD_MASK                (0xF8U)
#define ELS_ELS_CTRL_ELS_CMD_SHIFT               (3U)
/*! ELS_CMD - ELS Command ID */
#define ELS_ELS_CTRL_ELS_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_ELS_CMD_SHIFT)) & ELS_ELS_CTRL_ELS_CMD_MASK)

#define ELS_ELS_CTRL_BYTE_ORDER_MASK             (0x100U)
#define ELS_ELS_CTRL_BYTE_ORDER_SHIFT            (8U)
/*! BYTE_ORDER
 *  0b1..Big endian
 *  0b0..Little endian
 */
#define ELS_ELS_CTRL_BYTE_ORDER(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_BYTE_ORDER_SHIFT)) & ELS_ELS_CTRL_BYTE_ORDER_MASK)
/*! @} */

/*! @name ELS_CMDCFG0 - Command Configuration */
/*! @{ */

#define ELS_ELS_CMDCFG0_CMDCFG0_MASK             (0xFFFFFFFFU)
#define ELS_ELS_CMDCFG0_CMDCFG0_SHIFT            (0U)
#define ELS_ELS_CMDCFG0_CMDCFG0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CMDCFG0_CMDCFG0_SHIFT)) & ELS_ELS_CMDCFG0_CMDCFG0_MASK)
/*! @} */

/*! @name ELS_CFG - Configuration Register */
/*! @{ */

#define ELS_ELS_CFG_ADCTRL_MASK                  (0x3FF0000U)
#define ELS_ELS_CFG_ADCTRL_SHIFT                 (16U)
#define ELS_ELS_CFG_ADCTRL(x)                    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CFG_ADCTRL_SHIFT)) & ELS_ELS_CFG_ADCTRL_MASK)

#define ELS_ELS_CFG_SHA2_DIRECT_MASK             (0x80000000U)
#define ELS_ELS_CFG_SHA2_DIRECT_SHIFT            (31U)
/*! SHA2_DIRECT
 *  0b1..Enabled: direct access from external
 *  0b0..Disabled
 */
#define ELS_ELS_CFG_SHA2_DIRECT(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CFG_SHA2_DIRECT_SHIFT)) & ELS_ELS_CFG_SHA2_DIRECT_MASK)
/*! @} */

/*! @name ELS_KIDX0 - Keystore Index 0 Register */
/*! @{ */

#define ELS_ELS_KIDX0_KIDX0_MASK                 (0x1FU)
#define ELS_ELS_KIDX0_KIDX0_SHIFT                (0U)
#define ELS_ELS_KIDX0_KIDX0(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KIDX0_KIDX0_SHIFT)) & ELS_ELS_KIDX0_KIDX0_MASK)
/*! @} */

/*! @name ELS_KIDX1 - Keystore Index 1 Register */
/*! @{ */

#define ELS_ELS_KIDX1_KIDX1_MASK                 (0x1FU)
#define ELS_ELS_KIDX1_KIDX1_SHIFT                (0U)
#define ELS_ELS_KIDX1_KIDX1(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KIDX1_KIDX1_SHIFT)) & ELS_ELS_KIDX1_KIDX1_MASK)
/*! @} */

/*! @name ELS_KPROPIN - Key Properties Request Register */
/*! @{ */

#define ELS_ELS_KPROPIN_KPROPIN_MASK             (0xFFFFFFFFU)
#define ELS_ELS_KPROPIN_KPROPIN_SHIFT            (0U)
#define ELS_ELS_KPROPIN_KPROPIN(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KPROPIN_KPROPIN_SHIFT)) & ELS_ELS_KPROPIN_KPROPIN_MASK)
/*! @} */

/*! @name ELS_DMA_SRC0 - DMA Source 0 Register */
/*! @{ */

#define ELS_ELS_DMA_SRC0_ADDR_SRC0_MASK          (0xFFFFFFFFU)
#define ELS_ELS_DMA_SRC0_ADDR_SRC0_SHIFT         (0U)
#define ELS_ELS_DMA_SRC0_ADDR_SRC0(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & ELS_ELS_DMA_SRC0_ADDR_SRC0_MASK)
/*! @} */

/*! @name ELS_DMA_SRC0_LEN - DMA Source 0 Length Register */
/*! @{ */

#define ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK  (0xFFFFFFFFU)
#define ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U)
#define ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x)    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK)
/*! @} */

/*! @name ELS_DMA_SRC1 - DMA Source 1 Register */
/*! @{ */

#define ELS_ELS_DMA_SRC1_ADDR_SRC1_MASK          (0xFFFFFFFFU)
#define ELS_ELS_DMA_SRC1_ADDR_SRC1_SHIFT         (0U)
#define ELS_ELS_DMA_SRC1_ADDR_SRC1(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & ELS_ELS_DMA_SRC1_ADDR_SRC1_MASK)
/*! @} */

/*! @name ELS_DMA_SRC2 - DMA Source 2 Register */
/*! @{ */

#define ELS_ELS_DMA_SRC2_ADDR_SRC2_MASK          (0xFFFFFFFFU)
#define ELS_ELS_DMA_SRC2_ADDR_SRC2_SHIFT         (0U)
#define ELS_ELS_DMA_SRC2_ADDR_SRC2(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & ELS_ELS_DMA_SRC2_ADDR_SRC2_MASK)
/*! @} */

/*! @name ELS_DMA_SRC2_LEN - DMA Source 2 Length Register */
/*! @{ */

#define ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK  (0xFFFFFFFFU)
#define ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U)
#define ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x)    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK)
/*! @} */

/*! @name ELS_DMA_RES0 - DMA Result 0 Register */
/*! @{ */

#define ELS_ELS_DMA_RES0_ADDR_RES0_MASK          (0xFFFFFFFFU)
#define ELS_ELS_DMA_RES0_ADDR_RES0_SHIFT         (0U)
#define ELS_ELS_DMA_RES0_ADDR_RES0(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & ELS_ELS_DMA_RES0_ADDR_RES0_MASK)
/*! @} */

/*! @name ELS_DMA_RES0_LEN - DMA Result 0 Size Register */
/*! @{ */

#define ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK  (0xFFFFFFFFU)
#define ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U)
#define ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x)    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK)
/*! @} */

/*! @name ELS_INT_ENABLE - Interrupt Enable Register */
/*! @{ */

#define ELS_ELS_INT_ENABLE_INT_EN_MASK           (0x1U)
#define ELS_ELS_INT_ENABLE_INT_EN_SHIFT          (0U)
#define ELS_ELS_INT_ENABLE_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_ENABLE_INT_EN_SHIFT)) & ELS_ELS_INT_ENABLE_INT_EN_MASK)
/*! @} */

/*! @name ELS_INT_STATUS_CLR - Interrupt Status Clear Register */
/*! @{ */

#define ELS_ELS_INT_STATUS_CLR_INT_CLR_MASK      (0x1U)
#define ELS_ELS_INT_STATUS_CLR_INT_CLR_SHIFT     (0U)
#define ELS_ELS_INT_STATUS_CLR_INT_CLR(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & ELS_ELS_INT_STATUS_CLR_INT_CLR_MASK)
/*! @} */

/*! @name ELS_INT_STATUS_SET - Interrupt Status Set Register */
/*! @{ */

#define ELS_ELS_INT_STATUS_SET_INT_SET_MASK      (0x1U)
#define ELS_ELS_INT_STATUS_SET_INT_SET_SHIFT     (0U)
#define ELS_ELS_INT_STATUS_SET_INT_SET(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & ELS_ELS_INT_STATUS_SET_INT_SET_MASK)
/*! @} */

/*! @name ELS_ERR_STATUS - Error Status Register */
/*! @{ */

#define ELS_ELS_ERR_STATUS_BUS_ERR_MASK          (0x1U)
#define ELS_ELS_ERR_STATUS_BUS_ERR_SHIFT         (0U)
#define ELS_ELS_ERR_STATUS_BUS_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_BUS_ERR_MASK)

#define ELS_ELS_ERR_STATUS_OPN_ERR_MASK          (0x2U)
#define ELS_ELS_ERR_STATUS_OPN_ERR_SHIFT         (1U)
#define ELS_ELS_ERR_STATUS_OPN_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_OPN_ERR_MASK)

#define ELS_ELS_ERR_STATUS_ALG_ERR_MASK          (0x4U)
#define ELS_ELS_ERR_STATUS_ALG_ERR_SHIFT         (2U)
#define ELS_ELS_ERR_STATUS_ALG_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_ALG_ERR_MASK)

#define ELS_ELS_ERR_STATUS_ITG_ERR_MASK          (0x8U)
#define ELS_ELS_ERR_STATUS_ITG_ERR_SHIFT         (3U)
#define ELS_ELS_ERR_STATUS_ITG_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_ITG_ERR_MASK)

#define ELS_ELS_ERR_STATUS_FLT_ERR_MASK          (0x10U)
#define ELS_ELS_ERR_STATUS_FLT_ERR_SHIFT         (4U)
#define ELS_ELS_ERR_STATUS_FLT_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_FLT_ERR_MASK)

#define ELS_ELS_ERR_STATUS_PRNG_ERR_MASK         (0x20U)
#define ELS_ELS_ERR_STATUS_PRNG_ERR_SHIFT        (5U)
#define ELS_ELS_ERR_STATUS_PRNG_ERR(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_PRNG_ERR_MASK)

#define ELS_ELS_ERR_STATUS_ERR_LVL_MASK          (0xC0U)
#define ELS_ELS_ERR_STATUS_ERR_LVL_SHIFT         (6U)
#define ELS_ELS_ERR_STATUS_ERR_LVL(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & ELS_ELS_ERR_STATUS_ERR_LVL_MASK)

#define ELS_ELS_ERR_STATUS_DTRNG_ERR_MASK        (0x100U)
#define ELS_ELS_ERR_STATUS_DTRNG_ERR_SHIFT       (8U)
#define ELS_ELS_ERR_STATUS_DTRNG_ERR(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_DTRNG_ERR_MASK)
/*! @} */

/*! @name ELS_ERR_STATUS_CLR - Error Status Clear Register */
/*! @{ */

#define ELS_ELS_ERR_STATUS_CLR_ERR_CLR_MASK      (0x1U)
#define ELS_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT     (0U)
/*! ERR_CLR
 *  0b1..Clears ELS error status bits
 *  0b0..Exits ELS error state
 */
#define ELS_ELS_ERR_STATUS_CLR_ERR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & ELS_ELS_ERR_STATUS_CLR_ERR_CLR_MASK)
/*! @} */

/*! @name ELS_VERSION - Version Register */
/*! @{ */

#define ELS_ELS_VERSION_Z_MASK                   (0xFU)
#define ELS_ELS_VERSION_Z_SHIFT                  (0U)
#define ELS_ELS_VERSION_Z(x)                     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_Z_SHIFT)) & ELS_ELS_VERSION_Z_MASK)

#define ELS_ELS_VERSION_Y2_MASK                  (0xF0U)
#define ELS_ELS_VERSION_Y2_SHIFT                 (4U)
#define ELS_ELS_VERSION_Y2(x)                    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_Y2_SHIFT)) & ELS_ELS_VERSION_Y2_MASK)

#define ELS_ELS_VERSION_Y1_MASK                  (0xF00U)
#define ELS_ELS_VERSION_Y1_SHIFT                 (8U)
#define ELS_ELS_VERSION_Y1(x)                    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_Y1_SHIFT)) & ELS_ELS_VERSION_Y1_MASK)

#define ELS_ELS_VERSION_X_MASK                   (0xF000U)
#define ELS_ELS_VERSION_X_SHIFT                  (12U)
#define ELS_ELS_VERSION_X(x)                     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_X_SHIFT)) & ELS_ELS_VERSION_X_MASK)

#define ELS_ELS_VERSION_SW_Z_MASK                (0xF0000U)
#define ELS_ELS_VERSION_SW_Z_SHIFT               (16U)
#define ELS_ELS_VERSION_SW_Z(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_SW_Z_SHIFT)) & ELS_ELS_VERSION_SW_Z_MASK)

#define ELS_ELS_VERSION_SW_Y2_MASK               (0xF00000U)
#define ELS_ELS_VERSION_SW_Y2_SHIFT              (20U)
#define ELS_ELS_VERSION_SW_Y2(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_SW_Y2_SHIFT)) & ELS_ELS_VERSION_SW_Y2_MASK)

#define ELS_ELS_VERSION_SW_Y1_MASK               (0xF000000U)
#define ELS_ELS_VERSION_SW_Y1_SHIFT              (24U)
#define ELS_ELS_VERSION_SW_Y1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_SW_Y1_SHIFT)) & ELS_ELS_VERSION_SW_Y1_MASK)

#define ELS_ELS_VERSION_SW_X_MASK                (0xF0000000U)
#define ELS_ELS_VERSION_SW_X_SHIFT               (28U)
#define ELS_ELS_VERSION_SW_X(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_SW_X_SHIFT)) & ELS_ELS_VERSION_SW_X_MASK)
/*! @} */

/*! @name ELS_CONFIG - ELS CONFIG */
/*! @{ */

#define ELS_ELS_CONFIG_CIPHER_SUP_MASK           (0x1U)
#define ELS_ELS_CONFIG_CIPHER_SUP_SHIFT          (0U)
/*! cipher_sup - cipher command is supported */
#define ELS_ELS_CONFIG_CIPHER_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_CIPHER_SUP_SHIFT)) & ELS_ELS_CONFIG_CIPHER_SUP_MASK)

#define ELS_ELS_CONFIG_AUTH_CIPHER_SUP_MASK      (0x2U)
#define ELS_ELS_CONFIG_AUTH_CIPHER_SUP_SHIFT     (1U)
/*! auth_cipher_sup - auth_cipher command is supported */
#define ELS_ELS_CONFIG_AUTH_CIPHER_SUP(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_AUTH_CIPHER_SUP_SHIFT)) & ELS_ELS_CONFIG_AUTH_CIPHER_SUP_MASK)

#define ELS_ELS_CONFIG_RESERVED2_MASK            (0x4U)
#define ELS_ELS_CONFIG_RESERVED2_SHIFT           (2U)
/*! reserved2 - reserved */
#define ELS_ELS_CONFIG_RESERVED2(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED2_SHIFT)) & ELS_ELS_CONFIG_RESERVED2_MASK)

#define ELS_ELS_CONFIG_RESERVED3_MASK            (0x8U)
#define ELS_ELS_CONFIG_RESERVED3_SHIFT           (3U)
/*! reserved3 - reserved */
#define ELS_ELS_CONFIG_RESERVED3(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED3_SHIFT)) & ELS_ELS_CONFIG_RESERVED3_MASK)

#define ELS_ELS_CONFIG_ECSIGN_SUP_MASK           (0x10U)
#define ELS_ELS_CONFIG_ECSIGN_SUP_SHIFT          (4U)
/*! ecsign_sup - ecsign command is supported */
#define ELS_ELS_CONFIG_ECSIGN_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_ECSIGN_SUP_SHIFT)) & ELS_ELS_CONFIG_ECSIGN_SUP_MASK)

#define ELS_ELS_CONFIG_ECVFY_SUP_MASK            (0x20U)
#define ELS_ELS_CONFIG_ECVFY_SUP_SHIFT           (5U)
/*! ecvfy_sup - ecvfy command is supported */
#define ELS_ELS_CONFIG_ECVFY_SUP(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_ECVFY_SUP_SHIFT)) & ELS_ELS_CONFIG_ECVFY_SUP_MASK)

#define ELS_ELS_CONFIG_ECKXCH_SUP_MASK           (0x40U)
#define ELS_ELS_CONFIG_ECKXCH_SUP_SHIFT          (6U)
/*! eckxch_sup - dhkey_xch command is supported */
#define ELS_ELS_CONFIG_ECKXCH_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_ECKXCH_SUP_SHIFT)) & ELS_ELS_CONFIG_ECKXCH_SUP_MASK)

#define ELS_ELS_CONFIG_RESERVED7_MASK            (0x80U)
#define ELS_ELS_CONFIG_RESERVED7_SHIFT           (7U)
/*! reserved7 - reserved */
#define ELS_ELS_CONFIG_RESERVED7(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED7_SHIFT)) & ELS_ELS_CONFIG_RESERVED7_MASK)

#define ELS_ELS_CONFIG_KEYGEN_SUP_MASK           (0x100U)
#define ELS_ELS_CONFIG_KEYGEN_SUP_SHIFT          (8U)
/*! keygen_sup - keygen command is supported */
#define ELS_ELS_CONFIG_KEYGEN_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KEYGEN_SUP_SHIFT)) & ELS_ELS_CONFIG_KEYGEN_SUP_MASK)

#define ELS_ELS_CONFIG_KEYIN_SUP_MASK            (0x200U)
#define ELS_ELS_CONFIG_KEYIN_SUP_SHIFT           (9U)
/*! keyin_sup - keyin command is supported */
#define ELS_ELS_CONFIG_KEYIN_SUP(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KEYIN_SUP_SHIFT)) & ELS_ELS_CONFIG_KEYIN_SUP_MASK)

#define ELS_ELS_CONFIG_KEYOUT_SUP_MASK           (0x400U)
#define ELS_ELS_CONFIG_KEYOUT_SUP_SHIFT          (10U)
/*! keyout_sup - keyout command is supported */
#define ELS_ELS_CONFIG_KEYOUT_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KEYOUT_SUP_SHIFT)) & ELS_ELS_CONFIG_KEYOUT_SUP_MASK)

#define ELS_ELS_CONFIG_KDELETE_SUP_MASK          (0x800U)
#define ELS_ELS_CONFIG_KDELETE_SUP_SHIFT         (11U)
/*! kdelete_sup - kdelete command is supported */
#define ELS_ELS_CONFIG_KDELETE_SUP(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KDELETE_SUP_SHIFT)) & ELS_ELS_CONFIG_KDELETE_SUP_MASK)

#define ELS_ELS_CONFIG_RESERVED13_MASK           (0x2000U)
#define ELS_ELS_CONFIG_RESERVED13_SHIFT          (13U)
/*! reserved13 - reserved */
#define ELS_ELS_CONFIG_RESERVED13(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED13_SHIFT)) & ELS_ELS_CONFIG_RESERVED13_MASK)

#define ELS_ELS_CONFIG_RESERVED14_MASK           (0x4000U)
#define ELS_ELS_CONFIG_RESERVED14_SHIFT          (14U)
/*! reserved14 - reserved */
#define ELS_ELS_CONFIG_RESERVED14(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED14_SHIFT)) & ELS_ELS_CONFIG_RESERVED14_MASK)

#define ELS_ELS_CONFIG_RESERVED15_MASK           (0x8000U)
#define ELS_ELS_CONFIG_RESERVED15_SHIFT          (15U)
/*! reserved15 - reserved */
#define ELS_ELS_CONFIG_RESERVED15(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED15_SHIFT)) & ELS_ELS_CONFIG_RESERVED15_MASK)

#define ELS_ELS_CONFIG_CKDF_SUP_MASK             (0x10000U)
#define ELS_ELS_CONFIG_CKDF_SUP_SHIFT            (16U)
/*! ckdf_sup - ckdf command is supported */
#define ELS_ELS_CONFIG_CKDF_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_CKDF_SUP_SHIFT)) & ELS_ELS_CONFIG_CKDF_SUP_MASK)

#define ELS_ELS_CONFIG_HKDF_SUP_MASK             (0x20000U)
#define ELS_ELS_CONFIG_HKDF_SUP_SHIFT            (17U)
/*! hkdf_sup - hkdf command is supported */
#define ELS_ELS_CONFIG_HKDF_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_HKDF_SUP_SHIFT)) & ELS_ELS_CONFIG_HKDF_SUP_MASK)

#define ELS_ELS_CONFIG_TLS_INIT_SUP_MASK         (0x40000U)
#define ELS_ELS_CONFIG_TLS_INIT_SUP_SHIFT        (18U)
/*! tls_init_sup - tls_init command is supported */
#define ELS_ELS_CONFIG_TLS_INIT_SUP(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_TLS_INIT_SUP_SHIFT)) & ELS_ELS_CONFIG_TLS_INIT_SUP_MASK)

#define ELS_ELS_CONFIG_RESERVED19_MASK           (0x80000U)
#define ELS_ELS_CONFIG_RESERVED19_SHIFT          (19U)
/*! reserved19 - reserved */
#define ELS_ELS_CONFIG_RESERVED19(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED19_SHIFT)) & ELS_ELS_CONFIG_RESERVED19_MASK)

#define ELS_ELS_CONFIG_HASH_SUP_MASK             (0x100000U)
#define ELS_ELS_CONFIG_HASH_SUP_SHIFT            (20U)
/*! hash_sup - hash command is supported */
#define ELS_ELS_CONFIG_HASH_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_HASH_SUP_SHIFT)) & ELS_ELS_CONFIG_HASH_SUP_MASK)

#define ELS_ELS_CONFIG_HMAC_SUP_MASK             (0x200000U)
#define ELS_ELS_CONFIG_HMAC_SUP_SHIFT            (21U)
/*! hmac_sup - hmac command is supported */
#define ELS_ELS_CONFIG_HMAC_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_HMAC_SUP_SHIFT)) & ELS_ELS_CONFIG_HMAC_SUP_MASK)

#define ELS_ELS_CONFIG_CMAC_SUP_MASK             (0x400000U)
#define ELS_ELS_CONFIG_CMAC_SUP_SHIFT            (22U)
/*! cmac_sup - cmac command is supported */
#define ELS_ELS_CONFIG_CMAC_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_CMAC_SUP_SHIFT)) & ELS_ELS_CONFIG_CMAC_SUP_MASK)

#define ELS_ELS_CONFIG_RESERVED23_MASK           (0x800000U)
#define ELS_ELS_CONFIG_RESERVED23_SHIFT          (23U)
/*! reserved23 - reserved */
#define ELS_ELS_CONFIG_RESERVED23(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED23_SHIFT)) & ELS_ELS_CONFIG_RESERVED23_MASK)

#define ELS_ELS_CONFIG_RND_REQ_SUP_MASK          (0x1000000U)
#define ELS_ELS_CONFIG_RND_REQ_SUP_SHIFT         (24U)
/*! rnd_req_sup - rnd_req command is supported */
#define ELS_ELS_CONFIG_RND_REQ_SUP(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RND_REQ_SUP_SHIFT)) & ELS_ELS_CONFIG_RND_REQ_SUP_MASK)

#define ELS_ELS_CONFIG_DRBG_TEST_SUP_MASK        (0x2000000U)
#define ELS_ELS_CONFIG_DRBG_TEST_SUP_SHIFT       (25U)
/*! drbg_test_sup - drbg_test command is supported */
#define ELS_ELS_CONFIG_DRBG_TEST_SUP(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_DRBG_TEST_SUP_SHIFT)) & ELS_ELS_CONFIG_DRBG_TEST_SUP_MASK)

#define ELS_ELS_CONFIG_DTRNG_PRVL_CFG_LOAD_SUP_MASK (0x4000000U)
#define ELS_ELS_CONFIG_DTRNG_PRVL_CFG_LOAD_SUP_SHIFT (26U)
/*! dtrng_prvl_cfg_load_sup - dtrng_prvl_cfg_load command is supported */
#define ELS_ELS_CONFIG_DTRNG_PRVL_CFG_LOAD_SUP(x) (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_DTRNG_PRVL_CFG_LOAD_SUP_SHIFT)) & ELS_ELS_CONFIG_DTRNG_PRVL_CFG_LOAD_SUP_MASK)

#define ELS_ELS_CONFIG_RESERVED27_MASK           (0x8000000U)
#define ELS_ELS_CONFIG_RESERVED27_SHIFT          (27U)
/*! reserved27 - reserved */
#define ELS_ELS_CONFIG_RESERVED27(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED27_SHIFT)) & ELS_ELS_CONFIG_RESERVED27_MASK)

#define ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP_MASK   (0x10000000U)
#define ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP_SHIFT  (28U)
/*! dtrng_cfg_load_sup - dtrng_cfg_load command is supported */
#define ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP(x)     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP_SHIFT)) & ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP_MASK)

#define ELS_ELS_CONFIG_DTRNG_EVAL_SUP_MASK       (0x20000000U)
#define ELS_ELS_CONFIG_DTRNG_EVAL_SUP_SHIFT      (29U)
/*! dtrng_eval_sup - dtrng_eval command is supported */
#define ELS_ELS_CONFIG_DTRNG_EVAL_SUP(x)         (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_DTRNG_EVAL_SUP_SHIFT)) & ELS_ELS_CONFIG_DTRNG_EVAL_SUP_MASK)

#define ELS_ELS_CONFIG_RESERVED30_MASK           (0x40000000U)
#define ELS_ELS_CONFIG_RESERVED30_SHIFT          (30U)
/*! reserved30 - reserved */
#define ELS_ELS_CONFIG_RESERVED30(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED30_SHIFT)) & ELS_ELS_CONFIG_RESERVED30_MASK)

#define ELS_ELS_CONFIG_RESERVED31_MASK           (0x80000000U)
#define ELS_ELS_CONFIG_RESERVED31_SHIFT          (31U)
/*! reserved31 - reserved */
#define ELS_ELS_CONFIG_RESERVED31(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_RESERVED31_SHIFT)) & ELS_ELS_CONFIG_RESERVED31_MASK)
/*! @} */

/*! @name ELS_PRNG_DATOUT - PRNG SW Read Out Register */
/*! @{ */

#define ELS_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK     (0xFFFFFFFFU)
#define ELS_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT    (0U)
#define ELS_ELS_PRNG_DATOUT_PRNG_DATOUT(x)       (((uint32_t)(((uint32_t)(x)) << ELS_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & ELS_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK)
/*! @} */

/*! @name ELS_CMDCRC_CTRL - CRC Configuration Register */
/*! @{ */

#define ELS_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK      (0x1U)
#define ELS_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT     (0U)
#define ELS_ELS_CMDCRC_CTRL_CMDCRC_RST(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & ELS_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK)

#define ELS_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK       (0x2U)
#define ELS_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT      (1U)
#define ELS_ELS_CMDCRC_CTRL_CMDCRC_EN(x)         (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & ELS_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK)
/*! @} */

/*! @name ELS_CMDCRC - Command CRC Value Register */
/*! @{ */

#define ELS_ELS_CMDCRC_CMDCRC_MASK               (0xFFFFFFFFU)
#define ELS_ELS_CMDCRC_CMDCRC_SHIFT              (0U)
#define ELS_ELS_CMDCRC_CMDCRC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CMDCRC_CMDCRC_SHIFT)) & ELS_ELS_CMDCRC_CMDCRC_MASK)
/*! @} */

/*! @name ELS_SESSION_ID - Session ID Register */
/*! @{ */

#define ELS_ELS_SESSION_ID_SESSION_ID_MASK       (0xFFFFFFFFU)
#define ELS_ELS_SESSION_ID_SESSION_ID_SHIFT      (0U)
#define ELS_ELS_SESSION_ID_SESSION_ID(x)         (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SESSION_ID_SESSION_ID_SHIFT)) & ELS_ELS_SESSION_ID_SESSION_ID_MASK)
/*! @} */

/*! @name ELS_DMA_FIN_ADDR - Final DMA Address Register */
/*! @{ */

#define ELS_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK   (0xFFFFFFFFU)
#define ELS_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT  (0U)
#define ELS_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & ELS_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK)
/*! @} */

/*! @name ELS_MASTER_ID - Master ID Register */
/*! @{ */

#define ELS_ELS_MASTER_ID_MASTER_ID_MASK         (0x1FU)
#define ELS_ELS_MASTER_ID_MASTER_ID_SHIFT        (0U)
#define ELS_ELS_MASTER_ID_MASTER_ID(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_MASTER_ID_MASTER_ID_SHIFT)) & ELS_ELS_MASTER_ID_MASTER_ID_MASK)
/*! @} */

/*! @name ELS_KIDX2 - Keystore Index 2 Register */
/*! @{ */

#define ELS_ELS_KIDX2_KIDX2_MASK                 (0x1FU)
#define ELS_ELS_KIDX2_KIDX2_SHIFT                (0U)
#define ELS_ELS_KIDX2_KIDX2(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KIDX2_KIDX2_SHIFT)) & ELS_ELS_KIDX2_KIDX2_MASK)
/*! @} */

/*! @name ELS_SHA2_STATUS - SHA2 Status Register */
/*! @{ */

#define ELS_ELS_SHA2_STATUS_SHA2_BUSY_MASK       (0x1U)
#define ELS_ELS_SHA2_STATUS_SHA2_BUSY_SHIFT      (0U)
#define ELS_ELS_SHA2_STATUS_SHA2_BUSY(x)         (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_STATUS_SHA2_BUSY_SHIFT)) & ELS_ELS_SHA2_STATUS_SHA2_BUSY_MASK)
/*! @} */

/*! @name ELS_SHA2_CTRL - SHA2 Control Register */
/*! @{ */

#define ELS_ELS_SHA2_CTRL_SHA2_START_MASK        (0x1U)
#define ELS_ELS_SHA2_CTRL_SHA2_START_SHIFT       (0U)
/*! sha2_start - Write to 1 to Init the SHA2 Module */
#define ELS_ELS_SHA2_CTRL_SHA2_START(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_START_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_START_MASK)

#define ELS_ELS_SHA2_CTRL_SHA2_RST_MASK          (0x2U)
#define ELS_ELS_SHA2_CTRL_SHA2_RST_SHIFT         (1U)
/*! sha2_rst - Write to 1 to Reset a SHA2 operation */
#define ELS_ELS_SHA2_CTRL_SHA2_RST(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_RST_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_RST_MASK)

#define ELS_ELS_SHA2_CTRL_SHA2_INIT_MASK         (0x4U)
#define ELS_ELS_SHA2_CTRL_SHA2_INIT_SHIFT        (2U)
/*! sha2_init - Write to 1 to Init the SHA2 Kernel */
#define ELS_ELS_SHA2_CTRL_SHA2_INIT(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_INIT_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_INIT_MASK)

#define ELS_ELS_SHA2_CTRL_SHA2_LOAD_MASK         (0x8U)
#define ELS_ELS_SHA2_CTRL_SHA2_LOAD_SHIFT        (3U)
/*! sha2_load - Write to 1 to Load the SHA2 Kernel */
#define ELS_ELS_SHA2_CTRL_SHA2_LOAD(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_LOAD_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_LOAD_MASK)

#define ELS_ELS_SHA2_CTRL_SHA2_MODE_MASK         (0x30U)
#define ELS_ELS_SHA2_CTRL_SHA2_MODE_SHIFT        (4U)
/*! sha2_mode - SHA2 MODE: */
#define ELS_ELS_SHA2_CTRL_SHA2_MODE(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_MODE_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_MODE_MASK)

#define ELS_ELS_SHA2_CTRL_CTRL_RSVD1_MASK        (0x1C0U)
#define ELS_ELS_SHA2_CTRL_CTRL_RSVD1_SHIFT       (6U)
/*! ctrl_rsvd1 - r-eserved */
#define ELS_ELS_SHA2_CTRL_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_CTRL_RSVD1_SHIFT)) & ELS_ELS_SHA2_CTRL_CTRL_RSVD1_MASK)

#define ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER_MASK   (0x200U)
#define ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER_SHIFT  (9U)
/*! sha2_byte_order - Write to 1 to Reverse byte endianess */
#define ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER(x)     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER_MASK)

#define ELS_ELS_SHA2_CTRL_CTRL_RSVD_MASK         (0xFFFFFC00U)
#define ELS_ELS_SHA2_CTRL_CTRL_RSVD_SHIFT        (10U)
/*! ctrl_rsvd - r-eserved */
#define ELS_ELS_SHA2_CTRL_CTRL_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_CTRL_RSVD_SHIFT)) & ELS_ELS_SHA2_CTRL_CTRL_RSVD_MASK)
/*! @} */

/*! @name ELS_SHA2_DIN - SHA_DATA IN 0 Register */
/*! @{ */

#define ELS_ELS_SHA2_DIN_SHA_DATIN_MASK          (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DIN_SHA_DATIN_SHIFT         (0U)
#define ELS_ELS_SHA2_DIN_SHA_DATIN(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DIN_SHA_DATIN_SHIFT)) & ELS_ELS_SHA2_DIN_SHA_DATIN_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT0 - SHA_DATA Out 0 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT0_SHA_DATA0_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT0_SHA_DATA0_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT0_SHA_DATA0(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT0_SHA_DATA0_SHIFT)) & ELS_ELS_SHA2_DOUT0_SHA_DATA0_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT1 - SHA_DATA Out 1 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT1_SHA_DATA1_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT1_SHA_DATA1_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT1_SHA_DATA1(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT1_SHA_DATA1_SHIFT)) & ELS_ELS_SHA2_DOUT1_SHA_DATA1_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT2 - SHA_DATA Out 2 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT2_SHA_DATA2_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT2_SHA_DATA2_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT2_SHA_DATA2(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT2_SHA_DATA2_SHIFT)) & ELS_ELS_SHA2_DOUT2_SHA_DATA2_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT3 - SHA_DATA Out 3 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT3_SHA_DATA3_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT3_SHA_DATA3_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT3_SHA_DATA3(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT3_SHA_DATA3_SHIFT)) & ELS_ELS_SHA2_DOUT3_SHA_DATA3_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT4 - SHA_DATA Out 4 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT4_SHA_DATA4_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT4_SHA_DATA4_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT4_SHA_DATA4(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT4_SHA_DATA4_SHIFT)) & ELS_ELS_SHA2_DOUT4_SHA_DATA4_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT5 - SHA_DATA Out 5 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT5_SHA_DATA5_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT5_SHA_DATA5_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT5_SHA_DATA5(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT5_SHA_DATA5_SHIFT)) & ELS_ELS_SHA2_DOUT5_SHA_DATA5_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT6 - SHA_DATA Out 6 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT6_SHA_DATA6_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT6_SHA_DATA6_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT6_SHA_DATA6(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT6_SHA_DATA6_SHIFT)) & ELS_ELS_SHA2_DOUT6_SHA_DATA6_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT7 - SHA_DATA Out 7 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT7_SHA_DATA7_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT7_SHA_DATA7_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT7_SHA_DATA7(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT7_SHA_DATA7_SHIFT)) & ELS_ELS_SHA2_DOUT7_SHA_DATA7_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT8 - SHA_DATA Out 8 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT8_SHA_DATA8_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT8_SHA_DATA8_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT8_SHA_DATA8(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT8_SHA_DATA8_SHIFT)) & ELS_ELS_SHA2_DOUT8_SHA_DATA8_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT9 - SHA_DATA Out 9 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT9_SHA_DATA9_MASK        (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT9_SHA_DATA9_SHIFT       (0U)
#define ELS_ELS_SHA2_DOUT9_SHA_DATA9(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT9_SHA_DATA9_SHIFT)) & ELS_ELS_SHA2_DOUT9_SHA_DATA9_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT10 - SHA_DATA Out 10 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT10_SHA_DATA10_MASK      (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT10_SHA_DATA10_SHIFT     (0U)
#define ELS_ELS_SHA2_DOUT10_SHA_DATA10(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT10_SHA_DATA10_SHIFT)) & ELS_ELS_SHA2_DOUT10_SHA_DATA10_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT11 - SHA_DATA Out 11 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT11_SHA_DATA11_MASK      (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT11_SHA_DATA11_SHIFT     (0U)
#define ELS_ELS_SHA2_DOUT11_SHA_DATA11(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT11_SHA_DATA11_SHIFT)) & ELS_ELS_SHA2_DOUT11_SHA_DATA11_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT12 - SHA_DATA Out 12 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT12_SHA_DATA12_MASK      (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT12_SHA_DATA12_SHIFT     (0U)
#define ELS_ELS_SHA2_DOUT12_SHA_DATA12(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT12_SHA_DATA12_SHIFT)) & ELS_ELS_SHA2_DOUT12_SHA_DATA12_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT13 - SHA_DATA Out 13 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT13_SHA_DATA13_MASK      (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT13_SHA_DATA13_SHIFT     (0U)
#define ELS_ELS_SHA2_DOUT13_SHA_DATA13(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT13_SHA_DATA13_SHIFT)) & ELS_ELS_SHA2_DOUT13_SHA_DATA13_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT14 - SHA_DATA Out 14 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT14_SHA_DATA14_MASK      (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT14_SHA_DATA14_SHIFT     (0U)
#define ELS_ELS_SHA2_DOUT14_SHA_DATA14(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT14_SHA_DATA14_SHIFT)) & ELS_ELS_SHA2_DOUT14_SHA_DATA14_MASK)
/*! @} */

/*! @name ELS_SHA2_DOUT15 - SHA_DATA Out 15 Register */
/*! @{ */

#define ELS_ELS_SHA2_DOUT15_SHA_DATA15_MASK      (0xFFFFFFFFU)
#define ELS_ELS_SHA2_DOUT15_SHA_DATA15_SHIFT     (0U)
#define ELS_ELS_SHA2_DOUT15_SHA_DATA15(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT15_SHA_DATA15_SHIFT)) & ELS_ELS_SHA2_DOUT15_SHA_DATA15_MASK)
/*! @} */

/*! @name ELS_KS0 - Status Register */
/*! @{ */

#define ELS_ELS_KS0_KS0_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS0_KS0_KSIZE_SHIFT              (0U)
/*! KS0_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS0_KS0_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_KSIZE_SHIFT)) & ELS_ELS_KS0_KS0_KSIZE_MASK)

#define ELS_ELS_KS0_KS0_KACT_MASK                (0x20U)
#define ELS_ELS_KS0_KS0_KACT_SHIFT               (5U)
#define ELS_ELS_KS0_KS0_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_KACT_SHIFT)) & ELS_ELS_KS0_KS0_KACT_MASK)

#define ELS_ELS_KS0_KS0_KBASE_MASK               (0x40U)
#define ELS_ELS_KS0_KS0_KBASE_SHIFT              (6U)
#define ELS_ELS_KS0_KS0_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_KBASE_SHIFT)) & ELS_ELS_KS0_KS0_KBASE_MASK)

#define ELS_ELS_KS0_KS0_FGP_MASK                 (0x80U)
#define ELS_ELS_KS0_KS0_FGP_SHIFT                (7U)
#define ELS_ELS_KS0_KS0_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_FGP_SHIFT)) & ELS_ELS_KS0_KS0_FGP_MASK)

#define ELS_ELS_KS0_KS0_FRTN_MASK                (0x100U)
#define ELS_ELS_KS0_KS0_FRTN_SHIFT               (8U)
#define ELS_ELS_KS0_KS0_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_FRTN_SHIFT)) & ELS_ELS_KS0_KS0_FRTN_MASK)

#define ELS_ELS_KS0_KS0_FHWO_MASK                (0x200U)
#define ELS_ELS_KS0_KS0_FHWO_SHIFT               (9U)
#define ELS_ELS_KS0_KS0_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_FHWO_SHIFT)) & ELS_ELS_KS0_KS0_FHWO_MASK)

#define ELS_ELS_KS0_KS0_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS0_KS0_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS0_KS0_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKPUK_SHIFT)) & ELS_ELS_KS0_KS0_UKPUK_MASK)

#define ELS_ELS_KS0_KS0_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS0_KS0_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS0_KS0_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UTECDH_SHIFT)) & ELS_ELS_KS0_KS0_UTECDH_MASK)

#define ELS_ELS_KS0_KS0_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS0_KS0_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS0_KS0_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UCMAC_SHIFT)) & ELS_ELS_KS0_KS0_UCMAC_MASK)

#define ELS_ELS_KS0_KS0_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS0_KS0_UKSK_SHIFT               (14U)
#define ELS_ELS_KS0_KS0_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKSK_SHIFT)) & ELS_ELS_KS0_KS0_UKSK_MASK)

#define ELS_ELS_KS0_KS0_URTF_MASK                (0x8000U)
#define ELS_ELS_KS0_KS0_URTF_SHIFT               (15U)
#define ELS_ELS_KS0_KS0_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_URTF_SHIFT)) & ELS_ELS_KS0_KS0_URTF_MASK)

#define ELS_ELS_KS0_KS0_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS0_KS0_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS0_KS0_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UCKDF_SHIFT)) & ELS_ELS_KS0_KS0_UCKDF_MASK)

#define ELS_ELS_KS0_KS0_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS0_KS0_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS0_KS0_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UHKDF_SHIFT)) & ELS_ELS_KS0_KS0_UHKDF_MASK)

#define ELS_ELS_KS0_KS0_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS0_KS0_UECSG_SHIFT              (18U)
#define ELS_ELS_KS0_KS0_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UECSG_SHIFT)) & ELS_ELS_KS0_KS0_UECSG_MASK)

#define ELS_ELS_KS0_KS0_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS0_KS0_UECDH_SHIFT              (19U)
#define ELS_ELS_KS0_KS0_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UECDH_SHIFT)) & ELS_ELS_KS0_KS0_UECDH_MASK)

#define ELS_ELS_KS0_KS0_UAES_MASK                (0x100000U)
#define ELS_ELS_KS0_KS0_UAES_SHIFT               (20U)
#define ELS_ELS_KS0_KS0_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UAES_SHIFT)) & ELS_ELS_KS0_KS0_UAES_MASK)

#define ELS_ELS_KS0_KS0_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS0_KS0_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS0_KS0_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UHMAC_SHIFT)) & ELS_ELS_KS0_KS0_UHMAC_MASK)

#define ELS_ELS_KS0_KS0_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS0_KS0_UKWK_SHIFT               (22U)
#define ELS_ELS_KS0_KS0_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKWK_SHIFT)) & ELS_ELS_KS0_KS0_UKWK_MASK)

#define ELS_ELS_KS0_KS0_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS0_KS0_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS0_KS0_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKUOK_SHIFT)) & ELS_ELS_KS0_KS0_UKUOK_MASK)

#define ELS_ELS_KS0_KS0_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS0_KS0_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS0_KS0_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UTLSPMS_SHIFT)) & ELS_ELS_KS0_KS0_UTLSPMS_MASK)

#define ELS_ELS_KS0_KS0_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS0_KS0_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS0_KS0_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UTLSMS_SHIFT)) & ELS_ELS_KS0_KS0_UTLSMS_MASK)

#define ELS_ELS_KS0_KS0_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS0_KS0_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS0_KS0_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKGSRC_SHIFT)) & ELS_ELS_KS0_KS0_UKGSRC_MASK)

#define ELS_ELS_KS0_KS0_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS0_KS0_UHWO_SHIFT               (27U)
#define ELS_ELS_KS0_KS0_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UHWO_SHIFT)) & ELS_ELS_KS0_KS0_UHWO_MASK)

#define ELS_ELS_KS0_KS0_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS0_KS0_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS0_KS0_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UWRPOK_SHIFT)) & ELS_ELS_KS0_KS0_UWRPOK_MASK)

#define ELS_ELS_KS0_KS0_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS0_KS0_UDUK_SHIFT               (29U)
#define ELS_ELS_KS0_KS0_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UDUK_SHIFT)) & ELS_ELS_KS0_KS0_UDUK_MASK)

#define ELS_ELS_KS0_KS0_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS0_KS0_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS0_KS0_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UPPROT_SHIFT)) & ELS_ELS_KS0_KS0_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS1 - Status Register */
/*! @{ */

#define ELS_ELS_KS1_KS1_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS1_KS1_KSIZE_SHIFT              (0U)
/*! KS1_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS1_KS1_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_KSIZE_SHIFT)) & ELS_ELS_KS1_KS1_KSIZE_MASK)

#define ELS_ELS_KS1_KS1_KACT_MASK                (0x20U)
#define ELS_ELS_KS1_KS1_KACT_SHIFT               (5U)
#define ELS_ELS_KS1_KS1_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_KACT_SHIFT)) & ELS_ELS_KS1_KS1_KACT_MASK)

#define ELS_ELS_KS1_KS1_KBASE_MASK               (0x40U)
#define ELS_ELS_KS1_KS1_KBASE_SHIFT              (6U)
#define ELS_ELS_KS1_KS1_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_KBASE_SHIFT)) & ELS_ELS_KS1_KS1_KBASE_MASK)

#define ELS_ELS_KS1_KS1_FGP_MASK                 (0x80U)
#define ELS_ELS_KS1_KS1_FGP_SHIFT                (7U)
#define ELS_ELS_KS1_KS1_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_FGP_SHIFT)) & ELS_ELS_KS1_KS1_FGP_MASK)

#define ELS_ELS_KS1_KS1_FRTN_MASK                (0x100U)
#define ELS_ELS_KS1_KS1_FRTN_SHIFT               (8U)
#define ELS_ELS_KS1_KS1_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_FRTN_SHIFT)) & ELS_ELS_KS1_KS1_FRTN_MASK)

#define ELS_ELS_KS1_KS1_FHWO_MASK                (0x200U)
#define ELS_ELS_KS1_KS1_FHWO_SHIFT               (9U)
#define ELS_ELS_KS1_KS1_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_FHWO_SHIFT)) & ELS_ELS_KS1_KS1_FHWO_MASK)

#define ELS_ELS_KS1_KS1_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS1_KS1_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS1_KS1_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKPUK_SHIFT)) & ELS_ELS_KS1_KS1_UKPUK_MASK)

#define ELS_ELS_KS1_KS1_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS1_KS1_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS1_KS1_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UTECDH_SHIFT)) & ELS_ELS_KS1_KS1_UTECDH_MASK)

#define ELS_ELS_KS1_KS1_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS1_KS1_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS1_KS1_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UCMAC_SHIFT)) & ELS_ELS_KS1_KS1_UCMAC_MASK)

#define ELS_ELS_KS1_KS1_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS1_KS1_UKSK_SHIFT               (14U)
#define ELS_ELS_KS1_KS1_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKSK_SHIFT)) & ELS_ELS_KS1_KS1_UKSK_MASK)

#define ELS_ELS_KS1_KS1_URTF_MASK                (0x8000U)
#define ELS_ELS_KS1_KS1_URTF_SHIFT               (15U)
#define ELS_ELS_KS1_KS1_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_URTF_SHIFT)) & ELS_ELS_KS1_KS1_URTF_MASK)

#define ELS_ELS_KS1_KS1_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS1_KS1_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS1_KS1_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UCKDF_SHIFT)) & ELS_ELS_KS1_KS1_UCKDF_MASK)

#define ELS_ELS_KS1_KS1_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS1_KS1_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS1_KS1_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UHKDF_SHIFT)) & ELS_ELS_KS1_KS1_UHKDF_MASK)

#define ELS_ELS_KS1_KS1_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS1_KS1_UECSG_SHIFT              (18U)
#define ELS_ELS_KS1_KS1_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UECSG_SHIFT)) & ELS_ELS_KS1_KS1_UECSG_MASK)

#define ELS_ELS_KS1_KS1_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS1_KS1_UECDH_SHIFT              (19U)
#define ELS_ELS_KS1_KS1_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UECDH_SHIFT)) & ELS_ELS_KS1_KS1_UECDH_MASK)

#define ELS_ELS_KS1_KS1_UAES_MASK                (0x100000U)
#define ELS_ELS_KS1_KS1_UAES_SHIFT               (20U)
#define ELS_ELS_KS1_KS1_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UAES_SHIFT)) & ELS_ELS_KS1_KS1_UAES_MASK)

#define ELS_ELS_KS1_KS1_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS1_KS1_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS1_KS1_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UHMAC_SHIFT)) & ELS_ELS_KS1_KS1_UHMAC_MASK)

#define ELS_ELS_KS1_KS1_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS1_KS1_UKWK_SHIFT               (22U)
#define ELS_ELS_KS1_KS1_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKWK_SHIFT)) & ELS_ELS_KS1_KS1_UKWK_MASK)

#define ELS_ELS_KS1_KS1_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS1_KS1_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS1_KS1_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKUOK_SHIFT)) & ELS_ELS_KS1_KS1_UKUOK_MASK)

#define ELS_ELS_KS1_KS1_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS1_KS1_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS1_KS1_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UTLSPMS_SHIFT)) & ELS_ELS_KS1_KS1_UTLSPMS_MASK)

#define ELS_ELS_KS1_KS1_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS1_KS1_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS1_KS1_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UTLSMS_SHIFT)) & ELS_ELS_KS1_KS1_UTLSMS_MASK)

#define ELS_ELS_KS1_KS1_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS1_KS1_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS1_KS1_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKGSRC_SHIFT)) & ELS_ELS_KS1_KS1_UKGSRC_MASK)

#define ELS_ELS_KS1_KS1_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS1_KS1_UHWO_SHIFT               (27U)
#define ELS_ELS_KS1_KS1_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UHWO_SHIFT)) & ELS_ELS_KS1_KS1_UHWO_MASK)

#define ELS_ELS_KS1_KS1_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS1_KS1_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS1_KS1_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UWRPOK_SHIFT)) & ELS_ELS_KS1_KS1_UWRPOK_MASK)

#define ELS_ELS_KS1_KS1_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS1_KS1_UDUK_SHIFT               (29U)
#define ELS_ELS_KS1_KS1_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UDUK_SHIFT)) & ELS_ELS_KS1_KS1_UDUK_MASK)

#define ELS_ELS_KS1_KS1_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS1_KS1_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS1_KS1_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UPPROT_SHIFT)) & ELS_ELS_KS1_KS1_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS2 - Status Register */
/*! @{ */

#define ELS_ELS_KS2_KS2_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS2_KS2_KSIZE_SHIFT              (0U)
/*! KS2_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS2_KS2_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_KSIZE_SHIFT)) & ELS_ELS_KS2_KS2_KSIZE_MASK)

#define ELS_ELS_KS2_KS2_KACT_MASK                (0x20U)
#define ELS_ELS_KS2_KS2_KACT_SHIFT               (5U)
#define ELS_ELS_KS2_KS2_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_KACT_SHIFT)) & ELS_ELS_KS2_KS2_KACT_MASK)

#define ELS_ELS_KS2_KS2_KBASE_MASK               (0x40U)
#define ELS_ELS_KS2_KS2_KBASE_SHIFT              (6U)
#define ELS_ELS_KS2_KS2_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_KBASE_SHIFT)) & ELS_ELS_KS2_KS2_KBASE_MASK)

#define ELS_ELS_KS2_KS2_FGP_MASK                 (0x80U)
#define ELS_ELS_KS2_KS2_FGP_SHIFT                (7U)
#define ELS_ELS_KS2_KS2_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_FGP_SHIFT)) & ELS_ELS_KS2_KS2_FGP_MASK)

#define ELS_ELS_KS2_KS2_FRTN_MASK                (0x100U)
#define ELS_ELS_KS2_KS2_FRTN_SHIFT               (8U)
#define ELS_ELS_KS2_KS2_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_FRTN_SHIFT)) & ELS_ELS_KS2_KS2_FRTN_MASK)

#define ELS_ELS_KS2_KS2_FHWO_MASK                (0x200U)
#define ELS_ELS_KS2_KS2_FHWO_SHIFT               (9U)
#define ELS_ELS_KS2_KS2_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_FHWO_SHIFT)) & ELS_ELS_KS2_KS2_FHWO_MASK)

#define ELS_ELS_KS2_KS2_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS2_KS2_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS2_KS2_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKPUK_SHIFT)) & ELS_ELS_KS2_KS2_UKPUK_MASK)

#define ELS_ELS_KS2_KS2_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS2_KS2_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS2_KS2_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UTECDH_SHIFT)) & ELS_ELS_KS2_KS2_UTECDH_MASK)

#define ELS_ELS_KS2_KS2_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS2_KS2_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS2_KS2_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UCMAC_SHIFT)) & ELS_ELS_KS2_KS2_UCMAC_MASK)

#define ELS_ELS_KS2_KS2_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS2_KS2_UKSK_SHIFT               (14U)
#define ELS_ELS_KS2_KS2_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKSK_SHIFT)) & ELS_ELS_KS2_KS2_UKSK_MASK)

#define ELS_ELS_KS2_KS2_URTF_MASK                (0x8000U)
#define ELS_ELS_KS2_KS2_URTF_SHIFT               (15U)
#define ELS_ELS_KS2_KS2_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_URTF_SHIFT)) & ELS_ELS_KS2_KS2_URTF_MASK)

#define ELS_ELS_KS2_KS2_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS2_KS2_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS2_KS2_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UCKDF_SHIFT)) & ELS_ELS_KS2_KS2_UCKDF_MASK)

#define ELS_ELS_KS2_KS2_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS2_KS2_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS2_KS2_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UHKDF_SHIFT)) & ELS_ELS_KS2_KS2_UHKDF_MASK)

#define ELS_ELS_KS2_KS2_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS2_KS2_UECSG_SHIFT              (18U)
#define ELS_ELS_KS2_KS2_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UECSG_SHIFT)) & ELS_ELS_KS2_KS2_UECSG_MASK)

#define ELS_ELS_KS2_KS2_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS2_KS2_UECDH_SHIFT              (19U)
#define ELS_ELS_KS2_KS2_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UECDH_SHIFT)) & ELS_ELS_KS2_KS2_UECDH_MASK)

#define ELS_ELS_KS2_KS2_UAES_MASK                (0x100000U)
#define ELS_ELS_KS2_KS2_UAES_SHIFT               (20U)
#define ELS_ELS_KS2_KS2_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UAES_SHIFT)) & ELS_ELS_KS2_KS2_UAES_MASK)

#define ELS_ELS_KS2_KS2_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS2_KS2_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS2_KS2_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UHMAC_SHIFT)) & ELS_ELS_KS2_KS2_UHMAC_MASK)

#define ELS_ELS_KS2_KS2_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS2_KS2_UKWK_SHIFT               (22U)
#define ELS_ELS_KS2_KS2_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKWK_SHIFT)) & ELS_ELS_KS2_KS2_UKWK_MASK)

#define ELS_ELS_KS2_KS2_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS2_KS2_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS2_KS2_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKUOK_SHIFT)) & ELS_ELS_KS2_KS2_UKUOK_MASK)

#define ELS_ELS_KS2_KS2_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS2_KS2_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS2_KS2_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UTLSPMS_SHIFT)) & ELS_ELS_KS2_KS2_UTLSPMS_MASK)

#define ELS_ELS_KS2_KS2_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS2_KS2_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS2_KS2_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UTLSMS_SHIFT)) & ELS_ELS_KS2_KS2_UTLSMS_MASK)

#define ELS_ELS_KS2_KS2_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS2_KS2_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS2_KS2_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKGSRC_SHIFT)) & ELS_ELS_KS2_KS2_UKGSRC_MASK)

#define ELS_ELS_KS2_KS2_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS2_KS2_UHWO_SHIFT               (27U)
#define ELS_ELS_KS2_KS2_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UHWO_SHIFT)) & ELS_ELS_KS2_KS2_UHWO_MASK)

#define ELS_ELS_KS2_KS2_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS2_KS2_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS2_KS2_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UWRPOK_SHIFT)) & ELS_ELS_KS2_KS2_UWRPOK_MASK)

#define ELS_ELS_KS2_KS2_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS2_KS2_UDUK_SHIFT               (29U)
#define ELS_ELS_KS2_KS2_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UDUK_SHIFT)) & ELS_ELS_KS2_KS2_UDUK_MASK)

#define ELS_ELS_KS2_KS2_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS2_KS2_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS2_KS2_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UPPROT_SHIFT)) & ELS_ELS_KS2_KS2_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS3 - Status Register */
/*! @{ */

#define ELS_ELS_KS3_KS3_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS3_KS3_KSIZE_SHIFT              (0U)
/*! KS3_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS3_KS3_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_KSIZE_SHIFT)) & ELS_ELS_KS3_KS3_KSIZE_MASK)

#define ELS_ELS_KS3_KS3_KACT_MASK                (0x20U)
#define ELS_ELS_KS3_KS3_KACT_SHIFT               (5U)
#define ELS_ELS_KS3_KS3_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_KACT_SHIFT)) & ELS_ELS_KS3_KS3_KACT_MASK)

#define ELS_ELS_KS3_KS3_KBASE_MASK               (0x40U)
#define ELS_ELS_KS3_KS3_KBASE_SHIFT              (6U)
#define ELS_ELS_KS3_KS3_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_KBASE_SHIFT)) & ELS_ELS_KS3_KS3_KBASE_MASK)

#define ELS_ELS_KS3_KS3_FGP_MASK                 (0x80U)
#define ELS_ELS_KS3_KS3_FGP_SHIFT                (7U)
#define ELS_ELS_KS3_KS3_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_FGP_SHIFT)) & ELS_ELS_KS3_KS3_FGP_MASK)

#define ELS_ELS_KS3_KS3_FRTN_MASK                (0x100U)
#define ELS_ELS_KS3_KS3_FRTN_SHIFT               (8U)
#define ELS_ELS_KS3_KS3_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_FRTN_SHIFT)) & ELS_ELS_KS3_KS3_FRTN_MASK)

#define ELS_ELS_KS3_KS3_FHWO_MASK                (0x200U)
#define ELS_ELS_KS3_KS3_FHWO_SHIFT               (9U)
#define ELS_ELS_KS3_KS3_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_FHWO_SHIFT)) & ELS_ELS_KS3_KS3_FHWO_MASK)

#define ELS_ELS_KS3_KS3_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS3_KS3_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS3_KS3_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKPUK_SHIFT)) & ELS_ELS_KS3_KS3_UKPUK_MASK)

#define ELS_ELS_KS3_KS3_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS3_KS3_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS3_KS3_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UTECDH_SHIFT)) & ELS_ELS_KS3_KS3_UTECDH_MASK)

#define ELS_ELS_KS3_KS3_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS3_KS3_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS3_KS3_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UCMAC_SHIFT)) & ELS_ELS_KS3_KS3_UCMAC_MASK)

#define ELS_ELS_KS3_KS3_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS3_KS3_UKSK_SHIFT               (14U)
#define ELS_ELS_KS3_KS3_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKSK_SHIFT)) & ELS_ELS_KS3_KS3_UKSK_MASK)

#define ELS_ELS_KS3_KS3_URTF_MASK                (0x8000U)
#define ELS_ELS_KS3_KS3_URTF_SHIFT               (15U)
#define ELS_ELS_KS3_KS3_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_URTF_SHIFT)) & ELS_ELS_KS3_KS3_URTF_MASK)

#define ELS_ELS_KS3_KS3_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS3_KS3_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS3_KS3_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UCKDF_SHIFT)) & ELS_ELS_KS3_KS3_UCKDF_MASK)

#define ELS_ELS_KS3_KS3_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS3_KS3_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS3_KS3_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UHKDF_SHIFT)) & ELS_ELS_KS3_KS3_UHKDF_MASK)

#define ELS_ELS_KS3_KS3_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS3_KS3_UECSG_SHIFT              (18U)
#define ELS_ELS_KS3_KS3_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UECSG_SHIFT)) & ELS_ELS_KS3_KS3_UECSG_MASK)

#define ELS_ELS_KS3_KS3_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS3_KS3_UECDH_SHIFT              (19U)
#define ELS_ELS_KS3_KS3_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UECDH_SHIFT)) & ELS_ELS_KS3_KS3_UECDH_MASK)

#define ELS_ELS_KS3_KS3_UAES_MASK                (0x100000U)
#define ELS_ELS_KS3_KS3_UAES_SHIFT               (20U)
#define ELS_ELS_KS3_KS3_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UAES_SHIFT)) & ELS_ELS_KS3_KS3_UAES_MASK)

#define ELS_ELS_KS3_KS3_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS3_KS3_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS3_KS3_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UHMAC_SHIFT)) & ELS_ELS_KS3_KS3_UHMAC_MASK)

#define ELS_ELS_KS3_KS3_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS3_KS3_UKWK_SHIFT               (22U)
#define ELS_ELS_KS3_KS3_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKWK_SHIFT)) & ELS_ELS_KS3_KS3_UKWK_MASK)

#define ELS_ELS_KS3_KS3_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS3_KS3_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS3_KS3_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKUOK_SHIFT)) & ELS_ELS_KS3_KS3_UKUOK_MASK)

#define ELS_ELS_KS3_KS3_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS3_KS3_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS3_KS3_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UTLSPMS_SHIFT)) & ELS_ELS_KS3_KS3_UTLSPMS_MASK)

#define ELS_ELS_KS3_KS3_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS3_KS3_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS3_KS3_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UTLSMS_SHIFT)) & ELS_ELS_KS3_KS3_UTLSMS_MASK)

#define ELS_ELS_KS3_KS3_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS3_KS3_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS3_KS3_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKGSRC_SHIFT)) & ELS_ELS_KS3_KS3_UKGSRC_MASK)

#define ELS_ELS_KS3_KS3_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS3_KS3_UHWO_SHIFT               (27U)
#define ELS_ELS_KS3_KS3_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UHWO_SHIFT)) & ELS_ELS_KS3_KS3_UHWO_MASK)

#define ELS_ELS_KS3_KS3_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS3_KS3_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS3_KS3_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UWRPOK_SHIFT)) & ELS_ELS_KS3_KS3_UWRPOK_MASK)

#define ELS_ELS_KS3_KS3_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS3_KS3_UDUK_SHIFT               (29U)
#define ELS_ELS_KS3_KS3_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UDUK_SHIFT)) & ELS_ELS_KS3_KS3_UDUK_MASK)

#define ELS_ELS_KS3_KS3_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS3_KS3_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS3_KS3_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UPPROT_SHIFT)) & ELS_ELS_KS3_KS3_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS4 - Status Register */
/*! @{ */

#define ELS_ELS_KS4_KS4_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS4_KS4_KSIZE_SHIFT              (0U)
/*! KS4_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS4_KS4_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_KSIZE_SHIFT)) & ELS_ELS_KS4_KS4_KSIZE_MASK)

#define ELS_ELS_KS4_KS4_KACT_MASK                (0x20U)
#define ELS_ELS_KS4_KS4_KACT_SHIFT               (5U)
#define ELS_ELS_KS4_KS4_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_KACT_SHIFT)) & ELS_ELS_KS4_KS4_KACT_MASK)

#define ELS_ELS_KS4_KS4_KBASE_MASK               (0x40U)
#define ELS_ELS_KS4_KS4_KBASE_SHIFT              (6U)
#define ELS_ELS_KS4_KS4_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_KBASE_SHIFT)) & ELS_ELS_KS4_KS4_KBASE_MASK)

#define ELS_ELS_KS4_KS4_FGP_MASK                 (0x80U)
#define ELS_ELS_KS4_KS4_FGP_SHIFT                (7U)
#define ELS_ELS_KS4_KS4_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_FGP_SHIFT)) & ELS_ELS_KS4_KS4_FGP_MASK)

#define ELS_ELS_KS4_KS4_FRTN_MASK                (0x100U)
#define ELS_ELS_KS4_KS4_FRTN_SHIFT               (8U)
#define ELS_ELS_KS4_KS4_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_FRTN_SHIFT)) & ELS_ELS_KS4_KS4_FRTN_MASK)

#define ELS_ELS_KS4_KS4_FHWO_MASK                (0x200U)
#define ELS_ELS_KS4_KS4_FHWO_SHIFT               (9U)
#define ELS_ELS_KS4_KS4_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_FHWO_SHIFT)) & ELS_ELS_KS4_KS4_FHWO_MASK)

#define ELS_ELS_KS4_KS4_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS4_KS4_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS4_KS4_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKPUK_SHIFT)) & ELS_ELS_KS4_KS4_UKPUK_MASK)

#define ELS_ELS_KS4_KS4_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS4_KS4_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS4_KS4_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UTECDH_SHIFT)) & ELS_ELS_KS4_KS4_UTECDH_MASK)

#define ELS_ELS_KS4_KS4_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS4_KS4_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS4_KS4_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UCMAC_SHIFT)) & ELS_ELS_KS4_KS4_UCMAC_MASK)

#define ELS_ELS_KS4_KS4_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS4_KS4_UKSK_SHIFT               (14U)
#define ELS_ELS_KS4_KS4_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKSK_SHIFT)) & ELS_ELS_KS4_KS4_UKSK_MASK)

#define ELS_ELS_KS4_KS4_URTF_MASK                (0x8000U)
#define ELS_ELS_KS4_KS4_URTF_SHIFT               (15U)
#define ELS_ELS_KS4_KS4_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_URTF_SHIFT)) & ELS_ELS_KS4_KS4_URTF_MASK)

#define ELS_ELS_KS4_KS4_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS4_KS4_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS4_KS4_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UCKDF_SHIFT)) & ELS_ELS_KS4_KS4_UCKDF_MASK)

#define ELS_ELS_KS4_KS4_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS4_KS4_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS4_KS4_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UHKDF_SHIFT)) & ELS_ELS_KS4_KS4_UHKDF_MASK)

#define ELS_ELS_KS4_KS4_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS4_KS4_UECSG_SHIFT              (18U)
#define ELS_ELS_KS4_KS4_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UECSG_SHIFT)) & ELS_ELS_KS4_KS4_UECSG_MASK)

#define ELS_ELS_KS4_KS4_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS4_KS4_UECDH_SHIFT              (19U)
#define ELS_ELS_KS4_KS4_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UECDH_SHIFT)) & ELS_ELS_KS4_KS4_UECDH_MASK)

#define ELS_ELS_KS4_KS4_UAES_MASK                (0x100000U)
#define ELS_ELS_KS4_KS4_UAES_SHIFT               (20U)
#define ELS_ELS_KS4_KS4_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UAES_SHIFT)) & ELS_ELS_KS4_KS4_UAES_MASK)

#define ELS_ELS_KS4_KS4_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS4_KS4_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS4_KS4_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UHMAC_SHIFT)) & ELS_ELS_KS4_KS4_UHMAC_MASK)

#define ELS_ELS_KS4_KS4_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS4_KS4_UKWK_SHIFT               (22U)
#define ELS_ELS_KS4_KS4_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKWK_SHIFT)) & ELS_ELS_KS4_KS4_UKWK_MASK)

#define ELS_ELS_KS4_KS4_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS4_KS4_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS4_KS4_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKUOK_SHIFT)) & ELS_ELS_KS4_KS4_UKUOK_MASK)

#define ELS_ELS_KS4_KS4_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS4_KS4_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS4_KS4_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UTLSPMS_SHIFT)) & ELS_ELS_KS4_KS4_UTLSPMS_MASK)

#define ELS_ELS_KS4_KS4_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS4_KS4_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS4_KS4_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UTLSMS_SHIFT)) & ELS_ELS_KS4_KS4_UTLSMS_MASK)

#define ELS_ELS_KS4_KS4_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS4_KS4_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS4_KS4_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKGSRC_SHIFT)) & ELS_ELS_KS4_KS4_UKGSRC_MASK)

#define ELS_ELS_KS4_KS4_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS4_KS4_UHWO_SHIFT               (27U)
#define ELS_ELS_KS4_KS4_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UHWO_SHIFT)) & ELS_ELS_KS4_KS4_UHWO_MASK)

#define ELS_ELS_KS4_KS4_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS4_KS4_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS4_KS4_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UWRPOK_SHIFT)) & ELS_ELS_KS4_KS4_UWRPOK_MASK)

#define ELS_ELS_KS4_KS4_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS4_KS4_UDUK_SHIFT               (29U)
#define ELS_ELS_KS4_KS4_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UDUK_SHIFT)) & ELS_ELS_KS4_KS4_UDUK_MASK)

#define ELS_ELS_KS4_KS4_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS4_KS4_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS4_KS4_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UPPROT_SHIFT)) & ELS_ELS_KS4_KS4_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS5 - Status Register */
/*! @{ */

#define ELS_ELS_KS5_KS5_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS5_KS5_KSIZE_SHIFT              (0U)
/*! KS5_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS5_KS5_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_KSIZE_SHIFT)) & ELS_ELS_KS5_KS5_KSIZE_MASK)

#define ELS_ELS_KS5_KS5_KACT_MASK                (0x20U)
#define ELS_ELS_KS5_KS5_KACT_SHIFT               (5U)
#define ELS_ELS_KS5_KS5_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_KACT_SHIFT)) & ELS_ELS_KS5_KS5_KACT_MASK)

#define ELS_ELS_KS5_KS5_KBASE_MASK               (0x40U)
#define ELS_ELS_KS5_KS5_KBASE_SHIFT              (6U)
#define ELS_ELS_KS5_KS5_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_KBASE_SHIFT)) & ELS_ELS_KS5_KS5_KBASE_MASK)

#define ELS_ELS_KS5_KS5_FGP_MASK                 (0x80U)
#define ELS_ELS_KS5_KS5_FGP_SHIFT                (7U)
#define ELS_ELS_KS5_KS5_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_FGP_SHIFT)) & ELS_ELS_KS5_KS5_FGP_MASK)

#define ELS_ELS_KS5_KS5_FRTN_MASK                (0x100U)
#define ELS_ELS_KS5_KS5_FRTN_SHIFT               (8U)
#define ELS_ELS_KS5_KS5_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_FRTN_SHIFT)) & ELS_ELS_KS5_KS5_FRTN_MASK)

#define ELS_ELS_KS5_KS5_FHWO_MASK                (0x200U)
#define ELS_ELS_KS5_KS5_FHWO_SHIFT               (9U)
#define ELS_ELS_KS5_KS5_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_FHWO_SHIFT)) & ELS_ELS_KS5_KS5_FHWO_MASK)

#define ELS_ELS_KS5_KS5_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS5_KS5_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS5_KS5_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKPUK_SHIFT)) & ELS_ELS_KS5_KS5_UKPUK_MASK)

#define ELS_ELS_KS5_KS5_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS5_KS5_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS5_KS5_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UTECDH_SHIFT)) & ELS_ELS_KS5_KS5_UTECDH_MASK)

#define ELS_ELS_KS5_KS5_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS5_KS5_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS5_KS5_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UCMAC_SHIFT)) & ELS_ELS_KS5_KS5_UCMAC_MASK)

#define ELS_ELS_KS5_KS5_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS5_KS5_UKSK_SHIFT               (14U)
#define ELS_ELS_KS5_KS5_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKSK_SHIFT)) & ELS_ELS_KS5_KS5_UKSK_MASK)

#define ELS_ELS_KS5_KS5_URTF_MASK                (0x8000U)
#define ELS_ELS_KS5_KS5_URTF_SHIFT               (15U)
#define ELS_ELS_KS5_KS5_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_URTF_SHIFT)) & ELS_ELS_KS5_KS5_URTF_MASK)

#define ELS_ELS_KS5_KS5_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS5_KS5_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS5_KS5_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UCKDF_SHIFT)) & ELS_ELS_KS5_KS5_UCKDF_MASK)

#define ELS_ELS_KS5_KS5_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS5_KS5_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS5_KS5_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UHKDF_SHIFT)) & ELS_ELS_KS5_KS5_UHKDF_MASK)

#define ELS_ELS_KS5_KS5_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS5_KS5_UECSG_SHIFT              (18U)
#define ELS_ELS_KS5_KS5_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UECSG_SHIFT)) & ELS_ELS_KS5_KS5_UECSG_MASK)

#define ELS_ELS_KS5_KS5_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS5_KS5_UECDH_SHIFT              (19U)
#define ELS_ELS_KS5_KS5_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UECDH_SHIFT)) & ELS_ELS_KS5_KS5_UECDH_MASK)

#define ELS_ELS_KS5_KS5_UAES_MASK                (0x100000U)
#define ELS_ELS_KS5_KS5_UAES_SHIFT               (20U)
#define ELS_ELS_KS5_KS5_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UAES_SHIFT)) & ELS_ELS_KS5_KS5_UAES_MASK)

#define ELS_ELS_KS5_KS5_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS5_KS5_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS5_KS5_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UHMAC_SHIFT)) & ELS_ELS_KS5_KS5_UHMAC_MASK)

#define ELS_ELS_KS5_KS5_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS5_KS5_UKWK_SHIFT               (22U)
#define ELS_ELS_KS5_KS5_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKWK_SHIFT)) & ELS_ELS_KS5_KS5_UKWK_MASK)

#define ELS_ELS_KS5_KS5_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS5_KS5_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS5_KS5_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKUOK_SHIFT)) & ELS_ELS_KS5_KS5_UKUOK_MASK)

#define ELS_ELS_KS5_KS5_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS5_KS5_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS5_KS5_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UTLSPMS_SHIFT)) & ELS_ELS_KS5_KS5_UTLSPMS_MASK)

#define ELS_ELS_KS5_KS5_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS5_KS5_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS5_KS5_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UTLSMS_SHIFT)) & ELS_ELS_KS5_KS5_UTLSMS_MASK)

#define ELS_ELS_KS5_KS5_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS5_KS5_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS5_KS5_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKGSRC_SHIFT)) & ELS_ELS_KS5_KS5_UKGSRC_MASK)

#define ELS_ELS_KS5_KS5_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS5_KS5_UHWO_SHIFT               (27U)
#define ELS_ELS_KS5_KS5_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UHWO_SHIFT)) & ELS_ELS_KS5_KS5_UHWO_MASK)

#define ELS_ELS_KS5_KS5_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS5_KS5_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS5_KS5_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UWRPOK_SHIFT)) & ELS_ELS_KS5_KS5_UWRPOK_MASK)

#define ELS_ELS_KS5_KS5_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS5_KS5_UDUK_SHIFT               (29U)
#define ELS_ELS_KS5_KS5_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UDUK_SHIFT)) & ELS_ELS_KS5_KS5_UDUK_MASK)

#define ELS_ELS_KS5_KS5_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS5_KS5_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS5_KS5_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UPPROT_SHIFT)) & ELS_ELS_KS5_KS5_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS6 - Status Register */
/*! @{ */

#define ELS_ELS_KS6_KS6_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS6_KS6_KSIZE_SHIFT              (0U)
/*! KS6_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS6_KS6_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_KSIZE_SHIFT)) & ELS_ELS_KS6_KS6_KSIZE_MASK)

#define ELS_ELS_KS6_KS6_KACT_MASK                (0x20U)
#define ELS_ELS_KS6_KS6_KACT_SHIFT               (5U)
#define ELS_ELS_KS6_KS6_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_KACT_SHIFT)) & ELS_ELS_KS6_KS6_KACT_MASK)

#define ELS_ELS_KS6_KS6_KBASE_MASK               (0x40U)
#define ELS_ELS_KS6_KS6_KBASE_SHIFT              (6U)
#define ELS_ELS_KS6_KS6_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_KBASE_SHIFT)) & ELS_ELS_KS6_KS6_KBASE_MASK)

#define ELS_ELS_KS6_KS6_FGP_MASK                 (0x80U)
#define ELS_ELS_KS6_KS6_FGP_SHIFT                (7U)
#define ELS_ELS_KS6_KS6_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_FGP_SHIFT)) & ELS_ELS_KS6_KS6_FGP_MASK)

#define ELS_ELS_KS6_KS6_FRTN_MASK                (0x100U)
#define ELS_ELS_KS6_KS6_FRTN_SHIFT               (8U)
#define ELS_ELS_KS6_KS6_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_FRTN_SHIFT)) & ELS_ELS_KS6_KS6_FRTN_MASK)

#define ELS_ELS_KS6_KS6_FHWO_MASK                (0x200U)
#define ELS_ELS_KS6_KS6_FHWO_SHIFT               (9U)
#define ELS_ELS_KS6_KS6_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_FHWO_SHIFT)) & ELS_ELS_KS6_KS6_FHWO_MASK)

#define ELS_ELS_KS6_KS6_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS6_KS6_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS6_KS6_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKPUK_SHIFT)) & ELS_ELS_KS6_KS6_UKPUK_MASK)

#define ELS_ELS_KS6_KS6_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS6_KS6_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS6_KS6_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UTECDH_SHIFT)) & ELS_ELS_KS6_KS6_UTECDH_MASK)

#define ELS_ELS_KS6_KS6_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS6_KS6_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS6_KS6_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UCMAC_SHIFT)) & ELS_ELS_KS6_KS6_UCMAC_MASK)

#define ELS_ELS_KS6_KS6_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS6_KS6_UKSK_SHIFT               (14U)
#define ELS_ELS_KS6_KS6_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKSK_SHIFT)) & ELS_ELS_KS6_KS6_UKSK_MASK)

#define ELS_ELS_KS6_KS6_URTF_MASK                (0x8000U)
#define ELS_ELS_KS6_KS6_URTF_SHIFT               (15U)
#define ELS_ELS_KS6_KS6_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_URTF_SHIFT)) & ELS_ELS_KS6_KS6_URTF_MASK)

#define ELS_ELS_KS6_KS6_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS6_KS6_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS6_KS6_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UCKDF_SHIFT)) & ELS_ELS_KS6_KS6_UCKDF_MASK)

#define ELS_ELS_KS6_KS6_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS6_KS6_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS6_KS6_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UHKDF_SHIFT)) & ELS_ELS_KS6_KS6_UHKDF_MASK)

#define ELS_ELS_KS6_KS6_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS6_KS6_UECSG_SHIFT              (18U)
#define ELS_ELS_KS6_KS6_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UECSG_SHIFT)) & ELS_ELS_KS6_KS6_UECSG_MASK)

#define ELS_ELS_KS6_KS6_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS6_KS6_UECDH_SHIFT              (19U)
#define ELS_ELS_KS6_KS6_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UECDH_SHIFT)) & ELS_ELS_KS6_KS6_UECDH_MASK)

#define ELS_ELS_KS6_KS6_UAES_MASK                (0x100000U)
#define ELS_ELS_KS6_KS6_UAES_SHIFT               (20U)
#define ELS_ELS_KS6_KS6_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UAES_SHIFT)) & ELS_ELS_KS6_KS6_UAES_MASK)

#define ELS_ELS_KS6_KS6_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS6_KS6_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS6_KS6_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UHMAC_SHIFT)) & ELS_ELS_KS6_KS6_UHMAC_MASK)

#define ELS_ELS_KS6_KS6_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS6_KS6_UKWK_SHIFT               (22U)
#define ELS_ELS_KS6_KS6_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKWK_SHIFT)) & ELS_ELS_KS6_KS6_UKWK_MASK)

#define ELS_ELS_KS6_KS6_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS6_KS6_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS6_KS6_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKUOK_SHIFT)) & ELS_ELS_KS6_KS6_UKUOK_MASK)

#define ELS_ELS_KS6_KS6_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS6_KS6_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS6_KS6_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UTLSPMS_SHIFT)) & ELS_ELS_KS6_KS6_UTLSPMS_MASK)

#define ELS_ELS_KS6_KS6_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS6_KS6_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS6_KS6_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UTLSMS_SHIFT)) & ELS_ELS_KS6_KS6_UTLSMS_MASK)

#define ELS_ELS_KS6_KS6_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS6_KS6_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS6_KS6_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKGSRC_SHIFT)) & ELS_ELS_KS6_KS6_UKGSRC_MASK)

#define ELS_ELS_KS6_KS6_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS6_KS6_UHWO_SHIFT               (27U)
#define ELS_ELS_KS6_KS6_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UHWO_SHIFT)) & ELS_ELS_KS6_KS6_UHWO_MASK)

#define ELS_ELS_KS6_KS6_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS6_KS6_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS6_KS6_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UWRPOK_SHIFT)) & ELS_ELS_KS6_KS6_UWRPOK_MASK)

#define ELS_ELS_KS6_KS6_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS6_KS6_UDUK_SHIFT               (29U)
#define ELS_ELS_KS6_KS6_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UDUK_SHIFT)) & ELS_ELS_KS6_KS6_UDUK_MASK)

#define ELS_ELS_KS6_KS6_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS6_KS6_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS6_KS6_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UPPROT_SHIFT)) & ELS_ELS_KS6_KS6_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS7 - Status Register */
/*! @{ */

#define ELS_ELS_KS7_KS7_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS7_KS7_KSIZE_SHIFT              (0U)
/*! KS7_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS7_KS7_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_KSIZE_SHIFT)) & ELS_ELS_KS7_KS7_KSIZE_MASK)

#define ELS_ELS_KS7_KS7_KACT_MASK                (0x20U)
#define ELS_ELS_KS7_KS7_KACT_SHIFT               (5U)
#define ELS_ELS_KS7_KS7_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_KACT_SHIFT)) & ELS_ELS_KS7_KS7_KACT_MASK)

#define ELS_ELS_KS7_KS7_KBASE_MASK               (0x40U)
#define ELS_ELS_KS7_KS7_KBASE_SHIFT              (6U)
#define ELS_ELS_KS7_KS7_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_KBASE_SHIFT)) & ELS_ELS_KS7_KS7_KBASE_MASK)

#define ELS_ELS_KS7_KS7_FGP_MASK                 (0x80U)
#define ELS_ELS_KS7_KS7_FGP_SHIFT                (7U)
#define ELS_ELS_KS7_KS7_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_FGP_SHIFT)) & ELS_ELS_KS7_KS7_FGP_MASK)

#define ELS_ELS_KS7_KS7_FRTN_MASK                (0x100U)
#define ELS_ELS_KS7_KS7_FRTN_SHIFT               (8U)
#define ELS_ELS_KS7_KS7_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_FRTN_SHIFT)) & ELS_ELS_KS7_KS7_FRTN_MASK)

#define ELS_ELS_KS7_KS7_FHWO_MASK                (0x200U)
#define ELS_ELS_KS7_KS7_FHWO_SHIFT               (9U)
#define ELS_ELS_KS7_KS7_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_FHWO_SHIFT)) & ELS_ELS_KS7_KS7_FHWO_MASK)

#define ELS_ELS_KS7_KS7_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS7_KS7_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS7_KS7_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKPUK_SHIFT)) & ELS_ELS_KS7_KS7_UKPUK_MASK)

#define ELS_ELS_KS7_KS7_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS7_KS7_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS7_KS7_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UTECDH_SHIFT)) & ELS_ELS_KS7_KS7_UTECDH_MASK)

#define ELS_ELS_KS7_KS7_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS7_KS7_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS7_KS7_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UCMAC_SHIFT)) & ELS_ELS_KS7_KS7_UCMAC_MASK)

#define ELS_ELS_KS7_KS7_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS7_KS7_UKSK_SHIFT               (14U)
#define ELS_ELS_KS7_KS7_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKSK_SHIFT)) & ELS_ELS_KS7_KS7_UKSK_MASK)

#define ELS_ELS_KS7_KS7_URTF_MASK                (0x8000U)
#define ELS_ELS_KS7_KS7_URTF_SHIFT               (15U)
#define ELS_ELS_KS7_KS7_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_URTF_SHIFT)) & ELS_ELS_KS7_KS7_URTF_MASK)

#define ELS_ELS_KS7_KS7_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS7_KS7_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS7_KS7_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UCKDF_SHIFT)) & ELS_ELS_KS7_KS7_UCKDF_MASK)

#define ELS_ELS_KS7_KS7_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS7_KS7_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS7_KS7_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UHKDF_SHIFT)) & ELS_ELS_KS7_KS7_UHKDF_MASK)

#define ELS_ELS_KS7_KS7_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS7_KS7_UECSG_SHIFT              (18U)
#define ELS_ELS_KS7_KS7_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UECSG_SHIFT)) & ELS_ELS_KS7_KS7_UECSG_MASK)

#define ELS_ELS_KS7_KS7_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS7_KS7_UECDH_SHIFT              (19U)
#define ELS_ELS_KS7_KS7_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UECDH_SHIFT)) & ELS_ELS_KS7_KS7_UECDH_MASK)

#define ELS_ELS_KS7_KS7_UAES_MASK                (0x100000U)
#define ELS_ELS_KS7_KS7_UAES_SHIFT               (20U)
#define ELS_ELS_KS7_KS7_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UAES_SHIFT)) & ELS_ELS_KS7_KS7_UAES_MASK)

#define ELS_ELS_KS7_KS7_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS7_KS7_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS7_KS7_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UHMAC_SHIFT)) & ELS_ELS_KS7_KS7_UHMAC_MASK)

#define ELS_ELS_KS7_KS7_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS7_KS7_UKWK_SHIFT               (22U)
#define ELS_ELS_KS7_KS7_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKWK_SHIFT)) & ELS_ELS_KS7_KS7_UKWK_MASK)

#define ELS_ELS_KS7_KS7_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS7_KS7_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS7_KS7_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKUOK_SHIFT)) & ELS_ELS_KS7_KS7_UKUOK_MASK)

#define ELS_ELS_KS7_KS7_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS7_KS7_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS7_KS7_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UTLSPMS_SHIFT)) & ELS_ELS_KS7_KS7_UTLSPMS_MASK)

#define ELS_ELS_KS7_KS7_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS7_KS7_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS7_KS7_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UTLSMS_SHIFT)) & ELS_ELS_KS7_KS7_UTLSMS_MASK)

#define ELS_ELS_KS7_KS7_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS7_KS7_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS7_KS7_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKGSRC_SHIFT)) & ELS_ELS_KS7_KS7_UKGSRC_MASK)

#define ELS_ELS_KS7_KS7_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS7_KS7_UHWO_SHIFT               (27U)
#define ELS_ELS_KS7_KS7_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UHWO_SHIFT)) & ELS_ELS_KS7_KS7_UHWO_MASK)

#define ELS_ELS_KS7_KS7_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS7_KS7_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS7_KS7_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UWRPOK_SHIFT)) & ELS_ELS_KS7_KS7_UWRPOK_MASK)

#define ELS_ELS_KS7_KS7_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS7_KS7_UDUK_SHIFT               (29U)
#define ELS_ELS_KS7_KS7_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UDUK_SHIFT)) & ELS_ELS_KS7_KS7_UDUK_MASK)

#define ELS_ELS_KS7_KS7_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS7_KS7_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS7_KS7_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UPPROT_SHIFT)) & ELS_ELS_KS7_KS7_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS8 - Status Register */
/*! @{ */

#define ELS_ELS_KS8_KS8_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS8_KS8_KSIZE_SHIFT              (0U)
/*! KS8_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS8_KS8_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_KSIZE_SHIFT)) & ELS_ELS_KS8_KS8_KSIZE_MASK)

#define ELS_ELS_KS8_KS8_KACT_MASK                (0x20U)
#define ELS_ELS_KS8_KS8_KACT_SHIFT               (5U)
#define ELS_ELS_KS8_KS8_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_KACT_SHIFT)) & ELS_ELS_KS8_KS8_KACT_MASK)

#define ELS_ELS_KS8_KS8_KBASE_MASK               (0x40U)
#define ELS_ELS_KS8_KS8_KBASE_SHIFT              (6U)
#define ELS_ELS_KS8_KS8_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_KBASE_SHIFT)) & ELS_ELS_KS8_KS8_KBASE_MASK)

#define ELS_ELS_KS8_KS8_FGP_MASK                 (0x80U)
#define ELS_ELS_KS8_KS8_FGP_SHIFT                (7U)
#define ELS_ELS_KS8_KS8_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_FGP_SHIFT)) & ELS_ELS_KS8_KS8_FGP_MASK)

#define ELS_ELS_KS8_KS8_FRTN_MASK                (0x100U)
#define ELS_ELS_KS8_KS8_FRTN_SHIFT               (8U)
#define ELS_ELS_KS8_KS8_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_FRTN_SHIFT)) & ELS_ELS_KS8_KS8_FRTN_MASK)

#define ELS_ELS_KS8_KS8_FHWO_MASK                (0x200U)
#define ELS_ELS_KS8_KS8_FHWO_SHIFT               (9U)
#define ELS_ELS_KS8_KS8_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_FHWO_SHIFT)) & ELS_ELS_KS8_KS8_FHWO_MASK)

#define ELS_ELS_KS8_KS8_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS8_KS8_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS8_KS8_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKPUK_SHIFT)) & ELS_ELS_KS8_KS8_UKPUK_MASK)

#define ELS_ELS_KS8_KS8_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS8_KS8_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS8_KS8_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UTECDH_SHIFT)) & ELS_ELS_KS8_KS8_UTECDH_MASK)

#define ELS_ELS_KS8_KS8_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS8_KS8_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS8_KS8_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UCMAC_SHIFT)) & ELS_ELS_KS8_KS8_UCMAC_MASK)

#define ELS_ELS_KS8_KS8_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS8_KS8_UKSK_SHIFT               (14U)
#define ELS_ELS_KS8_KS8_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKSK_SHIFT)) & ELS_ELS_KS8_KS8_UKSK_MASK)

#define ELS_ELS_KS8_KS8_URTF_MASK                (0x8000U)
#define ELS_ELS_KS8_KS8_URTF_SHIFT               (15U)
#define ELS_ELS_KS8_KS8_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_URTF_SHIFT)) & ELS_ELS_KS8_KS8_URTF_MASK)

#define ELS_ELS_KS8_KS8_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS8_KS8_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS8_KS8_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UCKDF_SHIFT)) & ELS_ELS_KS8_KS8_UCKDF_MASK)

#define ELS_ELS_KS8_KS8_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS8_KS8_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS8_KS8_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UHKDF_SHIFT)) & ELS_ELS_KS8_KS8_UHKDF_MASK)

#define ELS_ELS_KS8_KS8_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS8_KS8_UECSG_SHIFT              (18U)
#define ELS_ELS_KS8_KS8_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UECSG_SHIFT)) & ELS_ELS_KS8_KS8_UECSG_MASK)

#define ELS_ELS_KS8_KS8_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS8_KS8_UECDH_SHIFT              (19U)
#define ELS_ELS_KS8_KS8_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UECDH_SHIFT)) & ELS_ELS_KS8_KS8_UECDH_MASK)

#define ELS_ELS_KS8_KS8_UAES_MASK                (0x100000U)
#define ELS_ELS_KS8_KS8_UAES_SHIFT               (20U)
#define ELS_ELS_KS8_KS8_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UAES_SHIFT)) & ELS_ELS_KS8_KS8_UAES_MASK)

#define ELS_ELS_KS8_KS8_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS8_KS8_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS8_KS8_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UHMAC_SHIFT)) & ELS_ELS_KS8_KS8_UHMAC_MASK)

#define ELS_ELS_KS8_KS8_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS8_KS8_UKWK_SHIFT               (22U)
#define ELS_ELS_KS8_KS8_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKWK_SHIFT)) & ELS_ELS_KS8_KS8_UKWK_MASK)

#define ELS_ELS_KS8_KS8_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS8_KS8_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS8_KS8_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKUOK_SHIFT)) & ELS_ELS_KS8_KS8_UKUOK_MASK)

#define ELS_ELS_KS8_KS8_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS8_KS8_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS8_KS8_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UTLSPMS_SHIFT)) & ELS_ELS_KS8_KS8_UTLSPMS_MASK)

#define ELS_ELS_KS8_KS8_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS8_KS8_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS8_KS8_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UTLSMS_SHIFT)) & ELS_ELS_KS8_KS8_UTLSMS_MASK)

#define ELS_ELS_KS8_KS8_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS8_KS8_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS8_KS8_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKGSRC_SHIFT)) & ELS_ELS_KS8_KS8_UKGSRC_MASK)

#define ELS_ELS_KS8_KS8_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS8_KS8_UHWO_SHIFT               (27U)
#define ELS_ELS_KS8_KS8_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UHWO_SHIFT)) & ELS_ELS_KS8_KS8_UHWO_MASK)

#define ELS_ELS_KS8_KS8_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS8_KS8_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS8_KS8_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UWRPOK_SHIFT)) & ELS_ELS_KS8_KS8_UWRPOK_MASK)

#define ELS_ELS_KS8_KS8_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS8_KS8_UDUK_SHIFT               (29U)
#define ELS_ELS_KS8_KS8_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UDUK_SHIFT)) & ELS_ELS_KS8_KS8_UDUK_MASK)

#define ELS_ELS_KS8_KS8_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS8_KS8_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS8_KS8_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UPPROT_SHIFT)) & ELS_ELS_KS8_KS8_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS9 - Status Register */
/*! @{ */

#define ELS_ELS_KS9_KS9_KSIZE_MASK               (0x3U)
#define ELS_ELS_KS9_KS9_KSIZE_SHIFT              (0U)
/*! KS9_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS9_KS9_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_KSIZE_SHIFT)) & ELS_ELS_KS9_KS9_KSIZE_MASK)

#define ELS_ELS_KS9_KS9_KACT_MASK                (0x20U)
#define ELS_ELS_KS9_KS9_KACT_SHIFT               (5U)
#define ELS_ELS_KS9_KS9_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_KACT_SHIFT)) & ELS_ELS_KS9_KS9_KACT_MASK)

#define ELS_ELS_KS9_KS9_KBASE_MASK               (0x40U)
#define ELS_ELS_KS9_KS9_KBASE_SHIFT              (6U)
#define ELS_ELS_KS9_KS9_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_KBASE_SHIFT)) & ELS_ELS_KS9_KS9_KBASE_MASK)

#define ELS_ELS_KS9_KS9_FGP_MASK                 (0x80U)
#define ELS_ELS_KS9_KS9_FGP_SHIFT                (7U)
#define ELS_ELS_KS9_KS9_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_FGP_SHIFT)) & ELS_ELS_KS9_KS9_FGP_MASK)

#define ELS_ELS_KS9_KS9_FRTN_MASK                (0x100U)
#define ELS_ELS_KS9_KS9_FRTN_SHIFT               (8U)
#define ELS_ELS_KS9_KS9_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_FRTN_SHIFT)) & ELS_ELS_KS9_KS9_FRTN_MASK)

#define ELS_ELS_KS9_KS9_FHWO_MASK                (0x200U)
#define ELS_ELS_KS9_KS9_FHWO_SHIFT               (9U)
#define ELS_ELS_KS9_KS9_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_FHWO_SHIFT)) & ELS_ELS_KS9_KS9_FHWO_MASK)

#define ELS_ELS_KS9_KS9_UKPUK_MASK               (0x800U)
#define ELS_ELS_KS9_KS9_UKPUK_SHIFT              (11U)
#define ELS_ELS_KS9_KS9_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKPUK_SHIFT)) & ELS_ELS_KS9_KS9_UKPUK_MASK)

#define ELS_ELS_KS9_KS9_UTECDH_MASK              (0x1000U)
#define ELS_ELS_KS9_KS9_UTECDH_SHIFT             (12U)
#define ELS_ELS_KS9_KS9_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UTECDH_SHIFT)) & ELS_ELS_KS9_KS9_UTECDH_MASK)

#define ELS_ELS_KS9_KS9_UCMAC_MASK               (0x2000U)
#define ELS_ELS_KS9_KS9_UCMAC_SHIFT              (13U)
#define ELS_ELS_KS9_KS9_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UCMAC_SHIFT)) & ELS_ELS_KS9_KS9_UCMAC_MASK)

#define ELS_ELS_KS9_KS9_UKSK_MASK                (0x4000U)
#define ELS_ELS_KS9_KS9_UKSK_SHIFT               (14U)
#define ELS_ELS_KS9_KS9_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKSK_SHIFT)) & ELS_ELS_KS9_KS9_UKSK_MASK)

#define ELS_ELS_KS9_KS9_URTF_MASK                (0x8000U)
#define ELS_ELS_KS9_KS9_URTF_SHIFT               (15U)
#define ELS_ELS_KS9_KS9_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_URTF_SHIFT)) & ELS_ELS_KS9_KS9_URTF_MASK)

#define ELS_ELS_KS9_KS9_UCKDF_MASK               (0x10000U)
#define ELS_ELS_KS9_KS9_UCKDF_SHIFT              (16U)
#define ELS_ELS_KS9_KS9_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UCKDF_SHIFT)) & ELS_ELS_KS9_KS9_UCKDF_MASK)

#define ELS_ELS_KS9_KS9_UHKDF_MASK               (0x20000U)
#define ELS_ELS_KS9_KS9_UHKDF_SHIFT              (17U)
#define ELS_ELS_KS9_KS9_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UHKDF_SHIFT)) & ELS_ELS_KS9_KS9_UHKDF_MASK)

#define ELS_ELS_KS9_KS9_UECSG_MASK               (0x40000U)
#define ELS_ELS_KS9_KS9_UECSG_SHIFT              (18U)
#define ELS_ELS_KS9_KS9_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UECSG_SHIFT)) & ELS_ELS_KS9_KS9_UECSG_MASK)

#define ELS_ELS_KS9_KS9_UECDH_MASK               (0x80000U)
#define ELS_ELS_KS9_KS9_UECDH_SHIFT              (19U)
#define ELS_ELS_KS9_KS9_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UECDH_SHIFT)) & ELS_ELS_KS9_KS9_UECDH_MASK)

#define ELS_ELS_KS9_KS9_UAES_MASK                (0x100000U)
#define ELS_ELS_KS9_KS9_UAES_SHIFT               (20U)
#define ELS_ELS_KS9_KS9_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UAES_SHIFT)) & ELS_ELS_KS9_KS9_UAES_MASK)

#define ELS_ELS_KS9_KS9_UHMAC_MASK               (0x200000U)
#define ELS_ELS_KS9_KS9_UHMAC_SHIFT              (21U)
#define ELS_ELS_KS9_KS9_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UHMAC_SHIFT)) & ELS_ELS_KS9_KS9_UHMAC_MASK)

#define ELS_ELS_KS9_KS9_UKWK_MASK                (0x400000U)
#define ELS_ELS_KS9_KS9_UKWK_SHIFT               (22U)
#define ELS_ELS_KS9_KS9_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKWK_SHIFT)) & ELS_ELS_KS9_KS9_UKWK_MASK)

#define ELS_ELS_KS9_KS9_UKUOK_MASK               (0x800000U)
#define ELS_ELS_KS9_KS9_UKUOK_SHIFT              (23U)
#define ELS_ELS_KS9_KS9_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKUOK_SHIFT)) & ELS_ELS_KS9_KS9_UKUOK_MASK)

#define ELS_ELS_KS9_KS9_UTLSPMS_MASK             (0x1000000U)
#define ELS_ELS_KS9_KS9_UTLSPMS_SHIFT            (24U)
#define ELS_ELS_KS9_KS9_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UTLSPMS_SHIFT)) & ELS_ELS_KS9_KS9_UTLSPMS_MASK)

#define ELS_ELS_KS9_KS9_UTLSMS_MASK              (0x2000000U)
#define ELS_ELS_KS9_KS9_UTLSMS_SHIFT             (25U)
#define ELS_ELS_KS9_KS9_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UTLSMS_SHIFT)) & ELS_ELS_KS9_KS9_UTLSMS_MASK)

#define ELS_ELS_KS9_KS9_UKGSRC_MASK              (0x4000000U)
#define ELS_ELS_KS9_KS9_UKGSRC_SHIFT             (26U)
#define ELS_ELS_KS9_KS9_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKGSRC_SHIFT)) & ELS_ELS_KS9_KS9_UKGSRC_MASK)

#define ELS_ELS_KS9_KS9_UHWO_MASK                (0x8000000U)
#define ELS_ELS_KS9_KS9_UHWO_SHIFT               (27U)
#define ELS_ELS_KS9_KS9_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UHWO_SHIFT)) & ELS_ELS_KS9_KS9_UHWO_MASK)

#define ELS_ELS_KS9_KS9_UWRPOK_MASK              (0x10000000U)
#define ELS_ELS_KS9_KS9_UWRPOK_SHIFT             (28U)
#define ELS_ELS_KS9_KS9_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UWRPOK_SHIFT)) & ELS_ELS_KS9_KS9_UWRPOK_MASK)

#define ELS_ELS_KS9_KS9_UDUK_MASK                (0x20000000U)
#define ELS_ELS_KS9_KS9_UDUK_SHIFT               (29U)
#define ELS_ELS_KS9_KS9_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UDUK_SHIFT)) & ELS_ELS_KS9_KS9_UDUK_MASK)

#define ELS_ELS_KS9_KS9_UPPROT_MASK              (0xC0000000U)
#define ELS_ELS_KS9_KS9_UPPROT_SHIFT             (30U)
#define ELS_ELS_KS9_KS9_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UPPROT_SHIFT)) & ELS_ELS_KS9_KS9_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS10 - Status Register */
/*! @{ */

#define ELS_ELS_KS10_KS10_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS10_KS10_KSIZE_SHIFT            (0U)
/*! KS10_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS10_KS10_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_KSIZE_SHIFT)) & ELS_ELS_KS10_KS10_KSIZE_MASK)

#define ELS_ELS_KS10_KS10_KACT_MASK              (0x20U)
#define ELS_ELS_KS10_KS10_KACT_SHIFT             (5U)
#define ELS_ELS_KS10_KS10_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_KACT_SHIFT)) & ELS_ELS_KS10_KS10_KACT_MASK)

#define ELS_ELS_KS10_KS10_KBASE_MASK             (0x40U)
#define ELS_ELS_KS10_KS10_KBASE_SHIFT            (6U)
#define ELS_ELS_KS10_KS10_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_KBASE_SHIFT)) & ELS_ELS_KS10_KS10_KBASE_MASK)

#define ELS_ELS_KS10_KS10_FGP_MASK               (0x80U)
#define ELS_ELS_KS10_KS10_FGP_SHIFT              (7U)
#define ELS_ELS_KS10_KS10_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_FGP_SHIFT)) & ELS_ELS_KS10_KS10_FGP_MASK)

#define ELS_ELS_KS10_KS10_FRTN_MASK              (0x100U)
#define ELS_ELS_KS10_KS10_FRTN_SHIFT             (8U)
#define ELS_ELS_KS10_KS10_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_FRTN_SHIFT)) & ELS_ELS_KS10_KS10_FRTN_MASK)

#define ELS_ELS_KS10_KS10_FHWO_MASK              (0x200U)
#define ELS_ELS_KS10_KS10_FHWO_SHIFT             (9U)
#define ELS_ELS_KS10_KS10_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_FHWO_SHIFT)) & ELS_ELS_KS10_KS10_FHWO_MASK)

#define ELS_ELS_KS10_KS10_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS10_KS10_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS10_KS10_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKPUK_SHIFT)) & ELS_ELS_KS10_KS10_UKPUK_MASK)

#define ELS_ELS_KS10_KS10_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS10_KS10_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS10_KS10_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UTECDH_SHIFT)) & ELS_ELS_KS10_KS10_UTECDH_MASK)

#define ELS_ELS_KS10_KS10_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS10_KS10_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS10_KS10_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UCMAC_SHIFT)) & ELS_ELS_KS10_KS10_UCMAC_MASK)

#define ELS_ELS_KS10_KS10_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS10_KS10_UKSK_SHIFT             (14U)
#define ELS_ELS_KS10_KS10_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKSK_SHIFT)) & ELS_ELS_KS10_KS10_UKSK_MASK)

#define ELS_ELS_KS10_KS10_URTF_MASK              (0x8000U)
#define ELS_ELS_KS10_KS10_URTF_SHIFT             (15U)
#define ELS_ELS_KS10_KS10_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_URTF_SHIFT)) & ELS_ELS_KS10_KS10_URTF_MASK)

#define ELS_ELS_KS10_KS10_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS10_KS10_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS10_KS10_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UCKDF_SHIFT)) & ELS_ELS_KS10_KS10_UCKDF_MASK)

#define ELS_ELS_KS10_KS10_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS10_KS10_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS10_KS10_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UHKDF_SHIFT)) & ELS_ELS_KS10_KS10_UHKDF_MASK)

#define ELS_ELS_KS10_KS10_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS10_KS10_UECSG_SHIFT            (18U)
#define ELS_ELS_KS10_KS10_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UECSG_SHIFT)) & ELS_ELS_KS10_KS10_UECSG_MASK)

#define ELS_ELS_KS10_KS10_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS10_KS10_UECDH_SHIFT            (19U)
#define ELS_ELS_KS10_KS10_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UECDH_SHIFT)) & ELS_ELS_KS10_KS10_UECDH_MASK)

#define ELS_ELS_KS10_KS10_UAES_MASK              (0x100000U)
#define ELS_ELS_KS10_KS10_UAES_SHIFT             (20U)
#define ELS_ELS_KS10_KS10_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UAES_SHIFT)) & ELS_ELS_KS10_KS10_UAES_MASK)

#define ELS_ELS_KS10_KS10_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS10_KS10_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS10_KS10_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UHMAC_SHIFT)) & ELS_ELS_KS10_KS10_UHMAC_MASK)

#define ELS_ELS_KS10_KS10_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS10_KS10_UKWK_SHIFT             (22U)
#define ELS_ELS_KS10_KS10_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKWK_SHIFT)) & ELS_ELS_KS10_KS10_UKWK_MASK)

#define ELS_ELS_KS10_KS10_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS10_KS10_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS10_KS10_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKUOK_SHIFT)) & ELS_ELS_KS10_KS10_UKUOK_MASK)

#define ELS_ELS_KS10_KS10_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS10_KS10_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS10_KS10_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UTLSPMS_SHIFT)) & ELS_ELS_KS10_KS10_UTLSPMS_MASK)

#define ELS_ELS_KS10_KS10_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS10_KS10_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS10_KS10_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UTLSMS_SHIFT)) & ELS_ELS_KS10_KS10_UTLSMS_MASK)

#define ELS_ELS_KS10_KS10_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS10_KS10_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS10_KS10_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKGSRC_SHIFT)) & ELS_ELS_KS10_KS10_UKGSRC_MASK)

#define ELS_ELS_KS10_KS10_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS10_KS10_UHWO_SHIFT             (27U)
#define ELS_ELS_KS10_KS10_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UHWO_SHIFT)) & ELS_ELS_KS10_KS10_UHWO_MASK)

#define ELS_ELS_KS10_KS10_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS10_KS10_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS10_KS10_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UWRPOK_SHIFT)) & ELS_ELS_KS10_KS10_UWRPOK_MASK)

#define ELS_ELS_KS10_KS10_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS10_KS10_UDUK_SHIFT             (29U)
#define ELS_ELS_KS10_KS10_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UDUK_SHIFT)) & ELS_ELS_KS10_KS10_UDUK_MASK)

#define ELS_ELS_KS10_KS10_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS10_KS10_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS10_KS10_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UPPROT_SHIFT)) & ELS_ELS_KS10_KS10_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS11 - Status Register */
/*! @{ */

#define ELS_ELS_KS11_KS11_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS11_KS11_KSIZE_SHIFT            (0U)
/*! KS11_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS11_KS11_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_KSIZE_SHIFT)) & ELS_ELS_KS11_KS11_KSIZE_MASK)

#define ELS_ELS_KS11_KS11_KACT_MASK              (0x20U)
#define ELS_ELS_KS11_KS11_KACT_SHIFT             (5U)
#define ELS_ELS_KS11_KS11_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_KACT_SHIFT)) & ELS_ELS_KS11_KS11_KACT_MASK)

#define ELS_ELS_KS11_KS11_KBASE_MASK             (0x40U)
#define ELS_ELS_KS11_KS11_KBASE_SHIFT            (6U)
#define ELS_ELS_KS11_KS11_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_KBASE_SHIFT)) & ELS_ELS_KS11_KS11_KBASE_MASK)

#define ELS_ELS_KS11_KS11_FGP_MASK               (0x80U)
#define ELS_ELS_KS11_KS11_FGP_SHIFT              (7U)
#define ELS_ELS_KS11_KS11_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_FGP_SHIFT)) & ELS_ELS_KS11_KS11_FGP_MASK)

#define ELS_ELS_KS11_KS11_FRTN_MASK              (0x100U)
#define ELS_ELS_KS11_KS11_FRTN_SHIFT             (8U)
#define ELS_ELS_KS11_KS11_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_FRTN_SHIFT)) & ELS_ELS_KS11_KS11_FRTN_MASK)

#define ELS_ELS_KS11_KS11_FHWO_MASK              (0x200U)
#define ELS_ELS_KS11_KS11_FHWO_SHIFT             (9U)
#define ELS_ELS_KS11_KS11_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_FHWO_SHIFT)) & ELS_ELS_KS11_KS11_FHWO_MASK)

#define ELS_ELS_KS11_KS11_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS11_KS11_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS11_KS11_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKPUK_SHIFT)) & ELS_ELS_KS11_KS11_UKPUK_MASK)

#define ELS_ELS_KS11_KS11_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS11_KS11_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS11_KS11_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UTECDH_SHIFT)) & ELS_ELS_KS11_KS11_UTECDH_MASK)

#define ELS_ELS_KS11_KS11_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS11_KS11_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS11_KS11_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UCMAC_SHIFT)) & ELS_ELS_KS11_KS11_UCMAC_MASK)

#define ELS_ELS_KS11_KS11_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS11_KS11_UKSK_SHIFT             (14U)
#define ELS_ELS_KS11_KS11_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKSK_SHIFT)) & ELS_ELS_KS11_KS11_UKSK_MASK)

#define ELS_ELS_KS11_KS11_URTF_MASK              (0x8000U)
#define ELS_ELS_KS11_KS11_URTF_SHIFT             (15U)
#define ELS_ELS_KS11_KS11_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_URTF_SHIFT)) & ELS_ELS_KS11_KS11_URTF_MASK)

#define ELS_ELS_KS11_KS11_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS11_KS11_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS11_KS11_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UCKDF_SHIFT)) & ELS_ELS_KS11_KS11_UCKDF_MASK)

#define ELS_ELS_KS11_KS11_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS11_KS11_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS11_KS11_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UHKDF_SHIFT)) & ELS_ELS_KS11_KS11_UHKDF_MASK)

#define ELS_ELS_KS11_KS11_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS11_KS11_UECSG_SHIFT            (18U)
#define ELS_ELS_KS11_KS11_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UECSG_SHIFT)) & ELS_ELS_KS11_KS11_UECSG_MASK)

#define ELS_ELS_KS11_KS11_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS11_KS11_UECDH_SHIFT            (19U)
#define ELS_ELS_KS11_KS11_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UECDH_SHIFT)) & ELS_ELS_KS11_KS11_UECDH_MASK)

#define ELS_ELS_KS11_KS11_UAES_MASK              (0x100000U)
#define ELS_ELS_KS11_KS11_UAES_SHIFT             (20U)
#define ELS_ELS_KS11_KS11_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UAES_SHIFT)) & ELS_ELS_KS11_KS11_UAES_MASK)

#define ELS_ELS_KS11_KS11_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS11_KS11_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS11_KS11_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UHMAC_SHIFT)) & ELS_ELS_KS11_KS11_UHMAC_MASK)

#define ELS_ELS_KS11_KS11_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS11_KS11_UKWK_SHIFT             (22U)
#define ELS_ELS_KS11_KS11_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKWK_SHIFT)) & ELS_ELS_KS11_KS11_UKWK_MASK)

#define ELS_ELS_KS11_KS11_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS11_KS11_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS11_KS11_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKUOK_SHIFT)) & ELS_ELS_KS11_KS11_UKUOK_MASK)

#define ELS_ELS_KS11_KS11_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS11_KS11_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS11_KS11_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UTLSPMS_SHIFT)) & ELS_ELS_KS11_KS11_UTLSPMS_MASK)

#define ELS_ELS_KS11_KS11_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS11_KS11_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS11_KS11_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UTLSMS_SHIFT)) & ELS_ELS_KS11_KS11_UTLSMS_MASK)

#define ELS_ELS_KS11_KS11_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS11_KS11_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS11_KS11_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKGSRC_SHIFT)) & ELS_ELS_KS11_KS11_UKGSRC_MASK)

#define ELS_ELS_KS11_KS11_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS11_KS11_UHWO_SHIFT             (27U)
#define ELS_ELS_KS11_KS11_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UHWO_SHIFT)) & ELS_ELS_KS11_KS11_UHWO_MASK)

#define ELS_ELS_KS11_KS11_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS11_KS11_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS11_KS11_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UWRPOK_SHIFT)) & ELS_ELS_KS11_KS11_UWRPOK_MASK)

#define ELS_ELS_KS11_KS11_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS11_KS11_UDUK_SHIFT             (29U)
#define ELS_ELS_KS11_KS11_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UDUK_SHIFT)) & ELS_ELS_KS11_KS11_UDUK_MASK)

#define ELS_ELS_KS11_KS11_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS11_KS11_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS11_KS11_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UPPROT_SHIFT)) & ELS_ELS_KS11_KS11_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS12 - Status Register */
/*! @{ */

#define ELS_ELS_KS12_KS12_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS12_KS12_KSIZE_SHIFT            (0U)
/*! KS12_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS12_KS12_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_KSIZE_SHIFT)) & ELS_ELS_KS12_KS12_KSIZE_MASK)

#define ELS_ELS_KS12_KS12_KACT_MASK              (0x20U)
#define ELS_ELS_KS12_KS12_KACT_SHIFT             (5U)
#define ELS_ELS_KS12_KS12_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_KACT_SHIFT)) & ELS_ELS_KS12_KS12_KACT_MASK)

#define ELS_ELS_KS12_KS12_KBASE_MASK             (0x40U)
#define ELS_ELS_KS12_KS12_KBASE_SHIFT            (6U)
#define ELS_ELS_KS12_KS12_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_KBASE_SHIFT)) & ELS_ELS_KS12_KS12_KBASE_MASK)

#define ELS_ELS_KS12_KS12_FGP_MASK               (0x80U)
#define ELS_ELS_KS12_KS12_FGP_SHIFT              (7U)
#define ELS_ELS_KS12_KS12_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_FGP_SHIFT)) & ELS_ELS_KS12_KS12_FGP_MASK)

#define ELS_ELS_KS12_KS12_FRTN_MASK              (0x100U)
#define ELS_ELS_KS12_KS12_FRTN_SHIFT             (8U)
#define ELS_ELS_KS12_KS12_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_FRTN_SHIFT)) & ELS_ELS_KS12_KS12_FRTN_MASK)

#define ELS_ELS_KS12_KS12_FHWO_MASK              (0x200U)
#define ELS_ELS_KS12_KS12_FHWO_SHIFT             (9U)
#define ELS_ELS_KS12_KS12_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_FHWO_SHIFT)) & ELS_ELS_KS12_KS12_FHWO_MASK)

#define ELS_ELS_KS12_KS12_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS12_KS12_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS12_KS12_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKPUK_SHIFT)) & ELS_ELS_KS12_KS12_UKPUK_MASK)

#define ELS_ELS_KS12_KS12_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS12_KS12_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS12_KS12_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UTECDH_SHIFT)) & ELS_ELS_KS12_KS12_UTECDH_MASK)

#define ELS_ELS_KS12_KS12_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS12_KS12_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS12_KS12_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UCMAC_SHIFT)) & ELS_ELS_KS12_KS12_UCMAC_MASK)

#define ELS_ELS_KS12_KS12_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS12_KS12_UKSK_SHIFT             (14U)
#define ELS_ELS_KS12_KS12_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKSK_SHIFT)) & ELS_ELS_KS12_KS12_UKSK_MASK)

#define ELS_ELS_KS12_KS12_URTF_MASK              (0x8000U)
#define ELS_ELS_KS12_KS12_URTF_SHIFT             (15U)
#define ELS_ELS_KS12_KS12_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_URTF_SHIFT)) & ELS_ELS_KS12_KS12_URTF_MASK)

#define ELS_ELS_KS12_KS12_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS12_KS12_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS12_KS12_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UCKDF_SHIFT)) & ELS_ELS_KS12_KS12_UCKDF_MASK)

#define ELS_ELS_KS12_KS12_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS12_KS12_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS12_KS12_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UHKDF_SHIFT)) & ELS_ELS_KS12_KS12_UHKDF_MASK)

#define ELS_ELS_KS12_KS12_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS12_KS12_UECSG_SHIFT            (18U)
#define ELS_ELS_KS12_KS12_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UECSG_SHIFT)) & ELS_ELS_KS12_KS12_UECSG_MASK)

#define ELS_ELS_KS12_KS12_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS12_KS12_UECDH_SHIFT            (19U)
#define ELS_ELS_KS12_KS12_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UECDH_SHIFT)) & ELS_ELS_KS12_KS12_UECDH_MASK)

#define ELS_ELS_KS12_KS12_UAES_MASK              (0x100000U)
#define ELS_ELS_KS12_KS12_UAES_SHIFT             (20U)
#define ELS_ELS_KS12_KS12_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UAES_SHIFT)) & ELS_ELS_KS12_KS12_UAES_MASK)

#define ELS_ELS_KS12_KS12_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS12_KS12_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS12_KS12_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UHMAC_SHIFT)) & ELS_ELS_KS12_KS12_UHMAC_MASK)

#define ELS_ELS_KS12_KS12_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS12_KS12_UKWK_SHIFT             (22U)
#define ELS_ELS_KS12_KS12_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKWK_SHIFT)) & ELS_ELS_KS12_KS12_UKWK_MASK)

#define ELS_ELS_KS12_KS12_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS12_KS12_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS12_KS12_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKUOK_SHIFT)) & ELS_ELS_KS12_KS12_UKUOK_MASK)

#define ELS_ELS_KS12_KS12_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS12_KS12_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS12_KS12_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UTLSPMS_SHIFT)) & ELS_ELS_KS12_KS12_UTLSPMS_MASK)

#define ELS_ELS_KS12_KS12_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS12_KS12_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS12_KS12_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UTLSMS_SHIFT)) & ELS_ELS_KS12_KS12_UTLSMS_MASK)

#define ELS_ELS_KS12_KS12_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS12_KS12_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS12_KS12_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKGSRC_SHIFT)) & ELS_ELS_KS12_KS12_UKGSRC_MASK)

#define ELS_ELS_KS12_KS12_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS12_KS12_UHWO_SHIFT             (27U)
#define ELS_ELS_KS12_KS12_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UHWO_SHIFT)) & ELS_ELS_KS12_KS12_UHWO_MASK)

#define ELS_ELS_KS12_KS12_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS12_KS12_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS12_KS12_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UWRPOK_SHIFT)) & ELS_ELS_KS12_KS12_UWRPOK_MASK)

#define ELS_ELS_KS12_KS12_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS12_KS12_UDUK_SHIFT             (29U)
#define ELS_ELS_KS12_KS12_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UDUK_SHIFT)) & ELS_ELS_KS12_KS12_UDUK_MASK)

#define ELS_ELS_KS12_KS12_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS12_KS12_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS12_KS12_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UPPROT_SHIFT)) & ELS_ELS_KS12_KS12_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS13 - Status Register */
/*! @{ */

#define ELS_ELS_KS13_KS13_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS13_KS13_KSIZE_SHIFT            (0U)
/*! KS13_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS13_KS13_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_KSIZE_SHIFT)) & ELS_ELS_KS13_KS13_KSIZE_MASK)

#define ELS_ELS_KS13_KS13_KACT_MASK              (0x20U)
#define ELS_ELS_KS13_KS13_KACT_SHIFT             (5U)
#define ELS_ELS_KS13_KS13_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_KACT_SHIFT)) & ELS_ELS_KS13_KS13_KACT_MASK)

#define ELS_ELS_KS13_KS13_KBASE_MASK             (0x40U)
#define ELS_ELS_KS13_KS13_KBASE_SHIFT            (6U)
#define ELS_ELS_KS13_KS13_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_KBASE_SHIFT)) & ELS_ELS_KS13_KS13_KBASE_MASK)

#define ELS_ELS_KS13_KS13_FGP_MASK               (0x80U)
#define ELS_ELS_KS13_KS13_FGP_SHIFT              (7U)
#define ELS_ELS_KS13_KS13_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_FGP_SHIFT)) & ELS_ELS_KS13_KS13_FGP_MASK)

#define ELS_ELS_KS13_KS13_FRTN_MASK              (0x100U)
#define ELS_ELS_KS13_KS13_FRTN_SHIFT             (8U)
#define ELS_ELS_KS13_KS13_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_FRTN_SHIFT)) & ELS_ELS_KS13_KS13_FRTN_MASK)

#define ELS_ELS_KS13_KS13_FHWO_MASK              (0x200U)
#define ELS_ELS_KS13_KS13_FHWO_SHIFT             (9U)
#define ELS_ELS_KS13_KS13_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_FHWO_SHIFT)) & ELS_ELS_KS13_KS13_FHWO_MASK)

#define ELS_ELS_KS13_KS13_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS13_KS13_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS13_KS13_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKPUK_SHIFT)) & ELS_ELS_KS13_KS13_UKPUK_MASK)

#define ELS_ELS_KS13_KS13_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS13_KS13_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS13_KS13_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UTECDH_SHIFT)) & ELS_ELS_KS13_KS13_UTECDH_MASK)

#define ELS_ELS_KS13_KS13_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS13_KS13_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS13_KS13_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UCMAC_SHIFT)) & ELS_ELS_KS13_KS13_UCMAC_MASK)

#define ELS_ELS_KS13_KS13_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS13_KS13_UKSK_SHIFT             (14U)
#define ELS_ELS_KS13_KS13_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKSK_SHIFT)) & ELS_ELS_KS13_KS13_UKSK_MASK)

#define ELS_ELS_KS13_KS13_URTF_MASK              (0x8000U)
#define ELS_ELS_KS13_KS13_URTF_SHIFT             (15U)
#define ELS_ELS_KS13_KS13_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_URTF_SHIFT)) & ELS_ELS_KS13_KS13_URTF_MASK)

#define ELS_ELS_KS13_KS13_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS13_KS13_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS13_KS13_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UCKDF_SHIFT)) & ELS_ELS_KS13_KS13_UCKDF_MASK)

#define ELS_ELS_KS13_KS13_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS13_KS13_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS13_KS13_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UHKDF_SHIFT)) & ELS_ELS_KS13_KS13_UHKDF_MASK)

#define ELS_ELS_KS13_KS13_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS13_KS13_UECSG_SHIFT            (18U)
#define ELS_ELS_KS13_KS13_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UECSG_SHIFT)) & ELS_ELS_KS13_KS13_UECSG_MASK)

#define ELS_ELS_KS13_KS13_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS13_KS13_UECDH_SHIFT            (19U)
#define ELS_ELS_KS13_KS13_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UECDH_SHIFT)) & ELS_ELS_KS13_KS13_UECDH_MASK)

#define ELS_ELS_KS13_KS13_UAES_MASK              (0x100000U)
#define ELS_ELS_KS13_KS13_UAES_SHIFT             (20U)
#define ELS_ELS_KS13_KS13_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UAES_SHIFT)) & ELS_ELS_KS13_KS13_UAES_MASK)

#define ELS_ELS_KS13_KS13_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS13_KS13_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS13_KS13_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UHMAC_SHIFT)) & ELS_ELS_KS13_KS13_UHMAC_MASK)

#define ELS_ELS_KS13_KS13_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS13_KS13_UKWK_SHIFT             (22U)
#define ELS_ELS_KS13_KS13_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKWK_SHIFT)) & ELS_ELS_KS13_KS13_UKWK_MASK)

#define ELS_ELS_KS13_KS13_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS13_KS13_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS13_KS13_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKUOK_SHIFT)) & ELS_ELS_KS13_KS13_UKUOK_MASK)

#define ELS_ELS_KS13_KS13_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS13_KS13_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS13_KS13_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UTLSPMS_SHIFT)) & ELS_ELS_KS13_KS13_UTLSPMS_MASK)

#define ELS_ELS_KS13_KS13_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS13_KS13_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS13_KS13_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UTLSMS_SHIFT)) & ELS_ELS_KS13_KS13_UTLSMS_MASK)

#define ELS_ELS_KS13_KS13_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS13_KS13_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS13_KS13_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKGSRC_SHIFT)) & ELS_ELS_KS13_KS13_UKGSRC_MASK)

#define ELS_ELS_KS13_KS13_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS13_KS13_UHWO_SHIFT             (27U)
#define ELS_ELS_KS13_KS13_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UHWO_SHIFT)) & ELS_ELS_KS13_KS13_UHWO_MASK)

#define ELS_ELS_KS13_KS13_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS13_KS13_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS13_KS13_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UWRPOK_SHIFT)) & ELS_ELS_KS13_KS13_UWRPOK_MASK)

#define ELS_ELS_KS13_KS13_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS13_KS13_UDUK_SHIFT             (29U)
#define ELS_ELS_KS13_KS13_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UDUK_SHIFT)) & ELS_ELS_KS13_KS13_UDUK_MASK)

#define ELS_ELS_KS13_KS13_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS13_KS13_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS13_KS13_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UPPROT_SHIFT)) & ELS_ELS_KS13_KS13_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS14 - Status Register */
/*! @{ */

#define ELS_ELS_KS14_KS14_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS14_KS14_KSIZE_SHIFT            (0U)
/*! KS14_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS14_KS14_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_KSIZE_SHIFT)) & ELS_ELS_KS14_KS14_KSIZE_MASK)

#define ELS_ELS_KS14_KS14_KACT_MASK              (0x20U)
#define ELS_ELS_KS14_KS14_KACT_SHIFT             (5U)
#define ELS_ELS_KS14_KS14_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_KACT_SHIFT)) & ELS_ELS_KS14_KS14_KACT_MASK)

#define ELS_ELS_KS14_KS14_KBASE_MASK             (0x40U)
#define ELS_ELS_KS14_KS14_KBASE_SHIFT            (6U)
#define ELS_ELS_KS14_KS14_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_KBASE_SHIFT)) & ELS_ELS_KS14_KS14_KBASE_MASK)

#define ELS_ELS_KS14_KS14_FGP_MASK               (0x80U)
#define ELS_ELS_KS14_KS14_FGP_SHIFT              (7U)
#define ELS_ELS_KS14_KS14_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_FGP_SHIFT)) & ELS_ELS_KS14_KS14_FGP_MASK)

#define ELS_ELS_KS14_KS14_FRTN_MASK              (0x100U)
#define ELS_ELS_KS14_KS14_FRTN_SHIFT             (8U)
#define ELS_ELS_KS14_KS14_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_FRTN_SHIFT)) & ELS_ELS_KS14_KS14_FRTN_MASK)

#define ELS_ELS_KS14_KS14_FHWO_MASK              (0x200U)
#define ELS_ELS_KS14_KS14_FHWO_SHIFT             (9U)
#define ELS_ELS_KS14_KS14_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_FHWO_SHIFT)) & ELS_ELS_KS14_KS14_FHWO_MASK)

#define ELS_ELS_KS14_KS14_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS14_KS14_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS14_KS14_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKPUK_SHIFT)) & ELS_ELS_KS14_KS14_UKPUK_MASK)

#define ELS_ELS_KS14_KS14_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS14_KS14_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS14_KS14_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UTECDH_SHIFT)) & ELS_ELS_KS14_KS14_UTECDH_MASK)

#define ELS_ELS_KS14_KS14_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS14_KS14_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS14_KS14_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UCMAC_SHIFT)) & ELS_ELS_KS14_KS14_UCMAC_MASK)

#define ELS_ELS_KS14_KS14_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS14_KS14_UKSK_SHIFT             (14U)
#define ELS_ELS_KS14_KS14_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKSK_SHIFT)) & ELS_ELS_KS14_KS14_UKSK_MASK)

#define ELS_ELS_KS14_KS14_URTF_MASK              (0x8000U)
#define ELS_ELS_KS14_KS14_URTF_SHIFT             (15U)
#define ELS_ELS_KS14_KS14_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_URTF_SHIFT)) & ELS_ELS_KS14_KS14_URTF_MASK)

#define ELS_ELS_KS14_KS14_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS14_KS14_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS14_KS14_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UCKDF_SHIFT)) & ELS_ELS_KS14_KS14_UCKDF_MASK)

#define ELS_ELS_KS14_KS14_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS14_KS14_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS14_KS14_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UHKDF_SHIFT)) & ELS_ELS_KS14_KS14_UHKDF_MASK)

#define ELS_ELS_KS14_KS14_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS14_KS14_UECSG_SHIFT            (18U)
#define ELS_ELS_KS14_KS14_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UECSG_SHIFT)) & ELS_ELS_KS14_KS14_UECSG_MASK)

#define ELS_ELS_KS14_KS14_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS14_KS14_UECDH_SHIFT            (19U)
#define ELS_ELS_KS14_KS14_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UECDH_SHIFT)) & ELS_ELS_KS14_KS14_UECDH_MASK)

#define ELS_ELS_KS14_KS14_UAES_MASK              (0x100000U)
#define ELS_ELS_KS14_KS14_UAES_SHIFT             (20U)
#define ELS_ELS_KS14_KS14_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UAES_SHIFT)) & ELS_ELS_KS14_KS14_UAES_MASK)

#define ELS_ELS_KS14_KS14_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS14_KS14_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS14_KS14_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UHMAC_SHIFT)) & ELS_ELS_KS14_KS14_UHMAC_MASK)

#define ELS_ELS_KS14_KS14_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS14_KS14_UKWK_SHIFT             (22U)
#define ELS_ELS_KS14_KS14_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKWK_SHIFT)) & ELS_ELS_KS14_KS14_UKWK_MASK)

#define ELS_ELS_KS14_KS14_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS14_KS14_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS14_KS14_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKUOK_SHIFT)) & ELS_ELS_KS14_KS14_UKUOK_MASK)

#define ELS_ELS_KS14_KS14_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS14_KS14_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS14_KS14_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UTLSPMS_SHIFT)) & ELS_ELS_KS14_KS14_UTLSPMS_MASK)

#define ELS_ELS_KS14_KS14_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS14_KS14_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS14_KS14_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UTLSMS_SHIFT)) & ELS_ELS_KS14_KS14_UTLSMS_MASK)

#define ELS_ELS_KS14_KS14_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS14_KS14_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS14_KS14_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKGSRC_SHIFT)) & ELS_ELS_KS14_KS14_UKGSRC_MASK)

#define ELS_ELS_KS14_KS14_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS14_KS14_UHWO_SHIFT             (27U)
#define ELS_ELS_KS14_KS14_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UHWO_SHIFT)) & ELS_ELS_KS14_KS14_UHWO_MASK)

#define ELS_ELS_KS14_KS14_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS14_KS14_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS14_KS14_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UWRPOK_SHIFT)) & ELS_ELS_KS14_KS14_UWRPOK_MASK)

#define ELS_ELS_KS14_KS14_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS14_KS14_UDUK_SHIFT             (29U)
#define ELS_ELS_KS14_KS14_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UDUK_SHIFT)) & ELS_ELS_KS14_KS14_UDUK_MASK)

#define ELS_ELS_KS14_KS14_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS14_KS14_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS14_KS14_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UPPROT_SHIFT)) & ELS_ELS_KS14_KS14_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS15 - Status Register */
/*! @{ */

#define ELS_ELS_KS15_KS15_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS15_KS15_KSIZE_SHIFT            (0U)
/*! KS15_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS15_KS15_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_KSIZE_SHIFT)) & ELS_ELS_KS15_KS15_KSIZE_MASK)

#define ELS_ELS_KS15_KS15_KACT_MASK              (0x20U)
#define ELS_ELS_KS15_KS15_KACT_SHIFT             (5U)
#define ELS_ELS_KS15_KS15_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_KACT_SHIFT)) & ELS_ELS_KS15_KS15_KACT_MASK)

#define ELS_ELS_KS15_KS15_KBASE_MASK             (0x40U)
#define ELS_ELS_KS15_KS15_KBASE_SHIFT            (6U)
#define ELS_ELS_KS15_KS15_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_KBASE_SHIFT)) & ELS_ELS_KS15_KS15_KBASE_MASK)

#define ELS_ELS_KS15_KS15_FGP_MASK               (0x80U)
#define ELS_ELS_KS15_KS15_FGP_SHIFT              (7U)
#define ELS_ELS_KS15_KS15_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_FGP_SHIFT)) & ELS_ELS_KS15_KS15_FGP_MASK)

#define ELS_ELS_KS15_KS15_FRTN_MASK              (0x100U)
#define ELS_ELS_KS15_KS15_FRTN_SHIFT             (8U)
#define ELS_ELS_KS15_KS15_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_FRTN_SHIFT)) & ELS_ELS_KS15_KS15_FRTN_MASK)

#define ELS_ELS_KS15_KS15_FHWO_MASK              (0x200U)
#define ELS_ELS_KS15_KS15_FHWO_SHIFT             (9U)
#define ELS_ELS_KS15_KS15_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_FHWO_SHIFT)) & ELS_ELS_KS15_KS15_FHWO_MASK)

#define ELS_ELS_KS15_KS15_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS15_KS15_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS15_KS15_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKPUK_SHIFT)) & ELS_ELS_KS15_KS15_UKPUK_MASK)

#define ELS_ELS_KS15_KS15_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS15_KS15_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS15_KS15_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UTECDH_SHIFT)) & ELS_ELS_KS15_KS15_UTECDH_MASK)

#define ELS_ELS_KS15_KS15_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS15_KS15_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS15_KS15_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UCMAC_SHIFT)) & ELS_ELS_KS15_KS15_UCMAC_MASK)

#define ELS_ELS_KS15_KS15_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS15_KS15_UKSK_SHIFT             (14U)
#define ELS_ELS_KS15_KS15_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKSK_SHIFT)) & ELS_ELS_KS15_KS15_UKSK_MASK)

#define ELS_ELS_KS15_KS15_URTF_MASK              (0x8000U)
#define ELS_ELS_KS15_KS15_URTF_SHIFT             (15U)
#define ELS_ELS_KS15_KS15_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_URTF_SHIFT)) & ELS_ELS_KS15_KS15_URTF_MASK)

#define ELS_ELS_KS15_KS15_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS15_KS15_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS15_KS15_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UCKDF_SHIFT)) & ELS_ELS_KS15_KS15_UCKDF_MASK)

#define ELS_ELS_KS15_KS15_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS15_KS15_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS15_KS15_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UHKDF_SHIFT)) & ELS_ELS_KS15_KS15_UHKDF_MASK)

#define ELS_ELS_KS15_KS15_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS15_KS15_UECSG_SHIFT            (18U)
#define ELS_ELS_KS15_KS15_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UECSG_SHIFT)) & ELS_ELS_KS15_KS15_UECSG_MASK)

#define ELS_ELS_KS15_KS15_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS15_KS15_UECDH_SHIFT            (19U)
#define ELS_ELS_KS15_KS15_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UECDH_SHIFT)) & ELS_ELS_KS15_KS15_UECDH_MASK)

#define ELS_ELS_KS15_KS15_UAES_MASK              (0x100000U)
#define ELS_ELS_KS15_KS15_UAES_SHIFT             (20U)
#define ELS_ELS_KS15_KS15_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UAES_SHIFT)) & ELS_ELS_KS15_KS15_UAES_MASK)

#define ELS_ELS_KS15_KS15_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS15_KS15_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS15_KS15_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UHMAC_SHIFT)) & ELS_ELS_KS15_KS15_UHMAC_MASK)

#define ELS_ELS_KS15_KS15_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS15_KS15_UKWK_SHIFT             (22U)
#define ELS_ELS_KS15_KS15_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKWK_SHIFT)) & ELS_ELS_KS15_KS15_UKWK_MASK)

#define ELS_ELS_KS15_KS15_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS15_KS15_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS15_KS15_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKUOK_SHIFT)) & ELS_ELS_KS15_KS15_UKUOK_MASK)

#define ELS_ELS_KS15_KS15_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS15_KS15_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS15_KS15_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UTLSPMS_SHIFT)) & ELS_ELS_KS15_KS15_UTLSPMS_MASK)

#define ELS_ELS_KS15_KS15_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS15_KS15_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS15_KS15_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UTLSMS_SHIFT)) & ELS_ELS_KS15_KS15_UTLSMS_MASK)

#define ELS_ELS_KS15_KS15_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS15_KS15_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS15_KS15_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKGSRC_SHIFT)) & ELS_ELS_KS15_KS15_UKGSRC_MASK)

#define ELS_ELS_KS15_KS15_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS15_KS15_UHWO_SHIFT             (27U)
#define ELS_ELS_KS15_KS15_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UHWO_SHIFT)) & ELS_ELS_KS15_KS15_UHWO_MASK)

#define ELS_ELS_KS15_KS15_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS15_KS15_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS15_KS15_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UWRPOK_SHIFT)) & ELS_ELS_KS15_KS15_UWRPOK_MASK)

#define ELS_ELS_KS15_KS15_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS15_KS15_UDUK_SHIFT             (29U)
#define ELS_ELS_KS15_KS15_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UDUK_SHIFT)) & ELS_ELS_KS15_KS15_UDUK_MASK)

#define ELS_ELS_KS15_KS15_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS15_KS15_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS15_KS15_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UPPROT_SHIFT)) & ELS_ELS_KS15_KS15_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS16 - Status Register */
/*! @{ */

#define ELS_ELS_KS16_KS16_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS16_KS16_KSIZE_SHIFT            (0U)
/*! KS16_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS16_KS16_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_KSIZE_SHIFT)) & ELS_ELS_KS16_KS16_KSIZE_MASK)

#define ELS_ELS_KS16_KS16_KACT_MASK              (0x20U)
#define ELS_ELS_KS16_KS16_KACT_SHIFT             (5U)
#define ELS_ELS_KS16_KS16_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_KACT_SHIFT)) & ELS_ELS_KS16_KS16_KACT_MASK)

#define ELS_ELS_KS16_KS16_KBASE_MASK             (0x40U)
#define ELS_ELS_KS16_KS16_KBASE_SHIFT            (6U)
#define ELS_ELS_KS16_KS16_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_KBASE_SHIFT)) & ELS_ELS_KS16_KS16_KBASE_MASK)

#define ELS_ELS_KS16_KS16_FGP_MASK               (0x80U)
#define ELS_ELS_KS16_KS16_FGP_SHIFT              (7U)
#define ELS_ELS_KS16_KS16_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_FGP_SHIFT)) & ELS_ELS_KS16_KS16_FGP_MASK)

#define ELS_ELS_KS16_KS16_FRTN_MASK              (0x100U)
#define ELS_ELS_KS16_KS16_FRTN_SHIFT             (8U)
#define ELS_ELS_KS16_KS16_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_FRTN_SHIFT)) & ELS_ELS_KS16_KS16_FRTN_MASK)

#define ELS_ELS_KS16_KS16_FHWO_MASK              (0x200U)
#define ELS_ELS_KS16_KS16_FHWO_SHIFT             (9U)
#define ELS_ELS_KS16_KS16_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_FHWO_SHIFT)) & ELS_ELS_KS16_KS16_FHWO_MASK)

#define ELS_ELS_KS16_KS16_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS16_KS16_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS16_KS16_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKPUK_SHIFT)) & ELS_ELS_KS16_KS16_UKPUK_MASK)

#define ELS_ELS_KS16_KS16_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS16_KS16_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS16_KS16_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UTECDH_SHIFT)) & ELS_ELS_KS16_KS16_UTECDH_MASK)

#define ELS_ELS_KS16_KS16_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS16_KS16_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS16_KS16_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UCMAC_SHIFT)) & ELS_ELS_KS16_KS16_UCMAC_MASK)

#define ELS_ELS_KS16_KS16_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS16_KS16_UKSK_SHIFT             (14U)
#define ELS_ELS_KS16_KS16_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKSK_SHIFT)) & ELS_ELS_KS16_KS16_UKSK_MASK)

#define ELS_ELS_KS16_KS16_URTF_MASK              (0x8000U)
#define ELS_ELS_KS16_KS16_URTF_SHIFT             (15U)
#define ELS_ELS_KS16_KS16_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_URTF_SHIFT)) & ELS_ELS_KS16_KS16_URTF_MASK)

#define ELS_ELS_KS16_KS16_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS16_KS16_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS16_KS16_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UCKDF_SHIFT)) & ELS_ELS_KS16_KS16_UCKDF_MASK)

#define ELS_ELS_KS16_KS16_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS16_KS16_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS16_KS16_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UHKDF_SHIFT)) & ELS_ELS_KS16_KS16_UHKDF_MASK)

#define ELS_ELS_KS16_KS16_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS16_KS16_UECSG_SHIFT            (18U)
#define ELS_ELS_KS16_KS16_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UECSG_SHIFT)) & ELS_ELS_KS16_KS16_UECSG_MASK)

#define ELS_ELS_KS16_KS16_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS16_KS16_UECDH_SHIFT            (19U)
#define ELS_ELS_KS16_KS16_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UECDH_SHIFT)) & ELS_ELS_KS16_KS16_UECDH_MASK)

#define ELS_ELS_KS16_KS16_UAES_MASK              (0x100000U)
#define ELS_ELS_KS16_KS16_UAES_SHIFT             (20U)
#define ELS_ELS_KS16_KS16_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UAES_SHIFT)) & ELS_ELS_KS16_KS16_UAES_MASK)

#define ELS_ELS_KS16_KS16_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS16_KS16_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS16_KS16_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UHMAC_SHIFT)) & ELS_ELS_KS16_KS16_UHMAC_MASK)

#define ELS_ELS_KS16_KS16_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS16_KS16_UKWK_SHIFT             (22U)
#define ELS_ELS_KS16_KS16_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKWK_SHIFT)) & ELS_ELS_KS16_KS16_UKWK_MASK)

#define ELS_ELS_KS16_KS16_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS16_KS16_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS16_KS16_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKUOK_SHIFT)) & ELS_ELS_KS16_KS16_UKUOK_MASK)

#define ELS_ELS_KS16_KS16_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS16_KS16_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS16_KS16_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UTLSPMS_SHIFT)) & ELS_ELS_KS16_KS16_UTLSPMS_MASK)

#define ELS_ELS_KS16_KS16_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS16_KS16_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS16_KS16_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UTLSMS_SHIFT)) & ELS_ELS_KS16_KS16_UTLSMS_MASK)

#define ELS_ELS_KS16_KS16_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS16_KS16_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS16_KS16_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKGSRC_SHIFT)) & ELS_ELS_KS16_KS16_UKGSRC_MASK)

#define ELS_ELS_KS16_KS16_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS16_KS16_UHWO_SHIFT             (27U)
#define ELS_ELS_KS16_KS16_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UHWO_SHIFT)) & ELS_ELS_KS16_KS16_UHWO_MASK)

#define ELS_ELS_KS16_KS16_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS16_KS16_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS16_KS16_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UWRPOK_SHIFT)) & ELS_ELS_KS16_KS16_UWRPOK_MASK)

#define ELS_ELS_KS16_KS16_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS16_KS16_UDUK_SHIFT             (29U)
#define ELS_ELS_KS16_KS16_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UDUK_SHIFT)) & ELS_ELS_KS16_KS16_UDUK_MASK)

#define ELS_ELS_KS16_KS16_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS16_KS16_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS16_KS16_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UPPROT_SHIFT)) & ELS_ELS_KS16_KS16_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS17 - Status Register */
/*! @{ */

#define ELS_ELS_KS17_KS17_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS17_KS17_KSIZE_SHIFT            (0U)
/*! KS17_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS17_KS17_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_KSIZE_SHIFT)) & ELS_ELS_KS17_KS17_KSIZE_MASK)

#define ELS_ELS_KS17_KS17_KACT_MASK              (0x20U)
#define ELS_ELS_KS17_KS17_KACT_SHIFT             (5U)
#define ELS_ELS_KS17_KS17_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_KACT_SHIFT)) & ELS_ELS_KS17_KS17_KACT_MASK)

#define ELS_ELS_KS17_KS17_KBASE_MASK             (0x40U)
#define ELS_ELS_KS17_KS17_KBASE_SHIFT            (6U)
#define ELS_ELS_KS17_KS17_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_KBASE_SHIFT)) & ELS_ELS_KS17_KS17_KBASE_MASK)

#define ELS_ELS_KS17_KS17_FGP_MASK               (0x80U)
#define ELS_ELS_KS17_KS17_FGP_SHIFT              (7U)
#define ELS_ELS_KS17_KS17_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_FGP_SHIFT)) & ELS_ELS_KS17_KS17_FGP_MASK)

#define ELS_ELS_KS17_KS17_FRTN_MASK              (0x100U)
#define ELS_ELS_KS17_KS17_FRTN_SHIFT             (8U)
#define ELS_ELS_KS17_KS17_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_FRTN_SHIFT)) & ELS_ELS_KS17_KS17_FRTN_MASK)

#define ELS_ELS_KS17_KS17_FHWO_MASK              (0x200U)
#define ELS_ELS_KS17_KS17_FHWO_SHIFT             (9U)
#define ELS_ELS_KS17_KS17_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_FHWO_SHIFT)) & ELS_ELS_KS17_KS17_FHWO_MASK)

#define ELS_ELS_KS17_KS17_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS17_KS17_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS17_KS17_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKPUK_SHIFT)) & ELS_ELS_KS17_KS17_UKPUK_MASK)

#define ELS_ELS_KS17_KS17_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS17_KS17_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS17_KS17_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UTECDH_SHIFT)) & ELS_ELS_KS17_KS17_UTECDH_MASK)

#define ELS_ELS_KS17_KS17_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS17_KS17_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS17_KS17_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UCMAC_SHIFT)) & ELS_ELS_KS17_KS17_UCMAC_MASK)

#define ELS_ELS_KS17_KS17_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS17_KS17_UKSK_SHIFT             (14U)
#define ELS_ELS_KS17_KS17_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKSK_SHIFT)) & ELS_ELS_KS17_KS17_UKSK_MASK)

#define ELS_ELS_KS17_KS17_URTF_MASK              (0x8000U)
#define ELS_ELS_KS17_KS17_URTF_SHIFT             (15U)
#define ELS_ELS_KS17_KS17_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_URTF_SHIFT)) & ELS_ELS_KS17_KS17_URTF_MASK)

#define ELS_ELS_KS17_KS17_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS17_KS17_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS17_KS17_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UCKDF_SHIFT)) & ELS_ELS_KS17_KS17_UCKDF_MASK)

#define ELS_ELS_KS17_KS17_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS17_KS17_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS17_KS17_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UHKDF_SHIFT)) & ELS_ELS_KS17_KS17_UHKDF_MASK)

#define ELS_ELS_KS17_KS17_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS17_KS17_UECSG_SHIFT            (18U)
#define ELS_ELS_KS17_KS17_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UECSG_SHIFT)) & ELS_ELS_KS17_KS17_UECSG_MASK)

#define ELS_ELS_KS17_KS17_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS17_KS17_UECDH_SHIFT            (19U)
#define ELS_ELS_KS17_KS17_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UECDH_SHIFT)) & ELS_ELS_KS17_KS17_UECDH_MASK)

#define ELS_ELS_KS17_KS17_UAES_MASK              (0x100000U)
#define ELS_ELS_KS17_KS17_UAES_SHIFT             (20U)
#define ELS_ELS_KS17_KS17_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UAES_SHIFT)) & ELS_ELS_KS17_KS17_UAES_MASK)

#define ELS_ELS_KS17_KS17_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS17_KS17_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS17_KS17_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UHMAC_SHIFT)) & ELS_ELS_KS17_KS17_UHMAC_MASK)

#define ELS_ELS_KS17_KS17_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS17_KS17_UKWK_SHIFT             (22U)
#define ELS_ELS_KS17_KS17_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKWK_SHIFT)) & ELS_ELS_KS17_KS17_UKWK_MASK)

#define ELS_ELS_KS17_KS17_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS17_KS17_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS17_KS17_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKUOK_SHIFT)) & ELS_ELS_KS17_KS17_UKUOK_MASK)

#define ELS_ELS_KS17_KS17_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS17_KS17_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS17_KS17_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UTLSPMS_SHIFT)) & ELS_ELS_KS17_KS17_UTLSPMS_MASK)

#define ELS_ELS_KS17_KS17_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS17_KS17_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS17_KS17_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UTLSMS_SHIFT)) & ELS_ELS_KS17_KS17_UTLSMS_MASK)

#define ELS_ELS_KS17_KS17_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS17_KS17_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS17_KS17_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKGSRC_SHIFT)) & ELS_ELS_KS17_KS17_UKGSRC_MASK)

#define ELS_ELS_KS17_KS17_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS17_KS17_UHWO_SHIFT             (27U)
#define ELS_ELS_KS17_KS17_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UHWO_SHIFT)) & ELS_ELS_KS17_KS17_UHWO_MASK)

#define ELS_ELS_KS17_KS17_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS17_KS17_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS17_KS17_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UWRPOK_SHIFT)) & ELS_ELS_KS17_KS17_UWRPOK_MASK)

#define ELS_ELS_KS17_KS17_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS17_KS17_UDUK_SHIFT             (29U)
#define ELS_ELS_KS17_KS17_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UDUK_SHIFT)) & ELS_ELS_KS17_KS17_UDUK_MASK)

#define ELS_ELS_KS17_KS17_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS17_KS17_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS17_KS17_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UPPROT_SHIFT)) & ELS_ELS_KS17_KS17_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS18 - Status Register */
/*! @{ */

#define ELS_ELS_KS18_KS18_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS18_KS18_KSIZE_SHIFT            (0U)
/*! KS18_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS18_KS18_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_KSIZE_SHIFT)) & ELS_ELS_KS18_KS18_KSIZE_MASK)

#define ELS_ELS_KS18_KS18_KACT_MASK              (0x20U)
#define ELS_ELS_KS18_KS18_KACT_SHIFT             (5U)
#define ELS_ELS_KS18_KS18_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_KACT_SHIFT)) & ELS_ELS_KS18_KS18_KACT_MASK)

#define ELS_ELS_KS18_KS18_KBASE_MASK             (0x40U)
#define ELS_ELS_KS18_KS18_KBASE_SHIFT            (6U)
#define ELS_ELS_KS18_KS18_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_KBASE_SHIFT)) & ELS_ELS_KS18_KS18_KBASE_MASK)

#define ELS_ELS_KS18_KS18_FGP_MASK               (0x80U)
#define ELS_ELS_KS18_KS18_FGP_SHIFT              (7U)
#define ELS_ELS_KS18_KS18_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_FGP_SHIFT)) & ELS_ELS_KS18_KS18_FGP_MASK)

#define ELS_ELS_KS18_KS18_FRTN_MASK              (0x100U)
#define ELS_ELS_KS18_KS18_FRTN_SHIFT             (8U)
#define ELS_ELS_KS18_KS18_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_FRTN_SHIFT)) & ELS_ELS_KS18_KS18_FRTN_MASK)

#define ELS_ELS_KS18_KS18_FHWO_MASK              (0x200U)
#define ELS_ELS_KS18_KS18_FHWO_SHIFT             (9U)
#define ELS_ELS_KS18_KS18_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_FHWO_SHIFT)) & ELS_ELS_KS18_KS18_FHWO_MASK)

#define ELS_ELS_KS18_KS18_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS18_KS18_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS18_KS18_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKPUK_SHIFT)) & ELS_ELS_KS18_KS18_UKPUK_MASK)

#define ELS_ELS_KS18_KS18_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS18_KS18_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS18_KS18_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UTECDH_SHIFT)) & ELS_ELS_KS18_KS18_UTECDH_MASK)

#define ELS_ELS_KS18_KS18_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS18_KS18_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS18_KS18_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UCMAC_SHIFT)) & ELS_ELS_KS18_KS18_UCMAC_MASK)

#define ELS_ELS_KS18_KS18_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS18_KS18_UKSK_SHIFT             (14U)
#define ELS_ELS_KS18_KS18_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKSK_SHIFT)) & ELS_ELS_KS18_KS18_UKSK_MASK)

#define ELS_ELS_KS18_KS18_URTF_MASK              (0x8000U)
#define ELS_ELS_KS18_KS18_URTF_SHIFT             (15U)
#define ELS_ELS_KS18_KS18_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_URTF_SHIFT)) & ELS_ELS_KS18_KS18_URTF_MASK)

#define ELS_ELS_KS18_KS18_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS18_KS18_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS18_KS18_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UCKDF_SHIFT)) & ELS_ELS_KS18_KS18_UCKDF_MASK)

#define ELS_ELS_KS18_KS18_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS18_KS18_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS18_KS18_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UHKDF_SHIFT)) & ELS_ELS_KS18_KS18_UHKDF_MASK)

#define ELS_ELS_KS18_KS18_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS18_KS18_UECSG_SHIFT            (18U)
#define ELS_ELS_KS18_KS18_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UECSG_SHIFT)) & ELS_ELS_KS18_KS18_UECSG_MASK)

#define ELS_ELS_KS18_KS18_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS18_KS18_UECDH_SHIFT            (19U)
#define ELS_ELS_KS18_KS18_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UECDH_SHIFT)) & ELS_ELS_KS18_KS18_UECDH_MASK)

#define ELS_ELS_KS18_KS18_UAES_MASK              (0x100000U)
#define ELS_ELS_KS18_KS18_UAES_SHIFT             (20U)
#define ELS_ELS_KS18_KS18_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UAES_SHIFT)) & ELS_ELS_KS18_KS18_UAES_MASK)

#define ELS_ELS_KS18_KS18_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS18_KS18_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS18_KS18_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UHMAC_SHIFT)) & ELS_ELS_KS18_KS18_UHMAC_MASK)

#define ELS_ELS_KS18_KS18_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS18_KS18_UKWK_SHIFT             (22U)
#define ELS_ELS_KS18_KS18_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKWK_SHIFT)) & ELS_ELS_KS18_KS18_UKWK_MASK)

#define ELS_ELS_KS18_KS18_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS18_KS18_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS18_KS18_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKUOK_SHIFT)) & ELS_ELS_KS18_KS18_UKUOK_MASK)

#define ELS_ELS_KS18_KS18_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS18_KS18_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS18_KS18_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UTLSPMS_SHIFT)) & ELS_ELS_KS18_KS18_UTLSPMS_MASK)

#define ELS_ELS_KS18_KS18_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS18_KS18_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS18_KS18_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UTLSMS_SHIFT)) & ELS_ELS_KS18_KS18_UTLSMS_MASK)

#define ELS_ELS_KS18_KS18_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS18_KS18_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS18_KS18_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKGSRC_SHIFT)) & ELS_ELS_KS18_KS18_UKGSRC_MASK)

#define ELS_ELS_KS18_KS18_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS18_KS18_UHWO_SHIFT             (27U)
#define ELS_ELS_KS18_KS18_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UHWO_SHIFT)) & ELS_ELS_KS18_KS18_UHWO_MASK)

#define ELS_ELS_KS18_KS18_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS18_KS18_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS18_KS18_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UWRPOK_SHIFT)) & ELS_ELS_KS18_KS18_UWRPOK_MASK)

#define ELS_ELS_KS18_KS18_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS18_KS18_UDUK_SHIFT             (29U)
#define ELS_ELS_KS18_KS18_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UDUK_SHIFT)) & ELS_ELS_KS18_KS18_UDUK_MASK)

#define ELS_ELS_KS18_KS18_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS18_KS18_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS18_KS18_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UPPROT_SHIFT)) & ELS_ELS_KS18_KS18_UPPROT_MASK)
/*! @} */

/*! @name ELS_KS19 - Status Register */
/*! @{ */

#define ELS_ELS_KS19_KS19_KSIZE_MASK             (0x3U)
#define ELS_ELS_KS19_KS19_KSIZE_SHIFT            (0U)
/*! KS19_KSIZE
 *  0b00..128
 *  0b01..256
 */
#define ELS_ELS_KS19_KS19_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_KSIZE_SHIFT)) & ELS_ELS_KS19_KS19_KSIZE_MASK)

#define ELS_ELS_KS19_KS19_KACT_MASK              (0x20U)
#define ELS_ELS_KS19_KS19_KACT_SHIFT             (5U)
#define ELS_ELS_KS19_KS19_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_KACT_SHIFT)) & ELS_ELS_KS19_KS19_KACT_MASK)

#define ELS_ELS_KS19_KS19_KBASE_MASK             (0x40U)
#define ELS_ELS_KS19_KS19_KBASE_SHIFT            (6U)
#define ELS_ELS_KS19_KS19_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_KBASE_SHIFT)) & ELS_ELS_KS19_KS19_KBASE_MASK)

#define ELS_ELS_KS19_KS19_FGP_MASK               (0x80U)
#define ELS_ELS_KS19_KS19_FGP_SHIFT              (7U)
#define ELS_ELS_KS19_KS19_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_FGP_SHIFT)) & ELS_ELS_KS19_KS19_FGP_MASK)

#define ELS_ELS_KS19_KS19_FRTN_MASK              (0x100U)
#define ELS_ELS_KS19_KS19_FRTN_SHIFT             (8U)
#define ELS_ELS_KS19_KS19_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_FRTN_SHIFT)) & ELS_ELS_KS19_KS19_FRTN_MASK)

#define ELS_ELS_KS19_KS19_FHWO_MASK              (0x200U)
#define ELS_ELS_KS19_KS19_FHWO_SHIFT             (9U)
#define ELS_ELS_KS19_KS19_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_FHWO_SHIFT)) & ELS_ELS_KS19_KS19_FHWO_MASK)

#define ELS_ELS_KS19_KS19_UKPUK_MASK             (0x800U)
#define ELS_ELS_KS19_KS19_UKPUK_SHIFT            (11U)
#define ELS_ELS_KS19_KS19_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKPUK_SHIFT)) & ELS_ELS_KS19_KS19_UKPUK_MASK)

#define ELS_ELS_KS19_KS19_UTECDH_MASK            (0x1000U)
#define ELS_ELS_KS19_KS19_UTECDH_SHIFT           (12U)
#define ELS_ELS_KS19_KS19_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UTECDH_SHIFT)) & ELS_ELS_KS19_KS19_UTECDH_MASK)

#define ELS_ELS_KS19_KS19_UCMAC_MASK             (0x2000U)
#define ELS_ELS_KS19_KS19_UCMAC_SHIFT            (13U)
#define ELS_ELS_KS19_KS19_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UCMAC_SHIFT)) & ELS_ELS_KS19_KS19_UCMAC_MASK)

#define ELS_ELS_KS19_KS19_UKSK_MASK              (0x4000U)
#define ELS_ELS_KS19_KS19_UKSK_SHIFT             (14U)
#define ELS_ELS_KS19_KS19_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKSK_SHIFT)) & ELS_ELS_KS19_KS19_UKSK_MASK)

#define ELS_ELS_KS19_KS19_URTF_MASK              (0x8000U)
#define ELS_ELS_KS19_KS19_URTF_SHIFT             (15U)
#define ELS_ELS_KS19_KS19_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_URTF_SHIFT)) & ELS_ELS_KS19_KS19_URTF_MASK)

#define ELS_ELS_KS19_KS19_UCKDF_MASK             (0x10000U)
#define ELS_ELS_KS19_KS19_UCKDF_SHIFT            (16U)
#define ELS_ELS_KS19_KS19_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UCKDF_SHIFT)) & ELS_ELS_KS19_KS19_UCKDF_MASK)

#define ELS_ELS_KS19_KS19_UHKDF_MASK             (0x20000U)
#define ELS_ELS_KS19_KS19_UHKDF_SHIFT            (17U)
#define ELS_ELS_KS19_KS19_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UHKDF_SHIFT)) & ELS_ELS_KS19_KS19_UHKDF_MASK)

#define ELS_ELS_KS19_KS19_UECSG_MASK             (0x40000U)
#define ELS_ELS_KS19_KS19_UECSG_SHIFT            (18U)
#define ELS_ELS_KS19_KS19_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UECSG_SHIFT)) & ELS_ELS_KS19_KS19_UECSG_MASK)

#define ELS_ELS_KS19_KS19_UECDH_MASK             (0x80000U)
#define ELS_ELS_KS19_KS19_UECDH_SHIFT            (19U)
#define ELS_ELS_KS19_KS19_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UECDH_SHIFT)) & ELS_ELS_KS19_KS19_UECDH_MASK)

#define ELS_ELS_KS19_KS19_UAES_MASK              (0x100000U)
#define ELS_ELS_KS19_KS19_UAES_SHIFT             (20U)
#define ELS_ELS_KS19_KS19_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UAES_SHIFT)) & ELS_ELS_KS19_KS19_UAES_MASK)

#define ELS_ELS_KS19_KS19_UHMAC_MASK             (0x200000U)
#define ELS_ELS_KS19_KS19_UHMAC_SHIFT            (21U)
#define ELS_ELS_KS19_KS19_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UHMAC_SHIFT)) & ELS_ELS_KS19_KS19_UHMAC_MASK)

#define ELS_ELS_KS19_KS19_UKWK_MASK              (0x400000U)
#define ELS_ELS_KS19_KS19_UKWK_SHIFT             (22U)
#define ELS_ELS_KS19_KS19_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKWK_SHIFT)) & ELS_ELS_KS19_KS19_UKWK_MASK)

#define ELS_ELS_KS19_KS19_UKUOK_MASK             (0x800000U)
#define ELS_ELS_KS19_KS19_UKUOK_SHIFT            (23U)
#define ELS_ELS_KS19_KS19_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKUOK_SHIFT)) & ELS_ELS_KS19_KS19_UKUOK_MASK)

#define ELS_ELS_KS19_KS19_UTLSPMS_MASK           (0x1000000U)
#define ELS_ELS_KS19_KS19_UTLSPMS_SHIFT          (24U)
#define ELS_ELS_KS19_KS19_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UTLSPMS_SHIFT)) & ELS_ELS_KS19_KS19_UTLSPMS_MASK)

#define ELS_ELS_KS19_KS19_UTLSMS_MASK            (0x2000000U)
#define ELS_ELS_KS19_KS19_UTLSMS_SHIFT           (25U)
#define ELS_ELS_KS19_KS19_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UTLSMS_SHIFT)) & ELS_ELS_KS19_KS19_UTLSMS_MASK)

#define ELS_ELS_KS19_KS19_UKGSRC_MASK            (0x4000000U)
#define ELS_ELS_KS19_KS19_UKGSRC_SHIFT           (26U)
#define ELS_ELS_KS19_KS19_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKGSRC_SHIFT)) & ELS_ELS_KS19_KS19_UKGSRC_MASK)

#define ELS_ELS_KS19_KS19_UHWO_MASK              (0x8000000U)
#define ELS_ELS_KS19_KS19_UHWO_SHIFT             (27U)
#define ELS_ELS_KS19_KS19_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UHWO_SHIFT)) & ELS_ELS_KS19_KS19_UHWO_MASK)

#define ELS_ELS_KS19_KS19_UWRPOK_MASK            (0x10000000U)
#define ELS_ELS_KS19_KS19_UWRPOK_SHIFT           (28U)
#define ELS_ELS_KS19_KS19_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UWRPOK_SHIFT)) & ELS_ELS_KS19_KS19_UWRPOK_MASK)

#define ELS_ELS_KS19_KS19_UDUK_MASK              (0x20000000U)
#define ELS_ELS_KS19_KS19_UDUK_SHIFT             (29U)
#define ELS_ELS_KS19_KS19_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UDUK_SHIFT)) & ELS_ELS_KS19_KS19_UDUK_MASK)

#define ELS_ELS_KS19_KS19_UPPROT_MASK            (0xC0000000U)
#define ELS_ELS_KS19_KS19_UPPROT_SHIFT           (30U)
#define ELS_ELS_KS19_KS19_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UPPROT_SHIFT)) & ELS_ELS_KS19_KS19_UPPROT_MASK)
/*! @} */

/*! @name RESERVED_LA4 - Reserved LA4 */
/*! @{ */

#define ELS_RESERVED_LA4_RESERVED31_MASK         (0xFFFFFFFFU)
#define ELS_RESERVED_LA4_RESERVED31_SHIFT        (0U)
/*! reserved31 - should be 0 */
#define ELS_RESERVED_LA4_RESERVED31(x)           (((uint32_t)(((uint32_t)(x)) << ELS_RESERVED_LA4_RESERVED31_SHIFT)) & ELS_RESERVED_LA4_RESERVED31_MASK)
/*! @} */

/*! @name RESERVED_LA8 - Reserved LA8 */
/*! @{ */

#define ELS_RESERVED_LA8_RESERVED31_MASK         (0xFFFFFFFFU)
#define ELS_RESERVED_LA8_RESERVED31_SHIFT        (0U)
/*! reserved31 - should be 0x2d */
#define ELS_RESERVED_LA8_RESERVED31(x)           (((uint32_t)(((uint32_t)(x)) << ELS_RESERVED_LA8_RESERVED31_SHIFT)) & ELS_RESERVED_LA8_RESERVED31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ELS_Register_Masks */


/* ELS - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ELS base address */
  #define ELS_BASE                                 (0x50190000u)
  /** Peripheral ELS base address */
  #define ELS_BASE_NS                              (0x40190000u)
  /** Peripheral ELS base pointer */
  #define ELS                                      ((ELS_Type *)ELS_BASE)
  /** Peripheral ELS base pointer */
  #define ELS_NS                                   ((ELS_Type *)ELS_BASE_NS)
  /** Peripheral ELS_ALIAS1 base address */
  #define ELS_ALIAS1_BASE                          (0x50191000u)
  /** Peripheral ELS_ALIAS1 base address */
  #define ELS_ALIAS1_BASE_NS                       (0x40191000u)
  /** Peripheral ELS_ALIAS1 base pointer */
  #define ELS_ALIAS1                               ((ELS_Type *)ELS_ALIAS1_BASE)
  /** Peripheral ELS_ALIAS1 base pointer */
  #define ELS_ALIAS1_NS                            ((ELS_Type *)ELS_ALIAS1_BASE_NS)
  /** Peripheral ELS_ALIAS2 base address */
  #define ELS_ALIAS2_BASE                          (0x50192000u)
  /** Peripheral ELS_ALIAS2 base address */
  #define ELS_ALIAS2_BASE_NS                       (0x40192000u)
  /** Peripheral ELS_ALIAS2 base pointer */
  #define ELS_ALIAS2                               ((ELS_Type *)ELS_ALIAS2_BASE)
  /** Peripheral ELS_ALIAS2 base pointer */
  #define ELS_ALIAS2_NS                            ((ELS_Type *)ELS_ALIAS2_BASE_NS)
  /** Peripheral ELS_ALIAS3 base address */
  #define ELS_ALIAS3_BASE                          (0x50193000u)
  /** Peripheral ELS_ALIAS3 base address */
  #define ELS_ALIAS3_BASE_NS                       (0x40193000u)
  /** Peripheral ELS_ALIAS3 base pointer */
  #define ELS_ALIAS3                               ((ELS_Type *)ELS_ALIAS3_BASE)
  /** Peripheral ELS_ALIAS3 base pointer */
  #define ELS_ALIAS3_NS                            ((ELS_Type *)ELS_ALIAS3_BASE_NS)
  /** Array initializer of ELS peripheral base addresses */
  #define ELS_BASE_ADDRS                           { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE }
  /** Array initializer of ELS peripheral base pointers */
  #define ELS_BASE_PTRS                            { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 }
  /** Array initializer of ELS peripheral base addresses */
  #define ELS_BASE_ADDRS_NS                        { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS }
  /** Array initializer of ELS peripheral base pointers */
  #define ELS_BASE_PTRS_NS                         { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS }
#else
  /** Peripheral ELS base address */
  #define ELS_BASE                                 (0x40190000u)
  /** Peripheral ELS base pointer */
  #define ELS                                      ((ELS_Type *)ELS_BASE)
  /** Peripheral ELS_ALIAS1 base address */
  #define ELS_ALIAS1_BASE                          (0x40191000u)
  /** Peripheral ELS_ALIAS1 base pointer */
  #define ELS_ALIAS1                               ((ELS_Type *)ELS_ALIAS1_BASE)
  /** Peripheral ELS_ALIAS2 base address */
  #define ELS_ALIAS2_BASE                          (0x40192000u)
  /** Peripheral ELS_ALIAS2 base pointer */
  #define ELS_ALIAS2                               ((ELS_Type *)ELS_ALIAS2_BASE)
  /** Peripheral ELS_ALIAS3 base address */
  #define ELS_ALIAS3_BASE                          (0x40193000u)
  /** Peripheral ELS_ALIAS3 base pointer */
  #define ELS_ALIAS3                               ((ELS_Type *)ELS_ALIAS3_BASE)
  /** Array initializer of ELS peripheral base addresses */
  #define ELS_BASE_ADDRS                           { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE }
  /** Array initializer of ELS peripheral base pointers */
  #define ELS_BASE_PTRS                            { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 }
#endif

/*!
 * @}
 */ /* end of group ELS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
 * @{
 */

/** FLEXIO - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t CTRL;                              /**< FLEXIO Control, offset: 0x8 */
  __I  uint32_t PIN;                               /**< Pin State, offset: 0xC */
  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status, offset: 0x10 */
  __IO uint32_t SHIFTERR;                          /**< Shifter Error, offset: 0x14 */
  __IO uint32_t TIMSTAT;                           /**< Timer Status Flag, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable, offset: 0x28 */
       uint8_t RESERVED_1[4];
  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
       uint8_t RESERVED_3[4];
  __IO uint32_t SHIFTSTATE;                        /**< Shifter State, offset: 0x40 */
       uint8_t RESERVED_4[4];
  __IO uint32_t TRGSTAT;                           /**< Trigger Status, offset: 0x48 */
  __IO uint32_t TRIGIEN;                           /**< External Trigger Interrupt Enable, offset: 0x4C */
  __IO uint32_t PINSTAT;                           /**< Pin Status, offset: 0x50 */
  __IO uint32_t PINIEN;                            /**< Pin Interrupt Enable, offset: 0x54 */
  __IO uint32_t PINREN;                            /**< Pin Rising Edge Enable, offset: 0x58 */
  __IO uint32_t PINFEN;                            /**< Pin Falling Edge Enable, offset: 0x5C */
  __IO uint32_t PINOUTD;                           /**< Pin Output Data, offset: 0x60 */
  __IO uint32_t PINOUTE;                           /**< Pin Output Enable, offset: 0x64 */
  __IO uint32_t PINOUTDIS;                         /**< Pin Output Disable, offset: 0x68 */
  __IO uint32_t PINOUTCLR;                         /**< Pin Output Clear, offset: 0x6C */
  __IO uint32_t PINOUTSET;                         /**< Pin Output Set, offset: 0x70 */
  __IO uint32_t PINOUTTOG;                         /**< Pin Output Toggle, offset: 0x74 */
       uint8_t RESERVED_5[8];
  __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_6[96];
  __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_7[224];
  __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_8[96];
  __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */
       uint8_t RESERVED_9[96];
  __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_10[96];
  __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */
       uint8_t RESERVED_11[96];
  __IO uint32_t TIMCTL[8];                         /**< Timer Control, array offset: 0x400, array step: 0x4 */
       uint8_t RESERVED_12[96];
  __IO uint32_t TIMCFG[8];                         /**< Timer Configuration, array offset: 0x480, array step: 0x4 */
       uint8_t RESERVED_13[96];
  __IO uint32_t TIMCMP[8];                         /**< Timer Compare, array offset: 0x500, array step: 0x4 */
       uint8_t RESERVED_14[352];
  __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */
       uint8_t RESERVED_15[96];
  __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */
       uint8_t RESERVED_16[96];
  __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */
       uint8_t RESERVED_17[96];
  __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */
       uint8_t RESERVED_18[96];
  __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */
       uint8_t RESERVED_19[96];
  __IO uint32_t SHIFTBUFHBS[8];                    /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */
} FLEXIO_Type;

/* ----------------------------------------------------------------------------
   -- FLEXIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
#define FLEXIO_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard features implemented
 *  0b0000000000000001..State, logic, and parallel modes supported
 *  0b0000000000000010..Pin control registers supported
 *  0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported
 */
#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)

#define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
#define FLEXIO_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number */
#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)

#define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
#define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number */
#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
#define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
/*! SHIFTER - Shifter Number */
#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)

#define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
#define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
/*! TIMER - Timer Number */
#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)

#define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
#define FLEXIO_PARAM_PIN_SHIFT                   (16U)
/*! PIN - Pin Number */
#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)

#define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
#define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
/*! TRIGGER - Trigger Number */
#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
/*! @} */

/*! @name CTRL - FLEXIO Control */
/*! @{ */

#define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
#define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
/*! FLEXEN - FLEXIO Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)

#define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
#define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
/*! SWRST - Software Reset
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)

#define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
#define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
/*! FASTACC - Fast Access
 *  0b0..Normal
 *  0b1..Fast
 */
#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)

#define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
#define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
/*! DBGE - Debug Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)

#define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
#define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
/*! DOZEN - Doze Enable
 *  0b0..Enable
 *  0b1..Disable
 */
#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
/*! @} */

/*! @name PIN - Pin State */
/*! @{ */

#define FLEXIO_PIN_PDI_MASK                      (0xFFFFU)
#define FLEXIO_PIN_PDI_SHIFT                     (0U)
/*! PDI - Pin Data Input */
#define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
/*! @} */

/*! @name SHIFTSTAT - Shifter Status */
/*! @{ */

#define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
#define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
/*! SSF - Shifter Status Flag
 *  0b00000000..Clear
 *  0b00000001..Set
 *  0b00000000..No effect
 *  0b00000001..Clear the flag
 */
#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
/*! @} */

/*! @name SHIFTERR - Shifter Error */
/*! @{ */

#define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
#define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
/*! SEF - Shifter Error Flag
 *  0b00000000..Clear
 *  0b00000001..Set
 *  0b00000000..No effect
 *  0b00000001..Clear the flag
 */
#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
/*! @} */

/*! @name TIMSTAT - Timer Status Flag */
/*! @{ */

#define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
#define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
/*! TSF - Timer Status Flag
 *  0b00000000..Clear
 *  0b00000001..Set
 *  0b00000000..No effect
 *  0b00000001..Clear the flag
 */
#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
/*! @} */

/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
/*! @{ */

#define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
/*! SSIE - Shifter Status Interrupt Enable */
#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
/*! @} */

/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
/*! @{ */

#define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
/*! SEIE - Shifter Error Interrupt Enable */
#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
/*! @} */

/*! @name TIMIEN - Timer Interrupt Enable */
/*! @{ */

#define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
#define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
/*! TEIE - Timer Status Interrupt Enable */
#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
/*! @} */

/*! @name SHIFTSDEN - Shifter Status DMA Enable */
/*! @{ */

#define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
/*! SSDE - Shifter Status DMA Enable */
#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
/*! @} */

/*! @name TIMERSDEN - Timer Status DMA Enable */
/*! @{ */

#define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
#define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
/*! TSDE - Timer Status DMA Enable */
#define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
/*! @} */

/*! @name SHIFTSTATE - Shifter State */
/*! @{ */

#define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
#define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
/*! STATE - Current State Pointer */
#define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
/*! @} */

/*! @name TRGSTAT - Trigger Status */
/*! @{ */

#define FLEXIO_TRGSTAT_ETSF_MASK                 (0xFU)
#define FLEXIO_TRGSTAT_ETSF_SHIFT                (0U)
/*! ETSF - External Trigger Status Flag
 *  0b0000..Clear
 *  0b0001..Set
 *  0b0000..No effect
 *  0b0001..Clear the flag
 */
#define FLEXIO_TRGSTAT_ETSF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK)
/*! @} */

/*! @name TRIGIEN - External Trigger Interrupt Enable */
/*! @{ */

#define FLEXIO_TRIGIEN_TRIE_MASK                 (0xFU)
#define FLEXIO_TRIGIEN_TRIE_SHIFT                (0U)
/*! TRIE - External Trigger Interrupt Enable */
#define FLEXIO_TRIGIEN_TRIE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK)
/*! @} */

/*! @name PINSTAT - Pin Status */
/*! @{ */

#define FLEXIO_PINSTAT_PSF_MASK                  (0xFFFFU)
#define FLEXIO_PINSTAT_PSF_SHIFT                 (0U)
/*! PSF - Pin Status Flag
 *  0b0000000000000000..Clear
 *  0b0000000000000001..Set
 *  0b0000000000000000..No effect
 *  0b0000000000000001..Clear the flag
 */
#define FLEXIO_PINSTAT_PSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK)
/*! @} */

/*! @name PINIEN - Pin Interrupt Enable */
/*! @{ */

#define FLEXIO_PINIEN_PSIE_MASK                  (0xFFFFU)
#define FLEXIO_PINIEN_PSIE_SHIFT                 (0U)
/*! PSIE - Pin Status Interrupt Enable */
#define FLEXIO_PINIEN_PSIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK)
/*! @} */

/*! @name PINREN - Pin Rising Edge Enable */
/*! @{ */

#define FLEXIO_PINREN_PRE_MASK                   (0xFFFFU)
#define FLEXIO_PINREN_PRE_SHIFT                  (0U)
/*! PRE - Pin Rising Edge */
#define FLEXIO_PINREN_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK)
/*! @} */

/*! @name PINFEN - Pin Falling Edge Enable */
/*! @{ */

#define FLEXIO_PINFEN_PFE_MASK                   (0xFFFFU)
#define FLEXIO_PINFEN_PFE_SHIFT                  (0U)
/*! PFE - Pin Falling Edge */
#define FLEXIO_PINFEN_PFE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK)
/*! @} */

/*! @name PINOUTD - Pin Output Data */
/*! @{ */

#define FLEXIO_PINOUTD_OUTD_MASK                 (0xFFFFU)
#define FLEXIO_PINOUTD_OUTD_SHIFT                (0U)
/*! OUTD - Output Data */
#define FLEXIO_PINOUTD_OUTD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK)
/*! @} */

/*! @name PINOUTE - Pin Output Enable */
/*! @{ */

#define FLEXIO_PINOUTE_OUTE_MASK                 (0xFFFFU)
#define FLEXIO_PINOUTE_OUTE_SHIFT                (0U)
/*! OUTE - Output Enable */
#define FLEXIO_PINOUTE_OUTE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK)
/*! @} */

/*! @name PINOUTDIS - Pin Output Disable */
/*! @{ */

#define FLEXIO_PINOUTDIS_OUTDIS_MASK             (0xFFFFU)
#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT            (0U)
/*! OUTDIS - Output Disable */
#define FLEXIO_PINOUTDIS_OUTDIS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK)
/*! @} */

/*! @name PINOUTCLR - Pin Output Clear */
/*! @{ */

#define FLEXIO_PINOUTCLR_OUTCLR_MASK             (0xFFFFU)
#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT            (0U)
/*! OUTCLR - Output Clear */
#define FLEXIO_PINOUTCLR_OUTCLR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK)
/*! @} */

/*! @name PINOUTSET - Pin Output Set */
/*! @{ */

#define FLEXIO_PINOUTSET_OUTSET_MASK             (0xFFFFU)
#define FLEXIO_PINOUTSET_OUTSET_SHIFT            (0U)
/*! OUTSET - Output Set */
#define FLEXIO_PINOUTSET_OUTSET(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK)
/*! @} */

/*! @name PINOUTTOG - Pin Output Toggle */
/*! @{ */

#define FLEXIO_PINOUTTOG_OUTTOG_MASK             (0xFFFFU)
#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT            (0U)
/*! OUTTOG - Output Toggle */
#define FLEXIO_PINOUTTOG_OUTTOG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK)
/*! @} */

/*! @name SHIFTCTL - Shifter Control */
/*! @{ */

#define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
#define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
/*! SMOD - Shifter Mode
 *  0b000..Disable
 *  0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer
 *  0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer
 *  0b011..Reserved
 *  0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer
 *  0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents
 *  0b110..State mode; SHIFTBUF contents store programmable state attributes
 *  0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table
 */
#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)

#define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
/*! PINPOL - Shifter Pin Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)

#define FLEXIO_SHIFTCTL_PINSEL_MASK              (0xF00U)
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
/*! PINSEL - Shifter Pin Select */
#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)

#define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
/*! PINCFG - Shifter Pin Configuration
 *  0b00..Shifter pin output disabled
 *  0b01..Shifter pin open-drain or bidirectional output enable
 *  0b10..Shifter pin bidirectional output data
 *  0b11..Shifter pin output
 */
#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)

#define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
/*! TIMPOL - Timer Polarity
 *  0b0..Positive edge
 *  0b1..Negative edge
 */
#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)

#define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
/*! TIMSEL - Timer Select */
#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTCTL */
#define FLEXIO_SHIFTCTL_COUNT                    (8U)

/*! @name SHIFTCFG - Shifter Configuration */
/*! @{ */

#define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
#define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
/*! SSTART - Shifter Start
 *  0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable
 *  0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift
 *  0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0,
 *        Receiver and Match Store modes set error flag
 *  0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1,
 *        Receiver and Match Store modes set error flag
 */
#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)

#define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
/*! SSTOP - Shifter Stop
 *  0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes
 *  0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition,
 *        Receiver and Match Store modes store receive data on the configured shift edge
 *  0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match
 *        Store modes set error flag (when timer is in stop condition, these modes also store receive data on the
 *        configured shift edge)
 *  0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match
 *        Store modes set error flag (when timer is in stop condition, these modes also store receive data on the
 *        configured shift edge)
 */
#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)

#define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
#define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
/*! INSRC - Input Source
 *  0b0..Pin
 *  0b1..Shifter n+1 output
 */
#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)

#define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
#define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
/*! LATST - Late Store
 *  0b0..Store the pre-shift register state
 *  0b1..Store the post-shift register state
 */
#define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)

#define FLEXIO_SHIFTCFG_SSIZE_MASK               (0x1000U)
#define FLEXIO_SHIFTCFG_SSIZE_SHIFT              (12U)
/*! SSIZE - Shifter Size
 *  0b0..32-bit
 *  0b1..24-bit
 */
#define FLEXIO_SHIFTCFG_SSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK)

#define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0xF0000U)
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
/*! PWIDTH - Parallel Width */
#define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTCFG */
#define FLEXIO_SHIFTCFG_COUNT                    (8U)

/*! @name SHIFTBUF - Shifter Buffer */
/*! @{ */

#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
/*! SHIFTBUF - Shift Buffer */
#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUF */
#define FLEXIO_SHIFTBUF_COUNT                    (8U)

/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
/*! SHIFTBUFBIS - Shift Buffer */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBIS */
#define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)

/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
/*! SHIFTBUFBYS - Shift Buffer */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBYS */
#define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)

/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
/*! SHIFTBUFBBS - Shift Buffer */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBBS */
#define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)

/*! @name TIMCTL - Timer Control */
/*! @{ */

#define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
#define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
/*! TIMOD - Timer Mode
 *  0b000..Timer disabled
 *  0b001..Dual 8-bit counters baud mode
 *  0b010..Dual 8-bit counters PWM high mode
 *  0b011..Single 16-bit counter mode
 *  0b100..Single 16-bit counter disable mode
 *  0b101..Dual 8-bit counters word mode
 *  0b110..Dual 8-bit counters PWM low mode
 *  0b111..Single 16-bit input capture mode
 */
#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)

#define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
#define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
/*! ONETIM - Timer One Time Operation
 *  0b0..Generate the timer enable event as normal
 *  0b1..Block the timer enable event unless the timer status flag is clear
 */
#define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)

#define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
#define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
/*! PININS - Timer Pin Input Select
 *  0b0..PINSEL selects timer pin input and output
 *  0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL
 */
#define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)

#define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
#define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
/*! PINPOL - Timer Pin Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)

#define FLEXIO_TIMCTL_PINSEL_MASK                (0xF00U)
#define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
/*! PINSEL - Timer Pin Select */
#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)

#define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
#define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
/*! PINCFG - Timer Pin Configuration
 *  0b00..Timer pin output disabled
 *  0b01..Timer pin open-drain or bidirectional output enable
 *  0b10..Timer pin bidirectional output data
 *  0b11..Timer pin output
 */
#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)

#define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
#define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
/*! TRGSRC - Trigger Source
 *  0b0..External
 *  0b1..Internal
 */
#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)

#define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
#define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
/*! TRGPOL - Trigger Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)

#define FLEXIO_TIMCTL_TRGSEL_MASK                (0x1F000000U)
#define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
/*! TRGSEL - Trigger Select */
#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
/*! @} */

/* The count of FLEXIO_TIMCTL */
#define FLEXIO_TIMCTL_COUNT                      (8U)

/*! @name TIMCFG - Timer Configuration */
/*! @{ */

#define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
#define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
/*! TSTART - Timer Start
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)

#define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
#define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
/*! TSTOP - Timer Stop
 *  0b00..Disabled
 *  0b01..Enabled on timer compare
 *  0b10..Enabled on timer disable
 *  0b11..Enabled on timer compare and timer disable
 */
#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)

#define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
#define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
/*! TIMENA - Timer Enable
 *  0b000..Timer always enabled
 *  0b001..Timer enabled on timer n-1 enable
 *  0b010..Timer enabled on trigger high
 *  0b011..Timer enabled on trigger high and pin high
 *  0b100..Timer enabled on pin rising edge
 *  0b101..Timer enabled on pin rising edge and trigger high
 *  0b110..Timer enabled on trigger rising edge
 *  0b111..Timer enabled on trigger rising or falling edge
 */
#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)

#define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
#define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
/*! TIMDIS - Timer Disable
 *  0b000..Timer never disabled
 *  0b001..Timer disabled on timer n-1 disable
 *  0b010..Timer disabled on timer compare (upper 8 bits match and decrement)
 *  0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low
 *  0b100..Timer disabled on pin rising or falling edge
 *  0b101..Timer disabled on pin rising or falling edge provided trigger is high
 *  0b110..Timer disabled on trigger falling edge
 *  0b111..Reserved
 */
#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)

#define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
#define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
/*! TIMRST - Timer Reset
 *  0b000..Never reset timer
 *  0b001..Timer reset on timer output high.
 *  0b010..Timer reset on timer pin equal to timer output
 *  0b011..Timer reset on timer trigger equal to timer output
 *  0b100..Timer reset on timer pin rising edge
 *  0b101..Reserved
 *  0b110..Timer reset on trigger rising edge
 *  0b111..Timer reset on trigger rising or falling edge
 */
#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)

#define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
#define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
/*! TIMDEC - Timer Decrement
 *  0b000..Decrement counter on FLEXIO clock; shift clock equals timer output
 *  0b001..Decrement counter on trigger input (both edges); shift clock equals timer output
 *  0b010..Decrement counter on pin input (both edges); shift clock equals pin input
 *  0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input
 *  0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output
 *  0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output
 *  0b110..Decrement counter on pin input (rising edge); shift clock equals pin input
 *  0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input
 */
#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)

#define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
#define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
/*! TIMOUT - Timer Output
 *  0b00..Logic one when enabled; not affected by timer reset
 *  0b01..Logic zero when enabled; not affected by timer reset
 *  0b10..Logic one when enabled and on timer reset
 *  0b11..Logic zero when enabled and on timer reset
 */
#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
/*! @} */

/* The count of FLEXIO_TIMCFG */
#define FLEXIO_TIMCFG_COUNT                      (8U)

/*! @name TIMCMP - Timer Compare */
/*! @{ */

#define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
#define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
/*! CMP - Timer Compare Value */
#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
/*! @} */

/* The count of FLEXIO_TIMCMP */
#define FLEXIO_TIMCMP_COUNT                      (8U)

/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
/*! SHIFTBUFNBS - Shift Buffer */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFNBS */
#define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)

/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
/*! SHIFTBUFHWS - Shift Buffer */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFHWS */
#define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)

/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
/*! SHIFTBUFNIS - Shift Buffer */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFNIS */
#define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)

/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
/*! SHIFTBUFOES - Shift Buffer */
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFOES */
#define FLEXIO_SHIFTBUFOES_COUNT                 (8U)

/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
/*! SHIFTBUFEOS - Shift Buffer */
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFEOS */
#define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)

/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */
/*! @{ */

#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT     (0U)
/*! SHIFTBUFHBS - Shift Buffer */
#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFHBS */
#define FLEXIO_SHIFTBUFHBS_COUNT                 (8U)


/*!
 * @}
 */ /* end of group FLEXIO_Register_Masks */


/* FLEXIO - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FLEXIO base address */
  #define FLEXIO_BASE                              (0x50416000u)
  /** Peripheral FLEXIO base address */
  #define FLEXIO_BASE_NS                           (0x40416000u)
  /** Peripheral FLEXIO base pointer */
  #define FLEXIO                                   ((FLEXIO_Type *)FLEXIO_BASE)
  /** Peripheral FLEXIO base pointer */
  #define FLEXIO_NS                                ((FLEXIO_Type *)FLEXIO_BASE_NS)
  /** Array initializer of FLEXIO peripheral base addresses */
  #define FLEXIO_BASE_ADDRS                        { FLEXIO_BASE }
  /** Array initializer of FLEXIO peripheral base pointers */
  #define FLEXIO_BASE_PTRS                         { FLEXIO }
  /** Array initializer of FLEXIO peripheral base addresses */
  #define FLEXIO_BASE_ADDRS_NS                     { FLEXIO_BASE_NS }
  /** Array initializer of FLEXIO peripheral base pointers */
  #define FLEXIO_BASE_PTRS_NS                      { FLEXIO_NS }
#else
  /** Peripheral FLEXIO base address */
  #define FLEXIO_BASE                              (0x40416000u)
  /** Peripheral FLEXIO base pointer */
  #define FLEXIO                                   ((FLEXIO_Type *)FLEXIO_BASE)
  /** Array initializer of FLEXIO peripheral base addresses */
  #define FLEXIO_BASE_ADDRS                        { FLEXIO_BASE }
  /** Array initializer of FLEXIO peripheral base pointers */
  #define FLEXIO_BASE_PTRS                         { FLEXIO }
#endif
/** Interrupt vectors for the FLEXIO peripheral type */
#define FLEXIO_IRQS                              { FLEXIO_IRQn }

/*!
 * @}
 */ /* end of group FLEXIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FREQME Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer
 * @{
 */

/** FREQME - Register Layout Typedef */
typedef struct {
  union {                                          /* offset: 0x0 */
    __I  uint32_t CTRL_R;                            /**< Control (in Read mode), offset: 0x0 */
    __O  uint32_t CTRL_W;                            /**< Control (in Write mode), offset: 0x0 */
  };
  __IO uint32_t CTRLSTAT;                          /**< Control Status, offset: 0x4 */
  __IO uint32_t MIN;                               /**< Minimum, offset: 0x8 */
  __IO uint32_t MAX;                               /**< Maximum, offset: 0xC */
} FREQME_Type;

/* ----------------------------------------------------------------------------
   -- FREQME Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FREQME_Register_Masks FREQME Register Masks
 * @{
 */

/*! @name CTRL_R - Control (in Read mode) */
/*! @{ */

#define FREQME_CTRL_R_RESULT_MASK                (0x7FFFFFFFU)
#define FREQME_CTRL_R_RESULT_SHIFT               (0U)
#define FREQME_CTRL_R_RESULT(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK)

#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK   (0x80000000U)
#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT  (31U)
/*! MEASURE_IN_PROGRESS - Measurement In Progress
 *  0b0..Complete
 *  0b1..In progress
 */
#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK)
/*! @} */

/*! @name CTRL_W - Control (in Write mode) */
/*! @{ */

#define FREQME_CTRL_W_REF_SCALE_MASK             (0x1FU)
#define FREQME_CTRL_W_REF_SCALE_SHIFT            (0U)
/*! REF_SCALE - Reference Clock Scaling Factor */
#define FREQME_CTRL_W_REF_SCALE(x)               (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK)

#define FREQME_CTRL_W_PULSE_MODE_MASK            (0x100U)
#define FREQME_CTRL_W_PULSE_MODE_SHIFT           (8U)
/*! PULSE_MODE - Pulse Width Measurement Mode Select
 *  0b0..Frequency Measurement mode
 *  0b1..Pulse Width Measurement mode
 */
#define FREQME_CTRL_W_PULSE_MODE(x)              (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK)

#define FREQME_CTRL_W_PULSE_POL_MASK             (0x200U)
#define FREQME_CTRL_W_PULSE_POL_SHIFT            (9U)
/*! PULSE_POL - Pulse Polarity
 *  0b0..High period
 *  0b1..Low period
 */
#define FREQME_CTRL_W_PULSE_POL(x)               (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK)

#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK         (0x1000U)
#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT        (12U)
/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FREQME_CTRL_W_LT_MIN_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK)

#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK         (0x2000U)
#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT        (13U)
/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FREQME_CTRL_W_GT_MAX_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK)

#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK   (0x4000U)
#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT  (14U)
/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FREQME_CTRL_W_RESULT_READY_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK)

#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK    (0x40000000U)
#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT   (30U)
/*! CONTINUOUS_MODE_EN - Continuous Mode Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x)      (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK)

#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK   (0x80000000U)
#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT  (31U)
/*! MEASURE_IN_PROGRESS - Measurement In Progress
 *  0b0..Terminates measurement
 *  0b1..Initiates measurement
 */
#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK)
/*! @} */

/*! @name CTRLSTAT - Control Status */
/*! @{ */

#define FREQME_CTRLSTAT_REF_SCALE_MASK           (0x1FU)
#define FREQME_CTRLSTAT_REF_SCALE_SHIFT          (0U)
/*! REF_SCALE - Reference Scale */
#define FREQME_CTRLSTAT_REF_SCALE(x)             (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK)

#define FREQME_CTRLSTAT_PULSE_MODE_MASK          (0x100U)
#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT         (8U)
/*! PULSE_MODE - Pulse Mode
 *  0b0..Frequency Measurement mode
 *  0b1..Pulse Width Measurement mode
 */
#define FREQME_CTRLSTAT_PULSE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK)

#define FREQME_CTRLSTAT_PULSE_POL_MASK           (0x200U)
#define FREQME_CTRLSTAT_PULSE_POL_SHIFT          (9U)
/*! PULSE_POL - Pulse Polarity
 *  0b0..High period
 *  0b1..Low period
 */
#define FREQME_CTRLSTAT_PULSE_POL(x)             (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK)

#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK       (0x1000U)
#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT      (12U)
/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK)

#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK       (0x2000U)
#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT      (13U)
/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK)

#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U)
#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U)
/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK)

#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK         (0x1000000U)
#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT        (24U)
/*! LT_MIN_STAT - Less Than Minimum Results Status
 *  0b0..Greater than MIN[MIN_VALUE]
 *  0b1..Less than MIN[MIN_VALUE]
 */
#define FREQME_CTRLSTAT_LT_MIN_STAT(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK)

#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK         (0x2000000U)
#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT        (25U)
/*! GT_MAX_STAT - Greater Than Maximum Result Status
 *  0b0..Less than MAX[MAX_VALUE]
 *  0b1..Greater than MAX[MAX_VALUE]
 */
#define FREQME_CTRLSTAT_GT_MAX_STAT(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK)

#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK   (0x4000000U)
#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT  (26U)
/*! RESULT_READY_STAT - Result Ready Status
 *  0b0..Not complete
 *  0b1..Complete
 */
#define FREQME_CTRLSTAT_RESULT_READY_STAT(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK)

#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK  (0x40000000U)
#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U)
/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x)    (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK)

#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U)
#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U)
/*! MEASURE_IN_PROGRESS - Measurement in Progress Status
 *  0b0..Not in progress
 *  0b1..In progress
 */
#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x)   (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK)
/*! @} */

/*! @name MIN - Minimum */
/*! @{ */

#define FREQME_MIN_MIN_VALUE_MASK                (0x7FFFFFFFU)
#define FREQME_MIN_MIN_VALUE_SHIFT               (0U)
/*! MIN_VALUE - Minimum Value */
#define FREQME_MIN_MIN_VALUE(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK)
/*! @} */

/*! @name MAX - Maximum */
/*! @{ */

#define FREQME_MAX_MAX_VALUE_MASK                (0x7FFFFFFFU)
#define FREQME_MAX_MAX_VALUE_SHIFT               (0U)
/*! MAX_VALUE - Maximum Value */
#define FREQME_MAX_MAX_VALUE(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FREQME_Register_Masks */


/* FREQME - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FREQME base address */
  #define FREQME_BASE                              (0x50023000u)
  /** Peripheral FREQME base address */
  #define FREQME_BASE_NS                           (0x40023000u)
  /** Peripheral FREQME base pointer */
  #define FREQME                                   ((FREQME_Type *)FREQME_BASE)
  /** Peripheral FREQME base pointer */
  #define FREQME_NS                                ((FREQME_Type *)FREQME_BASE_NS)
  /** Array initializer of FREQME peripheral base addresses */
  #define FREQME_BASE_ADDRS                        { FREQME_BASE }
  /** Array initializer of FREQME peripheral base pointers */
  #define FREQME_BASE_PTRS                         { FREQME }
  /** Array initializer of FREQME peripheral base addresses */
  #define FREQME_BASE_ADDRS_NS                     { FREQME_BASE_NS }
  /** Array initializer of FREQME peripheral base pointers */
  #define FREQME_BASE_PTRS_NS                      { FREQME_NS }
#else
  /** Peripheral FREQME base address */
  #define FREQME_BASE                              (0x40023000u)
  /** Peripheral FREQME base pointer */
  #define FREQME                                   ((FREQME_Type *)FREQME_BASE)
  /** Array initializer of FREQME peripheral base addresses */
  #define FREQME_BASE_ADDRS                        { FREQME_BASE }
  /** Array initializer of FREQME peripheral base pointers */
  #define FREQME_BASE_PTRS                         { FREQME }
#endif

/*!
 * @}
 */ /* end of group FREQME_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FRO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FRO_Peripheral_Access_Layer FRO Peripheral Access Layer
 * @{
 */

/** FRO - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[512];
  struct {                                         /* offset: 0x200 */
    __IO uint32_t RW;                                /**< Control Status, offset: 0x200 */
    __IO uint32_t SET;                               /**< Control Status, offset: 0x204 */
    __IO uint32_t CLR;                               /**< Control Status, offset: 0x208 */
    __IO uint32_t TOG;                               /**< Control Status, offset: 0x20C */
  } CSR;
  struct {                                         /* offset: 0x210 */
    __IO uint32_t RW;                                /**< Trim Configuration 1, offset: 0x210 */
    __IO uint32_t SET;                               /**< Trim Configuration 1, offset: 0x214 */
    __IO uint32_t CLR;                               /**< Trim Configuration 1, offset: 0x218 */
    __IO uint32_t TOG;                               /**< Trim Configuration 1, offset: 0x21C */
  } CNFG1;
  struct {                                         /* offset: 0x220 */
    __IO uint32_t RW;                                /**< Trim Configuration 2, offset: 0x220 */
    __IO uint32_t SET;                               /**< Trim Configuration 2, offset: 0x224 */
    __IO uint32_t CLR;                               /**< Trim Configuration 2, offset: 0x228 */
    __IO uint32_t TOG;                               /**< Trim Configuration 2, offset: 0x22C */
  } CNFG2;
       uint8_t RESERVED_1[16];
  struct {                                         /* offset: 0x240 */
    __IO uint32_t RW;                                /**< FRO Trim, offset: 0x240 */
    __IO uint32_t SET;                               /**< FRO Trim, offset: 0x244 */
    __IO uint32_t CLR;                               /**< FRO Trim, offset: 0x248 */
    __IO uint32_t TOG;                               /**< FRO Trim, offset: 0x24C */
  } FROTRIM;
  struct {                                         /* offset: 0x250 */
    __IO uint32_t RW;                                /**< FRO Expected Trim Count, offset: 0x250 */
    __IO uint32_t SET;                               /**< FRO Expected Trim Count, offset: 0x254 */
    __IO uint32_t CLR;                               /**< FRO Expected Trim Count, offset: 0x258 */
    __IO uint32_t TOG;                               /**< FRO Expected Trim Count, offset: 0x25C */
  } TEXPCNT;
  struct {                                         /* offset: 0x260 */
    __I  uint32_t RW;                                /**< FRO Auto Tune Trim, offset: 0x260 */
    __I  uint32_t SET;                               /**< FRO Auto Tune Trim, offset: 0x264 */
    __I  uint32_t CLR;                               /**< FRO Auto Tune Trim, offset: 0x268 */
    __I  uint32_t TOG;                               /**< FRO Auto Tune Trim, offset: 0x26C */
  } AUTOTRIM;
  struct {                                         /* offset: 0x270 */
    __I  uint32_t RW;                                /**< FRO Trim Count, offset: 0x270 */
    __I  uint32_t SET;                               /**< FRO Trim Count, offset: 0x274 */
    __I  uint32_t CLR;                               /**< FRO Trim Count, offset: 0x278 */
    __I  uint32_t TOG;                               /**< FRO Trim Count, offset: 0x27C */
  } TRIMCNT;
} FRO_Type;

/* ----------------------------------------------------------------------------
   -- FRO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FRO_Register_Masks FRO Register Masks
 * @{
 */

/*! @name CSR - Control Status */
/*! @{ */

#define FRO_CSR_FROEN_MASK                       (0x1U)
#define FRO_CSR_FROEN_SHIFT                      (0U)
/*! FROEN - FRO Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FRO_CSR_FROEN(x)                         (((uint32_t)(((uint32_t)(x)) << FRO_CSR_FROEN_SHIFT)) & FRO_CSR_FROEN_MASK)

#define FRO_CSR_TREN_MASK                        (0x10U)
#define FRO_CSR_TREN_SHIFT                       (4U)
/*! TREN - FRO Trim Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FRO_CSR_TREN(x)                          (((uint32_t)(((uint32_t)(x)) << FRO_CSR_TREN_SHIFT)) & FRO_CSR_TREN_MASK)

#define FRO_CSR_TRUPEN_MASK                      (0x20U)
#define FRO_CSR_TRUPEN_SHIFT                     (5U)
/*! TRUPEN - FRO Autotrim Update Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FRO_CSR_TRUPEN(x)                        (((uint32_t)(((uint32_t)(x)) << FRO_CSR_TRUPEN_SHIFT)) & FRO_CSR_TRUPEN_MASK)

#define FRO_CSR_COARSEN_MASK                     (0x40U)
#define FRO_CSR_COARSEN_SHIFT                    (6U)
/*! COARSEN - Coarse Trim Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FRO_CSR_COARSEN(x)                       (((uint32_t)(((uint32_t)(x)) << FRO_CSR_COARSEN_SHIFT)) & FRO_CSR_COARSEN_MASK)

#define FRO_CSR_TUNEONCE_MASK                    (0x80U)
#define FRO_CSR_TUNEONCE_SHIFT                   (7U)
/*! TUNEONCE - Tune Once Control */
#define FRO_CSR_TUNEONCE(x)                      (((uint32_t)(((uint32_t)(x)) << FRO_CSR_TUNEONCE_SHIFT)) & FRO_CSR_TUNEONCE_MASK)

#define FRO_CSR_CLKGATE_MASK                     (0x1F00U)
#define FRO_CSR_CLKGATE_SHIFT                    (8U)
/*! CLKGATE - FRO Clock Enable
 *  0bxxxx0..Disables FRO divider 1 clock
 *  0bxxxx1..Enables FRO divider 1 clock
 *  0bxxx0x..Disables FRO divider 2 clock
 *  0bxxx1x..Enables FRO divider 2 clock
 *  0bxx0xx..Disables FRO divider 3 clock
 *  0bxx1xx..Enables FRO divider 3 clock
 *  0bx0xxx..Disables FRO divider 6 clock
 *  0bx1xxx..Enables FRO divider 6 clock
 *  0b0xxxx..Disables FRO divider 8 clock
 *  0b1xxxx..Enables FRO divider 8 clock
 */
#define FRO_CSR_CLKGATE(x)                       (((uint32_t)(((uint32_t)(x)) << FRO_CSR_CLKGATE_SHIFT)) & FRO_CSR_CLKGATE_MASK)

#define FRO_CSR_LOL_ERR_MASK                     (0x10000U)
#define FRO_CSR_LOL_ERR_SHIFT                    (16U)
/*! LOL_ERR - Loss-of-Lock Error Flag
 *  0b0..Not detected
 *  0b1..Detected
 */
#define FRO_CSR_LOL_ERR(x)                       (((uint32_t)(((uint32_t)(x)) << FRO_CSR_LOL_ERR_SHIFT)) & FRO_CSR_LOL_ERR_MASK)

#define FRO_CSR_TUNE_ERR_MASK                    (0x20000U)
#define FRO_CSR_TUNE_ERR_SHIFT                   (17U)
/*! TUNE_ERR - Tune Error Flag
 *  0b0..Not detected
 *  0b1..Detected
 */
#define FRO_CSR_TUNE_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << FRO_CSR_TUNE_ERR_SHIFT)) & FRO_CSR_TUNE_ERR_MASK)

#define FRO_CSR_TRUPREQ_MASK                     (0x40000U)
#define FRO_CSR_TRUPREQ_SHIFT                    (18U)
/*! TRUPREQ - Trim Update Request Flag
 *  0b0..Not detected
 *  0b1..Detected
 */
#define FRO_CSR_TRUPREQ(x)                       (((uint32_t)(((uint32_t)(x)) << FRO_CSR_TRUPREQ_SHIFT)) & FRO_CSR_TRUPREQ_MASK)

#define FRO_CSR_TRIM_LOCK_MASK                   (0x1000000U)
#define FRO_CSR_TRIM_LOCK_SHIFT                  (24U)
/*! TRIM_LOCK - FRO Trim Lock Flag
 *  0b0..Not locked
 *  0b1..Locked
 */
#define FRO_CSR_TRIM_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << FRO_CSR_TRIM_LOCK_SHIFT)) & FRO_CSR_TRIM_LOCK_MASK)

#define FRO_CSR_TUNEONCE_DONE_MASK               (0x2000000U)
#define FRO_CSR_TUNEONCE_DONE_SHIFT              (25U)
/*! TUNEONCE_DONE - FRO Tune Once Done Flag
 *  0b0..Not complete
 *  0b1..Complete
 */
#define FRO_CSR_TUNEONCE_DONE(x)                 (((uint32_t)(((uint32_t)(x)) << FRO_CSR_TUNEONCE_DONE_SHIFT)) & FRO_CSR_TUNEONCE_DONE_MASK)
/*! @} */

/*! @name CNFG1 - Trim Configuration 1 */
/*! @{ */

#define FRO_CNFG1_REFDIV_MASK                    (0x7FFU)
#define FRO_CNFG1_REFDIV_SHIFT                   (0U)
/*! REFDIV - OSC Reference Clock Divider */
#define FRO_CNFG1_REFDIV(x)                      (((uint32_t)(((uint32_t)(x)) << FRO_CNFG1_REFDIV_SHIFT)) & FRO_CNFG1_REFDIV_MASK)

#define FRO_CNFG1_LOL_ERR_IE_MASK                (0x1000U)
#define FRO_CNFG1_LOL_ERR_IE_SHIFT               (12U)
/*! LOL_ERR_IE - Loss-of-Lock Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FRO_CNFG1_LOL_ERR_IE(x)                  (((uint32_t)(((uint32_t)(x)) << FRO_CNFG1_LOL_ERR_IE_SHIFT)) & FRO_CNFG1_LOL_ERR_IE_MASK)

#define FRO_CNFG1_TUNE_ERR_IE_MASK               (0x2000U)
#define FRO_CNFG1_TUNE_ERR_IE_SHIFT              (13U)
/*! TUNE_ERR_IE - Tune Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FRO_CNFG1_TUNE_ERR_IE(x)                 (((uint32_t)(((uint32_t)(x)) << FRO_CNFG1_TUNE_ERR_IE_SHIFT)) & FRO_CNFG1_TUNE_ERR_IE_MASK)

#define FRO_CNFG1_TRUPREQ_IE_MASK                (0x4000U)
#define FRO_CNFG1_TRUPREQ_IE_SHIFT               (14U)
/*! TRUPREQ_IE - Trim Update Request Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FRO_CNFG1_TRUPREQ_IE(x)                  (((uint32_t)(((uint32_t)(x)) << FRO_CNFG1_TRUPREQ_IE_SHIFT)) & FRO_CNFG1_TRUPREQ_IE_MASK)

#define FRO_CNFG1_RFCLKCNT_MASK                  (0xFFFF0000U)
#define FRO_CNFG1_RFCLKCNT_SHIFT                 (16U)
/*! RFCLKCNT - Reference Clock Counter */
#define FRO_CNFG1_RFCLKCNT(x)                    (((uint32_t)(((uint32_t)(x)) << FRO_CNFG1_RFCLKCNT_SHIFT)) & FRO_CNFG1_RFCLKCNT_MASK)
/*! @} */

/*! @name CNFG2 - Trim Configuration 2 */
/*! @{ */

#define FRO_CNFG2_TRIM2_DELAY_MASK               (0xFFFU)
#define FRO_CNFG2_TRIM2_DELAY_SHIFT              (0U)
/*! TRIM2_DELAY - Trim 2 Delay Register */
#define FRO_CNFG2_TRIM2_DELAY(x)                 (((uint32_t)(((uint32_t)(x)) << FRO_CNFG2_TRIM2_DELAY_SHIFT)) & FRO_CNFG2_TRIM2_DELAY_MASK)

#define FRO_CNFG2_TRIM1_DELAY_MASK               (0xFFF0000U)
#define FRO_CNFG2_TRIM1_DELAY_SHIFT              (16U)
/*! TRIM1_DELAY - Trim 1 Delay Register */
#define FRO_CNFG2_TRIM1_DELAY(x)                 (((uint32_t)(((uint32_t)(x)) << FRO_CNFG2_TRIM1_DELAY_SHIFT)) & FRO_CNFG2_TRIM1_DELAY_MASK)
/*! @} */

/*! @name FROTRIM - FRO Trim */
/*! @{ */

#define FRO_FROTRIM_FINE_TRIM_MASK               (0x7FU)
#define FRO_FROTRIM_FINE_TRIM_SHIFT              (0U)
/*! FINE_TRIM - Fine Trim */
#define FRO_FROTRIM_FINE_TRIM(x)                 (((uint32_t)(((uint32_t)(x)) << FRO_FROTRIM_FINE_TRIM_SHIFT)) & FRO_FROTRIM_FINE_TRIM_MASK)

#define FRO_FROTRIM_COARSE_TRIM_MASK             (0xF80U)
#define FRO_FROTRIM_COARSE_TRIM_SHIFT            (7U)
/*! COARSE_TRIM - Coarse Trim */
#define FRO_FROTRIM_COARSE_TRIM(x)               (((uint32_t)(((uint32_t)(x)) << FRO_FROTRIM_COARSE_TRIM_SHIFT)) & FRO_FROTRIM_COARSE_TRIM_MASK)

#define FRO_FROTRIM_TRIMTEMP_MASK                (0x3F0000U)
#define FRO_FROTRIM_TRIMTEMP_SHIFT               (16U)
/*! TRIMTEMP - Trim Temperature */
#define FRO_FROTRIM_TRIMTEMP(x)                  (((uint32_t)(((uint32_t)(x)) << FRO_FROTRIM_TRIMTEMP_SHIFT)) & FRO_FROTRIM_TRIMTEMP_MASK)
/*! @} */

/*! @name TEXPCNT - FRO Expected Trim Count */
/*! @{ */

#define FRO_TEXPCNT_TEXPCNT_MASK                 (0xFFFFU)
#define FRO_TEXPCNT_TEXPCNT_SHIFT                (0U)
/*! TEXPCNT - Trim Expected Count */
#define FRO_TEXPCNT_TEXPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << FRO_TEXPCNT_TEXPCNT_SHIFT)) & FRO_TEXPCNT_TEXPCNT_MASK)

#define FRO_TEXPCNT_TEXPCNT_RANGE_MASK           (0xFF0000U)
#define FRO_TEXPCNT_TEXPCNT_RANGE_SHIFT          (16U)
/*! TEXPCNT_RANGE - Trim Expected Count Range */
#define FRO_TEXPCNT_TEXPCNT_RANGE(x)             (((uint32_t)(((uint32_t)(x)) << FRO_TEXPCNT_TEXPCNT_RANGE_SHIFT)) & FRO_TEXPCNT_TEXPCNT_RANGE_MASK)
/*! @} */

/*! @name AUTOTRIM - FRO Auto Tune Trim */
/*! @{ */

#define FRO_AUTOTRIM_AUTOTRIM_MASK               (0xFFFU)
#define FRO_AUTOTRIM_AUTOTRIM_SHIFT              (0U)
/*! AUTOTRIM - Auto Tune Trim Value */
#define FRO_AUTOTRIM_AUTOTRIM(x)                 (((uint32_t)(((uint32_t)(x)) << FRO_AUTOTRIM_AUTOTRIM_SHIFT)) & FRO_AUTOTRIM_AUTOTRIM_MASK)
/*! @} */

/*! @name TRIMCNT - FRO Trim Count */
/*! @{ */

#define FRO_TRIMCNT_TRIMCNT_MASK                 (0xFFFFFFFFU)
#define FRO_TRIMCNT_TRIMCNT_SHIFT                (0U)
/*! TRIMCNT - Trim Expected Count */
#define FRO_TRIMCNT_TRIMCNT(x)                   (((uint32_t)(((uint32_t)(x)) << FRO_TRIMCNT_TRIMCNT_SHIFT)) & FRO_TRIMCNT_TRIMCNT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FRO_Register_Masks */


/* FRO - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FRO0 base address */
  #define FRO0_BASE                                (0x50001100u)
  /** Peripheral FRO0 base address */
  #define FRO0_BASE_NS                             (0x40001100u)
  /** Peripheral FRO0 base pointer */
  #define FRO0                                     ((FRO_Type *)FRO0_BASE)
  /** Peripheral FRO0 base pointer */
  #define FRO0_NS                                  ((FRO_Type *)FRO0_BASE_NS)
  /** Peripheral FRO1 base address */
  #define FRO1_BASE                                (0x50001000u)
  /** Peripheral FRO1 base address */
  #define FRO1_BASE_NS                             (0x40001000u)
  /** Peripheral FRO1 base pointer */
  #define FRO1                                     ((FRO_Type *)FRO1_BASE)
  /** Peripheral FRO1 base pointer */
  #define FRO1_NS                                  ((FRO_Type *)FRO1_BASE_NS)
  /** Peripheral FRO2 base address */
  #define FRO2_BASE                                (0x50061100u)
  /** Peripheral FRO2 base address */
  #define FRO2_BASE_NS                             (0x40061100u)
  /** Peripheral FRO2 base pointer */
  #define FRO2                                     ((FRO_Type *)FRO2_BASE)
  /** Peripheral FRO2 base pointer */
  #define FRO2_NS                                  ((FRO_Type *)FRO2_BASE_NS)
  /** Array initializer of FRO peripheral base addresses */
  #define FRO_BASE_ADDRS                           { FRO0_BASE, FRO1_BASE, FRO2_BASE }
  /** Array initializer of FRO peripheral base pointers */
  #define FRO_BASE_PTRS                            { FRO0, FRO1, FRO2 }
  /** Array initializer of FRO peripheral base addresses */
  #define FRO_BASE_ADDRS_NS                        { FRO0_BASE_NS, FRO1_BASE_NS, FRO2_BASE_NS }
  /** Array initializer of FRO peripheral base pointers */
  #define FRO_BASE_PTRS_NS                         { FRO0_NS, FRO1_NS, FRO2_NS }
#else
  /** Peripheral FRO0 base address */
  #define FRO0_BASE                                (0x40001100u)
  /** Peripheral FRO0 base pointer */
  #define FRO0                                     ((FRO_Type *)FRO0_BASE)
  /** Peripheral FRO1 base address */
  #define FRO1_BASE                                (0x40001000u)
  /** Peripheral FRO1 base pointer */
  #define FRO1                                     ((FRO_Type *)FRO1_BASE)
  /** Peripheral FRO2 base address */
  #define FRO2_BASE                                (0x40061100u)
  /** Peripheral FRO2 base pointer */
  #define FRO2                                     ((FRO_Type *)FRO2_BASE)
  /** Array initializer of FRO peripheral base addresses */
  #define FRO_BASE_ADDRS                           { FRO0_BASE, FRO1_BASE, FRO2_BASE }
  /** Array initializer of FRO peripheral base pointers */
  #define FRO_BASE_PTRS                            { FRO0, FRO1, FRO2 }
#endif

/*!
 * @}
 */ /* end of group FRO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GDET Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GDET_Peripheral_Access_Layer GDET Peripheral Access Layer
 * @{
 */

/** GDET - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[8];
  __IO uint32_t GDET_ENABLE1;                      /**< Enable register, offset: 0x8 */
       uint8_t RESERVED_1[2044];
  __IO uint32_t GDET_DLY_CTRL;                     /**< GDET delay control register, offset: 0x808 */
  __O  uint32_t GDET_CTRL_CLR;                     /**< GDET Clear Control register, offset: 0x80C */
} GDET_Type;

/* ----------------------------------------------------------------------------
   -- GDET Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GDET_Register_Masks GDET Register Masks
 * @{
 */

/*! @name GDET_ENABLE1 - Enable register */
/*! @{ */

#define GDET_GDET_ENABLE1_EN1_MASK               (0x1U)
#define GDET_GDET_ENABLE1_EN1_SHIFT              (0U)
#define GDET_GDET_ENABLE1_EN1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK)

#define GDET_GDET_ENABLE1_RFU_MASK               (0xFFFFFFFEU)
#define GDET_GDET_ENABLE1_RFU_SHIFT              (1U)
#define GDET_GDET_ENABLE1_RFU(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK)
/*! @} */

/*! @name GDET_DLY_CTRL - GDET delay control register */
/*! @{ */

#define GDET_GDET_DLY_CTRL_VOL_SEL_MASK          (0x3U)
#define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT         (0U)
#define GDET_GDET_DLY_CTRL_VOL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK)

#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK      (0x4U)
#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT     (2U)
#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK)

#define GDET_GDET_DLY_CTRL_RFU_MASK              (0xFFFFFFF8U)
#define GDET_GDET_DLY_CTRL_RFU_SHIFT             (3U)
#define GDET_GDET_DLY_CTRL_RFU(x)                (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK)
/*! @} */

/*! @name GDET_CTRL_CLR - GDET Clear Control register */
/*! @{ */

#define GDET_GDET_CTRL_CLR_SFT_RST_MASK          (0x1U)
#define GDET_GDET_CTRL_CLR_SFT_RST_SHIFT         (0U)
#define GDET_GDET_CTRL_CLR_SFT_RST(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CTRL_CLR_SFT_RST_SHIFT)) & GDET_GDET_CTRL_CLR_SFT_RST_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group GDET_Register_Masks */


/* GDET - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral GDET0 base address */
  #define GDET0_BASE                               (0x50013000u)
  /** Peripheral GDET0 base address */
  #define GDET0_BASE_NS                            (0x40013000u)
  /** Peripheral GDET0 base pointer */
  #define GDET0                                    ((GDET_Type *)GDET0_BASE)
  /** Peripheral GDET0 base pointer */
  #define GDET0_NS                                 ((GDET_Type *)GDET0_BASE_NS)
  /** Peripheral GDET1 base address */
  #define GDET1_BASE                               (0x50014000u)
  /** Peripheral GDET1 base address */
  #define GDET1_BASE_NS                            (0x40014000u)
  /** Peripheral GDET1 base pointer */
  #define GDET1                                    ((GDET_Type *)GDET1_BASE)
  /** Peripheral GDET1 base pointer */
  #define GDET1_NS                                 ((GDET_Type *)GDET1_BASE_NS)
  /** Peripheral GDET2 base address */
  #define GDET2_BASE                               (0x5006A000u)
  /** Peripheral GDET2 base address */
  #define GDET2_BASE_NS                            (0x4006A000u)
  /** Peripheral GDET2 base pointer */
  #define GDET2                                    ((GDET_Type *)GDET2_BASE)
  /** Peripheral GDET2 base pointer */
  #define GDET2_NS                                 ((GDET_Type *)GDET2_BASE_NS)
  /** Peripheral GDET3 base address */
  #define GDET3_BASE                               (0x5006B000u)
  /** Peripheral GDET3 base address */
  #define GDET3_BASE_NS                            (0x4006B000u)
  /** Peripheral GDET3 base pointer */
  #define GDET3                                    ((GDET_Type *)GDET3_BASE)
  /** Peripheral GDET3 base pointer */
  #define GDET3_NS                                 ((GDET_Type *)GDET3_BASE_NS)
  /** Array initializer of GDET peripheral base addresses */
  #define GDET_BASE_ADDRS                          { GDET0_BASE, GDET1_BASE, GDET2_BASE, GDET3_BASE }
  /** Array initializer of GDET peripheral base pointers */
  #define GDET_BASE_PTRS                           { GDET0, GDET1, GDET2, GDET3 }
  /** Array initializer of GDET peripheral base addresses */
  #define GDET_BASE_ADDRS_NS                       { GDET0_BASE_NS, GDET1_BASE_NS, GDET2_BASE_NS, GDET3_BASE_NS }
  /** Array initializer of GDET peripheral base pointers */
  #define GDET_BASE_PTRS_NS                        { GDET0_NS, GDET1_NS, GDET2_NS, GDET3_NS }
#else
  /** Peripheral GDET0 base address */
  #define GDET0_BASE                               (0x40013000u)
  /** Peripheral GDET0 base pointer */
  #define GDET0                                    ((GDET_Type *)GDET0_BASE)
  /** Peripheral GDET1 base address */
  #define GDET1_BASE                               (0x40014000u)
  /** Peripheral GDET1 base pointer */
  #define GDET1                                    ((GDET_Type *)GDET1_BASE)
  /** Peripheral GDET2 base address */
  #define GDET2_BASE                               (0x4006A000u)
  /** Peripheral GDET2 base pointer */
  #define GDET2                                    ((GDET_Type *)GDET2_BASE)
  /** Peripheral GDET3 base address */
  #define GDET3_BASE                               (0x4006B000u)
  /** Peripheral GDET3 base pointer */
  #define GDET3                                    ((GDET_Type *)GDET3_BASE)
  /** Array initializer of GDET peripheral base addresses */
  #define GDET_BASE_ADDRS                          { GDET0_BASE, GDET1_BASE, GDET2_BASE, GDET3_BASE }
  /** Array initializer of GDET peripheral base pointers */
  #define GDET_BASE_PTRS                           { GDET0, GDET1, GDET2, GDET3 }
#endif

/*!
 * @}
 */ /* end of group GDET_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GLIKEY Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GLIKEY_Peripheral_Access_Layer GLIKEY Peripheral Access Layer
 * @{
 */

/** GLIKEY - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL_0;                            /**< Control Register 0 SFR, offset: 0x0 */
  __IO uint32_t CTRL_1;                            /**< Control Register 1 SFR, offset: 0x4 */
  __IO uint32_t INTR_CTRL;                         /**< Interrupt Control, offset: 0x8 */
  __I  uint32_t STATUS;                            /**< Status, offset: 0xC */
} GLIKEY_Type;

/* ----------------------------------------------------------------------------
   -- GLIKEY Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GLIKEY_Register_Masks GLIKEY Register Masks
 * @{
 */

/*! @name CTRL_0 - Control Register 0 SFR */
/*! @{ */

#define GLIKEY_CTRL_0_WRITE_INDEX_MASK           (0xFFU)
#define GLIKEY_CTRL_0_WRITE_INDEX_SHIFT          (0U)
/*! WRITE_INDEX - Write Index */
#define GLIKEY_CTRL_0_WRITE_INDEX(x)             (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WRITE_INDEX_SHIFT)) & GLIKEY_CTRL_0_WRITE_INDEX_MASK)

#define GLIKEY_CTRL_0_RESERVED15_MASK            (0xFF00U)
#define GLIKEY_CTRL_0_RESERVED15_SHIFT           (8U)
/*! RESERVED15 - Reserved for Future Use */
#define GLIKEY_CTRL_0_RESERVED15(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED15_SHIFT)) & GLIKEY_CTRL_0_RESERVED15_MASK)

#define GLIKEY_CTRL_0_WR_EN_0_MASK               (0x30000U)
#define GLIKEY_CTRL_0_WR_EN_0_SHIFT              (16U)
/*! WR_EN_0 - Write Enable 0 */
#define GLIKEY_CTRL_0_WR_EN_0(x)                 (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WR_EN_0_SHIFT)) & GLIKEY_CTRL_0_WR_EN_0_MASK)

#define GLIKEY_CTRL_0_SFT_RST_MASK               (0x40000U)
#define GLIKEY_CTRL_0_SFT_RST_SHIFT              (18U)
/*! SFT_RST - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0
 *  0b0..No effect
 *  0b1..Triggers the soft reset
 */
#define GLIKEY_CTRL_0_SFT_RST(x)                 (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_SFT_RST_SHIFT)) & GLIKEY_CTRL_0_SFT_RST_MASK)

#define GLIKEY_CTRL_0_RESERVED31_MASK            (0xFFF80000U)
#define GLIKEY_CTRL_0_RESERVED31_SHIFT           (19U)
/*! RESERVED31 - Reserved for Future Use */
#define GLIKEY_CTRL_0_RESERVED31(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED31_SHIFT)) & GLIKEY_CTRL_0_RESERVED31_MASK)
/*! @} */

/*! @name CTRL_1 - Control Register 1 SFR */
/*! @{ */

#define GLIKEY_CTRL_1_READ_INDEX_MASK            (0xFFU)
#define GLIKEY_CTRL_1_READ_INDEX_SHIFT           (0U)
/*! READ_INDEX - Index status, Writing an index value to this register will request the block to return the lock status of this index. */
#define GLIKEY_CTRL_1_READ_INDEX(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_READ_INDEX_SHIFT)) & GLIKEY_CTRL_1_READ_INDEX_MASK)

#define GLIKEY_CTRL_1_RESERVED15_MASK            (0xFF00U)
#define GLIKEY_CTRL_1_RESERVED15_SHIFT           (8U)
/*! RESERVED15 - Reserved for Future Use */
#define GLIKEY_CTRL_1_RESERVED15(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED15_SHIFT)) & GLIKEY_CTRL_1_RESERVED15_MASK)

#define GLIKEY_CTRL_1_WR_EN_1_MASK               (0x30000U)
#define GLIKEY_CTRL_1_WR_EN_1_SHIFT              (16U)
/*! WR_EN_1 - Write Enable One */
#define GLIKEY_CTRL_1_WR_EN_1(x)                 (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_WR_EN_1_SHIFT)) & GLIKEY_CTRL_1_WR_EN_1_MASK)

#define GLIKEY_CTRL_1_SFR_LOCK_MASK              (0x3C0000U)
#define GLIKEY_CTRL_1_SFR_LOCK_SHIFT             (18U)
/*! SFR_LOCK - LOCK register for GLIKEY */
#define GLIKEY_CTRL_1_SFR_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_SFR_LOCK_SHIFT)) & GLIKEY_CTRL_1_SFR_LOCK_MASK)

#define GLIKEY_CTRL_1_RESERVED31_MASK            (0xFFC00000U)
#define GLIKEY_CTRL_1_RESERVED31_SHIFT           (22U)
/*! RESERVED31 - Reserved for Future Use */
#define GLIKEY_CTRL_1_RESERVED31(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED31_SHIFT)) & GLIKEY_CTRL_1_RESERVED31_MASK)
/*! @} */

/*! @name INTR_CTRL - Interrupt Control */
/*! @{ */

#define GLIKEY_INTR_CTRL_INT_EN_MASK             (0x1U)
#define GLIKEY_INTR_CTRL_INT_EN_SHIFT            (0U)
/*! INT_EN - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port */
#define GLIKEY_INTR_CTRL_INT_EN(x)               (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_EN_SHIFT)) & GLIKEY_INTR_CTRL_INT_EN_MASK)

#define GLIKEY_INTR_CTRL_INT_CLR_MASK            (0x2U)
#define GLIKEY_INTR_CTRL_INT_CLR_SHIFT           (1U)
/*! INT_CLR - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0 */
#define GLIKEY_INTR_CTRL_INT_CLR(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_CLR_SHIFT)) & GLIKEY_INTR_CTRL_INT_CLR_MASK)

#define GLIKEY_INTR_CTRL_INT_SET_MASK            (0x4U)
#define GLIKEY_INTR_CTRL_INT_SET_SHIFT           (2U)
/*! INT_SET - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0
 *  0b0..No effect
 *  0b1..Triggers interrupt
 */
#define GLIKEY_INTR_CTRL_INT_SET(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_SET_SHIFT)) & GLIKEY_INTR_CTRL_INT_SET_MASK)

#define GLIKEY_INTR_CTRL_RESERVED31_MASK         (0xFFFFFFF8U)
#define GLIKEY_INTR_CTRL_RESERVED31_SHIFT        (3U)
/*! RESERVED31 - Reserved for Future Use */
#define GLIKEY_INTR_CTRL_RESERVED31(x)           (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_RESERVED31_SHIFT)) & GLIKEY_INTR_CTRL_RESERVED31_MASK)
/*! @} */

/*! @name STATUS - Status */
/*! @{ */

#define GLIKEY_STATUS_INT_STATUS_MASK            (0x1U)
#define GLIKEY_STATUS_INT_STATUS_SHIFT           (0U)
/*! INT_STATUS - Interrupt Status.
 *  0b0..No effect
 *  0b1..Triggers interrupt
 */
#define GLIKEY_STATUS_INT_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_INT_STATUS_SHIFT)) & GLIKEY_STATUS_INT_STATUS_MASK)

#define GLIKEY_STATUS_LOCK_STATUS_MASK           (0x2U)
#define GLIKEY_STATUS_LOCK_STATUS_SHIFT          (1U)
/*! LOCK_STATUS - Provides the current lock status of indexes.
 *  0b0..Current read index is not locked
 *  0b1..Current read index is locked
 */
#define GLIKEY_STATUS_LOCK_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_LOCK_STATUS_SHIFT)) & GLIKEY_STATUS_LOCK_STATUS_MASK)

#define GLIKEY_STATUS_ERROR_STATUS_MASK          (0x1CU)
#define GLIKEY_STATUS_ERROR_STATUS_SHIFT         (2U)
/*! ERROR_STATUS - Status of the Error
 *  0b000..No error
 *  0b001..FSM error has occurred
 *  0b010..Write index out of the bound (OOB) error
 *  0b011..Write index OOB and FSM error
 *  0b100..Read index OOB error
 *  0b110..Write index and read index OOB error
 *  0b111..Read index OOB, write index OOB, and FSM error
 */
#define GLIKEY_STATUS_ERROR_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_ERROR_STATUS_SHIFT)) & GLIKEY_STATUS_ERROR_STATUS_MASK)

#define GLIKEY_STATUS_RESERVED18_MASK            (0x7FFE0U)
#define GLIKEY_STATUS_RESERVED18_SHIFT           (5U)
/*! RESERVED18 - Reserved for Future Use */
#define GLIKEY_STATUS_RESERVED18(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_RESERVED18_SHIFT)) & GLIKEY_STATUS_RESERVED18_MASK)

#define GLIKEY_STATUS_FSM_STATE_MASK             (0xFFF80000U)
#define GLIKEY_STATUS_FSM_STATE_SHIFT            (19U)
/*! FSM_STATE - Status of FSM */
#define GLIKEY_STATUS_FSM_STATE(x)               (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_FSM_STATE_SHIFT)) & GLIKEY_STATUS_FSM_STATE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group GLIKEY_Register_Masks */


/* GLIKEY - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral GLIKEY0 base address */
  #define GLIKEY0_BASE                             (0x5017CC00u)
  /** Peripheral GLIKEY0 base address */
  #define GLIKEY0_BASE_NS                          (0x4017CC00u)
  /** Peripheral GLIKEY0 base pointer */
  #define GLIKEY0                                  ((GLIKEY_Type *)GLIKEY0_BASE)
  /** Peripheral GLIKEY0 base pointer */
  #define GLIKEY0_NS                               ((GLIKEY_Type *)GLIKEY0_BASE_NS)
  /** Peripheral GLIKEY1 base address */
  #define GLIKEY1_BASE                             (0x50220C00u)
  /** Peripheral GLIKEY1 base address */
  #define GLIKEY1_BASE_NS                          (0x40220C00u)
  /** Peripheral GLIKEY1 base pointer */
  #define GLIKEY1                                  ((GLIKEY_Type *)GLIKEY1_BASE)
  /** Peripheral GLIKEY1 base pointer */
  #define GLIKEY1_NS                               ((GLIKEY_Type *)GLIKEY1_BASE_NS)
  /** Peripheral GLIKEY2 base address */
  #define GLIKEY2_BASE                             (0x50400C00u)
  /** Peripheral GLIKEY2 base address */
  #define GLIKEY2_BASE_NS                          (0x40400C00u)
  /** Peripheral GLIKEY2 base pointer */
  #define GLIKEY2                                  ((GLIKEY_Type *)GLIKEY2_BASE)
  /** Peripheral GLIKEY2 base pointer */
  #define GLIKEY2_NS                               ((GLIKEY_Type *)GLIKEY2_BASE_NS)
  /** Peripheral GLIKEY3 base address */
  #define GLIKEY3_BASE                             (0x50002C00u)
  /** Peripheral GLIKEY3 base address */
  #define GLIKEY3_BASE_NS                          (0x40002C00u)
  /** Peripheral GLIKEY3 base pointer */
  #define GLIKEY3                                  ((GLIKEY_Type *)GLIKEY3_BASE)
  /** Peripheral GLIKEY3 base pointer */
  #define GLIKEY3_NS                               ((GLIKEY_Type *)GLIKEY3_BASE_NS)
  /** Peripheral GLIKEY4 base address */
  #define GLIKEY4_BASE                             (0x50062C00u)
  /** Peripheral GLIKEY4 base address */
  #define GLIKEY4_BASE_NS                          (0x40062C00u)
  /** Peripheral GLIKEY4 base pointer */
  #define GLIKEY4                                  ((GLIKEY_Type *)GLIKEY4_BASE)
  /** Peripheral GLIKEY4 base pointer */
  #define GLIKEY4_NS                               ((GLIKEY_Type *)GLIKEY4_BASE_NS)
  /** Peripheral GLIKEY5 base address */
  #define GLIKEY5_BASE                             (0x500A2C00u)
  /** Peripheral GLIKEY5 base address */
  #define GLIKEY5_BASE_NS                          (0x400A2C00u)
  /** Peripheral GLIKEY5 base pointer */
  #define GLIKEY5                                  ((GLIKEY_Type *)GLIKEY5_BASE)
  /** Peripheral GLIKEY5 base pointer */
  #define GLIKEY5_NS                               ((GLIKEY_Type *)GLIKEY5_BASE_NS)
  /** Array initializer of GLIKEY peripheral base addresses */
  #define GLIKEY_BASE_ADDRS                        { GLIKEY0_BASE, GLIKEY1_BASE, GLIKEY2_BASE, GLIKEY3_BASE, GLIKEY4_BASE, GLIKEY5_BASE }
  /** Array initializer of GLIKEY peripheral base pointers */
  #define GLIKEY_BASE_PTRS                         { GLIKEY0, GLIKEY1, GLIKEY2, GLIKEY3, GLIKEY4, GLIKEY5 }
  /** Array initializer of GLIKEY peripheral base addresses */
  #define GLIKEY_BASE_ADDRS_NS                     { GLIKEY0_BASE_NS, GLIKEY1_BASE_NS, GLIKEY2_BASE_NS, GLIKEY3_BASE_NS, GLIKEY4_BASE_NS, GLIKEY5_BASE_NS }
  /** Array initializer of GLIKEY peripheral base pointers */
  #define GLIKEY_BASE_PTRS_NS                      { GLIKEY0_NS, GLIKEY1_NS, GLIKEY2_NS, GLIKEY3_NS, GLIKEY4_NS, GLIKEY5_NS }
#else
  /** Peripheral GLIKEY0 base address */
  #define GLIKEY0_BASE                             (0x4017CC00u)
  /** Peripheral GLIKEY0 base pointer */
  #define GLIKEY0                                  ((GLIKEY_Type *)GLIKEY0_BASE)
  /** Peripheral GLIKEY1 base address */
  #define GLIKEY1_BASE                             (0x40220C00u)
  /** Peripheral GLIKEY1 base pointer */
  #define GLIKEY1                                  ((GLIKEY_Type *)GLIKEY1_BASE)
  /** Peripheral GLIKEY2 base address */
  #define GLIKEY2_BASE                             (0x40400C00u)
  /** Peripheral GLIKEY2 base pointer */
  #define GLIKEY2                                  ((GLIKEY_Type *)GLIKEY2_BASE)
  /** Peripheral GLIKEY3 base address */
  #define GLIKEY3_BASE                             (0x40002C00u)
  /** Peripheral GLIKEY3 base pointer */
  #define GLIKEY3                                  ((GLIKEY_Type *)GLIKEY3_BASE)
  /** Peripheral GLIKEY4 base address */
  #define GLIKEY4_BASE                             (0x40062C00u)
  /** Peripheral GLIKEY4 base pointer */
  #define GLIKEY4                                  ((GLIKEY_Type *)GLIKEY4_BASE)
  /** Peripheral GLIKEY5 base address */
  #define GLIKEY5_BASE                             (0x400A2C00u)
  /** Peripheral GLIKEY5 base pointer */
  #define GLIKEY5                                  ((GLIKEY_Type *)GLIKEY5_BASE)
  /** Array initializer of GLIKEY peripheral base addresses */
  #define GLIKEY_BASE_ADDRS                        { GLIKEY0_BASE, GLIKEY1_BASE, GLIKEY2_BASE, GLIKEY3_BASE, GLIKEY4_BASE, GLIKEY5_BASE }
  /** Array initializer of GLIKEY peripheral base pointers */
  #define GLIKEY_BASE_PTRS                         { GLIKEY0, GLIKEY1, GLIKEY2, GLIKEY3, GLIKEY4, GLIKEY5 }
#endif

/*!
 * @}
 */ /* end of group GLIKEY_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
 * @{
 */

/** GPIO - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t LOCK;                              /**< Lock, offset: 0xC */
  __IO uint32_t PCNS;                              /**< Pin Control Nonsecure, offset: 0x10 */
  __IO uint32_t ICNS;                              /**< Interrupt Control Nonsecure, offset: 0x14 */
  __IO uint32_t PCNP;                              /**< Pin Control Nonprivilege, offset: 0x18 */
  __IO uint32_t ICNP;                              /**< Interrupt Control Nonprivilege, offset: 0x1C */
       uint8_t RESERVED_1[32];
  __IO uint32_t PDOR;                              /**< Port Data Output, offset: 0x40 */
  __O  uint32_t PSOR;                              /**< Port Set Output, offset: 0x44 */
  __O  uint32_t PCOR;                              /**< Port Clear Output, offset: 0x48 */
  __O  uint32_t PTOR;                              /**< Port Toggle Output, offset: 0x4C */
  __I  uint32_t PDIR;                              /**< Port Data Input, offset: 0x50 */
  __IO uint32_t PDDR;                              /**< Port Data Direction, offset: 0x54 */
  __IO uint32_t PIDR;                              /**< Port Input Disable, offset: 0x58 */
       uint8_t RESERVED_2[4];
  __IO uint8_t PDR[32];                            /**< Pin Data, array offset: 0x60, array step: 0x1 */
  __IO uint32_t ICR[32];                           /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */
  __O  uint32_t GICLR;                             /**< Global Interrupt Control Low, offset: 0x100 */
  __O  uint32_t GICHR;                             /**< Global Interrupt Control High, offset: 0x104 */
       uint8_t RESERVED_3[24];
  __IO uint32_t ISFR[2];                           /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */
} GPIO_Type;

/* ----------------------------------------------------------------------------
   -- GPIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Register_Masks GPIO Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define GPIO_VERID_FEATURE_MASK                  (0xFFFFU)
#define GPIO_VERID_FEATURE_SHIFT                 (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Basic implementation
 *  0b0000000000000001..Protection registers implemented
 */
#define GPIO_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK)

#define GPIO_VERID_MINOR_MASK                    (0xFF0000U)
#define GPIO_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - Minor Version Number */
#define GPIO_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK)

#define GPIO_VERID_MAJOR_MASK                    (0xFF000000U)
#define GPIO_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - Major Version Number */
#define GPIO_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define GPIO_PARAM_IRQNUM_MASK                   (0xFU)
#define GPIO_PARAM_IRQNUM_SHIFT                  (0U)
/*! IRQNUM - Interrupt Number */
#define GPIO_PARAM_IRQNUM(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK)
/*! @} */

/*! @name LOCK - Lock */
/*! @{ */

#define GPIO_LOCK_PCNS_MASK                      (0x1U)
#define GPIO_LOCK_PCNS_SHIFT                     (0U)
/*! PCNS - Lock PCNS
 *  0b0..Writable in Secure-Privilege state
 *  0b1..Not writable until the next reset
 */
#define GPIO_LOCK_PCNS(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK)

#define GPIO_LOCK_ICNS_MASK                      (0x2U)
#define GPIO_LOCK_ICNS_SHIFT                     (1U)
/*! ICNS - Lock ICNS
 *  0b0..Writable in Secure-Privilege state
 *  0b1..Not writable until the next reset
 */
#define GPIO_LOCK_ICNS(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK)

#define GPIO_LOCK_PCNP_MASK                      (0x4U)
#define GPIO_LOCK_PCNP_SHIFT                     (2U)
/*! PCNP - Lock PCNP
 *  0b0..Writable in Secure-Privilege state
 *  0b1..Not writable until the next reset
 */
#define GPIO_LOCK_PCNP(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK)

#define GPIO_LOCK_ICNP_MASK                      (0x8U)
#define GPIO_LOCK_ICNP_SHIFT                     (3U)
/*! ICNP - Lock ICNP
 *  0b0..Writable in Secure-Privilege state
 *  0b1..Not writable until the next reset
 */
#define GPIO_LOCK_ICNP(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK)
/*! @} */

/*! @name PCNS - Pin Control Nonsecure */
/*! @{ */

#define GPIO_PCNS_NSE0_MASK                      (0x1U)
#define GPIO_PCNS_NSE0_SHIFT                     (0U)
/*! NSE0 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK)

#define GPIO_PCNS_NSE1_MASK                      (0x2U)
#define GPIO_PCNS_NSE1_SHIFT                     (1U)
/*! NSE1 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK)

#define GPIO_PCNS_NSE2_MASK                      (0x4U)
#define GPIO_PCNS_NSE2_SHIFT                     (2U)
/*! NSE2 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK)

#define GPIO_PCNS_NSE3_MASK                      (0x8U)
#define GPIO_PCNS_NSE3_SHIFT                     (3U)
/*! NSE3 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK)

#define GPIO_PCNS_NSE4_MASK                      (0x10U)
#define GPIO_PCNS_NSE4_SHIFT                     (4U)
/*! NSE4 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK)

#define GPIO_PCNS_NSE5_MASK                      (0x20U)
#define GPIO_PCNS_NSE5_SHIFT                     (5U)
/*! NSE5 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK)

#define GPIO_PCNS_NSE6_MASK                      (0x40U)
#define GPIO_PCNS_NSE6_SHIFT                     (6U)
/*! NSE6 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK)

#define GPIO_PCNS_NSE7_MASK                      (0x80U)
#define GPIO_PCNS_NSE7_SHIFT                     (7U)
/*! NSE7 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK)

#define GPIO_PCNS_NSE8_MASK                      (0x100U)
#define GPIO_PCNS_NSE8_SHIFT                     (8U)
/*! NSE8 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK)

#define GPIO_PCNS_NSE9_MASK                      (0x200U)
#define GPIO_PCNS_NSE9_SHIFT                     (9U)
/*! NSE9 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK)

#define GPIO_PCNS_NSE10_MASK                     (0x400U)
#define GPIO_PCNS_NSE10_SHIFT                    (10U)
/*! NSE10 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK)

#define GPIO_PCNS_NSE11_MASK                     (0x800U)
#define GPIO_PCNS_NSE11_SHIFT                    (11U)
/*! NSE11 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK)

#define GPIO_PCNS_NSE12_MASK                     (0x1000U)
#define GPIO_PCNS_NSE12_SHIFT                    (12U)
/*! NSE12 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK)

#define GPIO_PCNS_NSE13_MASK                     (0x2000U)
#define GPIO_PCNS_NSE13_SHIFT                    (13U)
/*! NSE13 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK)

#define GPIO_PCNS_NSE14_MASK                     (0x4000U)
#define GPIO_PCNS_NSE14_SHIFT                    (14U)
/*! NSE14 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK)

#define GPIO_PCNS_NSE15_MASK                     (0x8000U)
#define GPIO_PCNS_NSE15_SHIFT                    (15U)
/*! NSE15 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK)

#define GPIO_PCNS_NSE16_MASK                     (0x10000U)
#define GPIO_PCNS_NSE16_SHIFT                    (16U)
/*! NSE16 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK)

#define GPIO_PCNS_NSE17_MASK                     (0x20000U)
#define GPIO_PCNS_NSE17_SHIFT                    (17U)
/*! NSE17 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK)

#define GPIO_PCNS_NSE18_MASK                     (0x40000U)
#define GPIO_PCNS_NSE18_SHIFT                    (18U)
/*! NSE18 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK)

#define GPIO_PCNS_NSE19_MASK                     (0x80000U)
#define GPIO_PCNS_NSE19_SHIFT                    (19U)
/*! NSE19 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK)

#define GPIO_PCNS_NSE20_MASK                     (0x100000U)
#define GPIO_PCNS_NSE20_SHIFT                    (20U)
/*! NSE20 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK)

#define GPIO_PCNS_NSE21_MASK                     (0x200000U)
#define GPIO_PCNS_NSE21_SHIFT                    (21U)
/*! NSE21 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK)

#define GPIO_PCNS_NSE22_MASK                     (0x400000U)
#define GPIO_PCNS_NSE22_SHIFT                    (22U)
/*! NSE22 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK)

#define GPIO_PCNS_NSE23_MASK                     (0x800000U)
#define GPIO_PCNS_NSE23_SHIFT                    (23U)
/*! NSE23 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK)

#define GPIO_PCNS_NSE24_MASK                     (0x1000000U)
#define GPIO_PCNS_NSE24_SHIFT                    (24U)
/*! NSE24 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK)

#define GPIO_PCNS_NSE25_MASK                     (0x2000000U)
#define GPIO_PCNS_NSE25_SHIFT                    (25U)
/*! NSE25 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK)

#define GPIO_PCNS_NSE26_MASK                     (0x4000000U)
#define GPIO_PCNS_NSE26_SHIFT                    (26U)
/*! NSE26 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK)

#define GPIO_PCNS_NSE27_MASK                     (0x8000000U)
#define GPIO_PCNS_NSE27_SHIFT                    (27U)
/*! NSE27 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK)

#define GPIO_PCNS_NSE28_MASK                     (0x10000000U)
#define GPIO_PCNS_NSE28_SHIFT                    (28U)
/*! NSE28 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK)

#define GPIO_PCNS_NSE29_MASK                     (0x20000000U)
#define GPIO_PCNS_NSE29_SHIFT                    (29U)
/*! NSE29 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK)

#define GPIO_PCNS_NSE30_MASK                     (0x40000000U)
#define GPIO_PCNS_NSE30_SHIFT                    (30U)
/*! NSE30 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK)

#define GPIO_PCNS_NSE31_MASK                     (0x80000000U)
#define GPIO_PCNS_NSE31_SHIFT                    (31U)
/*! NSE31 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_PCNS_NSE31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK)
/*! @} */

/*! @name ICNS - Interrupt Control Nonsecure */
/*! @{ */

#define GPIO_ICNS_NSE0_MASK                      (0x1U)
#define GPIO_ICNS_NSE0_SHIFT                     (0U)
/*! NSE0 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_ICNS_NSE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK)

#define GPIO_ICNS_NSE1_MASK                      (0x2U)
#define GPIO_ICNS_NSE1_SHIFT                     (1U)
/*! NSE1 - Nonsecure Enable
 *  0b0..Secure access
 *  0b1..Nonsecure access
 */
#define GPIO_ICNS_NSE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK)
/*! @} */

/*! @name PCNP - Pin Control Nonprivilege */
/*! @{ */

#define GPIO_PCNP_NPE0_MASK                      (0x1U)
#define GPIO_PCNP_NPE0_SHIFT                     (0U)
/*! NPE0 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK)

#define GPIO_PCNP_NPE1_MASK                      (0x2U)
#define GPIO_PCNP_NPE1_SHIFT                     (1U)
/*! NPE1 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK)

#define GPIO_PCNP_NPE2_MASK                      (0x4U)
#define GPIO_PCNP_NPE2_SHIFT                     (2U)
/*! NPE2 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK)

#define GPIO_PCNP_NPE3_MASK                      (0x8U)
#define GPIO_PCNP_NPE3_SHIFT                     (3U)
/*! NPE3 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK)

#define GPIO_PCNP_NPE4_MASK                      (0x10U)
#define GPIO_PCNP_NPE4_SHIFT                     (4U)
/*! NPE4 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK)

#define GPIO_PCNP_NPE5_MASK                      (0x20U)
#define GPIO_PCNP_NPE5_SHIFT                     (5U)
/*! NPE5 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK)

#define GPIO_PCNP_NPE6_MASK                      (0x40U)
#define GPIO_PCNP_NPE6_SHIFT                     (6U)
/*! NPE6 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK)

#define GPIO_PCNP_NPE7_MASK                      (0x80U)
#define GPIO_PCNP_NPE7_SHIFT                     (7U)
/*! NPE7 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK)

#define GPIO_PCNP_NPE8_MASK                      (0x100U)
#define GPIO_PCNP_NPE8_SHIFT                     (8U)
/*! NPE8 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK)

#define GPIO_PCNP_NPE9_MASK                      (0x200U)
#define GPIO_PCNP_NPE9_SHIFT                     (9U)
/*! NPE9 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK)

#define GPIO_PCNP_NPE10_MASK                     (0x400U)
#define GPIO_PCNP_NPE10_SHIFT                    (10U)
/*! NPE10 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK)

#define GPIO_PCNP_NPE11_MASK                     (0x800U)
#define GPIO_PCNP_NPE11_SHIFT                    (11U)
/*! NPE11 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK)

#define GPIO_PCNP_NPE12_MASK                     (0x1000U)
#define GPIO_PCNP_NPE12_SHIFT                    (12U)
/*! NPE12 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK)

#define GPIO_PCNP_NPE13_MASK                     (0x2000U)
#define GPIO_PCNP_NPE13_SHIFT                    (13U)
/*! NPE13 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK)

#define GPIO_PCNP_NPE14_MASK                     (0x4000U)
#define GPIO_PCNP_NPE14_SHIFT                    (14U)
/*! NPE14 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK)

#define GPIO_PCNP_NPE15_MASK                     (0x8000U)
#define GPIO_PCNP_NPE15_SHIFT                    (15U)
/*! NPE15 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK)

#define GPIO_PCNP_NPE16_MASK                     (0x10000U)
#define GPIO_PCNP_NPE16_SHIFT                    (16U)
/*! NPE16 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK)

#define GPIO_PCNP_NPE17_MASK                     (0x20000U)
#define GPIO_PCNP_NPE17_SHIFT                    (17U)
/*! NPE17 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK)

#define GPIO_PCNP_NPE18_MASK                     (0x40000U)
#define GPIO_PCNP_NPE18_SHIFT                    (18U)
/*! NPE18 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK)

#define GPIO_PCNP_NPE19_MASK                     (0x80000U)
#define GPIO_PCNP_NPE19_SHIFT                    (19U)
/*! NPE19 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK)

#define GPIO_PCNP_NPE20_MASK                     (0x100000U)
#define GPIO_PCNP_NPE20_SHIFT                    (20U)
/*! NPE20 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK)

#define GPIO_PCNP_NPE21_MASK                     (0x200000U)
#define GPIO_PCNP_NPE21_SHIFT                    (21U)
/*! NPE21 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK)

#define GPIO_PCNP_NPE22_MASK                     (0x400000U)
#define GPIO_PCNP_NPE22_SHIFT                    (22U)
/*! NPE22 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK)

#define GPIO_PCNP_NPE23_MASK                     (0x800000U)
#define GPIO_PCNP_NPE23_SHIFT                    (23U)
/*! NPE23 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK)

#define GPIO_PCNP_NPE24_MASK                     (0x1000000U)
#define GPIO_PCNP_NPE24_SHIFT                    (24U)
/*! NPE24 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK)

#define GPIO_PCNP_NPE25_MASK                     (0x2000000U)
#define GPIO_PCNP_NPE25_SHIFT                    (25U)
/*! NPE25 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK)

#define GPIO_PCNP_NPE26_MASK                     (0x4000000U)
#define GPIO_PCNP_NPE26_SHIFT                    (26U)
/*! NPE26 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK)

#define GPIO_PCNP_NPE27_MASK                     (0x8000000U)
#define GPIO_PCNP_NPE27_SHIFT                    (27U)
/*! NPE27 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK)

#define GPIO_PCNP_NPE28_MASK                     (0x10000000U)
#define GPIO_PCNP_NPE28_SHIFT                    (28U)
/*! NPE28 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK)

#define GPIO_PCNP_NPE29_MASK                     (0x20000000U)
#define GPIO_PCNP_NPE29_SHIFT                    (29U)
/*! NPE29 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK)

#define GPIO_PCNP_NPE30_MASK                     (0x40000000U)
#define GPIO_PCNP_NPE30_SHIFT                    (30U)
/*! NPE30 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK)

#define GPIO_PCNP_NPE31_MASK                     (0x80000000U)
#define GPIO_PCNP_NPE31_SHIFT                    (31U)
/*! NPE31 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_PCNP_NPE31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK)
/*! @} */

/*! @name ICNP - Interrupt Control Nonprivilege */
/*! @{ */

#define GPIO_ICNP_NPE0_MASK                      (0x1U)
#define GPIO_ICNP_NPE0_SHIFT                     (0U)
/*! NPE0 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_ICNP_NPE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK)

#define GPIO_ICNP_NPE1_MASK                      (0x2U)
#define GPIO_ICNP_NPE1_SHIFT                     (1U)
/*! NPE1 - Nonprivilege Enable
 *  0b0..Privilege access
 *  0b1..Nonprivilege access
 */
#define GPIO_ICNP_NPE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK)
/*! @} */

/*! @name PDOR - Port Data Output */
/*! @{ */

#define GPIO_PDOR_PDO0_MASK                      (0x1U)
#define GPIO_PDOR_PDO0_SHIFT                     (0U)
/*! PDO0 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK)

#define GPIO_PDOR_PDO1_MASK                      (0x2U)
#define GPIO_PDOR_PDO1_SHIFT                     (1U)
/*! PDO1 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK)

#define GPIO_PDOR_PDO2_MASK                      (0x4U)
#define GPIO_PDOR_PDO2_SHIFT                     (2U)
/*! PDO2 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK)

#define GPIO_PDOR_PDO3_MASK                      (0x8U)
#define GPIO_PDOR_PDO3_SHIFT                     (3U)
/*! PDO3 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK)

#define GPIO_PDOR_PDO4_MASK                      (0x10U)
#define GPIO_PDOR_PDO4_SHIFT                     (4U)
/*! PDO4 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK)

#define GPIO_PDOR_PDO5_MASK                      (0x20U)
#define GPIO_PDOR_PDO5_SHIFT                     (5U)
/*! PDO5 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK)

#define GPIO_PDOR_PDO6_MASK                      (0x40U)
#define GPIO_PDOR_PDO6_SHIFT                     (6U)
/*! PDO6 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK)

#define GPIO_PDOR_PDO7_MASK                      (0x80U)
#define GPIO_PDOR_PDO7_SHIFT                     (7U)
/*! PDO7 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK)

#define GPIO_PDOR_PDO8_MASK                      (0x100U)
#define GPIO_PDOR_PDO8_SHIFT                     (8U)
/*! PDO8 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK)

#define GPIO_PDOR_PDO9_MASK                      (0x200U)
#define GPIO_PDOR_PDO9_SHIFT                     (9U)
/*! PDO9 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK)

#define GPIO_PDOR_PDO10_MASK                     (0x400U)
#define GPIO_PDOR_PDO10_SHIFT                    (10U)
/*! PDO10 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK)

#define GPIO_PDOR_PDO11_MASK                     (0x800U)
#define GPIO_PDOR_PDO11_SHIFT                    (11U)
/*! PDO11 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK)

#define GPIO_PDOR_PDO12_MASK                     (0x1000U)
#define GPIO_PDOR_PDO12_SHIFT                    (12U)
/*! PDO12 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK)

#define GPIO_PDOR_PDO13_MASK                     (0x2000U)
#define GPIO_PDOR_PDO13_SHIFT                    (13U)
/*! PDO13 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK)

#define GPIO_PDOR_PDO14_MASK                     (0x4000U)
#define GPIO_PDOR_PDO14_SHIFT                    (14U)
/*! PDO14 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK)

#define GPIO_PDOR_PDO15_MASK                     (0x8000U)
#define GPIO_PDOR_PDO15_SHIFT                    (15U)
/*! PDO15 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK)

#define GPIO_PDOR_PDO16_MASK                     (0x10000U)
#define GPIO_PDOR_PDO16_SHIFT                    (16U)
/*! PDO16 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK)

#define GPIO_PDOR_PDO17_MASK                     (0x20000U)
#define GPIO_PDOR_PDO17_SHIFT                    (17U)
/*! PDO17 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK)

#define GPIO_PDOR_PDO18_MASK                     (0x40000U)
#define GPIO_PDOR_PDO18_SHIFT                    (18U)
/*! PDO18 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK)

#define GPIO_PDOR_PDO19_MASK                     (0x80000U)
#define GPIO_PDOR_PDO19_SHIFT                    (19U)
/*! PDO19 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK)

#define GPIO_PDOR_PDO20_MASK                     (0x100000U)
#define GPIO_PDOR_PDO20_SHIFT                    (20U)
/*! PDO20 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK)

#define GPIO_PDOR_PDO21_MASK                     (0x200000U)
#define GPIO_PDOR_PDO21_SHIFT                    (21U)
/*! PDO21 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK)

#define GPIO_PDOR_PDO22_MASK                     (0x400000U)
#define GPIO_PDOR_PDO22_SHIFT                    (22U)
/*! PDO22 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK)

#define GPIO_PDOR_PDO23_MASK                     (0x800000U)
#define GPIO_PDOR_PDO23_SHIFT                    (23U)
/*! PDO23 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK)

#define GPIO_PDOR_PDO24_MASK                     (0x1000000U)
#define GPIO_PDOR_PDO24_SHIFT                    (24U)
/*! PDO24 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK)

#define GPIO_PDOR_PDO25_MASK                     (0x2000000U)
#define GPIO_PDOR_PDO25_SHIFT                    (25U)
/*! PDO25 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK)

#define GPIO_PDOR_PDO26_MASK                     (0x4000000U)
#define GPIO_PDOR_PDO26_SHIFT                    (26U)
/*! PDO26 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK)

#define GPIO_PDOR_PDO27_MASK                     (0x8000000U)
#define GPIO_PDOR_PDO27_SHIFT                    (27U)
/*! PDO27 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK)

#define GPIO_PDOR_PDO28_MASK                     (0x10000000U)
#define GPIO_PDOR_PDO28_SHIFT                    (28U)
/*! PDO28 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK)

#define GPIO_PDOR_PDO29_MASK                     (0x20000000U)
#define GPIO_PDOR_PDO29_SHIFT                    (29U)
/*! PDO29 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK)

#define GPIO_PDOR_PDO30_MASK                     (0x40000000U)
#define GPIO_PDOR_PDO30_SHIFT                    (30U)
/*! PDO30 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK)

#define GPIO_PDOR_PDO31_MASK                     (0x80000000U)
#define GPIO_PDOR_PDO31_SHIFT                    (31U)
/*! PDO31 - Port Data Output
 *  0b0..Logic level 0
 *  0b1..Logic level 1
 */
#define GPIO_PDOR_PDO31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK)
/*! @} */

/*! @name PSOR - Port Set Output */
/*! @{ */

#define GPIO_PSOR_PTSO0_MASK                     (0x1U)
#define GPIO_PSOR_PTSO0_SHIFT                    (0U)
/*! PTSO0 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK)

#define GPIO_PSOR_PTSO1_MASK                     (0x2U)
#define GPIO_PSOR_PTSO1_SHIFT                    (1U)
/*! PTSO1 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK)

#define GPIO_PSOR_PTSO2_MASK                     (0x4U)
#define GPIO_PSOR_PTSO2_SHIFT                    (2U)
/*! PTSO2 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK)

#define GPIO_PSOR_PTSO3_MASK                     (0x8U)
#define GPIO_PSOR_PTSO3_SHIFT                    (3U)
/*! PTSO3 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK)

#define GPIO_PSOR_PTSO4_MASK                     (0x10U)
#define GPIO_PSOR_PTSO4_SHIFT                    (4U)
/*! PTSO4 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK)

#define GPIO_PSOR_PTSO5_MASK                     (0x20U)
#define GPIO_PSOR_PTSO5_SHIFT                    (5U)
/*! PTSO5 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK)

#define GPIO_PSOR_PTSO6_MASK                     (0x40U)
#define GPIO_PSOR_PTSO6_SHIFT                    (6U)
/*! PTSO6 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK)

#define GPIO_PSOR_PTSO7_MASK                     (0x80U)
#define GPIO_PSOR_PTSO7_SHIFT                    (7U)
/*! PTSO7 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK)

#define GPIO_PSOR_PTSO8_MASK                     (0x100U)
#define GPIO_PSOR_PTSO8_SHIFT                    (8U)
/*! PTSO8 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK)

#define GPIO_PSOR_PTSO9_MASK                     (0x200U)
#define GPIO_PSOR_PTSO9_SHIFT                    (9U)
/*! PTSO9 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK)

#define GPIO_PSOR_PTSO10_MASK                    (0x400U)
#define GPIO_PSOR_PTSO10_SHIFT                   (10U)
/*! PTSO10 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK)

#define GPIO_PSOR_PTSO11_MASK                    (0x800U)
#define GPIO_PSOR_PTSO11_SHIFT                   (11U)
/*! PTSO11 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK)

#define GPIO_PSOR_PTSO12_MASK                    (0x1000U)
#define GPIO_PSOR_PTSO12_SHIFT                   (12U)
/*! PTSO12 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK)

#define GPIO_PSOR_PTSO13_MASK                    (0x2000U)
#define GPIO_PSOR_PTSO13_SHIFT                   (13U)
/*! PTSO13 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK)

#define GPIO_PSOR_PTSO14_MASK                    (0x4000U)
#define GPIO_PSOR_PTSO14_SHIFT                   (14U)
/*! PTSO14 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK)

#define GPIO_PSOR_PTSO15_MASK                    (0x8000U)
#define GPIO_PSOR_PTSO15_SHIFT                   (15U)
/*! PTSO15 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK)

#define GPIO_PSOR_PTSO16_MASK                    (0x10000U)
#define GPIO_PSOR_PTSO16_SHIFT                   (16U)
/*! PTSO16 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK)

#define GPIO_PSOR_PTSO17_MASK                    (0x20000U)
#define GPIO_PSOR_PTSO17_SHIFT                   (17U)
/*! PTSO17 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK)

#define GPIO_PSOR_PTSO18_MASK                    (0x40000U)
#define GPIO_PSOR_PTSO18_SHIFT                   (18U)
/*! PTSO18 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK)

#define GPIO_PSOR_PTSO19_MASK                    (0x80000U)
#define GPIO_PSOR_PTSO19_SHIFT                   (19U)
/*! PTSO19 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK)

#define GPIO_PSOR_PTSO20_MASK                    (0x100000U)
#define GPIO_PSOR_PTSO20_SHIFT                   (20U)
/*! PTSO20 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK)

#define GPIO_PSOR_PTSO21_MASK                    (0x200000U)
#define GPIO_PSOR_PTSO21_SHIFT                   (21U)
/*! PTSO21 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK)

#define GPIO_PSOR_PTSO22_MASK                    (0x400000U)
#define GPIO_PSOR_PTSO22_SHIFT                   (22U)
/*! PTSO22 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK)

#define GPIO_PSOR_PTSO23_MASK                    (0x800000U)
#define GPIO_PSOR_PTSO23_SHIFT                   (23U)
/*! PTSO23 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK)

#define GPIO_PSOR_PTSO24_MASK                    (0x1000000U)
#define GPIO_PSOR_PTSO24_SHIFT                   (24U)
/*! PTSO24 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK)

#define GPIO_PSOR_PTSO25_MASK                    (0x2000000U)
#define GPIO_PSOR_PTSO25_SHIFT                   (25U)
/*! PTSO25 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK)

#define GPIO_PSOR_PTSO26_MASK                    (0x4000000U)
#define GPIO_PSOR_PTSO26_SHIFT                   (26U)
/*! PTSO26 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK)

#define GPIO_PSOR_PTSO27_MASK                    (0x8000000U)
#define GPIO_PSOR_PTSO27_SHIFT                   (27U)
/*! PTSO27 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK)

#define GPIO_PSOR_PTSO28_MASK                    (0x10000000U)
#define GPIO_PSOR_PTSO28_SHIFT                   (28U)
/*! PTSO28 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK)

#define GPIO_PSOR_PTSO29_MASK                    (0x20000000U)
#define GPIO_PSOR_PTSO29_SHIFT                   (29U)
/*! PTSO29 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK)

#define GPIO_PSOR_PTSO30_MASK                    (0x40000000U)
#define GPIO_PSOR_PTSO30_SHIFT                   (30U)
/*! PTSO30 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK)

#define GPIO_PSOR_PTSO31_MASK                    (0x80000000U)
#define GPIO_PSOR_PTSO31_SHIFT                   (31U)
/*! PTSO31 - Port Set Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 1
 */
#define GPIO_PSOR_PTSO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK)
/*! @} */

/*! @name PCOR - Port Clear Output */
/*! @{ */

#define GPIO_PCOR_PTCO0_MASK                     (0x1U)
#define GPIO_PCOR_PTCO0_SHIFT                    (0U)
/*! PTCO0 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK)

#define GPIO_PCOR_PTCO1_MASK                     (0x2U)
#define GPIO_PCOR_PTCO1_SHIFT                    (1U)
/*! PTCO1 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK)

#define GPIO_PCOR_PTCO2_MASK                     (0x4U)
#define GPIO_PCOR_PTCO2_SHIFT                    (2U)
/*! PTCO2 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK)

#define GPIO_PCOR_PTCO3_MASK                     (0x8U)
#define GPIO_PCOR_PTCO3_SHIFT                    (3U)
/*! PTCO3 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK)

#define GPIO_PCOR_PTCO4_MASK                     (0x10U)
#define GPIO_PCOR_PTCO4_SHIFT                    (4U)
/*! PTCO4 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK)

#define GPIO_PCOR_PTCO5_MASK                     (0x20U)
#define GPIO_PCOR_PTCO5_SHIFT                    (5U)
/*! PTCO5 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK)

#define GPIO_PCOR_PTCO6_MASK                     (0x40U)
#define GPIO_PCOR_PTCO6_SHIFT                    (6U)
/*! PTCO6 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK)

#define GPIO_PCOR_PTCO7_MASK                     (0x80U)
#define GPIO_PCOR_PTCO7_SHIFT                    (7U)
/*! PTCO7 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK)

#define GPIO_PCOR_PTCO8_MASK                     (0x100U)
#define GPIO_PCOR_PTCO8_SHIFT                    (8U)
/*! PTCO8 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK)

#define GPIO_PCOR_PTCO9_MASK                     (0x200U)
#define GPIO_PCOR_PTCO9_SHIFT                    (9U)
/*! PTCO9 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK)

#define GPIO_PCOR_PTCO10_MASK                    (0x400U)
#define GPIO_PCOR_PTCO10_SHIFT                   (10U)
/*! PTCO10 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK)

#define GPIO_PCOR_PTCO11_MASK                    (0x800U)
#define GPIO_PCOR_PTCO11_SHIFT                   (11U)
/*! PTCO11 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK)

#define GPIO_PCOR_PTCO12_MASK                    (0x1000U)
#define GPIO_PCOR_PTCO12_SHIFT                   (12U)
/*! PTCO12 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK)

#define GPIO_PCOR_PTCO13_MASK                    (0x2000U)
#define GPIO_PCOR_PTCO13_SHIFT                   (13U)
/*! PTCO13 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK)

#define GPIO_PCOR_PTCO14_MASK                    (0x4000U)
#define GPIO_PCOR_PTCO14_SHIFT                   (14U)
/*! PTCO14 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK)

#define GPIO_PCOR_PTCO15_MASK                    (0x8000U)
#define GPIO_PCOR_PTCO15_SHIFT                   (15U)
/*! PTCO15 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK)

#define GPIO_PCOR_PTCO16_MASK                    (0x10000U)
#define GPIO_PCOR_PTCO16_SHIFT                   (16U)
/*! PTCO16 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK)

#define GPIO_PCOR_PTCO17_MASK                    (0x20000U)
#define GPIO_PCOR_PTCO17_SHIFT                   (17U)
/*! PTCO17 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK)

#define GPIO_PCOR_PTCO18_MASK                    (0x40000U)
#define GPIO_PCOR_PTCO18_SHIFT                   (18U)
/*! PTCO18 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK)

#define GPIO_PCOR_PTCO19_MASK                    (0x80000U)
#define GPIO_PCOR_PTCO19_SHIFT                   (19U)
/*! PTCO19 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK)

#define GPIO_PCOR_PTCO20_MASK                    (0x100000U)
#define GPIO_PCOR_PTCO20_SHIFT                   (20U)
/*! PTCO20 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK)

#define GPIO_PCOR_PTCO21_MASK                    (0x200000U)
#define GPIO_PCOR_PTCO21_SHIFT                   (21U)
/*! PTCO21 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK)

#define GPIO_PCOR_PTCO22_MASK                    (0x400000U)
#define GPIO_PCOR_PTCO22_SHIFT                   (22U)
/*! PTCO22 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK)

#define GPIO_PCOR_PTCO23_MASK                    (0x800000U)
#define GPIO_PCOR_PTCO23_SHIFT                   (23U)
/*! PTCO23 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK)

#define GPIO_PCOR_PTCO24_MASK                    (0x1000000U)
#define GPIO_PCOR_PTCO24_SHIFT                   (24U)
/*! PTCO24 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK)

#define GPIO_PCOR_PTCO25_MASK                    (0x2000000U)
#define GPIO_PCOR_PTCO25_SHIFT                   (25U)
/*! PTCO25 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK)

#define GPIO_PCOR_PTCO26_MASK                    (0x4000000U)
#define GPIO_PCOR_PTCO26_SHIFT                   (26U)
/*! PTCO26 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK)

#define GPIO_PCOR_PTCO27_MASK                    (0x8000000U)
#define GPIO_PCOR_PTCO27_SHIFT                   (27U)
/*! PTCO27 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK)

#define GPIO_PCOR_PTCO28_MASK                    (0x10000000U)
#define GPIO_PCOR_PTCO28_SHIFT                   (28U)
/*! PTCO28 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK)

#define GPIO_PCOR_PTCO29_MASK                    (0x20000000U)
#define GPIO_PCOR_PTCO29_SHIFT                   (29U)
/*! PTCO29 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK)

#define GPIO_PCOR_PTCO30_MASK                    (0x40000000U)
#define GPIO_PCOR_PTCO30_SHIFT                   (30U)
/*! PTCO30 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK)

#define GPIO_PCOR_PTCO31_MASK                    (0x80000000U)
#define GPIO_PCOR_PTCO31_SHIFT                   (31U)
/*! PTCO31 - Port Clear Output
 *  0b0..No change
 *  0b1..Corresponding field in PDOR becomes 0
 */
#define GPIO_PCOR_PTCO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK)
/*! @} */

/*! @name PTOR - Port Toggle Output */
/*! @{ */

#define GPIO_PTOR_PTTO0_MASK                     (0x1U)
#define GPIO_PTOR_PTTO0_SHIFT                    (0U)
/*! PTTO0 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK)

#define GPIO_PTOR_PTTO1_MASK                     (0x2U)
#define GPIO_PTOR_PTTO1_SHIFT                    (1U)
/*! PTTO1 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK)

#define GPIO_PTOR_PTTO2_MASK                     (0x4U)
#define GPIO_PTOR_PTTO2_SHIFT                    (2U)
/*! PTTO2 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK)

#define GPIO_PTOR_PTTO3_MASK                     (0x8U)
#define GPIO_PTOR_PTTO3_SHIFT                    (3U)
/*! PTTO3 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK)

#define GPIO_PTOR_PTTO4_MASK                     (0x10U)
#define GPIO_PTOR_PTTO4_SHIFT                    (4U)
/*! PTTO4 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK)

#define GPIO_PTOR_PTTO5_MASK                     (0x20U)
#define GPIO_PTOR_PTTO5_SHIFT                    (5U)
/*! PTTO5 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK)

#define GPIO_PTOR_PTTO6_MASK                     (0x40U)
#define GPIO_PTOR_PTTO6_SHIFT                    (6U)
/*! PTTO6 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK)

#define GPIO_PTOR_PTTO7_MASK                     (0x80U)
#define GPIO_PTOR_PTTO7_SHIFT                    (7U)
/*! PTTO7 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK)

#define GPIO_PTOR_PTTO8_MASK                     (0x100U)
#define GPIO_PTOR_PTTO8_SHIFT                    (8U)
/*! PTTO8 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK)

#define GPIO_PTOR_PTTO9_MASK                     (0x200U)
#define GPIO_PTOR_PTTO9_SHIFT                    (9U)
/*! PTTO9 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK)

#define GPIO_PTOR_PTTO10_MASK                    (0x400U)
#define GPIO_PTOR_PTTO10_SHIFT                   (10U)
/*! PTTO10 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK)

#define GPIO_PTOR_PTTO11_MASK                    (0x800U)
#define GPIO_PTOR_PTTO11_SHIFT                   (11U)
/*! PTTO11 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK)

#define GPIO_PTOR_PTTO12_MASK                    (0x1000U)
#define GPIO_PTOR_PTTO12_SHIFT                   (12U)
/*! PTTO12 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK)

#define GPIO_PTOR_PTTO13_MASK                    (0x2000U)
#define GPIO_PTOR_PTTO13_SHIFT                   (13U)
/*! PTTO13 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK)

#define GPIO_PTOR_PTTO14_MASK                    (0x4000U)
#define GPIO_PTOR_PTTO14_SHIFT                   (14U)
/*! PTTO14 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK)

#define GPIO_PTOR_PTTO15_MASK                    (0x8000U)
#define GPIO_PTOR_PTTO15_SHIFT                   (15U)
/*! PTTO15 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK)

#define GPIO_PTOR_PTTO16_MASK                    (0x10000U)
#define GPIO_PTOR_PTTO16_SHIFT                   (16U)
/*! PTTO16 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK)

#define GPIO_PTOR_PTTO17_MASK                    (0x20000U)
#define GPIO_PTOR_PTTO17_SHIFT                   (17U)
/*! PTTO17 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK)

#define GPIO_PTOR_PTTO18_MASK                    (0x40000U)
#define GPIO_PTOR_PTTO18_SHIFT                   (18U)
/*! PTTO18 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK)

#define GPIO_PTOR_PTTO19_MASK                    (0x80000U)
#define GPIO_PTOR_PTTO19_SHIFT                   (19U)
/*! PTTO19 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK)

#define GPIO_PTOR_PTTO20_MASK                    (0x100000U)
#define GPIO_PTOR_PTTO20_SHIFT                   (20U)
/*! PTTO20 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK)

#define GPIO_PTOR_PTTO21_MASK                    (0x200000U)
#define GPIO_PTOR_PTTO21_SHIFT                   (21U)
/*! PTTO21 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK)

#define GPIO_PTOR_PTTO22_MASK                    (0x400000U)
#define GPIO_PTOR_PTTO22_SHIFT                   (22U)
/*! PTTO22 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK)

#define GPIO_PTOR_PTTO23_MASK                    (0x800000U)
#define GPIO_PTOR_PTTO23_SHIFT                   (23U)
/*! PTTO23 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK)

#define GPIO_PTOR_PTTO24_MASK                    (0x1000000U)
#define GPIO_PTOR_PTTO24_SHIFT                   (24U)
/*! PTTO24 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK)

#define GPIO_PTOR_PTTO25_MASK                    (0x2000000U)
#define GPIO_PTOR_PTTO25_SHIFT                   (25U)
/*! PTTO25 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK)

#define GPIO_PTOR_PTTO26_MASK                    (0x4000000U)
#define GPIO_PTOR_PTTO26_SHIFT                   (26U)
/*! PTTO26 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK)

#define GPIO_PTOR_PTTO27_MASK                    (0x8000000U)
#define GPIO_PTOR_PTTO27_SHIFT                   (27U)
/*! PTTO27 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK)

#define GPIO_PTOR_PTTO28_MASK                    (0x10000000U)
#define GPIO_PTOR_PTTO28_SHIFT                   (28U)
/*! PTTO28 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK)

#define GPIO_PTOR_PTTO29_MASK                    (0x20000000U)
#define GPIO_PTOR_PTTO29_SHIFT                   (29U)
/*! PTTO29 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK)

#define GPIO_PTOR_PTTO30_MASK                    (0x40000000U)
#define GPIO_PTOR_PTTO30_SHIFT                   (30U)
/*! PTTO30 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK)

#define GPIO_PTOR_PTTO31_MASK                    (0x80000000U)
#define GPIO_PTOR_PTTO31_SHIFT                   (31U)
/*! PTTO31 - Port Toggle Output
 *  0b0..No change
 *  0b1..Set to the inverse of its current logic state
 */
#define GPIO_PTOR_PTTO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK)
/*! @} */

/*! @name PDIR - Port Data Input */
/*! @{ */

#define GPIO_PDIR_PDI0_MASK                      (0x1U)
#define GPIO_PDIR_PDI0_SHIFT                     (0U)
/*! PDI0 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK)

#define GPIO_PDIR_PDI1_MASK                      (0x2U)
#define GPIO_PDIR_PDI1_SHIFT                     (1U)
/*! PDI1 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK)

#define GPIO_PDIR_PDI2_MASK                      (0x4U)
#define GPIO_PDIR_PDI2_SHIFT                     (2U)
/*! PDI2 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK)

#define GPIO_PDIR_PDI3_MASK                      (0x8U)
#define GPIO_PDIR_PDI3_SHIFT                     (3U)
/*! PDI3 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK)

#define GPIO_PDIR_PDI4_MASK                      (0x10U)
#define GPIO_PDIR_PDI4_SHIFT                     (4U)
/*! PDI4 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK)

#define GPIO_PDIR_PDI5_MASK                      (0x20U)
#define GPIO_PDIR_PDI5_SHIFT                     (5U)
/*! PDI5 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK)

#define GPIO_PDIR_PDI6_MASK                      (0x40U)
#define GPIO_PDIR_PDI6_SHIFT                     (6U)
/*! PDI6 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK)

#define GPIO_PDIR_PDI7_MASK                      (0x80U)
#define GPIO_PDIR_PDI7_SHIFT                     (7U)
/*! PDI7 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK)

#define GPIO_PDIR_PDI8_MASK                      (0x100U)
#define GPIO_PDIR_PDI8_SHIFT                     (8U)
/*! PDI8 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK)

#define GPIO_PDIR_PDI9_MASK                      (0x200U)
#define GPIO_PDIR_PDI9_SHIFT                     (9U)
/*! PDI9 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK)

#define GPIO_PDIR_PDI10_MASK                     (0x400U)
#define GPIO_PDIR_PDI10_SHIFT                    (10U)
/*! PDI10 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK)

#define GPIO_PDIR_PDI11_MASK                     (0x800U)
#define GPIO_PDIR_PDI11_SHIFT                    (11U)
/*! PDI11 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK)

#define GPIO_PDIR_PDI12_MASK                     (0x1000U)
#define GPIO_PDIR_PDI12_SHIFT                    (12U)
/*! PDI12 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK)

#define GPIO_PDIR_PDI13_MASK                     (0x2000U)
#define GPIO_PDIR_PDI13_SHIFT                    (13U)
/*! PDI13 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK)

#define GPIO_PDIR_PDI14_MASK                     (0x4000U)
#define GPIO_PDIR_PDI14_SHIFT                    (14U)
/*! PDI14 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK)

#define GPIO_PDIR_PDI15_MASK                     (0x8000U)
#define GPIO_PDIR_PDI15_SHIFT                    (15U)
/*! PDI15 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK)

#define GPIO_PDIR_PDI16_MASK                     (0x10000U)
#define GPIO_PDIR_PDI16_SHIFT                    (16U)
/*! PDI16 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK)

#define GPIO_PDIR_PDI17_MASK                     (0x20000U)
#define GPIO_PDIR_PDI17_SHIFT                    (17U)
/*! PDI17 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK)

#define GPIO_PDIR_PDI18_MASK                     (0x40000U)
#define GPIO_PDIR_PDI18_SHIFT                    (18U)
/*! PDI18 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK)

#define GPIO_PDIR_PDI19_MASK                     (0x80000U)
#define GPIO_PDIR_PDI19_SHIFT                    (19U)
/*! PDI19 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK)

#define GPIO_PDIR_PDI20_MASK                     (0x100000U)
#define GPIO_PDIR_PDI20_SHIFT                    (20U)
/*! PDI20 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK)

#define GPIO_PDIR_PDI21_MASK                     (0x200000U)
#define GPIO_PDIR_PDI21_SHIFT                    (21U)
/*! PDI21 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK)

#define GPIO_PDIR_PDI22_MASK                     (0x400000U)
#define GPIO_PDIR_PDI22_SHIFT                    (22U)
/*! PDI22 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK)

#define GPIO_PDIR_PDI23_MASK                     (0x800000U)
#define GPIO_PDIR_PDI23_SHIFT                    (23U)
/*! PDI23 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK)

#define GPIO_PDIR_PDI24_MASK                     (0x1000000U)
#define GPIO_PDIR_PDI24_SHIFT                    (24U)
/*! PDI24 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK)

#define GPIO_PDIR_PDI25_MASK                     (0x2000000U)
#define GPIO_PDIR_PDI25_SHIFT                    (25U)
/*! PDI25 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK)

#define GPIO_PDIR_PDI26_MASK                     (0x4000000U)
#define GPIO_PDIR_PDI26_SHIFT                    (26U)
/*! PDI26 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK)

#define GPIO_PDIR_PDI27_MASK                     (0x8000000U)
#define GPIO_PDIR_PDI27_SHIFT                    (27U)
/*! PDI27 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK)

#define GPIO_PDIR_PDI28_MASK                     (0x10000000U)
#define GPIO_PDIR_PDI28_SHIFT                    (28U)
/*! PDI28 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK)

#define GPIO_PDIR_PDI29_MASK                     (0x20000000U)
#define GPIO_PDIR_PDI29_SHIFT                    (29U)
/*! PDI29 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK)

#define GPIO_PDIR_PDI30_MASK                     (0x40000000U)
#define GPIO_PDIR_PDI30_SHIFT                    (30U)
/*! PDI30 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK)

#define GPIO_PDIR_PDI31_MASK                     (0x80000000U)
#define GPIO_PDIR_PDI31_SHIFT                    (31U)
/*! PDI31 - Port Data Input
 *  0b0..Logic 0
 *  0b1..Logic 1
 */
#define GPIO_PDIR_PDI31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK)
/*! @} */

/*! @name PDDR - Port Data Direction */
/*! @{ */

#define GPIO_PDDR_PDD0_MASK                      (0x1U)
#define GPIO_PDDR_PDD0_SHIFT                     (0U)
/*! PDD0 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK)

#define GPIO_PDDR_PDD1_MASK                      (0x2U)
#define GPIO_PDDR_PDD1_SHIFT                     (1U)
/*! PDD1 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK)

#define GPIO_PDDR_PDD2_MASK                      (0x4U)
#define GPIO_PDDR_PDD2_SHIFT                     (2U)
/*! PDD2 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK)

#define GPIO_PDDR_PDD3_MASK                      (0x8U)
#define GPIO_PDDR_PDD3_SHIFT                     (3U)
/*! PDD3 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK)

#define GPIO_PDDR_PDD4_MASK                      (0x10U)
#define GPIO_PDDR_PDD4_SHIFT                     (4U)
/*! PDD4 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK)

#define GPIO_PDDR_PDD5_MASK                      (0x20U)
#define GPIO_PDDR_PDD5_SHIFT                     (5U)
/*! PDD5 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK)

#define GPIO_PDDR_PDD6_MASK                      (0x40U)
#define GPIO_PDDR_PDD6_SHIFT                     (6U)
/*! PDD6 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK)

#define GPIO_PDDR_PDD7_MASK                      (0x80U)
#define GPIO_PDDR_PDD7_SHIFT                     (7U)
/*! PDD7 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK)

#define GPIO_PDDR_PDD8_MASK                      (0x100U)
#define GPIO_PDDR_PDD8_SHIFT                     (8U)
/*! PDD8 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK)

#define GPIO_PDDR_PDD9_MASK                      (0x200U)
#define GPIO_PDDR_PDD9_SHIFT                     (9U)
/*! PDD9 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK)

#define GPIO_PDDR_PDD10_MASK                     (0x400U)
#define GPIO_PDDR_PDD10_SHIFT                    (10U)
/*! PDD10 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK)

#define GPIO_PDDR_PDD11_MASK                     (0x800U)
#define GPIO_PDDR_PDD11_SHIFT                    (11U)
/*! PDD11 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK)

#define GPIO_PDDR_PDD12_MASK                     (0x1000U)
#define GPIO_PDDR_PDD12_SHIFT                    (12U)
/*! PDD12 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK)

#define GPIO_PDDR_PDD13_MASK                     (0x2000U)
#define GPIO_PDDR_PDD13_SHIFT                    (13U)
/*! PDD13 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK)

#define GPIO_PDDR_PDD14_MASK                     (0x4000U)
#define GPIO_PDDR_PDD14_SHIFT                    (14U)
/*! PDD14 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK)

#define GPIO_PDDR_PDD15_MASK                     (0x8000U)
#define GPIO_PDDR_PDD15_SHIFT                    (15U)
/*! PDD15 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK)

#define GPIO_PDDR_PDD16_MASK                     (0x10000U)
#define GPIO_PDDR_PDD16_SHIFT                    (16U)
/*! PDD16 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK)

#define GPIO_PDDR_PDD17_MASK                     (0x20000U)
#define GPIO_PDDR_PDD17_SHIFT                    (17U)
/*! PDD17 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK)

#define GPIO_PDDR_PDD18_MASK                     (0x40000U)
#define GPIO_PDDR_PDD18_SHIFT                    (18U)
/*! PDD18 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK)

#define GPIO_PDDR_PDD19_MASK                     (0x80000U)
#define GPIO_PDDR_PDD19_SHIFT                    (19U)
/*! PDD19 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK)

#define GPIO_PDDR_PDD20_MASK                     (0x100000U)
#define GPIO_PDDR_PDD20_SHIFT                    (20U)
/*! PDD20 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK)

#define GPIO_PDDR_PDD21_MASK                     (0x200000U)
#define GPIO_PDDR_PDD21_SHIFT                    (21U)
/*! PDD21 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK)

#define GPIO_PDDR_PDD22_MASK                     (0x400000U)
#define GPIO_PDDR_PDD22_SHIFT                    (22U)
/*! PDD22 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK)

#define GPIO_PDDR_PDD23_MASK                     (0x800000U)
#define GPIO_PDDR_PDD23_SHIFT                    (23U)
/*! PDD23 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK)

#define GPIO_PDDR_PDD24_MASK                     (0x1000000U)
#define GPIO_PDDR_PDD24_SHIFT                    (24U)
/*! PDD24 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK)

#define GPIO_PDDR_PDD25_MASK                     (0x2000000U)
#define GPIO_PDDR_PDD25_SHIFT                    (25U)
/*! PDD25 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK)

#define GPIO_PDDR_PDD26_MASK                     (0x4000000U)
#define GPIO_PDDR_PDD26_SHIFT                    (26U)
/*! PDD26 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK)

#define GPIO_PDDR_PDD27_MASK                     (0x8000000U)
#define GPIO_PDDR_PDD27_SHIFT                    (27U)
/*! PDD27 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK)

#define GPIO_PDDR_PDD28_MASK                     (0x10000000U)
#define GPIO_PDDR_PDD28_SHIFT                    (28U)
/*! PDD28 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK)

#define GPIO_PDDR_PDD29_MASK                     (0x20000000U)
#define GPIO_PDDR_PDD29_SHIFT                    (29U)
/*! PDD29 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK)

#define GPIO_PDDR_PDD30_MASK                     (0x40000000U)
#define GPIO_PDDR_PDD30_SHIFT                    (30U)
/*! PDD30 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK)

#define GPIO_PDDR_PDD31_MASK                     (0x80000000U)
#define GPIO_PDDR_PDD31_SHIFT                    (31U)
/*! PDD31 - Port Data Direction
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_PDDR_PDD31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK)
/*! @} */

/*! @name PIDR - Port Input Disable */
/*! @{ */

#define GPIO_PIDR_PID0_MASK                      (0x1U)
#define GPIO_PIDR_PID0_SHIFT                     (0U)
/*! PID0 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK)

#define GPIO_PIDR_PID1_MASK                      (0x2U)
#define GPIO_PIDR_PID1_SHIFT                     (1U)
/*! PID1 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK)

#define GPIO_PIDR_PID2_MASK                      (0x4U)
#define GPIO_PIDR_PID2_SHIFT                     (2U)
/*! PID2 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK)

#define GPIO_PIDR_PID3_MASK                      (0x8U)
#define GPIO_PIDR_PID3_SHIFT                     (3U)
/*! PID3 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK)

#define GPIO_PIDR_PID4_MASK                      (0x10U)
#define GPIO_PIDR_PID4_SHIFT                     (4U)
/*! PID4 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK)

#define GPIO_PIDR_PID5_MASK                      (0x20U)
#define GPIO_PIDR_PID5_SHIFT                     (5U)
/*! PID5 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK)

#define GPIO_PIDR_PID6_MASK                      (0x40U)
#define GPIO_PIDR_PID6_SHIFT                     (6U)
/*! PID6 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK)

#define GPIO_PIDR_PID7_MASK                      (0x80U)
#define GPIO_PIDR_PID7_SHIFT                     (7U)
/*! PID7 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK)

#define GPIO_PIDR_PID8_MASK                      (0x100U)
#define GPIO_PIDR_PID8_SHIFT                     (8U)
/*! PID8 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK)

#define GPIO_PIDR_PID9_MASK                      (0x200U)
#define GPIO_PIDR_PID9_SHIFT                     (9U)
/*! PID9 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK)

#define GPIO_PIDR_PID10_MASK                     (0x400U)
#define GPIO_PIDR_PID10_SHIFT                    (10U)
/*! PID10 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK)

#define GPIO_PIDR_PID11_MASK                     (0x800U)
#define GPIO_PIDR_PID11_SHIFT                    (11U)
/*! PID11 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK)

#define GPIO_PIDR_PID12_MASK                     (0x1000U)
#define GPIO_PIDR_PID12_SHIFT                    (12U)
/*! PID12 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK)

#define GPIO_PIDR_PID13_MASK                     (0x2000U)
#define GPIO_PIDR_PID13_SHIFT                    (13U)
/*! PID13 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK)

#define GPIO_PIDR_PID14_MASK                     (0x4000U)
#define GPIO_PIDR_PID14_SHIFT                    (14U)
/*! PID14 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK)

#define GPIO_PIDR_PID15_MASK                     (0x8000U)
#define GPIO_PIDR_PID15_SHIFT                    (15U)
/*! PID15 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK)

#define GPIO_PIDR_PID16_MASK                     (0x10000U)
#define GPIO_PIDR_PID16_SHIFT                    (16U)
/*! PID16 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK)

#define GPIO_PIDR_PID17_MASK                     (0x20000U)
#define GPIO_PIDR_PID17_SHIFT                    (17U)
/*! PID17 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK)

#define GPIO_PIDR_PID18_MASK                     (0x40000U)
#define GPIO_PIDR_PID18_SHIFT                    (18U)
/*! PID18 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK)

#define GPIO_PIDR_PID19_MASK                     (0x80000U)
#define GPIO_PIDR_PID19_SHIFT                    (19U)
/*! PID19 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK)

#define GPIO_PIDR_PID20_MASK                     (0x100000U)
#define GPIO_PIDR_PID20_SHIFT                    (20U)
/*! PID20 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK)

#define GPIO_PIDR_PID21_MASK                     (0x200000U)
#define GPIO_PIDR_PID21_SHIFT                    (21U)
/*! PID21 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK)

#define GPIO_PIDR_PID22_MASK                     (0x400000U)
#define GPIO_PIDR_PID22_SHIFT                    (22U)
/*! PID22 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK)

#define GPIO_PIDR_PID23_MASK                     (0x800000U)
#define GPIO_PIDR_PID23_SHIFT                    (23U)
/*! PID23 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK)

#define GPIO_PIDR_PID24_MASK                     (0x1000000U)
#define GPIO_PIDR_PID24_SHIFT                    (24U)
/*! PID24 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK)

#define GPIO_PIDR_PID25_MASK                     (0x2000000U)
#define GPIO_PIDR_PID25_SHIFT                    (25U)
/*! PID25 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK)

#define GPIO_PIDR_PID26_MASK                     (0x4000000U)
#define GPIO_PIDR_PID26_SHIFT                    (26U)
/*! PID26 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK)

#define GPIO_PIDR_PID27_MASK                     (0x8000000U)
#define GPIO_PIDR_PID27_SHIFT                    (27U)
/*! PID27 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK)

#define GPIO_PIDR_PID28_MASK                     (0x10000000U)
#define GPIO_PIDR_PID28_SHIFT                    (28U)
/*! PID28 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK)

#define GPIO_PIDR_PID29_MASK                     (0x20000000U)
#define GPIO_PIDR_PID29_SHIFT                    (29U)
/*! PID29 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK)

#define GPIO_PIDR_PID30_MASK                     (0x40000000U)
#define GPIO_PIDR_PID30_SHIFT                    (30U)
/*! PID30 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK)

#define GPIO_PIDR_PID31_MASK                     (0x80000000U)
#define GPIO_PIDR_PID31_SHIFT                    (31U)
/*! PID31 - Port Input Disable
 *  0b0..Configured for general-purpose input
 *  0b1..Disabled for general-purpose input
 */
#define GPIO_PIDR_PID31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK)
/*! @} */

/*! @name PDR - Pin Data */
/*! @{ */

#define GPIO_PDR_PD_MASK                         (0x1U)
#define GPIO_PDR_PD_SHIFT                        (0U)
/*! PD - Pin Data (I/O)
 *  0b0..Logic zero
 *  0b1..Logic one
 */
#define GPIO_PDR_PD(x)                           (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK)
/*! @} */

/* The count of GPIO_PDR */
#define GPIO_PDR_COUNT                           (32U)

/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */
/*! @{ */

#define GPIO_ICR_IRQC_MASK                       (0xF0000U)
#define GPIO_ICR_IRQC_SHIFT                      (16U)
/*! IRQC - Interrupt Configuration
 *  0b0000..ISF is disabled
 *  0b0001..ISF and DMA request on rising edge
 *  0b0010..ISF and DMA request on falling edge
 *  0b0011..ISF and DMA request on either edge
 *  0b0100..Reserved
 *  0b0101..ISF sets on rising edge
 *  0b0110..ISF sets on falling edge
 *  0b0111..ISF sets on either edge
 *  0b1000..ISF and interrupt when logic 0
 *  0b1001..ISF and interrupt on rising edge
 *  0b1010..ISF and interrupt on falling edge
 *  0b1011..ISF and Interrupt on either edge
 *  0b1100..ISF and interrupt when logic 1
 *  0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers
 *          to generate the output trigger for use by other peripherals)
 *  0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other
 *          enabled triggers to generate the output trigger for use by other peripherals)
 *  0b1111..Reserved
 */
#define GPIO_ICR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK)

#define GPIO_ICR_IRQS_MASK                       (0x100000U)
#define GPIO_ICR_IRQS_SHIFT                      (20U)
/*! IRQS - Interrupt Select
 *  0b0..Interrupt, trigger output, or DMA request 0
 *  0b1..Interrupt, trigger output, or DMA request 1
 */
#define GPIO_ICR_IRQS(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK)

#define GPIO_ICR_LK_MASK                         (0x800000U)
#define GPIO_ICR_LK_SHIFT                        (23U)
/*! LK - Lock
 *  0b0..Not locked
 *  0b1..Locked
 */
#define GPIO_ICR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK)

#define GPIO_ICR_ISF_MASK                        (0x1000000U)
#define GPIO_ICR_ISF_SHIFT                       (24U)
/*! ISF - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ICR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK)
/*! @} */

/* The count of GPIO_ICR */
#define GPIO_ICR_COUNT                           (32U)

/*! @name GICLR - Global Interrupt Control Low */
/*! @{ */

#define GPIO_GICLR_GIWE0_MASK                    (0x1U)
#define GPIO_GICLR_GIWE0_SHIFT                   (0U)
/*! GIWE0 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE0(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK)

#define GPIO_GICLR_GIWE1_MASK                    (0x2U)
#define GPIO_GICLR_GIWE1_SHIFT                   (1U)
/*! GIWE1 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE1(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK)

#define GPIO_GICLR_GIWE2_MASK                    (0x4U)
#define GPIO_GICLR_GIWE2_SHIFT                   (2U)
/*! GIWE2 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE2(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK)

#define GPIO_GICLR_GIWE3_MASK                    (0x8U)
#define GPIO_GICLR_GIWE3_SHIFT                   (3U)
/*! GIWE3 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE3(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK)

#define GPIO_GICLR_GIWE4_MASK                    (0x10U)
#define GPIO_GICLR_GIWE4_SHIFT                   (4U)
/*! GIWE4 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE4(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK)

#define GPIO_GICLR_GIWE5_MASK                    (0x20U)
#define GPIO_GICLR_GIWE5_SHIFT                   (5U)
/*! GIWE5 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE5(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK)

#define GPIO_GICLR_GIWE6_MASK                    (0x40U)
#define GPIO_GICLR_GIWE6_SHIFT                   (6U)
/*! GIWE6 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE6(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK)

#define GPIO_GICLR_GIWE7_MASK                    (0x80U)
#define GPIO_GICLR_GIWE7_SHIFT                   (7U)
/*! GIWE7 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE7(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK)

#define GPIO_GICLR_GIWE8_MASK                    (0x100U)
#define GPIO_GICLR_GIWE8_SHIFT                   (8U)
/*! GIWE8 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE8(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK)

#define GPIO_GICLR_GIWE9_MASK                    (0x200U)
#define GPIO_GICLR_GIWE9_SHIFT                   (9U)
/*! GIWE9 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE9(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK)

#define GPIO_GICLR_GIWE10_MASK                   (0x400U)
#define GPIO_GICLR_GIWE10_SHIFT                  (10U)
/*! GIWE10 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE10(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK)

#define GPIO_GICLR_GIWE11_MASK                   (0x800U)
#define GPIO_GICLR_GIWE11_SHIFT                  (11U)
/*! GIWE11 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE11(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK)

#define GPIO_GICLR_GIWE12_MASK                   (0x1000U)
#define GPIO_GICLR_GIWE12_SHIFT                  (12U)
/*! GIWE12 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE12(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK)

#define GPIO_GICLR_GIWE13_MASK                   (0x2000U)
#define GPIO_GICLR_GIWE13_SHIFT                  (13U)
/*! GIWE13 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE13(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK)

#define GPIO_GICLR_GIWE14_MASK                   (0x4000U)
#define GPIO_GICLR_GIWE14_SHIFT                  (14U)
/*! GIWE14 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE14(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK)

#define GPIO_GICLR_GIWE15_MASK                   (0x8000U)
#define GPIO_GICLR_GIWE15_SHIFT                  (15U)
/*! GIWE15 - Global Interrupt Write Enable
 *  0b0..Not updated
 *  0b1..Updated
 */
#define GPIO_GICLR_GIWE15(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK)

#define GPIO_GICLR_GIWD_MASK                     (0xFFFF0000U)
#define GPIO_GICLR_GIWD_SHIFT                    (16U)
/*! GIWD - Global Interrupt Write Data */
#define GPIO_GICLR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK)
/*! @} */

/*! @name GICHR - Global Interrupt Control High */
/*! @{ */

#define GPIO_GICHR_GIWE16_MASK                   (0x1U)
#define GPIO_GICHR_GIWE16_SHIFT                  (0U)
/*! GIWE16 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE16(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK)

#define GPIO_GICHR_GIWE17_MASK                   (0x2U)
#define GPIO_GICHR_GIWE17_SHIFT                  (1U)
/*! GIWE17 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE17(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK)

#define GPIO_GICHR_GIWE18_MASK                   (0x4U)
#define GPIO_GICHR_GIWE18_SHIFT                  (2U)
/*! GIWE18 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE18(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK)

#define GPIO_GICHR_GIWE19_MASK                   (0x8U)
#define GPIO_GICHR_GIWE19_SHIFT                  (3U)
/*! GIWE19 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE19(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK)

#define GPIO_GICHR_GIWE20_MASK                   (0x10U)
#define GPIO_GICHR_GIWE20_SHIFT                  (4U)
/*! GIWE20 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE20(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK)

#define GPIO_GICHR_GIWE21_MASK                   (0x20U)
#define GPIO_GICHR_GIWE21_SHIFT                  (5U)
/*! GIWE21 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE21(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK)

#define GPIO_GICHR_GIWE22_MASK                   (0x40U)
#define GPIO_GICHR_GIWE22_SHIFT                  (6U)
/*! GIWE22 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE22(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK)

#define GPIO_GICHR_GIWE23_MASK                   (0x80U)
#define GPIO_GICHR_GIWE23_SHIFT                  (7U)
/*! GIWE23 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE23(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK)

#define GPIO_GICHR_GIWE24_MASK                   (0x100U)
#define GPIO_GICHR_GIWE24_SHIFT                  (8U)
/*! GIWE24 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE24(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK)

#define GPIO_GICHR_GIWE25_MASK                   (0x200U)
#define GPIO_GICHR_GIWE25_SHIFT                  (9U)
/*! GIWE25 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE25(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK)

#define GPIO_GICHR_GIWE26_MASK                   (0x400U)
#define GPIO_GICHR_GIWE26_SHIFT                  (10U)
/*! GIWE26 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE26(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK)

#define GPIO_GICHR_GIWE27_MASK                   (0x800U)
#define GPIO_GICHR_GIWE27_SHIFT                  (11U)
/*! GIWE27 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE27(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK)

#define GPIO_GICHR_GIWE28_MASK                   (0x1000U)
#define GPIO_GICHR_GIWE28_SHIFT                  (12U)
/*! GIWE28 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE28(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK)

#define GPIO_GICHR_GIWE29_MASK                   (0x2000U)
#define GPIO_GICHR_GIWE29_SHIFT                  (13U)
/*! GIWE29 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE29(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK)

#define GPIO_GICHR_GIWE30_MASK                   (0x4000U)
#define GPIO_GICHR_GIWE30_SHIFT                  (14U)
/*! GIWE30 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE30(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK)

#define GPIO_GICHR_GIWE31_MASK                   (0x8000U)
#define GPIO_GICHR_GIWE31_SHIFT                  (15U)
/*! GIWE31 - Global Interrupt Write Enable
 *  0b0..Not updated.
 *  0b1..Updated
 */
#define GPIO_GICHR_GIWE31(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK)

#define GPIO_GICHR_GIWD_MASK                     (0xFFFF0000U)
#define GPIO_GICHR_GIWD_SHIFT                    (16U)
/*! GIWD - Global Interrupt Write Data */
#define GPIO_GICHR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK)
/*! @} */

/*! @name ISFR - Interrupt Status Flag */
/*! @{ */

#define GPIO_ISFR_ISF0_MASK                      (0x1U)
#define GPIO_ISFR_ISF0_SHIFT                     (0U)
/*! ISF0 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK)

#define GPIO_ISFR_ISF1_MASK                      (0x2U)
#define GPIO_ISFR_ISF1_SHIFT                     (1U)
/*! ISF1 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK)

#define GPIO_ISFR_ISF2_MASK                      (0x4U)
#define GPIO_ISFR_ISF2_SHIFT                     (2U)
/*! ISF2 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK)

#define GPIO_ISFR_ISF3_MASK                      (0x8U)
#define GPIO_ISFR_ISF3_SHIFT                     (3U)
/*! ISF3 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK)

#define GPIO_ISFR_ISF4_MASK                      (0x10U)
#define GPIO_ISFR_ISF4_SHIFT                     (4U)
/*! ISF4 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK)

#define GPIO_ISFR_ISF5_MASK                      (0x20U)
#define GPIO_ISFR_ISF5_SHIFT                     (5U)
/*! ISF5 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK)

#define GPIO_ISFR_ISF6_MASK                      (0x40U)
#define GPIO_ISFR_ISF6_SHIFT                     (6U)
/*! ISF6 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK)

#define GPIO_ISFR_ISF7_MASK                      (0x80U)
#define GPIO_ISFR_ISF7_SHIFT                     (7U)
/*! ISF7 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK)

#define GPIO_ISFR_ISF8_MASK                      (0x100U)
#define GPIO_ISFR_ISF8_SHIFT                     (8U)
/*! ISF8 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK)

#define GPIO_ISFR_ISF9_MASK                      (0x200U)
#define GPIO_ISFR_ISF9_SHIFT                     (9U)
/*! ISF9 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK)

#define GPIO_ISFR_ISF10_MASK                     (0x400U)
#define GPIO_ISFR_ISF10_SHIFT                    (10U)
/*! ISF10 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK)

#define GPIO_ISFR_ISF11_MASK                     (0x800U)
#define GPIO_ISFR_ISF11_SHIFT                    (11U)
/*! ISF11 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK)

#define GPIO_ISFR_ISF12_MASK                     (0x1000U)
#define GPIO_ISFR_ISF12_SHIFT                    (12U)
/*! ISF12 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK)

#define GPIO_ISFR_ISF13_MASK                     (0x2000U)
#define GPIO_ISFR_ISF13_SHIFT                    (13U)
/*! ISF13 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK)

#define GPIO_ISFR_ISF14_MASK                     (0x4000U)
#define GPIO_ISFR_ISF14_SHIFT                    (14U)
/*! ISF14 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK)

#define GPIO_ISFR_ISF15_MASK                     (0x8000U)
#define GPIO_ISFR_ISF15_SHIFT                    (15U)
/*! ISF15 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK)

#define GPIO_ISFR_ISF16_MASK                     (0x10000U)
#define GPIO_ISFR_ISF16_SHIFT                    (16U)
/*! ISF16 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK)

#define GPIO_ISFR_ISF17_MASK                     (0x20000U)
#define GPIO_ISFR_ISF17_SHIFT                    (17U)
/*! ISF17 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK)

#define GPIO_ISFR_ISF18_MASK                     (0x40000U)
#define GPIO_ISFR_ISF18_SHIFT                    (18U)
/*! ISF18 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK)

#define GPIO_ISFR_ISF19_MASK                     (0x80000U)
#define GPIO_ISFR_ISF19_SHIFT                    (19U)
/*! ISF19 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK)

#define GPIO_ISFR_ISF20_MASK                     (0x100000U)
#define GPIO_ISFR_ISF20_SHIFT                    (20U)
/*! ISF20 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK)

#define GPIO_ISFR_ISF21_MASK                     (0x200000U)
#define GPIO_ISFR_ISF21_SHIFT                    (21U)
/*! ISF21 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK)

#define GPIO_ISFR_ISF22_MASK                     (0x400000U)
#define GPIO_ISFR_ISF22_SHIFT                    (22U)
/*! ISF22 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK)

#define GPIO_ISFR_ISF23_MASK                     (0x800000U)
#define GPIO_ISFR_ISF23_SHIFT                    (23U)
/*! ISF23 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK)

#define GPIO_ISFR_ISF24_MASK                     (0x1000000U)
#define GPIO_ISFR_ISF24_SHIFT                    (24U)
/*! ISF24 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK)

#define GPIO_ISFR_ISF25_MASK                     (0x2000000U)
#define GPIO_ISFR_ISF25_SHIFT                    (25U)
/*! ISF25 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK)

#define GPIO_ISFR_ISF26_MASK                     (0x4000000U)
#define GPIO_ISFR_ISF26_SHIFT                    (26U)
/*! ISF26 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK)

#define GPIO_ISFR_ISF27_MASK                     (0x8000000U)
#define GPIO_ISFR_ISF27_SHIFT                    (27U)
/*! ISF27 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK)

#define GPIO_ISFR_ISF28_MASK                     (0x10000000U)
#define GPIO_ISFR_ISF28_SHIFT                    (28U)
/*! ISF28 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK)

#define GPIO_ISFR_ISF29_MASK                     (0x20000000U)
#define GPIO_ISFR_ISF29_SHIFT                    (29U)
/*! ISF29 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK)

#define GPIO_ISFR_ISF30_MASK                     (0x40000000U)
#define GPIO_ISFR_ISF30_SHIFT                    (30U)
/*! ISF30 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK)

#define GPIO_ISFR_ISF31_MASK                     (0x80000000U)
#define GPIO_ISFR_ISF31_SHIFT                    (31U)
/*! ISF31 - Interrupt Status Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define GPIO_ISFR_ISF31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK)
/*! @} */

/* The count of GPIO_ISFR */
#define GPIO_ISFR_COUNT                          (2U)


/*!
 * @}
 */ /* end of group GPIO_Register_Masks */


/* GPIO - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral GPIO0 base address */
  #define GPIO0_BASE                               (0x50100000u)
  /** Peripheral GPIO0 base address */
  #define GPIO0_BASE_NS                            (0x40100000u)
  /** Peripheral GPIO0 base pointer */
  #define GPIO0                                    ((GPIO_Type *)GPIO0_BASE)
  /** Peripheral GPIO0 base pointer */
  #define GPIO0_NS                                 ((GPIO_Type *)GPIO0_BASE_NS)
  /** Peripheral GPIO1 base address */
  #define GPIO1_BASE                               (0x50102000u)
  /** Peripheral GPIO1 base address */
  #define GPIO1_BASE_NS                            (0x40102000u)
  /** Peripheral GPIO1 base pointer */
  #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
  /** Peripheral GPIO1 base pointer */
  #define GPIO1_NS                                 ((GPIO_Type *)GPIO1_BASE_NS)
  /** Peripheral GPIO2 base address */
  #define GPIO2_BASE                               (0x50104000u)
  /** Peripheral GPIO2 base address */
  #define GPIO2_BASE_NS                            (0x40104000u)
  /** Peripheral GPIO2 base pointer */
  #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
  /** Peripheral GPIO2 base pointer */
  #define GPIO2_NS                                 ((GPIO_Type *)GPIO2_BASE_NS)
  /** Peripheral GPIO3 base address */
  #define GPIO3_BASE                               (0x50106000u)
  /** Peripheral GPIO3 base address */
  #define GPIO3_BASE_NS                            (0x40106000u)
  /** Peripheral GPIO3 base pointer */
  #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
  /** Peripheral GPIO3 base pointer */
  #define GPIO3_NS                                 ((GPIO_Type *)GPIO3_BASE_NS)
  /** Peripheral GPIO4 base address */
  #define GPIO4_BASE                               (0x50108000u)
  /** Peripheral GPIO4 base address */
  #define GPIO4_BASE_NS                            (0x40108000u)
  /** Peripheral GPIO4 base pointer */
  #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
  /** Peripheral GPIO4 base pointer */
  #define GPIO4_NS                                 ((GPIO_Type *)GPIO4_BASE_NS)
  /** Peripheral GPIO5 base address */
  #define GPIO5_BASE                               (0x5010A000u)
  /** Peripheral GPIO5 base address */
  #define GPIO5_BASE_NS                            (0x4010A000u)
  /** Peripheral GPIO5 base pointer */
  #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
  /** Peripheral GPIO5 base pointer */
  #define GPIO5_NS                                 ((GPIO_Type *)GPIO5_BASE_NS)
  /** Peripheral GPIO6 base address */
  #define GPIO6_BASE                               (0x5010C000u)
  /** Peripheral GPIO6 base address */
  #define GPIO6_BASE_NS                            (0x4010C000u)
  /** Peripheral GPIO6 base pointer */
  #define GPIO6                                    ((GPIO_Type *)GPIO6_BASE)
  /** Peripheral GPIO6 base pointer */
  #define GPIO6_NS                                 ((GPIO_Type *)GPIO6_BASE_NS)
  /** Peripheral GPIO7 base address */
  #define GPIO7_BASE                               (0x5010E000u)
  /** Peripheral GPIO7 base address */
  #define GPIO7_BASE_NS                            (0x4010E000u)
  /** Peripheral GPIO7 base pointer */
  #define GPIO7                                    ((GPIO_Type *)GPIO7_BASE)
  /** Peripheral GPIO7 base pointer */
  #define GPIO7_NS                                 ((GPIO_Type *)GPIO7_BASE_NS)
  /** Peripheral GPIO0_ALIAS base address */
  #define GPIO0_ALIAS_BASE                         (0x50101000u)
  /** Peripheral GPIO0_ALIAS base address */
  #define GPIO0_ALIAS_BASE_NS                      (0x40101000u)
  /** Peripheral GPIO0_ALIAS base pointer */
  #define GPIO0_ALIAS                              ((GPIO_Type *)GPIO0_ALIAS_BASE)
  /** Peripheral GPIO0_ALIAS base pointer */
  #define GPIO0_ALIAS_NS                           ((GPIO_Type *)GPIO0_ALIAS_BASE_NS)
  /** Peripheral GPIO1_ALIAS base address */
  #define GPIO1_ALIAS_BASE                         (0x50103000u)
  /** Peripheral GPIO1_ALIAS base address */
  #define GPIO1_ALIAS_BASE_NS                      (0x40103000u)
  /** Peripheral GPIO1_ALIAS base pointer */
  #define GPIO1_ALIAS                              ((GPIO_Type *)GPIO1_ALIAS_BASE)
  /** Peripheral GPIO1_ALIAS base pointer */
  #define GPIO1_ALIAS_NS                           ((GPIO_Type *)GPIO1_ALIAS_BASE_NS)
  /** Peripheral GPIO2_ALIAS base address */
  #define GPIO2_ALIAS_BASE                         (0x50105000u)
  /** Peripheral GPIO2_ALIAS base address */
  #define GPIO2_ALIAS_BASE_NS                      (0x40105000u)
  /** Peripheral GPIO2_ALIAS base pointer */
  #define GPIO2_ALIAS                              ((GPIO_Type *)GPIO2_ALIAS_BASE)
  /** Peripheral GPIO2_ALIAS base pointer */
  #define GPIO2_ALIAS_NS                           ((GPIO_Type *)GPIO2_ALIAS_BASE_NS)
  /** Peripheral GPIO3_ALIAS base address */
  #define GPIO3_ALIAS_BASE                         (0x50107000u)
  /** Peripheral GPIO3_ALIAS base address */
  #define GPIO3_ALIAS_BASE_NS                      (0x40107000u)
  /** Peripheral GPIO3_ALIAS base pointer */
  #define GPIO3_ALIAS                              ((GPIO_Type *)GPIO3_ALIAS_BASE)
  /** Peripheral GPIO3_ALIAS base pointer */
  #define GPIO3_ALIAS_NS                           ((GPIO_Type *)GPIO3_ALIAS_BASE_NS)
  /** Peripheral GPIO4_ALIAS base address */
  #define GPIO4_ALIAS_BASE                         (0x50109000u)
  /** Peripheral GPIO4_ALIAS base address */
  #define GPIO4_ALIAS_BASE_NS                      (0x40109000u)
  /** Peripheral GPIO4_ALIAS base pointer */
  #define GPIO4_ALIAS                              ((GPIO_Type *)GPIO4_ALIAS_BASE)
  /** Peripheral GPIO4_ALIAS base pointer */
  #define GPIO4_ALIAS_NS                           ((GPIO_Type *)GPIO4_ALIAS_BASE_NS)
  /** Peripheral GPIO5_ALIAS base address */
  #define GPIO5_ALIAS_BASE                         (0x5010B000u)
  /** Peripheral GPIO5_ALIAS base address */
  #define GPIO5_ALIAS_BASE_NS                      (0x4010B000u)
  /** Peripheral GPIO5_ALIAS base pointer */
  #define GPIO5_ALIAS                              ((GPIO_Type *)GPIO5_ALIAS_BASE)
  /** Peripheral GPIO5_ALIAS base pointer */
  #define GPIO5_ALIAS_NS                           ((GPIO_Type *)GPIO5_ALIAS_BASE_NS)
  /** Peripheral GPIO6_ALIAS base address */
  #define GPIO6_ALIAS_BASE                         (0x5010D000u)
  /** Peripheral GPIO6_ALIAS base address */
  #define GPIO6_ALIAS_BASE_NS                      (0x4010D000u)
  /** Peripheral GPIO6_ALIAS base pointer */
  #define GPIO6_ALIAS                              ((GPIO_Type *)GPIO6_ALIAS_BASE)
  /** Peripheral GPIO6_ALIAS base pointer */
  #define GPIO6_ALIAS_NS                           ((GPIO_Type *)GPIO6_ALIAS_BASE_NS)
  /** Peripheral GPIO7_ALIAS base address */
  #define GPIO7_ALIAS_BASE                         (0x5010F000u)
  /** Peripheral GPIO7_ALIAS base address */
  #define GPIO7_ALIAS_BASE_NS                      (0x4010F000u)
  /** Peripheral GPIO7_ALIAS base pointer */
  #define GPIO7_ALIAS                              ((GPIO_Type *)GPIO7_ALIAS_BASE)
  /** Peripheral GPIO7_ALIAS base pointer */
  #define GPIO7_ALIAS_NS                           ((GPIO_Type *)GPIO7_ALIAS_BASE_NS)
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS                          { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, 0u, 0u, 0u, GPIO0_ALIAS_BASE, GPIO1_ALIAS_BASE, GPIO2_ALIAS_BASE, GPIO3_ALIAS_BASE, GPIO4_ALIAS_BASE, GPIO5_ALIAS_BASE, GPIO6_ALIAS_BASE, GPIO7_ALIAS_BASE }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS                           { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, (GPIO_Type *)0u, (GPIO_Type *)0u, (GPIO_Type *)0u, GPIO0_ALIAS, GPIO1_ALIAS, GPIO2_ALIAS, GPIO3_ALIAS, GPIO4_ALIAS, GPIO5_ALIAS, GPIO6_ALIAS, GPIO7_ALIAS }
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS_NS                       { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO6_BASE_NS, GPIO7_BASE_NS, 0u, 0u, 0u, GPIO0_ALIAS_BASE_NS, GPIO1_ALIAS_BASE_NS, GPIO2_ALIAS_BASE_NS, GPIO3_ALIAS_BASE_NS, GPIO4_ALIAS_BASE_NS, GPIO5_ALIAS_BASE_NS, GPIO6_ALIAS_BASE_NS, GPIO7_ALIAS_BASE_NS }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS_NS                        { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO6_NS, GPIO7_NS, (GPIO_Type *)0u, (GPIO_Type *)0u, (GPIO_Type *)0u, GPIO0_ALIAS_NS, GPIO1_ALIAS_NS, GPIO2_ALIAS_NS, GPIO3_ALIAS_NS, GPIO4_ALIAS_NS, GPIO5_ALIAS_NS, GPIO6_ALIAS_NS, GPIO7_ALIAS_NS }
#else
  /** Peripheral GPIO0 base address */
  #define GPIO0_BASE                               (0x40100000u)
  /** Peripheral GPIO0 base pointer */
  #define GPIO0                                    ((GPIO_Type *)GPIO0_BASE)
  /** Peripheral GPIO1 base address */
  #define GPIO1_BASE                               (0x40102000u)
  /** Peripheral GPIO1 base pointer */
  #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
  /** Peripheral GPIO2 base address */
  #define GPIO2_BASE                               (0x40104000u)
  /** Peripheral GPIO2 base pointer */
  #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
  /** Peripheral GPIO3 base address */
  #define GPIO3_BASE                               (0x40106000u)
  /** Peripheral GPIO3 base pointer */
  #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
  /** Peripheral GPIO4 base address */
  #define GPIO4_BASE                               (0x40108000u)
  /** Peripheral GPIO4 base pointer */
  #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
  /** Peripheral GPIO5 base address */
  #define GPIO5_BASE                               (0x4010A000u)
  /** Peripheral GPIO5 base pointer */
  #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
  /** Peripheral GPIO6 base address */
  #define GPIO6_BASE                               (0x4010C000u)
  /** Peripheral GPIO6 base pointer */
  #define GPIO6                                    ((GPIO_Type *)GPIO6_BASE)
  /** Peripheral GPIO7 base address */
  #define GPIO7_BASE                               (0x4010E000u)
  /** Peripheral GPIO7 base pointer */
  #define GPIO7                                    ((GPIO_Type *)GPIO7_BASE)
  /** Peripheral GPIO0_ALIAS base address */
  #define GPIO0_ALIAS_BASE                         (0x40101000u)
  /** Peripheral GPIO0_ALIAS base pointer */
  #define GPIO0_ALIAS                              ((GPIO_Type *)GPIO0_ALIAS_BASE)
  /** Peripheral GPIO1_ALIAS base address */
  #define GPIO1_ALIAS_BASE                         (0x40103000u)
  /** Peripheral GPIO1_ALIAS base pointer */
  #define GPIO1_ALIAS                              ((GPIO_Type *)GPIO1_ALIAS_BASE)
  /** Peripheral GPIO2_ALIAS base address */
  #define GPIO2_ALIAS_BASE                         (0x40105000u)
  /** Peripheral GPIO2_ALIAS base pointer */
  #define GPIO2_ALIAS                              ((GPIO_Type *)GPIO2_ALIAS_BASE)
  /** Peripheral GPIO3_ALIAS base address */
  #define GPIO3_ALIAS_BASE                         (0x40107000u)
  /** Peripheral GPIO3_ALIAS base pointer */
  #define GPIO3_ALIAS                              ((GPIO_Type *)GPIO3_ALIAS_BASE)
  /** Peripheral GPIO4_ALIAS base address */
  #define GPIO4_ALIAS_BASE                         (0x40109000u)
  /** Peripheral GPIO4_ALIAS base pointer */
  #define GPIO4_ALIAS                              ((GPIO_Type *)GPIO4_ALIAS_BASE)
  /** Peripheral GPIO5_ALIAS base address */
  #define GPIO5_ALIAS_BASE                         (0x4010B000u)
  /** Peripheral GPIO5_ALIAS base pointer */
  #define GPIO5_ALIAS                              ((GPIO_Type *)GPIO5_ALIAS_BASE)
  /** Peripheral GPIO6_ALIAS base address */
  #define GPIO6_ALIAS_BASE                         (0x4010D000u)
  /** Peripheral GPIO6_ALIAS base pointer */
  #define GPIO6_ALIAS                              ((GPIO_Type *)GPIO6_ALIAS_BASE)
  /** Peripheral GPIO7_ALIAS base address */
  #define GPIO7_ALIAS_BASE                         (0x4010F000u)
  /** Peripheral GPIO7_ALIAS base pointer */
  #define GPIO7_ALIAS                              ((GPIO_Type *)GPIO7_ALIAS_BASE)
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS                          { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, 0u, 0u, 0u, GPIO0_ALIAS_BASE, GPIO1_ALIAS_BASE, GPIO2_ALIAS_BASE, GPIO3_ALIAS_BASE, GPIO4_ALIAS_BASE, GPIO5_ALIAS_BASE, GPIO6_ALIAS_BASE, GPIO7_ALIAS_BASE }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS                           { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, (GPIO_Type *)0u, (GPIO_Type *)0u, (GPIO_Type *)0u, GPIO0_ALIAS, GPIO1_ALIAS, GPIO2_ALIAS, GPIO3_ALIAS, GPIO4_ALIAS, GPIO5_ALIAS, GPIO6_ALIAS, GPIO7_ALIAS }
#endif
/* Interrupt vectors for the GPIO peripheral type */


/*!
 * @}
 */ /* end of group GPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2S Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
 * @{
 */

/** I2S - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t TCSR;                              /**< Transmit Control, offset: 0x8 */
  __IO uint32_t TCR1;                              /**< Transmit Configuration 1, offset: 0xC */
  __IO uint32_t TCR2;                              /**< Transmit Configuration 2, offset: 0x10 */
  __IO uint32_t TCR3;                              /**< Transmit Configuration 3, offset: 0x14 */
  __IO uint32_t TCR4;                              /**< Transmit Configuration 4, offset: 0x18 */
  __IO uint32_t TCR5;                              /**< Transmit Configuration 5, offset: 0x1C */
  __O  uint32_t TDR[1];                            /**< Transmit Data, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_0[28];
  __I  uint32_t TFR[1];                            /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_1[28];
  __IO uint32_t TMR;                               /**< Transmit Mask, offset: 0x60 */
       uint8_t RESERVED_2[12];
  __IO uint32_t TTCR;                              /**< Transmit Timestamp Control, offset: 0x70 */
  __I  uint32_t TTSR;                              /**< Transmit Timestamp, offset: 0x74 */
  __I  uint32_t TBCR;                              /**< Transmit Bit Count, offset: 0x78 */
  __I  uint32_t TBCTR;                             /**< Transmit Bit Count Timestamp, offset: 0x7C */
       uint8_t RESERVED_3[8];
  __IO uint32_t RCSR;                              /**< Receive Control, offset: 0x88 */
  __IO uint32_t RCR1;                              /**< Receive Configuration 1, offset: 0x8C */
  __IO uint32_t RCR2;                              /**< Receive Configuration 2, offset: 0x90 */
  __IO uint32_t RCR3;                              /**< Receive Configuration 3, offset: 0x94 */
  __IO uint32_t RCR4;                              /**< Receive Configuration 4, offset: 0x98 */
  __IO uint32_t RCR5;                              /**< Receive Configuration 5, offset: 0x9C */
  __I  uint32_t RDR[1];                            /**< Receive Data, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_4[28];
  __I  uint32_t RFR[1];                            /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */
       uint8_t RESERVED_5[28];
  __IO uint32_t RMR;                               /**< Receive Mask, offset: 0xE0 */
       uint8_t RESERVED_6[12];
  __IO uint32_t RTCR;                              /**< Receive Timestamp Control, offset: 0xF0 */
  __I  uint32_t RTSR;                              /**< Receive Timestamp, offset: 0xF4 */
  __I  uint32_t RBCR;                              /**< Receive Bit Count, offset: 0xF8 */
  __I  uint32_t RBCTR;                             /**< Receive Bit Count Timestamp, offset: 0xFC */
  __IO uint32_t MCR;                               /**< MCLK Control, offset: 0x100 */
} I2S_Type;

/* ----------------------------------------------------------------------------
   -- I2S Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Register_Masks I2S Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
#define I2S_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard feature set
 *  0b0000000000000010..Standard feature set with timestamp registers
 */
#define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)

#define I2S_VERID_MINOR_MASK                     (0xFF0000U)
#define I2S_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)

#define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
#define I2S_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define I2S_PARAM_DATALINE_MASK                  (0xFU)
#define I2S_PARAM_DATALINE_SHIFT                 (0U)
/*! DATALINE - Number of Data Lines */
#define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)

#define I2S_PARAM_FIFO_MASK                      (0xF00U)
#define I2S_PARAM_FIFO_SHIFT                     (8U)
/*! FIFO - FIFO Size */
#define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)

#define I2S_PARAM_FRAME_MASK                     (0xF0000U)
#define I2S_PARAM_FRAME_SHIFT                    (16U)
/*! FRAME - Frame Size */
#define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
/*! @} */

/*! @name TCSR - Transmit Control */
/*! @{ */

#define I2S_TCSR_FRDE_MASK                       (0x1U)
#define I2S_TCSR_FRDE_SHIFT                      (0U)
/*! FRDE - FIFO Request DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

#define I2S_TCSR_FWDE_MASK                       (0x2U)
#define I2S_TCSR_FWDE_SHIFT                      (1U)
/*! FWDE - FIFO Warning DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

#define I2S_TCSR_FRIE_MASK                       (0x100U)
#define I2S_TCSR_FRIE_SHIFT                      (8U)
/*! FRIE - FIFO Request Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

#define I2S_TCSR_FWIE_MASK                       (0x200U)
#define I2S_TCSR_FWIE_SHIFT                      (9U)
/*! FWIE - FIFO Warning Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

#define I2S_TCSR_FEIE_MASK                       (0x400U)
#define I2S_TCSR_FEIE_SHIFT                      (10U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

#define I2S_TCSR_SEIE_MASK                       (0x800U)
#define I2S_TCSR_SEIE_SHIFT                      (11U)
/*! SEIE - Sync Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

#define I2S_TCSR_WSIE_MASK                       (0x1000U)
#define I2S_TCSR_WSIE_SHIFT                      (12U)
/*! WSIE - Word Start Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

#define I2S_TCSR_FRF_MASK                        (0x10000U)
#define I2S_TCSR_FRF_SHIFT                       (16U)
/*! FRF - FIFO Request Flag
 *  0b0..Watermark not reached
 *  0b1..Watermark reached
 */
#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

#define I2S_TCSR_FWF_MASK                        (0x20000U)
#define I2S_TCSR_FWF_SHIFT                       (17U)
/*! FWF - FIFO Warning Flag
 *  0b0..Not empty
 *  0b1..Empty
 */
#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

#define I2S_TCSR_FEF_MASK                        (0x40000U)
#define I2S_TCSR_FEF_SHIFT                       (18U)
/*! FEF - FIFO Error Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

#define I2S_TCSR_SEF_MASK                        (0x80000U)
#define I2S_TCSR_SEF_SHIFT                       (19U)
/*! SEF - Sync Error Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

#define I2S_TCSR_WSF_MASK                        (0x100000U)
#define I2S_TCSR_WSF_SHIFT                       (20U)
/*! WSF - Word Start Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

#define I2S_TCSR_SR_MASK                         (0x1000000U)
#define I2S_TCSR_SR_SHIFT                        (24U)
/*! SR - Software Reset
 *  0b0..No effect
 *  0b1..Software reset
 */
#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

#define I2S_TCSR_FR_MASK                         (0x2000000U)
#define I2S_TCSR_FR_SHIFT                        (25U)
/*! FR - FIFO Reset
 *  0b0..No effect
 *  0b1..FIFO reset
 */
#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

#define I2S_TCSR_BCE_MASK                        (0x10000000U)
#define I2S_TCSR_BCE_SHIFT                       (28U)
/*! BCE - Bit Clock Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

#define I2S_TCSR_DBGE_MASK                       (0x20000000U)
#define I2S_TCSR_DBGE_SHIFT                      (29U)
/*! DBGE - Debug Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

#define I2S_TCSR_STOPE_MASK                      (0x40000000U)
#define I2S_TCSR_STOPE_SHIFT                     (30U)
/*! STOPE - Stop Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

#define I2S_TCSR_TE_MASK                         (0x80000000U)
#define I2S_TCSR_TE_SHIFT                        (31U)
/*! TE - Transmitter Enable
 *  0b0..Disable
 *  0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame)
 */
#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
/*! @} */

/*! @name TCR1 - Transmit Configuration 1 */
/*! @{ */

#define I2S_TCR1_TFW_MASK                        (0x7U)
#define I2S_TCR1_TFW_SHIFT                       (0U)
/*! TFW - Transmit FIFO Watermark
 *  0b000..1
 *  0b001..2
 *  0b010-0b110..(TFW +1)
 *  0b111..8
 */
#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
/*! @} */

/*! @name TCR2 - Transmit Configuration 2 */
/*! @{ */

#define I2S_TCR2_DIV_MASK                        (0xFFU)
#define I2S_TCR2_DIV_SHIFT                       (0U)
/*! DIV - Bit Clock Divide */
#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)

#define I2S_TCR2_BYP_MASK                        (0x800000U)
#define I2S_TCR2_BYP_SHIFT                       (23U)
/*! BYP - Bit Clock Bypass
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)

#define I2S_TCR2_BCD_MASK                        (0x1000000U)
#define I2S_TCR2_BCD_SHIFT                       (24U)
/*! BCD - Bit Clock Direction
 *  0b0..Generate externally in Target mode
 *  0b1..Generate internally in Controller mode
 */
#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

#define I2S_TCR2_BCP_MASK                        (0x2000000U)
#define I2S_TCR2_BCP_SHIFT                       (25U)
/*! BCP - Bit Clock Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
#define I2S_TCR2_MSEL_SHIFT                      (26U)
/*! MSEL - MCLK Select
 *  0b00..Bus clock
 *  0b01..Controller clock (MCLK) option 1
 *  0b10..Controller clock (MCLK) option 2
 *  0b11..Controller clock (MCLK) option 3
 */
#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

#define I2S_TCR2_BCI_MASK                        (0x10000000U)
#define I2S_TCR2_BCI_SHIFT                       (28U)
/*! BCI - Bit Clock Input
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

#define I2S_TCR2_BCS_MASK                        (0x20000000U)
#define I2S_TCR2_BCS_SHIFT                       (29U)
/*! BCS - Bit Clock Swap
 *  0b0..Use the normal bit clock source
 *  0b1..Swap the bit clock source
 */
#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
#define I2S_TCR2_SYNC_SHIFT                      (30U)
/*! SYNC - Synchronous Mode
 *  0b00..Asynchronous mode
 *  0b01..Synchronous with receiver
 *  0b10..Synchronous with another SAI transmitter
 *  0b11..Synchronous with another SAI receiver
 */
#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
/*! @} */

/*! @name TCR3 - Transmit Configuration 3 */
/*! @{ */

#define I2S_TCR3_WDFL_MASK                       (0x1FU)
#define I2S_TCR3_WDFL_SHIFT                      (0U)
/*! WDFL - Word Flag Configuration */
#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)

#define I2S_TCR3_TCE_MASK                        (0x10000U)
#define I2S_TCR3_TCE_SHIFT                       (16U)
/*! TCE - Transmit Channel Enable */
#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
/*! @} */

/*! @name TCR4 - Transmit Configuration 4 */
/*! @{ */

#define I2S_TCR4_FSD_MASK                        (0x1U)
#define I2S_TCR4_FSD_SHIFT                       (0U)
/*! FSD - Frame Sync Direction
 *  0b0..Generated externally in Target mode
 *  0b1..Generated internally in Controller mode
 */
#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

#define I2S_TCR4_FSP_MASK                        (0x2U)
#define I2S_TCR4_FSP_SHIFT                       (1U)
/*! FSP - Frame Sync Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

#define I2S_TCR4_ONDEM_MASK                      (0x4U)
#define I2S_TCR4_ONDEM_SHIFT                     (2U)
/*! ONDEM - On-Demand Mode
 *  0b0..Generated continuously
 *  0b1..Generated after the FIFO warning flag is cleared
 */
#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)

#define I2S_TCR4_FSE_MASK                        (0x8U)
#define I2S_TCR4_FSE_SHIFT                       (3U)
/*! FSE - Frame Sync Early
 *  0b0..First bit of the frame
 *  0b1..One bit before the first bit of the frame
 */
#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

#define I2S_TCR4_MF_MASK                         (0x10U)
#define I2S_TCR4_MF_SHIFT                        (4U)
/*! MF - MSB First
 *  0b0..LSB
 *  0b1..MSB
 */
#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

#define I2S_TCR4_CHMOD_MASK                      (0x20U)
#define I2S_TCR4_CHMOD_SHIFT                     (5U)
/*! CHMOD - Channel Mode
 *  0b0..TDM mode
 *  0b1..Output mode
 */
#define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)

#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
#define I2S_TCR4_SYWD_SHIFT                      (8U)
/*! SYWD - Sync Width */
#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)

#define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
#define I2S_TCR4_FRSZ_SHIFT                      (16U)
/*! FRSZ - Frame Size */
#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)

#define I2S_TCR4_FPACK_MASK                      (0x3000000U)
#define I2S_TCR4_FPACK_SHIFT                     (24U)
/*! FPACK - FIFO Packing Mode
 *  0b00..Disable FIFO packing
 *  0b01..Reserved
 *  0b10..Enable 8-bit FIFO packing
 *  0b11..Enable 16-bit FIFO packing
 */
#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)

#define I2S_TCR4_FCONT_MASK                      (0x10000000U)
#define I2S_TCR4_FCONT_SHIFT                     (28U)
/*! FCONT - FIFO Continue on Error
 *  0b0..Continue from the start of the next frame
 *  0b1..Continue from the same word that caused the FIFO error
 */
#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
/*! @} */

/*! @name TCR5 - Transmit Configuration 5 */
/*! @{ */

#define I2S_TCR5_FBT_MASK                        (0x1F00U)
#define I2S_TCR5_FBT_SHIFT                       (8U)
/*! FBT - First Bit Shifted
 *  0b00000..0
 *  0b00001-0b11110..FBT
 *  0b11111..31
 */
#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)

#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
#define I2S_TCR5_W0W_SHIFT                       (16U)
/*! W0W - Word 0 Width
 *  0b00111..8
 *  0b01000..9
 *  0b01001-0b11110..(W0W value + 1)
 *  0b11111..32
 */
#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)

#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
#define I2S_TCR5_WNW_SHIFT                       (24U)
/*! WNW - Word N Width
 *  0b00111..8
 *  0b01000..9
 *  0b01001-0b11110..(WNW value + 1)
 *  0b11111..32
 */
#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
/*! @} */

/*! @name TDR - Transmit Data */
/*! @{ */

#define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
#define I2S_TDR_TDR_SHIFT                        (0U)
/*! TDR - Transmit Data */
#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
/*! @} */

/* The count of I2S_TDR */
#define I2S_TDR_COUNT                            (1U)

/*! @name TFR - Transmit FIFO */
/*! @{ */

#define I2S_TFR_RFP_MASK                         (0xFU)
#define I2S_TFR_RFP_SHIFT                        (0U)
/*! RFP - Read FIFO Pointer */
#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)

#define I2S_TFR_WFP_MASK                         (0xF0000U)
#define I2S_TFR_WFP_SHIFT                        (16U)
/*! WFP - Write FIFO Pointer */
#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
/*! @} */

/* The count of I2S_TFR */
#define I2S_TFR_COUNT                            (1U)

/*! @name TMR - Transmit Mask */
/*! @{ */

#define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
#define I2S_TMR_TWM_SHIFT                        (0U)
/*! TWM - Transmit Word Mask
 *  0b00000000000000000000000000000000..Enable
 *  0b00000000000000000000000000000001..Mask
 */
#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
/*! @} */

/*! @name TTCR - Transmit Timestamp Control */
/*! @{ */

#define I2S_TTCR_TSEN_MASK                       (0x1U)
#define I2S_TTCR_TSEN_SHIFT                      (0U)
/*! TSEN - Timestamp Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_TTCR_TSEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK)

#define I2S_TTCR_TSINC_MASK                      (0x2U)
#define I2S_TTCR_TSINC_SHIFT                     (1U)
/*! TSINC - Timestamp Increment
 *  0b0..When enabled and after the bit counter has incremented
 *  0b1..When enabled
 */
#define I2S_TTCR_TSINC(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK)

#define I2S_TTCR_TSSEL_MASK                      (0xCU)
#define I2S_TTCR_TSSEL_SHIFT                     (2U)
/*! TSSEL - Timestamp Select
 *  0b00..Increment when enabled
 *  0b01..Increment when the receive timestamp counter is enabled
 *  0b10..Increment when the transmit timestamp counter on another instance is enabled
 *  0b11..Increment when the receive timestamp counter on another instance is enabled
 */
#define I2S_TTCR_TSSEL(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSSEL_SHIFT)) & I2S_TTCR_TSSEL_MASK)

#define I2S_TTCR_RTSC_MASK                       (0x100U)
#define I2S_TTCR_RTSC_SHIFT                      (8U)
/*! RTSC - Reset Timestamp Counter
 *  0b0..No effect
 *  0b1..Reset
 */
#define I2S_TTCR_RTSC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK)

#define I2S_TTCR_RBC_MASK                        (0x200U)
#define I2S_TTCR_RBC_SHIFT                       (9U)
/*! RBC - Reset Bit Counter
 *  0b0..No effect
 *  0b1..Reset
 */
#define I2S_TTCR_RBC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK)
/*! @} */

/*! @name TTSR - Transmit Timestamp */
/*! @{ */

#define I2S_TTSR_TSC_MASK                        (0xFFFFFFFFU)
#define I2S_TTSR_TSC_SHIFT                       (0U)
/*! TSC - Timestamp Counter */
#define I2S_TTSR_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK)
/*! @} */

/*! @name TBCR - Transmit Bit Count */
/*! @{ */

#define I2S_TBCR_BCNT_MASK                       (0xFFFFFFFFU)
#define I2S_TBCR_BCNT_SHIFT                      (0U)
/*! BCNT - Bit Counter */
#define I2S_TBCR_BCNT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK)
/*! @} */

/*! @name TBCTR - Transmit Bit Count Timestamp */
/*! @{ */

#define I2S_TBCTR_BCTS_MASK                      (0xFFFFFFFFU)
#define I2S_TBCTR_BCTS_SHIFT                     (0U)
/*! BCTS - Bit Timestamp */
#define I2S_TBCTR_BCTS(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK)
/*! @} */

/*! @name RCSR - Receive Control */
/*! @{ */

#define I2S_RCSR_FRDE_MASK                       (0x1U)
#define I2S_RCSR_FRDE_SHIFT                      (0U)
/*! FRDE - FIFO Request DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

#define I2S_RCSR_FWDE_MASK                       (0x2U)
#define I2S_RCSR_FWDE_SHIFT                      (1U)
/*! FWDE - FIFO Warning DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

#define I2S_RCSR_FRIE_MASK                       (0x100U)
#define I2S_RCSR_FRIE_SHIFT                      (8U)
/*! FRIE - FIFO Request Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

#define I2S_RCSR_FWIE_MASK                       (0x200U)
#define I2S_RCSR_FWIE_SHIFT                      (9U)
/*! FWIE - FIFO Warning Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

#define I2S_RCSR_FEIE_MASK                       (0x400U)
#define I2S_RCSR_FEIE_SHIFT                      (10U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

#define I2S_RCSR_SEIE_MASK                       (0x800U)
#define I2S_RCSR_SEIE_SHIFT                      (11U)
/*! SEIE - Sync Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

#define I2S_RCSR_WSIE_MASK                       (0x1000U)
#define I2S_RCSR_WSIE_SHIFT                      (12U)
/*! WSIE - Word Start Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

#define I2S_RCSR_FRF_MASK                        (0x10000U)
#define I2S_RCSR_FRF_SHIFT                       (16U)
/*! FRF - FIFO Request Flag
 *  0b0..Watermark not reached
 *  0b1..Watermark reached
 */
#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

#define I2S_RCSR_FWF_MASK                        (0x20000U)
#define I2S_RCSR_FWF_SHIFT                       (17U)
/*! FWF - FIFO Warning Flag
 *  0b0..Not full
 *  0b1..Full
 */
#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

#define I2S_RCSR_FEF_MASK                        (0x40000U)
#define I2S_RCSR_FEF_SHIFT                       (18U)
/*! FEF - FIFO Error Flag
 *  0b0..No error
 *  0b1..Receive overflow detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

#define I2S_RCSR_SEF_MASK                        (0x80000U)
#define I2S_RCSR_SEF_SHIFT                       (19U)
/*! SEF - Sync Error Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

#define I2S_RCSR_WSF_MASK                        (0x100000U)
#define I2S_RCSR_WSF_SHIFT                       (20U)
/*! WSF - Word Start Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

#define I2S_RCSR_SR_MASK                         (0x1000000U)
#define I2S_RCSR_SR_SHIFT                        (24U)
/*! SR - Software Reset
 *  0b0..No effect
 *  0b1..Software reset
 */
#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

#define I2S_RCSR_FR_MASK                         (0x2000000U)
#define I2S_RCSR_FR_SHIFT                        (25U)
/*! FR - FIFO Reset
 *  0b0..No effect
 *  0b1..Reset
 */
#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

#define I2S_RCSR_BCE_MASK                        (0x10000000U)
#define I2S_RCSR_BCE_SHIFT                       (28U)
/*! BCE - Bit Clock Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

#define I2S_RCSR_DBGE_MASK                       (0x20000000U)
#define I2S_RCSR_DBGE_SHIFT                      (29U)
/*! DBGE - Debug Enable
 *  0b0..Disable after completing the current frame
 *  0b1..Enable
 */
#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

#define I2S_RCSR_STOPE_MASK                      (0x40000000U)
#define I2S_RCSR_STOPE_SHIFT                     (30U)
/*! STOPE - Stop Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

#define I2S_RCSR_RE_MASK                         (0x80000000U)
#define I2S_RCSR_RE_SHIFT                        (31U)
/*! RE - Receiver Enable
 *  0b0..Disable
 *  0b1..Enable (or receiver disabled and not yet reached end of frame)
 */
#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
/*! @} */

/*! @name RCR1 - Receive Configuration 1 */
/*! @{ */

#define I2S_RCR1_RFW_MASK                        (0x7U)
#define I2S_RCR1_RFW_SHIFT                       (0U)
/*! RFW - Receive FIFO Watermark
 *  0b000..1
 *  0b001..2
 *  0b010-0b110..(RFW value + 1)
 *  0b111..8
 */
#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
/*! @} */

/*! @name RCR2 - Receive Configuration 2 */
/*! @{ */

#define I2S_RCR2_DIV_MASK                        (0xFFU)
#define I2S_RCR2_DIV_SHIFT                       (0U)
/*! DIV - Bit Clock Divide */
#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)

#define I2S_RCR2_BYP_MASK                        (0x800000U)
#define I2S_RCR2_BYP_SHIFT                       (23U)
/*! BYP - Bit Clock Bypass
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)

#define I2S_RCR2_BCD_MASK                        (0x1000000U)
#define I2S_RCR2_BCD_SHIFT                       (24U)
/*! BCD - Bit Clock Direction
 *  0b0..Generated externally in Target mode
 *  0b1..Generated internally in Controller mode
 */
#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

#define I2S_RCR2_BCP_MASK                        (0x2000000U)
#define I2S_RCR2_BCP_SHIFT                       (25U)
/*! BCP - Bit Clock Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
#define I2S_RCR2_MSEL_SHIFT                      (26U)
/*! MSEL - MCLK Select
 *  0b00..Bus clock
 *  0b01..Controller clock (MCLK) option 1
 *  0b10..Controller clock (MCLK) option 2
 *  0b11..Controller clock (MCLK) option 3
 */
#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

#define I2S_RCR2_BCI_MASK                        (0x10000000U)
#define I2S_RCR2_BCI_SHIFT                       (28U)
/*! BCI - Bit Clock Input
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

#define I2S_RCR2_BCS_MASK                        (0x20000000U)
#define I2S_RCR2_BCS_SHIFT                       (29U)
/*! BCS - Bit Clock Swap
 *  0b0..Use the normal bit clock source
 *  0b1..Swap the bit clock source
 */
#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
#define I2S_RCR2_SYNC_SHIFT                      (30U)
/*! SYNC - Synchronous Mode
 *  0b00..Asynchronous mode
 *  0b01..Synchronous with transmitter
 *  0b10..Synchronous with another SAI receiver
 *  0b11..Synchronous with another SAI transmitter
 */
#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
/*! @} */

/*! @name RCR3 - Receive Configuration 3 */
/*! @{ */

#define I2S_RCR3_WDFL_MASK                       (0x1FU)
#define I2S_RCR3_WDFL_SHIFT                      (0U)
/*! WDFL - Word Flag Configuration
 *  0b00000..Word 1
 *  0b00001..Word 2
 *  0b00010-0b11110..Word (WDFL value + 1)
 *  0b11111..Word 32
 */
#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)

#define I2S_RCR3_RCE_MASK                        (0x10000U)
#define I2S_RCR3_RCE_SHIFT                       (16U)
/*! RCE - Receive Channel Enable */
#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
/*! @} */

/*! @name RCR4 - Receive Configuration 4 */
/*! @{ */

#define I2S_RCR4_FSD_MASK                        (0x1U)
#define I2S_RCR4_FSD_SHIFT                       (0U)
/*! FSD - Frame Sync Direction
 *  0b0..Generated externally in Target mode
 *  0b1..Generated internally in Controller mode
 */
#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

#define I2S_RCR4_FSP_MASK                        (0x2U)
#define I2S_RCR4_FSP_SHIFT                       (1U)
/*! FSP - Frame Sync Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

#define I2S_RCR4_ONDEM_MASK                      (0x4U)
#define I2S_RCR4_ONDEM_SHIFT                     (2U)
/*! ONDEM - On-Demand Mode
 *  0b0..Generated continuously
 *  0b1..Generated when the FIFO warning flag is 0
 */
#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)

#define I2S_RCR4_FSE_MASK                        (0x8U)
#define I2S_RCR4_FSE_SHIFT                       (3U)
/*! FSE - Frame Sync Early
 *  0b0..First bit of the frame
 *  0b1..One bit before the first bit of the frame
 */
#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

#define I2S_RCR4_MF_MASK                         (0x10U)
#define I2S_RCR4_MF_SHIFT                        (4U)
/*! MF - MSB First
 *  0b0..LSB
 *  0b1..MSB
 */
#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
#define I2S_RCR4_SYWD_SHIFT                      (8U)
/*! SYWD - Sync Width
 *  0b00000..1
 *  0b00001..2
 *  0b00010-0b11110..(SYWD value + 1)
 *  0b11111..32
 */
#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)

#define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
#define I2S_RCR4_FRSZ_SHIFT                      (16U)
/*! FRSZ - Frame Size
 *  0b00000..1
 *  0b00001..2
 *  0b00010-0b11110..(FRSZ value + 1)
 *  0b11111..32
 */
#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)

#define I2S_RCR4_FPACK_MASK                      (0x3000000U)
#define I2S_RCR4_FPACK_SHIFT                     (24U)
/*! FPACK - FIFO Packing Mode
 *  0b00..Disable
 *  0b01..Reserved
 *  0b10..Enable 8-bit FIFO packing
 *  0b11..Enable 16-bit FIFO packing
 */
#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)

#define I2S_RCR4_FCONT_MASK                      (0x10000000U)
#define I2S_RCR4_FCONT_SHIFT                     (28U)
/*! FCONT - FIFO Continue on Error
 *  0b0..From the start of the next frame after the FIFO error flag is cleared
 *  0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared
 */
#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
/*! @} */

/*! @name RCR5 - Receive Configuration 5 */
/*! @{ */

#define I2S_RCR5_FBT_MASK                        (0x1F00U)
#define I2S_RCR5_FBT_SHIFT                       (8U)
/*! FBT - First Bit Shifted
 *  0b00000..0
 *  0b00001-0b11110..FBT value
 *  0b11111..31
 */
#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)

#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
#define I2S_RCR5_W0W_SHIFT                       (16U)
/*! W0W - Word 0 Width
 *  0b00000..1
 *  0b00001..2
 *  0b00010-0b11110..(W0W value + 1)
 *  0b11111..32
 */
#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)

#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
#define I2S_RCR5_WNW_SHIFT                       (24U)
/*! WNW - Word N Width
 *  0b00111..8
 *  0b01000..9
 *  0b01001-0b11110..(WNW value + 1)
 *  0b11111..32
 */
#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
/*! @} */

/*! @name RDR - Receive Data */
/*! @{ */

#define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
#define I2S_RDR_RDR_SHIFT                        (0U)
/*! RDR - Receive Data */
#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
/*! @} */

/* The count of I2S_RDR */
#define I2S_RDR_COUNT                            (1U)

/*! @name RFR - Receive FIFO */
/*! @{ */

#define I2S_RFR_RFP_MASK                         (0xFU)
#define I2S_RFR_RFP_SHIFT                        (0U)
/*! RFP - Read FIFO Pointer */
#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)

#define I2S_RFR_WFP_MASK                         (0xF0000U)
#define I2S_RFR_WFP_SHIFT                        (16U)
/*! WFP - Write FIFO Pointer */
#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
/*! @} */

/* The count of I2S_RFR */
#define I2S_RFR_COUNT                            (1U)

/*! @name RMR - Receive Mask */
/*! @{ */

#define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
#define I2S_RMR_RWM_SHIFT                        (0U)
/*! RWM - Receive Word Mask
 *  0b00000000000000000000000000000000..Enable
 *  0b00000000000000000000000000000001..Mask
 */
#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
/*! @} */

/*! @name RTCR - Receive Timestamp Control */
/*! @{ */

#define I2S_RTCR_TSEN_MASK                       (0x1U)
#define I2S_RTCR_TSEN_SHIFT                      (0U)
/*! TSEN - Timestamp Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_RTCR_TSEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK)

#define I2S_RTCR_TSINC_MASK                      (0x2U)
#define I2S_RTCR_TSINC_SHIFT                     (1U)
/*! TSINC - Timestamp Increment
 *  0b0..When enabled and after the bit counter has incremented
 *  0b1..When enabled
 */
#define I2S_RTCR_TSINC(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK)

#define I2S_RTCR_TSSEL_MASK                      (0xCU)
#define I2S_RTCR_TSSEL_SHIFT                     (2U)
/*! TSSEL - Timestamp Select
 *  0b00..Increment when enabled
 *  0b01..Increment when the transmit timestamp counter is enabled
 *  0b10..Increment when the receive timestamp counter on another instance is enabled
 *  0b11..Increment when the transmit timestamp counter on another instance is enabled
 */
#define I2S_RTCR_TSSEL(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSSEL_SHIFT)) & I2S_RTCR_TSSEL_MASK)

#define I2S_RTCR_RTSC_MASK                       (0x100U)
#define I2S_RTCR_RTSC_SHIFT                      (8U)
/*! RTSC - Reset Timestamp Counter
 *  0b0..No effect
 *  0b1..Reset
 */
#define I2S_RTCR_RTSC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK)

#define I2S_RTCR_RBC_MASK                        (0x200U)
#define I2S_RTCR_RBC_SHIFT                       (9U)
/*! RBC - Reset Bit Counter
 *  0b0..No effect
 *  0b1..Reset
 */
#define I2S_RTCR_RBC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK)
/*! @} */

/*! @name RTSR - Receive Timestamp */
/*! @{ */

#define I2S_RTSR_TSC_MASK                        (0xFFFFFFFFU)
#define I2S_RTSR_TSC_SHIFT                       (0U)
/*! TSC - Timestamp Counter */
#define I2S_RTSR_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK)
/*! @} */

/*! @name RBCR - Receive Bit Count */
/*! @{ */

#define I2S_RBCR_BCNT_MASK                       (0xFFFFFFFFU)
#define I2S_RBCR_BCNT_SHIFT                      (0U)
/*! BCNT - Bit Counter */
#define I2S_RBCR_BCNT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK)
/*! @} */

/*! @name RBCTR - Receive Bit Count Timestamp */
/*! @{ */

#define I2S_RBCTR_BCTS_MASK                      (0xFFFFFFFFU)
#define I2S_RBCTR_BCTS_SHIFT                     (0U)
/*! BCTS - Bit Timestamp */
#define I2S_RBCTR_BCTS(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK)
/*! @} */

/*! @name MCR - MCLK Control */
/*! @{ */

#define I2S_MCR_DIV_MASK                         (0xFFU)
#define I2S_MCR_DIV_SHIFT                        (0U)
/*! DIV - MCLK Post Divide */
#define I2S_MCR_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK)

#define I2S_MCR_DIVEN_MASK                       (0x800000U)
#define I2S_MCR_DIVEN_SHIFT                      (23U)
/*! DIVEN - MCLK Post Divide Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define I2S_MCR_DIVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK)

#define I2S_MCR_MSEL_MASK                        (0x3000000U)
#define I2S_MCR_MSEL_SHIFT                       (24U)
/*! MSEL - MCLK Select
 *  0b00..Controller clock (MCLK) option 1
 *  0b01..Reserved
 *  0b10..Controller clock (MCLK) option 2
 *  0b11..Controller clock (MCLK) option 3
 */
#define I2S_MCR_MSEL(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK)

#define I2S_MCR_MOE_MASK                         (0x40000000U)
#define I2S_MCR_MOE_SHIFT                        (30U)
/*! MOE - MCLK Output Enable
 *  0b0..Input
 *  0b1..Output
 */
#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I2S_Register_Masks */


/* I2S - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SAI0 base address */
  #define SAI0_BASE                                (0x50152000u)
  /** Peripheral SAI0 base address */
  #define SAI0_BASE_NS                             (0x40152000u)
  /** Peripheral SAI0 base pointer */
  #define SAI0                                     ((I2S_Type *)SAI0_BASE)
  /** Peripheral SAI0 base pointer */
  #define SAI0_NS                                  ((I2S_Type *)SAI0_BASE_NS)
  /** Peripheral SAI1 base address */
  #define SAI1_BASE                                (0x50153000u)
  /** Peripheral SAI1 base address */
  #define SAI1_BASE_NS                             (0x40153000u)
  /** Peripheral SAI1 base pointer */
  #define SAI1                                     ((I2S_Type *)SAI1_BASE)
  /** Peripheral SAI1 base pointer */
  #define SAI1_NS                                  ((I2S_Type *)SAI1_BASE_NS)
  /** Peripheral SAI2 base address */
  #define SAI2_BASE                                (0x50154000u)
  /** Peripheral SAI2 base address */
  #define SAI2_BASE_NS                             (0x40154000u)
  /** Peripheral SAI2 base pointer */
  #define SAI2                                     ((I2S_Type *)SAI2_BASE)
  /** Peripheral SAI2 base pointer */
  #define SAI2_NS                                  ((I2S_Type *)SAI2_BASE_NS)
  /** Array initializer of I2S peripheral base addresses */
  #define I2S_BASE_ADDRS                           { SAI0_BASE, SAI1_BASE, SAI2_BASE }
  /** Array initializer of I2S peripheral base pointers */
  #define I2S_BASE_PTRS                            { SAI0, SAI1, SAI2 }
  /** Array initializer of I2S peripheral base addresses */
  #define I2S_BASE_ADDRS_NS                        { SAI0_BASE_NS, SAI1_BASE_NS, SAI2_BASE_NS }
  /** Array initializer of I2S peripheral base pointers */
  #define I2S_BASE_PTRS_NS                         { SAI0_NS, SAI1_NS, SAI2_NS }
#else
  /** Peripheral SAI0 base address */
  #define SAI0_BASE                                (0x40152000u)
  /** Peripheral SAI0 base pointer */
  #define SAI0                                     ((I2S_Type *)SAI0_BASE)
  /** Peripheral SAI1 base address */
  #define SAI1_BASE                                (0x40153000u)
  /** Peripheral SAI1 base pointer */
  #define SAI1                                     ((I2S_Type *)SAI1_BASE)
  /** Peripheral SAI2 base address */
  #define SAI2_BASE                                (0x40154000u)
  /** Peripheral SAI2 base pointer */
  #define SAI2                                     ((I2S_Type *)SAI2_BASE)
  /** Array initializer of I2S peripheral base addresses */
  #define I2S_BASE_ADDRS                           { SAI0_BASE, SAI1_BASE, SAI2_BASE }
  /** Array initializer of I2S peripheral base pointers */
  #define I2S_BASE_PTRS                            { SAI0, SAI1, SAI2 }
#endif
/** Interrupt vectors for the I2S peripheral type */
#define I2S_RX_IRQS                              { SAI0_TX_RX_IRQn, SAI1_TX_RX_IRQn, SAI2_TX_RX_IRQn }
#define I2S_TX_IRQS                              { SAI0_TX_RX_IRQn, SAI1_TX_RX_IRQn, SAI2_TX_RX_IRQn }

/*!
 * @}
 */ /* end of group I2S_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I3C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
 * @{
 */

/** I3C - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCONFIG;                           /**< Controller Configuration, offset: 0x0 */
  __IO uint32_t SCONFIG;                           /**< Target Configuration, offset: 0x4 */
  __IO uint32_t SSTATUS;                           /**< Target Status, offset: 0x8 */
  __IO uint32_t SCTRL;                             /**< Target Control, offset: 0xC */
  __IO uint32_t SINTSET;                           /**< Target Interrupt Set, offset: 0x10 */
  __IO uint32_t SINTCLR;                           /**< Target Interrupt Clear, offset: 0x14 */
  __I  uint32_t SINTMASKED;                        /**< Target Interrupt Mask, offset: 0x18 */
  __IO uint32_t SERRWARN;                          /**< Target Errors and Warnings, offset: 0x1C */
  __IO uint32_t SDMACTRL;                          /**< Target DMA Control, offset: 0x20 */
       uint8_t RESERVED_0[8];
  __IO uint32_t SDATACTRL;                         /**< Target Data Control, offset: 0x2C */
  __IO uint32_t SWDATAB;                           /**< Target Write Data Byte, offset: 0x30 */
  __IO uint32_t SWDATABE;                          /**< Target Write Data Byte End, offset: 0x34 */
  __IO uint32_t SWDATAH;                           /**< Target Write Data Halfword, offset: 0x38 */
  __IO uint32_t SWDATAHE;                          /**< Target Write Data Halfword End, offset: 0x3C */
  __I  uint32_t SRDATAB;                           /**< Target Read Data Byte, offset: 0x40 */
       uint8_t RESERVED_1[4];
  __I  uint32_t SRDATAH;                           /**< Target Read Data Halfword, offset: 0x48 */
       uint8_t RESERVED_2[8];
  union {                                          /* offset: 0x54 */
    __IO uint32_t SWDATAB1;                          /**< Target Write Data Byte, offset: 0x54 */
    __IO uint32_t SWDATAH1;                          /**< Target Write Data Halfword, offset: 0x54 */
  };
       uint8_t RESERVED_3[4];
  __I  uint32_t SCAPABILITIES2;                    /**< Target Capabilities 2, offset: 0x5C */
  __I  uint32_t SCAPABILITIES;                     /**< Target Capabilities, offset: 0x60 */
  __IO uint32_t SDYNADDR;                          /**< Target Dynamic Address, offset: 0x64 */
  __IO uint32_t SMAXLIMITS;                        /**< Target Maximum Limits, offset: 0x68 */
  __IO uint32_t SIDPARTNO;                         /**< Target ID Part Number, offset: 0x6C */
  __IO uint32_t SIDEXT;                            /**< Target ID Extension, offset: 0x70 */
  __IO uint32_t SVENDORID;                         /**< Target Vendor ID, offset: 0x74 */
  __IO uint32_t STCCLOCK;                          /**< Target Time Control Clock, offset: 0x78 */
  __I  uint32_t SMSGMAPADDR;                       /**< Target Message Map Address, offset: 0x7C */
  __IO uint32_t MCONFIG_EXT;                       /**< Controller Extended Configuration, offset: 0x80 */
  __IO uint32_t MCTRL;                             /**< Controller Control, offset: 0x84 */
  __IO uint32_t MSTATUS;                           /**< Controller Status, offset: 0x88 */
  __IO uint32_t MIBIRULES;                         /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */
  __IO uint32_t MINTSET;                           /**< Controller Interrupt Set, offset: 0x90 */
  __IO uint32_t MINTCLR;                           /**< Controller Interrupt Clear, offset: 0x94 */
  __I  uint32_t MINTMASKED;                        /**< Controller Interrupt Mask, offset: 0x98 */
  __IO uint32_t MERRWARN;                          /**< Controller Errors and Warnings, offset: 0x9C */
  __IO uint32_t MDMACTRL;                          /**< Controller DMA Control, offset: 0xA0 */
       uint8_t RESERVED_4[8];
  __IO uint32_t MDATACTRL;                         /**< Controller Data Control, offset: 0xAC */
  __IO uint32_t MWDATAB;                           /**< Controller Write Data Byte, offset: 0xB0 */
  __IO uint32_t MWDATABE;                          /**< Controller Write Data Byte End, offset: 0xB4 */
  __IO uint32_t MWDATAH;                           /**< Controller Write Data Halfword, offset: 0xB8 */
  __IO uint32_t MWDATAHE;                          /**< Controller Write Data Halfword End, offset: 0xBC */
  __I  uint32_t MRDATAB;                           /**< Controller Read Data Byte, offset: 0xC0 */
       uint8_t RESERVED_5[4];
  __I  uint32_t MRDATAH;                           /**< Controller Read Data Halfword, offset: 0xC8 */
  union {                                          /* offset: 0xCC */
    __IO uint32_t MWDATAB1;                          /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */
    __IO uint32_t MWDATAH1;                          /**< Controller Write Halfword Data (to Bus), offset: 0xCC */
  };
  union {                                          /* offset: 0xD0 */
    __IO uint32_t MWMSG_SDR_CONTROL;                 /**< Controller Write Message Control in SDR mode, offset: 0xD0 */
    __IO uint32_t MWMSG_SDR_DATA;                    /**< Controller Write Message Data in SDR mode, offset: 0xD0 */
  };
  __I  uint32_t MRMSG_SDR;                         /**< Controller Read Message in SDR mode, offset: 0xD4 */
  union {                                          /* offset: 0xD8 */
    __IO uint32_t MWMSG_DDR_CONTROL;                 /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */
    __IO uint32_t MWMSG_DDR_CONTROL2;                /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */
    __IO uint32_t MWMSG_DDR_DATA;                    /**< Controller Write Message Data in DDR mode, offset: 0xD8 */
  };
  __I  uint32_t MRMSG_DDR;                         /**< Controller Read Message in DDR mode, offset: 0xDC */
       uint8_t RESERVED_6[4];
  __IO uint32_t MDYNADDR;                          /**< Controller Dynamic Address, offset: 0xE4 */
       uint8_t RESERVED_7[52];
  __I  uint32_t SMAPCTRL0;                         /**< Map Feature Control 0, offset: 0x11C */
       uint8_t RESERVED_8[32];
  __IO uint32_t IBIEXT1;                           /**< Extended IBI Data 1, offset: 0x140 */
  __IO uint32_t IBIEXT2;                           /**< Extended IBI Data 2, offset: 0x144 */
       uint8_t RESERVED_9[3764];
  __I  uint32_t SID;                               /**< Target Module ID, offset: 0xFFC */
} I3C_Type;

/* ----------------------------------------------------------------------------
   -- I3C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Register_Masks I3C Register Masks
 * @{
 */

/*! @name MCONFIG - Controller Configuration */
/*! @{ */

#define I3C_MCONFIG_MSTENA_MASK                  (0x3U)
#define I3C_MCONFIG_MSTENA_SHIFT                 (0U)
/*! MSTENA - Controller Enable
 *  0b00..CONTROLLER_OFF
 *  0b01..CONTROLLER_ON
 *  0b10..CONTROLLER_CAPABLE
 *  0b11..I2C_CONTROLLER_MODE
 */
#define I3C_MCONFIG_MSTENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)

#define I3C_MCONFIG_DISTO_MASK                   (0x8U)
#define I3C_MCONFIG_DISTO_SHIFT                  (3U)
/*! DISTO - Disable Timeout
 *  0b1..Disabled, if configured
 *  0b0..Enabled
 */
#define I3C_MCONFIG_DISTO(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)

#define I3C_MCONFIG_HKEEP_MASK                   (0x30U)
#define I3C_MCONFIG_HKEEP_SHIFT                  (4U)
/*! HKEEP - High-Keeper
 *  0b00..None
 *  0b01..WIRED_IN
 *  0b10..PASSIVE_SDA
 *  0b11..PASSIVE_ON_SDA_SCL
 */
#define I3C_MCONFIG_HKEEP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)

#define I3C_MCONFIG_ODSTOP_MASK                  (0x40U)
#define I3C_MCONFIG_ODSTOP_SHIFT                 (6U)
/*! ODSTOP - Open Drain Stop
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MCONFIG_ODSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)

#define I3C_MCONFIG_PPBAUD_MASK                  (0xF00U)
#define I3C_MCONFIG_PPBAUD_SHIFT                 (8U)
/*! PPBAUD - Push-Pull Baud Rate */
#define I3C_MCONFIG_PPBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)

#define I3C_MCONFIG_PPLOW_MASK                   (0xF000U)
#define I3C_MCONFIG_PPLOW_SHIFT                  (12U)
/*! PPLOW - Push-Pull Low */
#define I3C_MCONFIG_PPLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)

#define I3C_MCONFIG_ODBAUD_MASK                  (0xFF0000U)
#define I3C_MCONFIG_ODBAUD_SHIFT                 (16U)
/*! ODBAUD - Open Drain Baud Rate */
#define I3C_MCONFIG_ODBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)

#define I3C_MCONFIG_ODHPP_MASK                   (0x1000000U)
#define I3C_MCONFIG_ODHPP_SHIFT                  (24U)
/*! ODHPP - Open Drain High Push-Pull
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MCONFIG_ODHPP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)

#define I3C_MCONFIG_SKEW_MASK                    (0xE000000U)
#define I3C_MCONFIG_SKEW_SHIFT                   (25U)
/*! SKEW - Skew */
#define I3C_MCONFIG_SKEW(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)

#define I3C_MCONFIG_I2CBAUD_MASK                 (0xF0000000U)
#define I3C_MCONFIG_I2CBAUD_SHIFT                (28U)
/*! I2CBAUD - I2C Baud Rate */
#define I3C_MCONFIG_I2CBAUD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
/*! @} */

/*! @name SCONFIG - Target Configuration */
/*! @{ */

#define I3C_SCONFIG_SLVENA_MASK                  (0x1U)
#define I3C_SCONFIG_SLVENA_SHIFT                 (0U)
/*! SLVENA - Target Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SCONFIG_SLVENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)

#define I3C_SCONFIG_NACK_MASK                    (0x2U)
#define I3C_SCONFIG_NACK_SHIFT                   (1U)
/*! NACK - Not Acknowledge
 *  0b1..Always enable NACK mode (works normally)
 *  0b0..Always disable NACK mode
 */
#define I3C_SCONFIG_NACK(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)

#define I3C_SCONFIG_MATCHSS_MASK                 (0x4U)
#define I3C_SCONFIG_MATCHSS_SHIFT                (2U)
/*! MATCHSS - Match Start or Stop
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SCONFIG_MATCHSS(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)

#define I3C_SCONFIG_S0IGNORE_MASK                (0x8U)
#define I3C_SCONFIG_S0IGNORE_SHIFT               (3U)
/*! S0IGNORE - Ignore TE0 or TE1 Errors
 *  0b1..Ignore TE0 or TE1 errors
 *  0b0..Do not ignore TE0 or TE1 errors
 */
#define I3C_SCONFIG_S0IGNORE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)

#define I3C_SCONFIG_HDROK_MASK                   (0x10U)
#define I3C_SCONFIG_HDROK_SHIFT                  (4U)
/*! HDROK - HDR OK
 *  0b1..Enable HDR OK
 *  0b0..Disable HDR OK
 */
#define I3C_SCONFIG_HDROK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK)

#define I3C_SCONFIG_OFFLINE_MASK                 (0x200U)
#define I3C_SCONFIG_OFFLINE_SHIFT                (9U)
/*! OFFLINE - Offline
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SCONFIG_OFFLINE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)

#define I3C_SCONFIG_BAMATCH_MASK                 (0xFF0000U)
#define I3C_SCONFIG_BAMATCH_SHIFT                (16U)
/*! BAMATCH - Bus Available Match */
#define I3C_SCONFIG_BAMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)

#define I3C_SCONFIG_SADDR_MASK                   (0xFE000000U)
#define I3C_SCONFIG_SADDR_SHIFT                  (25U)
/*! SADDR - Static Address */
#define I3C_SCONFIG_SADDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
/*! @} */

/*! @name SSTATUS - Target Status */
/*! @{ */

#define I3C_SSTATUS_STNOTSTOP_MASK               (0x1U)
#define I3C_SSTATUS_STNOTSTOP_SHIFT              (0U)
/*! STNOTSTOP - Status not Stop
 *  0b1..Busy
 *  0b0..In STOP condition
 */
#define I3C_SSTATUS_STNOTSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)

#define I3C_SSTATUS_STMSG_MASK                   (0x2U)
#define I3C_SSTATUS_STMSG_SHIFT                  (1U)
/*! STMSG - Status Message
 *  0b1..Busy
 *  0b0..Idle
 */
#define I3C_SSTATUS_STMSG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)

#define I3C_SSTATUS_STCCCH_MASK                  (0x4U)
#define I3C_SSTATUS_STCCCH_SHIFT                 (2U)
/*! STCCCH - Status Common Command Code Handler
 *  0b1..Handled automatically
 *  0b0..No CCC message handled
 */
#define I3C_SSTATUS_STCCCH(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)

#define I3C_SSTATUS_STREQRD_MASK                 (0x8U)
#define I3C_SSTATUS_STREQRD_SHIFT                (3U)
/*! STREQRD - Status Request Read
 *  0b1..SDR read from this target or an IBI is being pushed out
 *  0b0..Not an SDR read
 */
#define I3C_SSTATUS_STREQRD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)

#define I3C_SSTATUS_STREQWR_MASK                 (0x10U)
#define I3C_SSTATUS_STREQWR_SHIFT                (4U)
/*! STREQWR - Status Request Write
 *  0b1..SDR write data from the controller, but not in ENTDAA mode
 *  0b0..Not an SDR write
 */
#define I3C_SSTATUS_STREQWR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)

#define I3C_SSTATUS_STDAA_MASK                   (0x20U)
#define I3C_SSTATUS_STDAA_SHIFT                  (5U)
/*! STDAA - Status Dynamic Address Assignment
 *  0b1..In ENTDAA mode
 *  0b0..Not in ENTDAA mode
 */
#define I3C_SSTATUS_STDAA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)

#define I3C_SSTATUS_STHDR_MASK                   (0x40U)
#define I3C_SSTATUS_STHDR_SHIFT                  (6U)
/*! STHDR - Status High Data Rate
 *  0b1..I3C bus in HDR-DDR mode
 *  0b0..I3C bus not in HDR-DDR mode
 */
#define I3C_SSTATUS_STHDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)

#define I3C_SSTATUS_START_MASK                   (0x100U)
#define I3C_SSTATUS_START_SHIFT                  (8U)
/*! START - Start Flag
 *  0b1..Detected
 *  0b0..Not detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SSTATUS_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)

#define I3C_SSTATUS_MATCHED_MASK                 (0x200U)
#define I3C_SSTATUS_MATCHED_SHIFT                (9U)
/*! MATCHED - Matched Flag
 *  0b1..Header matched
 *  0b0..Header not matched
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SSTATUS_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)

#define I3C_SSTATUS_STOP_MASK                    (0x400U)
#define I3C_SSTATUS_STOP_SHIFT                   (10U)
/*! STOP - Stop Flag
 *  0b1..Stopped state detected
 *  0b0..No Stopped state detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SSTATUS_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)

#define I3C_SSTATUS_RX_PEND_MASK                 (0x800U)
#define I3C_SSTATUS_RX_PEND_SHIFT                (11U)
/*! RX_PEND - Received Message Pending
 *  0b1..Received message pending
 *  0b0..No received message pending
 */
#define I3C_SSTATUS_RX_PEND(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)

#define I3C_SSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_SSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - Transmit Buffer Not Full
 *  0b1..Transmit buffer not full
 *  0b0..Transmit buffer full
 */
#define I3C_SSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)

#define I3C_SSTATUS_DACHG_MASK                   (0x2000U)
#define I3C_SSTATUS_DACHG_SHIFT                  (13U)
/*! DACHG - Dynamic Address Change Flag
 *  0b1..DA change detected
 *  0b0..No DA change detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SSTATUS_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)

#define I3C_SSTATUS_CCC_MASK                     (0x4000U)
#define I3C_SSTATUS_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code Flag
 *  0b1..CCC received
 *  0b0..CCC not received
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SSTATUS_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)

#define I3C_SSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_SSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error Warning */
#define I3C_SSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)

#define I3C_SSTATUS_HDRMATCH_MASK                (0x10000U)
#define I3C_SSTATUS_HDRMATCH_SHIFT               (16U)
/*! HDRMATCH - High Data Rate Command Match Flag
 *  0b1..Matched the I3C dynamic address
 *  0b0..Did not match
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SSTATUS_HDRMATCH(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)

#define I3C_SSTATUS_CHANDLED_MASK                (0x20000U)
#define I3C_SSTATUS_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common Command Code Handled Flag
 *  0b1..CCC handling in progress
 *  0b0..CCC handling not in progress
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SSTATUS_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)

#define I3C_SSTATUS_EVENT_MASK                   (0x40000U)
#define I3C_SSTATUS_EVENT_SHIFT                  (18U)
/*! EVENT - Event Flag
 *  0b1..IBI, CR, or HJ occurred
 *  0b0..No event occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SSTATUS_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)

#define I3C_SSTATUS_EVDET_MASK                   (0x300000U)
#define I3C_SSTATUS_EVDET_SHIFT                  (20U)
/*! EVDET - Event Details
 *  0b00..NONE (no event or no pending event)
 *  0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ))
 *  0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again
 *  0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent)
 */
#define I3C_SSTATUS_EVDET(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)

#define I3C_SSTATUS_IBIDIS_MASK                  (0x1000000U)
#define I3C_SSTATUS_IBIDIS_SHIFT                 (24U)
/*! IBIDIS - In-Band Interrupts Disable
 *  0b1..Disabled
 *  0b0..Enabled
 */
#define I3C_SSTATUS_IBIDIS(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)

#define I3C_SSTATUS_MRDIS_MASK                   (0x2000000U)
#define I3C_SSTATUS_MRDIS_SHIFT                  (25U)
/*! MRDIS - Controller Requests Disable
 *  0b1..Disabled
 *  0b0..Enabled
 */
#define I3C_SSTATUS_MRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)

#define I3C_SSTATUS_HJDIS_MASK                   (0x8000000U)
#define I3C_SSTATUS_HJDIS_SHIFT                  (27U)
/*! HJDIS - Hot-Join Disabled
 *  0b1..Disabled
 *  0b0..Enabled
 */
#define I3C_SSTATUS_HJDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)

#define I3C_SSTATUS_ACTSTATE_MASK                (0x30000000U)
#define I3C_SSTATUS_ACTSTATE_SHIFT               (28U)
/*! ACTSTATE - Activity State from Common Command Codes (CCC)
 *  0b00..NO_LATENCY (normal bus operations)
 *  0b01..LATENCY_1MS (1 ms of latency)
 *  0b10..LATENCY_100MS (100 ms of latency)
 *  0b11..LATENCY_10S (10 seconds of latency)
 */
#define I3C_SSTATUS_ACTSTATE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)

#define I3C_SSTATUS_TIMECTRL_MASK                (0xC0000000U)
#define I3C_SSTATUS_TIMECTRL_SHIFT               (30U)
/*! TIMECTRL - Time Control
 *  0b00..NO_TIME_CONTROL (no time control is enabled)
 *  0b01..SYNC_MODE (Synchronous mode is enabled)
 *  0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled)
 *  0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled)
 */
#define I3C_SSTATUS_TIMECTRL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
/*! @} */

/*! @name SCTRL - Target Control */
/*! @{ */

#define I3C_SCTRL_EVENT_MASK                     (0x3U)
#define I3C_SCTRL_EVENT_SHIFT                    (0U)
/*! EVENT - Event
 *  0b00..NORMAL_MODE
 *  0b01..IBI
 *  0b10..CONTROLLER_REQUEST
 *  0b11..HOT_JOIN_REQUEST
 */
#define I3C_SCTRL_EVENT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)

#define I3C_SCTRL_EXTDATA_MASK                   (0x8U)
#define I3C_SCTRL_EXTDATA_SHIFT                  (3U)
/*! EXTDATA - Extended Data
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SCTRL_EXTDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK)

#define I3C_SCTRL_IBIDATA_MASK                   (0xFF00U)
#define I3C_SCTRL_IBIDATA_SHIFT                  (8U)
/*! IBIDATA - In-Band Interrupt Data */
#define I3C_SCTRL_IBIDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)

#define I3C_SCTRL_PENDINT_MASK                   (0xF0000U)
#define I3C_SCTRL_PENDINT_SHIFT                  (16U)
/*! PENDINT - Pending Interrupt */
#define I3C_SCTRL_PENDINT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)

#define I3C_SCTRL_ACTSTATE_MASK                  (0x300000U)
#define I3C_SCTRL_ACTSTATE_SHIFT                 (20U)
/*! ACTSTATE - Activity State of Target */
#define I3C_SCTRL_ACTSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)

#define I3C_SCTRL_VENDINFO_MASK                  (0xFF000000U)
#define I3C_SCTRL_VENDINFO_SHIFT                 (24U)
/*! VENDINFO - Vendor Information */
#define I3C_SCTRL_VENDINFO(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
/*! @} */

/*! @name SINTSET - Target Interrupt Set */
/*! @{ */

#define I3C_SINTSET_START_MASK                   (0x100U)
#define I3C_SINTSET_START_SHIFT                  (8U)
/*! START - Start Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)

#define I3C_SINTSET_MATCHED_MASK                 (0x200U)
#define I3C_SINTSET_MATCHED_SHIFT                (9U)
/*! MATCHED - Match Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)

#define I3C_SINTSET_STOP_MASK                    (0x400U)
#define I3C_SINTSET_STOP_SHIFT                   (10U)
/*! STOP - Stop Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)

#define I3C_SINTSET_RXPEND_MASK                  (0x800U)
#define I3C_SINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - Receive Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)

#define I3C_SINTSET_TXSEND_MASK                  (0x1000U)
#define I3C_SINTSET_TXSEND_SHIFT                 (12U)
/*! TXSEND - Transmit Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)

#define I3C_SINTSET_DACHG_MASK                   (0x2000U)
#define I3C_SINTSET_DACHG_SHIFT                  (13U)
/*! DACHG - Dynamic Address Change Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)

#define I3C_SINTSET_CCC_MASK                     (0x4000U)
#define I3C_SINTSET_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code (CCC) Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)

#define I3C_SINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or Warning Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)

#define I3C_SINTSET_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTSET_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - Double Data Rate Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)

#define I3C_SINTSET_CHANDLED_MASK                (0x20000U)
#define I3C_SINTSET_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common Command Code (CCC) Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)

#define I3C_SINTSET_EVENT_MASK                   (0x40000U)
#define I3C_SINTSET_EVENT_SHIFT                  (18U)
/*! EVENT - Event Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_SINTSET_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
/*! @} */

/*! @name SINTCLR - Target Interrupt Clear */
/*! @{ */

#define I3C_SINTCLR_START_MASK                   (0x100U)
#define I3C_SINTCLR_START_SHIFT                  (8U)
/*! START - START Interrupt Enable Clear Flag */
#define I3C_SINTCLR_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)

#define I3C_SINTCLR_MATCHED_MASK                 (0x200U)
#define I3C_SINTCLR_MATCHED_SHIFT                (9U)
/*! MATCHED - Matched Interrupt Enable Clear Flag */
#define I3C_SINTCLR_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)

#define I3C_SINTCLR_STOP_MASK                    (0x400U)
#define I3C_SINTCLR_STOP_SHIFT                   (10U)
/*! STOP - STOP Interrupt Enable Clear Flag */
#define I3C_SINTCLR_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)

#define I3C_SINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_SINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND Interrupt Enable Clear Flag */
#define I3C_SINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)

#define I3C_SINTCLR_TXSEND_MASK                  (0x1000U)
#define I3C_SINTCLR_TXSEND_SHIFT                 (12U)
/*! TXSEND - TXSEND Interrupt Enable Clear Flag */
#define I3C_SINTCLR_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)

#define I3C_SINTCLR_DACHG_MASK                   (0x2000U)
#define I3C_SINTCLR_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG Interrupt Enable Clear Flag */
#define I3C_SINTCLR_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)

#define I3C_SINTCLR_CCC_MASK                     (0x4000U)
#define I3C_SINTCLR_CCC_SHIFT                    (14U)
/*! CCC - CCC Interrupt Enable Clear Flag */
#define I3C_SINTCLR_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)

#define I3C_SINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN Interrupt Enable Clear Flag */
#define I3C_SINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)

#define I3C_SINTCLR_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTCLR_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear Flag */
#define I3C_SINTCLR_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)

#define I3C_SINTCLR_CHANDLED_MASK                (0x20000U)
#define I3C_SINTCLR_CHANDLED_SHIFT               (17U)
/*! CHANDLED - CHANDLED Interrupt Enable Clear Flag */
#define I3C_SINTCLR_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)

#define I3C_SINTCLR_EVENT_MASK                   (0x40000U)
#define I3C_SINTCLR_EVENT_SHIFT                  (18U)
/*! EVENT - EVENT Interrupt Enable Clear Flag */
#define I3C_SINTCLR_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
/*! @} */

/*! @name SINTMASKED - Target Interrupt Mask */
/*! @{ */

#define I3C_SINTMASKED_START_MASK                (0x100U)
#define I3C_SINTMASKED_START_SHIFT               (8U)
/*! START - START Interrupt Mask */
#define I3C_SINTMASKED_START(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)

#define I3C_SINTMASKED_MATCHED_MASK              (0x200U)
#define I3C_SINTMASKED_MATCHED_SHIFT             (9U)
/*! MATCHED - MATCHED Interrupt Mask */
#define I3C_SINTMASKED_MATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)

#define I3C_SINTMASKED_STOP_MASK                 (0x400U)
#define I3C_SINTMASKED_STOP_SHIFT                (10U)
/*! STOP - STOP Interrupt Mask */
#define I3C_SINTMASKED_STOP(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)

#define I3C_SINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_SINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND Interrupt Mask */
#define I3C_SINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)

#define I3C_SINTMASKED_TXSEND_MASK               (0x1000U)
#define I3C_SINTMASKED_TXSEND_SHIFT              (12U)
/*! TXSEND - TXSEND Interrupt Mask */
#define I3C_SINTMASKED_TXSEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)

#define I3C_SINTMASKED_DACHG_MASK                (0x2000U)
#define I3C_SINTMASKED_DACHG_SHIFT               (13U)
/*! DACHG - DACHG Interrupt Mask */
#define I3C_SINTMASKED_DACHG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)

#define I3C_SINTMASKED_CCC_MASK                  (0x4000U)
#define I3C_SINTMASKED_CCC_SHIFT                 (14U)
/*! CCC - CCC Interrupt Mask */
#define I3C_SINTMASKED_CCC(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)

#define I3C_SINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_SINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN Interrupt Mask */
#define I3C_SINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)

#define I3C_SINTMASKED_DDRMATCHED_MASK           (0x10000U)
#define I3C_SINTMASKED_DDRMATCHED_SHIFT          (16U)
/*! DDRMATCHED - DDRMATCHED Interrupt Mask */
#define I3C_SINTMASKED_DDRMATCHED(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)

#define I3C_SINTMASKED_CHANDLED_MASK             (0x20000U)
#define I3C_SINTMASKED_CHANDLED_SHIFT            (17U)
/*! CHANDLED - CHANDLED Interrupt Mask */
#define I3C_SINTMASKED_CHANDLED(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)

#define I3C_SINTMASKED_EVENT_MASK                (0x40000U)
#define I3C_SINTMASKED_EVENT_SHIFT               (18U)
/*! EVENT - EVENT Interrupt Mask */
#define I3C_SINTMASKED_EVENT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
/*! @} */

/*! @name SERRWARN - Target Errors and Warnings */
/*! @{ */

#define I3C_SERRWARN_ORUN_MASK                   (0x1U)
#define I3C_SERRWARN_ORUN_SHIFT                  (0U)
/*! ORUN - Overrun Error Flag
 *  0b1..Overrun error
 *  0b0..No overrun error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_ORUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)

#define I3C_SERRWARN_URUN_MASK                   (0x2U)
#define I3C_SERRWARN_URUN_SHIFT                  (1U)
/*! URUN - Underrun Error Flag
 *  0b1..Underrun error
 *  0b0..No underrun error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)

#define I3C_SERRWARN_URUNNACK_MASK               (0x4U)
#define I3C_SERRWARN_URUNNACK_SHIFT              (2U)
/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error Flag
 *  0b1..Underrun; not acknowledged error
 *  0b0..No underrun; not acknowledged error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_URUNNACK(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)

#define I3C_SERRWARN_TERM_MASK                   (0x8U)
#define I3C_SERRWARN_TERM_SHIFT                  (3U)
/*! TERM - Terminated Error Flag
 *  0b1..Terminated error
 *  0b0..No terminated error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)

#define I3C_SERRWARN_INVSTART_MASK               (0x10U)
#define I3C_SERRWARN_INVSTART_SHIFT              (4U)
/*! INVSTART - Invalid Start Error Flag
 *  0b1..Invalid start error
 *  0b0..No invalid start error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_INVSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)

#define I3C_SERRWARN_SPAR_MASK                   (0x100U)
#define I3C_SERRWARN_SPAR_SHIFT                  (8U)
/*! SPAR - SDR Parity Error Flag
 *  0b1..SDR parity error
 *  0b0..No SDR parity error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_SPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)

#define I3C_SERRWARN_HPAR_MASK                   (0x200U)
#define I3C_SERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - HDR Parity Error Flag
 *  0b1..HDR parity error
 *  0b0..No HDR parity error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)

#define I3C_SERRWARN_HCRC_MASK                   (0x400U)
#define I3C_SERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - HDR-DDR CRC Error Flag
 *  0b1..HDR-DDR CRC error occurred
 *  0b0..No HDR-DDR CRC error occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)

#define I3C_SERRWARN_S0S1_MASK                   (0x800U)
#define I3C_SERRWARN_S0S1_SHIFT                  (11U)
/*! S0S1 - TE0 or TE1 Error Flag
 *  0b1..TE0 or TE1 error occurred
 *  0b0..No TE0 or TE1 error occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_S0S1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)

#define I3C_SERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_SERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-Read Error Flag
 *  0b1..Over-read error
 *  0b0..No over-read error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)

#define I3C_SERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_SERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-Write Error Flag
 *  0b1..Overwrite error
 *  0b0..No overwrite error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_SERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
/*! @} */

/*! @name SDMACTRL - Target DMA Control */
/*! @{ */

#define I3C_SDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_SDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA Read (From-Bus) Trigger
 *  0b00..DMA not used
 *  0b01..DMA enabled for one frame
 *  0b10..DMA enabled until turned off
 *  0b11..
 */
#define I3C_SDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)

#define I3C_SDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_SDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA Write (To-Bus) Trigger
 *  0b00..DMA not used
 *  0b01..DMA enabled for one frame
 *  0b10..DMA enabled until turned off
 *  0b11..
 */
#define I3C_SDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)

#define I3C_SDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_SDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - Width of DMA Operations
 *  0b00, 0b01..Byte
 *  0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)
 *  0b11..
 */
#define I3C_SDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name SDATACTRL - Target Data Control */
/*! @{ */

#define I3C_SDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_SDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush To-Bus Buffer or FIFO
 *  0b1..Flush the buffer
 *  0b0..No action
 */
#define I3C_SDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)

#define I3C_SDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_SDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flush From-Bus Buffer or FIFO
 *  0b1..Flush the buffer
 *  0b0..No action
 */
#define I3C_SDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)

#define I3C_SDATACTRL_UNLOCK_MASK                (0x8U)
#define I3C_SDATACTRL_UNLOCK_SHIFT               (3U)
/*! UNLOCK - Unlock
 *  0b0..Cannot be changed
 *  0b1..Can be changed
 */
#define I3C_SDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)

#define I3C_SDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_SDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - Transmit Trigger Level
 *  0b00..Trigger when empty
 *  0b01..Trigger when 1/4 full or less
 *  0b10..Trigger when 1/2 full or less
 *  0b11..Default (trigger when 1 less than full or less)
 */
#define I3C_SDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)

#define I3C_SDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_SDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - Receive Trigger Level
 *  0b00..Trigger when not empty (default)
 *  0b01..Trigger when 1/4 or more full
 *  0b10..Trigger when 1/2 or more full
 *  0b11..Trigger when 3/4 or more full
 */
#define I3C_SDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)

#define I3C_SDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_SDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - Count of Bytes in Transmit */
#define I3C_SDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)

#define I3C_SDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_SDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - Count of Bytes in Receive */
#define I3C_SDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)

#define I3C_SDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_SDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - Transmit is Full
 *  0b1..Full
 *  0b0..Not full
 */
#define I3C_SDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)

#define I3C_SDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_SDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - Receive is Empty
 *  0b1..Empty
 *  0b0..Not empty
 */
#define I3C_SDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name SWDATAB - Target Write Data Byte */
/*! @{ */

#define I3C_SWDATAB_DATA_MASK                    (0xFFU)
#define I3C_SWDATAB_DATA_SHIFT                   (0U)
/*! DATA - Data */
#define I3C_SWDATAB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)

#define I3C_SWDATAB_END_MASK                     (0x100U)
#define I3C_SWDATAB_END_SHIFT                    (8U)
/*! END - End
 *  0b1..End
 *  0b0..Not the end
 */
#define I3C_SWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)

#define I3C_SWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_SWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End Also
 *  0b1..End
 *  0b0..Not the end
 */
#define I3C_SWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name SWDATABE - Target Write Data Byte End */
/*! @{ */

#define I3C_SWDATABE_DATA_MASK                   (0xFFU)
#define I3C_SWDATABE_DATA_SHIFT                  (0U)
/*! DATA - Data */
#define I3C_SWDATABE_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
/*! @} */

/*! @name SWDATAH - Target Write Data Halfword */
/*! @{ */

#define I3C_SWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_SWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - Data 0 */
#define I3C_SWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)

#define I3C_SWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_SWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - Data 1 */
#define I3C_SWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)

#define I3C_SWDATAH_END_MASK                     (0x10000U)
#define I3C_SWDATAH_END_SHIFT                    (16U)
/*! END - End of Message
 *  0b1..End
 *  0b0..Not the end
 */
#define I3C_SWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
/*! @} */

/*! @name SWDATAHE - Target Write Data Halfword End */
/*! @{ */

#define I3C_SWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_SWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - Data 0 */
#define I3C_SWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)

#define I3C_SWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_SWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - Data 1 */
#define I3C_SWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
/*! @} */

/*! @name SRDATAB - Target Read Data Byte */
/*! @{ */

#define I3C_SRDATAB_DATA0_MASK                   (0xFFU)
#define I3C_SRDATAB_DATA0_SHIFT                  (0U)
/*! DATA0 - Data 0 */
#define I3C_SRDATAB_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
/*! @} */

/*! @name SRDATAH - Target Read Data Halfword */
/*! @{ */

#define I3C_SRDATAH_LSB_MASK                     (0xFFU)
#define I3C_SRDATAH_LSB_SHIFT                    (0U)
/*! LSB - Low Byte */
#define I3C_SRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)

#define I3C_SRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_SRDATAH_MSB_SHIFT                    (8U)
/*! MSB - High Byte */
#define I3C_SRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
/*! @} */

/*! @name SWDATAB1 - Target Write Data Byte */
/*! @{ */

#define I3C_SWDATAB1_DATA_MASK                   (0xFFU)
#define I3C_SWDATAB1_DATA_SHIFT                  (0U)
/*! DATA - Data */
#define I3C_SWDATAB1_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK)
/*! @} */

/*! @name SWDATAH1 - Target Write Data Halfword */
/*! @{ */

#define I3C_SWDATAH1_DATA_MASK                   (0xFFFFU)
#define I3C_SWDATAH1_DATA_SHIFT                  (0U)
/*! DATA - Data */
#define I3C_SWDATAH1_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK)
/*! @} */

/*! @name SCAPABILITIES2 - Target Capabilities 2 */
/*! @{ */

#define I3C_SCAPABILITIES2_MAPCNT_MASK           (0xFU)
#define I3C_SCAPABILITIES2_MAPCNT_SHIFT          (0U)
/*! MAPCNT - Map Count */
#define I3C_SCAPABILITIES2_MAPCNT(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK)

#define I3C_SCAPABILITIES2_I2C10B_MASK           (0x10U)
#define I3C_SCAPABILITIES2_I2C10B_SHIFT          (4U)
/*! I2C10B - I2C 10-bit Address
 *  0b0..Not supported
 *  0b1..Supported
 */
#define I3C_SCAPABILITIES2_I2C10B(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK)

#define I3C_SCAPABILITIES2_I2CDEVID_MASK         (0x40U)
#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT        (6U)
/*! I2CDEVID - I2C Device ID
 *  0b0..Not supported
 *  0b1..Supported
 */
#define I3C_SCAPABILITIES2_I2CDEVID(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK)

#define I3C_SCAPABILITIES2_IBIEXT_MASK           (0x100U)
#define I3C_SCAPABILITIES2_IBIEXT_SHIFT          (8U)
/*! IBIEXT - In-Band Interrupt EXTDATA
 *  0b0..Not supported
 *  0b1..Supported
 */
#define I3C_SCAPABILITIES2_IBIEXT(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK)

#define I3C_SCAPABILITIES2_IBIXREG_MASK          (0x200U)
#define I3C_SCAPABILITIES2_IBIXREG_SHIFT         (9U)
/*! IBIXREG - In-Band Interrupt Extended Register
 *  0b0..Not supported
 *  0b1..Supported
 */
#define I3C_SCAPABILITIES2_IBIXREG(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK)

#define I3C_SCAPABILITIES2_SLVRST_MASK           (0x20000U)
#define I3C_SCAPABILITIES2_SLVRST_SHIFT          (17U)
/*! SLVRST - Target Reset
 *  0b0..Not supported
 *  0b1..Supported
 */
#define I3C_SCAPABILITIES2_SLVRST(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK)

#define I3C_SCAPABILITIES2_GROUP_MASK            (0xC0000U)
#define I3C_SCAPABILITIES2_GROUP_SHIFT           (18U)
/*! GROUP - Group
 *  0b00..v1.1 group addressing not supported
 *  0b01..One group supported
 *  0b10..Two groups supported
 *  0b11..Three groups supported
 */
#define I3C_SCAPABILITIES2_GROUP(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK)

#define I3C_SCAPABILITIES2_AASA_MASK             (0x200000U)
#define I3C_SCAPABILITIES2_AASA_SHIFT            (21U)
/*! AASA - SETAASA
 *  0b1..SETAASA supported
 *  0b0..SETAASA not supported
 */
#define I3C_SCAPABILITIES2_AASA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK)

#define I3C_SCAPABILITIES2_SSTSUB_MASK           (0x400000U)
#define I3C_SCAPABILITIES2_SSTSUB_SHIFT          (22U)
/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable
 *  0b1..Subscriber capable
 *  0b0..Not subscriber capable
 */
#define I3C_SCAPABILITIES2_SSTSUB(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK)

#define I3C_SCAPABILITIES2_SSTWR_MASK            (0x800000U)
#define I3C_SCAPABILITIES2_SSTWR_SHIFT           (23U)
/*! SSTWR - Target-Target(s)-Tunnel Write Capable
 *  0b1..Write capable
 *  0b0..Not write capable
 */
#define I3C_SCAPABILITIES2_SSTWR(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK)
/*! @} */

/*! @name SCAPABILITIES - Target Capabilities */
/*! @{ */

#define I3C_SCAPABILITIES_IDENA_MASK             (0x3U)
#define I3C_SCAPABILITIES_IDENA_SHIFT            (0U)
/*! IDENA - ID 48b Handler
 *  0b00..Application
 *  0b01..Hardware
 *  0b10..Hardware, but the I3C module instance handles ID 48b
 *  0b11..A part number register (PARTNO)
 */
#define I3C_SCAPABILITIES_IDENA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)

#define I3C_SCAPABILITIES_IDREG_MASK             (0x3CU)
#define I3C_SCAPABILITIES_IDREG_SHIFT            (2U)
/*! IDREG - ID Register
 *  0b0000..All ID register features disabled
 *  0bxxx1..ID Instance is a register; used if there is no PARTNO register
 *  0bxx1x..An ID Random field is available
 *  0bx1xx..A Device Characteristic Register (DCR) is available
 *  0b1xxx..A Bus Characteristics Register (BCR) is available
 */
#define I3C_SCAPABILITIES_IDREG(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)

#define I3C_SCAPABILITIES_HDRSUPP_MASK           (0xC0U)
#define I3C_SCAPABILITIES_HDRSUPP_SHIFT          (6U)
/*! HDRSUPP - High Data Rate Support
 *  0b00..No HDR modes supported
 *  0b01..DDR mode supported
 *  *..
 */
#define I3C_SCAPABILITIES_HDRSUPP(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)

#define I3C_SCAPABILITIES_MASTER_MASK            (0x200U)
#define I3C_SCAPABILITIES_MASTER_SHIFT           (9U)
/*! MASTER - Controller
 *  0b0..Not supported
 *  0b1..Supported
 */
#define I3C_SCAPABILITIES_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)

#define I3C_SCAPABILITIES_SADDR_MASK             (0xC00U)
#define I3C_SCAPABILITIES_SADDR_SHIFT            (10U)
/*! SADDR - Static Address
 *  0b00..No static address
 *  0b01..Static address is fixed in hardware
 *  0b10..Hardware controls the static address dynamically (for example, from the pin strap)
 *  0b11..SCONFIG register supplies the static address
 */
#define I3C_SCAPABILITIES_SADDR(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)

#define I3C_SCAPABILITIES_CCCHANDLE_MASK         (0xF000U)
#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT        (12U)
/*! CCCHANDLE - Common Command Codes Handling
 *  0b0000..All handling features disabled
 *  0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items
 *  0bxx1x..The I3C module manages maximum read and write lengths, and max data speed
 *  0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE]
 *  0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO]
 */
#define I3C_SCAPABILITIES_CCCHANDLE(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)

#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK         (0x1F0000U)
#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT        (16U)
/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events
 *  0b00000..Application cannot generate IBI, CR, or HJ
 *  0bxxxx1..Application can generate an IBI
 *  0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register
 *  0bxx1xx..Application can generate a controller request for a secondary controller
 *  0bx1xxx..Application can generate a Hot-Join event
 *  0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing
 */
#define I3C_SCAPABILITIES_IBI_MR_HJ(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)

#define I3C_SCAPABILITIES_TIMECTRL_MASK          (0x200000U)
#define I3C_SCAPABILITIES_TIMECTRL_SHIFT         (21U)
/*! TIMECTRL - Time Control
 *  0b0..No time control supported
 *  0b1..At least one time-control type supported
 */
#define I3C_SCAPABILITIES_TIMECTRL(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)

#define I3C_SCAPABILITIES_EXTFIFO_MASK           (0x3800000U)
#define I3C_SCAPABILITIES_EXTFIFO_SHIFT          (23U)
/*! EXTFIFO - External FIFO
 *  0b000..No external FIFO available
 *  0b001..Standard available or free external FIFO
 *  0b010..Request track external FIFO
 *  *..
 */
#define I3C_SCAPABILITIES_EXTFIFO(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)

#define I3C_SCAPABILITIES_FIFOTX_MASK            (0xC000000U)
#define I3C_SCAPABILITIES_FIFOTX_SHIFT           (26U)
/*! FIFOTX - FIFO Transmit
 *  0b00..Two
 *  0b01..Four
 *  0b10..Eight
 *  0b11..16 or larger
 */
#define I3C_SCAPABILITIES_FIFOTX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)

#define I3C_SCAPABILITIES_FIFORX_MASK            (0x30000000U)
#define I3C_SCAPABILITIES_FIFORX_SHIFT           (28U)
/*! FIFORX - FIFO Receive
 *  0b00..Two or three
 *  0b01..Four
 *  0b10..Eight
 *  0b11..16 or larger
 */
#define I3C_SCAPABILITIES_FIFORX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)

#define I3C_SCAPABILITIES_INT_MASK               (0x40000000U)
#define I3C_SCAPABILITIES_INT_SHIFT              (30U)
/*! INT - Interrupts
 *  0b1..Supported
 *  0b0..Not supported
 */
#define I3C_SCAPABILITIES_INT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)

#define I3C_SCAPABILITIES_DMA_MASK               (0x80000000U)
#define I3C_SCAPABILITIES_DMA_SHIFT              (31U)
/*! DMA - Direct Memory Access
 *  0b1..Supported
 *  0b0..Not supported
 */
#define I3C_SCAPABILITIES_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
/*! @} */

/*! @name SDYNADDR - Target Dynamic Address */
/*! @{ */

#define I3C_SDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_SDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - Dynamic Address Valid
 *  0b0..DANOTASSIGNED: a dynamic address is not assigned
 *  0b1..DAASSIGNED: a dynamic address is assigned
 */
#define I3C_SDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)

#define I3C_SDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_SDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic Address */
#define I3C_SDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)

#define I3C_SDYNADDR_MAPSA_MASK                  (0x1000U)
#define I3C_SDYNADDR_MAPSA_SHIFT                 (12U)
/*! MAPSA - Map a Static Address */
#define I3C_SDYNADDR_MAPSA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)

#define I3C_SDYNADDR_SA10B_MASK                  (0xE000U)
#define I3C_SDYNADDR_SA10B_SHIFT                 (13U)
/*! SA10B - 10-Bit Static Address */
#define I3C_SDYNADDR_SA10B(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK)

#define I3C_SDYNADDR_KEY_MASK                    (0xFFFF0000U)
#define I3C_SDYNADDR_KEY_SHIFT                   (16U)
/*! KEY - Key */
#define I3C_SDYNADDR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
/*! @} */

/*! @name SMAXLIMITS - Target Maximum Limits */
/*! @{ */

#define I3C_SMAXLIMITS_MAXRD_MASK                (0xFFFU)
#define I3C_SMAXLIMITS_MAXRD_SHIFT               (0U)
/*! MAXRD - Maximum Read Length */
#define I3C_SMAXLIMITS_MAXRD(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)

#define I3C_SMAXLIMITS_MAXWR_MASK                (0xFFF0000U)
#define I3C_SMAXLIMITS_MAXWR_SHIFT               (16U)
/*! MAXWR - Maximum Write Length */
#define I3C_SMAXLIMITS_MAXWR(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
/*! @} */

/*! @name SIDPARTNO - Target ID Part Number */
/*! @{ */

#define I3C_SIDPARTNO_PARTNO_MASK                (0xFFFFFFFFU)
#define I3C_SIDPARTNO_PARTNO_SHIFT               (0U)
/*! PARTNO - Part Number */
#define I3C_SIDPARTNO_PARTNO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
/*! @} */

/*! @name SIDEXT - Target ID Extension */
/*! @{ */

#define I3C_SIDEXT_DCR_MASK                      (0xFF00U)
#define I3C_SIDEXT_DCR_SHIFT                     (8U)
/*! DCR - Device Characteristic Register */
#define I3C_SIDEXT_DCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)

#define I3C_SIDEXT_BCR_MASK                      (0xFF0000U)
#define I3C_SIDEXT_BCR_SHIFT                     (16U)
/*! BCR - Bus Characteristics Register */
#define I3C_SIDEXT_BCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
/*! @} */

/*! @name SVENDORID - Target Vendor ID */
/*! @{ */

#define I3C_SVENDORID_VID_MASK                   (0x7FFFU)
#define I3C_SVENDORID_VID_SHIFT                  (0U)
/*! VID - Vendor ID */
#define I3C_SVENDORID_VID(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
/*! @} */

/*! @name STCCLOCK - Target Time Control Clock */
/*! @{ */

#define I3C_STCCLOCK_ACCURACY_MASK               (0xFFU)
#define I3C_STCCLOCK_ACCURACY_SHIFT              (0U)
/*! ACCURACY - Clock Accuracy */
#define I3C_STCCLOCK_ACCURACY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)

#define I3C_STCCLOCK_FREQ_MASK                   (0xFF00U)
#define I3C_STCCLOCK_FREQ_SHIFT                  (8U)
/*! FREQ - Clock Frequency */
#define I3C_STCCLOCK_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
/*! @} */

/*! @name SMSGMAPADDR - Target Message Map Address */
/*! @{ */

#define I3C_SMSGMAPADDR_MAPLAST_MASK             (0xFU)
#define I3C_SMSGMAPADDR_MAPLAST_SHIFT            (0U)
/*! MAPLAST - Matched Address Index */
#define I3C_SMSGMAPADDR_MAPLAST(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)

#define I3C_SMSGMAPADDR_LASTSTATIC_MASK          (0x10U)
#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT         (4U)
/*! LASTSTATIC - Last Static Address Matched
 *  0b1..I2C static address
 *  0b0..I3C dynamic address
 */
#define I3C_SMSGMAPADDR_LASTSTATIC(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK)

#define I3C_SMSGMAPADDR_MAPLASTM1_MASK           (0xF00U)
#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT          (8U)
/*! MAPLASTM1 - Matched Previous Address Index 1 */
#define I3C_SMSGMAPADDR_MAPLASTM1(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)

#define I3C_SMSGMAPADDR_MAPLASTM2_MASK           (0xF0000U)
#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT          (16U)
/*! MAPLASTM2 - Matched Previous Index 2 */
#define I3C_SMSGMAPADDR_MAPLASTM2(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
/*! @} */

/*! @name MCONFIG_EXT - Controller Extended Configuration */
/*! @{ */

#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK         (0x30000U)
#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT        (16U)
/*! I3C_CAS_DEL - I3C CAS Delay After START
 *  0b00..No delay
 *  0b01..Increases SCL clock period by 1/2
 *  0b10..Increases SCL clock period by 1
 *  0b11..Increases SCL clock period by 3/2
 */
#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x)           (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK)

#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK        (0xC0000U)
#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT       (18U)
/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START
 *  0b00..No delay
 *  0b01..Increases SCL clock period by 1/2
 *  0b10..Increases SCL clock period by 1
 *  0b11..Increases SCL clock period by 1 1/2
 */
#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x)          (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK)
/*! @} */

/*! @name MCTRL - Controller Control */
/*! @{ */

#define I3C_MCTRL_REQUEST_MASK                   (0x7U)
#define I3C_MCTRL_REQUEST_SHIFT                  (0U)
/*! REQUEST - Request
 *  0b000..NONE
 *  0b001..EMITSTARTADDR
 *  0b010..EMITSTOP
 *  0b011..IBIACKNACK
 *  0b100..PROCESSDAA
 *  0b101..
 *  0b110..Force Exit and Target Reset
 *  0b111..AUTOIBI
 */
#define I3C_MCTRL_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)

#define I3C_MCTRL_TYPE_MASK                      (0x30U)
#define I3C_MCTRL_TYPE_SHIFT                     (4U)
/*! TYPE - Bus Type with EmitStartAddr
 *  0b00..I3C
 *  0b01..I2C
 *  0b10..DDR
 *  0b11..
 */
#define I3C_MCTRL_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)

#define I3C_MCTRL_IBIRESP_MASK                   (0xC0U)
#define I3C_MCTRL_IBIRESP_SHIFT                  (6U)
/*! IBIRESP - In-Band Interrupt Response
 *  0b00..ACK (acknowledge)
 *  0b01..NACK (reject)
 *  0b10..Acknowledge with mandatory byte
 *  0b11..Manual
 */
#define I3C_MCTRL_IBIRESP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)

#define I3C_MCTRL_DIR_MASK                       (0x100U)
#define I3C_MCTRL_DIR_SHIFT                      (8U)
/*! DIR - Direction
 *  0b0..Write
 *  0b1..Read
 */
#define I3C_MCTRL_DIR(x)                         (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)

#define I3C_MCTRL_ADDR_MASK                      (0xFE00U)
#define I3C_MCTRL_ADDR_SHIFT                     (9U)
/*! ADDR - Address */
#define I3C_MCTRL_ADDR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)

#define I3C_MCTRL_RDTERM_MASK                    (0xFF0000U)
#define I3C_MCTRL_RDTERM_SHIFT                   (16U)
/*! RDTERM - Read Terminate Counter */
#define I3C_MCTRL_RDTERM(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
/*! @} */

/*! @name MSTATUS - Controller Status */
/*! @{ */

#define I3C_MSTATUS_STATE_MASK                   (0x7U)
#define I3C_MSTATUS_STATE_SHIFT                  (0U)
/*! STATE - State of the Controller
 *  0b000..IDLE (bus has stopped)
 *  0b001..SLVREQ (target request)
 *  0b010..MSGSDR
 *  0b011..NORMACT
 *  0b100..MSGDDR
 *  0b101..DAA
 *  0b110..IBIACK
 *  0b111..IBIRCV
 */
#define I3C_MSTATUS_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)

#define I3C_MSTATUS_BETWEEN_MASK                 (0x10U)
#define I3C_MSTATUS_BETWEEN_SHIFT                (4U)
/*! BETWEEN - Between
 *  0b0..Inactive (for other cases)
 *  0b1..Active
 */
#define I3C_MSTATUS_BETWEEN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)

#define I3C_MSTATUS_NACKED_MASK                  (0x20U)
#define I3C_MSTATUS_NACKED_SHIFT                 (5U)
/*! NACKED - Not Acknowledged
 *  0b1..NACKed (not acknowledged)
 *  0b0..Not NACKed
 */
#define I3C_MSTATUS_NACKED(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)

#define I3C_MSTATUS_IBITYPE_MASK                 (0xC0U)
#define I3C_MSTATUS_IBITYPE_SHIFT                (6U)
/*! IBITYPE - In-Band Interrupt (IBI) Type
 *  0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0)
 *  0b01..IBI
 *  0b10..CR
 *  0b11..HJ
 */
#define I3C_MSTATUS_IBITYPE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)

#define I3C_MSTATUS_SLVSTART_MASK                (0x100U)
#define I3C_MSTATUS_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Target Start Flag
 *  0b1..Target requesting START
 *  0b0..Target not requesting START
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MSTATUS_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)

#define I3C_MSTATUS_MCTRLDONE_MASK               (0x200U)
#define I3C_MSTATUS_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Controller Control Done Flag
 *  0b1..Done
 *  0b0..Not done
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MSTATUS_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)

#define I3C_MSTATUS_COMPLETE_MASK                (0x400U)
#define I3C_MSTATUS_COMPLETE_SHIFT               (10U)
/*! COMPLETE - Complete Flag
 *  0b1..Complete
 *  0b0..Not complete
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MSTATUS_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)

#define I3C_MSTATUS_RXPEND_MASK                  (0x800U)
#define I3C_MSTATUS_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND
 *  0b1..Receive message pending
 *  0b0..No receive message pending
 */
#define I3C_MSTATUS_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)

#define I3C_MSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_MSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX Buffer or FIFO Not Full
 *  0b1..Receive buffer or FIFO not full
 *  0b0..Receive buffer or FIFO full
 */
#define I3C_MSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)

#define I3C_MSTATUS_IBIWON_MASK                  (0x2000U)
#define I3C_MSTATUS_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) Won Flag
 *  0b1..IBI arbitration won
 *  0b0..No IBI arbitration won
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MSTATUS_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)

#define I3C_MSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_MSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or Warning
 *  0b1..Error or warning
 *  0b0..No error or warning
 */
#define I3C_MSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)

#define I3C_MSTATUS_NOWMASTER_MASK               (0x80000U)
#define I3C_MSTATUS_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Module is now Controller Flag
 *  0b1..Controller
 *  0b0..Not a controller
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MSTATUS_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)

#define I3C_MSTATUS_IBIADDR_MASK                 (0x7F000000U)
#define I3C_MSTATUS_IBIADDR_SHIFT                (24U)
/*! IBIADDR - IBI Address */
#define I3C_MSTATUS_IBIADDR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
/*! @} */

/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */
/*! @{ */

#define I3C_MIBIRULES_ADDR0_MASK                 (0x3FU)
#define I3C_MIBIRULES_ADDR0_SHIFT                (0U)
/*! ADDR0 - ADDR0 */
#define I3C_MIBIRULES_ADDR0(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)

#define I3C_MIBIRULES_ADDR1_MASK                 (0xFC0U)
#define I3C_MIBIRULES_ADDR1_SHIFT                (6U)
/*! ADDR1 - ADDR1 */
#define I3C_MIBIRULES_ADDR1(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)

#define I3C_MIBIRULES_ADDR2_MASK                 (0x3F000U)
#define I3C_MIBIRULES_ADDR2_SHIFT                (12U)
/*! ADDR2 - ADDR2 */
#define I3C_MIBIRULES_ADDR2(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)

#define I3C_MIBIRULES_ADDR3_MASK                 (0xFC0000U)
#define I3C_MIBIRULES_ADDR3_SHIFT                (18U)
/*! ADDR3 - ADDR3 */
#define I3C_MIBIRULES_ADDR3(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)

#define I3C_MIBIRULES_ADDR4_MASK                 (0x3F000000U)
#define I3C_MIBIRULES_ADDR4_SHIFT                (24U)
/*! ADDR4 - ADDR4 */
#define I3C_MIBIRULES_ADDR4(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)

#define I3C_MIBIRULES_MSB0_MASK                  (0x40000000U)
#define I3C_MIBIRULES_MSB0_SHIFT                 (30U)
/*! MSB0 - Most Significant Address Bit is 0
 *  0b1..MSB is 0
 *  0b0..MSB is not 0
 */
#define I3C_MIBIRULES_MSB0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)

#define I3C_MIBIRULES_NOBYTE_MASK                (0x80000000U)
#define I3C_MIBIRULES_NOBYTE_SHIFT               (31U)
/*! NOBYTE - No IBI byte
 *  0b1..Without mandatory IBI byte
 *  0b0..With mandatory IBI byte
 */
#define I3C_MIBIRULES_NOBYTE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
/*! @} */

/*! @name MINTSET - Controller Interrupt Set */
/*! @{ */

#define I3C_MINTSET_SLVSTART_MASK                (0x100U)
#define I3C_MINTSET_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Target Start Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MINTSET_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)

#define I3C_MINTSET_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTSET_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Controller Control Done Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MINTSET_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)

#define I3C_MINTSET_COMPLETE_MASK                (0x400U)
#define I3C_MINTSET_COMPLETE_SHIFT               (10U)
/*! COMPLETE - Completed Message Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MINTSET_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)

#define I3C_MINTSET_RXPEND_MASK                  (0x800U)
#define I3C_MINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - Receive Pending Interrupt Enable */
#define I3C_MINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)

#define I3C_MINTSET_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTSET_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MINTSET_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)

#define I3C_MINTSET_IBIWON_MASK                  (0x2000U)
#define I3C_MINTSET_IBIWON_SHIFT                 (13U)
/*! IBIWON - IBI Won Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MINTSET_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)

#define I3C_MINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)

#define I3C_MINTSET_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTSET_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now Controller Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define I3C_MINTSET_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
/*! @} */

/*! @name MINTCLR - Controller Interrupt Clear */
/*! @{ */

#define I3C_MINTCLR_SLVSTART_MASK                (0x100U)
#define I3C_MINTCLR_SLVSTART_SHIFT               (8U)
/*! SLVSTART - SLVSTART Interrupt Enable Clear Flag
 *  0b1..Interrupt enable cleared
 *  0b0..No effect
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MINTCLR_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)

#define I3C_MINTCLR_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTCLR_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear Flag
 *  0b1..Interrupt enable cleared
 *  0b0..No effect
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MINTCLR_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)

#define I3C_MINTCLR_COMPLETE_MASK                (0x400U)
#define I3C_MINTCLR_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE Interrupt Enable Clear Flag
 *  0b1..Interrupt enable cleared
 *  0b0..No effect
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MINTCLR_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)

#define I3C_MINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_MINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND Interrupt Enable Clear Flag
 *  0b1..Interrupt enable cleared
 *  0b0..No effect
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)

#define I3C_MINTCLR_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTCLR_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear Flag
 *  0b1..Interrupt enable cleared
 *  0b0..No effect
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MINTCLR_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)

#define I3C_MINTCLR_IBIWON_MASK                  (0x2000U)
#define I3C_MINTCLR_IBIWON_SHIFT                 (13U)
/*! IBIWON - IBIWON Interrupt Enable Clear Flag
 *  0b1..Interrupt enable cleared
 *  0b0..No effect
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MINTCLR_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)

#define I3C_MINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN Interrupt Enable Clear Flag
 *  0b1..Interrupt enable cleared
 *  0b0..No effect
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)

#define I3C_MINTCLR_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTCLR_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear Flag
 *  0b1..Interrupt enable cleared
 *  0b0..No effect
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MINTCLR_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
/*! @} */

/*! @name MINTMASKED - Controller Interrupt Mask */
/*! @{ */

#define I3C_MINTMASKED_SLVSTART_MASK             (0x100U)
#define I3C_MINTMASKED_SLVSTART_SHIFT            (8U)
/*! SLVSTART - SLVSTART Interrupt Mask
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define I3C_MINTMASKED_SLVSTART(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)

#define I3C_MINTMASKED_MCTRLDONE_MASK            (0x200U)
#define I3C_MINTMASKED_MCTRLDONE_SHIFT           (9U)
/*! MCTRLDONE - MCTRLDONE Interrupt Mask
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define I3C_MINTMASKED_MCTRLDONE(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)

#define I3C_MINTMASKED_COMPLETE_MASK             (0x400U)
#define I3C_MINTMASKED_COMPLETE_SHIFT            (10U)
/*! COMPLETE - COMPLETE Interrupt Mask
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define I3C_MINTMASKED_COMPLETE(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)

#define I3C_MINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_MINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND Interrupt Mask */
#define I3C_MINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)

#define I3C_MINTMASKED_TXNOTFULL_MASK            (0x1000U)
#define I3C_MINTMASKED_TXNOTFULL_SHIFT           (12U)
/*! TXNOTFULL - TXNOTFULL Interrupt Mask
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define I3C_MINTMASKED_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)

#define I3C_MINTMASKED_IBIWON_MASK               (0x2000U)
#define I3C_MINTMASKED_IBIWON_SHIFT              (13U)
/*! IBIWON - IBIWON Interrupt Mask
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define I3C_MINTMASKED_IBIWON(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)

#define I3C_MINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_MINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN Interrupt Mask
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define I3C_MINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)

#define I3C_MINTMASKED_NOWMASTER_MASK            (0x80000U)
#define I3C_MINTMASKED_NOWMASTER_SHIFT           (19U)
/*! NOWMASTER - NOWCONTROLLER Interrupt Mask
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define I3C_MINTMASKED_NOWMASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
/*! @} */

/*! @name MERRWARN - Controller Errors and Warnings */
/*! @{ */

#define I3C_MERRWARN_URUN_MASK                   (0x2U)
#define I3C_MERRWARN_URUN_SHIFT                  (1U)
/*! URUN - Underrun Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK)

#define I3C_MERRWARN_NACK_MASK                   (0x4U)
#define I3C_MERRWARN_NACK_SHIFT                  (2U)
/*! NACK - Not Acknowledge Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_NACK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)

#define I3C_MERRWARN_WRABT_MASK                  (0x8U)
#define I3C_MERRWARN_WRABT_SHIFT                 (3U)
/*! WRABT - Write Abort Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_WRABT(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)

#define I3C_MERRWARN_TERM_MASK                   (0x10U)
#define I3C_MERRWARN_TERM_SHIFT                  (4U)
/*! TERM - Terminate Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK)

#define I3C_MERRWARN_HPAR_MASK                   (0x200U)
#define I3C_MERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - High Data Rate Parity Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)

#define I3C_MERRWARN_HCRC_MASK                   (0x400U)
#define I3C_MERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - High Data Rate CRC Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)

#define I3C_MERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_MERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Overread Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)

#define I3C_MERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_MERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Overwrite Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)

#define I3C_MERRWARN_MSGERR_MASK                 (0x40000U)
#define I3C_MERRWARN_MSGERR_SHIFT                (18U)
/*! MSGERR - Message Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_MSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)

#define I3C_MERRWARN_INVREQ_MASK                 (0x80000U)
#define I3C_MERRWARN_INVREQ_SHIFT                (19U)
/*! INVREQ - Invalid Request Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_INVREQ(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)

#define I3C_MERRWARN_TIMEOUT_MASK                (0x100000U)
#define I3C_MERRWARN_TIMEOUT_SHIFT               (20U)
/*! TIMEOUT - Timeout Error Flag
 *  0b1..Error
 *  0b0..No error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define I3C_MERRWARN_TIMEOUT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
/*! @} */

/*! @name MDMACTRL - Controller DMA Control */
/*! @{ */

#define I3C_MDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_MDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA from Bus
 *  0b00..DMA not used
 *  0b01..Enable DMA for one frame
 *  0b10..Enable DMA until DMA is turned off
 *  0b11..
 */
#define I3C_MDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)

#define I3C_MDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_MDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA to Bus
 *  0b00..DMA not used
 *  0b01..Enable DMA for one frame (ended by DMA or terminated)
 *  0b10..Enable DMA until DMA is turned off
 *  0b11..
 */
#define I3C_MDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)

#define I3C_MDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_MDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - DMA Width
 *  0b00, 0b01..Byte
 *  0b10..Halfword (16 bits)
 *  0b11..
 */
#define I3C_MDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name MDATACTRL - Controller Data Control */
/*! @{ */

#define I3C_MDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_MDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush To-Bus Buffer or FIFO
 *  0b1..Flush the buffer
 *  0b0..No action
 */
#define I3C_MDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)

#define I3C_MDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_MDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flush From-Bus Buffer or FIFO
 *  0b1..Flush the buffer
 *  0b0..No action
 */
#define I3C_MDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)

#define I3C_MDATACTRL_UNLOCK_MASK                (0x8U)
#define I3C_MDATACTRL_UNLOCK_SHIFT               (3U)
/*! UNLOCK - Unlock
 *  0b0..Locked
 *  0b1..Unlocked
 */
#define I3C_MDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)

#define I3C_MDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_MDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - Transmit Trigger Level
 *  0b00..Trigger when empty
 *  0b01..Trigger when 1/4 full or less
 *  0b10..Trigger when 1/2 full or less
 *  0b11..Trigger when 1 less than full or less (default)
 */
#define I3C_MDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)

#define I3C_MDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_MDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - Receive Trigger Level
 *  0b00..Trigger when not empty (default)
 *  0b01..Trigger when 1/4 full or more
 *  0b10..Trigger when 1/2 full or more
 *  0b11..Trigger when 3/4 full or more
 */
#define I3C_MDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)

#define I3C_MDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_MDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - Transmit Byte Count */
#define I3C_MDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)

#define I3C_MDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_MDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - Receive Byte Count */
#define I3C_MDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)

#define I3C_MDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_MDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - Transmit is Full
 *  0b0..Not full
 *  0b1..Full
 */
#define I3C_MDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)

#define I3C_MDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_MDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - Receive is Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define I3C_MDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name MWDATAB - Controller Write Data Byte */
/*! @{ */

#define I3C_MWDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MWDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - Data Byte */
#define I3C_MWDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)

#define I3C_MWDATAB_END_MASK                     (0x100U)
#define I3C_MWDATAB_END_SHIFT                    (8U)
/*! END - End of Message
 *  0b0..Not the end
 *  0b1..End
 */
#define I3C_MWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)

#define I3C_MWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_MWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End of Message ALSO
 *  0b0..Not the end
 *  0b1..End
 */
#define I3C_MWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name MWDATABE - Controller Write Data Byte End */
/*! @{ */

#define I3C_MWDATABE_VALUE_MASK                  (0xFFU)
#define I3C_MWDATABE_VALUE_SHIFT                 (0U)
/*! VALUE - Data */
#define I3C_MWDATABE_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
/*! @} */

/*! @name MWDATAH - Controller Write Data Halfword */
/*! @{ */

#define I3C_MWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_MWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - Data Byte 0 */
#define I3C_MWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)

#define I3C_MWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_MWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - Data Byte 1 */
#define I3C_MWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)

#define I3C_MWDATAH_END_MASK                     (0x10000U)
#define I3C_MWDATAH_END_SHIFT                    (16U)
/*! END - End of Message
 *  0b0..Not the end
 *  0b1..End
 */
#define I3C_MWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
/*! @} */

/*! @name MWDATAHE - Controller Write Data Halfword End */
/*! @{ */

#define I3C_MWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_MWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - Data Byte 0 */
#define I3C_MWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)

#define I3C_MWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_MWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - Data Byte 1 */
#define I3C_MWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
/*! @} */

/*! @name MRDATAB - Controller Read Data Byte */
/*! @{ */

#define I3C_MRDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MRDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - Value */
#define I3C_MRDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
/*! @} */

/*! @name MRDATAH - Controller Read Data Halfword */
/*! @{ */

#define I3C_MRDATAH_LSB_MASK                     (0xFFU)
#define I3C_MRDATAH_LSB_SHIFT                    (0U)
/*! LSB - Low Byte */
#define I3C_MRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)

#define I3C_MRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_MRDATAH_MSB_SHIFT                    (8U)
/*! MSB - High Byte */
#define I3C_MRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
/*! @} */

/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */
/*! @{ */

#define I3C_MWDATAB1_VALUE_MASK                  (0xFFU)
#define I3C_MWDATAB1_VALUE_SHIFT                 (0U)
/*! VALUE - Value */
#define I3C_MWDATAB1_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK)
/*! @} */

/*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */
/*! @{ */

#define I3C_MWDATAH1_VALUE_MASK                  (0xFFFFU)
#define I3C_MWDATAH1_VALUE_SHIFT                 (0U)
/*! VALUE - Value */
#define I3C_MWDATAH1_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK)
/*! @} */

/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */
/*! @{ */

#define I3C_MWMSG_SDR_CONTROL_DIR_MASK           (0x1U)
#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT          (0U)
/*! DIR - Direction
 *  0b0..Write
 *  0b1..Read
 */
#define I3C_MWMSG_SDR_CONTROL_DIR(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)

#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK          (0xFEU)
#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT         (1U)
/*! ADDR - Address */
#define I3C_MWMSG_SDR_CONTROL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)

#define I3C_MWMSG_SDR_CONTROL_END_MASK           (0x100U)
#define I3C_MWMSG_SDR_CONTROL_END_SHIFT          (8U)
/*! END - End of SDR Message
 *  0b0..Not the end
 *  0b1..End
 */
#define I3C_MWMSG_SDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)

#define I3C_MWMSG_SDR_CONTROL_I2C_MASK           (0x400U)
#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT          (10U)
/*! I2C - I2C
 *  0b0..I3C message
 *  0b1..I2C message
 */
#define I3C_MWMSG_SDR_CONTROL_I2C(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)

#define I3C_MWMSG_SDR_CONTROL_LEN_MASK           (0xF800U)
#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT          (11U)
/*! LEN - Length */
#define I3C_MWMSG_SDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
/*! @} */

/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */
/*! @{ */

#define I3C_MWMSG_SDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data */
#define I3C_MWMSG_SDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)
/*! @} */

/*! @name MRMSG_SDR - Controller Read Message in SDR mode */
/*! @{ */

#define I3C_MRMSG_SDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_SDR_DATA_SHIFT                 (0U)
/*! DATA - Data */
#define I3C_MRMSG_SDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
/*! @} */

/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */
/*! @{ */

#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK       (0xFFFFU)
#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT      (0U)
/*! ADDRCMD - Address Command */
#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x)         (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK)
/*! @} */

/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */
/*! @{ */

#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK          (0x3FFU)
#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT         (0U)
/*! LEN - Length of Message */
#define I3C_MWMSG_DDR_CONTROL2_LEN(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK)

#define I3C_MWMSG_DDR_CONTROL2_END_MASK          (0x4000U)
#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT         (14U)
/*! END - End of Message
 *  0b1..End
 *  0b0..Not the end
 */
#define I3C_MWMSG_DDR_CONTROL2_END(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK)
/*! @} */

/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */
/*! @{ */

#define I3C_MWMSG_DDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data */
#define I3C_MWMSG_DDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)
/*! @} */

/*! @name MRMSG_DDR - Controller Read Message in DDR mode */
/*! @{ */

#define I3C_MRMSG_DDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_DDR_DATA_SHIFT                 (0U)
/*! DATA - Data */
#define I3C_MRMSG_DDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)
/*! @} */

/*! @name MDYNADDR - Controller Dynamic Address */
/*! @{ */

#define I3C_MDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_MDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - Dynamic Address Valid
 *  0b1..Valid DA assigned
 *  0b0..No valid DA assigned
 */
#define I3C_MDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)

#define I3C_MDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_MDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic Address */
#define I3C_MDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
/*! @} */

/*! @name SMAPCTRL0 - Map Feature Control 0 */
/*! @{ */

#define I3C_SMAPCTRL0_ENA_MASK                   (0x1U)
#define I3C_SMAPCTRL0_ENA_SHIFT                  (0U)
/*! ENA - Enable Primary Dynamic Address
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I3C_SMAPCTRL0_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK)

#define I3C_SMAPCTRL0_DA_MASK                    (0xFEU)
#define I3C_SMAPCTRL0_DA_SHIFT                   (1U)
/*! DA - Dynamic Address */
#define I3C_SMAPCTRL0_DA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK)

#define I3C_SMAPCTRL0_CAUSE_MASK                 (0x700U)
#define I3C_SMAPCTRL0_CAUSE_SHIFT                (8U)
/*! CAUSE - Cause
 *  0b000..No information (this value occurs when not configured to write DA)
 *  0b001..Set using ENTDAA
 *  0b010..Set using SETDASA, SETAASA, or SETNEWDA
 *  0b011..Cleared using RSTDAA
 *  0b100..Auto MAP change happened last
 *  *..
 */
#define I3C_SMAPCTRL0_CAUSE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK)
/*! @} */

/*! @name IBIEXT1 - Extended IBI Data 1 */
/*! @{ */

#define I3C_IBIEXT1_CNT_MASK                     (0x7U)
#define I3C_IBIEXT1_CNT_SHIFT                    (0U)
/*! CNT - Count */
#define I3C_IBIEXT1_CNT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK)

#define I3C_IBIEXT1_MAX_MASK                     (0x70U)
#define I3C_IBIEXT1_MAX_SHIFT                    (4U)
/*! MAX - Maximum */
#define I3C_IBIEXT1_MAX(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK)

#define I3C_IBIEXT1_EXT1_MASK                    (0xFF00U)
#define I3C_IBIEXT1_EXT1_SHIFT                   (8U)
/*! EXT1 - Extra Byte 1 */
#define I3C_IBIEXT1_EXT1(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK)

#define I3C_IBIEXT1_EXT2_MASK                    (0xFF0000U)
#define I3C_IBIEXT1_EXT2_SHIFT                   (16U)
/*! EXT2 - Extra Byte 2 */
#define I3C_IBIEXT1_EXT2(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK)

#define I3C_IBIEXT1_EXT3_MASK                    (0xFF000000U)
#define I3C_IBIEXT1_EXT3_SHIFT                   (24U)
/*! EXT3 - Extra Byte 3 */
#define I3C_IBIEXT1_EXT3(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK)
/*! @} */

/*! @name IBIEXT2 - Extended IBI Data 2 */
/*! @{ */

#define I3C_IBIEXT2_EXT4_MASK                    (0xFFU)
#define I3C_IBIEXT2_EXT4_SHIFT                   (0U)
/*! EXT4 - Extra Byte 4 */
#define I3C_IBIEXT2_EXT4(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK)

#define I3C_IBIEXT2_EXT5_MASK                    (0xFF00U)
#define I3C_IBIEXT2_EXT5_SHIFT                   (8U)
/*! EXT5 - Extra Byte 5 */
#define I3C_IBIEXT2_EXT5(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK)

#define I3C_IBIEXT2_EXT6_MASK                    (0xFF0000U)
#define I3C_IBIEXT2_EXT6_SHIFT                   (16U)
/*! EXT6 - Extra Byte 6 */
#define I3C_IBIEXT2_EXT6(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK)

#define I3C_IBIEXT2_EXT7_MASK                    (0xFF000000U)
#define I3C_IBIEXT2_EXT7_SHIFT                   (24U)
/*! EXT7 - Extra Byte 7 */
#define I3C_IBIEXT2_EXT7(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK)
/*! @} */

/*! @name SID - Target Module ID */
/*! @{ */

#define I3C_SID_ID_MASK                          (0xFFFFFFFFU)
#define I3C_SID_ID_SHIFT                         (0U)
/*! ID - ID */
#define I3C_SID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I3C_Register_Masks */


/* I3C - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral I3C0 base address */
  #define I3C0_BASE                                (0x50037000u)
  /** Peripheral I3C0 base address */
  #define I3C0_BASE_NS                             (0x40037000u)
  /** Peripheral I3C0 base pointer */
  #define I3C0                                     ((I3C_Type *)I3C0_BASE)
  /** Peripheral I3C0 base pointer */
  #define I3C0_NS                                  ((I3C_Type *)I3C0_BASE_NS)
  /** Peripheral I3C1 base address */
  #define I3C1_BASE                                (0x50038000u)
  /** Peripheral I3C1 base address */
  #define I3C1_BASE_NS                             (0x40038000u)
  /** Peripheral I3C1 base pointer */
  #define I3C1                                     ((I3C_Type *)I3C1_BASE)
  /** Peripheral I3C1 base pointer */
  #define I3C1_NS                                  ((I3C_Type *)I3C1_BASE_NS)
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS                           { I3C0_BASE, I3C1_BASE }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS                            { I3C0, I3C1 }
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS_NS                        { I3C0_BASE_NS, I3C1_BASE_NS }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS_NS                         { I3C0_NS, I3C1_NS }
#else
  /** Peripheral I3C0 base address */
  #define I3C0_BASE                                (0x40037000u)
  /** Peripheral I3C0 base pointer */
  #define I3C0                                     ((I3C_Type *)I3C0_BASE)
  /** Peripheral I3C1 base address */
  #define I3C1_BASE                                (0x40038000u)
  /** Peripheral I3C1 base pointer */
  #define I3C1                                     ((I3C_Type *)I3C1_BASE)
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS                           { I3C0_BASE, I3C1_BASE }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS                            { I3C0, I3C1 }
#endif
/** Interrupt vectors for the I3C peripheral type */
#define I3C_IRQS                                 { I3C0_IRQn, I3C1_IRQn }

/*!
 * @}
 */ /* end of group I3C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- INPUTMUX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
 * @{
 */

/** INPUTMUX - Register Layout Typedef */
typedef struct {
  __IO uint32_t SCT0_TRIG[7];                      /**< SCT0 Input Connections, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[228];
  __IO uint32_t PINT0_TRIG[8];                     /**< PINT0 Input Connections, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[32];
  __IO uint32_t HIFI4_INTERRUPT[27];               /**< HiFi4 Interrupt Connections, array offset: 0x140, array step: 0x4 */
       uint8_t RESERVED_2[84];
  struct {                                         /* offset: 0x200, array step: 0x20 */
    __IO uint32_t LP_FLEXCOMM_TRIG;                  /**< LP_FLEXCOMM Input Connections, array offset: 0x200, array step: 0x20 */
         uint8_t RESERVED_0[28];
  } FLEXCOMM_TRIG[14];
       uint8_t RESERVED_3[576];
  struct {                                         /* offset: 0x600, array step: 0x20 */
    __IO uint32_t CAP[4];                            /**< CTIMER Input Connections, array offset: 0x600, array step: index*0x20, index2*0x4 */
    __IO uint32_t TRIG;                              /**< CTIMER Input Connections, array offset: 0x610, array step: 0x20 */
         uint8_t RESERVED_0[12];
  } CTIMER[5];
       uint8_t RESERVED_4[96];
  __IO uint32_t FREQME_TRIG[2];                    /**< FREQME Clock Selection, array offset: 0x700, array step: 0x4 */
       uint8_t RESERVED_5[24];
  __IO uint32_t EZHV_TRIG[8];                      /**< EZH-V Input Connections, array offset: 0x720, array step: 0x4 */
       uint8_t RESERVED_6[32];
  __IO uint32_t FLEXIO_TRIG[4];                    /**< FLEXIO Input Connections, array offset: 0x760, array step: 0x4 */
} INPUTMUX_Type;

/* ----------------------------------------------------------------------------
   -- INPUTMUX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
 * @{
 */

/*! @name SCT0_TRIG - SCT0 Input Connections */
/*! @{ */

#define INPUTMUX_SCT0_TRIG_TRIGIN_MASK           (0x1FU)
#define INPUTMUX_SCT0_TRIG_TRIGIN_SHIFT          (0U)
/*! TRIGIN - SCT0 Input Trigger
 *  0b00000..Selects SCT0_GPIN0
 *  0b00001..Selects SCT0_GPIN1
 *  0b00010..Selects SCT0_GPIN2
 *  0b00011..Selects SCT0_GPIN3
 *  0b00100..Selects SCT0_GPIN4
 *  0b00101..Selects SCT0_GPIN5
 *  0b00110..Selects SCT0_GPIN6
 *  0b00111..Selects SCT0_GPIN7
 *  0b01000..Selects CTIMER0_MAT0
 *  0b01001..Selects CTIMER1_MAT0
 *  0b01010..Selects CTIMER2_MAT0
 *  0b01011..Selects CTIMER3_MAT0
 *  0b01100..Selects CTIMER4_MAT0
 *  0b01101..Selects USB1 start of frame
 *  0b01110..Selects PINT0 boolean pattern-match output
 *  0b01111..Selects USB0 start of frame
 *  0b10000..Selects ACMP0 CMPO
 *  0b10001..Selects SAI0_TX_BCLK
 *  0b10010..Selects SAI0_RX_BCLK
 *  0b10011..Selects SAI1_TX_BCLK
 *  0b10100..Selects SAI1_RX_BCLK
 *  0b10101..Selects SAI2_TX_BCLK
 *  0b10110..Selects SAI2_RX_BCLK
 *  0b10111..Selects MCLK
 *  0b11000..Selects CPU0 TXEV
 *  0b11001..Selects CPU0 Halted
 *  0b11010..Selects ADC0 trigger completion flag 0
 *  0b11011..Selects ADC0 trigger completion flag 1
 *  *..
 */
#define INPUTMUX_SCT0_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_SCT0_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_SCT0_TRIG */
#define INPUTMUX_SCT0_TRIG_COUNT                 (7U)

/*! @name PINT0_TRIG - PINT0 Input Connections */
/*! @{ */

#define INPUTMUX_PINT0_TRIG_TRIGIN_MASK          (0x3FU)
#define INPUTMUX_PINT0_TRIG_TRIGIN_SHIFT         (0U)
/*! TRIGIN - PINT0 Input Trigger
 *  0b000000..Selects PIO0_0
 *  0b000001..Selects PIO0_1
 *  0b000010..Selects PIO0_2
 *  0b000011..Selects PIO0_3
 *  0b000100..Selects PIO0_4
 *  0b000101..Selects PIO0_5
 *  0b000110..Selects PIO0_6
 *  0b000111..Selects PIO0_7
 *  0b001000..Selects PIO0_8
 *  0b001001..Selects PIO0_9
 *  0b001010..Selects PIO0_10
 *  0b001011..Selects PIO0_11
 *  0b001100..Selects PIO0_12
 *  0b001101..Selects PIO0_13
 *  0b001110..Selects PIO0_14
 *  0b001111..Selects PIO0_15
 *  0b010000..Selects PIO0_16
 *  0b010001..Selects PIO0_17
 *  0b010010..Selects PIO0_18
 *  0b010011..Selects PIO0_19
 *  0b010100..Selects PIO0_20
 *  0b010101..Selects PIO0_21
 *  0b010110..Selects PIO0_22
 *  0b010111..Selects PIO0_23
 *  0b011000..Selects PIO0_24
 *  0b011001..Selects PIO0_25
 *  0b011010..Selects PIO0_26
 *  0b011011..Selects PIO0_27
 *  0b011100..Selects PIO0_28
 *  0b011101..Selects PIO0_29
 *  0b011110..Selects PIO0_30
 *  0b011111..Selects PIO0_31
 *  0b100000..Selects PIO1_0
 *  0b100001..Selects PIO1_1
 *  0b100010..Selects PIO1_2
 *  0b100011..Selects PIO1_3
 *  0b100100..Selects PIO1_4
 *  0b100101..Selects PIO1_5
 *  0b100110..Selects PIO1_6
 *  0b100111..Selects PIO1_7
 *  0b101000..Selects PIO1_8
 *  0b101001..Selects PIO1_9
 *  0b101010..Selects PIO1_10
 *  0b101011..Selects PIO1_11
 *  0b101100..Selects PIO1_12
 *  0b101101..Selects PIO1_13
 *  0b101110..Selects PIO1_14
 *  0b101111..Selects PIO1_15
 *  0b110000..Selects PIO1_16
 *  0b110001..Selects PIO1_17
 *  0b110010..Selects PIO1_18
 *  0b110011..Selects PIO1_19
 *  *..
 */
#define INPUTMUX_PINT0_TRIG_TRIGIN(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINT0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_PINT0_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_PINT0_TRIG */
#define INPUTMUX_PINT0_TRIG_COUNT                (8U)

/*! @name HIFI4_INTERRUPT - HiFi4 Interrupt Connections */
/*! @{ */

#define INPUTMUX_HIFI4_INTERRUPT_TRIGIN_MASK     (0x7FU)
#define INPUTMUX_HIFI4_INTERRUPT_TRIGIN_SHIFT    (0U)
/*! TRIGIN - HiFi4 Input Interrupt
 *  0b0000000..Selects LP_FLEXCOMM0 interrupt
 *  0b0000001..Selects LP_FLEXCOMM1 interrupt
 *  0b0000010..Selects LP_FLEXCOMM2 interrupt
 *  0b0000011..Selects LP_FLEXCOMM3 interrupt
 *  0b0000100..Selects LP_FLEXCOMM4 interrupt
 *  0b0000101..Selects LP_FLEXCOMM5 interrupt
 *  0b0000110..Selects LP_FLEXCOMM6 interrupt
 *  0b0000111..Selects LP_FLEXCOMM7 interrupt
 *  0b0001000..Selects LP_FLEXCOMM8 interrupt
 *  0b0001001..Selects LP_FLEXCOMM9 interrupt
 *  0b0001010..Selects LP_FLEXCOMM10 interrupt
 *  0b0001011..Selects LP_FLEXCOMM11 interrupt
 *  0b0001100..Selects LP_FLEXCOMM12 interrupt
 *  0b0001101..Selects LP_FLEXCOMM13 interrupt
 *  0b0001110..Selects MU2_MUA interrupt for HiFi4 to CPU1
 *  0b0001111..Selects MU4_MUB interrupt for HiFi4 to CPU0
 *  0b0010000..Selects WWDT0 interrupt
 *  0b0010001..Selects WWDT1 interrupt
 *  0b0010010..Selects UTICK0 interrupt
 *  0b0010011..Selects LPSPI14 interrupt
 *  0b0010100..Selects MRT0 Ored interrupt
 *  0b0010101..Selects OSTIMER event timer for HiFi4 wakeup/interrupt
 *  0b0010110..Selects CTIMER0 interrupt
 *  0b0010111..Selects CTIMER1 interrupt
 *  0b0011000..Selects CTIMER2 interrupt
 *  0b0011001..Selects CTIMER3 interrupt
 *  0b0011010..Selects CTIMER4 interrupt
 *  0b0011011..Selects RTC0 alarm interrupt to computer domain
 *  0b0011100..Selects RTC_SS0 wakeup interrupt to compute domain
 *  0b0011101..Selects I3C0 interrupt
 *  0b0011110..Selects I3C1 interrupt
 *  0b0011111..Selects MICFIL interrupt for read data or error
 *  0b0100000..Selects MICFIL hardware voice activity detector interrupt or error interrupt
 *  0b0100001..Selects LCDIF interrupt
 *  0b0100010..Selects VGPU interrupt from graphics core (domain HCLK)
 *  0b0100011..Selects EZH-V interrupt
 *  0b0100100..Selects FLEXIO interrupt
 *  0b0100101..Selects LPSPI16 interrupt
 *  0b0100110..Selects eDMA0 channel 0 interrupt
 *  0b0100111..Selects eDMA0 channel 1 interrupt
 *  0b0101000..Selects eDMA0 channel 2 interrupt
 *  0b0101001..Selects eDMA0 channel 3 interrupt
 *  0b0101010..Selects eDMA0 channel 4 interrupt
 *  0b0101011..Selects eDMA0 channel 5 interrupt
 *  0b0101100..Selects eDMA0 channel 6 interrupt
 *  0b0101101..Selects eDMA0 channel 7 interrupt
 *  0b0101110..Selects eDMA0 channel 8 interrupt
 *  0b0101111..Selects eDMA0 channel 9 interrupt
 *  0b0110000..Selects eDMA0 channel 10 interrupt
 *  0b0110001..Selects eDMA0 channel 11 interrupt
 *  0b0110010..Selects eDMA0 channel 12 interrupt
 *  0b0110011..Selects eDMA0 channel 13 interrupt
 *  0b0110100..Selects eDMA0 channel 14 interrupt
 *  0b0110101..Selects eDMA0 channel 15 interrupt
 *  0b0110110..Selects eDMA1 channel 0 interrupt
 *  0b0110111..Selects eDMA1 channel 1 interrupt
 *  0b0111000..Selects eDMA1 channel 2 interrupt
 *  0b0111001..Selects eDMA1 channel 3 interrupt
 *  0b0111010..Selects eDMA1 channel 4 interrupt
 *  0b0111011..Selects eDMA1 channel 5 interrupt
 *  0b0111100..Selects eDMA1 channel 6 interrupt
 *  0b0111101..Selects eDMA1 channel 7 interrupt
 *  0b0111110..Selects eDMA1 channel 8 interrupt
 *  0b0111111..Selects eDMA1 channel 9 interrupt
 *  0b1000000..Selects eDMA1 channel 10 interrupt
 *  0b1000001..Selects eDMA1 channel 11 interrupt
 *  0b1000010..Selects eDMA1 channel 12 interrupt
 *  0b1000011..Selects eDMA1 channel 13 interrupt
 *  0b1000100..Selects eDMA1 channel 14 interrupt
 *  0b1000101..Selects eDMA1 channel 15 interrupt
 *  0b1000110..Selects GPIO0 channel 0 interrupt
 *  0b1000111..Selects GPIO0 channel 1 interrupt
 *  0b1001000..Selects GPIO1 channel 0 interrupt
 *  0b1001001..Selects GPIO1 channel 1 interrupt
 *  0b1001010..Selects GPIO2 channel 0 interrupt
 *  0b1001011..Selects GPIO2 channel 1 interrupt
 *  0b1001100..Selects GPIO3 channel 0 interrupt
 *  0b1001101..Selects GPIO3 channel 1 interrupt
 *  0b1001110..Selects GPIO4 channel 0 interrupt
 *  0b1001111..Selects GPIO4 channel 1 interrupt
 *  0b1010000..Selects GPIO5 channel 0 interrupt
 *  0b1010001..Selects GPIO5 channel 1 interrupt
 *  0b1010010..Selects GPIO6 channel 0 interrupt
 *  0b1010011..Selects GPIO6 channel 1 interrupt
 *  0b1010100..Selects GPIO7 channel 0 interrupt
 *  0b1010101..Selects GPIO7 channel 1 interrupt
 *  0b1010110..Selects PINT0 interrupt 0
 *  0b1010111..Selects PINT0 interrupt 1
 *  0b1011000..Selects PINT0 interrupt 2
 *  0b1011001..Selects PINT0 interrupt 3
 *  0b1011010..Selects PINT0 interrupt 4
 *  0b1011011..Selects PINT0 interrupt 5
 *  0b1011100..Selects PINT0 interrupt 6
 *  0b1011101..Selects PINT0 interrupt 7
 *  0b1011110..Selects SAI0 TX/RX interrupt
 *  0b1011111..Selects SAI1 TX/RX interrupt
 *  0b1100000..Selects SAI2 TX/RX interrupt
 *  0b1100010..Selects XSPI0 Ored interrupt and flash error interrupt.
 *  0b1100011..Selects XSPI1 Ored interrupt and flash error interrupt.
 *  0b1100100..Selects XSPI2 Ored interrupt and flash error interrupt.
 *  0b1100101..Selects JPGDECWRP Ored context 0-3 interrupt
 *  0b1100110..Selects PNGDEC interrupt
 *  0b1100111..Selects NPU interrupt
 *  0b1101000..Selects PMC0 interrupt
 *  *..
 */
#define INPUTMUX_HIFI4_INTERRUPT_TRIGIN(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HIFI4_INTERRUPT_TRIGIN_SHIFT)) & INPUTMUX_HIFI4_INTERRUPT_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_HIFI4_INTERRUPT */
#define INPUTMUX_HIFI4_INTERRUPT_COUNT           (27U)

/*! @name FLEXCOMM_TRIG_LP_FLEXCOMM_TRIG - LP_FLEXCOMM Input Connections */
/*! @{ */

#define INPUTMUX_FLEXCOMM_TRIG_LP_FLEXCOMM_TRIG_TRIGIN_MASK (0xFU)
#define INPUTMUX_FLEXCOMM_TRIG_LP_FLEXCOMM_TRIG_TRIGIN_SHIFT (0U)
/*! TRIGIN - LP_FLEXCOMM Input Trigger
 *  0b0000..Selects CTIMER_C_INP0
 *  0b0001..Selects CTIMER_C_INP1
 *  0b0010..Selects CTIMER_C_INP2
 *  0b0011..Selects CTIMER_C_INP3
 *  0b0100..Selects SCT0_OUT3
 *  0b0101..Selects SCT0_OUT6
 *  0b0110..Selects SCT0_OUT9
 *  0b0111..Selects CTIMER0_MAT3
 *  0b1000..Selects CTIMER1_MAT3
 *  0b1001..Selects CTIMER2_MAT3
 *  0b1010..Selects CTIMER3_MAT3
 *  0b1011..Selects CTIMER4_MAT3
 *  0b1100..Selects PINT0 boolean pattern-match output
 *  0b1101..Selects ACMP0 CMPO
 *  0b1110..Selects RTC_SS0 interrupt
 *  *..
 */
#define INPUTMUX_FLEXCOMM_TRIG_LP_FLEXCOMM_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM_TRIG_LP_FLEXCOMM_TRIG_TRIGIN_SHIFT)) & INPUTMUX_FLEXCOMM_TRIG_LP_FLEXCOMM_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_FLEXCOMM_TRIG_LP_FLEXCOMM_TRIG */
#define INPUTMUX_FLEXCOMM_TRIG_LP_FLEXCOMM_TRIG_COUNT (14U)

/*! @name CTIMER_CTIMER_CAP_CAP - CTIMER Input Connections */
/*! @{ */

#define INPUTMUX_CTIMER_CTIMER_CAP_CAP_CAPIN_MASK (0x1FU)
#define INPUTMUX_CTIMER_CTIMER_CAP_CAP_CAPIN_SHIFT (0U)
/*! CAPIN - CTIMER input capture
 *  0b00000..Selects CTIMER_C_INP0
 *  0b00001..Selects CTIMER_C_INP1
 *  0b00010..Selects CTIMER_C_INP2
 *  0b00011..Selects CTIMER_C_INP3
 *  0b00100..Selects CTIMER_C_INP4
 *  0b00101..Selects CTIMER_C_INP5
 *  0b00110..Selects CTIMER_C_INP6
 *  0b00111..Selects CTIMER_C_INP7
 *  0b01000..Selects CTIMER_C_INP8
 *  0b01001..Selects CTIMER_C_INP9
 *  0b01010..Selects CTIMER_C_INP10
 *  0b01011..Selects CTIMER_C_INP11
 *  0b01100..Selects CTIMER_C_INP12
 *  0b01101..Selects CTIMER_C_INP13
 *  0b01110..Selects CTIMER_C_INP14
 *  0b01111..Selects CTIMER_C_INP15
 *  0b10000..Selects SAI0_TX_SYNC
 *  0b10001..Selects SAI0_RX_SYNC
 *  0b10010..Selects SAI1_TX_SYNC
 *  0b10011..Selects SAI1_RX_SYNC
 *  0b10100..Selects SAI2_TX_SYNC
 *  0b10101..Selects SAI2_RX_SYNC
 *  0b10110..Selects USB0 start of frame
 *  0b10111..Selects USB1 start of frame
 *  0b11000..Selects ACMP0 CMPO
 *  0b11001..Selects ADC0 trigger completion flag 0
 *  0b11010..Selects ADC0 trigger completion flag 1
 *  0b11011..Selects ITRC TMPR_OUT[0]
 *  0b11100..Selects ITRC TMPR_OUT[1]
 *  *..
 */
#define INPUTMUX_CTIMER_CTIMER_CAP_CAP_CAPIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER_CTIMER_CAP_CAP_CAPIN_SHIFT)) & INPUTMUX_CTIMER_CTIMER_CAP_CAP_CAPIN_MASK)
/*! @} */

/* The count of INPUTMUX_CTIMER_CTIMER_CAP_CAP */
#define INPUTMUX_CTIMER_CTIMER_CAP_CAP_COUNT     (5U)

/* The count of INPUTMUX_CTIMER_CTIMER_CAP_CAP */
#define INPUTMUX_CTIMER_CTIMER_CAP_CAP_COUNT2    (4U)

/*! @name CTIMER_TRIG - CTIMER Input Connections */
/*! @{ */

#define INPUTMUX_CTIMER_TRIG_TRIGIN_MASK         (0x1FU)
#define INPUTMUX_CTIMER_TRIG_TRIGIN_SHIFT        (0U)
/*! TRIGIN - CTIMER Input Trigger
 *  0b00000..Selects CTIMER_C_INP0
 *  0b00001..Selects CTIMER_C_INP1
 *  0b00010..Selects CTIMER_C_INP2
 *  0b00011..Selects CTIMER_C_INP3
 *  0b00100..Selects CTIMER_C_INP4
 *  0b00101..Selects CTIMER_C_INP5
 *  0b00110..Selects CTIMER_C_INP6
 *  0b00111..Selects CTIMER_C_INP7
 *  0b01000..Selects CTIMER_C_INP8
 *  0b01001..Selects CTIMER_C_INP9
 *  0b01010..Selects CTIMER_C_INP10
 *  0b01011..Selects CTIMER_C_INP11
 *  0b01100..Selects CTIMER_C_INP12
 *  0b01101..Selects CTIMER_C_INP13
 *  0b01110..Selects CTIMER_C_INP14
 *  0b01111..Selects CTIMER_C_INP15
 *  0b10000..Selects SAI0_TX_SYNC
 *  0b10001..Selects SAI0_RX_SYNC
 *  0b10010..Selects SAI1_TX_SYNC
 *  0b10011..Selects SAI1_RX_SYNC
 *  0b10100..Selects SAI2_TX_SYNC
 *  0b10101..Selects SAI2_RX_SYNC
 *  0b10110..Selects USB0 start of frame
 *  0b10111..Selects USB1 start of frame
 *  0b11000..Selects ACMP0 CMPO
 *  0b11001..Selects ADC0 trigger completion flag 0
 *  0b11010..Selects ADC0 trigger completion flag 1
 *  0b11011..Selects ITRC TMPR_OUT[0]
 *  0b11100..Selects ITRC TMPR_OUT[1]
 *  *..
 */
#define INPUTMUX_CTIMER_TRIG_TRIGIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CTIMER_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_CTIMER_TRIG */
#define INPUTMUX_CTIMER_TRIG_COUNT               (5U)

/*! @name FREQ_MEASURE_FREQME_TRIG - FREQME Clock Selection */
/*! @{ */

#define INPUTMUX_FREQ_MEASURE_FREQME_TRIG_TRIGIN_MASK (0x1FU)
#define INPUTMUX_FREQ_MEASURE_FREQME_TRIG_TRIGIN_SHIFT (0U)
/*! TRIGIN - FREQME Input Clock
 *  0b00000..Selects main crystal oscillator
 *  0b00001..Selects FRO1_DIV8
 *  0b00010..Selects FRO1
 *  0b00011..Selects LPOSC
 *  0b00100..Selects OSC32KNP osc32k_out
 *  0b00110..Selects FRO0
 *  0b00111..Selects FRO2
 *  0b01000..Selects FREQME_GPIO_A_CLK
 *  0b01001..Selects FREQME_GPIO_B_CLK
 *  *..
 */
#define INPUTMUX_FREQ_MEASURE_FREQME_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQ_MEASURE_FREQME_TRIG_TRIGIN_SHIFT)) & INPUTMUX_FREQ_MEASURE_FREQME_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_FREQ_MEASURE_FREQME_TRIG */
#define INPUTMUX_FREQ_MEASURE_FREQME_TRIG_COUNT  (2U)

/*! @name EZH_TRIG_EZHV_TRIG - EZH-V Input Connections */
/*! @{ */

#define INPUTMUX_EZH_TRIG_EZHV_TRIG_TRIGIN_MASK  (0x7FU)
#define INPUTMUX_EZH_TRIG_EZHV_TRIG_TRIGIN_SHIFT (0U)
/*! TRIGIN - EZH-V Input Trigger
 *  0b0000000..Selects GPIO0 peripheral output channel 0 trigger
 *  0b0000001..Selects GPIO0 peripheral output channel 1 trigger
 *  0b0000010..Selects GPIO1 peripheral output channel 0 trigger
 *  0b0000011..Selects GPIO1 peripheral output channel 1 trigger
 *  0b0000100..Selects GPIO2 peripheral output channel 0 trigger
 *  0b0000101..Selects GPIO2 peripheral output channel 1 trigger
 *  0b0000110..Selects GPIO3 peripheral output channel 0 trigger
 *  0b0000111..Selects GPIO3 peripheral output channel 1 trigger
 *  0b0001000..Selects GPIO4 peripheral output channel 0 trigger
 *  0b0001001..Selects GPIO4 peripheral output channel 1 trigger
 *  0b0001010..Selects GPIO5 peripheral output channel 0 trigger
 *  0b0001011..Selects GPIO5 peripheral output channel 1 trigger
 *  0b0001100..Selects GPIO6 peripheral output channel 0 trigger
 *  0b0001101..Selects GPIO6 peripheral output channel 1 trigger
 *  0b0001110..Selects GPIO7 peripheral output channel 0 trigger
 *  0b0001111..Selects GPIO7 peripheral output channel 1 trigger
 *  0b0010000..Selects LP_FLEXCOMM0 interrupt
 *  0b0010001..Selects LP_FLEXCOMM1 interrupt
 *  0b0010010..Selects LP_FLEXCOMM2 interrupt
 *  0b0010011..Selects LP_FLEXCOMM3 interrupt
 *  0b0010100..Selects LP_FLEXCOMM4 interrupt
 *  0b0010101..Selects LP_FLEXCOMM5 interrupt
 *  0b0010110..Selects LP_FLEXCOMM6 interrupt
 *  0b0010111..Selects LP_FLEXCOMM7 interrupt
 *  0b0011000..Selects LPSPI14 interrupt
 *  0b0011001..Selects LPSPI16 interrupt
 *  0b0011010..Selects I3C0 interrupt
 *  0b0011011..Selects I3C1 interrupt
 *  0b0011100..Selects I3C2 interrupt
 *  0b0011101..Selects I3C3 interrupt
 *  0b0011110..Selects FLEXIO interrupt
 *  0b0011111..Selects GPIO0 interrupt
 *  0b0100000..Selects GPIO1 interrupt
 *  0b0100001..Selects GPIO2 interrupt
 *  0b0100010..Selects GPIO3 interrupt
 *  0b0100011..Selects GPIO4 interrupt
 *  0b0100100..Selects GPIO5 interrupt
 *  0b0100101..Selects GPIO6 interrupt
 *  0b0100110..Selects GPIO7 interrupt
 *  0b0100111..Selects GPIO8 interrupt
 *  0b0101000..Selects GPIO9 interrupt
 *  0b0101001..Selects GPIO10 interrupt
 *  0b0101010..Selects SCT0 interrupt
 *  0b0101011..Selects CTIMER0 interrupt
 *  0b0101100..Selects CTIMER1 interrupt
 *  0b0101101..Selects CTIMER2 interrupt
 *  0b0101110..Selects CTIMER3 interrupt
 *  0b0101111..Selects CTIMER4 interrupt
 *  0b0110000..Selects CTIMER5 interrupt
 *  0b0110001..Selects CTIMER6 interrupt
 *  0b0110010..Selects CTIMER7 interrupt
 *  0b0110011..Selects UTICK0 interrupt
 *  0b0110100..Selects MRT0 interrupt
 *  0b0110101..Selects RTC0 interrupt
 *  0b0110110..Selects OSTIMER event timer CPU0 wakeup/interrupt
 *  0b0110111..Selects WWDT0 interrupt
 *  0b0111000..Selects WWDT1 interrupt
 *  0b0111001..Selects ADC0 interrupt
 *  0b0111010..Selects ACMP0 interrupt
 *  0b0111011..Selects MICFIL interrupt
 *  0b0111100..Selects MICFIL HWVAD
 *  0b0111101..Selects uSDHC0 interrupt
 *  0b0111110..Selects uSDHC1 interrupt
 *  0b0111111..Selects USB0 interrupt
 *  0b1000000..Selects USB1 interrupt
 *  0b1000001..Selects LCDIF interrupt
 *  0b1000010..Selects VGPU interrupt
 *  0b1000011..Selects eDMA0 channel 0 interrupt
 *  0b1000100..Selects eDMA0 channel 1 interrupt
 *  0b1000101..Selects eDMA0 channel 2 interrupt
 *  0b1000110..Selects eDMA0 channel 3 interrupt
 *  0b1000111..Selects eDMA1 channel 0 interrupt
 *  0b1001000..Selects eDMA1 channel 1 interrupt
 *  0b1001001..Selects eDMA1 channel 2 interrupt
 *  0b1001010..Selects eDMA1 channel 3 interrupt
 *  0b1001011..Selects eDMA2 channel 0 interrupt
 *  0b1001100..Selects eDMA2 channel 1 interrupt
 *  0b1001101..Selects eDMA2 channel 2 interrupt
 *  0b1001110..Selects eDMA2 channel 3 interrupt
 *  0b1001111..Selects eDMA3 channel 0 interrupt
 *  0b1010000..Selects eDMA3 channel 1 interrupt
 *  0b1010001..Selects eDMA3 channel 2 interrupt
 *  0b1010010..Selects eDMA3 channel 3 interrupt
 *  0b1010011..Selects HiFi1 TIE_EXPSTATE_1
 *  0b1010100..Selects HiFi4 TIE_EXPSTATE_1
 *  0b1010101..Selects SCT0_OUT8
 *  0b1010110..Selects SCT0_OUT9
 *  0b1010111..Selects CTIMER4_MAT3
 *  0b1011000..Selects CTIMER4_MAT2
 *  0b1011001..Selects CTIMER3_MAT3
 *  0b1011010..Selects CTIMER3_MAT2
 *  0b1011011..Selects CPU0 TXEV
 *  0b1011100..Selects PINT0 boolean pattern-match output
 *  0b1011101..Selects MIPI_DSI_HOST interrupt
 *  0b1011110..Selects USB0 start of frame
 *  0b1011111..Selects USB1 start of frame
 *  0b1100000..Selects ITRC TMPR_OUT[0]
 *  0b1100001..Selects ITRC TMPR_OUT[1]
 *  *..
 */
#define INPUTMUX_EZH_TRIG_EZHV_TRIG_TRIGIN(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EZH_TRIG_EZHV_TRIG_TRIGIN_SHIFT)) & INPUTMUX_EZH_TRIG_EZHV_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_EZH_TRIG_EZHV_TRIG */
#define INPUTMUX_EZH_TRIG_EZHV_TRIG_COUNT        (8U)

/*! @name FLEXIO_TRIG - FLEXIO Input Connections */
/*! @{ */

#define INPUTMUX_FLEXIO_TRIG_TRIGIN_MASK         (0x3FU)
#define INPUTMUX_FLEXIO_TRIG_TRIGIN_SHIFT        (0U)
/*! TRIGIN - FLEXIO Input Trigger
 *  0b000000..Selects CTIMER_C_INP0
 *  0b000001..Selects CTIMER_C_INP1
 *  0b000010..Selects CTIMER_C_INP2
 *  0b000011..Selects CTIMER_C_INP3
 *  0b000100..Selects SCT0_OUT6
 *  0b000101..Selects SCT0_OUT7
 *  0b000110..Selects SCT0_OUT8
 *  0b000111..Selects CTIMER0_MAT3
 *  0b001000..Selects CTIMER1_MAT3
 *  0b001001..Selects CTIMER2_MAT3
 *  0b001010..Selects CTIMER3_MAT3
 *  0b001011..Selects CTIMER4_MAT3
 *  0b001100..Selects PINT0 boolean pattern-match output
 *  0b001101..Selects ACMP0 CMPO
 *  0b001110..Selects EZH-V trigger out channel 0
 *  0b001111..Selects RTC_SS0 interrupt
 *  0b010000..Selects GPIO0 peripheral output channel 0 trigger
 *  0b010001..Selects GPIO0 peripheral output channel 1 trigger
 *  0b010010..Selects GPIO1 peripheral output channel 0 trigger
 *  0b010011..Selects GPIO1 peripheral output channel 1 trigger
 *  0b010100..Selects GPIO2 peripheral output channel 0 trigger
 *  0b010101..Selects GPIO2 peripheral output channel 1 trigger
 *  0b010110..Selects GPIO3 peripheral output channel 0 trigger
 *  0b010111..Selects GPIO3 peripheral output channel 1 trigger
 *  0b011000..Selects GPIO4 peripheral output channel 0 trigger
 *  0b011001..Selects GPIO4 peripheral output channel 1 trigger
 *  0b011010..Selects GPIO5 peripheral output channel 0 trigger
 *  0b011011..Selects GPIO5 peripheral output channel 1 trigger
 *  0b011100..Selects GPIO6 peripheral output channel 0 trigger
 *  0b011101..Selects GPIO6 peripheral output channel 1 trigger
 *  0b011110..Selects GPIO7 peripheral output channel 0 trigger
 *  0b011111..Selects GPIO7 peripheral output channel 1 trigger
 *  0b100000..Selects GPIO8 peripheral output channel 0 trigger
 *  0b100001..Selects GPIO8 peripheral output channel 1 trigger
 *  0b100010..Selects GPIO9 peripheral output channel 0 trigger
 *  0b100011..Selects GPIO9 peripheral output channel 1 trigger
 *  0b100100..Selects GPIO10 peripheral output channel 0 trigger
 *  0b100101..Selects GPIO10 peripheral output channel 1 trigger
 *  0b100110..Selects ITRC TMPR_OUT[0]
 *  0b100111..Selects ITRC TMPR_OUT[1]
 *  *..
 */
#define INPUTMUX_FLEXIO_TRIG_TRIGIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG_TRIGIN_SHIFT)) & INPUTMUX_FLEXIO_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_FLEXIO_TRIG */
#define INPUTMUX_FLEXIO_TRIG_COUNT               (4U)


/*!
 * @}
 */ /* end of group INPUTMUX_Register_Masks */


/* INPUTMUX - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral INPUTMUX0 base address */
  #define INPUTMUX0_BASE                           (0x50026000u)
  /** Peripheral INPUTMUX0 base address */
  #define INPUTMUX0_BASE_NS                        (0x40026000u)
  /** Peripheral INPUTMUX0 base pointer */
  #define INPUTMUX0                                ((INPUTMUX_Type *)INPUTMUX0_BASE)
  /** Peripheral INPUTMUX0 base pointer */
  #define INPUTMUX0_NS                             ((INPUTMUX_Type *)INPUTMUX0_BASE_NS)
  /** Array initializer of INPUTMUX peripheral base addresses */
  #define INPUTMUX_BASE_ADDRS                      { INPUTMUX0_BASE }
  /** Array initializer of INPUTMUX peripheral base pointers */
  #define INPUTMUX_BASE_PTRS                       { INPUTMUX0 }
  /** Array initializer of INPUTMUX peripheral base addresses */
  #define INPUTMUX_BASE_ADDRS_NS                   { INPUTMUX0_BASE_NS }
  /** Array initializer of INPUTMUX peripheral base pointers */
  #define INPUTMUX_BASE_PTRS_NS                    { INPUTMUX0_NS }
#else
  /** Peripheral INPUTMUX0 base address */
  #define INPUTMUX0_BASE                           (0x40026000u)
  /** Peripheral INPUTMUX0 base pointer */
  #define INPUTMUX0                                ((INPUTMUX_Type *)INPUTMUX0_BASE)
  /** Array initializer of INPUTMUX peripheral base addresses */
  #define INPUTMUX_BASE_ADDRS                      { INPUTMUX0_BASE }
  /** Array initializer of INPUTMUX peripheral base pointers */
  #define INPUTMUX_BASE_PTRS                       { INPUTMUX0 }
#endif

/*!
 * @}
 */ /* end of group INPUTMUX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOPCTL0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOPCTL0_Peripheral_Access_Layer IOPCTL0 Peripheral Access Layer
 * @{
 */

/** IOPCTL0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t PIO[4][32];                        /**< IOPCTL Configuration, array offset: 0x0, array step: index*0x80, index2*0x4, valid indices: [0][0-31], [1][0-19], [2][0-15], [3][0-14] */
} IOPCTL0_Type;

/* ----------------------------------------------------------------------------
   -- IOPCTL0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOPCTL0_Register_Masks IOPCTL0 Register Masks
 * @{
 */

/*! @name PIO - IOPCTL Configuration */
/*! @{ */

#define IOPCTL0_PIO_FSEL_MASK                    (0xFU)
#define IOPCTL0_PIO_FSEL_SHIFT                   (0U)
/*! FSEL - Function Selector (Digital Function)
 *  0b0000..Function 0
 *  0b0001..Function 1
 *  0b0010..Function 2
 *  0b0011..Function 3
 *  0b0100..Function 4
 *  0b0101..Function 5
 *  0b0110..Function 6
 *  0b0111..Function 7
 *  *..
 */
#define IOPCTL0_PIO_FSEL(x)                      (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_FSEL_SHIFT)) & IOPCTL0_PIO_FSEL_MASK)

#define IOPCTL0_PIO_PUPDENA_MASK                 (0x10U)
#define IOPCTL0_PIO_PUPDENA_SHIFT                (4U)
/*! PUPDENA - Pullup / Pulldown Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define IOPCTL0_PIO_PUPDENA(x)                   (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_PUPDENA_SHIFT)) & IOPCTL0_PIO_PUPDENA_MASK)

#define IOPCTL0_PIO_PUPDSEL_MASK                 (0x20U)
#define IOPCTL0_PIO_PUPDSEL_SHIFT                (5U)
/*! PUPDSEL - Pullup or Pulldown Selector
 *  0b0..Enables the internal pull-down resistor.
 *  0b1..Enables the internal pull-up resistor.
 */
#define IOPCTL0_PIO_PUPDSEL(x)                   (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_PUPDSEL_SHIFT)) & IOPCTL0_PIO_PUPDSEL_MASK)

#define IOPCTL0_PIO_IBENA_MASK                   (0x40U)
#define IOPCTL0_PIO_IBENA_SHIFT                  (6U)
/*! IBENA - Input Buffer Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL0_PIO_IBENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_IBENA_SHIFT)) & IOPCTL0_PIO_IBENA_MASK)

#define IOPCTL0_PIO_SLEWRATE_MASK                (0x80U)
#define IOPCTL0_PIO_SLEWRATE_SHIFT               (7U)
/*! SLEWRATE - Slew Rate Control
 *  0b0..Disables, in standard mode.
 *  0b1..Enables, in slow mode.
 */
#define IOPCTL0_PIO_SLEWRATE(x)                  (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_SLEWRATE_SHIFT)) & IOPCTL0_PIO_SLEWRATE_MASK)

#define IOPCTL0_PIO_FULLDRIVE_MASK               (0x100U)
#define IOPCTL0_PIO_FULLDRIVE_SHIFT              (8U)
/*! FULLDRIVE - Drive Selector
 *  0b0..Normal output drive
 *  0b1..Full output drive, twice the drive of normal mode.
 */
#define IOPCTL0_PIO_FULLDRIVE(x)                 (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_FULLDRIVE_SHIFT)) & IOPCTL0_PIO_FULLDRIVE_MASK)

#define IOPCTL0_PIO_AMENA_MASK                   (0x200U)
#define IOPCTL0_PIO_AMENA_SHIFT                  (9U)
/*! AMENA - Analog Mux Enable
 *  0b0..Disables for digital pin function
 *  0b1..Enables for analog pin function
 */
#define IOPCTL0_PIO_AMENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_AMENA_SHIFT)) & IOPCTL0_PIO_AMENA_MASK)

#define IOPCTL0_PIO_ODENA_MASK                   (0x400U)
#define IOPCTL0_PIO_ODENA_SHIFT                  (10U)
/*! ODENA - Open-drain Mode Enable
 *  0b0..Disables for normal push-pull output
 *  0b1..Enables for simulated open-drain output (high drive disabled)
 */
#define IOPCTL0_PIO_ODENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_ODENA_SHIFT)) & IOPCTL0_PIO_ODENA_MASK)

#define IOPCTL0_PIO_IIENA_MASK                   (0x800U)
#define IOPCTL0_PIO_IIENA_SHIFT                  (11U)
/*! IIENA - Input Invert Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL0_PIO_IIENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_IIENA_SHIFT)) & IOPCTL0_PIO_IIENA_MASK)

#define IOPCTL0_PIO_DRIVE_MASK                   (0x3000U)
#define IOPCTL0_PIO_DRIVE_SHIFT                  (12U)
/*! DRIVE - Drive
 *  0b00..100 ohm
 *  0b01..66 ohm
 *  0b10..50 ohm
 *  0b11..33 ohm
 */
#define IOPCTL0_PIO_DRIVE(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL0_PIO_DRIVE_SHIFT)) & IOPCTL0_PIO_DRIVE_MASK)
/*! @} */

/* The count of IOPCTL0_PIO */
#define IOPCTL0_PIO_COUNT                        (4U)

/* The count of IOPCTL0_PIO */
#define IOPCTL0_PIO_COUNT2                       (32U)


/*!
 * @}
 */ /* end of group IOPCTL0_Register_Masks */


/* IOPCTL0 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral IOPCTL0 base address */
  #define IOPCTL0_BASE                             (0x50004000u)
  /** Peripheral IOPCTL0 base address */
  #define IOPCTL0_BASE_NS                          (0x40004000u)
  /** Peripheral IOPCTL0 base pointer */
  #define IOPCTL0                                  ((IOPCTL0_Type *)IOPCTL0_BASE)
  /** Peripheral IOPCTL0 base pointer */
  #define IOPCTL0_NS                               ((IOPCTL0_Type *)IOPCTL0_BASE_NS)
  /** Array initializer of IOPCTL0 peripheral base addresses */
  #define IOPCTL0_BASE_ADDRS                       { IOPCTL0_BASE }
  /** Array initializer of IOPCTL0 peripheral base pointers */
  #define IOPCTL0_BASE_PTRS                        { IOPCTL0 }
  /** Array initializer of IOPCTL0 peripheral base addresses */
  #define IOPCTL0_BASE_ADDRS_NS                    { IOPCTL0_BASE_NS }
  /** Array initializer of IOPCTL0 peripheral base pointers */
  #define IOPCTL0_BASE_PTRS_NS                     { IOPCTL0_NS }
#else
  /** Peripheral IOPCTL0 base address */
  #define IOPCTL0_BASE                             (0x40004000u)
  /** Peripheral IOPCTL0 base pointer */
  #define IOPCTL0                                  ((IOPCTL0_Type *)IOPCTL0_BASE)
  /** Array initializer of IOPCTL0 peripheral base addresses */
  #define IOPCTL0_BASE_ADDRS                       { IOPCTL0_BASE }
  /** Array initializer of IOPCTL0 peripheral base pointers */
  #define IOPCTL0_BASE_PTRS                        { IOPCTL0 }
#endif

/*!
 * @}
 */ /* end of group IOPCTL0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOPCTL1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOPCTL1_Peripheral_Access_Layer IOPCTL1 Peripheral Access Layer
 * @{
 */

/** IOPCTL1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t PIO[3][32];                        /**< IOPCTL Configuration, array offset: 0x0, array step: index*0x80, index2*0x4, valid indices: [0][0-31], [1][0-2], [2][0-17] */
  __IO uint32_t PMIC_I2C_SDA;                      /**< PMIC_I2C_SDA, offset: 0x180 */
  __IO uint32_t PMIC_I2C_SCL;                      /**< PMIC_I2C_SCL, offset: 0x184 */
} IOPCTL1_Type;

/* ----------------------------------------------------------------------------
   -- IOPCTL1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOPCTL1_Register_Masks IOPCTL1 Register Masks
 * @{
 */

/*! @name PIO - IOPCTL Configuration */
/*! @{ */

#define IOPCTL1_PIO_FSEL_MASK                    (0xFU)
#define IOPCTL1_PIO_FSEL_SHIFT                   (0U)
/*! FSEL - Function Selector (Digital Function)
 *  0b0000..Function 0
 *  0b0001..Function 1
 *  0b0010..Function 2
 *  0b0011..Function 3
 *  0b0100..Function 4
 *  0b0101..Function 5
 *  0b0110..Function 6
 *  0b0111..Function 7
 */
#define IOPCTL1_PIO_FSEL(x)                      (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_FSEL_SHIFT)) & IOPCTL1_PIO_FSEL_MASK)

#define IOPCTL1_PIO_PUPDENA_MASK                 (0x10U)
#define IOPCTL1_PIO_PUPDENA_SHIFT                (4U)
/*! PUPDENA - Pullup / Pulldown Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define IOPCTL1_PIO_PUPDENA(x)                   (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_PUPDENA_SHIFT)) & IOPCTL1_PIO_PUPDENA_MASK)

#define IOPCTL1_PIO_PUPDSEL_MASK                 (0x20U)
#define IOPCTL1_PIO_PUPDSEL_SHIFT                (5U)
/*! PUPDSEL - Pullup or Pulldown Selector
 *  0b0..Enables the internal pull-down resistor.
 *  0b1..Enables the internal pull-up resistor.
 */
#define IOPCTL1_PIO_PUPDSEL(x)                   (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_PUPDSEL_SHIFT)) & IOPCTL1_PIO_PUPDSEL_MASK)

#define IOPCTL1_PIO_IBENA_MASK                   (0x40U)
#define IOPCTL1_PIO_IBENA_SHIFT                  (6U)
/*! IBENA - Input Buffer Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL1_PIO_IBENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_IBENA_SHIFT)) & IOPCTL1_PIO_IBENA_MASK)

#define IOPCTL1_PIO_SLEWRATE_MASK                (0x80U)
#define IOPCTL1_PIO_SLEWRATE_SHIFT               (7U)
/*! SLEWRATE - Slew Rate Control
 *  0b0..Disables. Standard mode.
 *  0b1..Enables. Slow mode.
 */
#define IOPCTL1_PIO_SLEWRATE(x)                  (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_SLEWRATE_SHIFT)) & IOPCTL1_PIO_SLEWRATE_MASK)

#define IOPCTL1_PIO_FULLDRIVE_MASK               (0x100U)
#define IOPCTL1_PIO_FULLDRIVE_SHIFT              (8U)
/*! FULLDRIVE - Drive Selector
 *  0b0..Normal output drive
 *  0b1..Full output drive, twice the drive of normal mode.
 */
#define IOPCTL1_PIO_FULLDRIVE(x)                 (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_FULLDRIVE_SHIFT)) & IOPCTL1_PIO_FULLDRIVE_MASK)

#define IOPCTL1_PIO_AMENA_MASK                   (0x200U)
#define IOPCTL1_PIO_AMENA_SHIFT                  (9U)
/*! AMENA - Analog Mux Enable
 *  0b0..Disables for digital pin function
 *  0b1..Enables for analog pin function
 */
#define IOPCTL1_PIO_AMENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_AMENA_SHIFT)) & IOPCTL1_PIO_AMENA_MASK)

#define IOPCTL1_PIO_ODENA_MASK                   (0x400U)
#define IOPCTL1_PIO_ODENA_SHIFT                  (10U)
/*! ODENA - Open-drain Mode Enable
 *  0b0..Disables for Normal push-pull output
 *  0b1..Enables for open-drain output (high drive is disabled)
 */
#define IOPCTL1_PIO_ODENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_ODENA_SHIFT)) & IOPCTL1_PIO_ODENA_MASK)

#define IOPCTL1_PIO_IIENA_MASK                   (0x800U)
#define IOPCTL1_PIO_IIENA_SHIFT                  (11U)
/*! IIENA - Input Invert Enable
 *  0b0..Disables. Input function is not inverted
 *  0b1..Enables, input is function inverted
 */
#define IOPCTL1_PIO_IIENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PIO_IIENA_SHIFT)) & IOPCTL1_PIO_IIENA_MASK)
/*! @} */

/* The count of IOPCTL1_PIO */
#define IOPCTL1_PIO_COUNT                        (3U)

/* The count of IOPCTL1_PIO */
#define IOPCTL1_PIO_COUNT2                       (32U)

/*! @name PMIC_I2C_SDA - PMIC_I2C_SDA */
/*! @{ */

#define IOPCTL1_PMIC_I2C_SDA_PUPDENA_MASK        (0x10U)
#define IOPCTL1_PMIC_I2C_SDA_PUPDENA_SHIFT       (4U)
/*! PUPDENA - Pullup / Pulldown Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL1_PMIC_I2C_SDA_PUPDENA(x)          (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SDA_PUPDENA_SHIFT)) & IOPCTL1_PMIC_I2C_SDA_PUPDENA_MASK)

#define IOPCTL1_PMIC_I2C_SDA_PUPDSEL_MASK        (0x20U)
#define IOPCTL1_PMIC_I2C_SDA_PUPDSEL_SHIFT       (5U)
/*! PUPDSEL - Pullup or Pulldown Selector
 *  0b0..Enables the internal pull-down resistor.
 *  0b1..Enables the internal pull-up resistor.
 */
#define IOPCTL1_PMIC_I2C_SDA_PUPDSEL(x)          (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SDA_PUPDSEL_SHIFT)) & IOPCTL1_PMIC_I2C_SDA_PUPDSEL_MASK)

#define IOPCTL1_PMIC_I2C_SDA_IBENA_MASK          (0x40U)
#define IOPCTL1_PMIC_I2C_SDA_IBENA_SHIFT         (6U)
/*! IBENA - Input Buffer Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL1_PMIC_I2C_SDA_IBENA(x)            (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SDA_IBENA_SHIFT)) & IOPCTL1_PMIC_I2C_SDA_IBENA_MASK)

#define IOPCTL1_PMIC_I2C_SDA_SLEWRATE_MASK       (0x80U)
#define IOPCTL1_PMIC_I2C_SDA_SLEWRATE_SHIFT      (7U)
/*! SLEWRATE - Slew Rate Control
 *  0b0..Disables, in standard mode.
 *  0b1..Enables, in slow mode.
 */
#define IOPCTL1_PMIC_I2C_SDA_SLEWRATE(x)         (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SDA_SLEWRATE_SHIFT)) & IOPCTL1_PMIC_I2C_SDA_SLEWRATE_MASK)

#define IOPCTL1_PMIC_I2C_SDA_FULLDRIVE_MASK      (0x100U)
#define IOPCTL1_PMIC_I2C_SDA_FULLDRIVE_SHIFT     (8U)
/*! FULLDRIVE - Drive Selector
 *  0b0..Normal output drive
 *  0b1..Full output drive, twice the drive of normal mode.
 */
#define IOPCTL1_PMIC_I2C_SDA_FULLDRIVE(x)        (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SDA_FULLDRIVE_SHIFT)) & IOPCTL1_PMIC_I2C_SDA_FULLDRIVE_MASK)

#define IOPCTL1_PMIC_I2C_SDA_AMENA_MASK          (0x200U)
#define IOPCTL1_PMIC_I2C_SDA_AMENA_SHIFT         (9U)
/*! AMENA - Analog Mux Enable
 *  0b0..Disables for digital pin function
 *  0b1..Enables for analog pin function
 */
#define IOPCTL1_PMIC_I2C_SDA_AMENA(x)            (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SDA_AMENA_SHIFT)) & IOPCTL1_PMIC_I2C_SDA_AMENA_MASK)

#define IOPCTL1_PMIC_I2C_SDA_ODENA_MASK          (0x400U)
#define IOPCTL1_PMIC_I2C_SDA_ODENA_SHIFT         (10U)
/*! ODENA - Open-drain Mode Enable
 *  0b0..Disables for normal push-pull output
 *  0b1..Enables for simulated open-drain output (high drive disabled)
 */
#define IOPCTL1_PMIC_I2C_SDA_ODENA(x)            (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SDA_ODENA_SHIFT)) & IOPCTL1_PMIC_I2C_SDA_ODENA_MASK)

#define IOPCTL1_PMIC_I2C_SDA_IIENA_MASK          (0x800U)
#define IOPCTL1_PMIC_I2C_SDA_IIENA_SHIFT         (11U)
/*! IIENA - Input Invert Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL1_PMIC_I2C_SDA_IIENA(x)            (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SDA_IIENA_SHIFT)) & IOPCTL1_PMIC_I2C_SDA_IIENA_MASK)
/*! @} */

/*! @name PMIC_I2C_SCL - PMIC_I2C_SCL */
/*! @{ */

#define IOPCTL1_PMIC_I2C_SCL_PUPDENA_MASK        (0x10U)
#define IOPCTL1_PMIC_I2C_SCL_PUPDENA_SHIFT       (4U)
/*! PUPDENA - Pullup / Pulldown Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL1_PMIC_I2C_SCL_PUPDENA(x)          (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SCL_PUPDENA_SHIFT)) & IOPCTL1_PMIC_I2C_SCL_PUPDENA_MASK)

#define IOPCTL1_PMIC_I2C_SCL_PUPDSEL_MASK        (0x20U)
#define IOPCTL1_PMIC_I2C_SCL_PUPDSEL_SHIFT       (5U)
/*! PUPDSEL - Pullup or Pulldown Selector
 *  0b0..Enables the internal pull-down resistor.
 *  0b1..Enables the internal pull-up resistor.
 */
#define IOPCTL1_PMIC_I2C_SCL_PUPDSEL(x)          (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SCL_PUPDSEL_SHIFT)) & IOPCTL1_PMIC_I2C_SCL_PUPDSEL_MASK)

#define IOPCTL1_PMIC_I2C_SCL_IBENA_MASK          (0x40U)
#define IOPCTL1_PMIC_I2C_SCL_IBENA_SHIFT         (6U)
/*! IBENA - Input Buffer Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL1_PMIC_I2C_SCL_IBENA(x)            (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SCL_IBENA_SHIFT)) & IOPCTL1_PMIC_I2C_SCL_IBENA_MASK)

#define IOPCTL1_PMIC_I2C_SCL_SLEWRATE_MASK       (0x80U)
#define IOPCTL1_PMIC_I2C_SCL_SLEWRATE_SHIFT      (7U)
/*! SLEWRATE - Slew Rate Control
 *  0b0..Disables. Standard mode.
 *  0b1..Enables. Slow mode.
 */
#define IOPCTL1_PMIC_I2C_SCL_SLEWRATE(x)         (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SCL_SLEWRATE_SHIFT)) & IOPCTL1_PMIC_I2C_SCL_SLEWRATE_MASK)

#define IOPCTL1_PMIC_I2C_SCL_FULLDRIVE_MASK      (0x100U)
#define IOPCTL1_PMIC_I2C_SCL_FULLDRIVE_SHIFT     (8U)
/*! FULLDRIVE - Drive Selector
 *  0b0..Normal output drive
 *  0b1..Full output drive, twice the drive of normal mode.
 */
#define IOPCTL1_PMIC_I2C_SCL_FULLDRIVE(x)        (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SCL_FULLDRIVE_SHIFT)) & IOPCTL1_PMIC_I2C_SCL_FULLDRIVE_MASK)

#define IOPCTL1_PMIC_I2C_SCL_AMENA_MASK          (0x200U)
#define IOPCTL1_PMIC_I2C_SCL_AMENA_SHIFT         (9U)
/*! AMENA - Analog Mux Enable
 *  0b0..Disables for digital pin function
 *  0b1..Enables for analog pin function
 */
#define IOPCTL1_PMIC_I2C_SCL_AMENA(x)            (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SCL_AMENA_SHIFT)) & IOPCTL1_PMIC_I2C_SCL_AMENA_MASK)

#define IOPCTL1_PMIC_I2C_SCL_ODENA_MASK          (0x400U)
#define IOPCTL1_PMIC_I2C_SCL_ODENA_SHIFT         (10U)
/*! ODENA - Open-drain Mode Enable
 *  0b0..Disables for normal push-pull output
 *  0b1..Enables for simulated open-drain output (high drive disabled)
 */
#define IOPCTL1_PMIC_I2C_SCL_ODENA(x)            (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SCL_ODENA_SHIFT)) & IOPCTL1_PMIC_I2C_SCL_ODENA_MASK)

#define IOPCTL1_PMIC_I2C_SCL_IIENA_MASK          (0x800U)
#define IOPCTL1_PMIC_I2C_SCL_IIENA_SHIFT         (11U)
/*! IIENA - Input Invert Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL1_PMIC_I2C_SCL_IIENA(x)            (((uint32_t)(((uint32_t)(x)) << IOPCTL1_PMIC_I2C_SCL_IIENA_SHIFT)) & IOPCTL1_PMIC_I2C_SCL_IIENA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IOPCTL1_Register_Masks */


/* IOPCTL1 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral IOPCTL1 base address */
  #define IOPCTL1_BASE                             (0x50064000u)
  /** Peripheral IOPCTL1 base address */
  #define IOPCTL1_BASE_NS                          (0x40064000u)
  /** Peripheral IOPCTL1 base pointer */
  #define IOPCTL1                                  ((IOPCTL1_Type *)IOPCTL1_BASE)
  /** Peripheral IOPCTL1 base pointer */
  #define IOPCTL1_NS                               ((IOPCTL1_Type *)IOPCTL1_BASE_NS)
  /** Array initializer of IOPCTL1 peripheral base addresses */
  #define IOPCTL1_BASE_ADDRS                       { IOPCTL1_BASE }
  /** Array initializer of IOPCTL1 peripheral base pointers */
  #define IOPCTL1_BASE_PTRS                        { IOPCTL1 }
  /** Array initializer of IOPCTL1 peripheral base addresses */
  #define IOPCTL1_BASE_ADDRS_NS                    { IOPCTL1_BASE_NS }
  /** Array initializer of IOPCTL1 peripheral base pointers */
  #define IOPCTL1_BASE_PTRS_NS                     { IOPCTL1_NS }
#else
  /** Peripheral IOPCTL1 base address */
  #define IOPCTL1_BASE                             (0x40064000u)
  /** Peripheral IOPCTL1 base pointer */
  #define IOPCTL1                                  ((IOPCTL1_Type *)IOPCTL1_BASE)
  /** Array initializer of IOPCTL1 peripheral base addresses */
  #define IOPCTL1_BASE_ADDRS                       { IOPCTL1_BASE }
  /** Array initializer of IOPCTL1 peripheral base pointers */
  #define IOPCTL1_BASE_PTRS                        { IOPCTL1 }
#endif

/*!
 * @}
 */ /* end of group IOPCTL1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOPCTL2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOPCTL2_Peripheral_Access_Layer IOPCTL2 Peripheral Access Layer
 * @{
 */

/** IOPCTL2 - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x80 */
    __IO uint32_t PIO[26];                           /**< IOPCTL Configuration, array offset: 0x0, array step: index*0x80, index2*0x4, valid indices: [0][0-20], [1][0-20], [2][0-12], [3][0-25] */
         uint8_t RESERVED_0[24];
  } PIO[4];
} IOPCTL2_Type;

/* ----------------------------------------------------------------------------
   -- IOPCTL2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOPCTL2_Register_Masks IOPCTL2 Register Masks
 * @{
 */

/*! @name PIO - IOPCTL Configuration */
/*! @{ */

#define IOPCTL2_PIO_FSEL_MASK                    (0xFU)
#define IOPCTL2_PIO_FSEL_SHIFT                   (0U)
/*! FSEL - Function Selector (Digital Function)
 *  0b0000..Function 0
 *  0b0001..Function 1
 *  0b0010..Function 2
 *  0b0011..Function 3
 *  0b0100..Function 4
 *  0b0101..Function 5
 *  0b0110..Function 6
 *  0b0111..Function 7
 *  *..
 */
#define IOPCTL2_PIO_FSEL(x)                      (((uint32_t)(((uint32_t)(x)) << IOPCTL2_PIO_FSEL_SHIFT)) & IOPCTL2_PIO_FSEL_MASK)

#define IOPCTL2_PIO_PUPDENA_MASK                 (0x10U)
#define IOPCTL2_PIO_PUPDENA_SHIFT                (4U)
/*! PUPDENA - Pullup / Pulldown Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define IOPCTL2_PIO_PUPDENA(x)                   (((uint32_t)(((uint32_t)(x)) << IOPCTL2_PIO_PUPDENA_SHIFT)) & IOPCTL2_PIO_PUPDENA_MASK)

#define IOPCTL2_PIO_PUPDSEL_MASK                 (0x20U)
#define IOPCTL2_PIO_PUPDSEL_SHIFT                (5U)
/*! PUPDSEL - Pullup or Pulldown Selector
 *  0b0..Enables the internal pull-down resistor.
 *  0b1..Enables the internal pull-up resistor.
 */
#define IOPCTL2_PIO_PUPDSEL(x)                   (((uint32_t)(((uint32_t)(x)) << IOPCTL2_PIO_PUPDSEL_SHIFT)) & IOPCTL2_PIO_PUPDSEL_MASK)

#define IOPCTL2_PIO_IBENA_MASK                   (0x40U)
#define IOPCTL2_PIO_IBENA_SHIFT                  (6U)
/*! IBENA - Input Buffer Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL2_PIO_IBENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL2_PIO_IBENA_SHIFT)) & IOPCTL2_PIO_IBENA_MASK)

#define IOPCTL2_PIO_ODENA_MASK                   (0x400U)
#define IOPCTL2_PIO_ODENA_SHIFT                  (10U)
/*! ODENA - Open-drain Mode Enable
 *  0b0..Disables for normal push-pull output
 *  0b1..Enables for simulated open-drain output (high drive disabled)
 */
#define IOPCTL2_PIO_ODENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL2_PIO_ODENA_SHIFT)) & IOPCTL2_PIO_ODENA_MASK)

#define IOPCTL2_PIO_IIENA_MASK                   (0x800U)
#define IOPCTL2_PIO_IIENA_SHIFT                  (11U)
/*! IIENA - Input Invert Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define IOPCTL2_PIO_IIENA(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL2_PIO_IIENA_SHIFT)) & IOPCTL2_PIO_IIENA_MASK)

#define IOPCTL2_PIO_DRIVE_MASK                   (0x3000U)
#define IOPCTL2_PIO_DRIVE_SHIFT                  (12U)
/*! DRIVE - Drive
 *  0b00..100 ohm
 *  0b01..66 ohm
 *  0b10..50 ohm
 *  0b11..33 ohm
 */
#define IOPCTL2_PIO_DRIVE(x)                     (((uint32_t)(((uint32_t)(x)) << IOPCTL2_PIO_DRIVE_SHIFT)) & IOPCTL2_PIO_DRIVE_MASK)
/*! @} */

/* The count of IOPCTL2_PIO */
#define IOPCTL2_PIO_COUNT                        (4U)

/* The count of IOPCTL2_PIO */
#define IOPCTL2_PIO_COUNT2                       (26U)


/*!
 * @}
 */ /* end of group IOPCTL2_Register_Masks */


/* IOPCTL2 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral IOPCTL2 base address */
  #define IOPCTL2_BASE                             (0x500A5000u)
  /** Peripheral IOPCTL2 base address */
  #define IOPCTL2_BASE_NS                          (0x400A5000u)
  /** Peripheral IOPCTL2 base pointer */
  #define IOPCTL2                                  ((IOPCTL2_Type *)IOPCTL2_BASE)
  /** Peripheral IOPCTL2 base pointer */
  #define IOPCTL2_NS                               ((IOPCTL2_Type *)IOPCTL2_BASE_NS)
  /** Array initializer of IOPCTL2 peripheral base addresses */
  #define IOPCTL2_BASE_ADDRS                       { IOPCTL2_BASE }
  /** Array initializer of IOPCTL2 peripheral base pointers */
  #define IOPCTL2_BASE_PTRS                        { IOPCTL2 }
  /** Array initializer of IOPCTL2 peripheral base addresses */
  #define IOPCTL2_BASE_ADDRS_NS                    { IOPCTL2_BASE_NS }
  /** Array initializer of IOPCTL2 peripheral base pointers */
  #define IOPCTL2_BASE_PTRS_NS                     { IOPCTL2_NS }
#else
  /** Peripheral IOPCTL2 base address */
  #define IOPCTL2_BASE                             (0x400A5000u)
  /** Peripheral IOPCTL2 base pointer */
  #define IOPCTL2                                  ((IOPCTL2_Type *)IOPCTL2_BASE)
  /** Array initializer of IOPCTL2 peripheral base addresses */
  #define IOPCTL2_BASE_ADDRS                       { IOPCTL2_BASE }
  /** Array initializer of IOPCTL2 peripheral base pointers */
  #define IOPCTL2_BASE_PTRS                        { IOPCTL2 }
#endif

/*!
 * @}
 */ /* end of group IOPCTL2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ITRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer
 * @{
 */

/** ITRC - Register Layout Typedef */
typedef struct {
  __IO uint32_t STATUS;                            /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */
  __IO uint32_t STATUS1;                           /**< ITRC IN16 to IN47 Status, offset: 0x4 */
  __IO uint32_t OUT_SEL[8][2];                     /**< Trigger Source IN0 to IN15 selector, array offset: 0x8, array step: index*0x8, index2*0x4 */
  __IO uint32_t OUT_SEL_1[8][2];                   /**< Trigger Source IN16 to IN31 selector, array offset: 0x48, array step: index*0x8, index2*0x4 */
  __IO uint32_t OUT_SEL_2[8][2];                   /**< Trigger source IN32 to IN47 selector, array offset: 0x88, array step: index*0x8, index2*0x4 */
       uint8_t RESERVED_0[40];
  __O  uint32_t SW_EVENT0;                         /**< Software event 0, offset: 0xF0 */
  __O  uint32_t SW_EVENT1;                         /**< Software event 1, offset: 0xF4 */
} ITRC_Type;

/* ----------------------------------------------------------------------------
   -- ITRC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ITRC_Register_Masks ITRC Register Masks
 * @{
 */

/*! @name STATUS - ITRC outputs and IN0 to IN15 Status */
/*! @{ */

#define ITRC_STATUS_IN0_STATUS_MASK              (0x1U)
#define ITRC_STATUS_IN0_STATUS_SHIFT             (0U)
/*! IN0_STATUS - Digital glitch detector 0 or 1 event occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN0_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK)

#define ITRC_STATUS_IN1_STATUS_MASK              (0x2U)
#define ITRC_STATUS_IN1_STATUS_SHIFT             (1U)
/*! IN1_STATUS - Digital glitch detector 2 or 3 event occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN1_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK)

#define ITRC_STATUS_IN4_STATUS_MASK              (0x10U)
#define ITRC_STATUS_IN4_STATUS_SHIFT             (4U)
/*! IN4_STATUS - Code watchdog 0 detected an code execution anomaly.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN4_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK)

#define ITRC_STATUS_IN5_STATUS_MASK              (0x20U)
#define ITRC_STATUS_IN5_STATUS_SHIFT             (5U)
/*! IN5_STATUS - Code watchdog 1 detected an code execution anomaly..
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN5_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK)

#define ITRC_STATUS_IN6_STATUS_MASK              (0x40U)
#define ITRC_STATUS_IN6_STATUS_SHIFT             (6U)
/*! IN6_STATUS - Code watchdog 2 detected an code execution anomaly.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN6_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK)

#define ITRC_STATUS_IN7_STATUS_MASK              (0x80U)
#define ITRC_STATUS_IN7_STATUS_SHIFT             (7U)
/*! IN7_STATUS - Code watchdog 3 detected an code execution anomaly.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN7_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK)

#define ITRC_STATUS_IN8_STATUS_MASK              (0x100U)
#define ITRC_STATUS_IN8_STATUS_SHIFT             (8U)
/*! IN8_STATUS - Code watchdog 4 detected an code execution anomaly.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN8_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK)

#define ITRC_STATUS_IN9_STATUS_MASK              (0x200U)
#define ITRC_STATUS_IN9_STATUS_SHIFT             (9U)
/*! IN9_STATUS - Watchdog timer 0 event occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN9_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN9_STATUS_SHIFT)) & ITRC_STATUS_IN9_STATUS_MASK)

#define ITRC_STATUS_IN10_STATUS_MASK             (0x400U)
#define ITRC_STATUS_IN10_STATUS_SHIFT            (10U)
/*! IN10_STATUS - Watchdog timer 1 event occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN10_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK)

#define ITRC_STATUS_IN11_STATUS_MASK             (0x800U)
#define ITRC_STATUS_IN11_STATUS_SHIFT            (11U)
/*! IN11_STATUS - Watchdog timer 2 event occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN11_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN11_STATUS_SHIFT)) & ITRC_STATUS_IN11_STATUS_MASK)

#define ITRC_STATUS_IN12_STATUS_MASK             (0x1000U)
#define ITRC_STATUS_IN12_STATUS_SHIFT            (12U)
/*! IN12_STATUS - Watchdog timer 3 event occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN12_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN12_STATUS_SHIFT)) & ITRC_STATUS_IN12_STATUS_MASK)

#define ITRC_STATUS_IN13_STATUS_MASK             (0x2000U)
#define ITRC_STATUS_IN13_STATUS_SHIFT            (13U)
/*! IN13_STATUS - Low voltage/High voltage event detected on VDD1 rail.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN13_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN13_STATUS_SHIFT)) & ITRC_STATUS_IN13_STATUS_MASK)

#define ITRC_STATUS_IN14_STATUS_MASK             (0x4000U)
#define ITRC_STATUS_IN14_STATUS_SHIFT            (14U)
/*! IN14_STATUS - Low voltage/High voltage event detected on VDD1 rail.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN14_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK)

#define ITRC_STATUS_IN15_STATUS_MASK             (0x8000U)
#define ITRC_STATUS_IN15_STATUS_SHIFT            (15U)
/*! IN15_STATUS - Analog glitch detector 0 event detected on VDD2 rail.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_IN15_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK)

#define ITRC_STATUS_OUT0_STATUS_MASK             (0x10000U)
#define ITRC_STATUS_OUT0_STATUS_SHIFT            (16U)
/*! OUT0_STATUS - ITRC triggered ITRC_IRQ output.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_OUT0_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK)

#define ITRC_STATUS_OUT1_STATUS_MASK             (0x20000U)
#define ITRC_STATUS_OUT1_STATUS_SHIFT            (17U)
/*! OUT1_STATUS - ITRC triggered ELS_RESET to clear ELS key store.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_OUT1_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK)

#define ITRC_STATUS_OUT2_STATUS_MASK             (0x40000U)
#define ITRC_STATUS_OUT2_STATUS_SHIFT            (18U)
/*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_OUT2_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK)

#define ITRC_STATUS_OUT3_STATUS_MASK             (0x80000U)
#define ITRC_STATUS_OUT3_STATUS_SHIFT            (19U)
/*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_OUT3_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK)

#define ITRC_STATUS_OUT4_STATUS_MASK             (0x100000U)
#define ITRC_STATUS_OUT4_STATUS_SHIFT            (20U)
/*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_OUT4_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK)

#define ITRC_STATUS_OUT5_STATUS_MASK             (0x200000U)
#define ITRC_STATUS_OUT5_STATUS_SHIFT            (21U)
/*! OUT5_STATUS - ITRC triggered TMPR_OUT0 internal signal connected to various on-chip multiplexers.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_OUT5_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK)

#define ITRC_STATUS_OUT6_STATUS_MASK             (0x400000U)
#define ITRC_STATUS_OUT6_STATUS_SHIFT            (22U)
/*! OUT6_STATUS - ITRC triggered TMPR_OUT1 internal signal connected to various on-chip multiplexers.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS_OUT6_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT6_STATUS_SHIFT)) & ITRC_STATUS_OUT6_STATUS_MASK)
/*! @} */

/*! @name STATUS1 - ITRC IN16 to IN47 Status */
/*! @{ */

#define ITRC_STATUS1_IN16_STATUS_MASK            (0x1U)
#define ITRC_STATUS1_IN16_STATUS_SHIFT           (0U)
/*! IN16_STATUS - Analog glitch detector 1 event detected on VDD1 rail.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN16_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN16_STATUS_SHIFT)) & ITRC_STATUS1_IN16_STATUS_MASK)

#define ITRC_STATUS1_IN18_STATUS_MASK            (0x4U)
#define ITRC_STATUS1_IN18_STATUS_SHIFT           (2U)
/*! IN18_STATUS - Temperature tamper 0 or 1 event occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN18_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN18_STATUS_SHIFT)) & ITRC_STATUS1_IN18_STATUS_MASK)

#define ITRC_STATUS1_IN20_STATUS_MASK            (0x10U)
#define ITRC_STATUS1_IN20_STATUS_SHIFT           (4U)
/*! IN20_STATUS - Shared APB slave group 0 or Shared peripheral AIPS2 illegal access events occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN20_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN20_STATUS_SHIFT)) & ITRC_STATUS1_IN20_STATUS_MASK)

#define ITRC_STATUS1_IN21_STATUS_MASK            (0x20U)
#define ITRC_STATUS1_IN21_STATUS_SHIFT           (5U)
/*! IN21_STATUS - COMPUTE_AHBSC bus checkers detected illegal access.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN21_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN21_STATUS_SHIFT)) & ITRC_STATUS1_IN21_STATUS_MASK)

#define ITRC_STATUS1_IN22_STATUS_MASK            (0x40U)
#define ITRC_STATUS1_IN22_STATUS_SHIFT           (6U)
/*! IN22_STATUS - SENSE_AHBSC bus checkers detected illegal access.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN22_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN22_STATUS_SHIFT)) & ITRC_STATUS1_IN22_STATUS_MASK)

#define ITRC_STATUS1_IN23_STATUS_MASK            (0x80U)
#define ITRC_STATUS1_IN23_STATUS_SHIFT           (7U)
/*! IN23_STATUS - MEDIA_AHBSC bus checkers detected illegal access.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN23_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN23_STATUS_SHIFT)) & ITRC_STATUS1_IN23_STATUS_MASK)

#define ITRC_STATUS1_IN24_STATUS_MASK            (0x100U)
#define ITRC_STATUS1_IN24_STATUS_SHIFT           (8U)
/*! IN24_STATUS - PKC module detected an error event.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN24_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN24_STATUS_SHIFT)) & ITRC_STATUS1_IN24_STATUS_MASK)

#define ITRC_STATUS1_IN25_STATUS_MASK            (0x200U)
#define ITRC_STATUS1_IN25_STATUS_SHIFT           (9U)
/*! IN25_STATUS - ELS error event occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN25_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN25_STATUS_SHIFT)) & ITRC_STATUS1_IN25_STATUS_MASK)

#define ITRC_STATUS1_IN26_STATUS_MASK            (0x400U)
#define ITRC_STATUS1_IN26_STATUS_SHIFT           (10U)
/*! IN26_STATUS - Low frequency clock tamper output event occurred.
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN26_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN26_STATUS_SHIFT)) & ITRC_STATUS1_IN26_STATUS_MASK)

#define ITRC_STATUS1_IN28_STATUS_MASK            (0x1000U)
#define ITRC_STATUS1_IN28_STATUS_SHIFT           (12U)
/*! IN28_STATUS - SM3 or SM4 SGI error event occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN28_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN28_STATUS_SHIFT)) & ITRC_STATUS1_IN28_STATUS_MASK)

#define ITRC_STATUS1_IN29_STATUS_MASK            (0x2000U)
#define ITRC_STATUS1_IN29_STATUS_SHIFT           (13U)
/*! IN29_STATUS - TRNG HW error event occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN29_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN29_STATUS_SHIFT)) & ITRC_STATUS1_IN29_STATUS_MASK)

#define ITRC_STATUS1_IN30_STATUS_MASK            (0x4000U)
#define ITRC_STATUS1_IN30_STATUS_SHIFT           (14U)
/*! IN30_STATUS - PINT0 pin interrupt bit 0 occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN30_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN30_STATUS_SHIFT)) & ITRC_STATUS1_IN30_STATUS_MASK)

#define ITRC_STATUS1_IN31_STATUS_MASK            (0x8000U)
#define ITRC_STATUS1_IN31_STATUS_SHIFT           (15U)
/*! IN31_STATUS - PINT0 pin interrupt bit 1 occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN31_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN31_STATUS_SHIFT)) & ITRC_STATUS1_IN31_STATUS_MASK)

#define ITRC_STATUS1_IN32_STATUS_MASK            (0x10000U)
#define ITRC_STATUS1_IN32_STATUS_SHIFT           (16U)
/*! IN32_STATUS - PINT1 pin interrupt bit 0 occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN32_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN32_STATUS_SHIFT)) & ITRC_STATUS1_IN32_STATUS_MASK)

#define ITRC_STATUS1_IN33_STATUS_MASK            (0x20000U)
#define ITRC_STATUS1_IN33_STATUS_SHIFT           (17U)
/*! IN33_STATUS - PINT1 pin interrupt bit 1 occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN33_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN33_STATUS_SHIFT)) & ITRC_STATUS1_IN33_STATUS_MASK)

#define ITRC_STATUS1_IN34_STATUS_MASK            (0x40000U)
#define ITRC_STATUS1_IN34_STATUS_SHIFT           (18U)
/*! IN34_STATUS - Software event 0 occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN34_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN34_STATUS_SHIFT)) & ITRC_STATUS1_IN34_STATUS_MASK)

#define ITRC_STATUS1_IN35_STATUS_MASK            (0x80000U)
#define ITRC_STATUS1_IN35_STATUS_SHIFT           (19U)
/*! IN35_STATUS - Software event 1 occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN35_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN35_STATUS_SHIFT)) & ITRC_STATUS1_IN35_STATUS_MASK)

#define ITRC_STATUS1_IN36_STATUS_MASK            (0x100000U)
#define ITRC_STATUS1_IN36_STATUS_SHIFT           (20U)
/*! IN36_STATUS - XSPI0 GCM error occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN36_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN36_STATUS_SHIFT)) & ITRC_STATUS1_IN36_STATUS_MASK)

#define ITRC_STATUS1_IN37_STATUS_MASK            (0x200000U)
#define ITRC_STATUS1_IN37_STATUS_SHIFT           (21U)
/*! IN37_STATUS - GLIKEY error occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN37_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN37_STATUS_SHIFT)) & ITRC_STATUS1_IN37_STATUS_MASK)

#define ITRC_STATUS1_IN38_STATUS_MASK            (0x400000U)
#define ITRC_STATUS1_IN38_STATUS_SHIFT           (22U)
/*! IN38_STATUS - XSPI1 GCM error occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN38_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN38_STATUS_SHIFT)) & ITRC_STATUS1_IN38_STATUS_MASK)

#define ITRC_STATUS1_IN47_STATUS_MASK            (0x80000000U)
#define ITRC_STATUS1_IN47_STATUS_SHIFT           (31U)
/*! IN47_STATUS - OCOTP error occurred
 *  0b0..Output not triggered.
 *  0b1..Output has been triggered.
 */
#define ITRC_STATUS1_IN47_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN47_STATUS_SHIFT)) & ITRC_STATUS1_IN47_STATUS_MASK)
/*! @} */

/*! @name OUT_SEL - Trigger Source IN0 to IN15 selector */
/*! @{ */

#define ITRC_OUT_SEL_IN0_SELn_MASK               (0x3U)
#define ITRC_OUT_SEL_IN0_SELn_SHIFT              (0U)
/*! IN0_SELn - Selects digital glitch detector 0 and 1 as a trigger source. */
#define ITRC_OUT_SEL_IN0_SELn(x)                 (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN0_SELn_SHIFT)) & ITRC_OUT_SEL_IN0_SELn_MASK)

#define ITRC_OUT_SEL_IN1_SELn_MASK               (0xCU)
#define ITRC_OUT_SEL_IN1_SELn_SHIFT              (2U)
/*! IN1_SELn - Selects digital glitch detector 2 and 3 as a trigger source. */
#define ITRC_OUT_SEL_IN1_SELn(x)                 (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN1_SELn_SHIFT)) & ITRC_OUT_SEL_IN1_SELn_MASK)

#define ITRC_OUT_SEL_IN4_SELn_MASK               (0x300U)
#define ITRC_OUT_SEL_IN4_SELn_SHIFT              (8U)
/*! IN4_SELn - Selects Code Watchdog 0 event as a trigger source. */
#define ITRC_OUT_SEL_IN4_SELn(x)                 (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN4_SELn_SHIFT)) & ITRC_OUT_SEL_IN4_SELn_MASK)

#define ITRC_OUT_SEL_IN5_SELn_MASK               (0xC00U)
#define ITRC_OUT_SEL_IN5_SELn_SHIFT              (10U)
/*! IN5_SELn - Selects Code Watchdog 1 event as a trigger source. */
#define ITRC_OUT_SEL_IN5_SELn(x)                 (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN5_SELn_SHIFT)) & ITRC_OUT_SEL_IN5_SELn_MASK)

#define ITRC_OUT_SEL_IN6_SELn_MASK               (0x3000U)
#define ITRC_OUT_SEL_IN6_SELn_SHIFT              (12U)
/*! IN6_SELn - Selects Code Watchdog 2 event as a trigger source. */
#define ITRC_OUT_SEL_IN6_SELn(x)                 (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN6_SELn_SHIFT)) & ITRC_OUT_SEL_IN6_SELn_MASK)

#define ITRC_OUT_SEL_IN7_SELn_MASK               (0xC000U)
#define ITRC_OUT_SEL_IN7_SELn_SHIFT              (14U)
/*! IN7_SELn - Selects Code Watchdog 3 event as a trigger source. */
#define ITRC_OUT_SEL_IN7_SELn(x)                 (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN7_SELn_SHIFT)) & ITRC_OUT_SEL_IN7_SELn_MASK)

#define ITRC_OUT_SEL_IN8_SELn_MASK               (0x30000U)
#define ITRC_OUT_SEL_IN8_SELn_SHIFT              (16U)
/*! IN8_SELn - Selects Code Watchdog 4 event as a trigger source. */
#define ITRC_OUT_SEL_IN8_SELn(x)                 (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN8_SELn_SHIFT)) & ITRC_OUT_SEL_IN8_SELn_MASK)

#define ITRC_OUT_SEL_IN9_SELn_MASK               (0xC0000U)
#define ITRC_OUT_SEL_IN9_SELn_SHIFT              (18U)
/*! IN9_SELn - Selects Watchdog 0 timer event as a trigger source. */
#define ITRC_OUT_SEL_IN9_SELn(x)                 (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN9_SELn_SHIFT)) & ITRC_OUT_SEL_IN9_SELn_MASK)

#define ITRC_OUT_SEL_IN10_SELn_MASK              (0x300000U)
#define ITRC_OUT_SEL_IN10_SELn_SHIFT             (20U)
/*! IN10_SELn - Selects Watchdog 1 timer event as a trigger source. */
#define ITRC_OUT_SEL_IN10_SELn(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN10_SELn_SHIFT)) & ITRC_OUT_SEL_IN10_SELn_MASK)

#define ITRC_OUT_SEL_IN11_SELn_MASK              (0xC00000U)
#define ITRC_OUT_SEL_IN11_SELn_SHIFT             (22U)
/*! IN11_SELn - Selects Watchdog 2 timer event as a trigger source. */
#define ITRC_OUT_SEL_IN11_SELn(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN11_SELn_SHIFT)) & ITRC_OUT_SEL_IN11_SELn_MASK)

#define ITRC_OUT_SEL_IN12_SELn_MASK              (0x3000000U)
#define ITRC_OUT_SEL_IN12_SELn_SHIFT             (24U)
/*! IN12_SELn - Selects Watchdog 3 timer event as a trigger source. */
#define ITRC_OUT_SEL_IN12_SELn(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN12_SELn_SHIFT)) & ITRC_OUT_SEL_IN12_SELn_MASK)

#define ITRC_OUT_SEL_IN13_SELn_MASK              (0xC000000U)
#define ITRC_OUT_SEL_IN13_SELn_SHIFT             (26U)
/*! IN13_SELn - Selects High-voltage and Low-voltage event on VDD2 rail as a trigger source. */
#define ITRC_OUT_SEL_IN13_SELn(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN13_SELn_SHIFT)) & ITRC_OUT_SEL_IN13_SELn_MASK)

#define ITRC_OUT_SEL_IN14_SELn_MASK              (0x30000000U)
#define ITRC_OUT_SEL_IN14_SELn_SHIFT             (28U)
/*! IN14_SELn - Selects High-voltage and Low-voltage event on VDD1 rail as a trigger source. */
#define ITRC_OUT_SEL_IN14_SELn(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN14_SELn_SHIFT)) & ITRC_OUT_SEL_IN14_SELn_MASK)

#define ITRC_OUT_SEL_IN15_SELn_MASK              (0xC0000000U)
#define ITRC_OUT_SEL_IN15_SELn_SHIFT             (30U)
/*! IN15_SELn - Selects Analog glitch detector 0 event on VDD2 rail as a trigger source. */
#define ITRC_OUT_SEL_IN15_SELn(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_IN15_SELn_SHIFT)) & ITRC_OUT_SEL_IN15_SELn_MASK)
/*! @} */

/* The count of ITRC_OUT_SEL */
#define ITRC_OUT_SEL_COUNT                       (8U)

/* The count of ITRC_OUT_SEL */
#define ITRC_OUT_SEL_COUNT2                      (2U)

/*! @name OUT_SEL_1 - Trigger Source IN16 to IN31 selector */
/*! @{ */

#define ITRC_OUT_SEL_1_IN16_SELn_MASK            (0x3U)
#define ITRC_OUT_SEL_1_IN16_SELn_SHIFT           (0U)
/*! IN16_SELn - Selects Analog glitch detector 1 event on VDD1 rail as a trigger source. */
#define ITRC_OUT_SEL_1_IN16_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN16_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN16_SELn_MASK)

#define ITRC_OUT_SEL_1_IN18_SELn_MASK            (0x30U)
#define ITRC_OUT_SEL_1_IN18_SELn_SHIFT           (4U)
/*! IN18_SELn - Selects Temperature detector 0 and 1 tamper output event as a trigger source. */
#define ITRC_OUT_SEL_1_IN18_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN18_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN18_SELn_MASK)

#define ITRC_OUT_SEL_1_IN20_SELn_MASK            (0x300U)
#define ITRC_OUT_SEL_1_IN20_SELn_SHIFT           (8U)
/*! IN20_SELn - Selects Shared APB slave group 0 and Shared peripheral AIPS2 illegal access event as a trigger source. */
#define ITRC_OUT_SEL_1_IN20_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN20_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN20_SELn_MASK)

#define ITRC_OUT_SEL_1_IN21_SELn_MASK            (0xC00U)
#define ITRC_OUT_SEL_1_IN21_SELn_SHIFT           (10U)
/*! IN21_SELn - Selects AHBSC_COMPUTE illegal access event as a trigger source. */
#define ITRC_OUT_SEL_1_IN21_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN21_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN21_SELn_MASK)

#define ITRC_OUT_SEL_1_IN22_SELn_MASK            (0x3000U)
#define ITRC_OUT_SEL_1_IN22_SELn_SHIFT           (12U)
/*! IN22_SELn - Selects AHBSC_SENSE illegal access event as a trigger source. */
#define ITRC_OUT_SEL_1_IN22_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN22_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN22_SELn_MASK)

#define ITRC_OUT_SEL_1_IN23_SELn_MASK            (0xC000U)
#define ITRC_OUT_SEL_1_IN23_SELn_SHIFT           (14U)
/*! IN23_SELn - Selects AHBSC_MEDIA illegal access event as a trigger source. */
#define ITRC_OUT_SEL_1_IN23_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN23_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN23_SELn_MASK)

#define ITRC_OUT_SEL_1_IN24_SELn_MASK            (0x30000U)
#define ITRC_OUT_SEL_1_IN24_SELn_SHIFT           (16U)
/*! IN24_SELn - Selects PKC error event as a trigger source. */
#define ITRC_OUT_SEL_1_IN24_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN24_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN24_SELn_MASK)

#define ITRC_OUT_SEL_1_IN25_SELn_MASK            (0xC0000U)
#define ITRC_OUT_SEL_1_IN25_SELn_SHIFT           (18U)
/*! IN25_SELn - Selects ELS error event as a trigger source. */
#define ITRC_OUT_SEL_1_IN25_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN25_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN25_SELn_MASK)

#define ITRC_OUT_SEL_1_IN26_SELn_MASK            (0x300000U)
#define ITRC_OUT_SEL_1_IN26_SELn_SHIFT           (20U)
/*! IN26_SELn - Selects low-frequency Clock monitor tamper output event as a trigger source. */
#define ITRC_OUT_SEL_1_IN26_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN26_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN26_SELn_MASK)

#define ITRC_OUT_SEL_1_IN28_SELn_MASK            (0x3000000U)
#define ITRC_OUT_SEL_1_IN28_SELn_SHIFT           (24U)
/*! IN28_SELn - Selects SM3 and SM4 SGI error event as a trigger source. */
#define ITRC_OUT_SEL_1_IN28_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN28_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN28_SELn_MASK)

#define ITRC_OUT_SEL_1_IN29_SELn_MASK            (0xC000000U)
#define ITRC_OUT_SEL_1_IN29_SELn_SHIFT           (26U)
/*! IN29_SELn - Selects TRNG HW error event as a trigger source. */
#define ITRC_OUT_SEL_1_IN29_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN29_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN29_SELn_MASK)

#define ITRC_OUT_SEL_1_IN30_SELn_MASK            (0x30000000U)
#define ITRC_OUT_SEL_1_IN30_SELn_SHIFT           (28U)
/*! IN30_SELn - Selects PINT0 pin input interrupt bit 0 as a trigger source. */
#define ITRC_OUT_SEL_1_IN30_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN30_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN30_SELn_MASK)

#define ITRC_OUT_SEL_1_IN31_SELn_MASK            (0xC0000000U)
#define ITRC_OUT_SEL_1_IN31_SELn_SHIFT           (30U)
/*! IN31_SELn - Selects PINT0 pin input interrupt bit 1 as a trigger source. */
#define ITRC_OUT_SEL_1_IN31_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_1_IN31_SELn_SHIFT)) & ITRC_OUT_SEL_1_IN31_SELn_MASK)
/*! @} */

/* The count of ITRC_OUT_SEL_1 */
#define ITRC_OUT_SEL_1_COUNT                     (8U)

/* The count of ITRC_OUT_SEL_1 */
#define ITRC_OUT_SEL_1_COUNT2                    (2U)

/*! @name OUT_SEL_2 - Trigger source IN32 to IN47 selector */
/*! @{ */

#define ITRC_OUT_SEL_2_IN32_SELn_MASK            (0x3U)
#define ITRC_OUT_SEL_2_IN32_SELn_SHIFT           (0U)
/*! IN32_SELn - Select PINT1 pin input interrupt bit 0 as a trigger source. */
#define ITRC_OUT_SEL_2_IN32_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN32_SELn_SHIFT)) & ITRC_OUT_SEL_2_IN32_SELn_MASK)

#define ITRC_OUT_SEL_2_IN33_SELn_MASK            (0xCU)
#define ITRC_OUT_SEL_2_IN33_SELn_SHIFT           (2U)
/*! IN33_SELn - Select PINT1 pin input interrupt bit 1 as a trigger source. */
#define ITRC_OUT_SEL_2_IN33_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN33_SELn_SHIFT)) & ITRC_OUT_SEL_2_IN33_SELn_MASK)

#define ITRC_OUT_SEL_2_IN34_SELn_MASK            (0x30U)
#define ITRC_OUT_SEL_2_IN34_SELn_SHIFT           (4U)
/*! IN34_SELn - Selects software event 0 as a trigger source. */
#define ITRC_OUT_SEL_2_IN34_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN34_SELn_SHIFT)) & ITRC_OUT_SEL_2_IN34_SELn_MASK)

#define ITRC_OUT_SEL_2_IN35_SELn_MASK            (0xC0U)
#define ITRC_OUT_SEL_2_IN35_SELn_SHIFT           (6U)
/*! IN35_SELn - Selects software event 1 as a trigger source. */
#define ITRC_OUT_SEL_2_IN35_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN35_SELn_SHIFT)) & ITRC_OUT_SEL_2_IN35_SELn_MASK)

#define ITRC_OUT_SEL_2_IN36_SELn_MASK            (0x300U)
#define ITRC_OUT_SEL_2_IN36_SELn_SHIFT           (8U)
/*! IN36_SELn - Selects XSPI0 GCM error as a trigger source. */
#define ITRC_OUT_SEL_2_IN36_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN36_SELn_SHIFT)) & ITRC_OUT_SEL_2_IN36_SELn_MASK)

#define ITRC_OUT_SEL_2_IN37_SELn_MASK            (0xC00U)
#define ITRC_OUT_SEL_2_IN37_SELn_SHIFT           (10U)
/*! IN37_SELn - Selects GLIKEY error as a trigger source. */
#define ITRC_OUT_SEL_2_IN37_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN37_SELn_SHIFT)) & ITRC_OUT_SEL_2_IN37_SELn_MASK)

#define ITRC_OUT_SEL_2_IN38_SEL0_MASK            (0x3000U)
#define ITRC_OUT_SEL_2_IN38_SEL0_SHIFT           (12U)
/*! IN38_SEL0 - Selects XSPI1 GCM error as a trigger source. */
#define ITRC_OUT_SEL_2_IN38_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN38_SEL0_SHIFT)) & ITRC_OUT_SEL_2_IN38_SEL0_MASK)

#define ITRC_OUT_SEL_2_IN38_SEL1_MASK            (0x3000U)
#define ITRC_OUT_SEL_2_IN38_SEL1_SHIFT           (12U)
/*! IN38_SEL1 - Selects XSPI1 GCM error as a trigger source. */
#define ITRC_OUT_SEL_2_IN38_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN38_SEL1_SHIFT)) & ITRC_OUT_SEL_2_IN38_SEL1_MASK)

#define ITRC_OUT_SEL_2_IN47_SELn_MASK            (0xC0000000U)
#define ITRC_OUT_SEL_2_IN47_SELn_SHIFT           (30U)
/*! IN47_SELn - Selects OCOTP error as a trigger source */
#define ITRC_OUT_SEL_2_IN47_SELn(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT_SEL_2_IN47_SELn_SHIFT)) & ITRC_OUT_SEL_2_IN47_SELn_MASK)
/*! @} */

/* The count of ITRC_OUT_SEL_2 */
#define ITRC_OUT_SEL_2_COUNT                     (8U)

/* The count of ITRC_OUT_SEL_2 */
#define ITRC_OUT_SEL_2_COUNT2                    (2U)

/*! @name SW_EVENT0 - Software event 0 */
/*! @{ */

#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK   (0xFFFFFFFFU)
#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT  (0U)
/*! TRIGGER_SW_EVENT_0 - Trigger software event 0. */
#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x)     (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK)
/*! @} */

/*! @name SW_EVENT1 - Software event 1 */
/*! @{ */

#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK   (0xFFFFFFFFU)
#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT  (0U)
/*! TRIGGER_SW_EVENT_1 - Trigger software event 1. */
#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x)     (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ITRC_Register_Masks */


/* ITRC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ITRC base address */
  #define ITRC_BASE                                (0x50012000u)
  /** Peripheral ITRC base address */
  #define ITRC_BASE_NS                             (0x40012000u)
  /** Peripheral ITRC base pointer */
  #define ITRC                                     ((ITRC_Type *)ITRC_BASE)
  /** Peripheral ITRC base pointer */
  #define ITRC_NS                                  ((ITRC_Type *)ITRC_BASE_NS)
  /** Array initializer of ITRC peripheral base addresses */
  #define ITRC_BASE_ADDRS                          { ITRC_BASE }
  /** Array initializer of ITRC peripheral base pointers */
  #define ITRC_BASE_PTRS                           { ITRC }
  /** Array initializer of ITRC peripheral base addresses */
  #define ITRC_BASE_ADDRS_NS                       { ITRC_BASE_NS }
  /** Array initializer of ITRC peripheral base pointers */
  #define ITRC_BASE_PTRS_NS                        { ITRC_NS }
#else
  /** Peripheral ITRC base address */
  #define ITRC_BASE                                (0x40012000u)
  /** Peripheral ITRC base pointer */
  #define ITRC                                     ((ITRC_Type *)ITRC_BASE)
  /** Array initializer of ITRC peripheral base addresses */
  #define ITRC_BASE_ADDRS                          { ITRC_BASE }
  /** Array initializer of ITRC peripheral base pointers */
  #define ITRC_BASE_PTRS                           { ITRC }
#endif

/*!
 * @}
 */ /* end of group ITRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- JPEGDEC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup JPEGDEC_Peripheral_Access_Layer JPEGDEC Peripheral Access Layer
 * @{
 */

/** JPEGDEC - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[52];
  __IO uint32_t CTRL;                              /**< Control, offset: 0x34 */
} JPEGDEC_Type;

/* ----------------------------------------------------------------------------
   -- JPEGDEC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup JPEGDEC_Register_Masks JPEGDEC Register Masks
 * @{
 */

/*! @name CTRL - Control */
/*! @{ */

#define JPEGDEC_CTRL_LP_MASK                     (0x1U)
#define JPEGDEC_CTRL_LP_SHIFT                    (0U)
/*! LP - Low Power
 *  0b0..No effect
 *  0b1..Enable
 */
#define JPEGDEC_CTRL_LP(x)                       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_CTRL_LP_SHIFT)) & JPEGDEC_CTRL_LP_MASK)

#define JPEGDEC_CTRL_SWR_MASK                    (0x2U)
#define JPEGDEC_CTRL_SWR_SHIFT                   (1U)
/*! SWR - Soft Reset
 *  0b0..No effect
 *  0b1..Enable
 */
#define JPEGDEC_CTRL_SWR(x)                      (((uint32_t)(((uint32_t)(x)) << JPEGDEC_CTRL_SWR_SHIFT)) & JPEGDEC_CTRL_SWR_MASK)

#define JPEGDEC_CTRL_GO_MASK                     (0x4U)
#define JPEGDEC_CTRL_GO_SHIFT                    (2U)
/*! GO - Go
 *  0b0..No effect
 *  0b1..Enable
 */
#define JPEGDEC_CTRL_GO(x)                       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_CTRL_GO_SHIFT)) & JPEGDEC_CTRL_GO_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group JPEGDEC_Register_Masks */


/* JPEGDEC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral JPEGDEC base address */
  #define JPEGDEC_BASE                             (0x500A6100u)
  /** Peripheral JPEGDEC base address */
  #define JPEGDEC_BASE_NS                          (0x400A6100u)
  /** Peripheral JPEGDEC base pointer */
  #define JPEGDEC                                  ((JPEGDEC_Type *)JPEGDEC_BASE)
  /** Peripheral JPEGDEC base pointer */
  #define JPEGDEC_NS                               ((JPEGDEC_Type *)JPEGDEC_BASE_NS)
  /** Array initializer of JPEGDEC peripheral base addresses */
  #define JPEGDEC_BASE_ADDRS                       { JPEGDEC_BASE }
  /** Array initializer of JPEGDEC peripheral base pointers */
  #define JPEGDEC_BASE_PTRS                        { JPEGDEC }
  /** Array initializer of JPEGDEC peripheral base addresses */
  #define JPEGDEC_BASE_ADDRS_NS                    { JPEGDEC_BASE_NS }
  /** Array initializer of JPEGDEC peripheral base pointers */
  #define JPEGDEC_BASE_PTRS_NS                     { JPEGDEC_NS }
#else
  /** Peripheral JPEGDEC base address */
  #define JPEGDEC_BASE                             (0x400A6100u)
  /** Peripheral JPEGDEC base pointer */
  #define JPEGDEC                                  ((JPEGDEC_Type *)JPEGDEC_BASE)
  /** Array initializer of JPEGDEC peripheral base addresses */
  #define JPEGDEC_BASE_ADDRS                       { JPEGDEC_BASE }
  /** Array initializer of JPEGDEC peripheral base pointers */
  #define JPEGDEC_BASE_PTRS                        { JPEGDEC }
#endif

/*!
 * @}
 */ /* end of group JPEGDEC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- JPGDECWRP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup JPGDECWRP_Peripheral_Access_Layer JPGDECWRP Peripheral Access Layer
 * @{
 */

/** JPGDECWRP - Register Layout Typedef */
typedef struct {
  __IO uint32_t GLB_CTRL;                          /**< Global Control, offset: 0x0 */
  __I  uint32_t COM_STATUS;                        /**< Common Status, offset: 0x4 */
       uint8_t RESERVED_0[12];
  __IO uint32_t OUT_BUF_BASE0;                     /**< Output Image Frame Buffer0 Base Address, offset: 0x14 */
  __IO uint32_t OUT_BUF_BASE1;                     /**< Output Image Frame Buffer1 Base Address, offset: 0x18 */
  __IO uint32_t OUT_PITCH;                         /**< Image Output Buffer Pitch, offset: 0x1C */
  __IO uint32_t STM_BUFBASE;                       /**< Input JPEG Stream Buffer Base Address, offset: 0x20 */
  __IO uint32_t STM_BUFSIZE;                       /**< Input JPEG Stream Buffer Size, offset: 0x24 */
  __IO uint32_t IMGSIZE;                           /**< Image Resolution, offset: 0x28 */
  __IO uint32_t STM_CTRL;                          /**< Bit Stream and Switching Control, offset: 0x2C */
       uint8_t RESERVED_1[464];
  struct {                                         /* offset: 0x200, array step: 0x200 */
    __IO uint32_t SLOT_STATUS;                       /**< Bit Stream Status, array offset: 0x200, array step: 0x200 */
    __IO uint32_t SLOT_IRQ_EN;                       /**< Bit Stream Interrupt Enable, array offset: 0x204, array step: 0x200 */
    __I  uint32_t SLOT_BUF_PTR;                      /**< Bit Stream Buffer Pointer, array offset: 0x208, array step: 0x200 */
    __I  uint32_t SLOT_CUR_DESCPT_PTR;               /**< Current Descriptors, array offset: 0x20C, array step: 0x200 */
    __IO uint32_t SLOT_NXT_DESCPT_PTR;               /**< Next Descriptors, array offset: 0x210, array step: 0x200 */
         uint8_t RESERVED_0[492];
  } SLOT_REGS[4];
} JPGDECWRP_Type;

/* ----------------------------------------------------------------------------
   -- JPGDECWRP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup JPGDECWRP_Register_Masks JPGDECWRP Register Masks
 * @{
 */

/*! @name GLB_CTRL - Global Control */
/*! @{ */

#define JPGDECWRP_GLB_CTRL_JPG_DEC_EN_MASK       (0x1U)
#define JPGDECWRP_GLB_CTRL_JPG_DEC_EN_SHIFT      (0U)
/*! JPG_DEC_EN - JPEGDEC and JPGDECWRP Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_GLB_CTRL_JPG_DEC_EN(x)         (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_GLB_CTRL_JPG_DEC_EN_SHIFT)) & JPGDECWRP_GLB_CTRL_JPG_DEC_EN_MASK)

#define JPGDECWRP_GLB_CTRL_SFTRST_MASK           (0x2U)
#define JPGDECWRP_GLB_CTRL_SFTRST_SHIFT          (1U)
/*! SFTRST - Engine Soft Reset
 *  0b0..No effect
 *  0b1..Performs a soft reset.
 */
#define JPGDECWRP_GLB_CTRL_SFTRST(x)             (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_GLB_CTRL_SFTRST_SHIFT)) & JPGDECWRP_GLB_CTRL_SFTRST_MASK)

#define JPGDECWRP_GLB_CTRL_DEC_GO_MASK           (0x4U)
#define JPGDECWRP_GLB_CTRL_DEC_GO_SHIFT          (2U)
/*! DEC_GO - Start Decoding
 *  0b0..Do not start decoding manually.
 *  0b1..Starts decoding manually.
 */
#define JPGDECWRP_GLB_CTRL_DEC_GO(x)             (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_GLB_CTRL_DEC_GO_SHIFT)) & JPGDECWRP_GLB_CTRL_DEC_GO_MASK)

#define JPGDECWRP_GLB_CTRL_L_ENDIAN_MASK         (0x8U)
#define JPGDECWRP_GLB_CTRL_L_ENDIAN_SHIFT        (3U)
/*! L_ENDIAN - Little-Endian Enable
 *  0b0..Big-Endian
 *  0b1..Little-Endian
 */
#define JPGDECWRP_GLB_CTRL_L_ENDIAN(x)           (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_GLB_CTRL_L_ENDIAN_SHIFT)) & JPGDECWRP_GLB_CTRL_L_ENDIAN_MASK)

#define JPGDECWRP_GLB_CTRL_SLOT_EN_MASK          (0xF0U)
#define JPGDECWRP_GLB_CTRL_SLOT_EN_SHIFT         (4U)
/*! SLOT_EN - Slots Enable
 *  0b0000..Disables all slots.
 *  0b0001..Enables SLOT0.
 *  0b0010..Enables SLOT1.
 *  0b0100..Enables SLOT2.
 *  0b1000..Enables SLOT3.
 *  *..
 */
#define JPGDECWRP_GLB_CTRL_SLOT_EN(x)            (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_GLB_CTRL_SLOT_EN_SHIFT)) & JPGDECWRP_GLB_CTRL_SLOT_EN_MASK)
/*! @} */

/*! @name COM_STATUS - Common Status */
/*! @{ */

#define JPGDECWRP_COM_STATUS_CUR_SLOT_MASK       (0x60000000U)
#define JPGDECWRP_COM_STATUS_CUR_SLOT_SHIFT      (29U)
/*! CUR_SLOT - Current Slot */
#define JPGDECWRP_COM_STATUS_CUR_SLOT(x)         (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_COM_STATUS_CUR_SLOT_SHIFT)) & JPGDECWRP_COM_STATUS_CUR_SLOT_MASK)

#define JPGDECWRP_COM_STATUS_DEC_ONGOING_MASK    (0x80000000U)
#define JPGDECWRP_COM_STATUS_DEC_ONGOING_SHIFT   (31U)
/*! DEC_ONGOING - Decoding Ongoing */
#define JPGDECWRP_COM_STATUS_DEC_ONGOING(x)      (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_COM_STATUS_DEC_ONGOING_SHIFT)) & JPGDECWRP_COM_STATUS_DEC_ONGOING_MASK)
/*! @} */

/*! @name OUT_BUF_BASE0 - Output Image Frame Buffer0 Base Address */
/*! @{ */

#define JPGDECWRP_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK (0xFFFFFFF0U)
#define JPGDECWRP_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT (4U)
/*! OUT_BUF_BASE0 - Pixel Frame Buffer0 Base */
#define JPGDECWRP_OUT_BUF_BASE0_OUT_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT)) & JPGDECWRP_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK)
/*! @} */

/*! @name OUT_BUF_BASE1 - Output Image Frame Buffer1 Base Address */
/*! @{ */

#define JPGDECWRP_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK (0xFFFFFFF0U)
#define JPGDECWRP_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT (4U)
/*! OUT_BUF_BASE1 - Pixel Frame Buffer1 Base */
#define JPGDECWRP_OUT_BUF_BASE1_OUT_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT)) & JPGDECWRP_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK)
/*! @} */

/*! @name OUT_PITCH - Image Output Buffer Pitch */
/*! @{ */

#define JPGDECWRP_OUT_PITCH_OUT_PITCH_MASK       (0xFFFFU)
#define JPGDECWRP_OUT_PITCH_OUT_PITCH_SHIFT      (0U)
/*! OUT_PITCH - Output Image Pitch */
#define JPGDECWRP_OUT_PITCH_OUT_PITCH(x)         (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_OUT_PITCH_OUT_PITCH_SHIFT)) & JPGDECWRP_OUT_PITCH_OUT_PITCH_MASK)
/*! @} */

/*! @name STM_BUFBASE - Input JPEG Stream Buffer Base Address */
/*! @{ */

#define JPGDECWRP_STM_BUFBASE_STM_BUFBASE_MASK   (0xFFFFFFF0U)
#define JPGDECWRP_STM_BUFBASE_STM_BUFBASE_SHIFT  (4U)
/*! STM_BUFBASE - Bit Stream Buffer Base */
#define JPGDECWRP_STM_BUFBASE_STM_BUFBASE(x)     (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPGDECWRP_STM_BUFBASE_STM_BUFBASE_MASK)
/*! @} */

/*! @name STM_BUFSIZE - Input JPEG Stream Buffer Size */
/*! @{ */

#define JPGDECWRP_STM_BUFSIZE_STM_BUFSIZE_MASK   (0xFFFFFC00U)
#define JPGDECWRP_STM_BUFSIZE_STM_BUFSIZE_SHIFT  (10U)
/*! STM_BUFSIZE - Bit Stream Buffer Size */
#define JPGDECWRP_STM_BUFSIZE_STM_BUFSIZE(x)     (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPGDECWRP_STM_BUFSIZE_STM_BUFSIZE_MASK)
/*! @} */

/*! @name IMGSIZE - Image Resolution */
/*! @{ */

#define JPGDECWRP_IMGSIZE_IMG_HEIGHT_MASK        (0x3FFFU)
#define JPGDECWRP_IMGSIZE_IMG_HEIGHT_SHIFT       (0U)
/*! IMG_HEIGHT - Image Height */
#define JPGDECWRP_IMGSIZE_IMG_HEIGHT(x)          (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_IMGSIZE_IMG_HEIGHT_SHIFT)) & JPGDECWRP_IMGSIZE_IMG_HEIGHT_MASK)

#define JPGDECWRP_IMGSIZE_IMG_WIDTH_MASK         (0x3FFF0000U)
#define JPGDECWRP_IMGSIZE_IMG_WIDTH_SHIFT        (16U)
/*! IMG_WIDTH - Image Width */
#define JPGDECWRP_IMGSIZE_IMG_WIDTH(x)           (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_IMGSIZE_IMG_WIDTH_SHIFT)) & JPGDECWRP_IMGSIZE_IMG_WIDTH_MASK)
/*! @} */

/*! @name STM_CTRL - Bit Stream and Switching Control */
/*! @{ */

#define JPGDECWRP_STM_CTRL_PIXEL_PRECISION_MASK  (0x4U)
#define JPGDECWRP_STM_CTRL_PIXEL_PRECISION_SHIFT (2U)
/*! PIXEL_PRECISION - Pixel Precision
 *  0b0..8-bit
 *  0b1..12-bit
 */
#define JPGDECWRP_STM_CTRL_PIXEL_PRECISION(x)    (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_STM_CTRL_PIXEL_PRECISION_SHIFT)) & JPGDECWRP_STM_CTRL_PIXEL_PRECISION_MASK)

#define JPGDECWRP_STM_CTRL_IMAGE_FORMAT_MASK     (0x78U)
#define JPGDECWRP_STM_CTRL_IMAGE_FORMAT_SHIFT    (3U)
/*! IMAGE_FORMAT - Image Format
 *  0b0000..YUV420 (2-planar, Y at the first planar, and UV at the second planar)
 *  0b0001..YUV422 (1-planar in the YUYV sequence)
 *  0b0010..RGB (BGRBGR packed format)
 *  0b0011..YUV444 (first planar in the YUVYUV sequence)
 *  0b0100..Gray (Y8 or Y12) or single component
 *  0b0101..
 *  0b0110..ARGB
 */
#define JPGDECWRP_STM_CTRL_IMAGE_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_STM_CTRL_IMAGE_FORMAT_SHIFT)) & JPGDECWRP_STM_CTRL_IMAGE_FORMAT_MASK)

#define JPGDECWRP_STM_CTRL_BITBUF_PTR_CLR_MASK   (0x80U)
#define JPGDECWRP_STM_CTRL_BITBUF_PTR_CLR_SHIFT  (7U)
/*! BITBUF_PTR_CLR - Bit Buffer Pointer Clear
 *  0b0..Restores the bit stream buffer pointer from the save pointer.
 *  0b1..Clears the bit stream buffer pointer from the save pointer.
 */
#define JPGDECWRP_STM_CTRL_BITBUF_PTR_CLR(x)     (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_STM_CTRL_BITBUF_PTR_CLR_SHIFT)) & JPGDECWRP_STM_CTRL_BITBUF_PTR_CLR_MASK)

#define JPGDECWRP_STM_CTRL_AUTO_START_MASK       (0x100U)
#define JPGDECWRP_STM_CTRL_AUTO_START_SHIFT      (8U)
/*! AUTO_START - Auto Start
 *  0b0..Do not write 1 to CTRL[GO] in JPEGDEC.
 *  0b1..Writes 1 to CTRL[GO] in JPEGDEC.
 */
#define JPGDECWRP_STM_CTRL_AUTO_START(x)         (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_STM_CTRL_AUTO_START_SHIFT)) & JPGDECWRP_STM_CTRL_AUTO_START_MASK)
/*! @} */

/*! @name SLOT_STATUS - Bit Stream Status */
/*! @{ */

#define JPGDECWRP_SLOT_STATUS_STMBUF_HALF_MASK   (0x1U)
#define JPGDECWRP_SLOT_STATUS_STMBUF_HALF_SHIFT  (0U)
/*! STMBUF_HALF - Stream Buffer Half Flag
 *  0b0..The bit stream buffer pointer for the current slot has not passed half of the buffer size.
 *  0b1..The bit stream buffer pointer for the current slot passed half of the buffer size.
 *  0b0..No effect
 *  0b1..Clears the flag.
 */
#define JPGDECWRP_SLOT_STATUS_STMBUF_HALF(x)     (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPGDECWRP_SLOT_STATUS_STMBUF_HALF_MASK)

#define JPGDECWRP_SLOT_STATUS_STMBUF_RTND_MASK   (0x2U)
#define JPGDECWRP_SLOT_STATUS_STMBUF_RTND_SHIFT  (1U)
/*! STMBUF_RTND - Stream Buffer Returned Flag
 *  0b0..The bit stream buffer pointer for the current slot has not passed the top mark of the buffer.
 *  0b1..The bit stream buffer pointer for the current slot passed the top mark of the buffer.
 *  0b0..No effect
 *  0b1..Clears the flag.
 */
#define JPGDECWRP_SLOT_STATUS_STMBUF_RTND(x)     (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPGDECWRP_SLOT_STATUS_STMBUF_RTND_MASK)

#define JPGDECWRP_SLOT_STATUS_SWITCHED_IN_MASK   (0x4U)
#define JPGDECWRP_SLOT_STATUS_SWITCHED_IN_SHIFT  (2U)
/*! SWITCHED_IN - Switched In Flag
 *  0b0..The current slot is not switched in during context switching.
 *  0b1..The current slot is switched in during context switching.
 *  0b0..No effect
 *  0b1..Clears the flag.
 */
#define JPGDECWRP_SLOT_STATUS_SWITCHED_IN(x)     (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPGDECWRP_SLOT_STATUS_SWITCHED_IN_MASK)

#define JPGDECWRP_SLOT_STATUS_FRMDONE_MASK       (0x8U)
#define JPGDECWRP_SLOT_STATUS_FRMDONE_SHIFT      (3U)
/*! FRMDONE - Frame Done Flag
 *  0b0..Decoding is not completed.
 *  0b1..Decoding is completed.
 *  0b0..No effect
 *  0b1..Clears the flag.
 */
#define JPGDECWRP_SLOT_STATUS_FRMDONE(x)         (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_FRMDONE_SHIFT)) & JPGDECWRP_SLOT_STATUS_FRMDONE_MASK)

#define JPGDECWRP_SLOT_STATUS_DECERR_MASK        (0x100U)
#define JPGDECWRP_SLOT_STATUS_DECERR_SHIFT       (8U)
/*! DECERR - Decoding Error Flag
 *  0b0..No decoding error occurred.
 *  0b1..A decoding error occurred.
 *  0b0..No effect
 *  0b1..Clears the flag.
 */
#define JPGDECWRP_SLOT_STATUS_DECERR(x)          (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_DECERR_SHIFT)) & JPGDECWRP_SLOT_STATUS_DECERR_MASK)

#define JPGDECWRP_SLOT_STATUS_DES_RD_ERR_MASK    (0x200U)
#define JPGDECWRP_SLOT_STATUS_DES_RD_ERR_SHIFT   (9U)
/*! DES_RD_ERR - Descriptor Read Error Flag
 *  0b0..No descriptor read error occurred.
 *  0b1..A descriptor read error occurred.
 *  0b0..No effect
 *  0b1..Clears the flag.
 */
#define JPGDECWRP_SLOT_STATUS_DES_RD_ERR(x)      (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPGDECWRP_SLOT_STATUS_DES_RD_ERR_MASK)

#define JPGDECWRP_SLOT_STATUS_BIT_RD_ERR_MASK    (0x400U)
#define JPGDECWRP_SLOT_STATUS_BIT_RD_ERR_SHIFT   (10U)
/*! BIT_RD_ERR - Bit Read Error Flag
 *  0b0..No bit read error occurred.
 *  0b1..A bit read error occurred.
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define JPGDECWRP_SLOT_STATUS_BIT_RD_ERR(x)      (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_BIT_RD_ERR_SHIFT)) & JPGDECWRP_SLOT_STATUS_BIT_RD_ERR_MASK)

#define JPGDECWRP_SLOT_STATUS_PIXEL_WT_ERR_MASK  (0x800U)
#define JPGDECWRP_SLOT_STATUS_PIXEL_WT_ERR_SHIFT (11U)
/*! PIXEL_WT_ERR - Pixel Write Error Flag
 *  0b0..No pixel write error occurred.
 *  0b1..A pixel write error occurred.
 *  0b0..No effect
 *  0b1..Clears the flag.
 */
#define JPGDECWRP_SLOT_STATUS_PIXEL_WT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_PIXEL_WT_ERR_SHIFT)) & JPGDECWRP_SLOT_STATUS_PIXEL_WT_ERR_MASK)

#define JPGDECWRP_SLOT_STATUS_CUR_SLOT_MASK      (0x60000000U)
#define JPGDECWRP_SLOT_STATUS_CUR_SLOT_SHIFT     (29U)
/*! CUR_SLOT - Current Slot */
#define JPGDECWRP_SLOT_STATUS_CUR_SLOT(x)        (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPGDECWRP_SLOT_STATUS_CUR_SLOT_MASK)

#define JPGDECWRP_SLOT_STATUS_DEC_ONGOING_MASK   (0x80000000U)
#define JPGDECWRP_SLOT_STATUS_DEC_ONGOING_SHIFT  (31U)
/*! DEC_ONGOING - Decoding Ongoing
 *  0b0..Paused or stopped
 *  0b1..Ongoing
 */
#define JPGDECWRP_SLOT_STATUS_DEC_ONGOING(x)     (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_STATUS_DEC_ONGOING_SHIFT)) & JPGDECWRP_SLOT_STATUS_DEC_ONGOING_MASK)
/*! @} */

/* The count of JPGDECWRP_SLOT_STATUS */
#define JPGDECWRP_SLOT_STATUS_COUNT              (4U)

/*! @name SLOT_IRQ_EN - Bit Stream Interrupt Enable */
/*! @{ */

#define JPGDECWRP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK (0x1U)
#define JPGDECWRP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT (0U)
/*! STMBUF_HALF_IRQ_EN - Stream Buffer Half Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT)) & JPGDECWRP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK)

#define JPGDECWRP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK (0x2U)
#define JPGDECWRP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT (1U)
/*! STMBUF_RTND_IRQ_EN - Stream Buffer Returned Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT)) & JPGDECWRP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK)

#define JPGDECWRP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK (0x4U)
#define JPGDECWRP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT (2U)
/*! SWITCHED_IN_IRQ_EN - Switched In Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT)) & JPGDECWRP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK)

#define JPGDECWRP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK (0x8U)
#define JPGDECWRP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT (3U)
/*! FRMDONE_IRQ_EN - Frame Done Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_IRQ_EN_FRMDONE_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT)) & JPGDECWRP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK)

#define JPGDECWRP_SLOT_IRQ_EN_DECERR_IRQ_EN_MASK (0x100U)
#define JPGDECWRP_SLOT_IRQ_EN_DECERR_IRQ_EN_SHIFT (8U)
/*! DECERR_IRQ_EN - Decoding Error Status Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_IRQ_EN_DECERR_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_IRQ_EN_DECERR_IRQ_EN_SHIFT)) & JPGDECWRP_SLOT_IRQ_EN_DECERR_IRQ_EN_MASK)

#define JPGDECWRP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK (0x200U)
#define JPGDECWRP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT (9U)
/*! DES_RD_ERR_IRQ_EN - Descriptor Read Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT)) & JPGDECWRP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK)

#define JPGDECWRP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_MASK (0x400U)
#define JPGDECWRP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_SHIFT (10U)
/*! BIT_RD_ERR_IRQ_EN - Bit Read Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_SHIFT)) & JPGDECWRP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_MASK)

#define JPGDECWRP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_MASK (0x800U)
#define JPGDECWRP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_SHIFT (11U)
/*! PIXEL_WT_ERR_IRQ_EN - Pixel Write Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_SHIFT)) & JPGDECWRP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_MASK)
/*! @} */

/* The count of JPGDECWRP_SLOT_IRQ_EN */
#define JPGDECWRP_SLOT_IRQ_EN_COUNT              (4U)

/*! @name SLOT_BUF_PTR - Bit Stream Buffer Pointer */
/*! @{ */

#define JPGDECWRP_SLOT_BUF_PTR_STMBUF_PTR_MASK   (0xFFFFFFFFU)
#define JPGDECWRP_SLOT_BUF_PTR_STMBUF_PTR_SHIFT  (0U)
/*! STMBUF_PTR - Stream Buffer Pointer */
#define JPGDECWRP_SLOT_BUF_PTR_STMBUF_PTR(x)     (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_BUF_PTR_STMBUF_PTR_SHIFT)) & JPGDECWRP_SLOT_BUF_PTR_STMBUF_PTR_MASK)
/*! @} */

/* The count of JPGDECWRP_SLOT_BUF_PTR */
#define JPGDECWRP_SLOT_BUF_PTR_COUNT             (4U)

/*! @name SLOT_CUR_DESCPT_PTR - Current Descriptors */
/*! @{ */

#define JPGDECWRP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU)
#define JPGDECWRP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U)
/*! CUR_DESCPT_PRT - Current Decoding Descriptor Pointer */
#define JPGDECWRP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPGDECWRP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK)
/*! @} */

/* The count of JPGDECWRP_SLOT_CUR_DESCPT_PTR */
#define JPGDECWRP_SLOT_CUR_DESCPT_PTR_COUNT      (4U)

/*! @name SLOT_NXT_DESCPT_PTR - Next Descriptors */
/*! @{ */

#define JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK (0x1U)
#define JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT (0U)
/*! NXT_DESCPT_EN - Next Stream Descriptor Pointer Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT)) & JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK)

#define JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_MASK (0xFFFFFFFCU)
#define JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_SHIFT (2U)
/*! NXT_DESCPT_PTR - Next Descriptor Pointer */
#define JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR(x) (((uint32_t)(((uint32_t)(x)) << JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_SHIFT)) & JPGDECWRP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_MASK)
/*! @} */

/* The count of JPGDECWRP_SLOT_NXT_DESCPT_PTR */
#define JPGDECWRP_SLOT_NXT_DESCPT_PTR_COUNT      (4U)


/*!
 * @}
 */ /* end of group JPGDECWRP_Register_Masks */


/* JPGDECWRP - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral JPGDECWRP base address */
  #define JPGDECWRP_BASE                           (0x500A6000u)
  /** Peripheral JPGDECWRP base address */
  #define JPGDECWRP_BASE_NS                        (0x400A6000u)
  /** Peripheral JPGDECWRP base pointer */
  #define JPGDECWRP                                ((JPGDECWRP_Type *)JPGDECWRP_BASE)
  /** Peripheral JPGDECWRP base pointer */
  #define JPGDECWRP_NS                             ((JPGDECWRP_Type *)JPGDECWRP_BASE_NS)
  /** Array initializer of JPGDECWRP peripheral base addresses */
  #define JPGDECWRP_BASE_ADDRS                     { JPGDECWRP_BASE }
  /** Array initializer of JPGDECWRP peripheral base pointers */
  #define JPGDECWRP_BASE_PTRS                      { JPGDECWRP }
  /** Array initializer of JPGDECWRP peripheral base addresses */
  #define JPGDECWRP_BASE_ADDRS_NS                  { JPGDECWRP_BASE_NS }
  /** Array initializer of JPGDECWRP peripheral base pointers */
  #define JPGDECWRP_BASE_PTRS_NS                   { JPGDECWRP_NS }
#else
  /** Peripheral JPGDECWRP base address */
  #define JPGDECWRP_BASE                           (0x400A6000u)
  /** Peripheral JPGDECWRP base pointer */
  #define JPGDECWRP                                ((JPGDECWRP_Type *)JPGDECWRP_BASE)
  /** Array initializer of JPGDECWRP peripheral base addresses */
  #define JPGDECWRP_BASE_ADDRS                     { JPGDECWRP_BASE }
  /** Array initializer of JPGDECWRP peripheral base pointers */
  #define JPGDECWRP_BASE_PTRS                      { JPGDECWRP }
#endif

/*!
 * @}
 */ /* end of group JPGDECWRP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LCDIF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
 * @{
 */

/** LCDIF - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[8228];
  __IO uint32_t FRAMEBUFFERCONFIG0;                /**< Frame Buffer Configuration, offset: 0x2024 */
  __IO uint32_t FRAMEBUFFERADDRESS0;               /**< Frame Buffer Base Address, offset: 0x2028 */
  __IO uint32_t FRAMEBUFFERSTRIDE0;                /**< Frame Buffer Stride, offset: 0x202C */
       uint8_t RESERVED_1[4];
  __IO uint32_t DCTILEINCFG0;                      /**< Tile Input Configuration, offset: 0x2034 */
  __IO uint32_t DCTILEUVFRAMEBUFFERADR0;           /**< Frame Buffer Tiled UV Base Address, offset: 0x2038 */
  __IO uint32_t DCTILEUVFRAMEBUFFERSTR0;           /**< Frame Buffer Tiled UV Stride, offset: 0x203C */
       uint8_t RESERVED_2[24];
  __IO uint32_t FRAMEBUFFERBACKGROUND;             /**< Frame Buffer Background, offset: 0x2058 */
  __IO uint32_t FRAMEBUFFERCOLORKEY;               /**< Frame Buffer Color Keying Start Address, offset: 0x205C */
  __IO uint32_t FRAMEBUFFERCOLORKEYHIGH;           /**< Frame Buffer Color Key End Address, offset: 0x2060 */
  __IO uint32_t FRAMEBUFFERCLEARVALUE;             /**< Frame Buffer Clear Value, offset: 0x2064 */
  __IO uint32_t VIDEOTL;                           /**< Video Top Left Coordinate, offset: 0x2068 */
  __IO uint32_t FRAMEBUFFERSIZE;                   /**< Frame Buffer Size, offset: 0x206C */
  __IO uint32_t VIDEOGLOBALALPHA;                  /**< Video Global Alpha, offset: 0x2070 */
  __IO uint32_t BLENDSTACKORDER;                   /**< Blend Stack Order, offset: 0x2074 */
  __IO uint32_t VIDEOALPHABLENDCONFIG;             /**< Alpha Blending Configuration, offset: 0x2078 */
  __IO uint32_t OVERLAYCONFIG;                     /**< Overlay Configuration, offset: 0x207C */
  __IO uint32_t OVERLAYADDRESS;                    /**< Overlay Address, offset: 0x2080 */
  __IO uint32_t OVERLAYSTRIDE;                     /**< Overlay Stride, offset: 0x2084 */
  __IO uint32_t DCOVERLAYTILEINCFG;                /**< Tile Input Configuration, offset: 0x2088 */
  __IO uint32_t DCTILEUVOVERLAYADR;                /**< Tile Uv Overlay Address, offset: 0x208C */
  __IO uint32_t DCTILEUVOVERLAYSTR;                /**< Tile Uv Overlay Stride, offset: 0x2090 */
  __IO uint32_t OVERLAYTL;                         /**< Overlay Top Left, offset: 0x2094 */
  __IO uint32_t OVERLAYSIZE;                       /**< Overlay Size, offset: 0x2098 */
  __IO uint32_t OVERLAYCOLORKEY;                   /**< Overlay Color Keying Start Address, offset: 0x209C */
  __IO uint32_t OVERLAYCOLORKEYHIGH;               /**< Overlay Color Keying End Address, offset: 0x20A0 */
  __IO uint32_t OVERLAYALPHABLENDCONFIG;           /**< Overlay Alpha Blending Configuration, offset: 0x20A4 */
  __IO uint32_t OVERLAYGLOBALALPHA;                /**< Overlay Global Alpha, offset: 0x20A8 */
  __IO uint32_t OVERLAYCLEARVALUE;                 /**< Overlay Clear Value, offset: 0x20AC */
  __IO uint32_t OVERLAYCONFIG1;                    /**< Overlay Layer 1 Configuration, offset: 0x20B0 */
  __IO uint32_t OVERLAYADDRESS1;                   /**< Overlay Layer 1 Address, offset: 0x20B4 */
  __IO uint32_t OVERLAYSTRIDE1;                    /**< Overlay Layer 1 Stride, offset: 0x20B8 */
  __IO uint32_t OVERLAYTL1;                        /**< Overlay Layer 1 Top Left, offset: 0x20BC */
  __IO uint32_t OVERLAYSIZE1;                      /**< Overlay Layer 1 Size, offset: 0x20C0 */
  __IO uint32_t OVERLAYCOLORKEY1;                  /**< Overlay Layer 1 Color Keying Start Address, offset: 0x20C4 */
  __IO uint32_t OVERLAYCOLORKEYHIGH1;              /**< Overlay Layer 1 Color Keying End Address, offset: 0x20C8 */
  __IO uint32_t OVERLAYALPHABLENDCONFIG1;          /**< Overlay Layer 1 Alpha Blending Configuration, offset: 0x20CC */
  __IO uint32_t OVERLAYGLOBALALPHA1;               /**< Overlay Layer 1 Global Alpha, offset: 0x20D0 */
  __IO uint32_t OVERLAYCLEARVALUE1;                /**< Overlay Layer 1 Clear Value, offset: 0x20D4 */
       uint8_t RESERVED_3[8];
  __IO uint32_t DISPLAYDITHERTABLELOW0;            /**< Dither Lookup Table Low Threshold, offset: 0x20E0 */
  __IO uint32_t DISPLAYDITHERTABLEHIGH0;           /**< Dither Lookup Table High Threshold, offset: 0x20E4 */
  __IO uint32_t PANELCONFIG0;                      /**< Panel Configuration, offset: 0x20E8 */
  __IO uint32_t PANELCONTROL;                      /**< Panel Control, offset: 0x20EC */
  __IO uint32_t PANELFUNCTION;                     /**< Panel Function, offset: 0x20F0 */
  __O  uint32_t PANELWORKING;                      /**< Panel Working, offset: 0x20F4 */
  __I  uint32_t PANELSTATE;                        /**< Panel State, offset: 0x20F8 */
       uint8_t RESERVED_4[4];
  __IO uint32_t HDISPLAY0;                         /**< Horizontal Display Total and Visible Pixel Count, offset: 0x2100 */
  __IO uint32_t HSYNC0;                            /**< Horizontal Sync Counter, offset: 0x2104 */
       uint8_t RESERVED_5[8];
  __IO uint32_t VDISPLAY0;                         /**< Vertical Total and Visible Pixel Count, offset: 0x2110 */
  __IO uint32_t VSYNC0;                            /**< Vertical Sync Counter, offset: 0x2114 */
  __I  uint32_t DISPLAYCURRENTLOCATION0;           /**< Display Current Location, offset: 0x2118 */
  __O  uint32_t GAMMAINDEX0;                       /**< Gamma Index, offset: 0x211C */
  __O  uint32_t GAMMADATA0;                        /**< Gamma Data, offset: 0x2120 */
  __IO uint32_t CURSORCONFIG;                      /**< Cursor Configuration, offset: 0x2124 */
  __IO uint32_t CURSORADDRESS;                     /**< Cursor Base Address, offset: 0x2128 */
  __IO uint32_t CURSORLOCATION;                    /**< Cursor Location, offset: 0x212C */
  __IO uint32_t CURSORBACKGROUND;                  /**< Cursor Background Color, offset: 0x2130 */
  __IO uint32_t CURSORFOREGROUND;                  /**< Cursor Foreground Color, offset: 0x2134 */
  __I  uint32_t DISPLAYINTR;                       /**< Display Interrupt, offset: 0x2138 */
  __IO uint32_t DISPLAYINTRENABLE;                 /**< Display Interrupt Enable, offset: 0x213C */
  __IO uint32_t DBICONFIG0;                        /**< DBI Configuration, offset: 0x2140 */
  __O  uint32_t DBIIFRESET0;                       /**< DBI Interface Reset, offset: 0x2144 */
  __IO uint32_t DBIWRCHAR10;                       /**< DBI Write AC Characteristics 1, offset: 0x2148 */
  __IO uint32_t DBIWRCHAR20;                       /**< DBI Write AC Characteristics 2, offset: 0x214C */
  __O  uint32_t DBICMD0;                           /**< DBI Command Control, offset: 0x2150 */
  __IO uint32_t DPICONFIG0;                        /**< DPI Configuration, offset: 0x2154 */
       uint8_t RESERVED_6[8];
  __IO uint32_t SRCCONFIGENDIAN;                   /**< Source Endian Configuration, offset: 0x2160 */
  __O  uint32_t SOFTRESET;                         /**< Soft Reset, offset: 0x2164 */
  __IO uint32_t DCCONTROL;                         /**< Display Controller Control, offset: 0x2168 */
       uint8_t RESERVED_7[52];
  __IO uint32_t LAYERCLOCKGATE;                    /**< Layer Clock Gating, offset: 0x21A0 */
} LCDIF_Type;

/* ----------------------------------------------------------------------------
   -- LCDIF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
 * @{
 */

/*! @name FRAMEBUFFERCONFIG0 - Frame Buffer Configuration */
/*! @{ */

#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT_MASK     (0x7U)
#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT_SHIFT    (0U)
/*! FORMAT - Frame Buffer Format
 *  0b000..None; no frame buffer exists and LCDIF does not produce any output
 *  0b001..A4R4G4B4
 *  0b010..A1R5G5B5
 *  0b011..R5G6B5
 *  0b100..A8R8G8B8
 *  0b101..R8G8B8
 *  0b110..A8R5G6B5
 *  *..
 */
#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_FORMAT_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_FORMAT_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_ENABLE_MASK     (0x8U)
#define LCDIF_FRAMEBUFFERCONFIG0_ENABLE_SHIFT    (3U)
/*! ENABLE - Enable Layer
 *  0b0..Disable
 *  0b1..Enable
 */
#define LCDIF_FRAMEBUFFERCONFIG0_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_ENABLE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_ENABLE_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_CLEAR_EN_MASK   (0x20U)
#define LCDIF_FRAMEBUFFERCONFIG0_CLEAR_EN_SHIFT  (5U)
/*! CLEAR_EN - Enable Clear
 *  0b0..Disable
 *  0b1..Enable
 */
#define LCDIF_FRAMEBUFFERCONFIG0_CLEAR_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_CLEAR_EN_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_CLEAR_EN_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_COLOR_KEY_EN_MASK (0x400U)
#define LCDIF_FRAMEBUFFERCONFIG0_COLOR_KEY_EN_SHIFT (10U)
/*! COLOR_KEY_EN - Enable Color Keying
 *  0b0..Disable
 *  0b1..Enable
 */
#define LCDIF_FRAMEBUFFERCONFIG0_COLOR_KEY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_COLOR_KEY_EN_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_COLOR_KEY_EN_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_SWIZZLE_MASK    (0x60000U)
#define LCDIF_FRAMEBUFFERCONFIG0_SWIZZLE_SHIFT   (17U)
/*! SWIZZLE - Swizzle for RGB
 *  0b00..ARGB
 *  0b01..RGBA
 *  0b10..ABGR
 *  0b11..BGRA
 */
#define LCDIF_FRAMEBUFFERCONFIG0_SWIZZLE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_SWIZZLE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_SWIZZLE_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_UV_SWIZZLE_MASK (0x80000U)
#define LCDIF_FRAMEBUFFERCONFIG0_UV_SWIZZLE_SHIFT (19U)
/*! UV_SWIZZLE - Swizzle for UV */
#define LCDIF_FRAMEBUFFERCONFIG0_UV_SWIZZLE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_UV_SWIZZLE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_UV_SWIZZLE_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_DEC_MODE_MASK   (0xE00000U)
#define LCDIF_FRAMEBUFFERCONFIG0_DEC_MODE_SHIFT  (21U)
/*! DEC_MODE - Decompression Mode
 *  0b000..Decompression disabled
 *  0b001..Non-Subsample
 *  0b010..Horizontal Subsample
 *  0b011..Horizontal and Vertical Subsample
 *  0b100..ETC2
 *  *..
 */
#define LCDIF_FRAMEBUFFERCONFIG0_DEC_MODE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_DEC_MODE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_DEC_MODE_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_ROT_ANGLE_MASK  (0x7000000U)
#define LCDIF_FRAMEBUFFERCONFIG0_ROT_ANGLE_SHIFT (24U)
/*! ROT_ANGLE - Rotation Angle
 *  0b000..Sets the rotation angle to 0 degree.
 *  0b010..Sets the rotation angle to 180 degree.
 *  0b100..Flips horizontal
 *  0b101..Flips vertical
 *  *..
 */
#define LCDIF_FRAMEBUFFERCONFIG0_ROT_ANGLE(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_ROT_ANGLE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_ROT_ANGLE_MASK)
/*! @} */

/*! @name FRAMEBUFFERADDRESS0 - Frame Buffer Base Address */
/*! @{ */

#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_MASK   (0xFFFFFFFFU)
#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_SHIFT  (0U)
/*! ADDRESS - Starting Address */
#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_SHIFT)) & LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_MASK)
/*! @} */

/*! @name FRAMEBUFFERSTRIDE0 - Frame Buffer Stride */
/*! @{ */

#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_MASK     (0x1FFFFU)
#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_SHIFT    (0U)
/*! STRIDE - Frame Buffer Stride */
#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_SHIFT)) & LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_MASK)
/*! @} */

/*! @name DCTILEINCFG0 - Tile Input Configuration */
/*! @{ */

#define LCDIF_DCTILEINCFG0_TILE_FORMAT_MASK      (0x3U)
#define LCDIF_DCTILEINCFG0_TILE_FORMAT_SHIFT     (0U)
/*! TILE_FORMAT - Tile Input Format
 *  0b00..No tile input. See DcTileInCfg0[TILE_FORMAT1].
 *  0b01..ARGB8888
 *  0b10..YUY2
 *  0b11..NV12
 */
#define LCDIF_DCTILEINCFG0_TILE_FORMAT(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_TILE_FORMAT_SHIFT)) & LCDIF_DCTILEINCFG0_TILE_FORMAT_MASK)

#define LCDIF_DCTILEINCFG0_YUV_STANDARD_MASK     (0x4U)
#define LCDIF_DCTILEINCFG0_YUV_STANDARD_SHIFT    (2U)
/*! YUV_STANDARD - YUV Standard
 *  0b0..BT601
 *  0b1..BT709
 */
#define LCDIF_DCTILEINCFG0_YUV_STANDARD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_YUV_STANDARD_SHIFT)) & LCDIF_DCTILEINCFG0_YUV_STANDARD_MASK)

#define LCDIF_DCTILEINCFG0_TILE_FORMAT1_MASK     (0x18U)
#define LCDIF_DCTILEINCFG0_TILE_FORMAT1_SHIFT    (3U)
/*! TILE_FORMAT1 - Tile Format 1 */
#define LCDIF_DCTILEINCFG0_TILE_FORMAT1(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_TILE_FORMAT1_SHIFT)) & LCDIF_DCTILEINCFG0_TILE_FORMAT1_MASK)
/*! @} */

/*! @name DCTILEUVFRAMEBUFFERADR0 - Frame Buffer Tiled UV Base Address */
/*! @{ */

#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_MASK (0xFFFFFFFFU)
#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_SHIFT (0U)
/*! ADDRESS - Base Address */
#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_SHIFT)) & LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_MASK)
/*! @} */

/*! @name DCTILEUVFRAMEBUFFERSTR0 - Frame Buffer Tiled UV Stride */
/*! @{ */

#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_MASK (0xFFFFU)
#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_SHIFT (0U)
/*! STRIDE - Stride */
#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_SHIFT)) & LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_MASK)
/*! @} */

/*! @name FRAMEBUFFERBACKGROUND - Frame Buffer Background */
/*! @{ */

#define LCDIF_FRAMEBUFFERBACKGROUND_BLUE_MASK    (0xFFU)
#define LCDIF_FRAMEBUFFERBACKGROUND_BLUE_SHIFT   (0U)
/*! BLUE - Blue */
#define LCDIF_FRAMEBUFFERBACKGROUND_BLUE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERBACKGROUND_BLUE_SHIFT)) & LCDIF_FRAMEBUFFERBACKGROUND_BLUE_MASK)

#define LCDIF_FRAMEBUFFERBACKGROUND_GREEN_MASK   (0xFF00U)
#define LCDIF_FRAMEBUFFERBACKGROUND_GREEN_SHIFT  (8U)
/*! GREEN - Green */
#define LCDIF_FRAMEBUFFERBACKGROUND_GREEN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERBACKGROUND_GREEN_SHIFT)) & LCDIF_FRAMEBUFFERBACKGROUND_GREEN_MASK)

#define LCDIF_FRAMEBUFFERBACKGROUND_RED_MASK     (0xFF0000U)
#define LCDIF_FRAMEBUFFERBACKGROUND_RED_SHIFT    (16U)
/*! RED - Red */
#define LCDIF_FRAMEBUFFERBACKGROUND_RED(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERBACKGROUND_RED_SHIFT)) & LCDIF_FRAMEBUFFERBACKGROUND_RED_MASK)

#define LCDIF_FRAMEBUFFERBACKGROUND_ALPHA_MASK   (0xFF000000U)
#define LCDIF_FRAMEBUFFERBACKGROUND_ALPHA_SHIFT  (24U)
/*! ALPHA - Alpha */
#define LCDIF_FRAMEBUFFERBACKGROUND_ALPHA(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERBACKGROUND_ALPHA_SHIFT)) & LCDIF_FRAMEBUFFERBACKGROUND_ALPHA_MASK)
/*! @} */

/*! @name FRAMEBUFFERCOLORKEY - Frame Buffer Color Keying Start Address */
/*! @{ */

#define LCDIF_FRAMEBUFFERCOLORKEY_BLUE_MASK      (0xFFU)
#define LCDIF_FRAMEBUFFERCOLORKEY_BLUE_SHIFT     (0U)
/*! BLUE - Blue */
#define LCDIF_FRAMEBUFFERCOLORKEY_BLUE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCOLORKEY_BLUE_SHIFT)) & LCDIF_FRAMEBUFFERCOLORKEY_BLUE_MASK)

#define LCDIF_FRAMEBUFFERCOLORKEY_GREEN_MASK     (0xFF00U)
#define LCDIF_FRAMEBUFFERCOLORKEY_GREEN_SHIFT    (8U)
/*! GREEN - Green */
#define LCDIF_FRAMEBUFFERCOLORKEY_GREEN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCOLORKEY_GREEN_SHIFT)) & LCDIF_FRAMEBUFFERCOLORKEY_GREEN_MASK)

#define LCDIF_FRAMEBUFFERCOLORKEY_RED_MASK       (0xFF0000U)
#define LCDIF_FRAMEBUFFERCOLORKEY_RED_SHIFT      (16U)
/*! RED - Red */
#define LCDIF_FRAMEBUFFERCOLORKEY_RED(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCOLORKEY_RED_SHIFT)) & LCDIF_FRAMEBUFFERCOLORKEY_RED_MASK)

#define LCDIF_FRAMEBUFFERCOLORKEY_ALPHA_MASK     (0xFF000000U)
#define LCDIF_FRAMEBUFFERCOLORKEY_ALPHA_SHIFT    (24U)
/*! ALPHA - Alpha */
#define LCDIF_FRAMEBUFFERCOLORKEY_ALPHA(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCOLORKEY_ALPHA_SHIFT)) & LCDIF_FRAMEBUFFERCOLORKEY_ALPHA_MASK)
/*! @} */

/*! @name FRAMEBUFFERCOLORKEYHIGH - Frame Buffer Color Key End Address */
/*! @{ */

#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_BLUE_MASK  (0xFFU)
#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_BLUE_SHIFT (0U)
/*! BLUE - Blue */
#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_BLUE(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCOLORKEYHIGH_BLUE_SHIFT)) & LCDIF_FRAMEBUFFERCOLORKEYHIGH_BLUE_MASK)

#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_GREEN_MASK (0xFF00U)
#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_GREEN_SHIFT (8U)
/*! GREEN - Green */
#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_GREEN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCOLORKEYHIGH_GREEN_SHIFT)) & LCDIF_FRAMEBUFFERCOLORKEYHIGH_GREEN_MASK)

#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_RED_MASK   (0xFF0000U)
#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_RED_SHIFT  (16U)
/*! RED - Red */
#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_RED(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCOLORKEYHIGH_RED_SHIFT)) & LCDIF_FRAMEBUFFERCOLORKEYHIGH_RED_MASK)

#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_ALPHA_MASK (0xFF000000U)
#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_ALPHA_SHIFT (24U)
/*! ALPHA - Alpha */
#define LCDIF_FRAMEBUFFERCOLORKEYHIGH_ALPHA(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCOLORKEYHIGH_ALPHA_SHIFT)) & LCDIF_FRAMEBUFFERCOLORKEYHIGH_ALPHA_MASK)
/*! @} */

/*! @name FRAMEBUFFERCLEARVALUE - Frame Buffer Clear Value */
/*! @{ */

#define LCDIF_FRAMEBUFFERCLEARVALUE_BLUE_MASK    (0xFFU)
#define LCDIF_FRAMEBUFFERCLEARVALUE_BLUE_SHIFT   (0U)
/*! BLUE - Blue */
#define LCDIF_FRAMEBUFFERCLEARVALUE_BLUE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCLEARVALUE_BLUE_SHIFT)) & LCDIF_FRAMEBUFFERCLEARVALUE_BLUE_MASK)

#define LCDIF_FRAMEBUFFERCLEARVALUE_GREEN_MASK   (0xFF00U)
#define LCDIF_FRAMEBUFFERCLEARVALUE_GREEN_SHIFT  (8U)
/*! GREEN - Green */
#define LCDIF_FRAMEBUFFERCLEARVALUE_GREEN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCLEARVALUE_GREEN_SHIFT)) & LCDIF_FRAMEBUFFERCLEARVALUE_GREEN_MASK)

#define LCDIF_FRAMEBUFFERCLEARVALUE_RED_MASK     (0xFF0000U)
#define LCDIF_FRAMEBUFFERCLEARVALUE_RED_SHIFT    (16U)
/*! RED - Red */
#define LCDIF_FRAMEBUFFERCLEARVALUE_RED(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCLEARVALUE_RED_SHIFT)) & LCDIF_FRAMEBUFFERCLEARVALUE_RED_MASK)

#define LCDIF_FRAMEBUFFERCLEARVALUE_ALPHA_MASK   (0xFF000000U)
#define LCDIF_FRAMEBUFFERCLEARVALUE_ALPHA_SHIFT  (24U)
/*! ALPHA - Alpha */
#define LCDIF_FRAMEBUFFERCLEARVALUE_ALPHA(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCLEARVALUE_ALPHA_SHIFT)) & LCDIF_FRAMEBUFFERCLEARVALUE_ALPHA_MASK)
/*! @} */

/*! @name VIDEOTL - Video Top Left Coordinate */
/*! @{ */

#define LCDIF_VIDEOTL_X_MASK                     (0xFFFU)
#define LCDIF_VIDEOTL_X_SHIFT                    (0U)
/*! X - Left Boundary */
#define LCDIF_VIDEOTL_X(x)                       (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOTL_X_SHIFT)) & LCDIF_VIDEOTL_X_MASK)

#define LCDIF_VIDEOTL_Y_MASK                     (0xFFF0000U)
#define LCDIF_VIDEOTL_Y_SHIFT                    (16U)
/*! Y - Top Boundary */
#define LCDIF_VIDEOTL_Y(x)                       (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOTL_Y_SHIFT)) & LCDIF_VIDEOTL_Y_MASK)
/*! @} */

/*! @name FRAMEBUFFERSIZE - Frame Buffer Size */
/*! @{ */

#define LCDIF_FRAMEBUFFERSIZE_WIDTH_MASK         (0xFFFU)
#define LCDIF_FRAMEBUFFERSIZE_WIDTH_SHIFT        (0U)
/*! WIDTH - Video Width */
#define LCDIF_FRAMEBUFFERSIZE_WIDTH(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERSIZE_WIDTH_SHIFT)) & LCDIF_FRAMEBUFFERSIZE_WIDTH_MASK)

#define LCDIF_FRAMEBUFFERSIZE_HEIGHT_MASK        (0xFFF0000U)
#define LCDIF_FRAMEBUFFERSIZE_HEIGHT_SHIFT       (16U)
/*! HEIGHT - Video Height */
#define LCDIF_FRAMEBUFFERSIZE_HEIGHT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERSIZE_HEIGHT_SHIFT)) & LCDIF_FRAMEBUFFERSIZE_HEIGHT_MASK)
/*! @} */

/*! @name VIDEOGLOBALALPHA - Video Global Alpha */
/*! @{ */

#define LCDIF_VIDEOGLOBALALPHA_SRC_ALPHA_MASK    (0xFFU)
#define LCDIF_VIDEOGLOBALALPHA_SRC_ALPHA_SHIFT   (0U)
/*! SRC_ALPHA - Source Alpha */
#define LCDIF_VIDEOGLOBALALPHA_SRC_ALPHA(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOGLOBALALPHA_SRC_ALPHA_SHIFT)) & LCDIF_VIDEOGLOBALALPHA_SRC_ALPHA_MASK)

#define LCDIF_VIDEOGLOBALALPHA_DST_ALPHA_MASK    (0xFF00U)
#define LCDIF_VIDEOGLOBALALPHA_DST_ALPHA_SHIFT   (8U)
/*! DST_ALPHA - Destination Alpha */
#define LCDIF_VIDEOGLOBALALPHA_DST_ALPHA(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOGLOBALALPHA_DST_ALPHA_SHIFT)) & LCDIF_VIDEOGLOBALALPHA_DST_ALPHA_MASK)
/*! @} */

/*! @name BLENDSTACKORDER - Blend Stack Order */
/*! @{ */

#define LCDIF_BLENDSTACKORDER_ORDER_MASK         (0x7U)
#define LCDIF_BLENDSTACKORDER_ORDER_SHIFT        (0U)
/*! ORDER - Stack Order
 *  0b000..In the order of VG, Overlay 0 and Overlay 1 layers.
 *  0b001..In the order of VG, Overlay 1 and Overlay 0 layers.
 *  0b010..In the order of Overlay 0, VG and Overlay 1 layers.
 *  0b011..In the order of Overlay 0, Overlay 1, and VG layers.
 *  0b100..In the order of Overlay 1, VG and Overlay 0 layers.
 *  0b101..In the order of Overlay 1, Overlay 0, and VG layers.
 */
#define LCDIF_BLENDSTACKORDER_ORDER(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_BLENDSTACKORDER_ORDER_SHIFT)) & LCDIF_BLENDSTACKORDER_ORDER_MASK)
/*! @} */

/*! @name VIDEOALPHABLENDCONFIG - Alpha Blending Configuration */
/*! @{ */

#define LCDIF_VIDEOALPHABLENDCONFIG_ALPHA_BLEND_MASK (0x1U)
#define LCDIF_VIDEOALPHABLENDCONFIG_ALPHA_BLEND_SHIFT (0U)
/*! ALPHA_BLEND - Alpha Blending
 *  0b0..Disables alpha blending for video.
 *  0b1..Enables alpha blending for video.
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_ALPHA_BLEND(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_ALPHA_BLEND_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_ALPHA_BLEND_MASK)

#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_MODE_MASK (0x2U)
#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_MODE_SHIFT (1U)
/*! SRC_ALPHA_MODE - Source Alpha Mode
 *  0b0..Normal source alpha mode
 *  0b1..Inversed alpha mode if the internal alpha rule needs to be followed
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_MODE_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_MODE_MASK)

#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE_MASK (0x18U)
#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE_SHIFT (3U)
/*! SRC_GLOBAL_ALPHA_MODE - Source Global Alpha Mode
 *  0b00..Normal source alpha mode
 *  0b01..Global source alpha mode
 *  0b10..Scaled (by the global alpha value) source alpha mode
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE_MASK)

#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_BLENDING_MODE_MASK (0xC0U)
#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_BLENDING_MODE_SHIFT (6U)
/*! SRC_BLENDING_MODE - Source Blending Mode
 *  0b00..Each component of the color is multiplied by (0, 0, 0,0).
 *  0b01..Each component of the color is multiplied by (1, 1, 1,1).
 *  0b10..Normal as the result color is the source color
 *  0b11..Not affected by the color of the underlying pixel
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_BLENDING_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_SRC_BLENDING_MODE_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_SRC_BLENDING_MODE_MASK)

#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_FACTOR_MASK (0x100U)
#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_FACTOR_SHIFT (8U)
/*! SRC_ALPHA_FACTOR - Source Alpha Factor
 *  0b0..Do not generate the blending factor.
 *  0b1..Generates the blending factor.
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_FACTOR_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_SRC_ALPHA_FACTOR_MASK)

#define LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_MODE_MASK (0x200U)
#define LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_MODE_SHIFT (9U)
/*! DST_ALPHA_MODE - Destination Alpha Mode
 *  0b0..Normal destination alpha mode
 *  0b1..Inversed alpha mode if the internal alpha rule needs to be followed
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_MODE_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_MODE_MASK)

#define LCDIF_VIDEOALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE_MASK (0xC00U)
#define LCDIF_VIDEOALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE_SHIFT (10U)
/*! DST_GLOBAL_ALPHA_MODE - Destination Global Alpha Mode
 *  0b00..Normal destination alpha mode
 *  0b01..Global destination alpha mode
 *  0b10..Scaled (by the global alpha value) destination alpha mode
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE_MASK)

#define LCDIF_VIDEOALPHABLENDCONFIG_DST_BLENDING_MODE_MASK (0x6000U)
#define LCDIF_VIDEOALPHABLENDCONFIG_DST_BLENDING_MODE_SHIFT (13U)
/*! DST_BLENDING_MODE - Destination Alpha Blending Mode
 *  0b00..Each component of the color is multiplied by (0, 0, 0,0).
 *  0b01..Each component of the color is multiplied by (1, 1, 1,1).
 *  0b10..Normal as the result color is the destination color
 *  0b11..Not affected by the color of the underlying pixel
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_DST_BLENDING_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_DST_BLENDING_MODE_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_DST_BLENDING_MODE_MASK)

#define LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_FACTOR_MASK (0x8000U)
#define LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_FACTOR_SHIFT (15U)
/*! DST_ALPHA_FACTOR - Destination Alpha Factor
 *  0b0..Do not generate the blending factor for destination alpha.
 *  0b1..Generates the blending factor for destination alpha.
 */
#define LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_FACTOR_SHIFT)) & LCDIF_VIDEOALPHABLENDCONFIG_DST_ALPHA_FACTOR_MASK)
/*! @} */

/*! @name OVERLAYCONFIG - Overlay Configuration */
/*! @{ */

#define LCDIF_OVERLAYCONFIG_FORMAT_MASK          (0x7U)
#define LCDIF_OVERLAYCONFIG_FORMAT_SHIFT         (0U)
/*! FORMAT - Overlay Format
 *  0b000..No overlay
 *  0b001..Overlay format is A4R4G4B4.
 *  0b010..Overlay format is A1R5G5B5.
 *  0b011..Overlay format is R5G6B5.
 *  0b100..Overlay format is A8R8G8B8.
 *  0b101..Overlay format is A8R5G6B5.
 */
#define LCDIF_OVERLAYCONFIG_FORMAT(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG_FORMAT_SHIFT)) & LCDIF_OVERLAYCONFIG_FORMAT_MASK)

#define LCDIF_OVERLAYCONFIG_ENABLE_MASK          (0x8U)
#define LCDIF_OVERLAYCONFIG_ENABLE_SHIFT         (3U)
/*! ENABLE - Enable
 *  0b0..Disables this overlay layer.
 *  0b1..Enables this overlay layer.
 */
#define LCDIF_OVERLAYCONFIG_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG_ENABLE_SHIFT)) & LCDIF_OVERLAYCONFIG_ENABLE_MASK)

#define LCDIF_OVERLAYCONFIG_CLEAR_EN_MASK        (0x20U)
#define LCDIF_OVERLAYCONFIG_CLEAR_EN_SHIFT       (5U)
/*! CLEAR_EN - Clear
 *  0b0..Disables clearing the overlay layer.
 *  0b1..Enables clearing the overlay layer.
 */
#define LCDIF_OVERLAYCONFIG_CLEAR_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG_CLEAR_EN_SHIFT)) & LCDIF_OVERLAYCONFIG_CLEAR_EN_MASK)

#define LCDIF_OVERLAYCONFIG_SWIZZLE_MASK         (0x60000U)
#define LCDIF_OVERLAYCONFIG_SWIZZLE_SHIFT        (17U)
/*! SWIZZLE - RGB Swizzle
 *  0b00..Input pixel in ARGB format
 *  0b01..Input pixel in RGBA format
 *  0b10..Input pixel in ABGR format
 *  0b11..Input pixel in BGRA format
 */
#define LCDIF_OVERLAYCONFIG_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG_SWIZZLE_SHIFT)) & LCDIF_OVERLAYCONFIG_SWIZZLE_MASK)

#define LCDIF_OVERLAYCONFIG_UV_SWIZZLE_MASK      (0x80000U)
#define LCDIF_OVERLAYCONFIG_UV_SWIZZLE_SHIFT     (19U)
/*! UV_SWIZZLE - UV Swizzle */
#define LCDIF_OVERLAYCONFIG_UV_SWIZZLE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG_UV_SWIZZLE_SHIFT)) & LCDIF_OVERLAYCONFIG_UV_SWIZZLE_MASK)

#define LCDIF_OVERLAYCONFIG_COLOR_KEY_EN_MASK    (0x100000U)
#define LCDIF_OVERLAYCONFIG_COLOR_KEY_EN_SHIFT   (20U)
/*! COLOR_KEY_EN - Color Keying
 *  0b0..Disables color keying.
 *  0b1..Enables color keying.
 */
#define LCDIF_OVERLAYCONFIG_COLOR_KEY_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG_COLOR_KEY_EN_SHIFT)) & LCDIF_OVERLAYCONFIG_COLOR_KEY_EN_MASK)

#define LCDIF_OVERLAYCONFIG_DEC_MODE_MASK        (0xE00000U)
#define LCDIF_OVERLAYCONFIG_DEC_MODE_SHIFT       (21U)
/*! DEC_MODE - Decompression Mode
 *  0b000..Disables decompression.
 *  0b001..Non Subsample
 *  0b010..Horizontal Subsample
 *  0b011..Horizontal Vertical Subsample
 *  0b100..ETC2
 */
#define LCDIF_OVERLAYCONFIG_DEC_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG_DEC_MODE_SHIFT)) & LCDIF_OVERLAYCONFIG_DEC_MODE_MASK)

#define LCDIF_OVERLAYCONFIG_ROT_ANGLE_MASK       (0x7000000U)
#define LCDIF_OVERLAYCONFIG_ROT_ANGLE_SHIFT      (24U)
/*! ROT_ANGLE - Rotation Angle
 *  0b000..Sets the rotation angle to 0 degree.
 *  0b010..Sets the rotation angle to 180 degree.
 *  0b100..Flips horizontal
 *  0b101..Flips vertical
 *  *..
 */
#define LCDIF_OVERLAYCONFIG_ROT_ANGLE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG_ROT_ANGLE_SHIFT)) & LCDIF_OVERLAYCONFIG_ROT_ANGLE_MASK)
/*! @} */

/*! @name OVERLAYADDRESS - Overlay Address */
/*! @{ */

#define LCDIF_OVERLAYADDRESS_ADDRESS_MASK        (0xFFFFFFFFU)
#define LCDIF_OVERLAYADDRESS_ADDRESS_SHIFT       (0U)
/*! ADDRESS - Starting Address */
#define LCDIF_OVERLAYADDRESS_ADDRESS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYADDRESS_ADDRESS_SHIFT)) & LCDIF_OVERLAYADDRESS_ADDRESS_MASK)
/*! @} */

/*! @name OVERLAYSTRIDE - Overlay Stride */
/*! @{ */

#define LCDIF_OVERLAYSTRIDE_STRIDE_MASK          (0x1FFFFU)
#define LCDIF_OVERLAYSTRIDE_STRIDE_SHIFT         (0U)
/*! STRIDE - Stride */
#define LCDIF_OVERLAYSTRIDE_STRIDE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYSTRIDE_STRIDE_SHIFT)) & LCDIF_OVERLAYSTRIDE_STRIDE_MASK)
/*! @} */

/*! @name DCOVERLAYTILEINCFG - Tile Input Configuration */
/*! @{ */

#define LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT_MASK (0x3U)
#define LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT_SHIFT (0U)
/*! TILE_FORMAT - Tile Input Format
 *  0b00..No tile input. See DcOverlayTileInCfg[TILE_FORMAT1].
 *  0b01..Sets the tile input format to ARGB8888.
 *  0b10..Sets the tile input format to YUY2.
 *  0b11..Sets the tile input format to NV12.
 */
#define LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT_SHIFT)) & LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT_MASK)

#define LCDIF_DCOVERLAYTILEINCFG_YUV_STANDARD_MASK (0x4U)
#define LCDIF_DCOVERLAYTILEINCFG_YUV_STANDARD_SHIFT (2U)
/*! YUV_STANDARD - YUV Standard
 *  0b0..Selects the YUV standard BT601.
 *  0b1..Selects the YUV standard BT709.
 */
#define LCDIF_DCOVERLAYTILEINCFG_YUV_STANDARD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCOVERLAYTILEINCFG_YUV_STANDARD_SHIFT)) & LCDIF_DCOVERLAYTILEINCFG_YUV_STANDARD_MASK)

#define LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT1_MASK (0x18U)
#define LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT1_SHIFT (3U)
/*! TILE_FORMAT1 - Tile Format 1 */
#define LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT1_SHIFT)) & LCDIF_DCOVERLAYTILEINCFG_TILE_FORMAT1_MASK)
/*! @} */

/*! @name DCTILEUVOVERLAYADR - Tile Uv Overlay Address */
/*! @{ */

#define LCDIF_DCTILEUVOVERLAYADR_ADDRESS_MASK    (0xFFFFFFFFU)
#define LCDIF_DCTILEUVOVERLAYADR_ADDRESS_SHIFT   (0U)
/*! ADDRESS - Starting Overlay Address */
#define LCDIF_DCTILEUVOVERLAYADR_ADDRESS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVOVERLAYADR_ADDRESS_SHIFT)) & LCDIF_DCTILEUVOVERLAYADR_ADDRESS_MASK)
/*! @} */

/*! @name DCTILEUVOVERLAYSTR - Tile Uv Overlay Stride */
/*! @{ */

#define LCDIF_DCTILEUVOVERLAYSTR_STRIDE_MASK     (0xFFFFU)
#define LCDIF_DCTILEUVOVERLAYSTR_STRIDE_SHIFT    (0U)
/*! STRIDE - Overlay Stride */
#define LCDIF_DCTILEUVOVERLAYSTR_STRIDE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVOVERLAYSTR_STRIDE_SHIFT)) & LCDIF_DCTILEUVOVERLAYSTR_STRIDE_MASK)
/*! @} */

/*! @name OVERLAYTL - Overlay Top Left */
/*! @{ */

#define LCDIF_OVERLAYTL_X_MASK                   (0xFFFU)
#define LCDIF_OVERLAYTL_X_SHIFT                  (0U)
/*! X - Left Boundary */
#define LCDIF_OVERLAYTL_X(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYTL_X_SHIFT)) & LCDIF_OVERLAYTL_X_MASK)

#define LCDIF_OVERLAYTL_Y_MASK                   (0xFFF0000U)
#define LCDIF_OVERLAYTL_Y_SHIFT                  (16U)
/*! Y - Top Boundary */
#define LCDIF_OVERLAYTL_Y(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYTL_Y_SHIFT)) & LCDIF_OVERLAYTL_Y_MASK)
/*! @} */

/*! @name OVERLAYSIZE - Overlay Size */
/*! @{ */

#define LCDIF_OVERLAYSIZE_WIDTH_MASK             (0xFFFU)
#define LCDIF_OVERLAYSIZE_WIDTH_SHIFT            (0U)
/*! WIDTH - Width */
#define LCDIF_OVERLAYSIZE_WIDTH(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYSIZE_WIDTH_SHIFT)) & LCDIF_OVERLAYSIZE_WIDTH_MASK)

#define LCDIF_OVERLAYSIZE_HEIGHT_MASK            (0xFFF0000U)
#define LCDIF_OVERLAYSIZE_HEIGHT_SHIFT           (16U)
/*! HEIGHT - Height */
#define LCDIF_OVERLAYSIZE_HEIGHT(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYSIZE_HEIGHT_SHIFT)) & LCDIF_OVERLAYSIZE_HEIGHT_MASK)
/*! @} */

/*! @name OVERLAYCOLORKEY - Overlay Color Keying Start Address */
/*! @{ */

#define LCDIF_OVERLAYCOLORKEY_BLUE_MASK          (0xFFU)
#define LCDIF_OVERLAYCOLORKEY_BLUE_SHIFT         (0U)
/*! BLUE - Blue */
#define LCDIF_OVERLAYCOLORKEY_BLUE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEY_BLUE_SHIFT)) & LCDIF_OVERLAYCOLORKEY_BLUE_MASK)

#define LCDIF_OVERLAYCOLORKEY_GREEN_MASK         (0xFF00U)
#define LCDIF_OVERLAYCOLORKEY_GREEN_SHIFT        (8U)
/*! GREEN - Green */
#define LCDIF_OVERLAYCOLORKEY_GREEN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEY_GREEN_SHIFT)) & LCDIF_OVERLAYCOLORKEY_GREEN_MASK)

#define LCDIF_OVERLAYCOLORKEY_RED_MASK           (0xFF0000U)
#define LCDIF_OVERLAYCOLORKEY_RED_SHIFT          (16U)
/*! RED - Red */
#define LCDIF_OVERLAYCOLORKEY_RED(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEY_RED_SHIFT)) & LCDIF_OVERLAYCOLORKEY_RED_MASK)

#define LCDIF_OVERLAYCOLORKEY_ALPHA_MASK         (0xFF000000U)
#define LCDIF_OVERLAYCOLORKEY_ALPHA_SHIFT        (24U)
/*! ALPHA - Alpha */
#define LCDIF_OVERLAYCOLORKEY_ALPHA(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEY_ALPHA_SHIFT)) & LCDIF_OVERLAYCOLORKEY_ALPHA_MASK)
/*! @} */

/*! @name OVERLAYCOLORKEYHIGH - Overlay Color Keying End Address */
/*! @{ */

#define LCDIF_OVERLAYCOLORKEYHIGH_BLUE_MASK      (0xFFU)
#define LCDIF_OVERLAYCOLORKEYHIGH_BLUE_SHIFT     (0U)
/*! BLUE - Blue */
#define LCDIF_OVERLAYCOLORKEYHIGH_BLUE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEYHIGH_BLUE_SHIFT)) & LCDIF_OVERLAYCOLORKEYHIGH_BLUE_MASK)

#define LCDIF_OVERLAYCOLORKEYHIGH_GREEN_MASK     (0xFF00U)
#define LCDIF_OVERLAYCOLORKEYHIGH_GREEN_SHIFT    (8U)
/*! GREEN - Green */
#define LCDIF_OVERLAYCOLORKEYHIGH_GREEN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEYHIGH_GREEN_SHIFT)) & LCDIF_OVERLAYCOLORKEYHIGH_GREEN_MASK)

#define LCDIF_OVERLAYCOLORKEYHIGH_RED_MASK       (0xFF0000U)
#define LCDIF_OVERLAYCOLORKEYHIGH_RED_SHIFT      (16U)
/*! RED - Red */
#define LCDIF_OVERLAYCOLORKEYHIGH_RED(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEYHIGH_RED_SHIFT)) & LCDIF_OVERLAYCOLORKEYHIGH_RED_MASK)

#define LCDIF_OVERLAYCOLORKEYHIGH_ALPHA_MASK     (0xFF000000U)
#define LCDIF_OVERLAYCOLORKEYHIGH_ALPHA_SHIFT    (24U)
/*! ALPHA - Alpha */
#define LCDIF_OVERLAYCOLORKEYHIGH_ALPHA(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEYHIGH_ALPHA_SHIFT)) & LCDIF_OVERLAYCOLORKEYHIGH_ALPHA_MASK)
/*! @} */

/*! @name OVERLAYALPHABLENDCONFIG - Overlay Alpha Blending Configuration */
/*! @{ */

#define LCDIF_OVERLAYALPHABLENDCONFIG_ALPHA_BLEND_MASK (0x1U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_ALPHA_BLEND_SHIFT (0U)
/*! ALPHA_BLEND - Alpha Blend
 *  0b0..Disables alpha blending for overlay.
 *  0b1..Enables alpha blending for overlay.
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_ALPHA_BLEND(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_ALPHA_BLEND_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_ALPHA_BLEND_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_MODE_MASK (0x2U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_MODE_SHIFT (1U)
/*! SRC_ALPHA_MODE - Source Alpha Mode
 *  0b0..Normal alpha mode
 *  0b1..Inversed alpha mode if the internal alpha rule needs to be followed
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE_MASK (0x18U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE_SHIFT (3U)
/*! SRC_GLOBAL_ALPHA_MODE - Source Global Alpha Mode
 *  0b00..Normal source alpha mode
 *  0b01..Global source alpha mode
 *  0b10..Scaled (by the global alpha value) source alpha mode
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_SRC_GLOBAL_ALPHA_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_BLENDING_MODE_MASK (0xC0U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_BLENDING_MODE_SHIFT (6U)
/*! SRC_BLENDING_MODE - Source Blending Mode
 *  0b00..Each component of the color is multiplied by (0, 0, 0,0).
 *  0b01..Each component of the color is multiplied by (1, 1, 1,1).
 *  0b10..Normal as the result color is the source color
 *  0b11..Not affected by the color of the underlying pixel
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_BLENDING_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_SRC_BLENDING_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_SRC_BLENDING_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_FACTOR_MASK (0x100U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_FACTOR_SHIFT (8U)
/*! SRC_ALPHA_FACTOR - Source Alpha Factor
 *  0b0..Do not generate the blending factor.
 *  0b1..Generates the blending factor.
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_FACTOR_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_SRC_ALPHA_FACTOR_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_MODE_MASK (0x200U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_MODE_SHIFT (9U)
/*! DST_ALPHA_MODE - Destination Alpha Mode
 *  0b0..Normal destination alpha mode
 *  0b1..Inversed alpha mode if the internal alpha rule needs to be followed
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE_MASK (0xC00U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE_SHIFT (10U)
/*! DST_GLOBAL_ALPHA_MODE - Destination Global Alpha Mode
 *  0b00..Normal destination alpha mode
 *  0b01..Global destination alpha mode
 *  0b10..Scaled (by the global alpha value) destination alpha mode
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_DST_GLOBAL_ALPHA_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_BLENDING_MODE_MASK (0x6000U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_BLENDING_MODE_SHIFT (13U)
/*! DST_BLENDING_MODE - Destination Blending Mode
 *  0b00..Each component of the color is multiplied by (0, 0, 0,0).
 *  0b01..Each component of the color is multiplied by (1, 1, 1,1).
 *  0b10..Normal as the result color is the destination color
 *  0b11..Not affected by the color of the underlying pixel
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_BLENDING_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_DST_BLENDING_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_DST_BLENDING_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_FACTOR_MASK (0x8000U)
#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_FACTOR_SHIFT (15U)
/*! DST_ALPHA_FACTOR - Destination Alpha Factor
 *  0b0..Do not generate the blending factor for destination alpha.
 *  0b1..Generates the blending factor for destination alpha.
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_FACTOR_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG_DST_ALPHA_FACTOR_MASK)
/*! @} */

/*! @name OVERLAYGLOBALALPHA - Overlay Global Alpha */
/*! @{ */

#define LCDIF_OVERLAYGLOBALALPHA_SRC_ALPHA_MASK  (0xFFU)
#define LCDIF_OVERLAYGLOBALALPHA_SRC_ALPHA_SHIFT (0U)
/*! SRC_ALPHA - Source Alpha */
#define LCDIF_OVERLAYGLOBALALPHA_SRC_ALPHA(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYGLOBALALPHA_SRC_ALPHA_SHIFT)) & LCDIF_OVERLAYGLOBALALPHA_SRC_ALPHA_MASK)

#define LCDIF_OVERLAYGLOBALALPHA_DST_ALPHA_MASK  (0xFF00U)
#define LCDIF_OVERLAYGLOBALALPHA_DST_ALPHA_SHIFT (8U)
/*! DST_ALPHA - Destination Alpha */
#define LCDIF_OVERLAYGLOBALALPHA_DST_ALPHA(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYGLOBALALPHA_DST_ALPHA_SHIFT)) & LCDIF_OVERLAYGLOBALALPHA_DST_ALPHA_MASK)
/*! @} */

/*! @name OVERLAYCLEARVALUE - Overlay Clear Value */
/*! @{ */

#define LCDIF_OVERLAYCLEARVALUE_BLUE_MASK        (0xFFU)
#define LCDIF_OVERLAYCLEARVALUE_BLUE_SHIFT       (0U)
/*! BLUE - Blue */
#define LCDIF_OVERLAYCLEARVALUE_BLUE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCLEARVALUE_BLUE_SHIFT)) & LCDIF_OVERLAYCLEARVALUE_BLUE_MASK)

#define LCDIF_OVERLAYCLEARVALUE_GREEN_MASK       (0xFF00U)
#define LCDIF_OVERLAYCLEARVALUE_GREEN_SHIFT      (8U)
/*! GREEN - Green */
#define LCDIF_OVERLAYCLEARVALUE_GREEN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCLEARVALUE_GREEN_SHIFT)) & LCDIF_OVERLAYCLEARVALUE_GREEN_MASK)

#define LCDIF_OVERLAYCLEARVALUE_RED_MASK         (0xFF0000U)
#define LCDIF_OVERLAYCLEARVALUE_RED_SHIFT        (16U)
/*! RED - Red */
#define LCDIF_OVERLAYCLEARVALUE_RED(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCLEARVALUE_RED_SHIFT)) & LCDIF_OVERLAYCLEARVALUE_RED_MASK)

#define LCDIF_OVERLAYCLEARVALUE_ALPHA_MASK       (0xFF000000U)
#define LCDIF_OVERLAYCLEARVALUE_ALPHA_SHIFT      (24U)
/*! ALPHA - Alpha */
#define LCDIF_OVERLAYCLEARVALUE_ALPHA(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCLEARVALUE_ALPHA_SHIFT)) & LCDIF_OVERLAYCLEARVALUE_ALPHA_MASK)
/*! @} */

/*! @name OVERLAYCONFIG1 - Overlay Layer 1 Configuration */
/*! @{ */

#define LCDIF_OVERLAYCONFIG1_FORMAT_MASK         (0x7U)
#define LCDIF_OVERLAYCONFIG1_FORMAT_SHIFT        (0U)
/*! FORMAT - Input Format
 *  0b000..No overlay
 *  0b001..Sets the input format to A4R4G4B4.
 *  0b010..Sets the input format to A1R5G5B5.
 *  0b011..Sets the input format to R5G6B5.
 *  0b100..Sets the input format to A8R8G8B8.
 *  0b101..Sets the input format to R8G8B8.
 *  0b110..Sets the input format to A8R5G6B5.
 */
#define LCDIF_OVERLAYCONFIG1_FORMAT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG1_FORMAT_SHIFT)) & LCDIF_OVERLAYCONFIG1_FORMAT_MASK)

#define LCDIF_OVERLAYCONFIG1_ENABLE_MASK         (0x8U)
#define LCDIF_OVERLAYCONFIG1_ENABLE_SHIFT        (3U)
/*! ENABLE - Enable
 *  0b0..Disables the overlay layer 1.
 *  0b1..Enables the overlay layer 1.
 */
#define LCDIF_OVERLAYCONFIG1_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG1_ENABLE_SHIFT)) & LCDIF_OVERLAYCONFIG1_ENABLE_MASK)

#define LCDIF_OVERLAYCONFIG1_CLEAR_EN_MASK       (0x20U)
#define LCDIF_OVERLAYCONFIG1_CLEAR_EN_SHIFT      (5U)
/*! CLEAR_EN - Enable Clear
 *  0b0..Disables clearing the overlay layer 1.
 *  0b1..Enables clearing the overlay layer 1.
 */
#define LCDIF_OVERLAYCONFIG1_CLEAR_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG1_CLEAR_EN_SHIFT)) & LCDIF_OVERLAYCONFIG1_CLEAR_EN_MASK)

#define LCDIF_OVERLAYCONFIG1_SWIZZLE_MASK        (0x60000U)
#define LCDIF_OVERLAYCONFIG1_SWIZZLE_SHIFT       (17U)
/*! SWIZZLE - RGB Swizzle
 *  0b00..Input pixel in ARGB format order
 *  0b01..Input pixel in RGBA format order
 *  0b10..Input pixel in ABGR format order
 *  0b11..Input pixel in BGRA format order
 */
#define LCDIF_OVERLAYCONFIG1_SWIZZLE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG1_SWIZZLE_SHIFT)) & LCDIF_OVERLAYCONFIG1_SWIZZLE_MASK)

#define LCDIF_OVERLAYCONFIG1_COLOR_KEY_EN_MASK   (0x100000U)
#define LCDIF_OVERLAYCONFIG1_COLOR_KEY_EN_SHIFT  (20U)
/*! COLOR_KEY_EN - Enable Color Keying
 *  0b0..Disables color keying.
 *  0b1..Enables color keying.
 */
#define LCDIF_OVERLAYCONFIG1_COLOR_KEY_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG1_COLOR_KEY_EN_SHIFT)) & LCDIF_OVERLAYCONFIG1_COLOR_KEY_EN_MASK)

#define LCDIF_OVERLAYCONFIG1_DEC_MODE_MASK       (0xE00000U)
#define LCDIF_OVERLAYCONFIG1_DEC_MODE_SHIFT      (21U)
/*! DEC_MODE - Decompression Mode
 *  0b000..Disables decompression.
 *  0b001..Enables non_subsample decompression mode.
 *  0b010..Enables horizontal subsample decompression mode.
 *  0b011..Enables horizontal and vertical subsample decompression mode.
 *  0b100..Enables ETC2 decompression mode.
 */
#define LCDIF_OVERLAYCONFIG1_DEC_MODE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG1_DEC_MODE_SHIFT)) & LCDIF_OVERLAYCONFIG1_DEC_MODE_MASK)

#define LCDIF_OVERLAYCONFIG1_ROT_ANGLE_MASK      (0x7000000U)
#define LCDIF_OVERLAYCONFIG1_ROT_ANGLE_SHIFT     (24U)
/*! ROT_ANGLE - Rotation Angle
 *  0b000..Sets the rotation angle to 0 degree.
 *  0b010..Sets the rotation angle to 180 degree.
 *  0b100..Flips horizontal
 *  0b101..Flips vertical
 */
#define LCDIF_OVERLAYCONFIG1_ROT_ANGLE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCONFIG1_ROT_ANGLE_SHIFT)) & LCDIF_OVERLAYCONFIG1_ROT_ANGLE_MASK)
/*! @} */

/*! @name OVERLAYADDRESS1 - Overlay Layer 1 Address */
/*! @{ */

#define LCDIF_OVERLAYADDRESS1_ADDRESS_MASK       (0xFFFFFFFFU)
#define LCDIF_OVERLAYADDRESS1_ADDRESS_SHIFT      (0U)
/*! ADDRESS - Start Address */
#define LCDIF_OVERLAYADDRESS1_ADDRESS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYADDRESS1_ADDRESS_SHIFT)) & LCDIF_OVERLAYADDRESS1_ADDRESS_MASK)
/*! @} */

/*! @name OVERLAYSTRIDE1 - Overlay Layer 1 Stride */
/*! @{ */

#define LCDIF_OVERLAYSTRIDE1_STRIDE_MASK         (0x1FFFFU)
#define LCDIF_OVERLAYSTRIDE1_STRIDE_SHIFT        (0U)
/*! STRIDE - Stride of Overlay Layer 1 */
#define LCDIF_OVERLAYSTRIDE1_STRIDE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYSTRIDE1_STRIDE_SHIFT)) & LCDIF_OVERLAYSTRIDE1_STRIDE_MASK)
/*! @} */

/*! @name OVERLAYTL1 - Overlay Layer 1 Top Left */
/*! @{ */

#define LCDIF_OVERLAYTL1_X_MASK                  (0xFFFU)
#define LCDIF_OVERLAYTL1_X_SHIFT                 (0U)
/*! X - Left Boundary */
#define LCDIF_OVERLAYTL1_X(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYTL1_X_SHIFT)) & LCDIF_OVERLAYTL1_X_MASK)

#define LCDIF_OVERLAYTL1_Y_MASK                  (0xFFF0000U)
#define LCDIF_OVERLAYTL1_Y_SHIFT                 (16U)
/*! Y - Top boundary */
#define LCDIF_OVERLAYTL1_Y(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYTL1_Y_SHIFT)) & LCDIF_OVERLAYTL1_Y_MASK)
/*! @} */

/*! @name OVERLAYSIZE1 - Overlay Layer 1 Size */
/*! @{ */

#define LCDIF_OVERLAYSIZE1_WIDTH_MASK            (0xFFFU)
#define LCDIF_OVERLAYSIZE1_WIDTH_SHIFT           (0U)
/*! WIDTH - Width */
#define LCDIF_OVERLAYSIZE1_WIDTH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYSIZE1_WIDTH_SHIFT)) & LCDIF_OVERLAYSIZE1_WIDTH_MASK)

#define LCDIF_OVERLAYSIZE1_HEIGHT_MASK           (0xFFF0000U)
#define LCDIF_OVERLAYSIZE1_HEIGHT_SHIFT          (16U)
/*! HEIGHT - Height */
#define LCDIF_OVERLAYSIZE1_HEIGHT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYSIZE1_HEIGHT_SHIFT)) & LCDIF_OVERLAYSIZE1_HEIGHT_MASK)
/*! @} */

/*! @name OVERLAYCOLORKEY1 - Overlay Layer 1 Color Keying Start Address */
/*! @{ */

#define LCDIF_OVERLAYCOLORKEY1_BLUE_MASK         (0xFFU)
#define LCDIF_OVERLAYCOLORKEY1_BLUE_SHIFT        (0U)
/*! BLUE - Blue */
#define LCDIF_OVERLAYCOLORKEY1_BLUE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEY1_BLUE_SHIFT)) & LCDIF_OVERLAYCOLORKEY1_BLUE_MASK)

#define LCDIF_OVERLAYCOLORKEY1_GREEN_MASK        (0xFF00U)
#define LCDIF_OVERLAYCOLORKEY1_GREEN_SHIFT       (8U)
/*! GREEN - Green */
#define LCDIF_OVERLAYCOLORKEY1_GREEN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEY1_GREEN_SHIFT)) & LCDIF_OVERLAYCOLORKEY1_GREEN_MASK)

#define LCDIF_OVERLAYCOLORKEY1_RED_MASK          (0xFF0000U)
#define LCDIF_OVERLAYCOLORKEY1_RED_SHIFT         (16U)
/*! RED - red */
#define LCDIF_OVERLAYCOLORKEY1_RED(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEY1_RED_SHIFT)) & LCDIF_OVERLAYCOLORKEY1_RED_MASK)

#define LCDIF_OVERLAYCOLORKEY1_ALPHA_MASK        (0xFF000000U)
#define LCDIF_OVERLAYCOLORKEY1_ALPHA_SHIFT       (24U)
/*! ALPHA - Alpha */
#define LCDIF_OVERLAYCOLORKEY1_ALPHA(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEY1_ALPHA_SHIFT)) & LCDIF_OVERLAYCOLORKEY1_ALPHA_MASK)
/*! @} */

/*! @name OVERLAYCOLORKEYHIGH1 - Overlay Layer 1 Color Keying End Address */
/*! @{ */

#define LCDIF_OVERLAYCOLORKEYHIGH1_BLUE_MASK     (0xFFU)
#define LCDIF_OVERLAYCOLORKEYHIGH1_BLUE_SHIFT    (0U)
/*! BLUE - Blue */
#define LCDIF_OVERLAYCOLORKEYHIGH1_BLUE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEYHIGH1_BLUE_SHIFT)) & LCDIF_OVERLAYCOLORKEYHIGH1_BLUE_MASK)

#define LCDIF_OVERLAYCOLORKEYHIGH1_GREEN_MASK    (0xFF00U)
#define LCDIF_OVERLAYCOLORKEYHIGH1_GREEN_SHIFT   (8U)
/*! GREEN - Green */
#define LCDIF_OVERLAYCOLORKEYHIGH1_GREEN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEYHIGH1_GREEN_SHIFT)) & LCDIF_OVERLAYCOLORKEYHIGH1_GREEN_MASK)

#define LCDIF_OVERLAYCOLORKEYHIGH1_RED_MASK      (0xFF0000U)
#define LCDIF_OVERLAYCOLORKEYHIGH1_RED_SHIFT     (16U)
/*! RED - red */
#define LCDIF_OVERLAYCOLORKEYHIGH1_RED(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEYHIGH1_RED_SHIFT)) & LCDIF_OVERLAYCOLORKEYHIGH1_RED_MASK)

#define LCDIF_OVERLAYCOLORKEYHIGH1_ALPHA_MASK    (0xFF000000U)
#define LCDIF_OVERLAYCOLORKEYHIGH1_ALPHA_SHIFT   (24U)
/*! ALPHA - Alpha */
#define LCDIF_OVERLAYCOLORKEYHIGH1_ALPHA(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCOLORKEYHIGH1_ALPHA_SHIFT)) & LCDIF_OVERLAYCOLORKEYHIGH1_ALPHA_MASK)
/*! @} */

/*! @name OVERLAYALPHABLENDCONFIG1 - Overlay Layer 1 Alpha Blending Configuration */
/*! @{ */

#define LCDIF_OVERLAYALPHABLENDCONFIG1_ALPHA_BLEND_MASK (0x1U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_ALPHA_BLEND_SHIFT (0U)
/*! ALPHA_BLEND - Alpha Blend
 *  0b0..Disables alpha blending for the overlay layer 1.
 *  0b1..Enables alpha blending for the overlay layer 1.
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_ALPHA_BLEND(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_ALPHA_BLEND_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_ALPHA_BLEND_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_MODE_MASK (0x2U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_MODE_SHIFT (1U)
/*! SRC_ALPHA_MODE - Source Alpha Mode
 *  0b0..Normal alpha mode
 *  0b1..Inversed alpha mode if the internal alpha rule needs to be followed
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_GLOBAL_ALPHA_MODE_MASK (0x18U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_GLOBAL_ALPHA_MODE_SHIFT (3U)
/*! SRC_GLOBAL_ALPHA_MODE - Source Global Alpha Mode
 *  0b00..Normal source alpha mode
 *  0b01..Global source alpha mode
 *  0b10..Scaled (by the global alpha value) source alpha mode
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_GLOBAL_ALPHA_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_BLENDING_MODE_MASK (0xC0U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_BLENDING_MODE_SHIFT (6U)
/*! SRC_BLENDING_MODE - Source Blending Mode
 *  0b00..Each component of the color is multiplied by (0, 0, 0,0).
 *  0b01..Each component of the color is multiplied by (1, 1, 1,1).
 *  0b10..Normal as the result color is the source color
 *  0b11..Not affected by the color of the underlying pixel
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_BLENDING_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_BLENDING_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_BLENDING_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_FACTOR_MASK (0x100U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_FACTOR_SHIFT (8U)
/*! SRC_ALPHA_FACTOR - Source Alpha Factor
 *  0b0..Do not generate the blending factor for source alpha for the overlay layer 1.
 *  0b1..Generates the blending factor for source alpha for the overlay layer 1.
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_FACTOR_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_SRC_ALPHA_FACTOR_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_MODE_MASK (0x200U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_MODE_SHIFT (9U)
/*! DST_ALPHA_MODE - Destination Alpha Mode
 *  0b0..Normal alpha mode
 *  0b1..Inversed alpha mode if the internal alpha rule needs to be followed
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_GLOBAL_ALPHA_MODE_MASK (0xC00U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_GLOBAL_ALPHA_MODE_SHIFT (10U)
/*! DST_GLOBAL_ALPHA_MODE - Destination Global Alpha Mode
 *  0b00..Normal destination alpha mode
 *  0b01..Global destination alpha mode
 *  0b10..Scaled (by the global alpha value) destination alpha mode
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_DST_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_DST_GLOBAL_ALPHA_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_BLENDING_MODE_MASK (0x6000U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_BLENDING_MODE_SHIFT (13U)
/*! DST_BLENDING_MODE - Destination Blending Mode
 *  0b00..Each component of the color is multiplied by (0, 0, 0,0).
 *  0b01..Each component of the color is multiplied by (1, 1, 1,1).
 *  0b10..Normal as the result color is the source color
 *  0b11..Not affected by the color of the underlying pixel
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_BLENDING_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_DST_BLENDING_MODE_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_DST_BLENDING_MODE_MASK)

#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_FACTOR_MASK (0x8000U)
#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_FACTOR_SHIFT (15U)
/*! DST_ALPHA_FACTOR - DST Alpha Factor
 *  0b0..Do not generate the blending factor for destination alpha for the overlay layer 1.
 *  0b1..Generates the blending factor for destination alpha for the overlay layer 1.
 */
#define LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_FACTOR_SHIFT)) & LCDIF_OVERLAYALPHABLENDCONFIG1_DST_ALPHA_FACTOR_MASK)
/*! @} */

/*! @name OVERLAYGLOBALALPHA1 - Overlay Layer 1 Global Alpha */
/*! @{ */

#define LCDIF_OVERLAYGLOBALALPHA1_SRC_ALPHA_MASK (0xFFU)
#define LCDIF_OVERLAYGLOBALALPHA1_SRC_ALPHA_SHIFT (0U)
/*! SRC_ALPHA - Source Alpha */
#define LCDIF_OVERLAYGLOBALALPHA1_SRC_ALPHA(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYGLOBALALPHA1_SRC_ALPHA_SHIFT)) & LCDIF_OVERLAYGLOBALALPHA1_SRC_ALPHA_MASK)

#define LCDIF_OVERLAYGLOBALALPHA1_DST_ALPHA_MASK (0xFF00U)
#define LCDIF_OVERLAYGLOBALALPHA1_DST_ALPHA_SHIFT (8U)
/*! DST_ALPHA - Destination Alpha */
#define LCDIF_OVERLAYGLOBALALPHA1_DST_ALPHA(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYGLOBALALPHA1_DST_ALPHA_SHIFT)) & LCDIF_OVERLAYGLOBALALPHA1_DST_ALPHA_MASK)
/*! @} */

/*! @name OVERLAYCLEARVALUE1 - Overlay Layer 1 Clear Value */
/*! @{ */

#define LCDIF_OVERLAYCLEARVALUE1_BLUE_MASK       (0xFFU)
#define LCDIF_OVERLAYCLEARVALUE1_BLUE_SHIFT      (0U)
/*! BLUE - Blue */
#define LCDIF_OVERLAYCLEARVALUE1_BLUE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCLEARVALUE1_BLUE_SHIFT)) & LCDIF_OVERLAYCLEARVALUE1_BLUE_MASK)

#define LCDIF_OVERLAYCLEARVALUE1_GREEN_MASK      (0xFF00U)
#define LCDIF_OVERLAYCLEARVALUE1_GREEN_SHIFT     (8U)
/*! GREEN - Green */
#define LCDIF_OVERLAYCLEARVALUE1_GREEN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCLEARVALUE1_GREEN_SHIFT)) & LCDIF_OVERLAYCLEARVALUE1_GREEN_MASK)

#define LCDIF_OVERLAYCLEARVALUE1_RED_MASK        (0xFF0000U)
#define LCDIF_OVERLAYCLEARVALUE1_RED_SHIFT       (16U)
/*! RED - Red */
#define LCDIF_OVERLAYCLEARVALUE1_RED(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCLEARVALUE1_RED_SHIFT)) & LCDIF_OVERLAYCLEARVALUE1_RED_MASK)

#define LCDIF_OVERLAYCLEARVALUE1_ALPHA_MASK      (0xFF000000U)
#define LCDIF_OVERLAYCLEARVALUE1_ALPHA_SHIFT     (24U)
/*! ALPHA - Alpha */
#define LCDIF_OVERLAYCLEARVALUE1_ALPHA(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_OVERLAYCLEARVALUE1_ALPHA_SHIFT)) & LCDIF_OVERLAYCLEARVALUE1_ALPHA_MASK)
/*! @} */

/*! @name DISPLAYDITHERTABLELOW0 - Dither Lookup Table Low Threshold */
/*! @{ */

#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_MASK  (0xFU)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_SHIFT (0U)
/*! Y0_X0 - Y0_X0 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_MASK  (0xF0U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_SHIFT (4U)
/*! Y0_X1 - Y0_X1 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_MASK  (0xF00U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_SHIFT (8U)
/*! Y0_X2 - Y0_X2 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_MASK  (0xF000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_SHIFT (12U)
/*! Y0_X3 - Y0_X3 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_MASK  (0xF0000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_SHIFT (16U)
/*! Y1_X0 - Y1_X0 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_MASK  (0xF00000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_SHIFT (20U)
/*! Y1_X1 - Y1_X1 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_MASK  (0xF000000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_SHIFT (24U)
/*! Y1_X2 - Y1_X2 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_MASK  (0xF0000000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_SHIFT (28U)
/*! Y1_X3 - Y1_X3 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_MASK)
/*! @} */

/*! @name DISPLAYDITHERTABLEHIGH0 - Dither Lookup Table High Threshold */
/*! @{ */

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_MASK (0xFU)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_SHIFT (0U)
/*! Y2_X0 - Y2_X0 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_MASK (0xF0U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_SHIFT (4U)
/*! Y2_X1 - Y2_X1 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_MASK (0xF00U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_SHIFT (8U)
/*! Y2_X2 - Y2_X2 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_MASK (0xF000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_SHIFT (12U)
/*! Y2_X3 - Y2_X3 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_MASK (0xF0000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_SHIFT (16U)
/*! Y3_X0 - Y3_X0 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_MASK (0xF00000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_SHIFT (20U)
/*! Y3_X1 - Y3_X1 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_MASK (0xF000000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_SHIFT (24U)
/*! Y3_X2 - Y3_X2 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_MASK (0xF0000000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_SHIFT (28U)
/*! Y3_X3 - Y3_X3 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_MASK)
/*! @} */

/*! @name PANELCONFIG0 - Panel Configuration */
/*! @{ */

#define LCDIF_PANELCONFIG0_DE_MASK               (0x1U)
#define LCDIF_PANELCONFIG0_DE_SHIFT              (0U)
/*! DE - Data Enable
 *  0b0..Disables data.
 *  0b1..Enables data.
 */
#define LCDIF_PANELCONFIG0_DE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DE_SHIFT)) & LCDIF_PANELCONFIG0_DE_MASK)

#define LCDIF_PANELCONFIG0_DE_POLARITY_MASK      (0x2U)
#define LCDIF_PANELCONFIG0_DE_POLARITY_SHIFT     (1U)
/*! DE_POLARITY - Data Enable Polarity
 *  0b0..Sets the polarity of data enabled to positive.
 *  0b1..Sets the polarity of data enabled to negative.
 */
#define LCDIF_PANELCONFIG0_DE_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DE_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_DE_POLARITY_MASK)

#define LCDIF_PANELCONFIG0_DATA_POLARITY_MASK    (0x20U)
#define LCDIF_PANELCONFIG0_DATA_POLARITY_SHIFT   (5U)
/*! DATA_POLARITY - Data Polarity
 *  0b0..Sets the data polarity to positive.
 *  0b1..Sets the data polarity to negative.
 */
#define LCDIF_PANELCONFIG0_DATA_POLARITY(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DATA_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_DATA_POLARITY_MASK)

#define LCDIF_PANELCONFIG0_CLOCK_MASK            (0x100U)
#define LCDIF_PANELCONFIG0_CLOCK_SHIFT           (8U)
/*! CLOCK - Clock
 *  0b0..Disables clock.
 *  0b1..Enables clock.
 */
#define LCDIF_PANELCONFIG0_CLOCK(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_CLOCK_SHIFT)) & LCDIF_PANELCONFIG0_CLOCK_MASK)

#define LCDIF_PANELCONFIG0_CLOCK_POLARITY_MASK   (0x200U)
#define LCDIF_PANELCONFIG0_CLOCK_POLARITY_SHIFT  (9U)
/*! CLOCK_POLARITY - Clock Polarity
 *  0b0..Sets the clock polarity to positive.
 *  0b1..Sets the clock polarity to negative.
 */
#define LCDIF_PANELCONFIG0_CLOCK_POLARITY(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_CLOCK_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_CLOCK_POLARITY_MASK)
/*! @} */

/*! @name PANELCONTROL - Panel Control */
/*! @{ */

#define LCDIF_PANELCONTROL_VALID_MASK            (0x1U)
#define LCDIF_PANELCONTROL_VALID_SHIFT           (0U)
/*! VALID - Valid
 *  0b0..Pending
 *  0b1..Copies a set of registers at the next VBLANK.
 */
#define LCDIF_PANELCONTROL_VALID(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONTROL_VALID_SHIFT)) & LCDIF_PANELCONTROL_VALID_MASK)

#define LCDIF_PANELCONTROL_BACK_PRESSURE_DISABLE_MASK (0x2U)
#define LCDIF_PANELCONTROL_BACK_PRESSURE_DISABLE_SHIFT (1U)
/*! BACK_PRESSURE_DISABLE - Back Pressure Disable
 *  0b0..Enables back pressure.
 *  0b1..Disables back pressure.
 */
#define LCDIF_PANELCONTROL_BACK_PRESSURE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONTROL_BACK_PRESSURE_DISABLE_SHIFT)) & LCDIF_PANELCONTROL_BACK_PRESSURE_DISABLE_MASK)
/*! @} */

/*! @name PANELFUNCTION - Panel Function */
/*! @{ */

#define LCDIF_PANELFUNCTION_OUTPUT_MASK          (0x1U)
#define LCDIF_PANELFUNCTION_OUTPUT_SHIFT         (0U)
/*! OUTPUT - Output
 *  0b0..Disables output panel.
 *  0b1..Enables output panel.
 */
#define LCDIF_PANELFUNCTION_OUTPUT(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELFUNCTION_OUTPUT_SHIFT)) & LCDIF_PANELFUNCTION_OUTPUT_MASK)

#define LCDIF_PANELFUNCTION_GAMMA_MASK           (0x2U)
#define LCDIF_PANELFUNCTION_GAMMA_SHIFT          (1U)
/*! GAMMA - Gamma
 *  0b0..Disables Gamma.
 *  0b1..Enables Gamma.
 */
#define LCDIF_PANELFUNCTION_GAMMA(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELFUNCTION_GAMMA_SHIFT)) & LCDIF_PANELFUNCTION_GAMMA_MASK)

#define LCDIF_PANELFUNCTION_DITHER_MASK          (0x4U)
#define LCDIF_PANELFUNCTION_DITHER_SHIFT         (2U)
/*! DITHER - Dither
 *  0b0..Disables dither.
 *  0b1..Enables dither.
 */
#define LCDIF_PANELFUNCTION_DITHER(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELFUNCTION_DITHER_SHIFT)) & LCDIF_PANELFUNCTION_DITHER_MASK)
/*! @} */

/*! @name PANELWORKING - Panel Working */
/*! @{ */

#define LCDIF_PANELWORKING_WORKING_MASK          (0x1U)
#define LCDIF_PANELWORKING_WORKING_SHIFT         (0U)
/*! WORKING - Working
 *  0b1..Starts reset of the display controller.
 */
#define LCDIF_PANELWORKING_WORKING(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELWORKING_WORKING_SHIFT)) & LCDIF_PANELWORKING_WORKING_MASK)
/*! @} */

/*! @name PANELSTATE - Panel State */
/*! @{ */

#define LCDIF_PANELSTATE_VIDEO_UNDER_FLOW_MASK   (0x2U)
#define LCDIF_PANELSTATE_VIDEO_UNDER_FLOW_SHIFT  (1U)
/*! VIDEO_UNDER_FLOW - Video Under Flow
 *  0b0..Do not set the display FIFO video to underflow.
 *  0b1..Sets the display FIFO video to underflow.
 */
#define LCDIF_PANELSTATE_VIDEO_UNDER_FLOW(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELSTATE_VIDEO_UNDER_FLOW_SHIFT)) & LCDIF_PANELSTATE_VIDEO_UNDER_FLOW_MASK)

#define LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW_MASK (0x4U)
#define LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW_SHIFT (2U)
/*! OVERLAY_UNDER_FLOW - Overlay Layer 0 Under Flow
 *  0b0..Do not set the overlay layer 0 FIFO to underflow.
 *  0b1..Sets the overlay layer 0 FIFO to underflow.
 */
#define LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW_SHIFT)) & LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW_MASK)

#define LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW1_MASK (0x8U)
#define LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW1_SHIFT (3U)
/*! OVERLAY_UNDER_FLOW1 - Overlay Layer 1 Under Flow
 *  0b0..Do not set the overlay layer 1 FIFO to underflow.
 *  0b1..Sets the overlay layer 1 FIFO to underflow.
 */
#define LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW1(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW1_SHIFT)) & LCDIF_PANELSTATE_OVERLAY_UNDER_FLOW1_MASK)
/*! @} */

/*! @name HDISPLAY0 - Horizontal Display Total and Visible Pixel Count */
/*! @{ */

#define LCDIF_HDISPLAY0_DISPLAY_END_MASK         (0x1FFFU)
#define LCDIF_HDISPLAY0_DISPLAY_END_SHIFT        (0U)
/*! DISPLAY_END - Display End */
#define LCDIF_HDISPLAY0_DISPLAY_END(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_HDISPLAY0_DISPLAY_END_SHIFT)) & LCDIF_HDISPLAY0_DISPLAY_END_MASK)

#define LCDIF_HDISPLAY0_TOTAL_MASK               (0x1FFF0000U)
#define LCDIF_HDISPLAY0_TOTAL_SHIFT              (16U)
/*! TOTAL - Total */
#define LCDIF_HDISPLAY0_TOTAL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_HDISPLAY0_TOTAL_SHIFT)) & LCDIF_HDISPLAY0_TOTAL_MASK)
/*! @} */

/*! @name HSYNC0 - Horizontal Sync Counter */
/*! @{ */

#define LCDIF_HSYNC0_START_MASK                  (0x1FFFU)
#define LCDIF_HSYNC0_START_SHIFT                 (0U)
/*! START - Start */
#define LCDIF_HSYNC0_START(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_START_SHIFT)) & LCDIF_HSYNC0_START_MASK)

#define LCDIF_HSYNC0_END_MASK                    (0x1FFF0000U)
#define LCDIF_HSYNC0_END_SHIFT                   (16U)
/*! END - End */
#define LCDIF_HSYNC0_END(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_END_SHIFT)) & LCDIF_HSYNC0_END_MASK)

#define LCDIF_HSYNC0_PULSE_MASK                  (0x40000000U)
#define LCDIF_HSYNC0_PULSE_SHIFT                 (30U)
/*! PULSE - Sync Pulse
 *  0b0..Disables horizontal sync pulse control.
 *  0b1..Enables horizontal sync pulse control.
 */
#define LCDIF_HSYNC0_PULSE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_PULSE_SHIFT)) & LCDIF_HSYNC0_PULSE_MASK)

#define LCDIF_HSYNC0_POLARITY_MASK               (0x80000000U)
#define LCDIF_HSYNC0_POLARITY_SHIFT              (31U)
/*! POLARITY - Sync Pulse Polarity
 *  0b0..Sets the polarity of the horizontal sync pulse to positive.
 *  0b1..Sets the polarity of the horizontal sync pulse to negative.
 */
#define LCDIF_HSYNC0_POLARITY(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_POLARITY_SHIFT)) & LCDIF_HSYNC0_POLARITY_MASK)
/*! @} */

/*! @name VDISPLAY0 - Vertical Total and Visible Pixel Count */
/*! @{ */

#define LCDIF_VDISPLAY0_DISPLAY_END_MASK         (0xFFFU)
#define LCDIF_VDISPLAY0_DISPLAY_END_SHIFT        (0U)
/*! DISPLAY_END - Display End */
#define LCDIF_VDISPLAY0_DISPLAY_END(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDISPLAY0_DISPLAY_END_SHIFT)) & LCDIF_VDISPLAY0_DISPLAY_END_MASK)

#define LCDIF_VDISPLAY0_TOTAL_MASK               (0xFFF0000U)
#define LCDIF_VDISPLAY0_TOTAL_SHIFT              (16U)
/*! TOTAL - Total */
#define LCDIF_VDISPLAY0_TOTAL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDISPLAY0_TOTAL_SHIFT)) & LCDIF_VDISPLAY0_TOTAL_MASK)
/*! @} */

/*! @name VSYNC0 - Vertical Sync Counter */
/*! @{ */

#define LCDIF_VSYNC0_START_MASK                  (0xFFFU)
#define LCDIF_VSYNC0_START_SHIFT                 (0U)
/*! START - Start */
#define LCDIF_VSYNC0_START(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_START_SHIFT)) & LCDIF_VSYNC0_START_MASK)

#define LCDIF_VSYNC0_END_MASK                    (0xFFF0000U)
#define LCDIF_VSYNC0_END_SHIFT                   (16U)
/*! END - End */
#define LCDIF_VSYNC0_END(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_END_SHIFT)) & LCDIF_VSYNC0_END_MASK)

#define LCDIF_VSYNC0_PULSE_MASK                  (0x40000000U)
#define LCDIF_VSYNC0_PULSE_SHIFT                 (30U)
/*! PULSE - Vertical Sync Pulse
 *  0b0..Disables vertical sync pulse.
 *  0b1..Enables vertical sync pulse.
 */
#define LCDIF_VSYNC0_PULSE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_PULSE_SHIFT)) & LCDIF_VSYNC0_PULSE_MASK)

#define LCDIF_VSYNC0_POLARITY_MASK               (0x80000000U)
#define LCDIF_VSYNC0_POLARITY_SHIFT              (31U)
/*! POLARITY - Polarity
 *  0b0..Sets the polarity of the vertical sync pulse to positive.
 *  0b1..Sets the polarity of the vertical sync pulse to negative.
 */
#define LCDIF_VSYNC0_POLARITY(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_POLARITY_SHIFT)) & LCDIF_VSYNC0_POLARITY_MASK)
/*! @} */

/*! @name DISPLAYCURRENTLOCATION0 - Display Current Location */
/*! @{ */

#define LCDIF_DISPLAYCURRENTLOCATION0_X_MASK     (0xFFFFU)
#define LCDIF_DISPLAYCURRENTLOCATION0_X_SHIFT    (0U)
/*! X - X */
#define LCDIF_DISPLAYCURRENTLOCATION0_X(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYCURRENTLOCATION0_X_SHIFT)) & LCDIF_DISPLAYCURRENTLOCATION0_X_MASK)

#define LCDIF_DISPLAYCURRENTLOCATION0_Y_MASK     (0xFFFF0000U)
#define LCDIF_DISPLAYCURRENTLOCATION0_Y_SHIFT    (16U)
/*! Y - Y */
#define LCDIF_DISPLAYCURRENTLOCATION0_Y(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYCURRENTLOCATION0_Y_SHIFT)) & LCDIF_DISPLAYCURRENTLOCATION0_Y_MASK)
/*! @} */

/*! @name GAMMAINDEX0 - Gamma Index */
/*! @{ */

#define LCDIF_GAMMAINDEX0_INDEX_MASK             (0xFFU)
#define LCDIF_GAMMAINDEX0_INDEX_SHIFT            (0U)
/*! INDEX - Index */
#define LCDIF_GAMMAINDEX0_INDEX(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMAINDEX0_INDEX_SHIFT)) & LCDIF_GAMMAINDEX0_INDEX_MASK)
/*! @} */

/*! @name GAMMADATA0 - Gamma Data */
/*! @{ */

#define LCDIF_GAMMADATA0_BLUE_MASK               (0xFFU)
#define LCDIF_GAMMADATA0_BLUE_SHIFT              (0U)
/*! BLUE - Blue */
#define LCDIF_GAMMADATA0_BLUE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_BLUE_SHIFT)) & LCDIF_GAMMADATA0_BLUE_MASK)

#define LCDIF_GAMMADATA0_GREEN_MASK              (0xFF00U)
#define LCDIF_GAMMADATA0_GREEN_SHIFT             (8U)
/*! GREEN - Green */
#define LCDIF_GAMMADATA0_GREEN(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_GREEN_SHIFT)) & LCDIF_GAMMADATA0_GREEN_MASK)

#define LCDIF_GAMMADATA0_RED_MASK                (0xFF0000U)
#define LCDIF_GAMMADATA0_RED_SHIFT               (16U)
/*! RED - Red */
#define LCDIF_GAMMADATA0_RED(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_RED_SHIFT)) & LCDIF_GAMMADATA0_RED_MASK)
/*! @} */

/*! @name CURSORCONFIG - Cursor Configuration */
/*! @{ */

#define LCDIF_CURSORCONFIG_FORMAT_MASK           (0x3U)
#define LCDIF_CURSORCONFIG_FORMAT_SHIFT          (0U)
/*! FORMAT - Format
 *  0b00..Disables the format of a cursor.
 *  0b01..Sets the cursor in masked format, where the mask values of the AND and XOR bits decide the color of one cursor image pixel..
 *  0b10..Sets the cursor in A8R8G8B8 format, where the color of the cursor image is decided by the ARGB values fetched from the memory.
 */
#define LCDIF_CURSORCONFIG_FORMAT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_FORMAT_SHIFT)) & LCDIF_CURSORCONFIG_FORMAT_MASK)

#define LCDIF_CURSORCONFIG_HOT_SPOT_Y_MASK       (0x1F00U)
#define LCDIF_CURSORCONFIG_HOT_SPOT_Y_SHIFT      (8U)
/*! HOT_SPOT_Y - Vertical Hot Spot */
#define LCDIF_CURSORCONFIG_HOT_SPOT_Y(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_HOT_SPOT_Y_SHIFT)) & LCDIF_CURSORCONFIG_HOT_SPOT_Y_MASK)

#define LCDIF_CURSORCONFIG_HOT_SPOT_X_MASK       (0x1F0000U)
#define LCDIF_CURSORCONFIG_HOT_SPOT_X_SHIFT      (16U)
/*! HOT_SPOT_X - Horizontal Hot Spot */
#define LCDIF_CURSORCONFIG_HOT_SPOT_X(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_HOT_SPOT_X_SHIFT)) & LCDIF_CURSORCONFIG_HOT_SPOT_X_MASK)
/*! @} */

/*! @name CURSORADDRESS - Cursor Base Address */
/*! @{ */

#define LCDIF_CURSORADDRESS_ADDRESS_MASK         (0xFFFFFFFFU)
#define LCDIF_CURSORADDRESS_ADDRESS_SHIFT        (0U)
/*! ADDRESS - Base address */
#define LCDIF_CURSORADDRESS_ADDRESS(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORADDRESS_ADDRESS_SHIFT)) & LCDIF_CURSORADDRESS_ADDRESS_MASK)
/*! @} */

/*! @name CURSORLOCATION - Cursor Location */
/*! @{ */

#define LCDIF_CURSORLOCATION_X_MASK              (0x1FFFU)
#define LCDIF_CURSORLOCATION_X_SHIFT             (0U)
/*! X - X */
#define LCDIF_CURSORLOCATION_X(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORLOCATION_X_SHIFT)) & LCDIF_CURSORLOCATION_X_MASK)

#define LCDIF_CURSORLOCATION_Y_MASK              (0xFFF0000U)
#define LCDIF_CURSORLOCATION_Y_SHIFT             (16U)
/*! Y - Y */
#define LCDIF_CURSORLOCATION_Y(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORLOCATION_Y_SHIFT)) & LCDIF_CURSORLOCATION_Y_MASK)
/*! @} */

/*! @name CURSORBACKGROUND - Cursor Background Color */
/*! @{ */

#define LCDIF_CURSORBACKGROUND_BLUE_MASK         (0xFFU)
#define LCDIF_CURSORBACKGROUND_BLUE_SHIFT        (0U)
/*! BLUE - Blue */
#define LCDIF_CURSORBACKGROUND_BLUE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_BLUE_SHIFT)) & LCDIF_CURSORBACKGROUND_BLUE_MASK)

#define LCDIF_CURSORBACKGROUND_GREEN_MASK        (0xFF00U)
#define LCDIF_CURSORBACKGROUND_GREEN_SHIFT       (8U)
/*! GREEN - Green */
#define LCDIF_CURSORBACKGROUND_GREEN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_GREEN_SHIFT)) & LCDIF_CURSORBACKGROUND_GREEN_MASK)

#define LCDIF_CURSORBACKGROUND_RED_MASK          (0xFF0000U)
#define LCDIF_CURSORBACKGROUND_RED_SHIFT         (16U)
/*! RED - Red */
#define LCDIF_CURSORBACKGROUND_RED(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_RED_SHIFT)) & LCDIF_CURSORBACKGROUND_RED_MASK)
/*! @} */

/*! @name CURSORFOREGROUND - Cursor Foreground Color */
/*! @{ */

#define LCDIF_CURSORFOREGROUND_BLUE_MASK         (0xFFU)
#define LCDIF_CURSORFOREGROUND_BLUE_SHIFT        (0U)
/*! BLUE - Blue */
#define LCDIF_CURSORFOREGROUND_BLUE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_BLUE_SHIFT)) & LCDIF_CURSORFOREGROUND_BLUE_MASK)

#define LCDIF_CURSORFOREGROUND_GREEN_MASK        (0xFF00U)
#define LCDIF_CURSORFOREGROUND_GREEN_SHIFT       (8U)
/*! GREEN - Green */
#define LCDIF_CURSORFOREGROUND_GREEN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_GREEN_SHIFT)) & LCDIF_CURSORFOREGROUND_GREEN_MASK)

#define LCDIF_CURSORFOREGROUND_RED_MASK          (0xFF0000U)
#define LCDIF_CURSORFOREGROUND_RED_SHIFT         (16U)
/*! RED - Red */
#define LCDIF_CURSORFOREGROUND_RED(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_RED_SHIFT)) & LCDIF_CURSORFOREGROUND_RED_MASK)
/*! @} */

/*! @name DISPLAYINTR - Display Interrupt */
/*! @{ */

#define LCDIF_DISPLAYINTR_DISP0_MASK             (0x1U)
#define LCDIF_DISPLAYINTR_DISP0_SHIFT            (0U)
/*! DISP0 - Display_0 */
#define LCDIF_DISPLAYINTR_DISP0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_DISP0_SHIFT)) & LCDIF_DISPLAYINTR_DISP0_MASK)

#define LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR_MASK (0x1000U)
#define LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR_SHIFT (12U)
/*! DISP0_DBI_CFG_ERROR - Display_0 DBI Configure Error */
#define LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR_SHIFT)) & LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR_MASK)

#define LCDIF_DISPLAYINTR_PANEL_UNDERFLOW_MASK   (0x20000000U)
#define LCDIF_DISPLAYINTR_PANEL_UNDERFLOW_SHIFT  (29U)
/*! PANEL_UNDERFLOW - Panel Underflow */
#define LCDIF_DISPLAYINTR_PANEL_UNDERFLOW(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_PANEL_UNDERFLOW_SHIFT)) & LCDIF_DISPLAYINTR_PANEL_UNDERFLOW_MASK)

#define LCDIF_DISPLAYINTR_SOFT_RESET_DONE_MASK   (0x40000000U)
#define LCDIF_DISPLAYINTR_SOFT_RESET_DONE_SHIFT  (30U)
/*! SOFT_RESET_DONE - Soft Reset Done */
#define LCDIF_DISPLAYINTR_SOFT_RESET_DONE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_SOFT_RESET_DONE_SHIFT)) & LCDIF_DISPLAYINTR_SOFT_RESET_DONE_MASK)

#define LCDIF_DISPLAYINTR_BUS_ERROR_MASK         (0x80000000U)
#define LCDIF_DISPLAYINTR_BUS_ERROR_SHIFT        (31U)
/*! BUS_ERROR - Bus Error */
#define LCDIF_DISPLAYINTR_BUS_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_BUS_ERROR_SHIFT)) & LCDIF_DISPLAYINTR_BUS_ERROR_MASK)
/*! @} */

/*! @name DISPLAYINTRENABLE - Display Interrupt Enable */
/*! @{ */

#define LCDIF_DISPLAYINTRENABLE_DISP0_MASK       (0x1U)
#define LCDIF_DISPLAYINTRENABLE_DISP0_SHIFT      (0U)
/*! DISP0 - Display_0
 *  0b0..Enables Display_0 interrupt.
 *  0b1..Disables Display_0 interrupt.
 */
#define LCDIF_DISPLAYINTRENABLE_DISP0(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTRENABLE_DISP0_SHIFT)) & LCDIF_DISPLAYINTRENABLE_DISP0_MASK)

#define LCDIF_DISPLAYINTRENABLE_DISP0_DBI_CFG_ERROR_MASK (0x1000U)
#define LCDIF_DISPLAYINTRENABLE_DISP0_DBI_CFG_ERROR_SHIFT (12U)
/*! DISP0_DBI_CFG_ERROR - Display_0 DBI Configuration Error
 *  0b0..Enables Display_0 DBI configuration error.
 *  0b1..Disables Display_0 DBI configuration error.
 */
#define LCDIF_DISPLAYINTRENABLE_DISP0_DBI_CFG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTRENABLE_DISP0_DBI_CFG_ERROR_SHIFT)) & LCDIF_DISPLAYINTRENABLE_DISP0_DBI_CFG_ERROR_MASK)

#define LCDIF_DISPLAYINTRENABLE_PANEL_UNDERFLOW_MASK (0x20000000U)
#define LCDIF_DISPLAYINTRENABLE_PANEL_UNDERFLOW_SHIFT (29U)
/*! PANEL_UNDERFLOW - Panel Underflow
 *  0b0..Enables panel underflow interrupt.
 *  0b1..Disables panel underflow interrupt.
 */
#define LCDIF_DISPLAYINTRENABLE_PANEL_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTRENABLE_PANEL_UNDERFLOW_SHIFT)) & LCDIF_DISPLAYINTRENABLE_PANEL_UNDERFLOW_MASK)

#define LCDIF_DISPLAYINTRENABLE_SOFT_RESET_DONE_MASK (0x40000000U)
#define LCDIF_DISPLAYINTRENABLE_SOFT_RESET_DONE_SHIFT (30U)
/*! SOFT_RESET_DONE - Soft Reset Done
 *  0b0..Disables soft reset done interrupt.
 *  0b1..Enables soft reset done interrupt.
 */
#define LCDIF_DISPLAYINTRENABLE_SOFT_RESET_DONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTRENABLE_SOFT_RESET_DONE_SHIFT)) & LCDIF_DISPLAYINTRENABLE_SOFT_RESET_DONE_MASK)

#define LCDIF_DISPLAYINTRENABLE_BUS_ERROR_MASK   (0x80000000U)
#define LCDIF_DISPLAYINTRENABLE_BUS_ERROR_SHIFT  (31U)
/*! BUS_ERROR - Bus Error
 *  0b0..Enables bus error interrupt.
 *  0b1..Disables bus error interrupt.
 */
#define LCDIF_DISPLAYINTRENABLE_BUS_ERROR(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTRENABLE_BUS_ERROR_SHIFT)) & LCDIF_DISPLAYINTRENABLE_BUS_ERROR_MASK)
/*! @} */

/*! @name DBICONFIG0 - DBI Configuration */
/*! @{ */

#define LCDIF_DBICONFIG0_DBI_TYPE_MASK           (0x3U)
#define LCDIF_DBICONFIG0_DBI_TYPE_SHIFT          (0U)
/*! DBI_TYPE - DBI Type
 *  0b00..Selects DBI Type A Fixed E mode.
 *  0b01..Selects DBI Type A Clocked E mode.
 *  0b10..Selects DBI type B.
 */
#define LCDIF_DBICONFIG0_DBI_TYPE(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_TYPE_SHIFT)) & LCDIF_DBICONFIG0_DBI_TYPE_MASK)

#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT_MASK    (0x3CU)
#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT_SHIFT   (2U)
/*! DBI_DATA_FORMAT - DBI Data Format
 *  0b0000..D8R3G3B2
 *  0b0001..D8R4G4B4
 *  0b0010..D8R5G6B5
 *  0b0011..D8R6G6B6
 *  0b0100..D8R8G8B8
 *  0b0101..D9R6G6B6
 *  0b0110..D16R3G3B2
 *  0b0111..D16R4G4B4
 *  0b1000..D16R5G6B5
 *  0b1001..D16_R6_G6_B6_OP1
 *  0b1010..D16_R6_G6_B6_OP2
 *  0b1011..D16_R8_G8_B8_OP1
 *  0b1100..D16_R8_G8_B8_OP2
 */
#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_DATA_FORMAT_SHIFT)) & LCDIF_DBICONFIG0_DBI_DATA_FORMAT_MASK)

#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_MASK     (0x40U)
#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_SHIFT    (6U)
/*! BUS_OUTPUT_SEL - Output Bus Select
 *  0b0..Uses DPI bus.
 *  0b1..Uses DBI bus.
 */
#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_SHIFT)) & LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_MASK)

#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_MASK   (0xF00U)
#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_SHIFT  (8U)
/*! DBI_AC_TIME_UNIT - DBI AC Time Unit */
#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_SHIFT)) & LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_MASK)

#define LCDIF_DBICONFIG0_DBI_OUTPUT_SWIZZLE_MASK (0x8000000U)
#define LCDIF_DBICONFIG0_DBI_OUTPUT_SWIZZLE_SHIFT (27U)
/*! DBI_OUTPUT_SWIZZLE - DBIT Output Swizzle Set
 *  0b0..RGB
 *  0b1..BGR
 */
#define LCDIF_DBICONFIG0_DBI_OUTPUT_SWIZZLE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_OUTPUT_SWIZZLE_SHIFT)) & LCDIF_DBICONFIG0_DBI_OUTPUT_SWIZZLE_MASK)
/*! @} */

/*! @name DBIIFRESET0 - DBI Interface Reset */
/*! @{ */

#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_MASK (0x1U)
#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_SHIFT (0U)
/*! DBI_IF_LEVEL_RESET - DBI Interface Level Reset
 *  0b1..Resets the DBI bus in idle state.
 */
#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_SHIFT)) & LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_MASK)
/*! @} */

/*! @name DBIWRCHAR10 - DBI Write AC Characteristics 1 */
/*! @{ */

#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_MASK     (0xFFU)
#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_SHIFT    (0U)
/*! DBI_WR_PERIOD - DBI Write Period */
#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_MASK)

#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_MASK (0xF00U)
#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_SHIFT (8U)
/*! DBI_WR_EOR_WR_ASSERT - DBI Clock E Signal or WRX Signal Assert */
#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_MASK)

#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_MASK  (0xF000U)
#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_SHIFT (12U)
/*! DBI_WR_CS_ASSERT - DBI Write CS Assert */
#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_MASK)
/*! @} */

/*! @name DBIWRCHAR20 - DBI Write AC Characteristics 2 */
/*! @{ */

#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_MASK (0xFFU)
#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_SHIFT (0U)
/*! DBI_WR_EOR_WR_DE_ASRT - DBI Clock E Signal or WRX Signal Desert Assert */
#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_SHIFT)) & LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_MASK)

#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_MASK (0xFF00U)
#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_SHIFT (8U)
/*! DBI_WR_CS_DE_ASRT - DBI Write CS De-assert */
#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_SHIFT)) & LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_MASK)
/*! @} */

/*! @name DBICMD0 - DBI Command Control */
/*! @{ */

#define LCDIF_DBICMD0_DBI_COMMAND_WORD_MASK      (0xFFFFU)
#define LCDIF_DBICMD0_DBI_COMMAND_WORD_SHIFT     (0U)
/*! DBI_COMMAND_WORD - DBI Command Word */
#define LCDIF_DBICMD0_DBI_COMMAND_WORD(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICMD0_DBI_COMMAND_WORD_SHIFT)) & LCDIF_DBICMD0_DBI_COMMAND_WORD_MASK)

#define LCDIF_DBICMD0_DBI_COMMANDFLAG_MASK       (0xC0000000U)
#define LCDIF_DBICMD0_DBI_COMMANDFLAG_SHIFT      (30U)
/*! DBI_COMMANDFLAG - DBI Command Flag
 *  0b00..Address
 *  0b01..Write Memory Start
 *  0b10..Parameter or Data
 */
#define LCDIF_DBICMD0_DBI_COMMANDFLAG(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICMD0_DBI_COMMANDFLAG_SHIFT)) & LCDIF_DBICMD0_DBI_COMMANDFLAG_MASK)
/*! @} */

/*! @name DPICONFIG0 - DPI Configuration */
/*! @{ */

#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT_MASK    (0x7U)
#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT_SHIFT   (0U)
/*! DPI_DATA_FORMAT - DPI Data Format
 *  0b000..D16CFG1
 *  0b001..D16CFG2
 *  0b010..D16CFG3
 *  0b011..D18CFG1
 *  0b100..D18CFG2
 *  0b101..D24
 */
#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DPICONFIG0_DPI_DATA_FORMAT_SHIFT)) & LCDIF_DPICONFIG0_DPI_DATA_FORMAT_MASK)

#define LCDIF_DPICONFIG0_DPI_COMMAND_MODE_MASK   (0x10U)
#define LCDIF_DPICONFIG0_DPI_COMMAND_MODE_SHIFT  (4U)
/*! DPI_COMMAND_MODE - DPI Command Mode
 *  0b0..Disables the DPI command mode.
 *  0b1..Enables the DPI command mode.
 */
#define LCDIF_DPICONFIG0_DPI_COMMAND_MODE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DPICONFIG0_DPI_COMMAND_MODE_SHIFT)) & LCDIF_DPICONFIG0_DPI_COMMAND_MODE_MASK)
/*! @} */

/*! @name SRCCONFIGENDIAN - Source Endian Configuration */
/*! @{ */

#define LCDIF_SRCCONFIGENDIAN_CONTROL_MASK       (0x3U)
#define LCDIF_SRCCONFIGENDIAN_CONTROL_SHIFT      (0U)
/*! CONTROL - Control
 *  0b00..No Swap
 *  0b01..Swap Word
 *  0b10..Swap Dword
 */
#define LCDIF_SRCCONFIGENDIAN_CONTROL(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_SRCCONFIGENDIAN_CONTROL_SHIFT)) & LCDIF_SRCCONFIGENDIAN_CONTROL_MASK)
/*! @} */

/*! @name SOFTRESET - Soft Reset */
/*! @{ */

#define LCDIF_SOFTRESET_RESET_MASK               (0x1U)
#define LCDIF_SOFTRESET_RESET_SHIFT              (0U)
/*! RESET - Reset Display Controller
 *  0b0..Disable
 *  0b1..Enable
 */
#define LCDIF_SOFTRESET_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_SOFTRESET_RESET_SHIFT)) & LCDIF_SOFTRESET_RESET_MASK)
/*! @} */

/*! @name DCCONTROL - Display Controller Control */
/*! @{ */

#define LCDIF_DCCONTROL_DEBUG_REGISTER_MASK      (0x8U)
#define LCDIF_DCCONTROL_DEBUG_REGISTER_SHIFT     (3U)
/*! DEBUG_REGISTER - Debug
 *  0b0..Disables debug.
 *  0b1..Enables debug.
 */
#define LCDIF_DCCONTROL_DEBUG_REGISTER(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCONTROL_DEBUG_REGISTER_SHIFT)) & LCDIF_DCCONTROL_DEBUG_REGISTER_MASK)

#define LCDIF_DCCONTROL_RAM_CLOCK_GATING_MASK    (0x10U)
#define LCDIF_DCCONTROL_RAM_CLOCK_GATING_SHIFT   (4U)
/*! RAM_CLOCK_GATING - Enables or disables RAM clock gating.
 *  0b0..Disables RAM clock gating.
 *  0b1..Enables RAM clock gating.
 */
#define LCDIF_DCCONTROL_RAM_CLOCK_GATING(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCONTROL_RAM_CLOCK_GATING_SHIFT)) & LCDIF_DCCONTROL_RAM_CLOCK_GATING_MASK)
/*! @} */

/*! @name LAYERCLOCKGATE - Layer Clock Gating */
/*! @{ */

#define LCDIF_LAYERCLOCKGATE_DISABLE_VIDEO_CLK_MASK (0x1U)
#define LCDIF_LAYERCLOCKGATE_DISABLE_VIDEO_CLK_SHIFT (0U)
/*! DISABLE_VIDEO_CLK - Disable Video Clock
 *  0b0..Disables clock gating on the VG layer.
 *  0b1..Enables clock gating on the VG layer.
 */
#define LCDIF_LAYERCLOCKGATE_DISABLE_VIDEO_CLK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LAYERCLOCKGATE_DISABLE_VIDEO_CLK_SHIFT)) & LCDIF_LAYERCLOCKGATE_DISABLE_VIDEO_CLK_MASK)

#define LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY0_CLK_MASK (0x2U)
#define LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY0_CLK_SHIFT (1U)
/*! DISABLE_OVERLAY0_CLK - Disable Overlay 0 Clock
 *  0b0..Disables clock gating on the overlay 0 layer.
 *  0b1..Enables clock gating on the overlay 0 layer.
 */
#define LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY0_CLK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY0_CLK_SHIFT)) & LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY0_CLK_MASK)

#define LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY1_CLK_MASK (0x4U)
#define LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY1_CLK_SHIFT (2U)
/*! DISABLE_OVERLAY1_CLK - Disable Overlay 1 Clock
 *  0b0..Disables clock gating on the overlay 1 layer.
 *  0b1..Enables clock gating on the overlay 1 layer.
 */
#define LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY1_CLK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY1_CLK_SHIFT)) & LCDIF_LAYERCLOCKGATE_DISABLE_OVERLAY1_CLK_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LCDIF_Register_Masks */


/* LCDIF - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LCDIF base address */
  #define LCDIF_BASE                               (0x50480000u)
  /** Peripheral LCDIF base address */
  #define LCDIF_BASE_NS                            (0x40480000u)
  /** Peripheral LCDIF base pointer */
  #define LCDIF                                    ((LCDIF_Type *)LCDIF_BASE)
  /** Peripheral LCDIF base pointer */
  #define LCDIF_NS                                 ((LCDIF_Type *)LCDIF_BASE_NS)
  /** Array initializer of LCDIF peripheral base addresses */
  #define LCDIF_BASE_ADDRS                         { LCDIF_BASE }
  /** Array initializer of LCDIF peripheral base pointers */
  #define LCDIF_BASE_PTRS                          { LCDIF }
  /** Array initializer of LCDIF peripheral base addresses */
  #define LCDIF_BASE_ADDRS_NS                      { LCDIF_BASE_NS }
  /** Array initializer of LCDIF peripheral base pointers */
  #define LCDIF_BASE_PTRS_NS                       { LCDIF_NS }
#else
  /** Peripheral LCDIF base address */
  #define LCDIF_BASE                               (0x40480000u)
  /** Peripheral LCDIF base pointer */
  #define LCDIF                                    ((LCDIF_Type *)LCDIF_BASE)
  /** Array initializer of LCDIF peripheral base addresses */
  #define LCDIF_BASE_ADDRS                         { LCDIF_BASE }
  /** Array initializer of LCDIF peripheral base pointers */
  #define LCDIF_BASE_PTRS                          { LCDIF }
#endif
/** Interrupt vectors for the LCDIF peripheral type */
#define LCDIF_IRQS                               { LCDIF_IRQn }

/*!
 * @}
 */ /* end of group LCDIF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPI2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
 * @{
 */

/** LPI2C - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t MCR;                               /**< Controller Control, offset: 0x10 */
  __IO uint32_t MSR;                               /**< Controller Status, offset: 0x14 */
  __IO uint32_t MIER;                              /**< Controller Interrupt Enable, offset: 0x18 */
  __IO uint32_t MDER;                              /**< Controller DMA Enable, offset: 0x1C */
  __IO uint32_t MCFGR0;                            /**< Controller Configuration 0, offset: 0x20 */
  __IO uint32_t MCFGR1;                            /**< Controller Configuration 1, offset: 0x24 */
  __IO uint32_t MCFGR2;                            /**< Controller Configuration 2, offset: 0x28 */
  __IO uint32_t MCFGR3;                            /**< Controller Configuration 3, offset: 0x2C */
       uint8_t RESERVED_1[16];
  __IO uint32_t MDMR;                              /**< Controller Data Match, offset: 0x40 */
       uint8_t RESERVED_2[4];
  __IO uint32_t MCCR0;                             /**< Controller Clock Configuration 0, offset: 0x48 */
       uint8_t RESERVED_3[4];
  __IO uint32_t MCCR1;                             /**< Controller Clock Configuration 1, offset: 0x50 */
       uint8_t RESERVED_4[4];
  __IO uint32_t MFCR;                              /**< Controller FIFO Control, offset: 0x58 */
  __I  uint32_t MFSR;                              /**< Controller FIFO Status, offset: 0x5C */
  __O  uint32_t MTDR;                              /**< Controller Transmit Data, offset: 0x60 */
       uint8_t RESERVED_5[12];
  __I  uint32_t MRDR;                              /**< Controller Receive Data, offset: 0x70 */
       uint8_t RESERVED_6[4];
  __I  uint32_t MRDROR;                            /**< Controller Receive Data Read Only, offset: 0x78 */
       uint8_t RESERVED_7[148];
  __IO uint32_t SCR;                               /**< Target Control, offset: 0x110, not available in all instances (available on 28 out of 30) */
  __IO uint32_t SSR;                               /**< Target Status, offset: 0x114, not available in all instances (available on 28 out of 30) */
  __IO uint32_t SIER;                              /**< Target Interrupt Enable, offset: 0x118, not available in all instances (available on 28 out of 30) */
  __IO uint32_t SDER;                              /**< Target DMA Enable, offset: 0x11C, not available in all instances (available on 28 out of 30) */
  __IO uint32_t SCFGR0;                            /**< Target Configuration 0, offset: 0x120, not available in all instances (available on 28 out of 30) */
  __IO uint32_t SCFGR1;                            /**< Target Configuration 1, offset: 0x124, not available in all instances (available on 28 out of 30) */
  __IO uint32_t SCFGR2;                            /**< Target Configuration 2, offset: 0x128, not available in all instances (available on 28 out of 30) */
       uint8_t RESERVED_8[20];
  __IO uint32_t SAMR;                              /**< Target Address Match, offset: 0x140, not available in all instances (available on 28 out of 30) */
       uint8_t RESERVED_9[12];
  __I  uint32_t SASR;                              /**< Target Address Status, offset: 0x150, not available in all instances (available on 28 out of 30) */
  __IO uint32_t STAR;                              /**< Target Transmit ACK, offset: 0x154, not available in all instances (available on 28 out of 30) */
       uint8_t RESERVED_10[8];
  __O  uint32_t STDR;                              /**< Target Transmit Data, offset: 0x160, not available in all instances (available on 28 out of 30) */
       uint8_t RESERVED_11[12];
  __I  uint32_t SRDR;                              /**< Target Receive Data, offset: 0x170, not available in all instances (available on 28 out of 30) */
       uint8_t RESERVED_12[4];
  __I  uint32_t SRDROR;                            /**< Target Receive Data Read Only, offset: 0x178, not available in all instances (available on 28 out of 30) */
       uint8_t RESERVED_13[132];
  __O  uint32_t MTCBR[128];                        /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */
  __O  uint32_t MTDBR[256];                        /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
} LPI2C_Type;

/* ----------------------------------------------------------------------------
   -- LPI2C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPI2C_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000010..Controller only, with standard feature set
 *  0b0000000000000011..Controller and target, with standard feature set
 */
#define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

#define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
#define LPI2C_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number */
#define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

#define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPI2C_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number */
#define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
#define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
/*! MTXFIFO - Controller Transmit FIFO Size */
#define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

#define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
#define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
/*! MRXFIFO - Controller Receive FIFO Size */
#define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
/*! @} */

/*! @name MCR - Controller Control */
/*! @{ */

#define LPI2C_MCR_MEN_MASK                       (0x1U)
#define LPI2C_MCR_MEN_SHIFT                      (0U)
/*! MEN - Controller Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

#define LPI2C_MCR_RST_MASK                       (0x2U)
#define LPI2C_MCR_RST_SHIFT                      (1U)
/*! RST - Software Reset
 *  0b0..No effect
 *  0b1..Reset
 */
#define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

#define LPI2C_MCR_DOZEN_MASK                     (0x4U)
#define LPI2C_MCR_DOZEN_SHIFT                    (2U)
/*! DOZEN - Doze Mode Enable
 *  0b0..Enable
 *  0b1..Disable
 */
#define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

#define LPI2C_MCR_DBGEN_MASK                     (0x8U)
#define LPI2C_MCR_DBGEN_SHIFT                    (3U)
/*! DBGEN - Debug Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

#define LPI2C_MCR_RTF_MASK                       (0x100U)
#define LPI2C_MCR_RTF_SHIFT                      (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Reset transmit FIFO
 */
#define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

#define LPI2C_MCR_RRF_MASK                       (0x200U)
#define LPI2C_MCR_RRF_SHIFT                      (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Reset receive FIFO
 */
#define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
/*! @} */

/*! @name MSR - Controller Status */
/*! @{ */

#define LPI2C_MSR_TDF_MASK                       (0x1U)
#define LPI2C_MSR_TDF_SHIFT                      (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data requested
 */
#define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

#define LPI2C_MSR_RDF_MASK                       (0x2U)
#define LPI2C_MSR_RDF_SHIFT                      (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive data not ready
 *  0b1..Receive data ready
 */
#define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

#define LPI2C_MSR_EPF_MASK                       (0x100U)
#define LPI2C_MSR_EPF_SHIFT                      (8U)
/*! EPF - End Packet Flag
 *  0b0..No Stop or repeated Start generated
 *  0b1..Stop or repeated Start generated
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

#define LPI2C_MSR_SDF_MASK                       (0x200U)
#define LPI2C_MSR_SDF_SHIFT                      (9U)
/*! SDF - Stop Detect Flag
 *  0b0..No Stop condition generated
 *  0b1..Stop condition generated
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

#define LPI2C_MSR_NDF_MASK                       (0x400U)
#define LPI2C_MSR_NDF_SHIFT                      (10U)
/*! NDF - NACK Detect Flag
 *  0b0..No unexpected NACK detected
 *  0b1..Unexpected NACK detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

#define LPI2C_MSR_ALF_MASK                       (0x800U)
#define LPI2C_MSR_ALF_SHIFT                      (11U)
/*! ALF - Arbitration Lost Flag
 *  0b0..Controller did not lose arbitration
 *  0b1..Controller lost arbitration
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

#define LPI2C_MSR_FEF_MASK                       (0x1000U)
#define LPI2C_MSR_FEF_SHIFT                      (12U)
/*! FEF - FIFO Error Flag
 *  0b0..No FIFO error
 *  0b1..FIFO error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

#define LPI2C_MSR_PLTF_MASK                      (0x2000U)
#define LPI2C_MSR_PLTF_SHIFT                     (13U)
/*! PLTF - Pin Low Timeout Flag
 *  0b0..Pin low timeout did not occur
 *  0b1..Pin low timeout occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

#define LPI2C_MSR_DMF_MASK                       (0x4000U)
#define LPI2C_MSR_DMF_SHIFT                      (14U)
/*! DMF - Data Match Flag
 *  0b0..Matching data not received
 *  0b1..Matching data received
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

#define LPI2C_MSR_STF_MASK                       (0x8000U)
#define LPI2C_MSR_STF_SHIFT                      (15U)
/*! STF - Start Flag
 *  0b0..Start condition not detected
 *  0b1..Start condition detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_MSR_STF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK)

#define LPI2C_MSR_MBF_MASK                       (0x1000000U)
#define LPI2C_MSR_MBF_SHIFT                      (24U)
/*! MBF - Controller Busy Flag
 *  0b0..Idle
 *  0b1..Busy
 */
#define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

#define LPI2C_MSR_BBF_MASK                       (0x2000000U)
#define LPI2C_MSR_BBF_SHIFT                      (25U)
/*! BBF - Bus Busy Flag
 *  0b0..Idle
 *  0b1..Busy
 */
#define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
/*! @} */

/*! @name MIER - Controller Interrupt Enable */
/*! @{ */

#define LPI2C_MIER_TDIE_MASK                     (0x1U)
#define LPI2C_MIER_TDIE_SHIFT                    (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

#define LPI2C_MIER_RDIE_MASK                     (0x2U)
#define LPI2C_MIER_RDIE_SHIFT                    (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

#define LPI2C_MIER_EPIE_MASK                     (0x100U)
#define LPI2C_MIER_EPIE_SHIFT                    (8U)
/*! EPIE - End Packet Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

#define LPI2C_MIER_SDIE_MASK                     (0x200U)
#define LPI2C_MIER_SDIE_SHIFT                    (9U)
/*! SDIE - Stop Detect Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

#define LPI2C_MIER_NDIE_MASK                     (0x400U)
#define LPI2C_MIER_NDIE_SHIFT                    (10U)
/*! NDIE - NACK Detect Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

#define LPI2C_MIER_ALIE_MASK                     (0x800U)
#define LPI2C_MIER_ALIE_SHIFT                    (11U)
/*! ALIE - Arbitration Lost Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

#define LPI2C_MIER_FEIE_MASK                     (0x1000U)
#define LPI2C_MIER_FEIE_SHIFT                    (12U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

#define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
#define LPI2C_MIER_PLTIE_SHIFT                   (13U)
/*! PLTIE - Pin Low Timeout Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

#define LPI2C_MIER_DMIE_MASK                     (0x4000U)
#define LPI2C_MIER_DMIE_SHIFT                    (14U)
/*! DMIE - Data Match Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)

#define LPI2C_MIER_STIE_MASK                     (0x8000U)
#define LPI2C_MIER_STIE_SHIFT                    (15U)
/*! STIE - Start Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MIER_STIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK)
/*! @} */

/*! @name MDER - Controller DMA Enable */
/*! @{ */

#define LPI2C_MDER_TDDE_MASK                     (0x1U)
#define LPI2C_MDER_TDDE_SHIFT                    (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

#define LPI2C_MDER_RDDE_MASK                     (0x2U)
#define LPI2C_MDER_RDDE_SHIFT                    (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
/*! @} */

/*! @name MCFGR0 - Controller Configuration 0 */
/*! @{ */

#define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
#define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
/*! HREN - Host Request Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

#define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
#define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
/*! HRPOL - Host Request Polarity
 *  0b0..Active low
 *  0b1..Active high
 */
#define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

#define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
#define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
/*! HRSEL - Host Request Select
 *  0b0..Host request input is pin HREQ
 *  0b1..Host request input is input trigger
 */
#define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

#define LPI2C_MCFGR0_HRDIR_MASK                  (0x8U)
#define LPI2C_MCFGR0_HRDIR_SHIFT                 (3U)
/*! HRDIR - Host Request Direction
 *  0b0..HREQ pin is input (for LPI2C controller)
 *  0b1..HREQ pin is output (for LPI2C target)
 */
#define LPI2C_MCFGR0_HRDIR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK)

#define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
#define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
/*! CIRFIFO - Circular FIFO Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

#define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
#define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
/*! RDMO - Receive Data Match Only
 *  0b0..Received data is stored in the receive FIFO
 *  0b1..Received data is discarded unless MSR[DMF] is set
 */
#define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)

#define LPI2C_MCFGR0_RELAX_MASK                  (0x10000U)
#define LPI2C_MCFGR0_RELAX_SHIFT                 (16U)
/*! RELAX - Relaxed Mode
 *  0b0..Normal transfer
 *  0b1..Relaxed transfer
 */
#define LPI2C_MCFGR0_RELAX(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK)

#define LPI2C_MCFGR0_ABORT_MASK                  (0x20000U)
#define LPI2C_MCFGR0_ABORT_SHIFT                 (17U)
/*! ABORT - Abort Transfer
 *  0b0..Normal transfer
 *  0b1..Abort existing transfer and do not start a new one
 */
#define LPI2C_MCFGR0_ABORT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK)
/*! @} */

/*! @name MCFGR1 - Controller Configuration 1 */
/*! @{ */

#define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
#define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
/*! PRESCALE - Prescaler
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

#define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
/*! AUTOSTOP - Automatic Stop Generation
 *  0b0..No effect
 *  0b1..Stop automatically generated
 */
#define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

#define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
#define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
/*! IGNACK - Ignore NACK
 *  0b0..No effect
 *  0b1..Treat a received NACK as an ACK
 */
#define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

#define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
#define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
/*! TIMECFG - Timeout Configuration
 *  0b0..SCL
 *  0b1..SCL or SDA
 */
#define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

#define LPI2C_MCFGR1_STOPCFG_MASK                (0x800U)
#define LPI2C_MCFGR1_STOPCFG_SHIFT               (11U)
/*! STOPCFG - Stop Configuration
 *  0b0..Any Stop condition
 *  0b1..Last Stop condition
 */
#define LPI2C_MCFGR1_STOPCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK)

#define LPI2C_MCFGR1_STARTCFG_MASK               (0x1000U)
#define LPI2C_MCFGR1_STARTCFG_SHIFT              (12U)
/*! STARTCFG - Start Configuration
 *  0b0..Sets when both I2C bus and LPI2C controller are idle
 *  0b1..Sets when I2C bus is idle
 */
#define LPI2C_MCFGR1_STARTCFG(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK)

#define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
#define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
/*! MATCFG - Match Configuration
 *  0b000..Match is disabled
 *  0b001..Reserved
 *  0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1]
 *  0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1]
 *  0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1)
 *  0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1)
 *  0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
 *  0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
 */
#define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

#define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
#define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
/*! PINCFG - Pin Configuration
 *  0b000..Two-pin open drain mode
 *  0b001..Two-pin output only mode (Ultra-Fast mode)
 *  0b010..Two-pin push-pull mode
 *  0b011..Four-pin push-pull mode
 *  0b100..Two-pin open-drain mode with separate LPI2C target
 *  0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target
 *  0b110..Two-pin push-pull mode with separate LPI2C target
 *  0b111..Four-pin push-pull mode (inverted outputs)
 */
#define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

#define LPI2C_MCFGR1_FRCHS_MASK                  (0x8000000U)
#define LPI2C_MCFGR1_FRCHS_SHIFT                 (27U)
/*! FRCHS - Force HS Mode
 *  0b0..No effect
 *  0b1..LPI2C pin state forced into HS mode
 */
#define LPI2C_MCFGR1_FRCHS(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_FRCHS_SHIFT)) & LPI2C_MCFGR1_FRCHS_MASK)
/*! @} */

/*! @name MCFGR2 - Controller Configuration 2 */
/*! @{ */

#define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
#define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
/*! BUSIDLE - Bus Idle Timeout */
#define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

#define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
#define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
/*! FILTSCL - Glitch Filter SCL */
#define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

#define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
#define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
/*! FILTSDA - Glitch Filter SDA */
#define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
/*! @} */

/*! @name MCFGR3 - Controller Configuration 3 */
/*! @{ */

#define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
#define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
/*! PINLOW - Pin Low Timeout */
#define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
/*! @} */

/*! @name MDMR - Controller Data Match */
/*! @{ */

#define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
#define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
/*! MATCH0 - Match 0 Value */
#define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

#define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
#define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
/*! MATCH1 - Match 1 Value */
#define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
/*! @} */

/*! @name MCCR0 - Controller Clock Configuration 0 */
/*! @{ */

#define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
#define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
/*! CLKLO - Clock Low Period */
#define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

#define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
#define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
/*! CLKHI - Clock High Period */
#define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

#define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
#define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
/*! SETHOLD - Setup Hold Delay */
#define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

#define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
#define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
/*! DATAVD - Data Valid Delay */
#define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
/*! @} */

/*! @name MCCR1 - Controller Clock Configuration 1 */
/*! @{ */

#define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
#define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
/*! CLKLO - Clock Low Period */
#define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

#define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
#define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
/*! CLKHI - Clock High Period */
#define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

#define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
#define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
/*! SETHOLD - Setup Hold Delay */
#define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

#define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
#define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
/*! DATAVD - Data Valid Delay */
#define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
/*! @} */

/*! @name MFCR - Controller FIFO Control */
/*! @{ */

#define LPI2C_MFCR_TXWATER_MASK                  (0x7U)
#define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
/*! TXWATER - Transmit FIFO Watermark */
#define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

#define LPI2C_MFCR_RXWATER_MASK                  (0x70000U)
#define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
/*! RXWATER - Receive FIFO Watermark */
#define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
/*! @} */

/*! @name MFSR - Controller FIFO Status */
/*! @{ */

#define LPI2C_MFSR_TXCOUNT_MASK                  (0xFU)
#define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
/*! TXCOUNT - Transmit FIFO Count */
#define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

#define LPI2C_MFSR_RXCOUNT_MASK                  (0xF0000U)
#define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
/*! RXCOUNT - Receive FIFO Count */
#define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
/*! @} */

/*! @name MTDR - Controller Transmit Data */
/*! @{ */

#define LPI2C_MTDR_DATA_MASK                     (0xFFU)
#define LPI2C_MTDR_DATA_SHIFT                    (0U)
/*! DATA - Transmit Data */
#define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

#define LPI2C_MTDR_CMD_MASK                      (0x700U)
#define LPI2C_MTDR_CMD_SHIFT                     (8U)
/*! CMD - Command Data
 *  0b000..Transmit the value in DATA[7:0]
 *  0b001..Receive (DATA[7:0] + 1) bytes
 *  0b010..Generate Stop condition on I2C bus
 *  0b011..Receive and discard (DATA[7:0] + 1) bytes
 *  0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0]
 *  0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned)
 *  0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode
 *  0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned)
 */
#define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
/*! @} */

/*! @name MRDR - Controller Receive Data */
/*! @{ */

#define LPI2C_MRDR_DATA_MASK                     (0xFFU)
#define LPI2C_MRDR_DATA_SHIFT                    (0U)
/*! DATA - Receive Data */
#define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

#define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
#define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
/*! RXEMPTY - Receive Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
/*! @} */

/*! @name MRDROR - Controller Receive Data Read Only */
/*! @{ */

#define LPI2C_MRDROR_DATA_MASK                   (0xFFU)
#define LPI2C_MRDROR_DATA_SHIFT                  (0U)
/*! DATA - Receive Data */
#define LPI2C_MRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK)

#define LPI2C_MRDROR_RXEMPTY_MASK                (0x4000U)
#define LPI2C_MRDROR_RXEMPTY_SHIFT               (14U)
/*! RXEMPTY - RX Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define LPI2C_MRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK)
/*! @} */

/*! @name SCR - Target Control */
/*! @{ */

#define LPI2C_SCR_SEN_MASK                       (0x1U)
#define LPI2C_SCR_SEN_SHIFT                      (0U)
/*! SEN - Target Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

#define LPI2C_SCR_RST_MASK                       (0x2U)
#define LPI2C_SCR_RST_SHIFT                      (1U)
/*! RST - Software Reset
 *  0b0..Not reset
 *  0b1..Reset
 */
#define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

#define LPI2C_SCR_FILTEN_MASK                    (0x10U)
#define LPI2C_SCR_FILTEN_SHIFT                   (4U)
/*! FILTEN - Filter Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

#define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
#define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
/*! FILTDZ - Filter Doze Enable
 *  0b0..Enable
 *  0b1..Disable
 */
#define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

#define LPI2C_SCR_RTF_MASK                       (0x100U)
#define LPI2C_SCR_RTF_SHIFT                      (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..STDR is now empty
 */
#define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

#define LPI2C_SCR_RRF_MASK                       (0x200U)
#define LPI2C_SCR_RRF_SHIFT                      (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..SRDR is now empty
 */
#define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
/*! @} */

/*! @name SSR - Target Status */
/*! @{ */

#define LPI2C_SSR_TDF_MASK                       (0x1U)
#define LPI2C_SSR_TDF_SHIFT                      (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data is requested
 */
#define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

#define LPI2C_SSR_RDF_MASK                       (0x2U)
#define LPI2C_SSR_RDF_SHIFT                      (1U)
/*! RDF - Receive Data Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

#define LPI2C_SSR_AVF_MASK                       (0x4U)
#define LPI2C_SSR_AVF_SHIFT                      (2U)
/*! AVF - Address Valid Flag
 *  0b0..Not valid
 *  0b1..Valid
 */
#define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

#define LPI2C_SSR_TAF_MASK                       (0x8U)
#define LPI2C_SSR_TAF_SHIFT                      (3U)
/*! TAF - Transmit ACK Flag
 *  0b0..Not required
 *  0b1..Required
 */
#define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

#define LPI2C_SSR_RSF_MASK                       (0x100U)
#define LPI2C_SSR_RSF_SHIFT                      (8U)
/*! RSF - Repeated Start Flag
 *  0b0..No repeated Start detected
 *  0b1..Repeated Start detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

#define LPI2C_SSR_SDF_MASK                       (0x200U)
#define LPI2C_SSR_SDF_SHIFT                      (9U)
/*! SDF - Stop Detect Flag
 *  0b0..No Stop detected
 *  0b1..Stop detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

#define LPI2C_SSR_BEF_MASK                       (0x400U)
#define LPI2C_SSR_BEF_SHIFT                      (10U)
/*! BEF - Bit Error Flag
 *  0b0..No bit error occurred
 *  0b1..Bit error occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

#define LPI2C_SSR_FEF_MASK                       (0x800U)
#define LPI2C_SSR_FEF_SHIFT                      (11U)
/*! FEF - FIFO Error Flag
 *  0b0..No FIFO error
 *  0b1..FIFO error
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

#define LPI2C_SSR_AM0F_MASK                      (0x1000U)
#define LPI2C_SSR_AM0F_SHIFT                     (12U)
/*! AM0F - Address Match 0 Flag
 *  0b0..ADDR0 matching address not received
 *  0b1..ADDR0 matching address received
 */
#define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

#define LPI2C_SSR_AM1F_MASK                      (0x2000U)
#define LPI2C_SSR_AM1F_SHIFT                     (13U)
/*! AM1F - Address Match 1 Flag
 *  0b0..Matching address not received
 *  0b1..Matching address received
 */
#define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

#define LPI2C_SSR_GCF_MASK                       (0x4000U)
#define LPI2C_SSR_GCF_SHIFT                      (14U)
/*! GCF - General Call Flag
 *  0b0..General call address disabled or not detected
 *  0b1..General call address detected
 */
#define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

#define LPI2C_SSR_SARF_MASK                      (0x8000U)
#define LPI2C_SSR_SARF_SHIFT                     (15U)
/*! SARF - SMBus Alert Response Flag
 *  0b0..Disabled or not detected
 *  0b1..Enabled and detected
 */
#define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

#define LPI2C_SSR_SBF_MASK                       (0x1000000U)
#define LPI2C_SSR_SBF_SHIFT                      (24U)
/*! SBF - Target Busy Flag
 *  0b0..Idle
 *  0b1..Busy
 */
#define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

#define LPI2C_SSR_BBF_MASK                       (0x2000000U)
#define LPI2C_SSR_BBF_SHIFT                      (25U)
/*! BBF - Bus Busy Flag
 *  0b0..Idle
 *  0b1..Busy
 */
#define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
/*! @} */

/*! @name SIER - Target Interrupt Enable */
/*! @{ */

#define LPI2C_SIER_TDIE_MASK                     (0x1U)
#define LPI2C_SIER_TDIE_SHIFT                    (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

#define LPI2C_SIER_RDIE_MASK                     (0x2U)
#define LPI2C_SIER_RDIE_SHIFT                    (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

#define LPI2C_SIER_AVIE_MASK                     (0x4U)
#define LPI2C_SIER_AVIE_SHIFT                    (2U)
/*! AVIE - Address Valid Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

#define LPI2C_SIER_TAIE_MASK                     (0x8U)
#define LPI2C_SIER_TAIE_SHIFT                    (3U)
/*! TAIE - Transmit ACK Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

#define LPI2C_SIER_RSIE_MASK                     (0x100U)
#define LPI2C_SIER_RSIE_SHIFT                    (8U)
/*! RSIE - Repeated Start Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

#define LPI2C_SIER_SDIE_MASK                     (0x200U)
#define LPI2C_SIER_SDIE_SHIFT                    (9U)
/*! SDIE - Stop Detect Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

#define LPI2C_SIER_BEIE_MASK                     (0x400U)
#define LPI2C_SIER_BEIE_SHIFT                    (10U)
/*! BEIE - Bit Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

#define LPI2C_SIER_FEIE_MASK                     (0x800U)
#define LPI2C_SIER_FEIE_SHIFT                    (11U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

#define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
#define LPI2C_SIER_AM0IE_SHIFT                   (12U)
/*! AM0IE - Address Match 0 Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

#define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
#define LPI2C_SIER_AM1IE_SHIFT                   (13U)
/*! AM1IE - Address Match 1 Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)

#define LPI2C_SIER_GCIE_MASK                     (0x4000U)
#define LPI2C_SIER_GCIE_SHIFT                    (14U)
/*! GCIE - General Call Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

#define LPI2C_SIER_SARIE_MASK                    (0x8000U)
#define LPI2C_SIER_SARIE_SHIFT                   (15U)
/*! SARIE - SMBus Alert Response Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
/*! @} */

/*! @name SDER - Target DMA Enable */
/*! @{ */

#define LPI2C_SDER_TDDE_MASK                     (0x1U)
#define LPI2C_SDER_TDDE_SHIFT                    (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

#define LPI2C_SDER_RDDE_MASK                     (0x2U)
#define LPI2C_SDER_RDDE_SHIFT                    (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..Disable DMA request
 *  0b1..Enable DMA request
 */
#define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

#define LPI2C_SDER_AVDE_MASK                     (0x4U)
#define LPI2C_SDER_AVDE_SHIFT                    (2U)
/*! AVDE - Address Valid DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

#define LPI2C_SDER_RSDE_MASK                     (0x100U)
#define LPI2C_SDER_RSDE_SHIFT                    (8U)
/*! RSDE - Repeated Start DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SDER_RSDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)

#define LPI2C_SDER_SDDE_MASK                     (0x200U)
#define LPI2C_SDER_SDDE_SHIFT                    (9U)
/*! SDDE - Stop Detect DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SDER_SDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
/*! @} */

/*! @name SCFGR0 - Target Configuration 0 */
/*! @{ */

#define LPI2C_SCFGR0_RDREQ_MASK                  (0x1U)
#define LPI2C_SCFGR0_RDREQ_SHIFT                 (0U)
/*! RDREQ - Read Request
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR0_RDREQ(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK)

#define LPI2C_SCFGR0_RDACK_MASK                  (0x2U)
#define LPI2C_SCFGR0_RDACK_SHIFT                 (1U)
/*! RDACK - Read Acknowledge Flag
 *  0b0..Read Request not acknowledged
 *  0b1..Read Request acknowledged
 */
#define LPI2C_SCFGR0_RDACK(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK)
/*! @} */

/*! @name SCFGR1 - Target Configuration 1 */
/*! @{ */

#define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
#define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
/*! ADRSTALL - Address SCL Stall
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

#define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
#define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
/*! RXSTALL - RX SCL Stall
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

#define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
#define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
/*! TXDSTALL - Transmit Data SCL Stall
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

#define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
#define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
/*! ACKSTALL - ACK SCL Stall
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

#define LPI2C_SCFGR1_RXNACK_MASK                 (0x10U)
#define LPI2C_SCFGR1_RXNACK_SHIFT                (4U)
/*! RXNACK - Receive NACK
 *  0b0..ACK or NACK always determined by STAR[TXNACK]
 *  0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]
 */
#define LPI2C_SCFGR1_RXNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK)

#define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
#define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
/*! GCEN - General Call Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

#define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
#define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
/*! SAEN - SMBus Alert Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

#define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
#define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
/*! TXCFG - Transmit Flag Configuration
 *  0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty
 *  0b1..MSR[TDF] is set whenever STDR is empty
 */
#define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

#define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
#define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
/*! RXCFG - Receive Data Configuration
 *  0b0..Return received data, clear MSR[RDF]
 *  0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set
 */
#define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

#define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
#define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
/*! IGNACK - Ignore NACK
 *  0b0..End transfer on NACK
 *  0b1..Do not end transfer on NACK
 */
#define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

#define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
#define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
/*! HSMEN - HS Mode Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

#define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
#define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
/*! ADDRCFG - Address Configuration
 *  0b000..Address match 0 (7-bit)
 *  0b001..Address match 0 (10-bit)
 *  0b010..Address match 0 (7-bit) or address match 1 (7-bit)
 *  0b011..Address match 0 (10-bit) or address match 1 (10-bit)
 *  0b100..Address match 0 (7-bit) or address match 1 (10-bit)
 *  0b101..Address match 0 (10-bit) or address match 1 (7-bit)
 *  0b110..From address match 0 (7-bit) to address match 1 (7-bit)
 *  0b111..From address match 0 (10-bit) to address match 1 (10-bit)
 */
#define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)

#define LPI2C_SCFGR1_RXALL_MASK                  (0x1000000U)
#define LPI2C_SCFGR1_RXALL_SHIFT                 (24U)
/*! RXALL - Receive All
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPI2C_SCFGR1_RXALL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK)

#define LPI2C_SCFGR1_RSCFG_MASK                  (0x2000000U)
#define LPI2C_SCFGR1_RSCFG_SHIFT                 (25U)
/*! RSCFG - Repeated Start Configuration
 *  0b0..Any repeated Start condition following an address match
 *  0b1..Any repeated Start condition
 */
#define LPI2C_SCFGR1_RSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK)

#define LPI2C_SCFGR1_SDCFG_MASK                  (0x4000000U)
#define LPI2C_SCFGR1_SDCFG_SHIFT                 (26U)
/*! SDCFG - Stop Detect Configuration
 *  0b0..Any Stop condition following an address match
 *  0b1..Any Stop condition
 */
#define LPI2C_SCFGR1_SDCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK)
/*! @} */

/*! @name SCFGR2 - Target Configuration 2 */
/*! @{ */

#define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
#define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
/*! CLKHOLD - Clock Hold Time */
#define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

#define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
#define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
/*! DATAVD - Data Valid Delay */
#define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

#define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
#define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
/*! FILTSCL - Glitch Filter SCL */
#define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

#define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
#define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
/*! FILTSDA - Glitch Filter SDA */
#define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
/*! @} */

/*! @name SAMR - Target Address Match */
/*! @{ */

#define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
#define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
/*! ADDR0 - Address 0 Value */
#define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

#define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
#define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
/*! ADDR1 - Address 1 Value */
#define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
/*! @} */

/*! @name SASR - Target Address Status */
/*! @{ */

#define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
#define LPI2C_SASR_RADDR_SHIFT                   (0U)
/*! RADDR - Received Address */
#define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

#define LPI2C_SASR_ANV_MASK                      (0x4000U)
#define LPI2C_SASR_ANV_SHIFT                     (14U)
/*! ANV - Address Not Valid
 *  0b0..Valid
 *  0b1..Not valid
 */
#define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
/*! @} */

/*! @name STAR - Target Transmit ACK */
/*! @{ */

#define LPI2C_STAR_TXNACK_MASK                   (0x1U)
#define LPI2C_STAR_TXNACK_SHIFT                  (0U)
/*! TXNACK - Transmit NACK
 *  0b0..Transmit ACK
 *  0b1..Transmit NACK
 */
#define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
/*! @} */

/*! @name STDR - Target Transmit Data */
/*! @{ */

#define LPI2C_STDR_DATA_MASK                     (0xFFU)
#define LPI2C_STDR_DATA_SHIFT                    (0U)
/*! DATA - Transmit Data */
#define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
/*! @} */

/*! @name SRDR - Target Receive Data */
/*! @{ */

#define LPI2C_SRDR_DATA_MASK                     (0xFFU)
#define LPI2C_SRDR_DATA_SHIFT                    (0U)
/*! DATA - Received Data */
#define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

#define LPI2C_SRDR_RADDR_MASK                    (0x700U)
#define LPI2C_SRDR_RADDR_SHIFT                   (8U)
/*! RADDR - Received Address */
#define LPI2C_SRDR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK)

#define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
#define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
/*! RXEMPTY - Receive Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

#define LPI2C_SRDR_SOF_MASK                      (0x8000U)
#define LPI2C_SRDR_SOF_SHIFT                     (15U)
/*! SOF - Start of Frame
 *  0b0..Not first
 *  0b1..First
 */
#define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
/*! @} */

/*! @name SRDROR - Target Receive Data Read Only */
/*! @{ */

#define LPI2C_SRDROR_DATA_MASK                   (0xFFU)
#define LPI2C_SRDROR_DATA_SHIFT                  (0U)
/*! DATA - Receive Data */
#define LPI2C_SRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK)

#define LPI2C_SRDROR_RADDR_MASK                  (0x700U)
#define LPI2C_SRDROR_RADDR_SHIFT                 (8U)
/*! RADDR - Received Address */
#define LPI2C_SRDROR_RADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK)

#define LPI2C_SRDROR_RXEMPTY_MASK                (0x4000U)
#define LPI2C_SRDROR_RXEMPTY_SHIFT               (14U)
/*! RXEMPTY - Receive Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define LPI2C_SRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK)

#define LPI2C_SRDROR_SOF_MASK                    (0x8000U)
#define LPI2C_SRDROR_SOF_SHIFT                   (15U)
/*! SOF - Start of Frame
 *  0b0..Not the first
 *  0b1..First
 */
#define LPI2C_SRDROR_SOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK)
/*! @} */

/*! @name MTCBR - Controller Transmit Command Burst */
/*! @{ */

#define LPI2C_MTCBR_DATA_MASK                    (0xFFU)
#define LPI2C_MTCBR_DATA_SHIFT                   (0U)
/*! DATA - Data */
#define LPI2C_MTCBR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK)

#define LPI2C_MTCBR_CMD_MASK                     (0x700U)
#define LPI2C_MTCBR_CMD_SHIFT                    (8U)
/*! CMD - Command */
#define LPI2C_MTCBR_CMD(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK)
/*! @} */

/* The count of LPI2C_MTCBR */
#define LPI2C_MTCBR_COUNT                        (128U)

/*! @name MTDBR - Transmit Data Burst */
/*! @{ */

#define LPI2C_MTDBR_DATA0_MASK                   (0xFFU)
#define LPI2C_MTDBR_DATA0_SHIFT                  (0U)
/*! DATA0 - Data */
#define LPI2C_MTDBR_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK)

#define LPI2C_MTDBR_DATA1_MASK                   (0xFF00U)
#define LPI2C_MTDBR_DATA1_SHIFT                  (8U)
/*! DATA1 - Data */
#define LPI2C_MTDBR_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK)

#define LPI2C_MTDBR_DATA2_MASK                   (0xFF0000U)
#define LPI2C_MTDBR_DATA2_SHIFT                  (16U)
/*! DATA2 - Data */
#define LPI2C_MTDBR_DATA2(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK)

#define LPI2C_MTDBR_DATA3_MASK                   (0xFF000000U)
#define LPI2C_MTDBR_DATA3_SHIFT                  (24U)
/*! DATA3 - Data */
#define LPI2C_MTDBR_DATA3(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK)
/*! @} */

/* The count of LPI2C_MTDBR */
#define LPI2C_MTDBR_COUNT                        (256U)


/*!
 * @}
 */ /* end of group LPI2C_Register_Masks */


/* LPI2C - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPI2C0 base address */
  #define LPI2C0_BASE                              (0x50110800u)
  /** Peripheral LPI2C0 base address */
  #define LPI2C0_BASE_NS                           (0x40110800u)
  /** Peripheral LPI2C0 base pointer */
  #define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
  /** Peripheral LPI2C0 base pointer */
  #define LPI2C0_NS                                ((LPI2C_Type *)LPI2C0_BASE_NS)
  /** Peripheral LPI2C1 base address */
  #define LPI2C1_BASE                              (0x50111800u)
  /** Peripheral LPI2C1 base address */
  #define LPI2C1_BASE_NS                           (0x40111800u)
  /** Peripheral LPI2C1 base pointer */
  #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
  /** Peripheral LPI2C1 base pointer */
  #define LPI2C1_NS                                ((LPI2C_Type *)LPI2C1_BASE_NS)
  /** Peripheral LPI2C2 base address */
  #define LPI2C2_BASE                              (0x50112800u)
  /** Peripheral LPI2C2 base address */
  #define LPI2C2_BASE_NS                           (0x40112800u)
  /** Peripheral LPI2C2 base pointer */
  #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
  /** Peripheral LPI2C2 base pointer */
  #define LPI2C2_NS                                ((LPI2C_Type *)LPI2C2_BASE_NS)
  /** Peripheral LPI2C3 base address */
  #define LPI2C3_BASE                              (0x50113800u)
  /** Peripheral LPI2C3 base address */
  #define LPI2C3_BASE_NS                           (0x40113800u)
  /** Peripheral LPI2C3 base pointer */
  #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
  /** Peripheral LPI2C3 base pointer */
  #define LPI2C3_NS                                ((LPI2C_Type *)LPI2C3_BASE_NS)
  /** Peripheral LPI2C4 base address */
  #define LPI2C4_BASE                              (0x50171800u)
  /** Peripheral LPI2C4 base address */
  #define LPI2C4_BASE_NS                           (0x40171800u)
  /** Peripheral LPI2C4 base pointer */
  #define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
  /** Peripheral LPI2C4 base pointer */
  #define LPI2C4_NS                                ((LPI2C_Type *)LPI2C4_BASE_NS)
  /** Peripheral LPI2C5 base address */
  #define LPI2C5_BASE                              (0x50172800u)
  /** Peripheral LPI2C5 base address */
  #define LPI2C5_BASE_NS                           (0x40172800u)
  /** Peripheral LPI2C5 base pointer */
  #define LPI2C5                                   ((LPI2C_Type *)LPI2C5_BASE)
  /** Peripheral LPI2C5 base pointer */
  #define LPI2C5_NS                                ((LPI2C_Type *)LPI2C5_BASE_NS)
  /** Peripheral LPI2C6 base address */
  #define LPI2C6_BASE                              (0x50173800u)
  /** Peripheral LPI2C6 base address */
  #define LPI2C6_BASE_NS                           (0x40173800u)
  /** Peripheral LPI2C6 base pointer */
  #define LPI2C6                                   ((LPI2C_Type *)LPI2C6_BASE)
  /** Peripheral LPI2C6 base pointer */
  #define LPI2C6_NS                                ((LPI2C_Type *)LPI2C6_BASE_NS)
  /** Peripheral LPI2C7 base address */
  #define LPI2C7_BASE                              (0x50174800u)
  /** Peripheral LPI2C7 base address */
  #define LPI2C7_BASE_NS                           (0x40174800u)
  /** Peripheral LPI2C7 base pointer */
  #define LPI2C7                                   ((LPI2C_Type *)LPI2C7_BASE)
  /** Peripheral LPI2C7 base pointer */
  #define LPI2C7_NS                                ((LPI2C_Type *)LPI2C7_BASE_NS)
  /** Peripheral LPI2C8 base address */
  #define LPI2C8_BASE                              (0x50199800u)
  /** Peripheral LPI2C8 base address */
  #define LPI2C8_BASE_NS                           (0x40199800u)
  /** Peripheral LPI2C8 base pointer */
  #define LPI2C8                                   ((LPI2C_Type *)LPI2C8_BASE)
  /** Peripheral LPI2C8 base pointer */
  #define LPI2C8_NS                                ((LPI2C_Type *)LPI2C8_BASE_NS)
  /** Peripheral LPI2C9 base address */
  #define LPI2C9_BASE                              (0x5019A800u)
  /** Peripheral LPI2C9 base address */
  #define LPI2C9_BASE_NS                           (0x4019A800u)
  /** Peripheral LPI2C9 base pointer */
  #define LPI2C9                                   ((LPI2C_Type *)LPI2C9_BASE)
  /** Peripheral LPI2C9 base pointer */
  #define LPI2C9_NS                                ((LPI2C_Type *)LPI2C9_BASE_NS)
  /** Peripheral LPI2C10 base address */
  #define LPI2C10_BASE                             (0x5019B800u)
  /** Peripheral LPI2C10 base address */
  #define LPI2C10_BASE_NS                          (0x4019B800u)
  /** Peripheral LPI2C10 base pointer */
  #define LPI2C10                                  ((LPI2C_Type *)LPI2C10_BASE)
  /** Peripheral LPI2C10 base pointer */
  #define LPI2C10_NS                               ((LPI2C_Type *)LPI2C10_BASE_NS)
  /** Peripheral LPI2C11 base address */
  #define LPI2C11_BASE                             (0x5019C800u)
  /** Peripheral LPI2C11 base address */
  #define LPI2C11_BASE_NS                          (0x4019C800u)
  /** Peripheral LPI2C11 base pointer */
  #define LPI2C11                                  ((LPI2C_Type *)LPI2C11_BASE)
  /** Peripheral LPI2C11 base pointer */
  #define LPI2C11_NS                               ((LPI2C_Type *)LPI2C11_BASE_NS)
  /** Peripheral LPI2C12 base address */
  #define LPI2C12_BASE                             (0x5019D800u)
  /** Peripheral LPI2C12 base address */
  #define LPI2C12_BASE_NS                          (0x4019D800u)
  /** Peripheral LPI2C12 base pointer */
  #define LPI2C12                                  ((LPI2C_Type *)LPI2C12_BASE)
  /** Peripheral LPI2C12 base pointer */
  #define LPI2C12_NS                               ((LPI2C_Type *)LPI2C12_BASE_NS)
  /** Peripheral LPI2C13 base address */
  #define LPI2C13_BASE                             (0x5019E800u)
  /** Peripheral LPI2C13 base address */
  #define LPI2C13_BASE_NS                          (0x4019E800u)
  /** Peripheral LPI2C13 base pointer */
  #define LPI2C13                                  ((LPI2C_Type *)LPI2C13_BASE)
  /** Peripheral LPI2C13 base pointer */
  #define LPI2C13_NS                               ((LPI2C_Type *)LPI2C13_BASE_NS)
  /** Peripheral LPI2C15 base address */
  #define LPI2C15_BASE                             (0x50213000u)
  /** Peripheral LPI2C15 base address */
  #define LPI2C15_BASE_NS                          (0x40213000u)
  /** Peripheral LPI2C15 base pointer */
  #define LPI2C15                                  ((LPI2C_Type *)LPI2C15_BASE)
  /** Peripheral LPI2C15 base pointer */
  #define LPI2C15_NS                               ((LPI2C_Type *)LPI2C15_BASE_NS)
  /** Array initializer of LPI2C peripheral base addresses */
  #define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE, LPI2C10_BASE, LPI2C11_BASE, LPI2C12_BASE, LPI2C13_BASE, 0u, LPI2C15_BASE }
  /** Array initializer of LPI2C peripheral base pointers */
  #define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9, LPI2C10, LPI2C11, LPI2C12, LPI2C13, (LPI2C_Type *)0u, LPI2C15 }
  /** Array initializer of LPI2C peripheral base addresses */
  #define LPI2C_BASE_ADDRS_NS                      { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS, LPI2C10_BASE_NS, LPI2C11_BASE_NS, LPI2C12_BASE_NS, LPI2C13_BASE_NS, 0u, LPI2C15_BASE_NS }
  /** Array initializer of LPI2C peripheral base pointers */
  #define LPI2C_BASE_PTRS_NS                       { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS, LPI2C10_NS, LPI2C11_NS, LPI2C12_NS, LPI2C13_NS, (LPI2C_Type *)0u, LPI2C15_NS }
#else
  /** Peripheral LPI2C0 base address */
  #define LPI2C0_BASE                              (0x40110800u)
  /** Peripheral LPI2C0 base pointer */
  #define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
  /** Peripheral LPI2C1 base address */
  #define LPI2C1_BASE                              (0x40111800u)
  /** Peripheral LPI2C1 base pointer */
  #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
  /** Peripheral LPI2C2 base address */
  #define LPI2C2_BASE                              (0x40112800u)
  /** Peripheral LPI2C2 base pointer */
  #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
  /** Peripheral LPI2C3 base address */
  #define LPI2C3_BASE                              (0x40113800u)
  /** Peripheral LPI2C3 base pointer */
  #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
  /** Peripheral LPI2C4 base address */
  #define LPI2C4_BASE                              (0x40171800u)
  /** Peripheral LPI2C4 base pointer */
  #define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
  /** Peripheral LPI2C5 base address */
  #define LPI2C5_BASE                              (0x40172800u)
  /** Peripheral LPI2C5 base pointer */
  #define LPI2C5                                   ((LPI2C_Type *)LPI2C5_BASE)
  /** Peripheral LPI2C6 base address */
  #define LPI2C6_BASE                              (0x40173800u)
  /** Peripheral LPI2C6 base pointer */
  #define LPI2C6                                   ((LPI2C_Type *)LPI2C6_BASE)
  /** Peripheral LPI2C7 base address */
  #define LPI2C7_BASE                              (0x40174800u)
  /** Peripheral LPI2C7 base pointer */
  #define LPI2C7                                   ((LPI2C_Type *)LPI2C7_BASE)
  /** Peripheral LPI2C8 base address */
  #define LPI2C8_BASE                              (0x40199800u)
  /** Peripheral LPI2C8 base pointer */
  #define LPI2C8                                   ((LPI2C_Type *)LPI2C8_BASE)
  /** Peripheral LPI2C9 base address */
  #define LPI2C9_BASE                              (0x4019A800u)
  /** Peripheral LPI2C9 base pointer */
  #define LPI2C9                                   ((LPI2C_Type *)LPI2C9_BASE)
  /** Peripheral LPI2C10 base address */
  #define LPI2C10_BASE                             (0x4019B800u)
  /** Peripheral LPI2C10 base pointer */
  #define LPI2C10                                  ((LPI2C_Type *)LPI2C10_BASE)
  /** Peripheral LPI2C11 base address */
  #define LPI2C11_BASE                             (0x4019C800u)
  /** Peripheral LPI2C11 base pointer */
  #define LPI2C11                                  ((LPI2C_Type *)LPI2C11_BASE)
  /** Peripheral LPI2C12 base address */
  #define LPI2C12_BASE                             (0x4019D800u)
  /** Peripheral LPI2C12 base pointer */
  #define LPI2C12                                  ((LPI2C_Type *)LPI2C12_BASE)
  /** Peripheral LPI2C13 base address */
  #define LPI2C13_BASE                             (0x4019E800u)
  /** Peripheral LPI2C13 base pointer */
  #define LPI2C13                                  ((LPI2C_Type *)LPI2C13_BASE)
  /** Peripheral LPI2C15 base address */
  #define LPI2C15_BASE                             (0x40213000u)
  /** Peripheral LPI2C15 base pointer */
  #define LPI2C15                                  ((LPI2C_Type *)LPI2C15_BASE)
  /** Array initializer of LPI2C peripheral base addresses */
  #define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE, LPI2C10_BASE, LPI2C11_BASE, LPI2C12_BASE, LPI2C13_BASE, 0u, LPI2C15_BASE }
  /** Array initializer of LPI2C peripheral base pointers */
  #define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9, LPI2C10, LPI2C11, LPI2C12, LPI2C13, (LPI2C_Type *)0u, LPI2C15 }
#endif
/** Interrupt vectors for the LPI2C peripheral type */
#define LPI2C_IRQS                               { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn, LP_FLEXCOMM10_IRQn, LP_FLEXCOMM11_IRQn, LP_FLEXCOMM12_IRQn, LP_FLEXCOMM13_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group LPI2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
 * @{
 */

/** LPSPI - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CR;                                /**< Control, offset: 0x10 */
  __IO uint32_t SR;                                /**< Status, offset: 0x14 */
  __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
  __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
  __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
  __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
       uint8_t RESERVED_1[8];
  __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
  __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
       uint8_t RESERVED_2[8];
  __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
  __IO uint32_t CCR1;                              /**< Clock Configuration 1, offset: 0x44 */
       uint8_t RESERVED_3[16];
  __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
  __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
  __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
  __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
       uint8_t RESERVED_4[8];
  __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
  __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
  __I  uint32_t RDROR;                             /**< Receive Data Read Only, offset: 0x78 */
       uint8_t RESERVED_5[896];
  __O  uint32_t TCBR;                              /**< Transmit Command Burst, offset: 0x3FC */
  __O  uint32_t TDBR[128];                         /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
  __I  uint32_t RDBR[128];                         /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */
} LPSPI_Type;

/* ----------------------------------------------------------------------------
   -- LPSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPSPI_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Module Identification Number
 *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
 *  *..
 */
#define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)

#define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
#define LPSPI_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number */
#define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)

#define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPSPI_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number */
#define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
#define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
/*! TXFIFO - Transmit FIFO Size */
#define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)

#define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
#define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
/*! RXFIFO - Receive FIFO Size */
#define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)

#define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
#define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
/*! PCSNUM - PCS Number */
#define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
/*! @} */

/*! @name CR - Control */
/*! @{ */

#define LPSPI_CR_MEN_MASK                        (0x1U)
#define LPSPI_CR_MEN_SHIFT                       (0U)
/*! MEN - Module Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

#define LPSPI_CR_RST_MASK                        (0x2U)
#define LPSPI_CR_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..Not reset
 *  0b1..Reset
 */
#define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

#define LPSPI_CR_DOZEN_MASK                      (0x4U)
#define LPSPI_CR_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Mode Enable
 *  0b0..Enable
 *  0b1..Disable
 */
#define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

#define LPSPI_CR_DBGEN_MASK                      (0x8U)
#define LPSPI_CR_DBGEN_SHIFT                     (3U)
/*! DBGEN - Debug Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

#define LPSPI_CR_RTF_MASK                        (0x100U)
#define LPSPI_CR_RTF_SHIFT                       (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Reset
 */
#define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

#define LPSPI_CR_RRF_MASK                        (0x200U)
#define LPSPI_CR_RRF_SHIFT                       (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Reset
 */
#define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
/*! @} */

/*! @name SR - Status */
/*! @{ */

#define LPSPI_SR_TDF_MASK                        (0x1U)
#define LPSPI_SR_TDF_SHIFT                       (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data requested
 */
#define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)

#define LPSPI_SR_RDF_MASK                        (0x2U)
#define LPSPI_SR_RDF_SHIFT                       (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive data not ready
 *  0b1..Receive data ready
 */
#define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)

#define LPSPI_SR_WCF_MASK                        (0x100U)
#define LPSPI_SR_WCF_SHIFT                       (8U)
/*! WCF - Word Complete Flag
 *  0b0..Not complete
 *  0b1..Complete
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)

#define LPSPI_SR_FCF_MASK                        (0x200U)
#define LPSPI_SR_FCF_SHIFT                       (9U)
/*! FCF - Frame Complete Flag
 *  0b0..Not complete
 *  0b1..Complete
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)

#define LPSPI_SR_TCF_MASK                        (0x400U)
#define LPSPI_SR_TCF_SHIFT                       (10U)
/*! TCF - Transfer Complete Flag
 *  0b0..Not complete
 *  0b1..Complete
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)

#define LPSPI_SR_TEF_MASK                        (0x800U)
#define LPSPI_SR_TEF_SHIFT                       (11U)
/*! TEF - Transmit Error Flag
 *  0b0..No underrun
 *  0b1..Underrun
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)

#define LPSPI_SR_REF_MASK                        (0x1000U)
#define LPSPI_SR_REF_SHIFT                       (12U)
/*! REF - Receive Error Flag
 *  0b0..No overflow
 *  0b1..Overflow
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)

#define LPSPI_SR_DMF_MASK                        (0x2000U)
#define LPSPI_SR_DMF_SHIFT                       (13U)
/*! DMF - Data Match Flag
 *  0b0..No match
 *  0b1..Match
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)

#define LPSPI_SR_MBF_MASK                        (0x1000000U)
#define LPSPI_SR_MBF_SHIFT                       (24U)
/*! MBF - Module Busy Flag
 *  0b0..LPSPI is idle
 *  0b1..LPSPI is busy
 */
#define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
/*! @} */

/*! @name IER - Interrupt Enable */
/*! @{ */

#define LPSPI_IER_TDIE_MASK                      (0x1U)
#define LPSPI_IER_TDIE_SHIFT                     (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)

#define LPSPI_IER_RDIE_MASK                      (0x2U)
#define LPSPI_IER_RDIE_SHIFT                     (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)

#define LPSPI_IER_WCIE_MASK                      (0x100U)
#define LPSPI_IER_WCIE_SHIFT                     (8U)
/*! WCIE - Word Complete Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)

#define LPSPI_IER_FCIE_MASK                      (0x200U)
#define LPSPI_IER_FCIE_SHIFT                     (9U)
/*! FCIE - Frame Complete Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)

#define LPSPI_IER_TCIE_MASK                      (0x400U)
#define LPSPI_IER_TCIE_SHIFT                     (10U)
/*! TCIE - Transfer Complete Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)

#define LPSPI_IER_TEIE_MASK                      (0x800U)
#define LPSPI_IER_TEIE_SHIFT                     (11U)
/*! TEIE - Transmit Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)

#define LPSPI_IER_REIE_MASK                      (0x1000U)
#define LPSPI_IER_REIE_SHIFT                     (12U)
/*! REIE - Receive Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)

#define LPSPI_IER_DMIE_MASK                      (0x2000U)
#define LPSPI_IER_DMIE_SHIFT                     (13U)
/*! DMIE - Data Match Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
/*! @} */

/*! @name DER - DMA Enable */
/*! @{ */

#define LPSPI_DER_TDDE_MASK                      (0x1U)
#define LPSPI_DER_TDDE_SHIFT                     (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)

#define LPSPI_DER_RDDE_MASK                      (0x2U)
#define LPSPI_DER_RDDE_SHIFT                     (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)

#define LPSPI_DER_FCDE_MASK                      (0x200U)
#define LPSPI_DER_FCDE_SHIFT                     (9U)
/*! FCDE - Frame Complete DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_DER_FCDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
/*! @} */

/*! @name CFGR0 - Configuration 0 */
/*! @{ */

#define LPSPI_CFGR0_HREN_MASK                    (0x1U)
#define LPSPI_CFGR0_HREN_SHIFT                   (0U)
/*! HREN - Host Request Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)

#define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
#define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
/*! HRPOL - Host Request Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)

#define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
#define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
/*! HRSEL - Host Request Select
 *  0b0..HREQ pin
 *  0b1..Input trigger
 */
#define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)

#define LPSPI_CFGR0_HRDIR_MASK                   (0x8U)
#define LPSPI_CFGR0_HRDIR_SHIFT                  (3U)
/*! HRDIR - Host Request Direction
 *  0b0..Input
 *  0b1..Output
 */
#define LPSPI_CFGR0_HRDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK)

#define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
#define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
/*! CIRFIFO - Circular FIFO Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)

#define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
#define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
/*! RDMO - Receive Data Match Only
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
/*! @} */

/*! @name CFGR1 - Configuration 1 */
/*! @{ */

#define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
#define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
/*! MASTER - Controller Mode
 *  0b0..Peripheral mode
 *  0b1..Controller mode
 */
#define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)

#define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
#define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
/*! SAMPLE - Sample Point
 *  0b0..SCK edge
 *  0b1..Delayed SCK edge
 */
#define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)

#define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
#define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
/*! AUTOPCS - Automatic PCS
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)

#define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
#define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
/*! NOSTALL - No Stall
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)

#define LPSPI_CFGR1_PARTIAL_MASK                 (0x10U)
#define LPSPI_CFGR1_PARTIAL_SHIFT                (4U)
/*! PARTIAL - Partial Enable
 *  0b0..Discard
 *  0b1..Store
 */
#define LPSPI_CFGR1_PARTIAL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK)

#define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
#define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
/*! PCSPOL - Peripheral Chip Select Polarity
 *  0b0000..Active low
 *  0b0001..Active high
 */
#define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)

#define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
#define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
/*! MATCFG - Match Configuration
 *  0b000..Match is disabled
 *  0b001..
 *  0b010..Match first data word with compare word
 *  0b011..Match any data word with compare word
 *  0b100..Sequential match, first data word
 *  0b101..Sequential match, any data word
 *  0b110..Match first data word (masked) with compare word (masked)
 *  0b111..Match any data word (masked) with compare word (masked)
 */
#define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)

#define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
#define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
/*! PINCFG - Pin Configuration
 *  0b00..SIN is used for input data; SOUT is used for output data
 *  0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported
 *  0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported
 *  0b11..SOUT is used for input data; SIN is used for output data
 */
#define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)

#define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
#define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
/*! OUTCFG - Output Configuration
 *  0b0..Retain last value
 *  0b1..3-stated
 */
#define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)

#define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
#define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
/*! PCSCFG - Peripheral Chip Select Configuration
 *  0b0..PCS[3:2] configured for chip select function
 *  0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
 */
#define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
/*! @} */

/*! @name DMR0 - Data Match 0 */
/*! @{ */

#define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
#define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
/*! MATCH0 - Match 0 Value */
#define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
/*! @} */

/*! @name DMR1 - Data Match 1 */
/*! @{ */

#define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
#define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
/*! MATCH1 - Match 1 Value */
#define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
/*! @} */

/*! @name CCR - Clock Configuration */
/*! @{ */

#define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
#define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
/*! SCKDIV - SCK Divider */
#define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)

#define LPSPI_CCR_DBT_MASK                       (0xFF00U)
#define LPSPI_CCR_DBT_SHIFT                      (8U)
/*! DBT - Delay Between Transfers */
#define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)

#define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
#define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
/*! PCSSCK - PCS-to-SCK Delay */
#define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)

#define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
#define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
/*! SCKPCS - SCK-to-PCS Delay */
#define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
/*! @} */

/*! @name CCR1 - Clock Configuration 1 */
/*! @{ */

#define LPSPI_CCR1_SCKSET_MASK                   (0xFFU)
#define LPSPI_CCR1_SCKSET_SHIFT                  (0U)
/*! SCKSET - SCK Setup */
#define LPSPI_CCR1_SCKSET(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK)

#define LPSPI_CCR1_SCKHLD_MASK                   (0xFF00U)
#define LPSPI_CCR1_SCKHLD_SHIFT                  (8U)
/*! SCKHLD - SCK Hold */
#define LPSPI_CCR1_SCKHLD(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK)

#define LPSPI_CCR1_PCSPCS_MASK                   (0xFF0000U)
#define LPSPI_CCR1_PCSPCS_SHIFT                  (16U)
/*! PCSPCS - PCS to PCS Delay */
#define LPSPI_CCR1_PCSPCS(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK)

#define LPSPI_CCR1_SCKSCK_MASK                   (0xFF000000U)
#define LPSPI_CCR1_SCKSCK_SHIFT                  (24U)
/*! SCKSCK - SCK Inter-Frame Delay */
#define LPSPI_CCR1_SCKSCK(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK)
/*! @} */

/*! @name FCR - FIFO Control */
/*! @{ */

#define LPSPI_FCR_TXWATER_MASK                   (0x7U)
#define LPSPI_FCR_TXWATER_SHIFT                  (0U)
/*! TXWATER - Transmit FIFO Watermark */
#define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)

#define LPSPI_FCR_RXWATER_MASK                   (0x70000U)
#define LPSPI_FCR_RXWATER_SHIFT                  (16U)
/*! RXWATER - Receive FIFO Watermark */
#define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
/*! @} */

/*! @name FSR - FIFO Status */
/*! @{ */

#define LPSPI_FSR_TXCOUNT_MASK                   (0xFU)
#define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
/*! TXCOUNT - Transmit FIFO Count */
#define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)

#define LPSPI_FSR_RXCOUNT_MASK                   (0xF0000U)
#define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
/*! RXCOUNT - Receive FIFO Count */
#define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
/*! @} */

/*! @name TCR - Transmit Command */
/*! @{ */

#define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
#define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
/*! FRAMESZ - Frame Size */
#define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)

#define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
#define LPSPI_TCR_WIDTH_SHIFT                    (16U)
/*! WIDTH - Transfer Width
 *  0b00..1-bit transfer
 *  0b01..2-bit transfer
 *  0b10..4-bit transfer
 *  0b11..Reserved
 */
#define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)

#define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
#define LPSPI_TCR_TXMSK_SHIFT                    (18U)
/*! TXMSK - Transmit Data Mask
 *  0b0..Normal transfer
 *  0b1..Mask transmit data
 */
#define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)

#define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
#define LPSPI_TCR_RXMSK_SHIFT                    (19U)
/*! RXMSK - Receive Data Mask
 *  0b0..Normal transfer
 *  0b1..Mask receive data
 */
#define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)

#define LPSPI_TCR_CONTC_MASK                     (0x100000U)
#define LPSPI_TCR_CONTC_SHIFT                    (20U)
/*! CONTC - Continuing Command
 *  0b0..Command word for start of new transfer
 *  0b1..Command word for continuing transfer
 */
#define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)

#define LPSPI_TCR_CONT_MASK                      (0x200000U)
#define LPSPI_TCR_CONT_SHIFT                     (21U)
/*! CONT - Continuous Transfer
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)

#define LPSPI_TCR_BYSW_MASK                      (0x400000U)
#define LPSPI_TCR_BYSW_SHIFT                     (22U)
/*! BYSW - Byte Swap
 *  0b0..Disable byte swap
 *  0b1..Enable byte swap
 */
#define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)

#define LPSPI_TCR_LSBF_MASK                      (0x800000U)
#define LPSPI_TCR_LSBF_SHIFT                     (23U)
/*! LSBF - LSB First
 *  0b0..MSB first
 *  0b1..LSB first
 */
#define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)

#define LPSPI_TCR_PCS_MASK                       (0x3000000U)
#define LPSPI_TCR_PCS_SHIFT                      (24U)
/*! PCS - Peripheral Chip Select
 *  0b00..Transfer using PCS[0]
 *  0b01..Transfer using PCS[1]
 *  0b10..Transfer using PCS[2]
 *  0b11..Transfer using PCS[3]
 */
#define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)

#define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
#define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
/*! PRESCALE - Prescaler Value
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)

#define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
#define LPSPI_TCR_CPHA_SHIFT                     (30U)
/*! CPHA - Clock Phase
 *  0b0..Captured
 *  0b1..Changed
 */
#define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)

#define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
#define LPSPI_TCR_CPOL_SHIFT                     (31U)
/*! CPOL - Clock Polarity
 *  0b0..Inactive low
 *  0b1..Inactive high
 */
#define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
/*! @} */

/*! @name TDR - Transmit Data */
/*! @{ */

#define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
#define LPSPI_TDR_DATA_SHIFT                     (0U)
/*! DATA - Transmit Data */
#define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
/*! @} */

/*! @name RSR - Receive Status */
/*! @{ */

#define LPSPI_RSR_SOF_MASK                       (0x1U)
#define LPSPI_RSR_SOF_SHIFT                      (0U)
/*! SOF - Start of Frame
 *  0b0..Subsequent data word or RX FIFO is empty (RXEMPTY=1).
 *  0b1..First data word
 */
#define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)

#define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
#define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
/*! RXEMPTY - RX FIFO Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
/*! @} */

/*! @name RDR - Receive Data */
/*! @{ */

#define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
#define LPSPI_RDR_DATA_SHIFT                     (0U)
/*! DATA - Receive Data */
#define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
/*! @} */

/*! @name RDROR - Receive Data Read Only */
/*! @{ */

#define LPSPI_RDROR_DATA_MASK                    (0xFFFFFFFFU)
#define LPSPI_RDROR_DATA_SHIFT                   (0U)
/*! DATA - Receive Data */
#define LPSPI_RDROR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK)
/*! @} */

/*! @name TCBR - Transmit Command Burst */
/*! @{ */

#define LPSPI_TCBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_TCBR_DATA_SHIFT                    (0U)
/*! DATA - Command Data */
#define LPSPI_TCBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK)
/*! @} */

/*! @name TDBR - Transmit Data Burst */
/*! @{ */

#define LPSPI_TDBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_TDBR_DATA_SHIFT                    (0U)
/*! DATA - Data */
#define LPSPI_TDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK)
/*! @} */

/* The count of LPSPI_TDBR */
#define LPSPI_TDBR_COUNT                         (128U)

/*! @name RDBR - Receive Data Burst */
/*! @{ */

#define LPSPI_RDBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_RDBR_DATA_SHIFT                    (0U)
/*! DATA - Data */
#define LPSPI_RDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK)
/*! @} */

/* The count of LPSPI_RDBR */
#define LPSPI_RDBR_COUNT                         (128U)


/*!
 * @}
 */ /* end of group LPSPI_Register_Masks */


/* LPSPI - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPSPI0 base address */
  #define LPSPI0_BASE                              (0x50110000u)
  /** Peripheral LPSPI0 base address */
  #define LPSPI0_BASE_NS                           (0x40110000u)
  /** Peripheral LPSPI0 base pointer */
  #define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
  /** Peripheral LPSPI0 base pointer */
  #define LPSPI0_NS                                ((LPSPI_Type *)LPSPI0_BASE_NS)
  /** Peripheral LPSPI1 base address */
  #define LPSPI1_BASE                              (0x50111000u)
  /** Peripheral LPSPI1 base address */
  #define LPSPI1_BASE_NS                           (0x40111000u)
  /** Peripheral LPSPI1 base pointer */
  #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
  /** Peripheral LPSPI1 base pointer */
  #define LPSPI1_NS                                ((LPSPI_Type *)LPSPI1_BASE_NS)
  /** Peripheral LPSPI2 base address */
  #define LPSPI2_BASE                              (0x50112000u)
  /** Peripheral LPSPI2 base address */
  #define LPSPI2_BASE_NS                           (0x40112000u)
  /** Peripheral LPSPI2 base pointer */
  #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
  /** Peripheral LPSPI2 base pointer */
  #define LPSPI2_NS                                ((LPSPI_Type *)LPSPI2_BASE_NS)
  /** Peripheral LPSPI3 base address */
  #define LPSPI3_BASE                              (0x50113000u)
  /** Peripheral LPSPI3 base address */
  #define LPSPI3_BASE_NS                           (0x40113000u)
  /** Peripheral LPSPI3 base pointer */
  #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
  /** Peripheral LPSPI3 base pointer */
  #define LPSPI3_NS                                ((LPSPI_Type *)LPSPI3_BASE_NS)
  /** Peripheral LPSPI4 base address */
  #define LPSPI4_BASE                              (0x50171000u)
  /** Peripheral LPSPI4 base address */
  #define LPSPI4_BASE_NS                           (0x40171000u)
  /** Peripheral LPSPI4 base pointer */
  #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
  /** Peripheral LPSPI4 base pointer */
  #define LPSPI4_NS                                ((LPSPI_Type *)LPSPI4_BASE_NS)
  /** Peripheral LPSPI5 base address */
  #define LPSPI5_BASE                              (0x50172000u)
  /** Peripheral LPSPI5 base address */
  #define LPSPI5_BASE_NS                           (0x40172000u)
  /** Peripheral LPSPI5 base pointer */
  #define LPSPI5                                   ((LPSPI_Type *)LPSPI5_BASE)
  /** Peripheral LPSPI5 base pointer */
  #define LPSPI5_NS                                ((LPSPI_Type *)LPSPI5_BASE_NS)
  /** Peripheral LPSPI6 base address */
  #define LPSPI6_BASE                              (0x50173000u)
  /** Peripheral LPSPI6 base address */
  #define LPSPI6_BASE_NS                           (0x40173000u)
  /** Peripheral LPSPI6 base pointer */
  #define LPSPI6                                   ((LPSPI_Type *)LPSPI6_BASE)
  /** Peripheral LPSPI6 base pointer */
  #define LPSPI6_NS                                ((LPSPI_Type *)LPSPI6_BASE_NS)
  /** Peripheral LPSPI7 base address */
  #define LPSPI7_BASE                              (0x50174000u)
  /** Peripheral LPSPI7 base address */
  #define LPSPI7_BASE_NS                           (0x40174000u)
  /** Peripheral LPSPI7 base pointer */
  #define LPSPI7                                   ((LPSPI_Type *)LPSPI7_BASE)
  /** Peripheral LPSPI7 base pointer */
  #define LPSPI7_NS                                ((LPSPI_Type *)LPSPI7_BASE_NS)
  /** Peripheral LPSPI8 base address */
  #define LPSPI8_BASE                              (0x50199000u)
  /** Peripheral LPSPI8 base address */
  #define LPSPI8_BASE_NS                           (0x40199000u)
  /** Peripheral LPSPI8 base pointer */
  #define LPSPI8                                   ((LPSPI_Type *)LPSPI8_BASE)
  /** Peripheral LPSPI8 base pointer */
  #define LPSPI8_NS                                ((LPSPI_Type *)LPSPI8_BASE_NS)
  /** Peripheral LPSPI9 base address */
  #define LPSPI9_BASE                              (0x5019A000u)
  /** Peripheral LPSPI9 base address */
  #define LPSPI9_BASE_NS                           (0x4019A000u)
  /** Peripheral LPSPI9 base pointer */
  #define LPSPI9                                   ((LPSPI_Type *)LPSPI9_BASE)
  /** Peripheral LPSPI9 base pointer */
  #define LPSPI9_NS                                ((LPSPI_Type *)LPSPI9_BASE_NS)
  /** Peripheral LPSPI10 base address */
  #define LPSPI10_BASE                             (0x5019B000u)
  /** Peripheral LPSPI10 base address */
  #define LPSPI10_BASE_NS                          (0x4019B000u)
  /** Peripheral LPSPI10 base pointer */
  #define LPSPI10                                  ((LPSPI_Type *)LPSPI10_BASE)
  /** Peripheral LPSPI10 base pointer */
  #define LPSPI10_NS                               ((LPSPI_Type *)LPSPI10_BASE_NS)
  /** Peripheral LPSPI11 base address */
  #define LPSPI11_BASE                             (0x5019C000u)
  /** Peripheral LPSPI11 base address */
  #define LPSPI11_BASE_NS                          (0x4019C000u)
  /** Peripheral LPSPI11 base pointer */
  #define LPSPI11                                  ((LPSPI_Type *)LPSPI11_BASE)
  /** Peripheral LPSPI11 base pointer */
  #define LPSPI11_NS                               ((LPSPI_Type *)LPSPI11_BASE_NS)
  /** Peripheral LPSPI12 base address */
  #define LPSPI12_BASE                             (0x5019D000u)
  /** Peripheral LPSPI12 base address */
  #define LPSPI12_BASE_NS                          (0x4019D000u)
  /** Peripheral LPSPI12 base pointer */
  #define LPSPI12                                  ((LPSPI_Type *)LPSPI12_BASE)
  /** Peripheral LPSPI12 base pointer */
  #define LPSPI12_NS                               ((LPSPI_Type *)LPSPI12_BASE_NS)
  /** Peripheral LPSPI13 base address */
  #define LPSPI13_BASE                             (0x5019E000u)
  /** Peripheral LPSPI13 base address */
  #define LPSPI13_BASE_NS                          (0x4019E000u)
  /** Peripheral LPSPI13 base pointer */
  #define LPSPI13                                  ((LPSPI_Type *)LPSPI13_BASE)
  /** Peripheral LPSPI13 base pointer */
  #define LPSPI13_NS                               ((LPSPI_Type *)LPSPI13_BASE_NS)
  /** Peripheral LPSPI14 base address */
  #define LPSPI14_BASE                             (0x50484000u)
  /** Peripheral LPSPI14 base address */
  #define LPSPI14_BASE_NS                          (0x40484000u)
  /** Peripheral LPSPI14 base pointer */
  #define LPSPI14                                  ((LPSPI_Type *)LPSPI14_BASE)
  /** Peripheral LPSPI14 base pointer */
  #define LPSPI14_NS                               ((LPSPI_Type *)LPSPI14_BASE_NS)
  /** Peripheral LPSPI16 base address */
  #define LPSPI16_BASE                             (0x50405000u)
  /** Peripheral LPSPI16 base address */
  #define LPSPI16_BASE_NS                          (0x40405000u)
  /** Peripheral LPSPI16 base pointer */
  #define LPSPI16                                  ((LPSPI_Type *)LPSPI16_BASE)
  /** Peripheral LPSPI16 base pointer */
  #define LPSPI16_NS                               ((LPSPI_Type *)LPSPI16_BASE_NS)
  /** Array initializer of LPSPI peripheral base addresses */
  #define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE, LPSPI10_BASE, LPSPI11_BASE, LPSPI12_BASE, LPSPI13_BASE, LPSPI14_BASE, 0u, LPSPI16_BASE }
  /** Array initializer of LPSPI peripheral base pointers */
  #define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9, LPSPI10, LPSPI11, LPSPI12, LPSPI13, LPSPI14, (LPSPI_Type *)0u, LPSPI16 }
  /** Array initializer of LPSPI peripheral base addresses */
  #define LPSPI_BASE_ADDRS_NS                      { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS, LPSPI10_BASE_NS, LPSPI11_BASE_NS, LPSPI12_BASE_NS, LPSPI13_BASE_NS, LPSPI14_BASE_NS, 0u, LPSPI16_BASE_NS }
  /** Array initializer of LPSPI peripheral base pointers */
  #define LPSPI_BASE_PTRS_NS                       { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS, LPSPI10_NS, LPSPI11_NS, LPSPI12_NS, LPSPI13_NS, LPSPI14_NS, (LPSPI_Type *)0u, LPSPI16_NS }
#else
  /** Peripheral LPSPI0 base address */
  #define LPSPI0_BASE                              (0x40110000u)
  /** Peripheral LPSPI0 base pointer */
  #define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
  /** Peripheral LPSPI1 base address */
  #define LPSPI1_BASE                              (0x40111000u)
  /** Peripheral LPSPI1 base pointer */
  #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
  /** Peripheral LPSPI2 base address */
  #define LPSPI2_BASE                              (0x40112000u)
  /** Peripheral LPSPI2 base pointer */
  #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
  /** Peripheral LPSPI3 base address */
  #define LPSPI3_BASE                              (0x40113000u)
  /** Peripheral LPSPI3 base pointer */
  #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
  /** Peripheral LPSPI4 base address */
  #define LPSPI4_BASE                              (0x40171000u)
  /** Peripheral LPSPI4 base pointer */
  #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
  /** Peripheral LPSPI5 base address */
  #define LPSPI5_BASE                              (0x40172000u)
  /** Peripheral LPSPI5 base pointer */
  #define LPSPI5                                   ((LPSPI_Type *)LPSPI5_BASE)
  /** Peripheral LPSPI6 base address */
  #define LPSPI6_BASE                              (0x40173000u)
  /** Peripheral LPSPI6 base pointer */
  #define LPSPI6                                   ((LPSPI_Type *)LPSPI6_BASE)
  /** Peripheral LPSPI7 base address */
  #define LPSPI7_BASE                              (0x40174000u)
  /** Peripheral LPSPI7 base pointer */
  #define LPSPI7                                   ((LPSPI_Type *)LPSPI7_BASE)
  /** Peripheral LPSPI8 base address */
  #define LPSPI8_BASE                              (0x40199000u)
  /** Peripheral LPSPI8 base pointer */
  #define LPSPI8                                   ((LPSPI_Type *)LPSPI8_BASE)
  /** Peripheral LPSPI9 base address */
  #define LPSPI9_BASE                              (0x4019A000u)
  /** Peripheral LPSPI9 base pointer */
  #define LPSPI9                                   ((LPSPI_Type *)LPSPI9_BASE)
  /** Peripheral LPSPI10 base address */
  #define LPSPI10_BASE                             (0x4019B000u)
  /** Peripheral LPSPI10 base pointer */
  #define LPSPI10                                  ((LPSPI_Type *)LPSPI10_BASE)
  /** Peripheral LPSPI11 base address */
  #define LPSPI11_BASE                             (0x4019C000u)
  /** Peripheral LPSPI11 base pointer */
  #define LPSPI11                                  ((LPSPI_Type *)LPSPI11_BASE)
  /** Peripheral LPSPI12 base address */
  #define LPSPI12_BASE                             (0x4019D000u)
  /** Peripheral LPSPI12 base pointer */
  #define LPSPI12                                  ((LPSPI_Type *)LPSPI12_BASE)
  /** Peripheral LPSPI13 base address */
  #define LPSPI13_BASE                             (0x4019E000u)
  /** Peripheral LPSPI13 base pointer */
  #define LPSPI13                                  ((LPSPI_Type *)LPSPI13_BASE)
  /** Peripheral LPSPI14 base address */
  #define LPSPI14_BASE                             (0x40484000u)
  /** Peripheral LPSPI14 base pointer */
  #define LPSPI14                                  ((LPSPI_Type *)LPSPI14_BASE)
  /** Peripheral LPSPI16 base address */
  #define LPSPI16_BASE                             (0x40405000u)
  /** Peripheral LPSPI16 base pointer */
  #define LPSPI16                                  ((LPSPI_Type *)LPSPI16_BASE)
  /** Array initializer of LPSPI peripheral base addresses */
  #define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE, LPSPI10_BASE, LPSPI11_BASE, LPSPI12_BASE, LPSPI13_BASE, LPSPI14_BASE, 0u, LPSPI16_BASE }
  /** Array initializer of LPSPI peripheral base pointers */
  #define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9, LPSPI10, LPSPI11, LPSPI12, LPSPI13, LPSPI14, (LPSPI_Type *)0u, LPSPI16 }
#endif
/** Interrupt vectors for the LPSPI peripheral type */
#define LPSPI_IRQS                               { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn, LP_FLEXCOMM10_IRQn, LP_FLEXCOMM11_IRQn, LP_FLEXCOMM12_IRQn, LP_FLEXCOMM13_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group LPSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPUART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
 * @{
 */

/** LPUART - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t GLOBAL;                            /**< Global, offset: 0x8 */
  __IO uint32_t PINCFG;                            /**< Pin Configuration, offset: 0xC */
  __IO uint32_t BAUD;                              /**< Baud Rate, offset: 0x10 */
  __IO uint32_t STAT;                              /**< Status, offset: 0x14 */
  __IO uint32_t CTRL;                              /**< Control, offset: 0x18 */
  __IO uint32_t DATA;                              /**< Data, offset: 0x1C */
  __IO uint32_t MATCH;                             /**< Match Address, offset: 0x20 */
  __IO uint32_t MODIR;                             /**< MODEM IrDA, offset: 0x24 */
  __IO uint32_t FIFO;                              /**< FIFO, offset: 0x28 */
  __IO uint32_t WATER;                             /**< Watermark, offset: 0x2C */
  __I  uint32_t DATARO;                            /**< Data Read-Only, offset: 0x30 */
       uint8_t RESERVED_0[460];
  __O  uint32_t TCBR[128];                         /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */
  __O  uint32_t TDBR[256];                         /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
} LPUART_Type;

/* ----------------------------------------------------------------------------
   -- LPUART Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPUART_Register_Masks LPUART Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
#define LPUART_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Identification Number
 *  0b0000000000000001..Standard feature set
 *  0b0000000000000011..Standard feature set with MODEM and IrDA support
 */
#define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

#define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
#define LPUART_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number */
#define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

#define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
#define LPUART_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number */
#define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
#define LPUART_PARAM_TXFIFO_SHIFT                (0U)
/*! TXFIFO - Transmit FIFO Size */
#define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

#define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
#define LPUART_PARAM_RXFIFO_SHIFT                (8U)
/*! RXFIFO - Receive FIFO Size */
#define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
/*! @} */

/*! @name GLOBAL - Global */
/*! @{ */

#define LPUART_GLOBAL_RST_MASK                   (0x2U)
#define LPUART_GLOBAL_RST_SHIFT                  (1U)
/*! RST - Software Reset
 *  0b0..Not reset
 *  0b1..Reset
 */
#define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
/*! @} */

/*! @name PINCFG - Pin Configuration */
/*! @{ */

#define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
#define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
/*! TRGSEL - Trigger Select
 *  0b00..Input trigger disabled
 *  0b01..Input trigger used instead of the RXD pin input
 *  0b10..Input trigger used instead of the CTS_B pin input
 *  0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
 */
#define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
/*! @} */

/*! @name BAUD - Baud Rate */
/*! @{ */

#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
#define LPUART_BAUD_SBR_SHIFT                    (0U)
/*! SBR - Baud Rate Modulo Divisor */
#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
#define LPUART_BAUD_SBNS_SHIFT                   (13U)
/*! SBNS - Stop Bit Number Select
 *  0b0..One stop bit
 *  0b1..Two stop bits
 */
#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
/*! RXEDGIE - RX Input Active Edge Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
/*! LBKDIE - LIN Break Detect Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
/*! RESYNCDIS - Resynchronization Disable
 *  0b0..Enable
 *  0b1..Disable
 */
#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
/*! BOTHEDGE - Both Edge Sampling
 *  0b0..Rising edge
 *  0b1..Both rising and falling edges
 */
#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
/*! MATCFG - Match Configuration
 *  0b00..Address match wake-up
 *  0b01..Idle match wake-up
 *  0b10..Match on and match off
 *  0b11..Enables RWU on data match and match on or off for the transmitter CTS input
 */
#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

#define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
#define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
/*! RIDMAE - Receiver Idle DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)

#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
/*! RDMAE - Receiver Full DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
/*! TDMAE - Transmitter DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
#define LPUART_BAUD_OSR_SHIFT                    (24U)
/*! OSR - Oversampling Ratio
 *  0b00000..Results in an OSR of 16
 *  0b00001..Reserved
 *  0b00010..Reserved
 *  0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1)
 *  0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1)
 *  0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1)
 *  0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1)
 *  0b00111..Results in an OSR of 8
 *  0b01000..Results in an OSR of 9
 *  0b01001..Results in an OSR of 10
 *  0b01010..Results in an OSR of 11
 *  0b01011..Results in an OSR of 12
 *  0b01100..Results in an OSR of 13
 *  0b01101..Results in an OSR of 14
 *  0b01110..Results in an OSR of 15
 *  0b01111..Results in an OSR of 16
 *  0b10000..Results in an OSR of 17
 *  0b10001..Results in an OSR of 18
 *  0b10010..Results in an OSR of 19
 *  0b10011..Results in an OSR of 20
 *  0b10100..Results in an OSR of 21
 *  0b10101..Results in an OSR of 22
 *  0b10110..Results in an OSR of 23
 *  0b10111..Results in an OSR of 24
 *  0b11000..Results in an OSR of 25
 *  0b11001..Results in an OSR of 26
 *  0b11010..Results in an OSR of 27
 *  0b11011..Results in an OSR of 28
 *  0b11100..Results in an OSR of 29
 *  0b11101..Results in an OSR of 30
 *  0b11110..Results in an OSR of 31
 *  0b11111..Results in an OSR of 32
 */
#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

#define LPUART_BAUD_M10_MASK                     (0x20000000U)
#define LPUART_BAUD_M10_SHIFT                    (29U)
/*! M10 - 10-Bit Mode Select
 *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters
 *  0b1..Receiver and transmitter use 10-bit data characters
 */
#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
/*! MAEN2 - Match Address Mode Enable 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
/*! MAEN1 - Match Address Mode Enable 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
/*! @} */

/*! @name STAT - Status */
/*! @{ */

#define LPUART_STAT_LBKFE_MASK                   (0x1U)
#define LPUART_STAT_LBKFE_SHIFT                  (0U)
/*! LBKFE - LIN Break Flag Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_STAT_LBKFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK)

#define LPUART_STAT_AME_MASK                     (0x2U)
#define LPUART_STAT_AME_SHIFT                    (1U)
/*! AME - Address Mark Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_STAT_AME(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK)

#define LPUART_STAT_MA2F_MASK                    (0x4000U)
#define LPUART_STAT_MA2F_SHIFT                   (14U)
/*! MA2F - Match 2 Flag
 *  0b0..Not equal to MA2
 *  0b1..Equal to MA2
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

#define LPUART_STAT_MA1F_MASK                    (0x8000U)
#define LPUART_STAT_MA1F_SHIFT                   (15U)
/*! MA1F - Match 1 Flag
 *  0b0..Not equal to MA1
 *  0b1..Equal to MA1
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

#define LPUART_STAT_PF_MASK                      (0x10000U)
#define LPUART_STAT_PF_SHIFT                     (16U)
/*! PF - Parity Error Flag
 *  0b0..No parity error detected
 *  0b1..Parity error detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

#define LPUART_STAT_FE_MASK                      (0x20000U)
#define LPUART_STAT_FE_SHIFT                     (17U)
/*! FE - Framing Error Flag
 *  0b0..No framing error detected (this does not guarantee that the framing is correct)
 *  0b1..Framing error detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

#define LPUART_STAT_NF_MASK                      (0x40000U)
#define LPUART_STAT_NF_SHIFT                     (18U)
/*! NF - Noise Flag
 *  0b0..No noise detected
 *  0b1..Noise detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

#define LPUART_STAT_OR_MASK                      (0x80000U)
#define LPUART_STAT_OR_SHIFT                     (19U)
/*! OR - Receiver Overrun Flag
 *  0b0..No overrun
 *  0b1..Receive overrun (new LPUART data is lost)
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

#define LPUART_STAT_IDLE_MASK                    (0x100000U)
#define LPUART_STAT_IDLE_SHIFT                   (20U)
/*! IDLE - Idle Line Flag
 *  0b0..Idle line detected
 *  0b1..Idle line not detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

#define LPUART_STAT_RDRF_MASK                    (0x200000U)
#define LPUART_STAT_RDRF_SHIFT                   (21U)
/*! RDRF - Receive Data Register Full Flag
 *  0b0..Equal to or less than watermark
 *  0b1..Greater than watermark
 */
#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

#define LPUART_STAT_TC_MASK                      (0x400000U)
#define LPUART_STAT_TC_SHIFT                     (22U)
/*! TC - Transmission Complete Flag
 *  0b0..Transmitter active
 *  0b1..Transmitter idle
 */
#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

#define LPUART_STAT_TDRE_MASK                    (0x800000U)
#define LPUART_STAT_TDRE_SHIFT                   (23U)
/*! TDRE - Transmit Data Register Empty Flag
 *  0b0..Greater than watermark
 *  0b1..Equal to or less than watermark
 */
#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

#define LPUART_STAT_RAF_MASK                     (0x1000000U)
#define LPUART_STAT_RAF_SHIFT                    (24U)
/*! RAF - Receiver Active Flag
 *  0b0..Idle, waiting for a start bit
 *  0b1..Receiver active (RXD pin input not idle)
 */
#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
#define LPUART_STAT_LBKDE_SHIFT                  (25U)
/*! LBKDE - LIN Break Detection Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
#define LPUART_STAT_BRK13_SHIFT                  (26U)
/*! BRK13 - Break Character Generation Length
 *  0b0..9 to 13 bit times
 *  0b1..12 to 15 bit times
 */
#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
#define LPUART_STAT_RWUID_SHIFT                  (27U)
/*! RWUID - Receive Wake Up Idle Detect
 *  0b0..STAT[IDLE] does not become 1
 *  0b1..STAT[IDLE] becomes 1
 */
#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
#define LPUART_STAT_RXINV_SHIFT                  (28U)
/*! RXINV - Receive Data Inversion
 *  0b0..Inverted
 *  0b1..Not inverted
 */
#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
#define LPUART_STAT_MSBF_SHIFT                   (29U)
/*! MSBF - MSB First
 *  0b0..LSB
 *  0b1..MSB
 */
#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
 *  0b0..Not occurred
 *  0b1..Occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
/*! LBKDIF - LIN Break Detect Interrupt Flag
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
/*! @} */

/*! @name CTRL - Control */
/*! @{ */

#define LPUART_CTRL_PT_MASK                      (0x1U)
#define LPUART_CTRL_PT_SHIFT                     (0U)
/*! PT - Parity Type
 *  0b0..Even parity
 *  0b1..Odd parity
 */
#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

#define LPUART_CTRL_PE_MASK                      (0x2U)
#define LPUART_CTRL_PE_SHIFT                     (1U)
/*! PE - Parity Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

#define LPUART_CTRL_ILT_MASK                     (0x4U)
#define LPUART_CTRL_ILT_SHIFT                    (2U)
/*! ILT - Idle Line Type Select
 *  0b0..After the start bit
 *  0b1..After the stop bit
 */
#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

#define LPUART_CTRL_WAKE_MASK                    (0x8U)
#define LPUART_CTRL_WAKE_SHIFT                   (3U)
/*! WAKE - Receiver Wake-Up Method Select
 *  0b0..Idle
 *  0b1..Mark
 */
#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

#define LPUART_CTRL_M_MASK                       (0x10U)
#define LPUART_CTRL_M_SHIFT                      (4U)
/*! M - 9-Bit Or 8-Bit Mode Select
 *  0b0..8-bit
 *  0b1..9-bit
 */
#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

#define LPUART_CTRL_RSRC_MASK                    (0x20U)
#define LPUART_CTRL_RSRC_SHIFT                   (5U)
/*! RSRC - Receiver Source Select
 *  0b0..Internal Loopback mode
 *  0b1..Single-wire mode
 */
#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
/*! DOZEEN - Doze Mode
 *  0b0..Enable
 *  0b1..Disable
 */
#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
/*! LOOPS - Loop Mode Select
 *  0b0..Normal operation: RXD and TXD use separate pins
 *  0b1..Loop mode or Single-Wire mode
 */
#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
/*! IDLECFG - Idle Configuration
 *  0b000..1
 *  0b001..2
 *  0b010..4
 *  0b011..8
 *  0b100..16
 *  0b101..32
 *  0b110..64
 *  0b111..128
 */
#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

#define LPUART_CTRL_M7_MASK                      (0x800U)
#define LPUART_CTRL_M7_SHIFT                     (11U)
/*! M7 - 7-Bit Mode Select
 *  0b0..8-bit to 10-bit
 *  0b1..7-bit
 */
#define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
/*! MA2IE - Match 2 (MA2F) Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
/*! MA1IE - Match 1 (MA1F) Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

#define LPUART_CTRL_SBK_MASK                     (0x10000U)
#define LPUART_CTRL_SBK_SHIFT                    (16U)
/*! SBK - Send Break
 *  0b0..Normal transmitter operation
 *  0b1..Queue break character(s) to be sent
 */
#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

#define LPUART_CTRL_RWU_MASK                     (0x20000U)
#define LPUART_CTRL_RWU_SHIFT                    (17U)
/*! RWU - Receiver Wake-Up Control
 *  0b0..Normal receiver operation
 *  0b1..LPUART receiver in standby, waiting for a wake-up condition
 */
#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

#define LPUART_CTRL_RE_MASK                      (0x40000U)
#define LPUART_CTRL_RE_SHIFT                     (18U)
/*! RE - Receiver Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

#define LPUART_CTRL_TE_MASK                      (0x80000U)
#define LPUART_CTRL_TE_SHIFT                     (19U)
/*! TE - Transmitter Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
#define LPUART_CTRL_ILIE_SHIFT                   (20U)
/*! ILIE - Idle Line Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

#define LPUART_CTRL_RIE_MASK                     (0x200000U)
#define LPUART_CTRL_RIE_SHIFT                    (21U)
/*! RIE - Receiver Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
#define LPUART_CTRL_TCIE_SHIFT                   (22U)
/*! TCIE - Transmission Complete Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

#define LPUART_CTRL_TIE_MASK                     (0x800000U)
#define LPUART_CTRL_TIE_SHIFT                    (23U)
/*! TIE - Transmit Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
#define LPUART_CTRL_PEIE_SHIFT                   (24U)
/*! PEIE - Parity Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
#define LPUART_CTRL_FEIE_SHIFT                   (25U)
/*! FEIE - Framing Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
#define LPUART_CTRL_NEIE_SHIFT                   (26U)
/*! NEIE - Noise Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
#define LPUART_CTRL_ORIE_SHIFT                   (27U)
/*! ORIE - Overrun Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
#define LPUART_CTRL_TXINV_SHIFT                  (28U)
/*! TXINV - Transmit Data Inversion
 *  0b0..Not inverted
 *  0b1..Inverted
 */
#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
/*! TXDIR - TXD Pin Direction in Single-Wire Mode
 *  0b0..Input
 *  0b1..Output
 */
#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
#define LPUART_CTRL_R9T8_SHIFT                   (30U)
/*! R9T8 - Receive Bit 9 Transmit Bit 8 */
#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
#define LPUART_CTRL_R8T9_SHIFT                   (31U)
/*! R8T9 - Receive Bit 8 Transmit Bit 9 */
#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
/*! @} */

/*! @name DATA - Data */
/*! @{ */

#define LPUART_DATA_R0T0_MASK                    (0x1U)
#define LPUART_DATA_R0T0_SHIFT                   (0U)
/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */
#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

#define LPUART_DATA_R1T1_MASK                    (0x2U)
#define LPUART_DATA_R1T1_SHIFT                   (1U)
/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */
#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

#define LPUART_DATA_R2T2_MASK                    (0x4U)
#define LPUART_DATA_R2T2_SHIFT                   (2U)
/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */
#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

#define LPUART_DATA_R3T3_MASK                    (0x8U)
#define LPUART_DATA_R3T3_SHIFT                   (3U)
/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */
#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

#define LPUART_DATA_R4T4_MASK                    (0x10U)
#define LPUART_DATA_R4T4_SHIFT                   (4U)
/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */
#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

#define LPUART_DATA_R5T5_MASK                    (0x20U)
#define LPUART_DATA_R5T5_SHIFT                   (5U)
/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */
#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

#define LPUART_DATA_R6T6_MASK                    (0x40U)
#define LPUART_DATA_R6T6_SHIFT                   (6U)
/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */
#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

#define LPUART_DATA_R7T7_MASK                    (0x80U)
#define LPUART_DATA_R7T7_SHIFT                   (7U)
/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */
#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

#define LPUART_DATA_R8T8_MASK                    (0x100U)
#define LPUART_DATA_R8T8_SHIFT                   (8U)
/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */
#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

#define LPUART_DATA_R9T9_MASK                    (0x200U)
#define LPUART_DATA_R9T9_SHIFT                   (9U)
/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */
#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

#define LPUART_DATA_LINBRK_MASK                  (0x400U)
#define LPUART_DATA_LINBRK_SHIFT                 (10U)
/*! LINBRK - LIN Break
 *  0b0..Not detected
 *  0b1..Detected
 */
#define LPUART_DATA_LINBRK(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK)

#define LPUART_DATA_IDLINE_MASK                  (0x800U)
#define LPUART_DATA_IDLINE_SHIFT                 (11U)
/*! IDLINE - Idle Line
 *  0b0..Not idle
 *  0b1..Idle
 */
#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
/*! RXEMPT - Receive Buffer Empty
 *  0b0..Valid data
 *  0b1..Invalid data and empty
 */
#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
#define LPUART_DATA_FRETSC_SHIFT                 (13U)
/*! FRETSC - Frame Error Transmit Special Character
 *  0b0..Received without a frame error on reads or transmits a normal character on writes
 *  0b1..Received with a frame error on reads or transmits an idle or break character on writes
 */
#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
#define LPUART_DATA_PARITYE_SHIFT                (14U)
/*! PARITYE - Parity Error
 *  0b0..Received without a parity error
 *  0b1..Received with a parity error
 */
#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

#define LPUART_DATA_NOISY_MASK                   (0x8000U)
#define LPUART_DATA_NOISY_SHIFT                  (15U)
/*! NOISY - Noisy Data Received
 *  0b0..Received without noise
 *  0b1..Received with noise
 */
#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
/*! @} */

/*! @name MATCH - Match Address */
/*! @{ */

#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
#define LPUART_MATCH_MA1_SHIFT                   (0U)
/*! MA1 - Match Address 1 */
#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
#define LPUART_MATCH_MA2_SHIFT                   (16U)
/*! MA2 - Match Address 2 */
#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
/*! @} */

/*! @name MODIR - MODEM IrDA */
/*! @{ */

#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
/*! TXCTSE - Transmitter CTS Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
/*! TXRTSE - Transmitter RTS Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
/*! TXRTSPOL - Transmitter RTS Polarity
 *  0b0..Active low
 *  0b1..Active high
 */
#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
/*! RXRTSE - Receiver RTS Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
/*! TXCTSC - Transmit CTS Configuration
 *  0b0..Sampled at the start of each character
 *  0b1..Sampled when the transmitter is idle
 */
#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
/*! TXCTSSRC - Transmit CTS Source
 *  0b0..The CTS_B pin
 *  0b1..An internal connection to the receiver address match result
 */
#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

#define LPUART_MODIR_RTSWATER_MASK               (0x700U)
#define LPUART_MODIR_RTSWATER_SHIFT              (8U)
/*! RTSWATER - Receive RTS Configuration */
#define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

#define LPUART_MODIR_TNP_MASK                    (0x30000U)
#define LPUART_MODIR_TNP_SHIFT                   (16U)
/*! TNP - Transmitter Narrow Pulse
 *  0b00..1 / OSR
 *  0b01..2 / OSR
 *  0b10..3 / OSR
 *  0b11..4 / OSR
 */
#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

#define LPUART_MODIR_IREN_MASK                   (0x40000U)
#define LPUART_MODIR_IREN_SHIFT                  (18U)
/*! IREN - IR Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
/*! @} */

/*! @name FIFO - FIFO */
/*! @{ */

#define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
#define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
/*! RXFIFOSIZE - Receive FIFO Buffer Depth
 *  0b000..1
 *  0b001..4
 *  0b010..8
 *  0b011..16
 *  0b100..32
 *  0b101..64
 *  0b110..128
 *  0b111..256
 */
#define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

#define LPUART_FIFO_RXFE_MASK                    (0x8U)
#define LPUART_FIFO_RXFE_SHIFT                   (3U)
/*! RXFE - Receive FIFO Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

#define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
#define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
 *  0b000..1
 *  0b001..4
 *  0b010..8
 *  0b011..16
 *  0b100..32
 *  0b101..64
 *  0b110..128
 *  0b111..256
 */
#define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

#define LPUART_FIFO_TXFE_MASK                    (0x80U)
#define LPUART_FIFO_TXFE_SHIFT                   (7U)
/*! TXFE - Transmit FIFO Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

#define LPUART_FIFO_RXUFE_MASK                   (0x100U)
#define LPUART_FIFO_RXUFE_SHIFT                  (8U)
/*! RXUFE - Receive FIFO Underflow Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

#define LPUART_FIFO_TXOFE_MASK                   (0x200U)
#define LPUART_FIFO_TXOFE_SHIFT                  (9U)
/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

#define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
#define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
/*! RXIDEN - Receiver Idle Empty Enable
 *  0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle
 *  0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character
 *  0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters
 *  0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters
 *  0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters
 *  0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters
 *  0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters
 *  0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
 */
#define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

#define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
#define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
/*! RXFLUSH - Receive FIFO Flush
 *  0b0..No effect
 *  0b1..All data flushed out
 */
#define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

#define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
#define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
/*! TXFLUSH - Transmit FIFO Flush
 *  0b0..No effect
 *  0b1..All data flushed out
 */
#define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

#define LPUART_FIFO_RXUF_MASK                    (0x10000U)
#define LPUART_FIFO_RXUF_SHIFT                   (16U)
/*! RXUF - Receiver FIFO Underflow Flag
 *  0b0..No underflow
 *  0b1..Underflow
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

#define LPUART_FIFO_TXOF_MASK                    (0x20000U)
#define LPUART_FIFO_TXOF_SHIFT                   (17U)
/*! TXOF - Transmitter FIFO Overflow Flag
 *  0b0..No overflow
 *  0b1..Overflow
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

#define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
#define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
/*! RXEMPT - Receive FIFO Or Buffer Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

#define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
#define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
/*! TXEMPT - Transmit FIFO Or Buffer Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
/*! @} */

/*! @name WATER - Watermark */
/*! @{ */

#define LPUART_WATER_TXWATER_MASK                (0x7U)
#define LPUART_WATER_TXWATER_SHIFT               (0U)
/*! TXWATER - Transmit Watermark */
#define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

#define LPUART_WATER_TXCOUNT_MASK                (0xF00U)
#define LPUART_WATER_TXCOUNT_SHIFT               (8U)
/*! TXCOUNT - Transmit Counter */
#define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

#define LPUART_WATER_RXWATER_MASK                (0x70000U)
#define LPUART_WATER_RXWATER_SHIFT               (16U)
/*! RXWATER - Receive Watermark */
#define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

#define LPUART_WATER_RXCOUNT_MASK                (0xF000000U)
#define LPUART_WATER_RXCOUNT_SHIFT               (24U)
/*! RXCOUNT - Receive Counter */
#define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
/*! @} */

/*! @name DATARO - Data Read-Only */
/*! @{ */

#define LPUART_DATARO_DATA_MASK                  (0xFFFFU)
#define LPUART_DATARO_DATA_SHIFT                 (0U)
/*! DATA - Receive Data */
#define LPUART_DATARO_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK)
/*! @} */

/*! @name TCBR - Transmit Command Burst */
/*! @{ */

#define LPUART_TCBR_DATA_MASK                    (0xFFFFU)
#define LPUART_TCBR_DATA_SHIFT                   (0U)
/*! DATA - Data */
#define LPUART_TCBR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK)
/*! @} */

/* The count of LPUART_TCBR */
#define LPUART_TCBR_COUNT                        (128U)

/*! @name TDBR - Transmit Data Burst */
/*! @{ */

#define LPUART_TDBR_DATA0_MASK                   (0xFFU)
#define LPUART_TDBR_DATA0_SHIFT                  (0U)
/*! DATA0 - Data0 */
#define LPUART_TDBR_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK)

#define LPUART_TDBR_DATA1_MASK                   (0xFF00U)
#define LPUART_TDBR_DATA1_SHIFT                  (8U)
/*! DATA1 - Data1 */
#define LPUART_TDBR_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK)

#define LPUART_TDBR_DATA2_MASK                   (0xFF0000U)
#define LPUART_TDBR_DATA2_SHIFT                  (16U)
/*! DATA2 - Data2 */
#define LPUART_TDBR_DATA2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK)

#define LPUART_TDBR_DATA3_MASK                   (0xFF000000U)
#define LPUART_TDBR_DATA3_SHIFT                  (24U)
/*! DATA3 - Data3 */
#define LPUART_TDBR_DATA3(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK)
/*! @} */

/* The count of LPUART_TDBR */
#define LPUART_TDBR_COUNT                        (256U)


/*!
 * @}
 */ /* end of group LPUART_Register_Masks */


/* LPUART - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPUART0 base address */
  #define LPUART0_BASE                             (0x50110000u)
  /** Peripheral LPUART0 base address */
  #define LPUART0_BASE_NS                          (0x40110000u)
  /** Peripheral LPUART0 base pointer */
  #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
  /** Peripheral LPUART0 base pointer */
  #define LPUART0_NS                               ((LPUART_Type *)LPUART0_BASE_NS)
  /** Peripheral LPUART1 base address */
  #define LPUART1_BASE                             (0x50111000u)
  /** Peripheral LPUART1 base address */
  #define LPUART1_BASE_NS                          (0x40111000u)
  /** Peripheral LPUART1 base pointer */
  #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
  /** Peripheral LPUART1 base pointer */
  #define LPUART1_NS                               ((LPUART_Type *)LPUART1_BASE_NS)
  /** Peripheral LPUART2 base address */
  #define LPUART2_BASE                             (0x50112000u)
  /** Peripheral LPUART2 base address */
  #define LPUART2_BASE_NS                          (0x40112000u)
  /** Peripheral LPUART2 base pointer */
  #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
  /** Peripheral LPUART2 base pointer */
  #define LPUART2_NS                               ((LPUART_Type *)LPUART2_BASE_NS)
  /** Peripheral LPUART3 base address */
  #define LPUART3_BASE                             (0x50113000u)
  /** Peripheral LPUART3 base address */
  #define LPUART3_BASE_NS                          (0x40113000u)
  /** Peripheral LPUART3 base pointer */
  #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
  /** Peripheral LPUART3 base pointer */
  #define LPUART3_NS                               ((LPUART_Type *)LPUART3_BASE_NS)
  /** Peripheral LPUART4 base address */
  #define LPUART4_BASE                             (0x50171000u)
  /** Peripheral LPUART4 base address */
  #define LPUART4_BASE_NS                          (0x40171000u)
  /** Peripheral LPUART4 base pointer */
  #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
  /** Peripheral LPUART4 base pointer */
  #define LPUART4_NS                               ((LPUART_Type *)LPUART4_BASE_NS)
  /** Peripheral LPUART5 base address */
  #define LPUART5_BASE                             (0x50172000u)
  /** Peripheral LPUART5 base address */
  #define LPUART5_BASE_NS                          (0x40172000u)
  /** Peripheral LPUART5 base pointer */
  #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
  /** Peripheral LPUART5 base pointer */
  #define LPUART5_NS                               ((LPUART_Type *)LPUART5_BASE_NS)
  /** Peripheral LPUART6 base address */
  #define LPUART6_BASE                             (0x50173000u)
  /** Peripheral LPUART6 base address */
  #define LPUART6_BASE_NS                          (0x40173000u)
  /** Peripheral LPUART6 base pointer */
  #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
  /** Peripheral LPUART6 base pointer */
  #define LPUART6_NS                               ((LPUART_Type *)LPUART6_BASE_NS)
  /** Peripheral LPUART7 base address */
  #define LPUART7_BASE                             (0x50174000u)
  /** Peripheral LPUART7 base address */
  #define LPUART7_BASE_NS                          (0x40174000u)
  /** Peripheral LPUART7 base pointer */
  #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
  /** Peripheral LPUART7 base pointer */
  #define LPUART7_NS                               ((LPUART_Type *)LPUART7_BASE_NS)
  /** Peripheral LPUART8 base address */
  #define LPUART8_BASE                             (0x50199000u)
  /** Peripheral LPUART8 base address */
  #define LPUART8_BASE_NS                          (0x40199000u)
  /** Peripheral LPUART8 base pointer */
  #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
  /** Peripheral LPUART8 base pointer */
  #define LPUART8_NS                               ((LPUART_Type *)LPUART8_BASE_NS)
  /** Peripheral LPUART9 base address */
  #define LPUART9_BASE                             (0x5019A000u)
  /** Peripheral LPUART9 base address */
  #define LPUART9_BASE_NS                          (0x4019A000u)
  /** Peripheral LPUART9 base pointer */
  #define LPUART9                                  ((LPUART_Type *)LPUART9_BASE)
  /** Peripheral LPUART9 base pointer */
  #define LPUART9_NS                               ((LPUART_Type *)LPUART9_BASE_NS)
  /** Peripheral LPUART10 base address */
  #define LPUART10_BASE                            (0x5019B000u)
  /** Peripheral LPUART10 base address */
  #define LPUART10_BASE_NS                         (0x4019B000u)
  /** Peripheral LPUART10 base pointer */
  #define LPUART10                                 ((LPUART_Type *)LPUART10_BASE)
  /** Peripheral LPUART10 base pointer */
  #define LPUART10_NS                              ((LPUART_Type *)LPUART10_BASE_NS)
  /** Peripheral LPUART11 base address */
  #define LPUART11_BASE                            (0x5019C000u)
  /** Peripheral LPUART11 base address */
  #define LPUART11_BASE_NS                         (0x4019C000u)
  /** Peripheral LPUART11 base pointer */
  #define LPUART11                                 ((LPUART_Type *)LPUART11_BASE)
  /** Peripheral LPUART11 base pointer */
  #define LPUART11_NS                              ((LPUART_Type *)LPUART11_BASE_NS)
  /** Peripheral LPUART12 base address */
  #define LPUART12_BASE                            (0x5019D000u)
  /** Peripheral LPUART12 base address */
  #define LPUART12_BASE_NS                         (0x4019D000u)
  /** Peripheral LPUART12 base pointer */
  #define LPUART12                                 ((LPUART_Type *)LPUART12_BASE)
  /** Peripheral LPUART12 base pointer */
  #define LPUART12_NS                              ((LPUART_Type *)LPUART12_BASE_NS)
  /** Peripheral LPUART13 base address */
  #define LPUART13_BASE                            (0x5019E000u)
  /** Peripheral LPUART13 base address */
  #define LPUART13_BASE_NS                         (0x4019E000u)
  /** Peripheral LPUART13 base pointer */
  #define LPUART13                                 ((LPUART_Type *)LPUART13_BASE)
  /** Peripheral LPUART13 base pointer */
  #define LPUART13_NS                              ((LPUART_Type *)LPUART13_BASE_NS)
  /** Array initializer of LPUART peripheral base addresses */
  #define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE, LPUART13_BASE }
  /** Array initializer of LPUART peripheral base pointers */
  #define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12, LPUART13 }
  /** Array initializer of LPUART peripheral base addresses */
  #define LPUART_BASE_ADDRS_NS                     { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS, LPUART10_BASE_NS, LPUART11_BASE_NS, LPUART12_BASE_NS, LPUART13_BASE_NS }
  /** Array initializer of LPUART peripheral base pointers */
  #define LPUART_BASE_PTRS_NS                      { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS, LPUART10_NS, LPUART11_NS, LPUART12_NS, LPUART13_NS }
#else
  /** Peripheral LPUART0 base address */
  #define LPUART0_BASE                             (0x40110000u)
  /** Peripheral LPUART0 base pointer */
  #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
  /** Peripheral LPUART1 base address */
  #define LPUART1_BASE                             (0x40111000u)
  /** Peripheral LPUART1 base pointer */
  #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
  /** Peripheral LPUART2 base address */
  #define LPUART2_BASE                             (0x40112000u)
  /** Peripheral LPUART2 base pointer */
  #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
  /** Peripheral LPUART3 base address */
  #define LPUART3_BASE                             (0x40113000u)
  /** Peripheral LPUART3 base pointer */
  #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
  /** Peripheral LPUART4 base address */
  #define LPUART4_BASE                             (0x40171000u)
  /** Peripheral LPUART4 base pointer */
  #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
  /** Peripheral LPUART5 base address */
  #define LPUART5_BASE                             (0x40172000u)
  /** Peripheral LPUART5 base pointer */
  #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
  /** Peripheral LPUART6 base address */
  #define LPUART6_BASE                             (0x40173000u)
  /** Peripheral LPUART6 base pointer */
  #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
  /** Peripheral LPUART7 base address */
  #define LPUART7_BASE                             (0x40174000u)
  /** Peripheral LPUART7 base pointer */
  #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
  /** Peripheral LPUART8 base address */
  #define LPUART8_BASE                             (0x40199000u)
  /** Peripheral LPUART8 base pointer */
  #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
  /** Peripheral LPUART9 base address */
  #define LPUART9_BASE                             (0x4019A000u)
  /** Peripheral LPUART9 base pointer */
  #define LPUART9                                  ((LPUART_Type *)LPUART9_BASE)
  /** Peripheral LPUART10 base address */
  #define LPUART10_BASE                            (0x4019B000u)
  /** Peripheral LPUART10 base pointer */
  #define LPUART10                                 ((LPUART_Type *)LPUART10_BASE)
  /** Peripheral LPUART11 base address */
  #define LPUART11_BASE                            (0x4019C000u)
  /** Peripheral LPUART11 base pointer */
  #define LPUART11                                 ((LPUART_Type *)LPUART11_BASE)
  /** Peripheral LPUART12 base address */
  #define LPUART12_BASE                            (0x4019D000u)
  /** Peripheral LPUART12 base pointer */
  #define LPUART12                                 ((LPUART_Type *)LPUART12_BASE)
  /** Peripheral LPUART13 base address */
  #define LPUART13_BASE                            (0x4019E000u)
  /** Peripheral LPUART13 base pointer */
  #define LPUART13                                 ((LPUART_Type *)LPUART13_BASE)
  /** Array initializer of LPUART peripheral base addresses */
  #define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE, LPUART13_BASE }
  /** Array initializer of LPUART peripheral base pointers */
  #define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12, LPUART13 }
#endif
/** Interrupt vectors for the LPUART peripheral type */
#define LPUART_RX_TX_IRQS                        { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn, LP_FLEXCOMM10_IRQn, LP_FLEXCOMM11_IRQn, LP_FLEXCOMM12_IRQn, LP_FLEXCOMM13_IRQn }
#define LPUART_ERR_IRQS                          { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn, LP_FLEXCOMM10_IRQn, LP_FLEXCOMM11_IRQn, LP_FLEXCOMM12_IRQn, LP_FLEXCOMM13_IRQn }

/*!
 * @}
 */ /* end of group LPUART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LP_FLEXCOMM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LP_FLEXCOMM_Peripheral_Access_Layer LP_FLEXCOMM Peripheral Access Layer
 * @{
 */

/** LP_FLEXCOMM - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4084];
  __I  uint32_t ISTAT;                             /**< Interrupt Status, offset: 0xFF4 */
  __IO uint32_t PSELID;                            /**< Peripheral Select and ID, offset: 0xFF8 */
} LP_FLEXCOMM_Type;

/* ----------------------------------------------------------------------------
   -- LP_FLEXCOMM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LP_FLEXCOMM_Register_Masks LP_FLEXCOMM Register Masks
 * @{
 */

/*! @name ISTAT - Interrupt Status */
/*! @{ */

#define LP_FLEXCOMM_ISTAT_UARTTX_MASK            (0x1U)
#define LP_FLEXCOMM_ISTAT_UARTTX_SHIFT           (0U)
/*! UARTTX - UART TX Interrupt
 *  0b0..Clear
 *  0b1..Set
 */
#define LP_FLEXCOMM_ISTAT_UARTTX(x)              (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTTX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTTX_MASK)

#define LP_FLEXCOMM_ISTAT_UARTRX_MASK            (0x2U)
#define LP_FLEXCOMM_ISTAT_UARTRX_SHIFT           (1U)
/*! UARTRX - UART RX Interrupt
 *  0b0..Clear
 *  0b1..Set
 */
#define LP_FLEXCOMM_ISTAT_UARTRX(x)              (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTRX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTRX_MASK)

#define LP_FLEXCOMM_ISTAT_SPI_MASK               (0x4U)
#define LP_FLEXCOMM_ISTAT_SPI_SHIFT              (2U)
/*! SPI - SPI Interrupt
 *  0b0..Clear
 *  0b1..Set
 */
#define LP_FLEXCOMM_ISTAT_SPI(x)                 (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_SPI_SHIFT)) & LP_FLEXCOMM_ISTAT_SPI_MASK)

#define LP_FLEXCOMM_ISTAT_I2CM_MASK              (0x10U)
#define LP_FLEXCOMM_ISTAT_I2CM_SHIFT             (4U)
/*! I2CM - I2C Controller Interrupt
 *  0b0..Clear
 *  0b1..Set
 */
#define LP_FLEXCOMM_ISTAT_I2CM(x)                (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CM_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CM_MASK)

#define LP_FLEXCOMM_ISTAT_I2CS_MASK              (0x20U)
#define LP_FLEXCOMM_ISTAT_I2CS_SHIFT             (5U)
/*! I2CS - I2C Subordinate Interrupt
 *  0b0..Clear
 *  0b1..Set
 */
#define LP_FLEXCOMM_ISTAT_I2CS(x)                (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CS_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CS_MASK)
/*! @} */

/*! @name PSELID - Peripheral Select and ID */
/*! @{ */

#define LP_FLEXCOMM_PSELID_PERSEL_MASK           (0x7U)
#define LP_FLEXCOMM_PSELID_PERSEL_SHIFT          (0U)
/*! PERSEL - Peripheral Select
 *  0b000..No peripheral selected
 *  0b001..UART
 *  0b011..I2C
 *  0b111..UART and I2C
 *  0b010..SPI
 */
#define LP_FLEXCOMM_PSELID_PERSEL(x)             (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_PERSEL_SHIFT)) & LP_FLEXCOMM_PSELID_PERSEL_MASK)

#define LP_FLEXCOMM_PSELID_LOCK_MASK             (0x8U)
#define LP_FLEXCOMM_PSELID_LOCK_SHIFT            (3U)
/*! LOCK - Lock
 *  0b0..PERSEL is writable
 *  0b1..PERSEL is not writable
 */
#define LP_FLEXCOMM_PSELID_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_LOCK_SHIFT)) & LP_FLEXCOMM_PSELID_LOCK_MASK)

#define LP_FLEXCOMM_PSELID_UARTPRESENT_MASK      (0x10U)
#define LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT     (4U)
/*! UARTPRESENT - UART Present
 *  0b0..Not supported
 *  0b1..Supported
 */
#define LP_FLEXCOMM_PSELID_UARTPRESENT(x)        (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_UARTPRESENT_MASK)

#define LP_FLEXCOMM_PSELID_SPIPRESENT_MASK       (0x20U)
#define LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT      (5U)
/*! SPIPRESENT - SPI Present
 *  0b0..Not supported
 *  0b1..Supported
 */
#define LP_FLEXCOMM_PSELID_SPIPRESENT(x)         (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_SPIPRESENT_MASK)

#define LP_FLEXCOMM_PSELID_I2CPRESENT_MASK       (0x40U)
#define LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT      (6U)
/*! I2CPRESENT - I2C Present
 *  0b0..Not supported
 *  0b1..Supported
 */
#define LP_FLEXCOMM_PSELID_I2CPRESENT(x)         (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_I2CPRESENT_MASK)

#define LP_FLEXCOMM_PSELID_ID_MASK               (0xFFFFF000U)
#define LP_FLEXCOMM_PSELID_ID_SHIFT              (12U)
/*! ID - LP_FLEXCOMM interface ID */
#define LP_FLEXCOMM_PSELID_ID(x)                 (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_ID_SHIFT)) & LP_FLEXCOMM_PSELID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LP_FLEXCOMM_Register_Masks */


/* LP_FLEXCOMM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LP_FLEXCOMM0 base address */
  #define LP_FLEXCOMM0_BASE                        (0x50110000u)
  /** Peripheral LP_FLEXCOMM0 base address */
  #define LP_FLEXCOMM0_BASE_NS                     (0x40110000u)
  /** Peripheral LP_FLEXCOMM0 base pointer */
  #define LP_FLEXCOMM0                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE)
  /** Peripheral LP_FLEXCOMM0 base pointer */
  #define LP_FLEXCOMM0_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS)
  /** Peripheral LP_FLEXCOMM1 base address */
  #define LP_FLEXCOMM1_BASE                        (0x50111000u)
  /** Peripheral LP_FLEXCOMM1 base address */
  #define LP_FLEXCOMM1_BASE_NS                     (0x40111000u)
  /** Peripheral LP_FLEXCOMM1 base pointer */
  #define LP_FLEXCOMM1                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE)
  /** Peripheral LP_FLEXCOMM1 base pointer */
  #define LP_FLEXCOMM1_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS)
  /** Peripheral LP_FLEXCOMM2 base address */
  #define LP_FLEXCOMM2_BASE                        (0x50112000u)
  /** Peripheral LP_FLEXCOMM2 base address */
  #define LP_FLEXCOMM2_BASE_NS                     (0x40112000u)
  /** Peripheral LP_FLEXCOMM2 base pointer */
  #define LP_FLEXCOMM2                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE)
  /** Peripheral LP_FLEXCOMM2 base pointer */
  #define LP_FLEXCOMM2_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS)
  /** Peripheral LP_FLEXCOMM3 base address */
  #define LP_FLEXCOMM3_BASE                        (0x50113000u)
  /** Peripheral LP_FLEXCOMM3 base address */
  #define LP_FLEXCOMM3_BASE_NS                     (0x40113000u)
  /** Peripheral LP_FLEXCOMM3 base pointer */
  #define LP_FLEXCOMM3                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE)
  /** Peripheral LP_FLEXCOMM3 base pointer */
  #define LP_FLEXCOMM3_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS)
  /** Peripheral LP_FLEXCOMM4 base address */
  #define LP_FLEXCOMM4_BASE                        (0x50171000u)
  /** Peripheral LP_FLEXCOMM4 base address */
  #define LP_FLEXCOMM4_BASE_NS                     (0x40171000u)
  /** Peripheral LP_FLEXCOMM4 base pointer */
  #define LP_FLEXCOMM4                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE)
  /** Peripheral LP_FLEXCOMM4 base pointer */
  #define LP_FLEXCOMM4_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS)
  /** Peripheral LP_FLEXCOMM5 base address */
  #define LP_FLEXCOMM5_BASE                        (0x50172000u)
  /** Peripheral LP_FLEXCOMM5 base address */
  #define LP_FLEXCOMM5_BASE_NS                     (0x40172000u)
  /** Peripheral LP_FLEXCOMM5 base pointer */
  #define LP_FLEXCOMM5                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE)
  /** Peripheral LP_FLEXCOMM5 base pointer */
  #define LP_FLEXCOMM5_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS)
  /** Peripheral LP_FLEXCOMM6 base address */
  #define LP_FLEXCOMM6_BASE                        (0x50173000u)
  /** Peripheral LP_FLEXCOMM6 base address */
  #define LP_FLEXCOMM6_BASE_NS                     (0x40173000u)
  /** Peripheral LP_FLEXCOMM6 base pointer */
  #define LP_FLEXCOMM6                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE)
  /** Peripheral LP_FLEXCOMM6 base pointer */
  #define LP_FLEXCOMM6_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS)
  /** Peripheral LP_FLEXCOMM7 base address */
  #define LP_FLEXCOMM7_BASE                        (0x50174000u)
  /** Peripheral LP_FLEXCOMM7 base address */
  #define LP_FLEXCOMM7_BASE_NS                     (0x40174000u)
  /** Peripheral LP_FLEXCOMM7 base pointer */
  #define LP_FLEXCOMM7                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE)
  /** Peripheral LP_FLEXCOMM7 base pointer */
  #define LP_FLEXCOMM7_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS)
  /** Peripheral LP_FLEXCOMM8 base address */
  #define LP_FLEXCOMM8_BASE                        (0x50199000u)
  /** Peripheral LP_FLEXCOMM8 base address */
  #define LP_FLEXCOMM8_BASE_NS                     (0x40199000u)
  /** Peripheral LP_FLEXCOMM8 base pointer */
  #define LP_FLEXCOMM8                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE)
  /** Peripheral LP_FLEXCOMM8 base pointer */
  #define LP_FLEXCOMM8_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS)
  /** Peripheral LP_FLEXCOMM9 base address */
  #define LP_FLEXCOMM9_BASE                        (0x5019A000u)
  /** Peripheral LP_FLEXCOMM9 base address */
  #define LP_FLEXCOMM9_BASE_NS                     (0x4019A000u)
  /** Peripheral LP_FLEXCOMM9 base pointer */
  #define LP_FLEXCOMM9                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE)
  /** Peripheral LP_FLEXCOMM9 base pointer */
  #define LP_FLEXCOMM9_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS)
  /** Peripheral LP_FLEXCOMM10 base address */
  #define LP_FLEXCOMM10_BASE                       (0x5019B000u)
  /** Peripheral LP_FLEXCOMM10 base address */
  #define LP_FLEXCOMM10_BASE_NS                    (0x4019B000u)
  /** Peripheral LP_FLEXCOMM10 base pointer */
  #define LP_FLEXCOMM10                            ((LP_FLEXCOMM_Type *)LP_FLEXCOMM10_BASE)
  /** Peripheral LP_FLEXCOMM10 base pointer */
  #define LP_FLEXCOMM10_NS                         ((LP_FLEXCOMM_Type *)LP_FLEXCOMM10_BASE_NS)
  /** Peripheral LP_FLEXCOMM11 base address */
  #define LP_FLEXCOMM11_BASE                       (0x5019C000u)
  /** Peripheral LP_FLEXCOMM11 base address */
  #define LP_FLEXCOMM11_BASE_NS                    (0x4019C000u)
  /** Peripheral LP_FLEXCOMM11 base pointer */
  #define LP_FLEXCOMM11                            ((LP_FLEXCOMM_Type *)LP_FLEXCOMM11_BASE)
  /** Peripheral LP_FLEXCOMM11 base pointer */
  #define LP_FLEXCOMM11_NS                         ((LP_FLEXCOMM_Type *)LP_FLEXCOMM11_BASE_NS)
  /** Peripheral LP_FLEXCOMM12 base address */
  #define LP_FLEXCOMM12_BASE                       (0x5019D000u)
  /** Peripheral LP_FLEXCOMM12 base address */
  #define LP_FLEXCOMM12_BASE_NS                    (0x4019D000u)
  /** Peripheral LP_FLEXCOMM12 base pointer */
  #define LP_FLEXCOMM12                            ((LP_FLEXCOMM_Type *)LP_FLEXCOMM12_BASE)
  /** Peripheral LP_FLEXCOMM12 base pointer */
  #define LP_FLEXCOMM12_NS                         ((LP_FLEXCOMM_Type *)LP_FLEXCOMM12_BASE_NS)
  /** Peripheral LP_FLEXCOMM13 base address */
  #define LP_FLEXCOMM13_BASE                       (0x5019E000u)
  /** Peripheral LP_FLEXCOMM13 base address */
  #define LP_FLEXCOMM13_BASE_NS                    (0x4019E000u)
  /** Peripheral LP_FLEXCOMM13 base pointer */
  #define LP_FLEXCOMM13                            ((LP_FLEXCOMM_Type *)LP_FLEXCOMM13_BASE)
  /** Peripheral LP_FLEXCOMM13 base pointer */
  #define LP_FLEXCOMM13_NS                         ((LP_FLEXCOMM_Type *)LP_FLEXCOMM13_BASE_NS)
  /** Array initializer of LP_FLEXCOMM peripheral base addresses */
  #define LP_FLEXCOMM_BASE_ADDRS                   { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE, LP_FLEXCOMM10_BASE, LP_FLEXCOMM11_BASE, LP_FLEXCOMM12_BASE, LP_FLEXCOMM13_BASE }
  /** Array initializer of LP_FLEXCOMM peripheral base pointers */
  #define LP_FLEXCOMM_BASE_PTRS                    { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9, LP_FLEXCOMM10, LP_FLEXCOMM11, LP_FLEXCOMM12, LP_FLEXCOMM13 }
  /** Array initializer of LP_FLEXCOMM peripheral base addresses */
  #define LP_FLEXCOMM_BASE_ADDRS_NS                { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS, LP_FLEXCOMM10_BASE_NS, LP_FLEXCOMM11_BASE_NS, LP_FLEXCOMM12_BASE_NS, LP_FLEXCOMM13_BASE_NS }
  /** Array initializer of LP_FLEXCOMM peripheral base pointers */
  #define LP_FLEXCOMM_BASE_PTRS_NS                 { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS, LP_FLEXCOMM10_NS, LP_FLEXCOMM11_NS, LP_FLEXCOMM12_NS, LP_FLEXCOMM13_NS }
#else
  /** Peripheral LP_FLEXCOMM0 base address */
  #define LP_FLEXCOMM0_BASE                        (0x40110000u)
  /** Peripheral LP_FLEXCOMM0 base pointer */
  #define LP_FLEXCOMM0                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE)
  /** Peripheral LP_FLEXCOMM1 base address */
  #define LP_FLEXCOMM1_BASE                        (0x40111000u)
  /** Peripheral LP_FLEXCOMM1 base pointer */
  #define LP_FLEXCOMM1                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE)
  /** Peripheral LP_FLEXCOMM2 base address */
  #define LP_FLEXCOMM2_BASE                        (0x40112000u)
  /** Peripheral LP_FLEXCOMM2 base pointer */
  #define LP_FLEXCOMM2                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE)
  /** Peripheral LP_FLEXCOMM3 base address */
  #define LP_FLEXCOMM3_BASE                        (0x40113000u)
  /** Peripheral LP_FLEXCOMM3 base pointer */
  #define LP_FLEXCOMM3                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE)
  /** Peripheral LP_FLEXCOMM4 base address */
  #define LP_FLEXCOMM4_BASE                        (0x40171000u)
  /** Peripheral LP_FLEXCOMM4 base pointer */
  #define LP_FLEXCOMM4                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE)
  /** Peripheral LP_FLEXCOMM5 base address */
  #define LP_FLEXCOMM5_BASE                        (0x40172000u)
  /** Peripheral LP_FLEXCOMM5 base pointer */
  #define LP_FLEXCOMM5                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE)
  /** Peripheral LP_FLEXCOMM6 base address */
  #define LP_FLEXCOMM6_BASE                        (0x40173000u)
  /** Peripheral LP_FLEXCOMM6 base pointer */
  #define LP_FLEXCOMM6                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE)
  /** Peripheral LP_FLEXCOMM7 base address */
  #define LP_FLEXCOMM7_BASE                        (0x40174000u)
  /** Peripheral LP_FLEXCOMM7 base pointer */
  #define LP_FLEXCOMM7                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE)
  /** Peripheral LP_FLEXCOMM8 base address */
  #define LP_FLEXCOMM8_BASE                        (0x40199000u)
  /** Peripheral LP_FLEXCOMM8 base pointer */
  #define LP_FLEXCOMM8                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE)
  /** Peripheral LP_FLEXCOMM9 base address */
  #define LP_FLEXCOMM9_BASE                        (0x4019A000u)
  /** Peripheral LP_FLEXCOMM9 base pointer */
  #define LP_FLEXCOMM9                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE)
  /** Peripheral LP_FLEXCOMM10 base address */
  #define LP_FLEXCOMM10_BASE                       (0x4019B000u)
  /** Peripheral LP_FLEXCOMM10 base pointer */
  #define LP_FLEXCOMM10                            ((LP_FLEXCOMM_Type *)LP_FLEXCOMM10_BASE)
  /** Peripheral LP_FLEXCOMM11 base address */
  #define LP_FLEXCOMM11_BASE                       (0x4019C000u)
  /** Peripheral LP_FLEXCOMM11 base pointer */
  #define LP_FLEXCOMM11                            ((LP_FLEXCOMM_Type *)LP_FLEXCOMM11_BASE)
  /** Peripheral LP_FLEXCOMM12 base address */
  #define LP_FLEXCOMM12_BASE                       (0x4019D000u)
  /** Peripheral LP_FLEXCOMM12 base pointer */
  #define LP_FLEXCOMM12                            ((LP_FLEXCOMM_Type *)LP_FLEXCOMM12_BASE)
  /** Peripheral LP_FLEXCOMM13 base address */
  #define LP_FLEXCOMM13_BASE                       (0x4019E000u)
  /** Peripheral LP_FLEXCOMM13 base pointer */
  #define LP_FLEXCOMM13                            ((LP_FLEXCOMM_Type *)LP_FLEXCOMM13_BASE)
  /** Array initializer of LP_FLEXCOMM peripheral base addresses */
  #define LP_FLEXCOMM_BASE_ADDRS                   { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE, LP_FLEXCOMM10_BASE, LP_FLEXCOMM11_BASE, LP_FLEXCOMM12_BASE, LP_FLEXCOMM13_BASE }
  /** Array initializer of LP_FLEXCOMM peripheral base pointers */
  #define LP_FLEXCOMM_BASE_PTRS                    { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9, LP_FLEXCOMM10, LP_FLEXCOMM11, LP_FLEXCOMM12, LP_FLEXCOMM13 }
#endif
/** Interrupt vectors for the LP_FLEXCOMM peripheral type */
#define LP_FLEXCOMM_IRQS                         { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn, LP_FLEXCOMM10_IRQn, LP_FLEXCOMM11_IRQn, LP_FLEXCOMM12_IRQn, LP_FLEXCOMM13_IRQn }

/*!
 * @}
 */ /* end of group LP_FLEXCOMM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MIPI_DSI_HOST Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer
 * @{
 */

/** MIPI_DSI_HOST - Register Layout Typedef */
typedef struct {
  __IO uint32_t CFG_NUM_LANES;                     /**< Configure Number of Lanes, offset: 0x0 */
  __IO uint32_t CFG_NONCONTINUOUS_CLK;             /**< Configure Non-continuous Clock, offset: 0x4 */
  __IO uint32_t CFG_T_PRE;                         /**< Configure Pre Clock Periods, offset: 0x8 */
  __IO uint32_t CFG_T_POST;                        /**< Configure Post Clock Periods, offset: 0xC */
  __IO uint32_t CFG_TX_GAP;                        /**< Configure Gap Clock Periods, offset: 0x10 */
  __IO uint32_t CFG_AUTOINSERT_EOTP;               /**< Configure Autoinsert EOTP, offset: 0x14 */
  __IO uint32_t CFG_EXTRA_CMDS_AFTER_EOTP;         /**< Configure Extra Commands after EOTP, offset: 0x18 */
  __IO uint32_t CFG_HTX_TO_COUNT;                  /**< Configure High Speed Tx Timeout Count, offset: 0x1C */
  __IO uint32_t CFG_LRX_H_TO_COUNT;                /**< Configure Low Power Rx Timeout Count, offset: 0x20 */
  __IO uint32_t CFG_BTA_H_TO_COUNT;                /**< Configure Bus Turn Around Timeout Count, offset: 0x24 */
  __IO uint32_t CFG_TWAKEUP;                       /**< Configure Twakeup, offset: 0x28 */
  __I  uint32_t CFG_STATUS_OUT;                    /**< Configure Status Out, offset: 0x2C */
  __I  uint32_t RX_ERROR_STATUS;                   /**< Receive Error Status, offset: 0x30 */
  __IO uint32_t ULPS_ENABLE;                       /**< ULPS Enable, offset: 0x34 */
  __I  uint32_t ULPS_ACTIVE;                       /**< ULPS Active, offset: 0x38 */
  __IO uint32_t HS_MODE_ENABLE;                    /**< High Speed Mode Enable, offset: 0x3C */
  __IO uint32_t HOST_TURNAROUND;                   /**< Host Turnaround, offset: 0x40 */
  __I  uint32_t PHY_DIRECTION;                     /**< PHY Direction, offset: 0x44 */
  __I  uint32_t PHY_RDY;                           /**< PHY Ready, offset: 0x48 */
       uint8_t RESERVED_0[180];
  __IO uint32_t CFG_DBI_PIXEL_PAYLOAD_SIZE;        /**< Pixel Payload Size, offset: 0x100 */
  __IO uint32_t CFG_DBI_PIXEL_FIFO_SEND_LEVEL;     /**< Configure DBI Pixel FIFO Send Level, offset: 0x104 */
  __IO uint32_t CFG_DBI_PIXEL_FORMAT;              /**< DBI Pixel Format, offset: 0x108 */
  __I  uint32_t DBI_UNDERRUN_ERR;                  /**< DBI Underrun Error, offset: 0x10C */
  __I  uint32_t DBI_OVERFLOW_ERR;                  /**< DBI Overflow Error, offset: 0x110 */
       uint8_t RESERVED_1[236];
  __IO uint32_t CFG_DPI_PIXEL_PAYLOAD_SIZE;        /**< Configure DPI Pixel Payload Size, offset: 0x200 */
  __IO uint32_t CFG_DPI_PIXEL_FIFO_SEND_LEVEL;     /**< Configure DPI Pixel FIFO Send Level, offset: 0x204 */
  __IO uint32_t CFG_DPI_INTERFACE_COLOR_CODING;    /**< Configure DPI Interface Color Coding, offset: 0x208 */
  __IO uint32_t CFG_DPI_PIXEL_FORMAT;              /**< Configure DPI Pixel Format, offset: 0x20C */
  __IO uint32_t CFG_DPI_VSYNC_POLARITY;            /**< Configure DPI vsync Polarity, offset: 0x210 */
  __IO uint32_t CFG_DPI_HSYNC_POLARITY;            /**< Configure DPI hsync Polarity, offset: 0x214 */
  __IO uint32_t CFG_DPI_VIDEO_MODE;                /**< Configure DPI Video Mode, offset: 0x218 */
  __IO uint32_t CFG_DPI_HFP;                       /**< Configure DPI horizontal front porch, offset: 0x21C */
  __IO uint32_t CFG_DPI_HBP;                       /**< Configure DPI Horizontal Back Porch, offset: 0x220 */
  __IO uint32_t CFG_DPI_HSA;                       /**< Configure DPI Horizontal Sync Width, offset: 0x224 */
  __IO uint32_t CFG_DPI_ENABLE_MULT_PKTS;          /**< Enable Multiple Packets, offset: 0x228 */
  __IO uint32_t CFG_DPI_VBP;                       /**< Configure DPI Vertical Back Porch, offset: 0x22C */
  __IO uint32_t CFG_DPI_VFP;                       /**< Configure DPI Vertical Front Porch, offset: 0x230 */
  __IO uint32_t CFG_DPI_BLLP_MODE;                 /**< Configure DPI BLLP Mode, offset: 0x234 */
  __IO uint32_t CFG_DPI_USE_NULL_PKT_BLLP;         /**< Configure DPI Blank Packet in BLLP, offset: 0x238 */
  __IO uint32_t CFG_DPI_VACTIVE;                   /**< Configure DPI Vertical Active, offset: 0x23C */
  __IO uint32_t CFG_DPI_VC;                        /**< Configure DPI Virtual Channel, offset: 0x240 */
  __I  uint32_t DPI_UNDERRUN_ERR;                  /**< DPI Underrun Error, offset: 0x244 */
       uint8_t RESERVED_2[56];
  __IO uint32_t TX_PAYLOAD;                        /**< Transmit Payload, offset: 0x280 */
  __IO uint32_t PKT_CONTROL;                       /**< Packet Control, offset: 0x284 */
  __IO uint32_t SEND_PACKET;                       /**< Send Packet, offset: 0x288 */
  __I  uint32_t PKT_STATUS;                        /**< Packet Status, offset: 0x28C */
  __I  uint32_t PKT_FIFO_WR_LEVEL;                 /**< Packet FIFO Write, offset: 0x290 */
  __I  uint32_t PKT_FIFO_RD_LEVEL;                 /**< Packet FIFO Read, offset: 0x294 */
  __I  uint32_t PKT_RX_PAYLOAD;                    /**< Packet Rx Payload, offset: 0x298 */
  __I  uint32_t PKT_RX_PKT_HEADER;                 /**< Packet Rx Packet Header, offset: 0x29C */
  __I  uint32_t IRQ_STATUS;                        /**< Interrupt Status, offset: 0x2A0 */
  __I  uint32_t IRQ_STATUS2;                       /**< Interrupt Status 2, offset: 0x2A4 */
  __IO uint32_t IRQ_MASK;                          /**< Mask Interrupt, offset: 0x2A8 */
  __IO uint32_t IRQ_MASK2;                         /**< Interrupt Mask 2, offset: 0x2AC */
       uint8_t RESERVED_3[80];
  __IO uint32_t PD_DPHY;                           /**< DPHY Power Down, offset: 0x300 */
  __IO uint32_t M_PRG_HS_PREPARE;                  /**< Program T_HS_PREPARE, offset: 0x304 */
  __IO uint32_t MC_PRG_HS_PREPARE;                 /**< Program HS T_CLK_PREPARE, offset: 0x308 */
  __IO uint32_t M_PRG_HS_ZERO;                     /**< Program T_HS_ZERO, offset: 0x30C */
  __IO uint32_t MC_PRG_HS_ZERO;                    /**< Program T_CLK_ZERO, offset: 0x310 */
  __IO uint32_t M_PRG_HS_TRAIL;                    /**< Program T_HS_TRAIL, offset: 0x314 */
  __IO uint32_t MC_PRG_HS_TRAIL;                   /**< Program T_CLK_TRAIL, offset: 0x318 */
  __IO uint32_t TST;                               /**< DPHY TST Input, offset: 0x31C */
  __IO uint32_t RTERM_SEL;                         /**< RTERM Select, offset: 0x320 */
  __IO uint32_t AUTO_PD_EN;                        /**< Power Down Auto Enable, offset: 0x324 */
  __IO uint32_t RXLPRP;                            /**< DPHY RXLPRP Input, offset: 0x328 */
  __IO uint32_t RXCDRP;                            /**< DPHY RXCDRP Input, offset: 0x32C */
} MIPI_DSI_HOST_Type;

/* ----------------------------------------------------------------------------
   -- MIPI_DSI_HOST Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks
 * @{
 */

/*! @name CFG_NUM_LANES - Configure Number of Lanes */
/*! @{ */

#define MIPI_DSI_HOST_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U)
#define MIPI_DSI_HOST_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U)
/*! CFG_NUM_LANES - Configure Number of Lanes
 *  0b00..1 Lane
 *  0b01..2 Lanes
 *  0b10..3 Lanes
 *  0b11..4 Lanes
 */
#define MIPI_DSI_HOST_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_DSI_HOST_CFG_NUM_LANES_CFG_NUM_LANES_MASK)
/*! @} */

/*! @name CFG_NONCONTINUOUS_CLK - Configure Non-continuous Clock */
/*! @{ */

#define MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CFG_NONCONTINUOUS_CLK_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CFG_NONCONTINUOUS_CLK_SHIFT (0U)
/*! CFG_NONCONTINUOUS_CLK - Configure Non-continuous Clock
 *  0b0..Continuous high speed clock
 *  0b1..Non-Continuous high speed clock
 */
#define MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CFG_NONCONTINUOUS_CLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CFG_NONCONTINUOUS_CLK_SHIFT)) & MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CFG_NONCONTINUOUS_CLK_MASK)
/*! @} */

/*! @name CFG_T_PRE - Configure Pre Clock Periods */
/*! @{ */

#define MIPI_DSI_HOST_CFG_T_PRE_CFG_T_PRE_MASK   (0xFFU)
#define MIPI_DSI_HOST_CFG_T_PRE_CFG_T_PRE_SHIFT  (0U)
/*! CFG_T_PRE - Configure Pre Clock Periods */
#define MIPI_DSI_HOST_CFG_T_PRE_CFG_T_PRE(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_T_PRE_CFG_T_PRE_SHIFT)) & MIPI_DSI_HOST_CFG_T_PRE_CFG_T_PRE_MASK)
/*! @} */

/*! @name CFG_T_POST - Configure Post Clock Periods */
/*! @{ */

#define MIPI_DSI_HOST_CFG_T_POST_CFG_T_POST_MASK (0xFFU)
#define MIPI_DSI_HOST_CFG_T_POST_CFG_T_POST_SHIFT (0U)
/*! CFG_T_POST - Configure Post Clock Periods */
#define MIPI_DSI_HOST_CFG_T_POST_CFG_T_POST(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_T_POST_CFG_T_POST_SHIFT)) & MIPI_DSI_HOST_CFG_T_POST_CFG_T_POST_MASK)
/*! @} */

/*! @name CFG_TX_GAP - Configure Gap Clock Periods */
/*! @{ */

#define MIPI_DSI_HOST_CFG_TX_GAP_CFG_TX_GAP_MASK (0xFFU)
#define MIPI_DSI_HOST_CFG_TX_GAP_CFG_TX_GAP_SHIFT (0U)
/*! CFG_TX_GAP - Configure Gap Clock Periods */
#define MIPI_DSI_HOST_CFG_TX_GAP_CFG_TX_GAP(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_TX_GAP_CFG_TX_GAP_SHIFT)) & MIPI_DSI_HOST_CFG_TX_GAP_CFG_TX_GAP_MASK)
/*! @} */

/*! @name CFG_AUTOINSERT_EOTP - Configure Autoinsert EOTP */
/*! @{ */

#define MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_CFG_AUTOINSERT_EOTP_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_CFG_AUTOINSERT_EOTP_SHIFT (0U)
/*! CFG_AUTOINSERT_EOTP - Configure Autoinsert EOTP
 *  0b0..EOTP is not automatically inserted
 *  0b1..EOTP is automatically inserted
 */
#define MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_CFG_AUTOINSERT_EOTP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_CFG_AUTOINSERT_EOTP_SHIFT)) & MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_CFG_AUTOINSERT_EOTP_MASK)
/*! @} */

/*! @name CFG_EXTRA_CMDS_AFTER_EOTP - Configure Extra Commands after EOTP */
/*! @{ */

#define MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_CFG_EXTRA_CMDS_AFTER_EOTP_MASK (0xFFU)
#define MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_CFG_EXTRA_CMDS_AFTER_EOTP_SHIFT (0U)
/*! CFG_EXTRA_CMDS_AFTER_EOTP - Configure Extra Commands after EOTP */
#define MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_CFG_EXTRA_CMDS_AFTER_EOTP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_CFG_EXTRA_CMDS_AFTER_EOTP_SHIFT)) & MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_CFG_EXTRA_CMDS_AFTER_EOTP_MASK)
/*! @} */

/*! @name CFG_HTX_TO_COUNT - Configure High Speed Tx Timeout Count */
/*! @{ */

#define MIPI_DSI_HOST_CFG_HTX_TO_COUNT_CFG_HTX_TO_COUNT_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_CFG_HTX_TO_COUNT_CFG_HTX_TO_COUNT_SHIFT (0U)
/*! CFG_HTX_TO_COUNT - Configure High Speed Tx Timeout Count */
#define MIPI_DSI_HOST_CFG_HTX_TO_COUNT_CFG_HTX_TO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_HTX_TO_COUNT_CFG_HTX_TO_COUNT_SHIFT)) & MIPI_DSI_HOST_CFG_HTX_TO_COUNT_CFG_HTX_TO_COUNT_MASK)
/*! @} */

/*! @name CFG_LRX_H_TO_COUNT - Configure Low Power Rx Timeout Count */
/*! @{ */

#define MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_CFG_LRX_H_TO_COUNT_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_CFG_LRX_H_TO_COUNT_SHIFT (0U)
/*! CFG_LRX_H_TO_COUNT - Configure Low Power Rx Timeout Count */
#define MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_CFG_LRX_H_TO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_CFG_LRX_H_TO_COUNT_SHIFT)) & MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_CFG_LRX_H_TO_COUNT_MASK)
/*! @} */

/*! @name CFG_BTA_H_TO_COUNT - Configure Bus Turn Around Timeout Count */
/*! @{ */

#define MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_CFG_BTA_H_TO_COUNT_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_CFG_BTA_H_TO_COUNT_SHIFT (0U)
/*! CFG_BTA_H_TO_COUNT - Configure Bus Turn Around Timeout Count */
#define MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_CFG_BTA_H_TO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_CFG_BTA_H_TO_COUNT_SHIFT)) & MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_CFG_BTA_H_TO_COUNT_MASK)
/*! @} */

/*! @name CFG_TWAKEUP - Configure Twakeup */
/*! @{ */

#define MIPI_DSI_HOST_CFG_TWAKEUP_CFG_TWAKEUP_MASK (0x7FFFFU)
#define MIPI_DSI_HOST_CFG_TWAKEUP_CFG_TWAKEUP_SHIFT (0U)
/*! CFG_TWAKEUP - DPHY Twakeup Timing Parameter */
#define MIPI_DSI_HOST_CFG_TWAKEUP_CFG_TWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_TWAKEUP_CFG_TWAKEUP_SHIFT)) & MIPI_DSI_HOST_CFG_TWAKEUP_CFG_TWAKEUP_MASK)
/*! @} */

/*! @name CFG_STATUS_OUT - Configure Status Out */
/*! @{ */

#define MIPI_DSI_HOST_CFG_STATUS_OUT_CFG_STATUS_OUT_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_CFG_STATUS_OUT_CFG_STATUS_OUT_SHIFT (0U)
/*! CFG_STATUS_OUT - Configure Status Out */
#define MIPI_DSI_HOST_CFG_STATUS_OUT_CFG_STATUS_OUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_STATUS_OUT_CFG_STATUS_OUT_SHIFT)) & MIPI_DSI_HOST_CFG_STATUS_OUT_CFG_STATUS_OUT_MASK)
/*! @} */

/*! @name RX_ERROR_STATUS - Receive Error Status */
/*! @{ */

#define MIPI_DSI_HOST_RX_ERROR_STATUS_RX_ERROR_STATUS_MASK (0x7FFU)
#define MIPI_DSI_HOST_RX_ERROR_STATUS_RX_ERROR_STATUS_SHIFT (0U)
/*! RX_ERROR_STATUS - Receive Error Status */
#define MIPI_DSI_HOST_RX_ERROR_STATUS_RX_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_RX_ERROR_STATUS_RX_ERROR_STATUS_SHIFT)) & MIPI_DSI_HOST_RX_ERROR_STATUS_RX_ERROR_STATUS_MASK)
/*! @} */

/*! @name ULPS_ENABLE - ULPS Enable */
/*! @{ */

#define MIPI_DSI_HOST_ULPS_ENABLE_EN0_MASK       (0x1U)
#define MIPI_DSI_HOST_ULPS_ENABLE_EN0_SHIFT      (0U)
/*! EN0 - Enable Clock Lane
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define MIPI_DSI_HOST_ULPS_ENABLE_EN0(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ENABLE_EN0_SHIFT)) & MIPI_DSI_HOST_ULPS_ENABLE_EN0_MASK)

#define MIPI_DSI_HOST_ULPS_ENABLE_EN1_MASK       (0x2U)
#define MIPI_DSI_HOST_ULPS_ENABLE_EN1_SHIFT      (1U)
/*! EN1 - Enable Data Lane 0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define MIPI_DSI_HOST_ULPS_ENABLE_EN1(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ENABLE_EN1_SHIFT)) & MIPI_DSI_HOST_ULPS_ENABLE_EN1_MASK)

#define MIPI_DSI_HOST_ULPS_ENABLE_EN2_MASK       (0x4U)
#define MIPI_DSI_HOST_ULPS_ENABLE_EN2_SHIFT      (2U)
/*! EN2 - Enable Data Lane 1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define MIPI_DSI_HOST_ULPS_ENABLE_EN2(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ENABLE_EN2_SHIFT)) & MIPI_DSI_HOST_ULPS_ENABLE_EN2_MASK)

#define MIPI_DSI_HOST_ULPS_ENABLE_EN3_MASK       (0x8U)
#define MIPI_DSI_HOST_ULPS_ENABLE_EN3_SHIFT      (3U)
/*! EN3 - Enable Data Lane 2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define MIPI_DSI_HOST_ULPS_ENABLE_EN3(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ENABLE_EN3_SHIFT)) & MIPI_DSI_HOST_ULPS_ENABLE_EN3_MASK)

#define MIPI_DSI_HOST_ULPS_ENABLE_EN4_MASK       (0x10U)
#define MIPI_DSI_HOST_ULPS_ENABLE_EN4_SHIFT      (4U)
/*! EN4 - Enable Data Lane 3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define MIPI_DSI_HOST_ULPS_ENABLE_EN4(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ENABLE_EN4_SHIFT)) & MIPI_DSI_HOST_ULPS_ENABLE_EN4_MASK)
/*! @} */

/*! @name ULPS_ACTIVE - ULPS Active */
/*! @{ */

#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE0_MASK   (0x1U)
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE0_SHIFT  (0U)
/*! ACTIVE0 - Clock Lane ULPS Active
 *  0b0..ULPS inactive
 *  0b1..ULPS active
 */
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE0(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE0_SHIFT)) & MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE0_MASK)

#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE1_MASK   (0x2U)
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE1_SHIFT  (1U)
/*! ACTIVE1 - Data Lane 0 ULPS ACTIVE
 *  0b0..ULPS inactive
 *  0b1..ULPS active
 */
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE1(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE1_SHIFT)) & MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE1_MASK)

#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE2_MASK   (0x4U)
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE2_SHIFT  (2U)
/*! ACTIVE2 - Data Lane 1 ULPS ACTIVE
 *  0b0..ULPS inactive
 *  0b1..ULPS active
 */
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE2(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE2_SHIFT)) & MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE2_MASK)

#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE3_MASK   (0x8U)
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE3_SHIFT  (3U)
/*! ACTIVE3 - Data Lane 2 ULPS ACTIVE
 *  0b0..ULPS inactive
 *  0b1..ULPS active
 */
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE3(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE3_SHIFT)) & MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE3_MASK)

#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE4_MASK   (0x10U)
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE4_SHIFT  (4U)
/*! ACTIVE4 - Data Lane 3 ULPS ACTIVE
 *  0b0..ULPS inactive
 *  0b1..ULPS active
 */
#define MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE4(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE4_SHIFT)) & MIPI_DSI_HOST_ULPS_ACTIVE_ACTIVE4_MASK)
/*! @} */

/*! @name HS_MODE_ENABLE - High Speed Mode Enable */
/*! @{ */

#define MIPI_DSI_HOST_HS_MODE_ENABLE_ENABLE_MASK (0x1U)
#define MIPI_DSI_HOST_HS_MODE_ENABLE_ENABLE_SHIFT (0U)
/*! ENABLE - Enable
 *  0b0..All transmissions in Low Power Data transmission mode.
 *  0b1..All transmissions in High Speed mode.
 */
#define MIPI_DSI_HOST_HS_MODE_ENABLE_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_HS_MODE_ENABLE_ENABLE_SHIFT)) & MIPI_DSI_HOST_HS_MODE_ENABLE_ENABLE_MASK)
/*! @} */

/*! @name HOST_TURNAROUND - Host Turnaround */
/*! @{ */

#define MIPI_DSI_HOST_HOST_TURNAROUND_REQUEST_BTA_MASK (0x1U)
#define MIPI_DSI_HOST_HOST_TURNAROUND_REQUEST_BTA_SHIFT (0U)
/*! REQUEST_BTA - Request BTA
 *  0b0..No Request
 *  0b1..Request BTA
 */
#define MIPI_DSI_HOST_HOST_TURNAROUND_REQUEST_BTA(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_HOST_TURNAROUND_REQUEST_BTA_SHIFT)) & MIPI_DSI_HOST_HOST_TURNAROUND_REQUEST_BTA_MASK)
/*! @} */

/*! @name PHY_DIRECTION - PHY Direction */
/*! @{ */

#define MIPI_DSI_HOST_PHY_DIRECTION_STATUS_MASK  (0x1U)
#define MIPI_DSI_HOST_PHY_DIRECTION_STATUS_SHIFT (0U)
/*! STATUS - PHY Direction
 *  0b0..Default PHY direction
 *  0b1..Reversed PHY direction
 */
#define MIPI_DSI_HOST_PHY_DIRECTION_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PHY_DIRECTION_STATUS_SHIFT)) & MIPI_DSI_HOST_PHY_DIRECTION_STATUS_MASK)
/*! @} */

/*! @name PHY_RDY - PHY Ready */
/*! @{ */

#define MIPI_DSI_HOST_PHY_RDY_STATUS_MASK        (0x1U)
#define MIPI_DSI_HOST_PHY_RDY_STATUS_SHIFT       (0U)
/*! STATUS - PHY Ready Status
 *  0b0..DPHY not ready
 *  0b1..DPHY ready
 */
#define MIPI_DSI_HOST_PHY_RDY_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PHY_RDY_STATUS_SHIFT)) & MIPI_DSI_HOST_PHY_RDY_STATUS_MASK)
/*! @} */

/*! @name CFG_DBI_PIXEL_PAYLOAD_SIZE - Pixel Payload Size */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_CFG_DBI_PIXEL_PAYLOAD_SIZE_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_CFG_DBI_PIXEL_PAYLOAD_SIZE_SHIFT (0U)
/*! CFG_DBI_PIXEL_PAYLOAD_SIZE - Pixel Payload Size */
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_CFG_DBI_PIXEL_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_CFG_DBI_PIXEL_PAYLOAD_SIZE_SHIFT)) & MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_CFG_DBI_PIXEL_PAYLOAD_SIZE_MASK)
/*! @} */

/*! @name CFG_DBI_PIXEL_FIFO_SEND_LEVEL - Configure DBI Pixel FIFO Send Level */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_SHIFT (0U)
/*! CFG_DBI_PIXEL_FIFO_SEND_LEVEL - Configure DBI Pixel FIFO Send Level */
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_CFG_DBI_PIXEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_SHIFT)) & MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_MASK)
/*! @} */

/*! @name CFG_DBI_PIXEL_FORMAT - DBI Pixel Format */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FORMAT_FORMAT_MASK (0x7U)
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FORMAT_FORMAT_SHIFT (0U)
/*! FORMAT - DBI Pixel Format Options
 *  0b000..Default. No pixel to byte mapping
 *  0b001..Option 1: RGB888
 *  0b010..Option 2: RGB666
 *  0b011..Option 3: RGB565
 *  0b100..Option 4: RGB444
 *  0b101..Option 5: RGB332
 *  0b110-0b111..
 */
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FORMAT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DBI_PIXEL_FORMAT_FORMAT_SHIFT)) & MIPI_DSI_HOST_CFG_DBI_PIXEL_FORMAT_FORMAT_MASK)
/*! @} */

/*! @name DBI_UNDERRUN_ERR - DBI Underrun Error */
/*! @{ */

#define MIPI_DSI_HOST_DBI_UNDERRUN_ERR_ERROR_MASK (0x1U)
#define MIPI_DSI_HOST_DBI_UNDERRUN_ERR_ERROR_SHIFT (0U)
/*! ERROR - Error
 *  0b0..No Error
 *  0b1..Error
 */
#define MIPI_DSI_HOST_DBI_UNDERRUN_ERR_ERROR(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DBI_UNDERRUN_ERR_ERROR_SHIFT)) & MIPI_DSI_HOST_DBI_UNDERRUN_ERR_ERROR_MASK)
/*! @} */

/*! @name DBI_OVERFLOW_ERR - DBI Overflow Error */
/*! @{ */

#define MIPI_DSI_HOST_DBI_OVERFLOW_ERR_ERROR_MASK (0x1U)
#define MIPI_DSI_HOST_DBI_OVERFLOW_ERR_ERROR_SHIFT (0U)
/*! ERROR - Error
 *  0b0..No Error
 *  0b1..Error
 */
#define MIPI_DSI_HOST_DBI_OVERFLOW_ERR_ERROR(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DBI_OVERFLOW_ERR_ERROR_SHIFT)) & MIPI_DSI_HOST_DBI_OVERFLOW_ERR_ERROR_MASK)
/*! @} */

/*! @name CFG_DPI_PIXEL_PAYLOAD_SIZE - Configure DPI Pixel Payload Size */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_CFG_DPI_PIXEL_PAYLOAD_SIZE_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_CFG_DPI_PIXEL_PAYLOAD_SIZE_SHIFT (0U)
/*! CFG_DPI_PIXEL_PAYLOAD_SIZE - Configure DPI Pixel Payload */
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_CFG_DPI_PIXEL_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_CFG_DPI_PIXEL_PAYLOAD_SIZE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_CFG_DPI_PIXEL_PAYLOAD_SIZE_MASK)
/*! @} */

/*! @name CFG_DPI_PIXEL_FIFO_SEND_LEVEL - Configure DPI Pixel FIFO Send Level */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_SHIFT (0U)
/*! CFG_DPI_PIXEL_FIFO_SEND_LEVEL - Configure DPI Pixel FIFO Send Level */
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_CFG_DPI_PIXEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_MASK)
/*! @} */

/*! @name CFG_DPI_INTERFACE_COLOR_CODING - Configure DPI Interface Color Coding */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_CFG_DPI_INTERFACE_COLOR_CODING_MASK (0x7U)
#define MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_CFG_DPI_INTERFACE_COLOR_CODING_SHIFT (0U)
/*! CFG_DPI_INTERFACE_COLOR_CODING - Configure DPI Interface Color Coding */
#define MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_CFG_DPI_INTERFACE_COLOR_CODING(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_CFG_DPI_INTERFACE_COLOR_CODING_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_CFG_DPI_INTERFACE_COLOR_CODING_MASK)
/*! @} */

/*! @name CFG_DPI_PIXEL_FORMAT - Configure DPI Pixel Format */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_CFG_DPI_PIXEL_FORMAT_MASK (0x3U)
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_CFG_DPI_PIXEL_FORMAT_SHIFT (0U)
/*! CFG_DPI_PIXEL_FORMAT - Configure DPI Pixel Format */
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_CFG_DPI_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_CFG_DPI_PIXEL_FORMAT_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_CFG_DPI_PIXEL_FORMAT_MASK)
/*! @} */

/*! @name CFG_DPI_VSYNC_POLARITY - Configure DPI vsync Polarity */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_CFG_DPI_VSYNC_POLARITY_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_CFG_DPI_VSYNC_POLARITY_SHIFT (0U)
/*! CFG_DPI_VSYNC_POLARITY - Configure DPI vsync Polarity */
#define MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_CFG_DPI_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_CFG_DPI_VSYNC_POLARITY_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_CFG_DPI_VSYNC_POLARITY_MASK)
/*! @} */

/*! @name CFG_DPI_HSYNC_POLARITY - Configure DPI hsync Polarity */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_CFG_DPI_HSYNC_POLARITY_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_CFG_DPI_HSYNC_POLARITY_SHIFT (0U)
/*! CFG_DPI_HSYNC_POLARITY - Configure DPI hsync Polarity */
#define MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_CFG_DPI_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_CFG_DPI_HSYNC_POLARITY_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_CFG_DPI_HSYNC_POLARITY_MASK)
/*! @} */

/*! @name CFG_DPI_VIDEO_MODE - Configure DPI Video Mode */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_CFG_DPI_VIDEO_MODE_MASK (0x3U)
#define MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_CFG_DPI_VIDEO_MODE_SHIFT (0U)
/*! CFG_DPI_VIDEO_MODE - Configure DPI Video Mode */
#define MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_CFG_DPI_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_CFG_DPI_VIDEO_MODE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_CFG_DPI_VIDEO_MODE_MASK)
/*! @} */

/*! @name CFG_DPI_HFP - Configure DPI horizontal front porch */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_HFP_CFG_DPI_HFP_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_HFP_CFG_DPI_HFP_SHIFT (0U)
/*! CFG_DPI_HFP - Configure DPI Horizontal Front Porch */
#define MIPI_DSI_HOST_CFG_DPI_HFP_CFG_DPI_HFP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_HFP_CFG_DPI_HFP_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_HFP_CFG_DPI_HFP_MASK)
/*! @} */

/*! @name CFG_DPI_HBP - Configure DPI Horizontal Back Porch */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_HBP_CFG_DPI_HBP_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_HBP_CFG_DPI_HBP_SHIFT (0U)
/*! CFG_DPI_HBP - Configure DPI Horizontal Back Porch */
#define MIPI_DSI_HOST_CFG_DPI_HBP_CFG_DPI_HBP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_HBP_CFG_DPI_HBP_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_HBP_CFG_DPI_HBP_MASK)
/*! @} */

/*! @name CFG_DPI_HSA - Configure DPI Horizontal Sync Width */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_HSA_CFG_DPI_HSA_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_HSA_CFG_DPI_HSA_SHIFT (0U)
/*! CFG_DPI_HSA - Configure DPI Horizontal Sync Width */
#define MIPI_DSI_HOST_CFG_DPI_HSA_CFG_DPI_HSA(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_HSA_CFG_DPI_HSA_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_HSA_CFG_DPI_HSA_MASK)
/*! @} */

/*! @name CFG_DPI_ENABLE_MULT_PKTS - Enable Multiple Packets */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_CFG_DPI_ENABLE_MULT_PKTS_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_CFG_DPI_ENABLE_MULT_PKTS_SHIFT (0U)
/*! CFG_DPI_ENABLE_MULT_PKTS - Enable Multiple Packets Per Video Line. */
#define MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_CFG_DPI_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_CFG_DPI_ENABLE_MULT_PKTS_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_CFG_DPI_ENABLE_MULT_PKTS_MASK)
/*! @} */

/*! @name CFG_DPI_VBP - Configure DPI Vertical Back Porch */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VBP_CFG_DPI_VBP_MASK (0xFFFU)
#define MIPI_DSI_HOST_CFG_DPI_VBP_CFG_DPI_VBP_SHIFT (0U)
/*! CFG_DPI_VBP - Configure DPI Vertical Back Porch */
#define MIPI_DSI_HOST_CFG_DPI_VBP_CFG_DPI_VBP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VBP_CFG_DPI_VBP_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VBP_CFG_DPI_VBP_MASK)
/*! @} */

/*! @name CFG_DPI_VFP - Configure DPI Vertical Front Porch */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VFP_CFG_DPI_VFP_MASK (0xFFFU)
#define MIPI_DSI_HOST_CFG_DPI_VFP_CFG_DPI_VFP_SHIFT (0U)
/*! CFG_DPI_VFP - Configure DPI VPP */
#define MIPI_DSI_HOST_CFG_DPI_VFP_CFG_DPI_VFP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VFP_CFG_DPI_VFP_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VFP_CFG_DPI_VFP_MASK)
/*! @} */

/*! @name CFG_DPI_BLLP_MODE - Configure DPI BLLP Mode */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_CFG_DPI_BLLP_MODE_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_CFG_DPI_BLLP_MODE_SHIFT (0U)
/*! CFG_DPI_BLLP_MODE - Configure DPI BLLP Mode */
#define MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_CFG_DPI_BLLP_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_CFG_DPI_BLLP_MODE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_CFG_DPI_BLLP_MODE_MASK)
/*! @} */

/*! @name CFG_DPI_USE_NULL_PKT_BLLP - Configure DPI Blank Packet in BLLP */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_CFG_DPI_USE_NULL_PKT_BLLP_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_CFG_DPI_USE_NULL_PKT_BLLP_SHIFT (0U)
/*! CFG_DPI_USE_NULL_PKT_BLLP - Configure DPI Blank Packet in BLLP */
#define MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_CFG_DPI_USE_NULL_PKT_BLLP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_CFG_DPI_USE_NULL_PKT_BLLP_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_CFG_DPI_USE_NULL_PKT_BLLP_MASK)
/*! @} */

/*! @name CFG_DPI_VACTIVE - Configure DPI Vertical Active */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VACTIVE_CFG_DPI_VACTIVE_MASK (0x3FFFU)
#define MIPI_DSI_HOST_CFG_DPI_VACTIVE_CFG_DPI_VACTIVE_SHIFT (0U)
/*! CFG_DPI_VACTIVE - Configure DPI Vertical Active */
#define MIPI_DSI_HOST_CFG_DPI_VACTIVE_CFG_DPI_VACTIVE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VACTIVE_CFG_DPI_VACTIVE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VACTIVE_CFG_DPI_VACTIVE_MASK)
/*! @} */

/*! @name CFG_DPI_VC - Configure DPI Virtual Channel */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VC_CFG_DPI_VC_MASK (0x3U)
#define MIPI_DSI_HOST_CFG_DPI_VC_CFG_DPI_VC_SHIFT (0U)
/*! CFG_DPI_VC - Configure DPI Virtual Channel */
#define MIPI_DSI_HOST_CFG_DPI_VC_CFG_DPI_VC(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VC_CFG_DPI_VC_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VC_CFG_DPI_VC_MASK)
/*! @} */

/*! @name DPI_UNDERRUN_ERR - DPI Underrun Error */
/*! @{ */

#define MIPI_DSI_HOST_DPI_UNDERRUN_ERR_ERR_MASK  (0x1U)
#define MIPI_DSI_HOST_DPI_UNDERRUN_ERR_ERR_SHIFT (0U)
/*! ERR - Error detected
 *  0b0..No error
 *  0b1..Error
 */
#define MIPI_DSI_HOST_DPI_UNDERRUN_ERR_ERR(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_UNDERRUN_ERR_ERR_SHIFT)) & MIPI_DSI_HOST_DPI_UNDERRUN_ERR_ERR_MASK)
/*! @} */

/*! @name TX_PAYLOAD - Transmit Payload */
/*! @{ */

#define MIPI_DSI_HOST_TX_PAYLOAD_TX_PAYLOAD_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_TX_PAYLOAD_TX_PAYLOAD_SHIFT (0U)
/*! TX_PAYLOAD - Tx Payload Data Write */
#define MIPI_DSI_HOST_TX_PAYLOAD_TX_PAYLOAD(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_TX_PAYLOAD_TX_PAYLOAD_SHIFT)) & MIPI_DSI_HOST_TX_PAYLOAD_TX_PAYLOAD_MASK)
/*! @} */

/*! @name PKT_CONTROL - Packet Control */
/*! @{ */

#define MIPI_DSI_HOST_PKT_CONTROL_PKT_CONTROL_MASK (0x7FFFFFFU)
#define MIPI_DSI_HOST_PKT_CONTROL_PKT_CONTROL_SHIFT (0U)
/*! PKT_CONTROL - Tx Packet Control */
#define MIPI_DSI_HOST_PKT_CONTROL_PKT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_CONTROL_PKT_CONTROL_SHIFT)) & MIPI_DSI_HOST_PKT_CONTROL_PKT_CONTROL_MASK)
/*! @} */

/*! @name SEND_PACKET - Send Packet */
/*! @{ */

#define MIPI_DSI_HOST_SEND_PACKET_SEND_PACKET_MASK (0x1U)
#define MIPI_DSI_HOST_SEND_PACKET_SEND_PACKET_SHIFT (0U)
/*! SEND_PACKET - Send Packet */
#define MIPI_DSI_HOST_SEND_PACKET_SEND_PACKET(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_SEND_PACKET_SEND_PACKET_SHIFT)) & MIPI_DSI_HOST_SEND_PACKET_SEND_PACKET_MASK)
/*! @} */

/*! @name PKT_STATUS - Packet Status */
/*! @{ */

#define MIPI_DSI_HOST_PKT_STATUS_PKT_STATUS_MASK (0x1FFU)
#define MIPI_DSI_HOST_PKT_STATUS_PKT_STATUS_SHIFT (0U)
/*! PKT_STATUS - Packet Status */
#define MIPI_DSI_HOST_PKT_STATUS_PKT_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_STATUS_PKT_STATUS_SHIFT)) & MIPI_DSI_HOST_PKT_STATUS_PKT_STATUS_MASK)
/*! @} */

/*! @name PKT_FIFO_WR_LEVEL - Packet FIFO Write */
/*! @{ */

#define MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_PKT_FIFO_WR_LEVEL_MASK (0xFFFFU)
#define MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_PKT_FIFO_WR_LEVEL_SHIFT (0U)
/*! PKT_FIFO_WR_LEVEL - Packet FIFO Write Level */
#define MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_PKT_FIFO_WR_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_PKT_FIFO_WR_LEVEL_SHIFT)) & MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_PKT_FIFO_WR_LEVEL_MASK)
/*! @} */

/*! @name PKT_FIFO_RD_LEVEL - Packet FIFO Read */
/*! @{ */

#define MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_PKT_FIFO_RD_LEVEL_MASK (0xFFFFU)
#define MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_PKT_FIFO_RD_LEVEL_SHIFT (0U)
/*! PKT_FIFO_RD_LEVEL - Packet FIFO Read Level */
#define MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_PKT_FIFO_RD_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_PKT_FIFO_RD_LEVEL_SHIFT)) & MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_PKT_FIFO_RD_LEVEL_MASK)
/*! @} */

/*! @name PKT_RX_PAYLOAD - Packet Rx Payload */
/*! @{ */

#define MIPI_DSI_HOST_PKT_RX_PAYLOAD_PKT_RX_PAYLOAD_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_PKT_RX_PAYLOAD_PKT_RX_PAYLOAD_SHIFT (0U)
/*! PKT_RX_PAYLOAD - Packet Rx Payload */
#define MIPI_DSI_HOST_PKT_RX_PAYLOAD_PKT_RX_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_RX_PAYLOAD_PKT_RX_PAYLOAD_SHIFT)) & MIPI_DSI_HOST_PKT_RX_PAYLOAD_PKT_RX_PAYLOAD_MASK)
/*! @} */

/*! @name PKT_RX_PKT_HEADER - Packet Rx Packet Header */
/*! @{ */

#define MIPI_DSI_HOST_PKT_RX_PKT_HEADER_PKT_RX_PKT_HEADER_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_PKT_RX_PKT_HEADER_PKT_RX_PKT_HEADER_SHIFT (0U)
/*! PKT_RX_PKT_HEADER - Packet Rx Packet Header */
#define MIPI_DSI_HOST_PKT_RX_PKT_HEADER_PKT_RX_PKT_HEADER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_RX_PKT_HEADER_PKT_RX_PKT_HEADER_SHIFT)) & MIPI_DSI_HOST_PKT_RX_PKT_HEADER_PKT_RX_PKT_HEADER_MASK)
/*! @} */

/*! @name IRQ_STATUS - Interrupt Status */
/*! @{ */

#define MIPI_DSI_HOST_IRQ_STATUS_IRQ_STATUS_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_IRQ_STATUS_IRQ_STATUS_SHIFT (0U)
/*! IRQ_STATUS - Interrupt Status */
#define MIPI_DSI_HOST_IRQ_STATUS_IRQ_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_DSI_HOST_IRQ_STATUS_IRQ_STATUS_MASK)
/*! @} */

/*! @name IRQ_STATUS2 - Interrupt Status 2 */
/*! @{ */

#define MIPI_DSI_HOST_IRQ_STATUS2_IRQ_STATUS2_MASK (0x7U)
#define MIPI_DSI_HOST_IRQ_STATUS2_IRQ_STATUS2_SHIFT (0U)
/*! IRQ_STATUS2 - Interrupt Status 2 */
#define MIPI_DSI_HOST_IRQ_STATUS2_IRQ_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_IRQ_STATUS2_IRQ_STATUS2_SHIFT)) & MIPI_DSI_HOST_IRQ_STATUS2_IRQ_STATUS2_MASK)
/*! @} */

/*! @name IRQ_MASK - Mask Interrupt */
/*! @{ */

#define MIPI_DSI_HOST_IRQ_MASK_IRQ_MASK_MASK     (0xFFFFFFFFU)
#define MIPI_DSI_HOST_IRQ_MASK_IRQ_MASK_SHIFT    (0U)
/*! IRQ_MASK - Mask Interrupt */
#define MIPI_DSI_HOST_IRQ_MASK_IRQ_MASK(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_DSI_HOST_IRQ_MASK_IRQ_MASK_MASK)
/*! @} */

/*! @name IRQ_MASK2 - Interrupt Mask 2 */
/*! @{ */

#define MIPI_DSI_HOST_IRQ_MASK2_irq_mask2_MASK   (0x7U)
#define MIPI_DSI_HOST_IRQ_MASK2_irq_mask2_SHIFT  (0U)
/*! irq_mask2 - Interrupt Mask 2 */
#define MIPI_DSI_HOST_IRQ_MASK2_irq_mask2(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_IRQ_MASK2_irq_mask2_SHIFT)) & MIPI_DSI_HOST_IRQ_MASK2_irq_mask2_MASK)
/*! @} */

/*! @name PD_DPHY - DPHY Power Down */
/*! @{ */

#define MIPI_DSI_HOST_PD_DPHY_PD_DPHY_MASK       (0x1U)
#define MIPI_DSI_HOST_PD_DPHY_PD_DPHY_SHIFT      (0U)
/*! PD_DPHY - Power Down Input for D-PHY
 *  0b0..Power up
 *  0b1..Power down
 */
#define MIPI_DSI_HOST_PD_DPHY_PD_DPHY(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PD_DPHY_PD_DPHY_SHIFT)) & MIPI_DSI_HOST_PD_DPHY_PD_DPHY_MASK)
/*! @} */

/*! @name M_PRG_HS_PREPARE - Program T_HS_PREPARE */
/*! @{ */

#define MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U)
#define MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U)
/*! M_PRG_HS_PREPARE - DPHY m_PRG_HS_PREPARE Input */
#define MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK)
/*! @} */

/*! @name MC_PRG_HS_PREPARE - Program HS T_CLK_PREPARE */
/*! @{ */

#define MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U)
#define MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U)
/*! MC_PRG_HS_PREPARE - DPHY mc_PRG_HS_PREPARE input */
#define MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK)
/*! @} */

/*! @name M_PRG_HS_ZERO - Program T_HS_ZERO */
/*! @{ */

#define MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x1FU)
#define MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U)
/*! M_PRG_HS_ZERO - DPHY m_PRG_HS_ZERO Input */
#define MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK)
/*! @} */

/*! @name MC_PRG_HS_ZERO - Program T_CLK_ZERO */
/*! @{ */

#define MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x3FU)
#define MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U)
/*! MC_PRG_HS_ZERO - DPHY mc_PRG_HS_ZERO Input */
#define MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK)
/*! @} */

/*! @name M_PRG_HS_TRAIL - Program T_HS_TRAIL */
/*! @{ */

#define MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0xFU)
#define MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U)
/*! M_PRG_HS_TRAIL - DPHY m_PRG_HS_TRAIL Input */
#define MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK)
/*! @} */

/*! @name MC_PRG_HS_TRAIL - Program T_CLK_TRAIL */
/*! @{ */

#define MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0xFU)
#define MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U)
/*! MC_PRG_HS_TRAIL - DPHY mc_PRG_HS_TRAIL input */
#define MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK)
/*! @} */

/*! @name TST - DPHY TST Input */
/*! @{ */

#define MIPI_DSI_HOST_TST_TST_MASK               (0x3FU)
#define MIPI_DSI_HOST_TST_TST_SHIFT              (0U)
/*! TST - DPHY TST Input */
#define MIPI_DSI_HOST_TST_TST(x)                 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_TST_TST_SHIFT)) & MIPI_DSI_HOST_TST_TST_MASK)
/*! @} */

/*! @name RTERM_SEL - RTERM Select */
/*! @{ */

#define MIPI_DSI_HOST_RTERM_SEL_RTERM_SEL_MASK   (0x1U)
#define MIPI_DSI_HOST_RTERM_SEL_RTERM_SEL_SHIFT  (0U)
/*! RTERM_SEL - DPHY RTERM_SEL Input
 *  0b0..LPCD levels enables HS termination (VIL-CD).
 *  0b1..LPRX levels enables HS terminations (LP-VIL).
 */
#define MIPI_DSI_HOST_RTERM_SEL_RTERM_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_RTERM_SEL_RTERM_SEL_SHIFT)) & MIPI_DSI_HOST_RTERM_SEL_RTERM_SEL_MASK)
/*! @} */

/*! @name AUTO_PD_EN - Power Down Auto Enable */
/*! @{ */

#define MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U)
#define MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U)
/*! AUTO_PD_EN - Power Down Auto Enable Input
 *  0b0..Inactive lanes are powered up and driving LP11.
 *  0b1..Inactive lanes are powered down.
 */
#define MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN_MASK)
/*! @} */

/*! @name RXLPRP - DPHY RXLPRP Input */
/*! @{ */

#define MIPI_DSI_HOST_RXLPRP_RXLPRP_MASK         (0x3U)
#define MIPI_DSI_HOST_RXLPRP_RXLPRP_SHIFT        (0U)
/*! RXLPRP - DPHY RXLPRP Input */
#define MIPI_DSI_HOST_RXLPRP_RXLPRP(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_RXLPRP_RXLPRP_SHIFT)) & MIPI_DSI_HOST_RXLPRP_RXLPRP_MASK)
/*! @} */

/*! @name RXCDRP - DPHY RXCDRP Input */
/*! @{ */

#define MIPI_DSI_HOST_RXCDRP_RXCDRP_MASK         (0x3U)
#define MIPI_DSI_HOST_RXCDRP_RXCDRP_SHIFT        (0U)
/*! RXCDRP - DPHY RXCDRP Input */
#define MIPI_DSI_HOST_RXCDRP_RXCDRP(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_RXCDRP_RXCDRP_SHIFT)) & MIPI_DSI_HOST_RXCDRP_RXCDRP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MIPI_DSI_HOST_Register_Masks */


/* MIPI_DSI_HOST - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral MIPI_DSI_HOST base address */
  #define MIPI_DSI_HOST_BASE                       (0x50417000u)
  /** Peripheral MIPI_DSI_HOST base address */
  #define MIPI_DSI_HOST_BASE_NS                    (0x40417000u)
  /** Peripheral MIPI_DSI_HOST base pointer */
  #define MIPI_DSI_HOST                            ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE)
  /** Peripheral MIPI_DSI_HOST base pointer */
  #define MIPI_DSI_HOST_NS                         ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE_NS)
  /** Array initializer of MIPI_DSI_HOST peripheral base addresses */
  #define MIPI_DSI_HOST_BASE_ADDRS                 { MIPI_DSI_HOST_BASE }
  /** Array initializer of MIPI_DSI_HOST peripheral base pointers */
  #define MIPI_DSI_HOST_BASE_PTRS                  { MIPI_DSI_HOST }
  /** Array initializer of MIPI_DSI_HOST peripheral base addresses */
  #define MIPI_DSI_HOST_BASE_ADDRS_NS              { MIPI_DSI_HOST_BASE_NS }
  /** Array initializer of MIPI_DSI_HOST peripheral base pointers */
  #define MIPI_DSI_HOST_BASE_PTRS_NS               { MIPI_DSI_HOST_NS }
#else
  /** Peripheral MIPI_DSI_HOST base address */
  #define MIPI_DSI_HOST_BASE                       (0x40417000u)
  /** Peripheral MIPI_DSI_HOST base pointer */
  #define MIPI_DSI_HOST                            ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE)
  /** Array initializer of MIPI_DSI_HOST peripheral base addresses */
  #define MIPI_DSI_HOST_BASE_ADDRS                 { MIPI_DSI_HOST_BASE }
  /** Array initializer of MIPI_DSI_HOST peripheral base pointers */
  #define MIPI_DSI_HOST_BASE_PTRS                  { MIPI_DSI_HOST }
#endif

/*!
 * @}
 */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MMU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MMU_Peripheral_Access_Layer MMU Peripheral Access Layer
 * @{
 */

/** MMU - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< MMU Control, offset: 0x0 */
  __IO uint32_t STS;                               /**< MMU Status, offset: 0x4 */
  __IO uint32_t INTEN;                             /**< Interrupt Enable, offset: 0x8 */
  __IO uint32_t ADDR_RANGE;                        /**< Address Range, offset: 0xC */
  __I  uint32_t FAIL_INFO;                         /**< Fail Information, offset: 0x10 */
  __I  uint32_t FAIL_ADDR;                         /**< Fail Address, offset: 0x14 */
  __IO uint32_t LUT_WDATA;                         /**< LUT Write Data, offset: 0x18 */
  __I  uint32_t LUT_RDATA;                         /**< LUT Read Data, offset: 0x1C */
  __IO uint32_t WRITE_PTR;                         /**< Write Pointer, offset: 0x20 */
  __IO uint32_t READ_PTR;                          /**< Read Pointer, offset: 0x24 */
  __IO uint32_t READ_VFY;                          /**< Read Verify, offset: 0x28 */
} MMU_Type;

/* ----------------------------------------------------------------------------
   -- MMU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MMU_Register_Masks MMU Register Masks
 * @{
 */

/*! @name CTRL - MMU Control */
/*! @{ */

#define MMU_CTRL_SWRST_MASK                      (0x1U)
#define MMU_CTRL_SWRST_SHIFT                     (0U)
/*! SWRST - Software Reset
 *  0b0..No reset
 *  0b1..Reset MMU logic
 */
#define MMU_CTRL_SWRST(x)                        (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_SWRST_SHIFT)) & MMU_CTRL_SWRST_MASK)

#define MMU_CTRL_MMU_EN_MASK                     (0x2U)
#define MMU_CTRL_MMU_EN_SHIFT                    (1U)
/*! MMU_EN - MMU Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MMU_CTRL_MMU_EN(x)                       (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_MMU_EN_SHIFT)) & MMU_CTRL_MMU_EN_MASK)

#define MMU_CTRL_CLK_DIS_MASK                    (0x4U)
#define MMU_CTRL_CLK_DIS_SHIFT                   (2U)
/*! CLK_DIS - Clock Gate
 *  0b0..Enable
 *  0b1..Disable
 */
#define MMU_CTRL_CLK_DIS(x)                      (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_CLK_DIS_SHIFT)) & MMU_CTRL_CLK_DIS_MASK)

#define MMU_CTRL_LOCK_LUT_MASK                   (0x8U)
#define MMU_CTRL_LOCK_LUT_SHIFT                  (3U)
/*! LOCK_LUT - Lock LUT
 *  0b0..Unlock
 *  0b1..Lock
 */
#define MMU_CTRL_LOCK_LUT(x)                     (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_LOCK_LUT_SHIFT)) & MMU_CTRL_LOCK_LUT_MASK)

#define MMU_CTRL_INV_ADDR_MODE_MASK              (0x10U)
#define MMU_CTRL_INV_ADDR_MODE_SHIFT             (4U)
/*! INV_ADDR_MODE - Invalid Address Mode
 *  0b0..Respond with a transfer error
 *  0b1..Allow transfer
 */
#define MMU_CTRL_INV_ADDR_MODE(x)                (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)

#define MMU_CTRL_PAGE_MODE_MASK                  (0x20U)
#define MMU_CTRL_PAGE_MODE_SHIFT                 (5U)
/*! PAGE_MODE - Page Mode
 *  0b0..MMU takes LUT SRAM as 1 page for address remapping
 *  0b1..MMU takes LUT SRAM as 4 pages for address remapping
 */
#define MMU_CTRL_PAGE_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_PAGE_MODE_SHIFT)) & MMU_CTRL_PAGE_MODE_MASK)

#define MMU_CTRL_PAGE_SEL_MASK                   (0xC0U)
#define MMU_CTRL_PAGE_SEL_SHIFT                  (6U)
/*! PAGE_SEL - Page Select
 *  0b00..Uses LUT SRAM low 2 KB words for address remapping
 *  0b01..Uses LUT SRAM mid-low 2 KB words for address remapping
 *  0b10..Uses LUT SRAM mid-high 2 KB words for address remapping
 *  0b11..Uses LUT SRAM high 2 KB words for address remapping
 */
#define MMU_CTRL_PAGE_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_PAGE_SEL_SHIFT)) & MMU_CTRL_PAGE_SEL_MASK)

#define MMU_CTRL_UNIT_SIZE_MASK                  (0x700U)
#define MMU_CTRL_UNIT_SIZE_SHIFT                 (8U)
/*! UNIT_SIZE - Unit Size
 *  0b000..Not supported, must configure to other value
 *  0b001..8 KB
 *  0b010..16 KB
 *  0b011..32 KB
 *  0b100-0b111..64 KB
 */
#define MMU_CTRL_UNIT_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_UNIT_SIZE_SHIFT)) & MMU_CTRL_UNIT_SIZE_MASK)
/*! @} */

/*! @name STS - MMU Status */
/*! @{ */

#define MMU_STS_BUSY_MASK                        (0x1U)
#define MMU_STS_BUSY_SHIFT                       (0U)
/*! BUSY - Busy
 *  0b0..Not busy
 *  0b1..In initialization sequence, burst-write operation, or read-verify operation
 */
#define MMU_STS_BUSY(x)                          (((uint32_t)(((uint32_t)(x)) << MMU_STS_BUSY_SHIFT)) & MMU_STS_BUSY_MASK)

#define MMU_STS_LUT_INVALID_MASK                 (0x2U)
#define MMU_STS_LUT_INVALID_SHIFT                (1U)
/*! LUT_INVALID - LUT Invalid
 *  0b0..Valid
 *  0b1..Invalid
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MMU_STS_LUT_INVALID(x)                   (((uint32_t)(((uint32_t)(x)) << MMU_STS_LUT_INVALID_SHIFT)) & MMU_STS_LUT_INVALID_MASK)

#define MMU_STS_INVALID_ADDR_MASK                (0x4U)
#define MMU_STS_INVALID_ADDR_SHIFT               (2U)
/*! INVALID_ADDR - Invalid Address
 *  0b0..Within range
 *  0b1..Out of range
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MMU_STS_INVALID_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << MMU_STS_INVALID_ADDR_SHIFT)) & MMU_STS_INVALID_ADDR_MASK)

#define MMU_STS_PARITY_ERROR_MASK                (0x8U)
#define MMU_STS_PARITY_ERROR_SHIFT               (3U)
/*! PARITY_ERROR - Parity Error
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MMU_STS_PARITY_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << MMU_STS_PARITY_ERROR_SHIFT)) & MMU_STS_PARITY_ERROR_MASK)

#define MMU_STS_LOCK_ERROR_MASK                  (0x10U)
#define MMU_STS_LOCK_ERROR_SHIFT                 (4U)
/*! LOCK_ERROR - Lock Error
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MMU_STS_LOCK_ERROR(x)                    (((uint32_t)(((uint32_t)(x)) << MMU_STS_LOCK_ERROR_SHIFT)) & MMU_STS_LOCK_ERROR_MASK)

#define MMU_STS_IPS_READ_ERROR_MASK              (0x20U)
#define MMU_STS_IPS_READ_ERROR_SHIFT             (5U)
/*! IPS_READ_ERROR - IPS Read Error
 *  0b0..Not detected
 *  0b1..Detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MMU_STS_IPS_READ_ERROR(x)                (((uint32_t)(((uint32_t)(x)) << MMU_STS_IPS_READ_ERROR_SHIFT)) & MMU_STS_IPS_READ_ERROR_MASK)

#define MMU_STS_IPS_ERR_ADDR_MASK                (0x1FFF0000U)
#define MMU_STS_IPS_ERR_ADDR_SHIFT               (16U)
/*! IPS_ERR_ADDR - IPS Error Address */
#define MMU_STS_IPS_ERR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << MMU_STS_IPS_ERR_ADDR_SHIFT)) & MMU_STS_IPS_ERR_ADDR_MASK)
/*! @} */

/*! @name INTEN - Interrupt Enable */
/*! @{ */

#define MMU_INTEN_LUT_INVALID_EN_MASK            (0x2U)
#define MMU_INTEN_LUT_INVALID_EN_SHIFT           (1U)
/*! LUT_INVALID_EN - LUT Invalid Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MMU_INTEN_LUT_INVALID_EN(x)              (((uint32_t)(((uint32_t)(x)) << MMU_INTEN_LUT_INVALID_EN_SHIFT)) & MMU_INTEN_LUT_INVALID_EN_MASK)

#define MMU_INTEN_INVALID_ADDR_EN_MASK           (0x4U)
#define MMU_INTEN_INVALID_ADDR_EN_SHIFT          (2U)
/*! INVALID_ADDR_EN - Invalid Address Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MMU_INTEN_INVALID_ADDR_EN(x)             (((uint32_t)(((uint32_t)(x)) << MMU_INTEN_INVALID_ADDR_EN_SHIFT)) & MMU_INTEN_INVALID_ADDR_EN_MASK)

#define MMU_INTEN_PARITY_ERROR_EN_MASK           (0x8U)
#define MMU_INTEN_PARITY_ERROR_EN_SHIFT          (3U)
/*! PARITY_ERROR_EN - Parity Error Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MMU_INTEN_PARITY_ERROR_EN(x)             (((uint32_t)(((uint32_t)(x)) << MMU_INTEN_PARITY_ERROR_EN_SHIFT)) & MMU_INTEN_PARITY_ERROR_EN_MASK)

#define MMU_INTEN_LOCK_ERROR_EN_MASK             (0x10U)
#define MMU_INTEN_LOCK_ERROR_EN_SHIFT            (4U)
/*! LOCK_ERROR_EN - Lock Error Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MMU_INTEN_LOCK_ERROR_EN(x)               (((uint32_t)(((uint32_t)(x)) << MMU_INTEN_LOCK_ERROR_EN_SHIFT)) & MMU_INTEN_LOCK_ERROR_EN_MASK)

#define MMU_INTEN_IPS_READ_ERROR_EN_MASK         (0x20U)
#define MMU_INTEN_IPS_READ_ERROR_EN_SHIFT        (5U)
/*! IPS_READ_ERROR_EN - IPS Read Error Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MMU_INTEN_IPS_READ_ERROR_EN(x)           (((uint32_t)(((uint32_t)(x)) << MMU_INTEN_IPS_READ_ERROR_EN_SHIFT)) & MMU_INTEN_IPS_READ_ERROR_EN_MASK)
/*! @} */

/*! @name ADDR_RANGE - Address Range */
/*! @{ */

#define MMU_ADDR_RANGE_BASE_ADDR_MASK            (0xFFFFU)
#define MMU_ADDR_RANGE_BASE_ADDR_SHIFT           (0U)
/*! BASE_ADDR - Base Address */
#define MMU_ADDR_RANGE_BASE_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << MMU_ADDR_RANGE_BASE_ADDR_SHIFT)) & MMU_ADDR_RANGE_BASE_ADDR_MASK)

#define MMU_ADDR_RANGE_MAX_ADDR_MASK             (0xFFFF0000U)
#define MMU_ADDR_RANGE_MAX_ADDR_SHIFT            (16U)
/*! MAX_ADDR - Maximum Address */
#define MMU_ADDR_RANGE_MAX_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << MMU_ADDR_RANGE_MAX_ADDR_SHIFT)) & MMU_ADDR_RANGE_MAX_ADDR_MASK)
/*! @} */

/*! @name FAIL_INFO - Fail Information */
/*! @{ */

#define MMU_FAIL_INFO_MASTER_ID_MASK             (0xFFU)
#define MMU_FAIL_INFO_MASTER_ID_SHIFT            (0U)
/*! MASTER_ID - Initiator ID */
#define MMU_FAIL_INFO_MASTER_ID(x)               (((uint32_t)(((uint32_t)(x)) << MMU_FAIL_INFO_MASTER_ID_SHIFT)) & MMU_FAIL_INFO_MASTER_ID_MASK)

#define MMU_FAIL_INFO_PROT_MASK                  (0x7F00U)
#define MMU_FAIL_INFO_PROT_SHIFT                 (8U)
/*! PROT - Protection */
#define MMU_FAIL_INFO_PROT(x)                    (((uint32_t)(((uint32_t)(x)) << MMU_FAIL_INFO_PROT_SHIFT)) & MMU_FAIL_INFO_PROT_MASK)

#define MMU_FAIL_INFO_ACC_TYPE_MASK              (0x8000U)
#define MMU_FAIL_INFO_ACC_TYPE_SHIFT             (15U)
/*! ACC_TYPE - Access Type
 *  0b0..Read
 *  0b1..Write
 */
#define MMU_FAIL_INFO_ACC_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << MMU_FAIL_INFO_ACC_TYPE_SHIFT)) & MMU_FAIL_INFO_ACC_TYPE_MASK)

#define MMU_FAIL_INFO_ERR_TYPE_MASK              (0x70000U)
#define MMU_FAIL_INFO_ERR_TYPE_SHIFT             (16U)
/*! ERR_TYPE - Error Type
 *  0bxx1..LUT invalid error
 *  0bx1x..Invalid address error
 *  0b1xx..Parity error
 */
#define MMU_FAIL_INFO_ERR_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << MMU_FAIL_INFO_ERR_TYPE_SHIFT)) & MMU_FAIL_INFO_ERR_TYPE_MASK)
/*! @} */

/*! @name FAIL_ADDR - Fail Address */
/*! @{ */

#define MMU_FAIL_ADDR_ADDR_MASK                  (0xFFFFFFFFU)
#define MMU_FAIL_ADDR_ADDR_SHIFT                 (0U)
/*! ADDR - Address */
#define MMU_FAIL_ADDR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << MMU_FAIL_ADDR_ADDR_SHIFT)) & MMU_FAIL_ADDR_ADDR_MASK)
/*! @} */

/*! @name LUT_WDATA - LUT Write Data */
/*! @{ */

#define MMU_LUT_WDATA_ADDR_MASK                  (0x7FFFU)
#define MMU_LUT_WDATA_ADDR_SHIFT                 (0U)
/*! ADDR - LUT Address Map Bits */
#define MMU_LUT_WDATA_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << MMU_LUT_WDATA_ADDR_SHIFT)) & MMU_LUT_WDATA_ADDR_MASK)

#define MMU_LUT_WDATA_VALID_MASK                 (0x8000U)
#define MMU_LUT_WDATA_VALID_SHIFT                (15U)
/*! VALID - LUT Address Valid
 *  0b1..Valid
 *  0b0..Not valid
 */
#define MMU_LUT_WDATA_VALID(x)                   (((uint32_t)(((uint32_t)(x)) << MMU_LUT_WDATA_VALID_SHIFT)) & MMU_LUT_WDATA_VALID_MASK)

#define MMU_LUT_WDATA_COUNT_MASK                 (0x1FFF0000U)
#define MMU_LUT_WDATA_COUNT_SHIFT                (16U)
/*! COUNT - Write Count */
#define MMU_LUT_WDATA_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << MMU_LUT_WDATA_COUNT_SHIFT)) & MMU_LUT_WDATA_COUNT_MASK)
/*! @} */

/*! @name LUT_RDATA - LUT Read Data */
/*! @{ */

#define MMU_LUT_RDATA_DATA_MASK                  (0xFFFFU)
#define MMU_LUT_RDATA_DATA_SHIFT                 (0U)
/*! DATA - Read Data */
#define MMU_LUT_RDATA_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << MMU_LUT_RDATA_DATA_SHIFT)) & MMU_LUT_RDATA_DATA_MASK)
/*! @} */

/*! @name WRITE_PTR - Write Pointer */
/*! @{ */

#define MMU_WRITE_PTR_POINTER_MASK               (0x1FFFU)
#define MMU_WRITE_PTR_POINTER_SHIFT              (0U)
/*! POINTER - Write Pointer */
#define MMU_WRITE_PTR_POINTER(x)                 (((uint32_t)(((uint32_t)(x)) << MMU_WRITE_PTR_POINTER_SHIFT)) & MMU_WRITE_PTR_POINTER_MASK)
/*! @} */

/*! @name READ_PTR - Read Pointer */
/*! @{ */

#define MMU_READ_PTR_POINTER_MASK                (0x1FFFU)
#define MMU_READ_PTR_POINTER_SHIFT               (0U)
/*! POINTER - Read Pointer */
#define MMU_READ_PTR_POINTER(x)                  (((uint32_t)(((uint32_t)(x)) << MMU_READ_PTR_POINTER_SHIFT)) & MMU_READ_PTR_POINTER_MASK)
/*! @} */

/*! @name READ_VFY - Read Verify */
/*! @{ */

#define MMU_READ_VFY_DATA_MASK                   (0xFFFFU)
#define MMU_READ_VFY_DATA_SHIFT                  (0U)
/*! DATA - Read Data */
#define MMU_READ_VFY_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << MMU_READ_VFY_DATA_SHIFT)) & MMU_READ_VFY_DATA_MASK)

#define MMU_READ_VFY_COUNT_MASK                  (0x1FFF0000U)
#define MMU_READ_VFY_COUNT_SHIFT                 (16U)
/*! COUNT - Read Count */
#define MMU_READ_VFY_COUNT(x)                    (((uint32_t)(((uint32_t)(x)) << MMU_READ_VFY_COUNT_SHIFT)) & MMU_READ_VFY_COUNT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MMU_Register_Masks */


/* MMU - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral MMU0 base address */
  #define MMU0_BASE                                (0x50030000u)
  /** Peripheral MMU0 base address */
  #define MMU0_BASE_NS                             (0x40030000u)
  /** Peripheral MMU0 base pointer */
  #define MMU0                                     ((MMU_Type *)MMU0_BASE)
  /** Peripheral MMU0 base pointer */
  #define MMU0_NS                                  ((MMU_Type *)MMU0_BASE_NS)
  /** Peripheral MMU1 base address */
  #define MMU1_BASE                                (0x50031000u)
  /** Peripheral MMU1 base address */
  #define MMU1_BASE_NS                             (0x40031000u)
  /** Peripheral MMU1 base pointer */
  #define MMU1                                     ((MMU_Type *)MMU1_BASE)
  /** Peripheral MMU1 base pointer */
  #define MMU1_NS                                  ((MMU_Type *)MMU1_BASE_NS)
  /** Peripheral MMU2 base address */
  #define MMU2_BASE                                (0x500A8000u)
  /** Peripheral MMU2 base address */
  #define MMU2_BASE_NS                             (0x400A8000u)
  /** Peripheral MMU2 base pointer */
  #define MMU2                                     ((MMU_Type *)MMU2_BASE)
  /** Peripheral MMU2 base pointer */
  #define MMU2_NS                                  ((MMU_Type *)MMU2_BASE_NS)
  /** Array initializer of MMU peripheral base addresses */
  #define MMU_BASE_ADDRS                           { MMU0_BASE, MMU1_BASE, MMU2_BASE }
  /** Array initializer of MMU peripheral base pointers */
  #define MMU_BASE_PTRS                            { MMU0, MMU1, MMU2 }
  /** Array initializer of MMU peripheral base addresses */
  #define MMU_BASE_ADDRS_NS                        { MMU0_BASE_NS, MMU1_BASE_NS, MMU2_BASE_NS }
  /** Array initializer of MMU peripheral base pointers */
  #define MMU_BASE_PTRS_NS                         { MMU0_NS, MMU1_NS, MMU2_NS }
#else
  /** Peripheral MMU0 base address */
  #define MMU0_BASE                                (0x40030000u)
  /** Peripheral MMU0 base pointer */
  #define MMU0                                     ((MMU_Type *)MMU0_BASE)
  /** Peripheral MMU1 base address */
  #define MMU1_BASE                                (0x40031000u)
  /** Peripheral MMU1 base pointer */
  #define MMU1                                     ((MMU_Type *)MMU1_BASE)
  /** Peripheral MMU2 base address */
  #define MMU2_BASE                                (0x400A8000u)
  /** Peripheral MMU2 base pointer */
  #define MMU2                                     ((MMU_Type *)MMU2_BASE)
  /** Array initializer of MMU peripheral base addresses */
  #define MMU_BASE_ADDRS                           { MMU0_BASE, MMU1_BASE, MMU2_BASE }
  /** Array initializer of MMU peripheral base pointers */
  #define MMU_BASE_PTRS                            { MMU0, MMU1, MMU2 }
#endif

/*!
 * @}
 */ /* end of group MMU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MRT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
 * @{
 */

/** MRT - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x10 */
    __IO uint32_t INTVAL;                            /**< Time Interval Value, array offset: 0x0, array step: 0x10 */
    __I  uint32_t TIMER;                             /**< Timer, array offset: 0x4, array step: 0x10 */
    __IO uint32_t CTRL;                              /**< Control, array offset: 0x8, array step: 0x10 */
    __IO uint32_t STAT;                              /**< Status, array offset: 0xC, array step: 0x10 */
  } CHANNEL[4];
       uint8_t RESERVED_0[176];
  __IO uint32_t MODCFG;                            /**< Module Configuration, offset: 0xF0 */
  __I  uint32_t IDLE_CH;                           /**< Idle Channel, offset: 0xF4 */
  __IO uint32_t IRQ_FLAG;                          /**< Global Interrupt Flag, offset: 0xF8 */
} MRT_Type;

/* ----------------------------------------------------------------------------
   -- MRT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRT_Register_Masks MRT Register Masks
 * @{
 */

/*! @name CHANNEL_INTVAL - Time Interval Value */
/*! @{ */

#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
/*! IVALUE - Time Interval Load Value. */
#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)

#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
/*! LOAD - Force Load Enable
 *  0b0..No force load
 *  0b1..Force load
 */
#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
/*! @} */

/* The count of MRT_CHANNEL_INTVAL */
#define MRT_CHANNEL_INTVAL_COUNT                 (4U)

/*! @name CHANNEL_TIMER - Timer */
/*! @{ */

#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
/*! VALUE - Current Timer Value */
#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_TIMER */
#define MRT_CHANNEL_TIMER_COUNT                  (4U)

/*! @name CHANNEL_CTRL - Control */
/*! @{ */

#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
/*! INTEN - Interrupt request
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)

#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
/*! MODE - MRT Operating mode
 *  0b00..Repeat Interrupt mode
 *  0b01..One-Shot Interrupt mode
 *  0b10..One-Shot Stall mode
 *  0b11..Reserved
 */
#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_CTRL */
#define MRT_CHANNEL_CTRL_COUNT                   (4U)

/*! @name CHANNEL_STAT - Status */
/*! @{ */

#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
/*! INTFLAG - Interrupt Flag
 *  0b0..No pending interrupt.
 *  0b1..Pending interrupt.
 */
#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)

#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
/*! RUN - Timer n State
 *  0b0..Idle state.
 *  0b1..Running.
 */
#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)

#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
/*! INUSE - Channel-In-Use flag
 *  0b0..This timer channel is not in use.
 *  0b1..This timer channel is in use.
 */
#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_STAT */
#define MRT_CHANNEL_STAT_COUNT                   (4U)

/*! @name MODCFG - Module Configuration */
/*! @{ */

#define MRT_MODCFG_NOC_MASK                      (0xFU)
#define MRT_MODCFG_NOC_SHIFT                     (0U)
/*! NOC - Number of Channels */
#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)

#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
#define MRT_MODCFG_NOB_SHIFT                     (4U)
/*! NOB - Number of Bits */
#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)

#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
/*! MULTITASK - MULTITASK
 *  0b0..Hardware status mode.
 *  0b1..Multitask mode
 */
#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
/*! @} */

/*! @name IDLE_CH - Idle Channel */
/*! @{ */

#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
/*! CHAN - Idle Channel */
#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
/*! @} */

/*! @name IRQ_FLAG - Global Interrupt Flag */
/*! @{ */

#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
/*! GFLAG0 - Interrupt Flag
 *  0b0..No pending interrupt.
 *  0b1..Pending interrupt
 */
#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)

#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
/*! GFLAG1 - Interrupt Flag */
#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)

#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
/*! GFLAG2 - Interrupt Flag */
#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)

#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
/*! GFLAG3 - Interrupt Flag */
#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MRT_Register_Masks */


/* MRT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral MRT0 base address */
  #define MRT0_BASE                                (0x5002D000u)
  /** Peripheral MRT0 base address */
  #define MRT0_BASE_NS                             (0x4002D000u)
  /** Peripheral MRT0 base pointer */
  #define MRT0                                     ((MRT_Type *)MRT0_BASE)
  /** Peripheral MRT0 base pointer */
  #define MRT0_NS                                  ((MRT_Type *)MRT0_BASE_NS)
  /** Array initializer of MRT peripheral base addresses */
  #define MRT_BASE_ADDRS                           { MRT0_BASE }
  /** Array initializer of MRT peripheral base pointers */
  #define MRT_BASE_PTRS                            { MRT0 }
  /** Array initializer of MRT peripheral base addresses */
  #define MRT_BASE_ADDRS_NS                        { MRT0_BASE_NS }
  /** Array initializer of MRT peripheral base pointers */
  #define MRT_BASE_PTRS_NS                         { MRT0_NS }
#else
  /** Peripheral MRT0 base address */
  #define MRT0_BASE                                (0x4002D000u)
  /** Peripheral MRT0 base pointer */
  #define MRT0                                     ((MRT_Type *)MRT0_BASE)
  /** Array initializer of MRT peripheral base addresses */
  #define MRT_BASE_ADDRS                           { MRT0_BASE }
  /** Array initializer of MRT peripheral base pointers */
  #define MRT_BASE_PTRS                            { MRT0 }
#endif
/** Interrupt vectors for the MRT peripheral type */
#define MRT_IRQS                                 { MRT0_IRQn }

/*!
 * @}
 */ /* end of group MRT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
 * @{
 */

/** MU - Register Layout Typedef */
typedef struct {
  __I  uint32_t VER;                               /**< Version ID, offset: 0x0 */
  __I  uint32_t PAR;                               /**< Parameter, offset: 0x4 */
  __IO uint32_t CR;                                /**< Control, offset: 0x8 */
  __I  uint32_t SR;                                /**< Status, offset: 0xC */
  __IO uint32_t CCR0;                              /**< Core Control 0, offset: 0x10 */
  __IO uint32_t CIER0;                             /**< Core Interrupt Enable 0, offset: 0x14 */
  __IO uint32_t CSSR0;                             /**< Core Sticky Status 0, offset: 0x18 */
  __I  uint32_t CSR0;                              /**< Core Status 0, offset: 0x1C */
       uint8_t RESERVED_0[224];
  __IO uint32_t FCR;                               /**< Flag Control, offset: 0x100 */
  __I  uint32_t FSR;                               /**< Flag Status, offset: 0x104 */
       uint8_t RESERVED_1[8];
  __IO uint32_t GIER;                              /**< General-Purpose Interrupt Enable, offset: 0x110 */
  __IO uint32_t GCR;                               /**< General-Purpose Control, offset: 0x114 */
  __IO uint32_t GSR;                               /**< General-purpose Status, offset: 0x118 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TCR;                               /**< Transmit Control, offset: 0x120 */
  __I  uint32_t TSR;                               /**< Transmit Status, offset: 0x124 */
  __IO uint32_t RCR;                               /**< Receive Control, offset: 0x128 */
  __I  uint32_t RSR;                               /**< Receive Status, offset: 0x12C */
       uint8_t RESERVED_3[208];
  __O  uint32_t TR[4];                             /**< Transmit, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_4[112];
  __I  uint32_t RR[4];                             /**< Receive, array offset: 0x280, array step: 0x4 */
} MU_Type;

/* ----------------------------------------------------------------------------
   -- MU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MU_Register_Masks MU Register Masks
 * @{
 */

/*! @name VER - Version ID */
/*! @{ */

#define MU_VER_FEATURE_MASK                      (0xFFFFU)
#define MU_VER_FEATURE_SHIFT                     (0U)
/*! FEATURE - Feature Set Number */
#define MU_VER_FEATURE(x)                        (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK)

#define MU_VER_MINOR_MASK                        (0xFF0000U)
#define MU_VER_MINOR_SHIFT                       (16U)
/*! MINOR - Minor Version Number */
#define MU_VER_MINOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK)

#define MU_VER_MAJOR_MASK                        (0xFF000000U)
#define MU_VER_MAJOR_SHIFT                       (24U)
/*! MAJOR - Major Version Number */
#define MU_VER_MAJOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK)
/*! @} */

/*! @name PAR - Parameter */
/*! @{ */

#define MU_PAR_TR_NUM_MASK                       (0xFFU)
#define MU_PAR_TR_NUM_SHIFT                      (0U)
/*! TR_NUM - Transmit Register Number */
#define MU_PAR_TR_NUM(x)                         (((uint32_t)(((uint32_t)(x)) << MU_PAR_TR_NUM_SHIFT)) & MU_PAR_TR_NUM_MASK)

#define MU_PAR_RR_NUM_MASK                       (0xFF00U)
#define MU_PAR_RR_NUM_SHIFT                      (8U)
/*! RR_NUM - Receive Register Number */
#define MU_PAR_RR_NUM(x)                         (((uint32_t)(((uint32_t)(x)) << MU_PAR_RR_NUM_SHIFT)) & MU_PAR_RR_NUM_MASK)

#define MU_PAR_GIR_NUM_MASK                      (0xFF0000U)
#define MU_PAR_GIR_NUM_SHIFT                     (16U)
/*! GIR_NUM - General-Purpose Interrupt Request Number */
#define MU_PAR_GIR_NUM(x)                        (((uint32_t)(((uint32_t)(x)) << MU_PAR_GIR_NUM_SHIFT)) & MU_PAR_GIR_NUM_MASK)

#define MU_PAR_FLAG_WIDTH_MASK                   (0xFF000000U)
#define MU_PAR_FLAG_WIDTH_SHIFT                  (24U)
/*! FLAG_WIDTH - Flag Width */
#define MU_PAR_FLAG_WIDTH(x)                     (((uint32_t)(((uint32_t)(x)) << MU_PAR_FLAG_WIDTH_SHIFT)) & MU_PAR_FLAG_WIDTH_MASK)
/*! @} */

/*! @name CR - Control */
/*! @{ */

#define MU_CR_MUR_MASK                           (0x1U)
#define MU_CR_MUR_SHIFT                          (0U)
/*! MUR - MU Reset
 *  0b0..Idle
 *  0b1..Reset
 */
#define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/*! @} */

/*! @name SR - Status */
/*! @{ */

#define MU_SR_MURS_MASK                          (0x1U)
#define MU_SR_MURS_SHIFT                         (0U)
/*! MURS - MUA and MUB Reset State
 *  0b0..Out of reset
 *  0b1..In reset
 */
#define MU_SR_MURS(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_MURS_SHIFT)) & MU_SR_MURS_MASK)

#define MU_SR_EP_MASK                            (0x4U)
#define MU_SR_EP_SHIFT                           (2U)
/*! EP - MUB Side Event Pending
 *  0b0..Not pending
 *  0b1..Pending
 */
#define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)

#define MU_SR_FUP_MASK                           (0x8U)
#define MU_SR_FUP_SHIFT                          (3U)
/*! FUP - MUB Flag Update Pending
 *  0b0..No pending update flags (initiated by MUA)
 *  0b1..Pending update flags (initiated by MUA)
 */
#define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)

#define MU_SR_GIRP_MASK                          (0x10U)
#define MU_SR_GIRP_SHIFT                         (4U)
/*! GIRP - MUB General-Purpose Interrupt Pending
 *  0b0..No request sent
 *  0b1..Request sent
 */
#define MU_SR_GIRP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIRP_SHIFT)) & MU_SR_GIRP_MASK)

#define MU_SR_TEP_MASK                           (0x20U)
#define MU_SR_TEP_SHIFT                          (5U)
/*! TEP - MUB Transmit Empty Pending
 *  0b0..Not pending; MUA is reading no Receive (RRn) register
 *  0b1..Pending; MUA is reading a Receive (RRn) register
 */
#define MU_SR_TEP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEP_SHIFT)) & MU_SR_TEP_MASK)

#define MU_SR_RFP_MASK                           (0x40U)
#define MU_SR_RFP_SHIFT                          (6U)
/*! RFP - MUB Receive Full Pending
 *  0b0..Not pending; MUA is not writing to a Transmit register
 *  0b1..Pending; MUA is writing to a Transmit register
 */
#define MU_SR_RFP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFP_SHIFT)) & MU_SR_RFP_MASK)

#define MU_SR_CEP_MASK                           (0x80U)
#define MU_SR_CEP_SHIFT                          (7U)
/*! CEP - Processor B Event Pending
 *  0b0..No event pending
 *  0b1..Event pending
 */
#define MU_SR_CEP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_CEP_SHIFT)) & MU_SR_CEP_MASK)
/*! @} */

/*! @name CCR0 - Core Control 0 */
/*! @{ */

#define MU_CCR0_NMI_MASK                         (0x1U)
#define MU_CCR0_NMI_SHIFT                        (0U)
/*! NMI - MUB Nonmaskable Interrupt Request
 *  0b0..Nonmaskable interrupt not issued
 *  0b1..Nonmaskable interrupt issued
 */
#define MU_CCR0_NMI(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR0_NMI_SHIFT)) & MU_CCR0_NMI_MASK)
/*! @} */

/*! @name CIER0 - Core Interrupt Enable 0 */
/*! @{ */

#define MU_CIER0_WAITIE_MASK                     (0x20U)
#define MU_CIER0_WAITIE_SHIFT                    (5U)
/*! WAITIE - Processor B Wait Mode Entry Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_CIER0_WAITIE(x)                       (((uint32_t)(((uint32_t)(x)) << MU_CIER0_WAITIE_SHIFT)) & MU_CIER0_WAITIE_MASK)
/*! @} */

/*! @name CSSR0 - Core Sticky Status 0 */
/*! @{ */

#define MU_CSSR0_NMIC_MASK                       (0x1U)
#define MU_CSSR0_NMIC_SHIFT                      (0U)
/*! NMIC - Processor B Nonmaskable Interrupt Clear
 *  0b0..Default
 *  0b1..Clear MUA_CCR0[NMI]
 */
#define MU_CSSR0_NMIC(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_NMIC_SHIFT)) & MU_CSSR0_NMIC_MASK)

#define MU_CSSR0_WAIT_MASK                       (0x20U)
#define MU_CSSR0_WAIT_SHIFT                      (5U)
/*! WAIT - Processor B Wait Mode Entry Interrupt Pending
 *  0b0..Processor A did not enter Wait Mode.
 *  0b1..Processor A entered Wait Mode.
 */
#define MU_CSSR0_WAIT(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_WAIT_SHIFT)) & MU_CSSR0_WAIT_MASK)
/*! @} */

/*! @name CSR0 - Core Status 0 */
/*! @{ */

#define MU_CSR0_WAIT_MASK                        (0x20U)
#define MU_CSR0_WAIT_SHIFT                       (5U)
/*! WAIT - Processor B Wait Mode Entry
 *  0b0..Not in Wait mode
 *  0b1..In Wait mode
 */
#define MU_CSR0_WAIT(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CSR0_WAIT_SHIFT)) & MU_CSR0_WAIT_MASK)
/*! @} */

/*! @name FCR - Flag Control */
/*! @{ */

#define MU_FCR_F0_MASK                           (0x1U)
#define MU_FCR_F0_SHIFT                          (0U)
/*! F0 - MUB to MUA Flag
 *  0b0..Clear MUA_FSR[Fn]
 *  0b1..Set MUA_FSR[Fn]
 */
#define MU_FCR_F0(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F0_SHIFT)) & MU_FCR_F0_MASK)

#define MU_FCR_F1_MASK                           (0x2U)
#define MU_FCR_F1_SHIFT                          (1U)
/*! F1 - MUB to MUA Flag
 *  0b0..Clear MUA_FSR[Fn]
 *  0b1..Set MUA_FSR[Fn]
 */
#define MU_FCR_F1(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F1_SHIFT)) & MU_FCR_F1_MASK)

#define MU_FCR_F2_MASK                           (0x4U)
#define MU_FCR_F2_SHIFT                          (2U)
/*! F2 - MUB to MUA Flag
 *  0b0..Clear MUA_FSR[Fn]
 *  0b1..Set MUA_FSR[Fn]
 */
#define MU_FCR_F2(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F2_SHIFT)) & MU_FCR_F2_MASK)
/*! @} */

/*! @name FSR - Flag Status */
/*! @{ */

#define MU_FSR_F0_MASK                           (0x1U)
#define MU_FSR_F0_SHIFT                          (0U)
/*! F0 - MUB to MUA-Side Flag
 *  0b0..MUA_FCR[Fn] = 0
 *  0b1..MUA_FCR[Fn] = 1
 */
#define MU_FSR_F0(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F0_SHIFT)) & MU_FSR_F0_MASK)

#define MU_FSR_F1_MASK                           (0x2U)
#define MU_FSR_F1_SHIFT                          (1U)
/*! F1 - MUB to MUA-Side Flag
 *  0b0..MUA_FCR[Fn] = 0
 *  0b1..MUA_FCR[Fn] = 1
 */
#define MU_FSR_F1(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F1_SHIFT)) & MU_FSR_F1_MASK)

#define MU_FSR_F2_MASK                           (0x4U)
#define MU_FSR_F2_SHIFT                          (2U)
/*! F2 - MUB to MUA-Side Flag
 *  0b0..MUA_FCR[Fn] = 0
 *  0b1..MUA_FCR[Fn] = 1
 */
#define MU_FSR_F2(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F2_SHIFT)) & MU_FSR_F2_MASK)
/*! @} */

/*! @name GIER - General-Purpose Interrupt Enable */
/*! @{ */

#define MU_GIER_GIE0_MASK                        (0x1U)
#define MU_GIER_GIE0_SHIFT                       (0U)
/*! GIE0 - MUB General-purpose Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_GIER_GIE0(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE0_SHIFT)) & MU_GIER_GIE0_MASK)

#define MU_GIER_GIE1_MASK                        (0x2U)
#define MU_GIER_GIE1_SHIFT                       (1U)
/*! GIE1 - MUB General-purpose Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_GIER_GIE1(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE1_SHIFT)) & MU_GIER_GIE1_MASK)

#define MU_GIER_GIE2_MASK                        (0x4U)
#define MU_GIER_GIE2_SHIFT                       (2U)
/*! GIE2 - MUB General-purpose Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_GIER_GIE2(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE2_SHIFT)) & MU_GIER_GIE2_MASK)

#define MU_GIER_GIE3_MASK                        (0x8U)
#define MU_GIER_GIE3_SHIFT                       (3U)
/*! GIE3 - MUB General-purpose Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_GIER_GIE3(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE3_SHIFT)) & MU_GIER_GIE3_MASK)
/*! @} */

/*! @name GCR - General-Purpose Control */
/*! @{ */

#define MU_GCR_GIR0_MASK                         (0x1U)
#define MU_GCR_GIR0_SHIFT                        (0U)
/*! GIR0 - MUB General-Purpose Interrupt Request
 *  0b0..Not requested
 *  0b1..Requested
 */
#define MU_GCR_GIR0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR0_SHIFT)) & MU_GCR_GIR0_MASK)

#define MU_GCR_GIR1_MASK                         (0x2U)
#define MU_GCR_GIR1_SHIFT                        (1U)
/*! GIR1 - MUB General-Purpose Interrupt Request
 *  0b0..Not requested
 *  0b1..Requested
 */
#define MU_GCR_GIR1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR1_SHIFT)) & MU_GCR_GIR1_MASK)

#define MU_GCR_GIR2_MASK                         (0x4U)
#define MU_GCR_GIR2_SHIFT                        (2U)
/*! GIR2 - MUB General-Purpose Interrupt Request
 *  0b0..Not requested
 *  0b1..Requested
 */
#define MU_GCR_GIR2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR2_SHIFT)) & MU_GCR_GIR2_MASK)

#define MU_GCR_GIR3_MASK                         (0x8U)
#define MU_GCR_GIR3_SHIFT                        (3U)
/*! GIR3 - MUB General-Purpose Interrupt Request
 *  0b0..Not requested
 *  0b1..Requested
 */
#define MU_GCR_GIR3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR3_SHIFT)) & MU_GCR_GIR3_MASK)
/*! @} */

/*! @name GSR - General-purpose Status */
/*! @{ */

#define MU_GSR_GIP0_MASK                         (0x1U)
#define MU_GSR_GIP0_SHIFT                        (0U)
/*! GIP0 - MUB General-Purpose Interrupt Request Pending
 *  0b0..Not pending
 *  0b1..Pending
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MU_GSR_GIP0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK)

#define MU_GSR_GIP1_MASK                         (0x2U)
#define MU_GSR_GIP1_SHIFT                        (1U)
/*! GIP1 - MUB General-Purpose Interrupt Request Pending
 *  0b0..Not pending
 *  0b1..Pending
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MU_GSR_GIP1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK)

#define MU_GSR_GIP2_MASK                         (0x4U)
#define MU_GSR_GIP2_SHIFT                        (2U)
/*! GIP2 - MUB General-Purpose Interrupt Request Pending
 *  0b0..Not pending
 *  0b1..Pending
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MU_GSR_GIP2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK)

#define MU_GSR_GIP3_MASK                         (0x8U)
#define MU_GSR_GIP3_SHIFT                        (3U)
/*! GIP3 - MUB General-Purpose Interrupt Request Pending
 *  0b0..Not pending
 *  0b1..Pending
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define MU_GSR_GIP3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK)
/*! @} */

/*! @name TCR - Transmit Control */
/*! @{ */

#define MU_TCR_TIE0_MASK                         (0x1U)
#define MU_TCR_TIE0_SHIFT                        (0U)
/*! TIE0 - MUB Transmit Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_TCR_TIE0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE0_SHIFT)) & MU_TCR_TIE0_MASK)

#define MU_TCR_TIE1_MASK                         (0x2U)
#define MU_TCR_TIE1_SHIFT                        (1U)
/*! TIE1 - MUB Transmit Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_TCR_TIE1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE1_SHIFT)) & MU_TCR_TIE1_MASK)

#define MU_TCR_TIE2_MASK                         (0x4U)
#define MU_TCR_TIE2_SHIFT                        (2U)
/*! TIE2 - MUB Transmit Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_TCR_TIE2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE2_SHIFT)) & MU_TCR_TIE2_MASK)

#define MU_TCR_TIE3_MASK                         (0x8U)
#define MU_TCR_TIE3_SHIFT                        (3U)
/*! TIE3 - MUB Transmit Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_TCR_TIE3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE3_SHIFT)) & MU_TCR_TIE3_MASK)
/*! @} */

/*! @name TSR - Transmit Status */
/*! @{ */

#define MU_TSR_TE0_MASK                          (0x1U)
#define MU_TSR_TE0_SHIFT                         (0U)
/*! TE0 - MUB Transmit Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define MU_TSR_TE0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE0_SHIFT)) & MU_TSR_TE0_MASK)

#define MU_TSR_TE1_MASK                          (0x2U)
#define MU_TSR_TE1_SHIFT                         (1U)
/*! TE1 - MUB Transmit Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define MU_TSR_TE1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE1_SHIFT)) & MU_TSR_TE1_MASK)

#define MU_TSR_TE2_MASK                          (0x4U)
#define MU_TSR_TE2_SHIFT                         (2U)
/*! TE2 - MUB Transmit Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define MU_TSR_TE2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE2_SHIFT)) & MU_TSR_TE2_MASK)

#define MU_TSR_TE3_MASK                          (0x8U)
#define MU_TSR_TE3_SHIFT                         (3U)
/*! TE3 - MUB Transmit Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define MU_TSR_TE3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE3_SHIFT)) & MU_TSR_TE3_MASK)
/*! @} */

/*! @name RCR - Receive Control */
/*! @{ */

#define MU_RCR_RIE0_MASK                         (0x1U)
#define MU_RCR_RIE0_SHIFT                        (0U)
/*! RIE0 - MUB Receive Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_RCR_RIE0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE0_SHIFT)) & MU_RCR_RIE0_MASK)

#define MU_RCR_RIE1_MASK                         (0x2U)
#define MU_RCR_RIE1_SHIFT                        (1U)
/*! RIE1 - MUB Receive Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_RCR_RIE1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE1_SHIFT)) & MU_RCR_RIE1_MASK)

#define MU_RCR_RIE2_MASK                         (0x4U)
#define MU_RCR_RIE2_SHIFT                        (2U)
/*! RIE2 - MUB Receive Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_RCR_RIE2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE2_SHIFT)) & MU_RCR_RIE2_MASK)

#define MU_RCR_RIE3_MASK                         (0x8U)
#define MU_RCR_RIE3_SHIFT                        (3U)
/*! RIE3 - MUB Receive Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define MU_RCR_RIE3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE3_SHIFT)) & MU_RCR_RIE3_MASK)
/*! @} */

/*! @name RSR - Receive Status */
/*! @{ */

#define MU_RSR_RF0_MASK                          (0x1U)
#define MU_RSR_RF0_SHIFT                         (0U)
/*! RF0 - MUB Receive Register Full
 *  0b0..Not full
 *  0b1..Full
 */
#define MU_RSR_RF0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF0_SHIFT)) & MU_RSR_RF0_MASK)

#define MU_RSR_RF1_MASK                          (0x2U)
#define MU_RSR_RF1_SHIFT                         (1U)
/*! RF1 - MUB Receive Register Full
 *  0b0..Not full
 *  0b1..Full
 */
#define MU_RSR_RF1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF1_SHIFT)) & MU_RSR_RF1_MASK)

#define MU_RSR_RF2_MASK                          (0x4U)
#define MU_RSR_RF2_SHIFT                         (2U)
/*! RF2 - MUB Receive Register Full
 *  0b0..Not full
 *  0b1..Full
 */
#define MU_RSR_RF2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF2_SHIFT)) & MU_RSR_RF2_MASK)

#define MU_RSR_RF3_MASK                          (0x8U)
#define MU_RSR_RF3_SHIFT                         (3U)
/*! RF3 - MUB Receive Register Full
 *  0b0..Not full
 *  0b1..Full
 */
#define MU_RSR_RF3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF3_SHIFT)) & MU_RSR_RF3_MASK)
/*! @} */

/*! @name TR - Transmit */
/*! @{ */

#define MU_TR_TR_DATA_MASK                       (0xFFFFFFFFU)
#define MU_TR_TR_DATA_SHIFT                      (0U)
/*! TR_DATA - MUB Transmit Data */
#define MU_TR_TR_DATA(x)                         (((uint32_t)(((uint32_t)(x)) << MU_TR_TR_DATA_SHIFT)) & MU_TR_TR_DATA_MASK)
/*! @} */

/* The count of MU_TR */
#define MU_TR_COUNT                              (4U)

/*! @name RR - Receive */
/*! @{ */

#define MU_RR_RR_DATA_MASK                       (0xFFFFFFFFU)
#define MU_RR_RR_DATA_SHIFT                      (0U)
/*! RR_DATA - MUB Receive Data */
#define MU_RR_RR_DATA(x)                         (((uint32_t)(((uint32_t)(x)) << MU_RR_RR_DATA_SHIFT)) & MU_RR_RR_DATA_MASK)
/*! @} */

/* The count of MU_RR */
#define MU_RR_COUNT                              (4U)


/*!
 * @}
 */ /* end of group MU_Register_Masks */


/* MU - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral MU2_MUA base address */
  #define MU2_MUA_BASE                             (0x50204000u)
  /** Peripheral MU2_MUA base address */
  #define MU2_MUA_BASE_NS                          (0x40204000u)
  /** Peripheral MU2_MUA base pointer */
  #define MU2_MUA                                  ((MU_Type *)MU2_MUA_BASE)
  /** Peripheral MU2_MUA base pointer */
  #define MU2_MUA_NS                               ((MU_Type *)MU2_MUA_BASE_NS)
  /** Peripheral MU4_MUB base address */
  #define MU4_MUB_BASE                             (0x50188000u)
  /** Peripheral MU4_MUB base address */
  #define MU4_MUB_BASE_NS                          (0x40188000u)
  /** Peripheral MU4_MUB base pointer */
  #define MU4_MUB                                  ((MU_Type *)MU4_MUB_BASE)
  /** Peripheral MU4_MUB base pointer */
  #define MU4_MUB_NS                               ((MU_Type *)MU4_MUB_BASE_NS)
  /** Array initializer of MU peripheral base addresses */
  #define MU_BASE_ADDRS                            { MU2_MUA_BASE, MU4_MUB_BASE }
  /** Array initializer of MU peripheral base pointers */
  #define MU_BASE_PTRS                             { MU2_MUA, MU4_MUB }
  /** Array initializer of MU peripheral base addresses */
  #define MU_BASE_ADDRS_NS                         { MU2_MUA_BASE_NS, MU4_MUB_BASE_NS }
  /** Array initializer of MU peripheral base pointers */
  #define MU_BASE_PTRS_NS                          { MU2_MUA_NS, MU4_MUB_NS }
#else
  /** Peripheral MU2_MUA base address */
  #define MU2_MUA_BASE                             (0x40204000u)
  /** Peripheral MU2_MUA base pointer */
  #define MU2_MUA                                  ((MU_Type *)MU2_MUA_BASE)
  /** Peripheral MU4_MUB base address */
  #define MU4_MUB_BASE                             (0x40188000u)
  /** Peripheral MU4_MUB base pointer */
  #define MU4_MUB                                  ((MU_Type *)MU4_MUB_BASE)
  /** Array initializer of MU peripheral base addresses */
  #define MU_BASE_ADDRS                            { MU2_MUA_BASE, MU4_MUB_BASE }
  /** Array initializer of MU peripheral base pointers */
  #define MU_BASE_PTRS                             { MU2_MUA, MU4_MUB }
#endif

/*!
 * @}
 */ /* end of group MU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- NIC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup NIC_Peripheral_Access_Layer NIC Peripheral Access Layer
 * @{
 */

/** NIC - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[73728];
  struct {                                         /* offset: 0x12000, array step: 0x1000 */
         uint8_t RESERVED_0[256];
    __IO uint32_t READ_QOS;                          /**< Read Channel QoS Value, array offset: 0x12100, array step: 0x1000 */
    __IO uint32_t WRITE_QOS;                         /**< Write Channel QoS Value, array offset: 0x12104, array step: 0x1000 */
    __IO uint32_t FN_MOD;                            /**< Issuing Functionality Modification, array offset: 0x12108, array step: 0x1000 */
    __IO uint32_t QOS_CNTL;                          /**< QoS Control, array offset: 0x1210C, array step: 0x1000 */
    __IO uint32_t MAX_OT;                            /**< Maximum Number of Outstanding Transactions, array offset: 0x12110, array step: 0x1000 */
    __IO uint32_t MAX_COMB_OT;                       /**< Maximum Combined Outstanding Transactions, array offset: 0x12114, array step: 0x1000 */
    __IO uint32_t AW_P;                              /**< AW Channel Peak Rate, array offset: 0x12118, array step: 0x1000 */
    __IO uint32_t AW_B;                              /**< AW Channel Burstiness Allowance, array offset: 0x1211C, array step: 0x1000 */
    __IO uint32_t AW_R;                              /**< AW Channel Average Rate, array offset: 0x12120, array step: 0x1000 */
    __IO uint32_t AR_P;                              /**< AR Channel Peak Rate, array offset: 0x12124, array step: 0x1000 */
    __IO uint32_t AR_B;                              /**< AR Channel Burstiness Allowance, array offset: 0x12128, array step: 0x1000 */
    __IO uint32_t AR_R;                              /**< AR Channel Average Rate, array offset: 0x1212C, array step: 0x1000 */
    __IO uint32_t TARGET_FC;                         /**< Feedback Controlled Target, array offset: 0x12130, array step: 0x1000 */
    __IO uint32_t KI_FC;                             /**< Feedback Controlled Scale, array offset: 0x12134, array step: 0x1000 */
    __IO uint32_t QOS_RANGE;                         /**< QoS Range, array offset: 0x12138, array step: 0x1000 */
         uint8_t RESERVED_1[3780];
  } ASIB[10];
} NIC_Type;

/* ----------------------------------------------------------------------------
   -- NIC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup NIC_Register_Masks NIC Register Masks
 * @{
 */

/*! @name READ_QOS - Read Channel QoS Value */
/*! @{ */

#define NIC_READ_QOS_READ_QOS_MASK               (0xFU)
#define NIC_READ_QOS_READ_QOS_SHIFT              (0U)
/*! READ_QOS - Read Channel QoS Value
 *  0b0000..The lowest priority
 *  0b0001-0b1110.....
 *  0b1111..The highest priority
 */
#define NIC_READ_QOS_READ_QOS(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_READ_QOS_READ_QOS_SHIFT)) & NIC_READ_QOS_READ_QOS_MASK)
/*! @} */

/* The count of NIC_READ_QOS */
#define NIC_READ_QOS_COUNT                       (10U)

/*! @name WRITE_QOS - Write Channel QoS Value */
/*! @{ */

#define NIC_WRITE_QOS_WRITE_QOS_MASK             (0xFU)
#define NIC_WRITE_QOS_WRITE_QOS_SHIFT            (0U)
/*! WRITE_QOS - Write channel QoS value
 *  0b0000..The lowest priority
 *  0b0001-0b1110.....
 *  0b1111..The highest priority
 */
#define NIC_WRITE_QOS_WRITE_QOS(x)               (((uint32_t)(((uint32_t)(x)) << NIC_WRITE_QOS_WRITE_QOS_SHIFT)) & NIC_WRITE_QOS_WRITE_QOS_MASK)
/*! @} */

/* The count of NIC_WRITE_QOS */
#define NIC_WRITE_QOS_COUNT                      (10U)

/*! @name FN_MOD - Issuing Functionality Modification */
/*! @{ */

#define NIC_FN_MOD_FN_MOD_MASK                   (0x3U)
#define NIC_FN_MOD_FN_MOD_SHIFT                  (0U)
/*! FN_MOD - Issuing Functionality Modification
 *  0b00..Default issuing
 *  0b01..Read issuing
 *  0b10..Write issuing
 *  0b11..Read and write issuing
 */
#define NIC_FN_MOD_FN_MOD(x)                     (((uint32_t)(((uint32_t)(x)) << NIC_FN_MOD_FN_MOD_SHIFT)) & NIC_FN_MOD_FN_MOD_MASK)
/*! @} */

/* The count of NIC_FN_MOD */
#define NIC_FN_MOD_COUNT                         (10U)

/*! @name QOS_CNTL - QoS Control */
/*! @{ */

#define NIC_QOS_CNTL_EN_AW_RATE_MASK             (0x1U)
#define NIC_QOS_CNTL_EN_AW_RATE_SHIFT            (0U)
/*! EN_AW_RATE - Enable AW Transaction Rate Regulation
 *  0b0..Disables
 *  0b1..Enables
 */
#define NIC_QOS_CNTL_EN_AW_RATE(x)               (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_EN_AW_RATE_SHIFT)) & NIC_QOS_CNTL_EN_AW_RATE_MASK)

#define NIC_QOS_CNTL_EN_AR_RATE_MASK             (0x2U)
#define NIC_QOS_CNTL_EN_AR_RATE_SHIFT            (1U)
/*! EN_AR_RATE - Enable AR Transaction Rate Regulation
 *  0b0..Disables
 *  0b1..Enables
 */
#define NIC_QOS_CNTL_EN_AR_RATE(x)               (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_EN_AR_RATE_SHIFT)) & NIC_QOS_CNTL_EN_AR_RATE_MASK)

#define NIC_QOS_CNTL_EN_AWAR_RATE_MASK           (0x4U)
#define NIC_QOS_CNTL_EN_AWAR_RATE_SHIFT          (2U)
/*! EN_AWAR_RATE - Enable Combined AW And AR Transaction Rate Regulation
 *  0b0..Disables
 *  0b1..Enables
 */
#define NIC_QOS_CNTL_EN_AWAR_RATE(x)             (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_EN_AWAR_RATE_SHIFT)) & NIC_QOS_CNTL_EN_AWAR_RATE_MASK)

#define NIC_QOS_CNTL_EN_AW_FC_MASK               (0x8U)
#define NIC_QOS_CNTL_EN_AW_FC_SHIFT              (3U)
/*! EN_AW_FC - Enable AW Feedback Control Regulation
 *  0b0..Disables
 *  0b1..Enables
 */
#define NIC_QOS_CNTL_EN_AW_FC(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_EN_AW_FC_SHIFT)) & NIC_QOS_CNTL_EN_AW_FC_MASK)

#define NIC_QOS_CNTL_EN_AR_FC_MASK               (0x10U)
#define NIC_QOS_CNTL_EN_AR_FC_SHIFT              (4U)
/*! EN_AR_FC - Enable AR Feedback Control Regulation
 *  0b0..Disables
 *  0b1..Enables
 */
#define NIC_QOS_CNTL_EN_AR_FC(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_EN_AR_FC_SHIFT)) & NIC_QOS_CNTL_EN_AR_FC_MASK)

#define NIC_QOS_CNTL_EN_AW_OT_MASK               (0x20U)
#define NIC_QOS_CNTL_EN_AW_OT_SHIFT              (5U)
/*! EN_AW_OT - Enable AW Outstanding Transaction Regulation
 *  0b0..Disables
 *  0b1..Enables
 */
#define NIC_QOS_CNTL_EN_AW_OT(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_EN_AW_OT_SHIFT)) & NIC_QOS_CNTL_EN_AW_OT_MASK)

#define NIC_QOS_CNTL_EN_AR_OT_MASK               (0x40U)
#define NIC_QOS_CNTL_EN_AR_OT_SHIFT              (6U)
/*! EN_AR_OT - Enable AR Outstanding Transaction Regulation
 *  0b0..Disables
 *  0b1..Enables
 */
#define NIC_QOS_CNTL_EN_AR_OT(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_EN_AR_OT_SHIFT)) & NIC_QOS_CNTL_EN_AR_OT_MASK)

#define NIC_QOS_CNTL_EN_AWAR_OT_MASK             (0x80U)
#define NIC_QOS_CNTL_EN_AWAR_OT_SHIFT            (7U)
/*! EN_AWAR_OT - Enable AW/AR Outstanding Transaction Regulation
 *  0b0..Disables
 *  0b1..Enables
 */
#define NIC_QOS_CNTL_EN_AWAR_OT(x)               (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_EN_AWAR_OT_SHIFT)) & NIC_QOS_CNTL_EN_AWAR_OT_MASK)

#define NIC_QOS_CNTL_MODE_AW_FC_MASK             (0x10000U)
#define NIC_QOS_CNTL_MODE_AW_FC_SHIFT            (16U)
/*! MODE_AW_FC - AW Feedback Control Mode
 *  0b0..Transaction latency
 *  0b1..Address latency
 */
#define NIC_QOS_CNTL_MODE_AW_FC(x)               (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_MODE_AW_FC_SHIFT)) & NIC_QOS_CNTL_MODE_AW_FC_MASK)

#define NIC_QOS_CNTL_MODE_AR_FC_MASK             (0x100000U)
#define NIC_QOS_CNTL_MODE_AR_FC_SHIFT            (20U)
/*! MODE_AR_FC - AR Feedback Control Mode
 *  0b0..Transaction latency
 *  0b1..Address latency
 */
#define NIC_QOS_CNTL_MODE_AR_FC(x)               (((uint32_t)(((uint32_t)(x)) << NIC_QOS_CNTL_MODE_AR_FC_SHIFT)) & NIC_QOS_CNTL_MODE_AR_FC_MASK)
/*! @} */

/* The count of NIC_QOS_CNTL */
#define NIC_QOS_CNTL_COUNT                       (10U)

/*! @name MAX_OT - Maximum Number of Outstanding Transactions */
/*! @{ */

#define NIC_MAX_OT_AW_MAX_OTF_MASK               (0xFFU)
#define NIC_MAX_OT_AW_MAX_OTF_SHIFT              (0U)
/*! AW_MAX_OTF - Fractional Part of Maximum Outstanding AW Addresses */
#define NIC_MAX_OT_AW_MAX_OTF(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_MAX_OT_AW_MAX_OTF_SHIFT)) & NIC_MAX_OT_AW_MAX_OTF_MASK)

#define NIC_MAX_OT_AW_MAX_OTI_MASK               (0x3F00U)
#define NIC_MAX_OT_AW_MAX_OTI_SHIFT              (8U)
/*! AW_MAX_OTI - Integer Part of Maximum Outstanding AW Addresses */
#define NIC_MAX_OT_AW_MAX_OTI(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_MAX_OT_AW_MAX_OTI_SHIFT)) & NIC_MAX_OT_AW_MAX_OTI_MASK)

#define NIC_MAX_OT_AR_MAX_OTF_MASK               (0xFF0000U)
#define NIC_MAX_OT_AR_MAX_OTF_SHIFT              (16U)
/*! AR_MAX_OTF - Fractional Part of Maximum Outstanding AR Addresses */
#define NIC_MAX_OT_AR_MAX_OTF(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_MAX_OT_AR_MAX_OTF_SHIFT)) & NIC_MAX_OT_AR_MAX_OTF_MASK)

#define NIC_MAX_OT_AR_MAX_OTI_MASK               (0x3F000000U)
#define NIC_MAX_OT_AR_MAX_OTI_SHIFT              (24U)
/*! AR_MAX_OTI - Integer Part of Maximum Outstanding AR Addresses */
#define NIC_MAX_OT_AR_MAX_OTI(x)                 (((uint32_t)(((uint32_t)(x)) << NIC_MAX_OT_AR_MAX_OTI_SHIFT)) & NIC_MAX_OT_AR_MAX_OTI_MASK)
/*! @} */

/* The count of NIC_MAX_OT */
#define NIC_MAX_OT_COUNT                         (10U)

/*! @name MAX_COMB_OT - Maximum Combined Outstanding Transactions */
/*! @{ */

#define NIC_MAX_COMB_OT_AWAR_MAX_OTF_MASK        (0xFFU)
#define NIC_MAX_COMB_OT_AWAR_MAX_OTF_SHIFT       (0U)
/*! AWAR_MAX_OTF - Fractional Part of Maximum Combined Outstanding AW and AR Addresses */
#define NIC_MAX_COMB_OT_AWAR_MAX_OTF(x)          (((uint32_t)(((uint32_t)(x)) << NIC_MAX_COMB_OT_AWAR_MAX_OTF_SHIFT)) & NIC_MAX_COMB_OT_AWAR_MAX_OTF_MASK)

#define NIC_MAX_COMB_OT_AWAR_MAX_OTI_MASK        (0x7F00U)
#define NIC_MAX_COMB_OT_AWAR_MAX_OTI_SHIFT       (8U)
/*! AWAR_MAX_OTI - Integer Part of Maximum Combined Outstanding AW and AR Addresses */
#define NIC_MAX_COMB_OT_AWAR_MAX_OTI(x)          (((uint32_t)(((uint32_t)(x)) << NIC_MAX_COMB_OT_AWAR_MAX_OTI_SHIFT)) & NIC_MAX_COMB_OT_AWAR_MAX_OTI_MASK)
/*! @} */

/* The count of NIC_MAX_COMB_OT */
#define NIC_MAX_COMB_OT_COUNT                    (10U)

/*! @name AW_P - AW Channel Peak Rate */
/*! @{ */

#define NIC_AW_P_AW_P_MASK                       (0xFF000000U)
#define NIC_AW_P_AW_P_SHIFT                      (24U)
/*! AW_P - AW Channel Peak Rate */
#define NIC_AW_P_AW_P(x)                         (((uint32_t)(((uint32_t)(x)) << NIC_AW_P_AW_P_SHIFT)) & NIC_AW_P_AW_P_MASK)
/*! @} */

/* The count of NIC_AW_P */
#define NIC_AW_P_COUNT                           (10U)

/*! @name AW_B - AW Channel Burstiness Allowance */
/*! @{ */

#define NIC_AW_B_AW_B_MASK                       (0xFFFFU)
#define NIC_AW_B_AW_B_SHIFT                      (0U)
/*! AW_B - AW Channel Burstiness */
#define NIC_AW_B_AW_B(x)                         (((uint32_t)(((uint32_t)(x)) << NIC_AW_B_AW_B_SHIFT)) & NIC_AW_B_AW_B_MASK)
/*! @} */

/* The count of NIC_AW_B */
#define NIC_AW_B_COUNT                           (10U)

/*! @name AW_R - AW Channel Average Rate */
/*! @{ */

#define NIC_AW_R_AW_R_MASK                       (0xFFF00000U)
#define NIC_AW_R_AW_R_SHIFT                      (20U)
/*! AW_R - AW Channel Average Rate */
#define NIC_AW_R_AW_R(x)                         (((uint32_t)(((uint32_t)(x)) << NIC_AW_R_AW_R_SHIFT)) & NIC_AW_R_AW_R_MASK)
/*! @} */

/* The count of NIC_AW_R */
#define NIC_AW_R_COUNT                           (10U)

/*! @name AR_P - AR Channel Peak Rate */
/*! @{ */

#define NIC_AR_P_AR_P_MASK                       (0xFF000000U)
#define NIC_AR_P_AR_P_SHIFT                      (24U)
/*! AR_P - AR Channel Peak Rate */
#define NIC_AR_P_AR_P(x)                         (((uint32_t)(((uint32_t)(x)) << NIC_AR_P_AR_P_SHIFT)) & NIC_AR_P_AR_P_MASK)
/*! @} */

/* The count of NIC_AR_P */
#define NIC_AR_P_COUNT                           (10U)

/*! @name AR_B - AR Channel Burstiness Allowance */
/*! @{ */

#define NIC_AR_B_AR_B_MASK                       (0xFFFFU)
#define NIC_AR_B_AR_B_SHIFT                      (0U)
/*! AR_B - AR Channel Burstiness */
#define NIC_AR_B_AR_B(x)                         (((uint32_t)(((uint32_t)(x)) << NIC_AR_B_AR_B_SHIFT)) & NIC_AR_B_AR_B_MASK)
/*! @} */

/* The count of NIC_AR_B */
#define NIC_AR_B_COUNT                           (10U)

/*! @name AR_R - AR Channel Average Rate */
/*! @{ */

#define NIC_AR_R_AR_R_MASK                       (0xFFF00000U)
#define NIC_AR_R_AR_R_SHIFT                      (20U)
/*! AR_R - AR Channel Average Rate */
#define NIC_AR_R_AR_R(x)                         (((uint32_t)(((uint32_t)(x)) << NIC_AR_R_AR_R_SHIFT)) & NIC_AR_R_AR_R_MASK)
/*! @} */

/* The count of NIC_AR_R */
#define NIC_AR_R_COUNT                           (10U)

/*! @name TARGET_FC - Feedback Controlled Target */
/*! @{ */

#define NIC_TARGET_FC_AW_TGT_LATENCY_MASK        (0xFFFU)
#define NIC_TARGET_FC_AW_TGT_LATENCY_SHIFT       (0U)
/*! AW_TGT_LATENCY - AW Channel Target Latency */
#define NIC_TARGET_FC_AW_TGT_LATENCY(x)          (((uint32_t)(((uint32_t)(x)) << NIC_TARGET_FC_AW_TGT_LATENCY_SHIFT)) & NIC_TARGET_FC_AW_TGT_LATENCY_MASK)

#define NIC_TARGET_FC_AR_TGT_LATENCY_MASK        (0xFFF0000U)
#define NIC_TARGET_FC_AR_TGT_LATENCY_SHIFT       (16U)
/*! AR_TGT_LATENCY - AR Channel Target Latency */
#define NIC_TARGET_FC_AR_TGT_LATENCY(x)          (((uint32_t)(((uint32_t)(x)) << NIC_TARGET_FC_AR_TGT_LATENCY_SHIFT)) & NIC_TARGET_FC_AR_TGT_LATENCY_MASK)
/*! @} */

/* The count of NIC_TARGET_FC */
#define NIC_TARGET_FC_COUNT                      (10U)

/*! @name KI_FC - Feedback Controlled Scale */
/*! @{ */

#define NIC_KI_FC_AW_KI_MASK                     (0x7U)
#define NIC_KI_FC_AW_KI_SHIFT                    (0U)
/*! AW_KI - awqos Scale Factor
 *  0b000..2^-3
 *  0b001..2^-4
 *  0b010-0b110..2^-5 to 2^-9
 *  0b111..2^-10
 */
#define NIC_KI_FC_AW_KI(x)                       (((uint32_t)(((uint32_t)(x)) << NIC_KI_FC_AW_KI_SHIFT)) & NIC_KI_FC_AW_KI_MASK)

#define NIC_KI_FC_AR_KI_MASK                     (0x700U)
#define NIC_KI_FC_AR_KI_SHIFT                    (8U)
/*! AR_KI - arqos Scale Factor
 *  0b000..2^-3
 *  0b001..2^-4
 *  0b010-0b110..2^-5 to 2^-9
 *  0b111..2^-10
 */
#define NIC_KI_FC_AR_KI(x)                       (((uint32_t)(((uint32_t)(x)) << NIC_KI_FC_AR_KI_SHIFT)) & NIC_KI_FC_AR_KI_MASK)
/*! @} */

/* The count of NIC_KI_FC */
#define NIC_KI_FC_COUNT                          (10U)

/*! @name QOS_RANGE - QoS Range */
/*! @{ */

#define NIC_QOS_RANGE_AW_MIN_QOS_MASK            (0xFU)
#define NIC_QOS_RANGE_AW_MIN_QOS_SHIFT           (0U)
/*! AW_MIN_QOS - Minimum awqos
 *  0b0000..The lowest priority
 *  0b0001-0b1110.....
 *  0b1111..The highest priority
 */
#define NIC_QOS_RANGE_AW_MIN_QOS(x)              (((uint32_t)(((uint32_t)(x)) << NIC_QOS_RANGE_AW_MIN_QOS_SHIFT)) & NIC_QOS_RANGE_AW_MIN_QOS_MASK)

#define NIC_QOS_RANGE_AW_MAX_QOS_MASK            (0xF00U)
#define NIC_QOS_RANGE_AW_MAX_QOS_SHIFT           (8U)
/*! AW_MAX_QOS - Maximum awqos
 *  0b0000..The lowest priority
 *  0b0001-0b1110.....
 *  0b1111..The highest priority
 */
#define NIC_QOS_RANGE_AW_MAX_QOS(x)              (((uint32_t)(((uint32_t)(x)) << NIC_QOS_RANGE_AW_MAX_QOS_SHIFT)) & NIC_QOS_RANGE_AW_MAX_QOS_MASK)

#define NIC_QOS_RANGE_AR_MIN_QOS_MASK            (0xF0000U)
#define NIC_QOS_RANGE_AR_MIN_QOS_SHIFT           (16U)
/*! AR_MIN_QOS - Minimum arqos
 *  0b0000..The lowest priority
 *  0b0001-0b1110.....
 *  0b1111..The highest priority
 */
#define NIC_QOS_RANGE_AR_MIN_QOS(x)              (((uint32_t)(((uint32_t)(x)) << NIC_QOS_RANGE_AR_MIN_QOS_SHIFT)) & NIC_QOS_RANGE_AR_MIN_QOS_MASK)

#define NIC_QOS_RANGE_AR_MAX_QOS_MASK            (0xF000000U)
#define NIC_QOS_RANGE_AR_MAX_QOS_SHIFT           (24U)
/*! AR_MAX_QOS - Maximum arqos
 *  0b0000..The lowest priority
 *  0b0001-0b1110.....
 *  0b1111..The highest priority
 */
#define NIC_QOS_RANGE_AR_MAX_QOS(x)              (((uint32_t)(((uint32_t)(x)) << NIC_QOS_RANGE_AR_MAX_QOS_SHIFT)) & NIC_QOS_RANGE_AR_MAX_QOS_MASK)
/*! @} */

/* The count of NIC_QOS_RANGE */
#define NIC_QOS_RANGE_COUNT                      (10U)


/*!
 * @}
 */ /* end of group NIC_Register_Masks */


/* NIC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral NIC_MEDIA1 base address */
  #define NIC_MEDIA1_BASE                          (0x504C0000u)
  /** Peripheral NIC_MEDIA1 base address */
  #define NIC_MEDIA1_BASE_NS                       (0x404C0000u)
  /** Peripheral NIC_MEDIA1 base pointer */
  #define NIC_MEDIA1                               ((NIC_Type *)NIC_MEDIA1_BASE)
  /** Peripheral NIC_MEDIA1 base pointer */
  #define NIC_MEDIA1_NS                            ((NIC_Type *)NIC_MEDIA1_BASE_NS)
  /** Array initializer of NIC peripheral base addresses */
  #define NIC_BASE_ADDRS                           { NIC_MEDIA1_BASE }
  /** Array initializer of NIC peripheral base pointers */
  #define NIC_BASE_PTRS                            { NIC_MEDIA1 }
  /** Array initializer of NIC peripheral base addresses */
  #define NIC_BASE_ADDRS_NS                        { NIC_MEDIA1_BASE_NS }
  /** Array initializer of NIC peripheral base pointers */
  #define NIC_BASE_PTRS_NS                         { NIC_MEDIA1_NS }
#else
  /** Peripheral NIC_MEDIA1 base address */
  #define NIC_MEDIA1_BASE                          (0x404C0000u)
  /** Peripheral NIC_MEDIA1 base pointer */
  #define NIC_MEDIA1                               ((NIC_Type *)NIC_MEDIA1_BASE)
  /** Array initializer of NIC peripheral base addresses */
  #define NIC_BASE_ADDRS                           { NIC_MEDIA1_BASE }
  /** Array initializer of NIC peripheral base pointers */
  #define NIC_BASE_PTRS                            { NIC_MEDIA1 }
#endif

/*!
 * @}
 */ /* end of group NIC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OCOTP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
 * @{
 */

/** OCOTP - Register Layout Typedef */
typedef struct {
  __IO uint32_t OTP_SHADOW_PARTA[48];              /**< OTP shadow register, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[384];
  __IO uint32_t OTP_SHADOW_PARTB[368];             /**< OTP shadow register, array offset: 0x240, array step: 0x4 */
} OCOTP_Type;

/* ----------------------------------------------------------------------------
   -- OCOTP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
 * @{
 */

/*! @name OTP_SHADOW_PARTA - OTP shadow register */
/*! @{ */

#define OCOTP_OTP_SHADOW_PARTA_SHADOW_MASK       (0xFFFFFFFFU)
#define OCOTP_OTP_SHADOW_PARTA_SHADOW_SHIFT      (0U)
/*! SHADOW - OTP shadow register, fsb have read access of shadow 0-47 (offset should be 0*4-47*4) */
#define OCOTP_OTP_SHADOW_PARTA_SHADOW(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_SHADOW_PARTA_SHADOW_SHIFT)) & OCOTP_OTP_SHADOW_PARTA_SHADOW_MASK)
/*! @} */

/* The count of OCOTP_OTP_SHADOW_PARTA */
#define OCOTP_OTP_SHADOW_PARTA_COUNT             (48U)

/*! @name OTP_SHADOW_PARTB - OTP shadow register */
/*! @{ */

#define OCOTP_OTP_SHADOW_PARTB_SHADOW_MASK       (0xFFFFFFFFU)
#define OCOTP_OTP_SHADOW_PARTB_SHADOW_SHIFT      (0U)
/*! SHADOW - OTP shadow register, fsb have read access of shadow 144-511 (offset should be 144*4-511*4) */
#define OCOTP_OTP_SHADOW_PARTB_SHADOW(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_SHADOW_PARTB_SHADOW_SHIFT)) & OCOTP_OTP_SHADOW_PARTB_SHADOW_MASK)
/*! @} */

/* The count of OCOTP_OTP_SHADOW_PARTB */
#define OCOTP_OTP_SHADOW_PARTB_COUNT             (368U)


/*!
 * @}
 */ /* end of group OCOTP_Register_Masks */


/* OCOTP - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral OCOTP base address */
  #define OCOTP_BASE                               (0x50018000u)
  /** Peripheral OCOTP base address */
  #define OCOTP_BASE_NS                            (0x40018000u)
  /** Peripheral OCOTP base pointer */
  #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
  /** Peripheral OCOTP base pointer */
  #define OCOTP_NS                                 ((OCOTP_Type *)OCOTP_BASE_NS)
  /** Array initializer of OCOTP peripheral base addresses */
  #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
  /** Array initializer of OCOTP peripheral base pointers */
  #define OCOTP_BASE_PTRS                          { OCOTP }
  /** Array initializer of OCOTP peripheral base addresses */
  #define OCOTP_BASE_ADDRS_NS                      { OCOTP_BASE_NS }
  /** Array initializer of OCOTP peripheral base pointers */
  #define OCOTP_BASE_PTRS_NS                       { OCOTP_NS }
#else
  /** Peripheral OCOTP base address */
  #define OCOTP_BASE                               (0x40018000u)
  /** Peripheral OCOTP base pointer */
  #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
  /** Array initializer of OCOTP peripheral base addresses */
  #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
  /** Array initializer of OCOTP peripheral base pointers */
  #define OCOTP_BASE_PTRS                          { OCOTP }
#endif

/*!
 * @}
 */ /* end of group OCOTP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OSC32KNP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSC32KNP_Peripheral_Access_Layer OSC32KNP Peripheral Access Layer
 * @{
 */

/** OSC32KNP - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Control, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __IO uint32_t STAT;                              /**< Clock Status, offset: 0x8 */
} OSC32KNP_Type;

/* ----------------------------------------------------------------------------
   -- OSC32KNP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSC32KNP_Register_Masks OSC32KNP Register Masks
 * @{
 */

/*! @name CTRL - Control */
/*! @{ */

#define OSC32KNP_CTRL_OSC_DIS_MASK               (0x1U)
#define OSC32KNP_CTRL_OSC_DIS_SHIFT              (0U)
/*! OSC_DIS - Oscillator Output Disable
 *  0b0..Enable the oscillator output
 *  0b1..Disable the oscillator output
 */
#define OSC32KNP_CTRL_OSC_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << OSC32KNP_CTRL_OSC_DIS_SHIFT)) & OSC32KNP_CTRL_OSC_DIS_MASK)

#define OSC32KNP_CTRL_MODE_MASK                  (0x2U)
#define OSC32KNP_CTRL_MODE_SHIFT                 (1U)
/*! MODE - Mode
 *  0b0..Low-Power (Nano-Power) mode
 *  0b1..High-Power mode
 */
#define OSC32KNP_CTRL_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << OSC32KNP_CTRL_MODE_SHIFT)) & OSC32KNP_CTRL_MODE_MASK)

#define OSC32KNP_CTRL_BYPASS_EN_MASK             (0x4U)
#define OSC32KNP_CTRL_BYPASS_EN_SHIFT            (2U)
/*! BYPASS_EN - Bypass Mode Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define OSC32KNP_CTRL_BYPASS_EN(x)               (((uint32_t)(((uint32_t)(x)) << OSC32KNP_CTRL_BYPASS_EN_SHIFT)) & OSC32KNP_CTRL_BYPASS_EN_MASK)

#define OSC32KNP_CTRL_CAP_TRIM_MASK              (0xF00U)
#define OSC32KNP_CTRL_CAP_TRIM_SHIFT             (8U)
/*! CAP_TRIM - Capacitor Trim Value
 *  0b0000..0 pF
 *  0b0001..2 pF
 *  0b0010..4 pF
 *  0b0011..6 pF
 *  0b0100..8 pF
 *  0b0101..10 pF
 *  0b0110..12 pF
 *  0b0111..14 pF
 *  0b1000..16 pF
 *  0b1001..18 pF
 *  0b1010..20 pF
 *  0b1011..22 pF
 *  0b1100..24 pF
 *  0b1101..26 pF
 *  0b1110..28 pF
 *  0b1111..30 pF
 */
#define OSC32KNP_CTRL_CAP_TRIM(x)                (((uint32_t)(((uint32_t)(x)) << OSC32KNP_CTRL_CAP_TRIM_SHIFT)) & OSC32KNP_CTRL_CAP_TRIM_MASK)

#define OSC32KNP_CTRL_CLKMON_EN_MASK             (0x10000U)
#define OSC32KNP_CTRL_CLKMON_EN_SHIFT            (16U)
/*! CLKMON_EN - Clock Monitor Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define OSC32KNP_CTRL_CLKMON_EN(x)               (((uint32_t)(((uint32_t)(x)) << OSC32KNP_CTRL_CLKMON_EN_SHIFT)) & OSC32KNP_CTRL_CLKMON_EN_MASK)
/*! @} */

/*! @name STAT - Clock Status */
/*! @{ */

#define OSC32KNP_STAT_TCXO_STABLE_MASK           (0x1U)
#define OSC32KNP_STAT_TCXO_STABLE_SHIFT          (0U)
/*! TCXO_STABLE - Startup Oscillator Stable
 *  0b0..Unstable
 *  0b1..Stable
 */
#define OSC32KNP_STAT_TCXO_STABLE(x)             (((uint32_t)(((uint32_t)(x)) << OSC32KNP_STAT_TCXO_STABLE_SHIFT)) & OSC32KNP_STAT_TCXO_STABLE_MASK)

#define OSC32KNP_STAT_SCXO_STABLE_MASK           (0x2U)
#define OSC32KNP_STAT_SCXO_STABLE_SHIFT          (1U)
/*! SCXO_STABLE - Self-Charge Oscillator Stable
 *  0b0..Unstable
 *  0b1..Stable
 */
#define OSC32KNP_STAT_SCXO_STABLE(x)             (((uint32_t)(((uint32_t)(x)) << OSC32KNP_STAT_SCXO_STABLE_SHIFT)) & OSC32KNP_STAT_SCXO_STABLE_MASK)

#define OSC32KNP_STAT_CLK_TAMPER_DETECTED_MASK   (0x100U)
#define OSC32KNP_STAT_CLK_TAMPER_DETECTED_SHIFT  (8U)
/*! CLK_TAMPER_DETECTED - Clock Tamper Detected
 *  0b0..Not detected
 *  0b1..Detected
 */
#define OSC32KNP_STAT_CLK_TAMPER_DETECTED(x)     (((uint32_t)(((uint32_t)(x)) << OSC32KNP_STAT_CLK_TAMPER_DETECTED_SHIFT)) & OSC32KNP_STAT_CLK_TAMPER_DETECTED_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group OSC32KNP_Register_Masks */


/* OSC32KNP - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral OSC32KNP base address */
  #define OSC32KNP_BASE                            (0x50063000u)
  /** Peripheral OSC32KNP base address */
  #define OSC32KNP_BASE_NS                         (0x40063000u)
  /** Peripheral OSC32KNP base pointer */
  #define OSC32KNP                                 ((OSC32KNP_Type *)OSC32KNP_BASE)
  /** Peripheral OSC32KNP base pointer */
  #define OSC32KNP_NS                              ((OSC32KNP_Type *)OSC32KNP_BASE_NS)
  /** Array initializer of OSC32KNP peripheral base addresses */
  #define OSC32KNP_BASE_ADDRS                      { OSC32KNP_BASE }
  /** Array initializer of OSC32KNP peripheral base pointers */
  #define OSC32KNP_BASE_PTRS                       { OSC32KNP }
  /** Array initializer of OSC32KNP peripheral base addresses */
  #define OSC32KNP_BASE_ADDRS_NS                   { OSC32KNP_BASE_NS }
  /** Array initializer of OSC32KNP peripheral base pointers */
  #define OSC32KNP_BASE_PTRS_NS                    { OSC32KNP_NS }
#else
  /** Peripheral OSC32KNP base address */
  #define OSC32KNP_BASE                            (0x40063000u)
  /** Peripheral OSC32KNP base pointer */
  #define OSC32KNP                                 ((OSC32KNP_Type *)OSC32KNP_BASE)
  /** Array initializer of OSC32KNP peripheral base addresses */
  #define OSC32KNP_BASE_ADDRS                      { OSC32KNP_BASE }
  /** Array initializer of OSC32KNP peripheral base pointers */
  #define OSC32KNP_BASE_PTRS                       { OSC32KNP }
#endif

/*!
 * @}
 */ /* end of group OSC32KNP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OSCCA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSCCA_Peripheral_Access_Layer OSCCA Peripheral Access Layer
 * @{
 */

/** OSCCA - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[512];
  __IO uint32_t SAFO_SGI_DATIN0A;                  /**< Input Data register 0 lower-bank low, offset: 0x200 */
  __IO uint32_t SAFO_SGI_DATIN0B;                  /**< Input Data register 0 lower-bank high, offset: 0x204 */
  __IO uint32_t SAFO_SGI_DATIN0C;                  /**< Input Data register 0 upper-bank low, offset: 0x208 */
  __IO uint32_t SAFO_SGI_DATIN0D;                  /**< Input Data register 0 upper-bank high, offset: 0x20C */
  __IO uint32_t SAFO_SGI_DATIN1A;                  /**< Input Data register 1 lower-bank low, offset: 0x210 */
  __IO uint32_t SAFO_SGI_DATIN1B;                  /**< Input Data register 1 lower-bank high, offset: 0x214 */
  __IO uint32_t SAFO_SGI_DATIN1C;                  /**< Input Data register 1 upper-bank low, offset: 0x218 */
  __IO uint32_t SAFO_SGI_DATIN1D;                  /**< Input Data register 1 upper-bank high, offset: 0x21C */
       uint8_t RESERVED_1[32];
  __IO uint32_t SAFO_SGI_KEY0A;                    /**< Input Key register 0 lower-bank low, offset: 0x240 */
  __IO uint32_t SAFO_SGI_KEY0B;                    /**< Input Key register 0 lower-bank high, offset: 0x244 */
  __IO uint32_t SAFO_SGI_KEY0C;                    /**< Input Key register 0 upper-bank low, offset: 0x248 */
  __IO uint32_t SAFO_SGI_KEY0D;                    /**< Input Key register 0 upper-bank high, offset: 0x24C */
  __IO uint32_t SAFO_SGI_KEY1A;                    /**< Input Key register 1 lower-bank low, offset: 0x250 */
  __IO uint32_t SAFO_SGI_KEY1B;                    /**< Input Key register 1 lower-bank high, offset: 0x254 */
  __IO uint32_t SAFO_SGI_KEY1C;                    /**< Input Key register 1 upper-bank low, offset: 0x258 */
  __IO uint32_t SAFO_SGI_KEY1D;                    /**< Input Key register 1 upper-bank high, offset: 0x25C */
       uint8_t RESERVED_2[96];
  __I  uint32_t SAFO_SGI_DATOUTA;                  /**< Output Data register lower-bank low, offset: 0x2C0 */
  __I  uint32_t SAFO_SGI_DATOUTB;                  /**< Ouput Data register lower-bank high, offset: 0x2C4 */
  __I  uint32_t SAFO_SGI_DATOUTC;                  /**< Ouput Data register upper-bank low, offset: 0x2C8 */
  __I  uint32_t SAFO_SGI_DATOUTD;                  /**< Output Data register upper-bank high, offset: 0x2CC */
       uint8_t RESERVED_3[2352];
  __I  uint32_t SAFO_SGI_STATUS;                   /**< Status Register, offset: 0xC00 */
  __IO uint32_t SAFO_SGI_COUNT;                    /**< Calculation Counter, offset: 0xC04 */
       uint8_t RESERVED_4[248];
  __IO uint32_t SAFO_SGI_CTRL;                     /**< SGI Control Register, offset: 0xD00 */
  __IO uint32_t SAFO_SGI_CTRL2;                    /**< SGI Control Register 2, offset: 0xD04 */
       uint8_t RESERVED_5[12];
  __IO uint32_t SAFO_SGI_SM3_CTRL;                 /**< SM3 Control Register, offset: 0xD14 */
  __O  uint32_t SAFO_SGI_SM3_FIFO;                 /**< SM3 FIFO Register, offset: 0xD18 */
  __I  uint32_t SAFO_SGI_CONFIG;                   /**< SGI Configuration Register, offset: 0xD1C */
       uint8_t RESERVED_6[708];
  __IO uint32_t SAFO_SGI_INT_ENABLE;               /**< Interrupt Enable, offset: 0xFE4 */
  __O  uint32_t SAFO_SGI_INT_STATUS_CLR;           /**< Interrupt Status Clear, offset: 0xFE8 */
  __O  uint32_t SAFO_SGI_INT_STATUS_SET;           /**< Interrupt Status Set, offset: 0xFEC */
} OSCCA_Type;

/* ----------------------------------------------------------------------------
   -- OSCCA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSCCA_Register_Masks OSCCA Register Masks
 * @{
 */

/*! @name SAFO_SGI_DATIN0A - Input Data register 0 lower-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_DATIN0A_DATIN0A_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATIN0A_DATIN0A_SHIFT     (0U)
/*! DATIN0A - Input Data register */
#define OSCCA_SAFO_SGI_DATIN0A_DATIN0A(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATIN0A_DATIN0A_SHIFT)) & OSCCA_SAFO_SGI_DATIN0A_DATIN0A_MASK)
/*! @} */

/*! @name SAFO_SGI_DATIN0B - Input Data register 0 lower-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_DATIN0B_DATIN0B_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATIN0B_DATIN0B_SHIFT     (0U)
/*! DATIN0B - Input Data register */
#define OSCCA_SAFO_SGI_DATIN0B_DATIN0B(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATIN0B_DATIN0B_SHIFT)) & OSCCA_SAFO_SGI_DATIN0B_DATIN0B_MASK)
/*! @} */

/*! @name SAFO_SGI_DATIN0C - Input Data register 0 upper-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_DATIN0C_DATIN0C_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATIN0C_DATIN0C_SHIFT     (0U)
/*! DATIN0C - Input Data register */
#define OSCCA_SAFO_SGI_DATIN0C_DATIN0C(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATIN0C_DATIN0C_SHIFT)) & OSCCA_SAFO_SGI_DATIN0C_DATIN0C_MASK)
/*! @} */

/*! @name SAFO_SGI_DATIN0D - Input Data register 0 upper-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_DATIN0D_DATIN0D_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATIN0D_DATIN0D_SHIFT     (0U)
/*! DATIN0D - Input Data register */
#define OSCCA_SAFO_SGI_DATIN0D_DATIN0D(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATIN0D_DATIN0D_SHIFT)) & OSCCA_SAFO_SGI_DATIN0D_DATIN0D_MASK)
/*! @} */

/*! @name SAFO_SGI_DATIN1A - Input Data register 1 lower-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_DATIN1A_DATIN1A_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATIN1A_DATIN1A_SHIFT     (0U)
/*! DATIN1A - Input Data register */
#define OSCCA_SAFO_SGI_DATIN1A_DATIN1A(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATIN1A_DATIN1A_SHIFT)) & OSCCA_SAFO_SGI_DATIN1A_DATIN1A_MASK)
/*! @} */

/*! @name SAFO_SGI_DATIN1B - Input Data register 1 lower-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_DATIN1B_DATIN1B_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATIN1B_DATIN1B_SHIFT     (0U)
/*! DATIN1B - Input Data register */
#define OSCCA_SAFO_SGI_DATIN1B_DATIN1B(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATIN1B_DATIN1B_SHIFT)) & OSCCA_SAFO_SGI_DATIN1B_DATIN1B_MASK)
/*! @} */

/*! @name SAFO_SGI_DATIN1C - Input Data register 1 upper-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_DATIN1C_DATIN1C_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATIN1C_DATIN1C_SHIFT     (0U)
/*! DATIN1C - Input Data register */
#define OSCCA_SAFO_SGI_DATIN1C_DATIN1C(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATIN1C_DATIN1C_SHIFT)) & OSCCA_SAFO_SGI_DATIN1C_DATIN1C_MASK)
/*! @} */

/*! @name SAFO_SGI_DATIN1D - Input Data register 1 upper-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_DATIN1D_DATIN1D_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATIN1D_DATIN1D_SHIFT     (0U)
/*! DATIN1D - Input Data register */
#define OSCCA_SAFO_SGI_DATIN1D_DATIN1D(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATIN1D_DATIN1D_SHIFT)) & OSCCA_SAFO_SGI_DATIN1D_DATIN1D_MASK)
/*! @} */

/*! @name SAFO_SGI_KEY0A - Input Key register 0 lower-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_KEY0A_KEY0A_MASK          (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_KEY0A_KEY0A_SHIFT         (0U)
/*! KEY0A - Input Key register */
#define OSCCA_SAFO_SGI_KEY0A_KEY0A(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_KEY0A_KEY0A_SHIFT)) & OSCCA_SAFO_SGI_KEY0A_KEY0A_MASK)
/*! @} */

/*! @name SAFO_SGI_KEY0B - Input Key register 0 lower-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_KEY0B_KEY0B_MASK          (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_KEY0B_KEY0B_SHIFT         (0U)
/*! KEY0B - Input Key register */
#define OSCCA_SAFO_SGI_KEY0B_KEY0B(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_KEY0B_KEY0B_SHIFT)) & OSCCA_SAFO_SGI_KEY0B_KEY0B_MASK)
/*! @} */

/*! @name SAFO_SGI_KEY0C - Input Key register 0 upper-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_KEY0C_KEY0C_MASK          (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_KEY0C_KEY0C_SHIFT         (0U)
/*! KEY0C - Input Key register */
#define OSCCA_SAFO_SGI_KEY0C_KEY0C(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_KEY0C_KEY0C_SHIFT)) & OSCCA_SAFO_SGI_KEY0C_KEY0C_MASK)
/*! @} */

/*! @name SAFO_SGI_KEY0D - Input Key register 0 upper-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_KEY0D_KEY0D_MASK          (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_KEY0D_KEY0D_SHIFT         (0U)
/*! KEY0D - Input Key register */
#define OSCCA_SAFO_SGI_KEY0D_KEY0D(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_KEY0D_KEY0D_SHIFT)) & OSCCA_SAFO_SGI_KEY0D_KEY0D_MASK)
/*! @} */

/*! @name SAFO_SGI_KEY1A - Input Key register 1 lower-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_KEY1A_KEY1A_MASK          (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_KEY1A_KEY1A_SHIFT         (0U)
/*! KEY1A - Input Key register */
#define OSCCA_SAFO_SGI_KEY1A_KEY1A(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_KEY1A_KEY1A_SHIFT)) & OSCCA_SAFO_SGI_KEY1A_KEY1A_MASK)
/*! @} */

/*! @name SAFO_SGI_KEY1B - Input Key register 1 lower-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_KEY1B_KEY1B_MASK          (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_KEY1B_KEY1B_SHIFT         (0U)
/*! KEY1B - Input Key register */
#define OSCCA_SAFO_SGI_KEY1B_KEY1B(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_KEY1B_KEY1B_SHIFT)) & OSCCA_SAFO_SGI_KEY1B_KEY1B_MASK)
/*! @} */

/*! @name SAFO_SGI_KEY1C - Input Key register 1 upper-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_KEY1C_KEY1C_MASK          (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_KEY1C_KEY1C_SHIFT         (0U)
/*! KEY1C - Input Key register */
#define OSCCA_SAFO_SGI_KEY1C_KEY1C(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_KEY1C_KEY1C_SHIFT)) & OSCCA_SAFO_SGI_KEY1C_KEY1C_MASK)
/*! @} */

/*! @name SAFO_SGI_KEY1D - Input Key register 1 upper-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_KEY1D_KEY1D_MASK          (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_KEY1D_KEY1D_SHIFT         (0U)
/*! KEY1D - Input Key register */
#define OSCCA_SAFO_SGI_KEY1D_KEY1D(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_KEY1D_KEY1D_SHIFT)) & OSCCA_SAFO_SGI_KEY1D_KEY1D_MASK)
/*! @} */

/*! @name SAFO_SGI_DATOUTA - Output Data register lower-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_DATOUTA_DATOUTA_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATOUTA_DATOUTA_SHIFT     (0U)
/*! DATOUTA - Output Data register */
#define OSCCA_SAFO_SGI_DATOUTA_DATOUTA(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATOUTA_DATOUTA_SHIFT)) & OSCCA_SAFO_SGI_DATOUTA_DATOUTA_MASK)
/*! @} */

/*! @name SAFO_SGI_DATOUTB - Ouput Data register lower-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_DATOUTB_DATOUTB_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATOUTB_DATOUTB_SHIFT     (0U)
/*! DATOUTB - Ouput Data register */
#define OSCCA_SAFO_SGI_DATOUTB_DATOUTB(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATOUTB_DATOUTB_SHIFT)) & OSCCA_SAFO_SGI_DATOUTB_DATOUTB_MASK)
/*! @} */

/*! @name SAFO_SGI_DATOUTC - Ouput Data register upper-bank low */
/*! @{ */

#define OSCCA_SAFO_SGI_DATOUTC_DATOUTC_MASK      (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATOUTC_DATOUTC_SHIFT     (0U)
/*! DATOUTC - Ouput Data register */
#define OSCCA_SAFO_SGI_DATOUTC_DATOUTC(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATOUTC_DATOUTC_SHIFT)) & OSCCA_SAFO_SGI_DATOUTC_DATOUTC_MASK)
/*! @} */

/*! @name SAFO_SGI_DATOUTD - Output Data register upper-bank high */
/*! @{ */

#define OSCCA_SAFO_SGI_DATOUTD_DOUTD_MASK        (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_DATOUTD_DOUTD_SHIFT       (0U)
/*! DOUTD - Output Data register */
#define OSCCA_SAFO_SGI_DATOUTD_DOUTD(x)          (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_DATOUTD_DOUTD_SHIFT)) & OSCCA_SAFO_SGI_DATOUTD_DOUTD_MASK)
/*! @} */

/*! @name SAFO_SGI_STATUS - Status Register */
/*! @{ */

#define OSCCA_SAFO_SGI_STATUS_BUSY_MASK          (0x1U)
#define OSCCA_SAFO_SGI_STATUS_BUSY_SHIFT         (0U)
/*! BUSY - Busy Flag */
#define OSCCA_SAFO_SGI_STATUS_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_BUSY_SHIFT)) & OSCCA_SAFO_SGI_STATUS_BUSY_MASK)

#define OSCCA_SAFO_SGI_STATUS_OFLOW_MASK         (0x2U)
#define OSCCA_SAFO_SGI_STATUS_OFLOW_SHIFT        (1U)
/*! OFLOW - Overflow Flag */
#define OSCCA_SAFO_SGI_STATUS_OFLOW(x)           (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_OFLOW_SHIFT)) & OSCCA_SAFO_SGI_STATUS_OFLOW_MASK)

#define OSCCA_SAFO_SGI_STATUS_PRNG_RDY_MASK      (0x4U)
#define OSCCA_SAFO_SGI_STATUS_PRNG_RDY_SHIFT     (2U)
/*! PRNG_RDY - PRNG Ready */
#define OSCCA_SAFO_SGI_STATUS_PRNG_RDY(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_PRNG_RDY_SHIFT)) & OSCCA_SAFO_SGI_STATUS_PRNG_RDY_MASK)

#define OSCCA_SAFO_SGI_STATUS_ERROR_MASK         (0x38U)
#define OSCCA_SAFO_SGI_STATUS_ERROR_SHIFT        (3U)
/*! ERROR - Error Indicator */
#define OSCCA_SAFO_SGI_STATUS_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_ERROR_SHIFT)) & OSCCA_SAFO_SGI_STATUS_ERROR_MASK)

#define OSCCA_SAFO_SGI_STATUS_SM3_BUSY_MASK      (0x40U)
#define OSCCA_SAFO_SGI_STATUS_SM3_BUSY_SHIFT     (6U)
/*! SM3_BUSY - SM3 Busy Status Flag */
#define OSCCA_SAFO_SGI_STATUS_SM3_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_SM3_BUSY_SHIFT)) & OSCCA_SAFO_SGI_STATUS_SM3_BUSY_MASK)

#define OSCCA_SAFO_SGI_STATUS_IRQ_MASK           (0x80U)
#define OSCCA_SAFO_SGI_STATUS_IRQ_SHIFT          (7U)
/*! IRQ - Interrupt Status Flag */
#define OSCCA_SAFO_SGI_STATUS_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_IRQ_SHIFT)) & OSCCA_SAFO_SGI_STATUS_IRQ_MASK)

#define OSCCA_SAFO_SGI_STATUS_SM3_FIFO_FULL_MASK (0x100U)
#define OSCCA_SAFO_SGI_STATUS_SM3_FIFO_FULL_SHIFT (8U)
/*! SM3_FIFO_FULL - SM3 FIFO Full Indicator */
#define OSCCA_SAFO_SGI_STATUS_SM3_FIFO_FULL(x)   (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_SM3_FIFO_FULL_SHIFT)) & OSCCA_SAFO_SGI_STATUS_SM3_FIFO_FULL_MASK)

#define OSCCA_SAFO_SGI_STATUS_SM3_FIFO_LEVEL_MASK (0x7E00U)
#define OSCCA_SAFO_SGI_STATUS_SM3_FIFO_LEVEL_SHIFT (9U)
/*! SM3_FIFO_LEVEL - SM3 FIFO Level */
#define OSCCA_SAFO_SGI_STATUS_SM3_FIFO_LEVEL(x)  (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_SM3_FIFO_LEVEL_SHIFT)) & OSCCA_SAFO_SGI_STATUS_SM3_FIFO_LEVEL_MASK)

#define OSCCA_SAFO_SGI_STATUS_SM3_ERROR_MASK     (0x8000U)
#define OSCCA_SAFO_SGI_STATUS_SM3_ERROR_SHIFT    (15U)
/*! SM3_ERROR - SM3 ERROR */
#define OSCCA_SAFO_SGI_STATUS_SM3_ERROR(x)       (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_STATUS_SM3_ERROR_SHIFT)) & OSCCA_SAFO_SGI_STATUS_SM3_ERROR_MASK)
/*! @} */

/*! @name SAFO_SGI_COUNT - Calculation Counter */
/*! @{ */

#define OSCCA_SAFO_SGI_COUNT_COUNT_MASK          (0xFFFFU)
#define OSCCA_SAFO_SGI_COUNT_COUNT_SHIFT         (0U)
/*! COUNT - Calculation Counter */
#define OSCCA_SAFO_SGI_COUNT_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_COUNT_COUNT_SHIFT)) & OSCCA_SAFO_SGI_COUNT_COUNT_MASK)
/*! @} */

/*! @name SAFO_SGI_CTRL - SGI Control Register */
/*! @{ */

#define OSCCA_SAFO_SGI_CTRL_START_MASK           (0x1U)
#define OSCCA_SAFO_SGI_CTRL_START_SHIFT          (0U)
/*! START - Start Crypto Operation */
#define OSCCA_SAFO_SGI_CTRL_START(x)             (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_START_SHIFT)) & OSCCA_SAFO_SGI_CTRL_START_MASK)

#define OSCCA_SAFO_SGI_CTRL_DECRYPT_MASK         (0x2U)
#define OSCCA_SAFO_SGI_CTRL_DECRYPT_SHIFT        (1U)
/*! DECRYPT - Sets Cipher direction(SM4) */
#define OSCCA_SAFO_SGI_CTRL_DECRYPT(x)           (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_DECRYPT_SHIFT)) & OSCCA_SAFO_SGI_CTRL_DECRYPT_MASK)

#define OSCCA_SAFO_SGI_CTRL_CRYPTO_OP_MASK       (0x70U)
#define OSCCA_SAFO_SGI_CTRL_CRYPTO_OP_SHIFT      (4U)
/*! CRYPTO_OP - Crypto Operation Type */
#define OSCCA_SAFO_SGI_CTRL_CRYPTO_OP(x)         (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_CRYPTO_OP_SHIFT)) & OSCCA_SAFO_SGI_CTRL_CRYPTO_OP_MASK)

#define OSCCA_SAFO_SGI_CTRL_INSEL_MASK           (0x780U)
#define OSCCA_SAFO_SGI_CTRL_INSEL_SHIFT          (7U)
/*! INSEL - Kernel Input Configuration */
#define OSCCA_SAFO_SGI_CTRL_INSEL(x)             (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_INSEL_SHIFT)) & OSCCA_SAFO_SGI_CTRL_INSEL_MASK)

#define OSCCA_SAFO_SGI_CTRL_OUTSEL_MASK          (0x3800U)
#define OSCCA_SAFO_SGI_CTRL_OUTSEL_SHIFT         (11U)
/*! OUTSEL - Kernel Input Configuration */
#define OSCCA_SAFO_SGI_CTRL_OUTSEL(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_OUTSEL_SHIFT)) & OSCCA_SAFO_SGI_CTRL_OUTSEL_MASK)

#define OSCCA_SAFO_SGI_CTRL_DATOUT_RES_MASK      (0xC000U)
#define OSCCA_SAFO_SGI_CTRL_DATOUT_RES_SHIFT     (14U)
/*! DATOUT_RES - Kernels Data Out Options */
#define OSCCA_SAFO_SGI_CTRL_DATOUT_RES(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_DATOUT_RES_SHIFT)) & OSCCA_SAFO_SGI_CTRL_DATOUT_RES_MASK)

#define OSCCA_SAFO_SGI_CTRL_INKEYSEL_MASK        (0x1F00000U)
#define OSCCA_SAFO_SGI_CTRL_INKEYSEL_SHIFT       (20U)
/*! INKEYSEL - Input key selection */
#define OSCCA_SAFO_SGI_CTRL_INKEYSEL(x)          (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_INKEYSEL_SHIFT)) & OSCCA_SAFO_SGI_CTRL_INKEYSEL_MASK)

#define OSCCA_SAFO_SGI_CTRL_SM4_EN_MASK          (0x8000000U)
#define OSCCA_SAFO_SGI_CTRL_SM4_EN_SHIFT         (27U)
/*! SM4_EN - SM4 Kernel Enable */
#define OSCCA_SAFO_SGI_CTRL_SM4_EN(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_SM4_EN_SHIFT)) & OSCCA_SAFO_SGI_CTRL_SM4_EN_MASK)

#define OSCCA_SAFO_SGI_CTRL_SM4_NO_KL_MASK       (0x10000000U)
#define OSCCA_SAFO_SGI_CTRL_SM4_NO_KL_SHIFT      (28U)
/*! SM4_NO_KL - SM4 No Decryption Key Schedule */
#define OSCCA_SAFO_SGI_CTRL_SM4_NO_KL(x)         (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL_SM4_NO_KL_SHIFT)) & OSCCA_SAFO_SGI_CTRL_SM4_NO_KL_MASK)
/*! @} */

/*! @name SAFO_SGI_CTRL2 - SGI Control Register 2 */
/*! @{ */

#define OSCCA_SAFO_SGI_CTRL2_FLUSH_MASK          (0x1U)
#define OSCCA_SAFO_SGI_CTRL2_FLUSH_SHIFT         (0U)
/*! FLUSH - Start Full SGI Flush */
#define OSCCA_SAFO_SGI_CTRL2_FLUSH(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_FLUSH_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_FLUSH_MASK)

#define OSCCA_SAFO_SGI_CTRL2_KEY_FLUSH_MASK      (0x2U)
#define OSCCA_SAFO_SGI_CTRL2_KEY_FLUSH_SHIFT     (1U)
/*! KEY_FLUSH - Start KEY register-bank Flush */
#define OSCCA_SAFO_SGI_CTRL2_KEY_FLUSH(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_KEY_FLUSH_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_KEY_FLUSH_MASK)

#define OSCCA_SAFO_SGI_CTRL2_DATIN_FLUSH_MASK    (0x4U)
#define OSCCA_SAFO_SGI_CTRL2_DATIN_FLUSH_SHIFT   (2U)
/*! DATIN_FLUSH - Start DATIN register-bank Flush */
#define OSCCA_SAFO_SGI_CTRL2_DATIN_FLUSH(x)      (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_DATIN_FLUSH_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_DATIN_FLUSH_MASK)

#define OSCCA_SAFO_SGI_CTRL2_INCR_MASK           (0x8U)
#define OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT          (3U)
/*! INCR - Increment(Triggered by SFR write) */
#define OSCCA_SAFO_SGI_CTRL2_INCR(x)             (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_MASK)

#define OSCCA_SAFO_SGI_CTRL2_XORWR_MASK          (0x10U)
#define OSCCA_SAFO_SGI_CTRL2_XORWR_SHIFT         (4U)
/*! XORWR - Write-XOR control */
#define OSCCA_SAFO_SGI_CTRL2_XORWR(x)            (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_XORWR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_XORWR_MASK)

#define OSCCA_SAFO_SGI_CTRL2_FLUSHWR_MASK        (0x20U)
#define OSCCA_SAFO_SGI_CTRL2_FLUSHWR_SHIFT       (5U)
/*! FLUSHWR - Flush Write control */
#define OSCCA_SAFO_SGI_CTRL2_FLUSHWR(x)          (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_FLUSHWR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_FLUSHWR_MASK)

#define OSCCA_SAFO_SGI_CTRL2_INCR_CIN_MASK       (0x40U)
#define OSCCA_SAFO_SGI_CTRL2_INCR_CIN_SHIFT      (6U)
/*! INCR_CIN - Increment Carry-In control */
#define OSCCA_SAFO_SGI_CTRL2_INCR_CIN(x)         (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_CIN_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_CIN_MASK)

#define OSCCA_SAFO_SGI_CTRL2_KEYRES_MASK         (0x1F0000U)
#define OSCCA_SAFO_SGI_CTRL2_KEYRES_SHIFT        (16U)
/*! KEYRES - Selects key registers to be updated when RKEY=1 */
#define OSCCA_SAFO_SGI_CTRL2_KEYRES(x)           (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_KEYRES_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_KEYRES_MASK)

#define OSCCA_SAFO_SGI_CTRL2_RKEY_MASK           (0x200000U)
#define OSCCA_SAFO_SGI_CTRL2_RKEY_SHIFT          (21U)
/*! RKEY - Crypto result location */
#define OSCCA_SAFO_SGI_CTRL2_RKEY(x)             (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_RKEY_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_RKEY_MASK)

#define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK    (0x400000U)
#define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT   (22U)
/*! BYTES_ORDER - Byte order of regbank read/write data */
#define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER(x)      (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK)
/*! @} */

/*! @name SAFO_SGI_SM3_CTRL - SM3 Control Register */
/*! @{ */

#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_MODE_MASK    (0x2U)
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_MODE_SHIFT   (1U)
/*! SM3_MODE - SM3 mode normal or automatic */
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_MODE(x)      (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_CTRL_SM3_MODE_SHIFT)) & OSCCA_SAFO_SGI_SM3_CTRL_SM3_MODE_MASK)

#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_LOW_LIM_MASK (0xF0U)
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_LOW_LIM_SHIFT (4U)
/*! SM3_LOW_LIM - SM3 FIFO low limit */
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_LOW_LIM(x)   (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_CTRL_SM3_LOW_LIM_SHIFT)) & OSCCA_SAFO_SGI_SM3_CTRL_SM3_LOW_LIM_MASK)

#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_HIGH_LIM_MASK (0xF00U)
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_HIGH_LIM_SHIFT (8U)
/*! SM3_HIGH_LIM - SM3 FIFO high limit */
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_HIGH_LIM(x)  (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_CTRL_SM3_HIGH_LIM_SHIFT)) & OSCCA_SAFO_SGI_SM3_CTRL_SM3_HIGH_LIM_MASK)

#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_COUNT_EN_MASK (0x1000U)
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_COUNT_EN_SHIFT (12U)
/*! SM3_COUNT_EN - SM3 Calculation Counter Enable */
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_COUNT_EN(x)  (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_CTRL_SM3_COUNT_EN_SHIFT)) & OSCCA_SAFO_SGI_SM3_CTRL_SM3_COUNT_EN_MASK)

#define OSCCA_SAFO_SGI_SM3_CTRL_HASH_RELOAD_MASK (0x2000U)
#define OSCCA_SAFO_SGI_SM3_CTRL_HASH_RELOAD_SHIFT (13U)
/*! HASH_RELOAD - SM3 HASH reload */
#define OSCCA_SAFO_SGI_SM3_CTRL_HASH_RELOAD(x)   (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_CTRL_HASH_RELOAD_SHIFT)) & OSCCA_SAFO_SGI_SM3_CTRL_HASH_RELOAD_MASK)

#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_STOP_MASK    (0x4000U)
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_STOP_SHIFT   (14U)
/*! SM3_STOP - STOP SM3 AUTO mode */
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_STOP(x)      (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_CTRL_SM3_STOP_SHIFT)) & OSCCA_SAFO_SGI_SM3_CTRL_SM3_STOP_MASK)

#define OSCCA_SAFO_SGI_SM3_CTRL_NO_AUTO_INIT_MASK (0x8000U)
#define OSCCA_SAFO_SGI_SM3_CTRL_NO_AUTO_INIT_SHIFT (15U)
/*! NO_AUTO_INIT - SM3 no automatic HASH initialisation */
#define OSCCA_SAFO_SGI_SM3_CTRL_NO_AUTO_INIT(x)  (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_CTRL_NO_AUTO_INIT_SHIFT)) & OSCCA_SAFO_SGI_SM3_CTRL_NO_AUTO_INIT_MASK)

#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_EN_MASK      (0x10000U)
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_EN_SHIFT     (16U)
/*! SM3_EN - SM3 enable */
#define OSCCA_SAFO_SGI_SM3_CTRL_SM3_EN(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_CTRL_SM3_EN_SHIFT)) & OSCCA_SAFO_SGI_SM3_CTRL_SM3_EN_MASK)
/*! @} */

/*! @name SAFO_SGI_SM3_FIFO - SM3 FIFO Register */
/*! @{ */

#define OSCCA_SAFO_SGI_SM3_FIFO_FIFO_MASK        (0xFFFFFFFFU)
#define OSCCA_SAFO_SGI_SM3_FIFO_FIFO_SHIFT       (0U)
/*! FIFO - SM3 FIFO Register */
#define OSCCA_SAFO_SGI_SM3_FIFO_FIFO(x)          (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_SM3_FIFO_FIFO_SHIFT)) & OSCCA_SAFO_SGI_SM3_FIFO_FIFO_MASK)
/*! @} */

/*! @name SAFO_SGI_CONFIG - SGI Configuration Register */
/*! @{ */

#define OSCCA_SAFO_SGI_CONFIG_HAS_CMAC_MASK      (0x80U)
#define OSCCA_SAFO_SGI_CONFIG_HAS_CMAC_SHIFT     (7U)
/*! HAS_CMAC - Has CMAC */
#define OSCCA_SAFO_SGI_CONFIG_HAS_CMAC(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_CMAC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_CMAC_MASK)

#define OSCCA_SAFO_SGI_CONFIG_HAS_GFMUL_MASK     (0x100U)
#define OSCCA_SAFO_SGI_CONFIG_HAS_GFMUL_SHIFT    (8U)
/*! HAS_GFMUL - Has GFMUL */
#define OSCCA_SAFO_SGI_CONFIG_HAS_GFMUL(x)       (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_GFMUL_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_GFMUL_MASK)

#define OSCCA_SAFO_SGI_CONFIG_INTERNAL_PRNG_MASK (0x200U)
#define OSCCA_SAFO_SGI_CONFIG_INTERNAL_PRNG_SHIFT (9U)
/*! INTERNAL_PRNG - Has internal PRNG */
#define OSCCA_SAFO_SGI_CONFIG_INTERNAL_PRNG(x)   (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_INTERNAL_PRNG_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_INTERNAL_PRNG_MASK)

#define OSCCA_SAFO_SGI_CONFIG_KEY_DIGEST_MASK    (0x400U)
#define OSCCA_SAFO_SGI_CONFIG_KEY_DIGEST_SHIFT   (10U)
/*! KEY_DIGEST - Has key digest */
#define OSCCA_SAFO_SGI_CONFIG_KEY_DIGEST(x)      (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_KEY_DIGEST_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_KEY_DIGEST_MASK)

#define OSCCA_SAFO_SGI_CONFIG_FA_MASK            (0x2000U)
#define OSCCA_SAFO_SGI_CONFIG_FA_SHIFT           (13U)
/*! FA - Has FA protection */
#define OSCCA_SAFO_SGI_CONFIG_FA(x)              (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_FA_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_FA_MASK)

#define OSCCA_SAFO_SGI_CONFIG_BUS_WIDTH_MASK     (0x8000U)
#define OSCCA_SAFO_SGI_CONFIG_BUS_WIDTH_SHIFT    (15U)
/*! BUS_WIDTH - Bus width */
#define OSCCA_SAFO_SGI_CONFIG_BUS_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_BUS_WIDTH_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_BUS_WIDTH_MASK)

#define OSCCA_SAFO_SGI_CONFIG_NUM_DATIN_MASK     (0x30000U)
#define OSCCA_SAFO_SGI_CONFIG_NUM_DATIN_SHIFT    (16U)
/*! NUM_DATIN - Number DATIN */
#define OSCCA_SAFO_SGI_CONFIG_NUM_DATIN(x)       (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_NUM_DATIN_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_NUM_DATIN_MASK)

#define OSCCA_SAFO_SGI_CONFIG_NUM_KEY_MASK       (0x1C0000U)
#define OSCCA_SAFO_SGI_CONFIG_NUM_KEY_SHIFT      (18U)
/*! NUM_KEY - Number KEY */
#define OSCCA_SAFO_SGI_CONFIG_NUM_KEY(x)         (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_NUM_KEY_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_NUM_KEY_MASK)

#define OSCCA_SAFO_SGI_CONFIG_EDC_MASK           (0x200000U)
#define OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT          (21U)
/*! EDC - EDC enable */
#define OSCCA_SAFO_SGI_CONFIG_EDC(x)             (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_EDC_MASK)

#define OSCCA_SAFO_SGI_CONFIG_DUAL_SGI_MASK      (0x400000U)
#define OSCCA_SAFO_SGI_CONFIG_DUAL_SGI_SHIFT     (22U)
/*! DUAL_SGI - Has dual SGI */
#define OSCCA_SAFO_SGI_CONFIG_DUAL_SGI(x)        (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_DUAL_SGI_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_DUAL_SGI_MASK)

#define OSCCA_SAFO_SGI_CONFIG_SHA_256_ONLY_MASK  (0x1000000U)
#define OSCCA_SAFO_SGI_CONFIG_SHA_256_ONLY_SHIFT (24U)
/*! SHA_256_ONLY - Has SHA 256 only */
#define OSCCA_SAFO_SGI_CONFIG_SHA_256_ONLY(x)    (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_SHA_256_ONLY_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_SHA_256_ONLY_MASK)

#define OSCCA_SAFO_SGI_CONFIG_SPB_SUPPORT_MASK   (0x2000000U)
#define OSCCA_SAFO_SGI_CONFIG_SPB_SUPPORT_SHIFT  (25U)
/*! SPB_SUPPORT - ID_CFG_SPB_SUPPORT is set */
#define OSCCA_SAFO_SGI_CONFIG_SPB_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_SPB_SUPPORT_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_SPB_SUPPORT_MASK)

#define OSCCA_SAFO_SGI_CONFIG_SPB_MASKING_MASK   (0x4000000U)
#define OSCCA_SAFO_SGI_CONFIG_SPB_MASKING_SHIFT  (26U)
/*! SPB_MASKING - ID_CFG_SAFO_SGI_SPB_MASKING is set */
#define OSCCA_SAFO_SGI_CONFIG_SPB_MASKING(x)     (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_SPB_MASKING_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_SPB_MASKING_MASK)

#define OSCCA_SAFO_SGI_CONFIG_SFR_SW_MASK_MASK   (0x8000000U)
#define OSCCA_SAFO_SGI_CONFIG_SFR_SW_MASK_SHIFT  (27U)
/*! SFR_SW_MASK - ID_CFG_SAFO_SGI_USE_SFR_SW_MASK is set */
#define OSCCA_SAFO_SGI_CONFIG_SFR_SW_MASK(x)     (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_SFR_SW_MASK_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_SFR_SW_MASK_MASK)

#define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK       (0x10000000U)
#define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT      (28U)
/*! HAS_SM3 - Has SM3 */
#define OSCCA_SAFO_SGI_CONFIG_HAS_SM3(x)         (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK)

#define OSCCA_SAFO_SGI_CONFIG_HAS_SM4_MASK       (0x20000000U)
#define OSCCA_SAFO_SGI_CONFIG_HAS_SM4_SHIFT      (29U)
/*! HAS_SM4 - Has SM4 */
#define OSCCA_SAFO_SGI_CONFIG_HAS_SM4(x)         (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM4_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM4_MASK)
/*! @} */

/*! @name SAFO_SGI_INT_ENABLE - Interrupt Enable */
/*! @{ */

#define OSCCA_SAFO_SGI_INT_ENABLE_INT_EN_MASK    (0x1U)
#define OSCCA_SAFO_SGI_INT_ENABLE_INT_EN_SHIFT   (0U)
/*! INT_EN - Interrupt enable bit */
#define OSCCA_SAFO_SGI_INT_ENABLE_INT_EN(x)      (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_INT_ENABLE_INT_EN_SHIFT)) & OSCCA_SAFO_SGI_INT_ENABLE_INT_EN_MASK)
/*! @} */

/*! @name SAFO_SGI_INT_STATUS_CLR - Interrupt Status Clear */
/*! @{ */

#define OSCCA_SAFO_SGI_INT_STATUS_CLR_INT_CLR_MASK (0x1U)
#define OSCCA_SAFO_SGI_INT_STATUS_CLR_INT_CLR_SHIFT (0U)
/*! INT_CLR - Interrupt Status Clear */
#define OSCCA_SAFO_SGI_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_INT_STATUS_CLR_INT_CLR_SHIFT)) & OSCCA_SAFO_SGI_INT_STATUS_CLR_INT_CLR_MASK)
/*! @} */

/*! @name SAFO_SGI_INT_STATUS_SET - Interrupt Status Set */
/*! @{ */

#define OSCCA_SAFO_SGI_INT_STATUS_SET_INT_SET_MASK (0x1U)
#define OSCCA_SAFO_SGI_INT_STATUS_SET_INT_SET_SHIFT (0U)
/*! INT_SET - Set Interrupt by SW */
#define OSCCA_SAFO_SGI_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_INT_STATUS_SET_INT_SET_SHIFT)) & OSCCA_SAFO_SGI_INT_STATUS_SET_INT_SET_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group OSCCA_Register_Masks */


/* OSCCA - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral OSCCA base address */
  #define OSCCA_BASE                               (0x5001A000u)
  /** Peripheral OSCCA base address */
  #define OSCCA_BASE_NS                            (0x4001A000u)
  /** Peripheral OSCCA base pointer */
  #define OSCCA                                    ((OSCCA_Type *)OSCCA_BASE)
  /** Peripheral OSCCA base pointer */
  #define OSCCA_NS                                 ((OSCCA_Type *)OSCCA_BASE_NS)
  /** Array initializer of OSCCA peripheral base addresses */
  #define OSCCA_BASE_ADDRS                         { OSCCA_BASE }
  /** Array initializer of OSCCA peripheral base pointers */
  #define OSCCA_BASE_PTRS                          { OSCCA }
  /** Array initializer of OSCCA peripheral base addresses */
  #define OSCCA_BASE_ADDRS_NS                      { OSCCA_BASE_NS }
  /** Array initializer of OSCCA peripheral base pointers */
  #define OSCCA_BASE_PTRS_NS                       { OSCCA_NS }
#else
  /** Peripheral OSCCA base address */
  #define OSCCA_BASE                               (0x4001A000u)
  /** Peripheral OSCCA base pointer */
  #define OSCCA                                    ((OSCCA_Type *)OSCCA_BASE)
  /** Array initializer of OSCCA peripheral base addresses */
  #define OSCCA_BASE_ADDRS                         { OSCCA_BASE }
  /** Array initializer of OSCCA peripheral base pointers */
  #define OSCCA_BASE_PTRS                          { OSCCA }
#endif

/*!
 * @}
 */ /* end of group OSCCA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OSTIMER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
 * @{
 */

/** OSTIMER - Register Layout Typedef */
typedef struct {
  __I  uint32_t EVTIMERL;                          /**< EVTIMER Low, offset: 0x0 */
  __I  uint32_t EVTIMERH;                          /**< EVTIMER High, offset: 0x4 */
  __I  uint32_t CAPTURE_L;                         /**< Local Capture Low for CPU, offset: 0x8 */
  __I  uint32_t CAPTURE_H;                         /**< Local Capture High for CPU, offset: 0xC */
  __IO uint32_t MATCH_L;                           /**< Local Match Low for CPU, offset: 0x10 */
  __IO uint32_t MATCH_H;                           /**< Local Match High for CPU, offset: 0x14 */
       uint8_t RESERVED_0[4];
  __IO uint32_t OSEVENT_CTRL;                      /**< OSTIMER Control for CPU, offset: 0x1C */
} OSTIMER_Type;

/* ----------------------------------------------------------------------------
   -- OSTIMER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
 * @{
 */

/*! @name EVTIMERL - EVTIMER Low */
/*! @{ */

#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
/*! @} */

/*! @name EVTIMERH - EVTIMER High */
/*! @{ */

#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
/*! @} */

/*! @name CAPTURE_L - Local Capture Low for CPU */
/*! @{ */

#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT    (0U)
/*! CAPTURE_VALUE - EVTimer Capture Value */
#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
/*! @} */

/*! @name CAPTURE_H - Local Capture High for CPU */
/*! @{ */

#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT    (0U)
/*! CAPTURE_VALUE - EVTimer Capture Value */
#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
/*! @} */

/*! @name MATCH_L - Local Match Low for CPU */
/*! @{ */

#define OSTIMER_MATCH_L_MATCH_VALUE_MASK         (0xFFFFFFFFU)
#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT        (0U)
/*! MATCH_VALUE - EVTimer Match Value */
#define OSTIMER_MATCH_L_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
/*! @} */

/*! @name MATCH_H - Local Match High for CPU */
/*! @{ */

#define OSTIMER_MATCH_H_MATCH_VALUE_MASK         (0xFFFFFFFFU)
#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT        (0U)
/*! MATCH_VALUE - EVTimer Match Value */
#define OSTIMER_MATCH_H_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
/*! @} */

/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */
/*! @{ */

#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
/*! OSTIMER_INTRFLAG - Interrupt Flag */
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)

#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
/*! OSTIMER_INTENA - Interrupt or Wake-Up Request
 *  0b0..Interrupts blocked
 *  0b1..Interrupts enabled
 */
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x)   (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)

#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK   (0x4U)
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT  (2U)
/*! MATCH_WR_RDY - EVTimer Match Write Ready */
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x)     (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)

#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK       (0x8U)
#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT      (3U)
/*! DEBUG_EN - Debug Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define OSTIMER_OSEVENT_CTRL_DEBUG_EN(x)         (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT)) & OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group OSTIMER_Register_Masks */


/* OSTIMER - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral OSTIMER_HIFI4 base address */
  #define OSTIMER_HIFI4_BASE                       (0x50208000u)
  /** Peripheral OSTIMER_HIFI4 base address */
  #define OSTIMER_HIFI4_BASE_NS                    (0x40208000u)
  /** Peripheral OSTIMER_HIFI4 base pointer */
  #define OSTIMER_HIFI4                            ((OSTIMER_Type *)OSTIMER_HIFI4_BASE)
  /** Peripheral OSTIMER_HIFI4 base pointer */
  #define OSTIMER_HIFI4_NS                         ((OSTIMER_Type *)OSTIMER_HIFI4_BASE_NS)
  /** Array initializer of OSTIMER peripheral base addresses */
  #define OSTIMER_BASE_ADDRS                       { OSTIMER_HIFI4_BASE }
  /** Array initializer of OSTIMER peripheral base pointers */
  #define OSTIMER_BASE_PTRS                        { OSTIMER_HIFI4 }
  /** Array initializer of OSTIMER peripheral base addresses */
  #define OSTIMER_BASE_ADDRS_NS                    { OSTIMER_HIFI4_BASE_NS }
  /** Array initializer of OSTIMER peripheral base pointers */
  #define OSTIMER_BASE_PTRS_NS                     { OSTIMER_HIFI4_NS }
#else
  /** Peripheral OSTIMER_HIFI4 base address */
  #define OSTIMER_HIFI4_BASE                       (0x40208000u)
  /** Peripheral OSTIMER_HIFI4 base pointer */
  #define OSTIMER_HIFI4                            ((OSTIMER_Type *)OSTIMER_HIFI4_BASE)
  /** Array initializer of OSTIMER peripheral base addresses */
  #define OSTIMER_BASE_ADDRS                       { OSTIMER_HIFI4_BASE }
  /** Array initializer of OSTIMER peripheral base pointers */
  #define OSTIMER_BASE_PTRS                        { OSTIMER_HIFI4 }
#endif

/*!
 * @}
 */ /* end of group OSTIMER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PDM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
 * @{
 */

/** PDM - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL_1;                            /**< MICFIL Control 1, offset: 0x0 */
  __IO uint32_t CTRL_2;                            /**< MICFIL Control 2, offset: 0x4 */
  __IO uint32_t STAT;                              /**< MICFIL Status, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t FIFO_CTRL;                         /**< MICFIL FIFO Control, offset: 0x10 */
  __IO uint32_t FIFO_STAT;                         /**< MICFIL FIFO Status, offset: 0x14 */
       uint8_t RESERVED_1[12];
  __I  uint32_t DATACH[8];                         /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */
       uint8_t RESERVED_2[32];
  __I  uint32_t DC_CTRL;                           /**< MICFIL DC Remover Control, offset: 0x64 */
  __IO uint32_t DC_OUT_CTRL;                       /**< MICFIL Output DC Remover Control, offset: 0x68 */
       uint8_t RESERVED_3[8];
  __IO uint32_t RANGE_CTRL;                        /**< MICFIL Range Control, offset: 0x74 */
       uint8_t RESERVED_4[4];
  __IO uint32_t RANGE_STAT;                        /**< MICFIL Range Status, offset: 0x7C */
  __IO uint32_t FSYNC_CTRL;                        /**< Frame Synchronization Control, offset: 0x80 */
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x84 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x88 */
       uint8_t RESERVED_5[4];
  __IO uint32_t VAD0_CTRL_1;                       /**< Voice Activity Detector 0 Control, offset: 0x90 */
  __IO uint32_t VAD0_CTRL_2;                       /**< Voice Activity Detector 0 Control, offset: 0x94 */
  __IO uint32_t VAD0_STAT;                         /**< Voice Activity Detector 0 Status, offset: 0x98 */
  __IO uint32_t VAD0_SCONFIG;                      /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */
  __IO uint32_t VAD0_NCONFIG;                      /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */
  __I  uint32_t VAD0_NDATA;                        /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */
  __IO uint32_t VAD0_ZCD;                          /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */
} PDM_Type;

/* ----------------------------------------------------------------------------
   -- PDM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PDM_Register_Masks PDM Register Masks
 * @{
 */

/*! @name CTRL_1 - MICFIL Control 1 */
/*! @{ */

#define PDM_CTRL_1_CH0EN_MASK                    (0x1U)
#define PDM_CTRL_1_CH0EN_SHIFT                   (0U)
/*! CH0EN - Channel 0 Enable */
#define PDM_CTRL_1_CH0EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)

#define PDM_CTRL_1_CH1EN_MASK                    (0x2U)
#define PDM_CTRL_1_CH1EN_SHIFT                   (1U)
/*! CH1EN - Channel 1 Enable */
#define PDM_CTRL_1_CH1EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)

#define PDM_CTRL_1_CH2EN_MASK                    (0x4U)
#define PDM_CTRL_1_CH2EN_SHIFT                   (2U)
/*! CH2EN - Channel 2 Enable */
#define PDM_CTRL_1_CH2EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)

#define PDM_CTRL_1_CH3EN_MASK                    (0x8U)
#define PDM_CTRL_1_CH3EN_SHIFT                   (3U)
/*! CH3EN - Channel 3 Enable */
#define PDM_CTRL_1_CH3EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)

#define PDM_CTRL_1_CH4EN_MASK                    (0x10U)
#define PDM_CTRL_1_CH4EN_SHIFT                   (4U)
/*! CH4EN - Channel 4 Enable */
#define PDM_CTRL_1_CH4EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)

#define PDM_CTRL_1_CH5EN_MASK                    (0x20U)
#define PDM_CTRL_1_CH5EN_SHIFT                   (5U)
/*! CH5EN - Channel 5 Enable */
#define PDM_CTRL_1_CH5EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)

#define PDM_CTRL_1_CH6EN_MASK                    (0x40U)
#define PDM_CTRL_1_CH6EN_SHIFT                   (6U)
/*! CH6EN - Channel 6 Enable */
#define PDM_CTRL_1_CH6EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)

#define PDM_CTRL_1_CH7EN_MASK                    (0x80U)
#define PDM_CTRL_1_CH7EN_SHIFT                   (7U)
/*! CH7EN - Channel 7 Enable */
#define PDM_CTRL_1_CH7EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)

#define PDM_CTRL_1_FSYNCEN_MASK                  (0x10000U)
#define PDM_CTRL_1_FSYNCEN_SHIFT                 (16U)
/*! FSYNCEN - Frame Synchronization Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_CTRL_1_FSYNCEN(x)                    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK)

#define PDM_CTRL_1_DECFILS_MASK                  (0x100000U)
#define PDM_CTRL_1_DECFILS_SHIFT                 (20U)
/*! DECFILS - Decimation Filter Enable in Stop
 *  0b0..Stops decimation filter
 *  0b1..Keeps decimation filter running
 */
#define PDM_CTRL_1_DECFILS(x)                    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK)

#define PDM_CTRL_1_ERREN_MASK                    (0x800000U)
#define PDM_CTRL_1_ERREN_SHIFT                   (23U)
/*! ERREN - Error Interruption Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_CTRL_1_ERREN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)

#define PDM_CTRL_1_DISEL_MASK                    (0x3000000U)
#define PDM_CTRL_1_DISEL_SHIFT                   (24U)
/*! DISEL - DMA Interrupt Selection
 *  0b00..Disables DMA and interrupt requests
 *  0b01..Enables DMA requests
 *  0b10..Enables interrupt requests
 *  0b11..Reserved
 */
#define PDM_CTRL_1_DISEL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)

#define PDM_CTRL_1_DBGE_MASK                     (0x4000000U)
#define PDM_CTRL_1_DBGE_SHIFT                    (26U)
/*! DBGE - Module Enable in Debug
 *  0b0..Disables after completing the current frame
 *  0b1..Enables operation
 */
#define PDM_CTRL_1_DBGE(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)

#define PDM_CTRL_1_SRES_MASK                     (0x8000000U)
#define PDM_CTRL_1_SRES_SHIFT                    (27U)
/*! SRES - Software Reset
 *  0b0..No action
 *  0b1..Software reset
 */
#define PDM_CTRL_1_SRES(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)

#define PDM_CTRL_1_DBG_MASK                      (0x10000000U)
#define PDM_CTRL_1_DBG_SHIFT                     (28U)
/*! DBG - Debug Mode
 *  0b0..Normal
 *  0b1..Debug
 */
#define PDM_CTRL_1_DBG(x)                        (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)

#define PDM_CTRL_1_PDMIEN_MASK                   (0x20000000U)
#define PDM_CTRL_1_PDMIEN_SHIFT                  (29U)
/*! PDMIEN - MICFIL Enable
 *  0b0..Stops MICFIL operation
 *  0b1..Starts MICFIL operation
 */
#define PDM_CTRL_1_PDMIEN(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)

#define PDM_CTRL_1_DOZEN_MASK                    (0x40000000U)
#define PDM_CTRL_1_DOZEN_SHIFT                   (30U)
/*! DOZEN - Stop Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_CTRL_1_DOZEN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)

#define PDM_CTRL_1_MDIS_MASK                     (0x80000000U)
#define PDM_CTRL_1_MDIS_SHIFT                    (31U)
/*! MDIS - Module Disable
 *  0b0..Normal mode
 *  0b1..DLL mode
 */
#define PDM_CTRL_1_MDIS(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
/*! @} */

/*! @name CTRL_2 - MICFIL Control 2 */
/*! @{ */

#define PDM_CTRL_2_CLKDIV_MASK                   (0xFFU)
#define PDM_CTRL_2_CLKDIV_SHIFT                  (0U)
/*! CLKDIV - Clock Divider
 *  0b00000000..Internal clock divider value = 0
 *  0b00000001..Internal clock divider value = 1
 *  0b00000010-0b11111110.....
 *  0b11111111..Internal clock divider value = 255
 */
#define PDM_CTRL_2_CLKDIV(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)

#define PDM_CTRL_2_CLKDIVDIS_MASK                (0x8000U)
#define PDM_CTRL_2_CLKDIVDIS_SHIFT               (15U)
/*! CLKDIVDIS - Clock Divider Disable
 *  0b0..Enables
 *  0b1..Disables
 */
#define PDM_CTRL_2_CLKDIVDIS(x)                  (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIVDIS_SHIFT)) & PDM_CTRL_2_CLKDIVDIS_MASK)

#define PDM_CTRL_2_CICOSR_MASK                   (0x1F0000U)
#define PDM_CTRL_2_CICOSR_SHIFT                  (16U)
/*! CICOSR - CIC Decimation Rate
 *  0b00000-0b00111..Not supported
 *  0b01000..CIC oversampling rate = 8
 *  0b01001..CIC oversampling rate = 9
 *  0b01010-0b11110.....
 *  0b11111..CIC oversampling rate = 31
 */
#define PDM_CTRL_2_CICOSR(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)

#define PDM_CTRL_2_QSEL_MASK                     (0xE000000U)
#define PDM_CTRL_2_QSEL_SHIFT                    (25U)
/*! QSEL - Quality Mode
 *  0b001..High-Quality mode
 *  0b000..Medium-Quality mode
 *  0b111..Low-Quality mode
 *  0b110..Very-Low-Quality 0 mode
 *  0b101..Very-Low-Quality 1 mode
 *  0b100..Very-Low-Quality 2 mode
 */
#define PDM_CTRL_2_QSEL(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)

#define PDM_CTRL_2_DEC_BYPASS_MASK               (0x80000000U)
#define PDM_CTRL_2_DEC_BYPASS_SHIFT              (31U)
/*! DEC_BYPASS - Decimation Filter Bypass
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_CTRL_2_DEC_BYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_DEC_BYPASS_SHIFT)) & PDM_CTRL_2_DEC_BYPASS_MASK)
/*! @} */

/*! @name STAT - MICFIL Status */
/*! @{ */

#define PDM_STAT_CH0F_MASK                       (0x1U)
#define PDM_STAT_CH0F_SHIFT                      (0U)
/*! CH0F - Channel 0 Output Data Flag
 *  0b0..Not surpassed
 *  0b1..Surpassed
 */
#define PDM_STAT_CH0F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)

#define PDM_STAT_CH1F_MASK                       (0x2U)
#define PDM_STAT_CH1F_SHIFT                      (1U)
/*! CH1F - Channel 1 Output Data Flag
 *  0b0..Not surpassed
 *  0b1..Surpassed
 */
#define PDM_STAT_CH1F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)

#define PDM_STAT_CH2F_MASK                       (0x4U)
#define PDM_STAT_CH2F_SHIFT                      (2U)
/*! CH2F - Channel 2 Output Data Flag
 *  0b0..Not surpassed
 *  0b1..Surpassed
 */
#define PDM_STAT_CH2F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)

#define PDM_STAT_CH3F_MASK                       (0x8U)
#define PDM_STAT_CH3F_SHIFT                      (3U)
/*! CH3F - Channel 3 Output Data Flag
 *  0b0..Not surpassed
 *  0b1..Surpassed
 */
#define PDM_STAT_CH3F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)

#define PDM_STAT_CH4F_MASK                       (0x10U)
#define PDM_STAT_CH4F_SHIFT                      (4U)
/*! CH4F - Channel 4 Output Data Flag
 *  0b0..Not surpassed
 *  0b1..Surpassed
 */
#define PDM_STAT_CH4F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)

#define PDM_STAT_CH5F_MASK                       (0x20U)
#define PDM_STAT_CH5F_SHIFT                      (5U)
/*! CH5F - Channel 5 Output Data Flag
 *  0b0..Not surpassed
 *  0b1..Surpassed
 */
#define PDM_STAT_CH5F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)

#define PDM_STAT_CH6F_MASK                       (0x40U)
#define PDM_STAT_CH6F_SHIFT                      (6U)
/*! CH6F - Channel 6 Output Data Flag
 *  0b0..Not surpassed
 *  0b1..Surpassed
 */
#define PDM_STAT_CH6F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)

#define PDM_STAT_CH7F_MASK                       (0x80U)
#define PDM_STAT_CH7F_SHIFT                      (7U)
/*! CH7F - Channel 7 Output Data Flag
 *  0b0..Not surpassed
 *  0b1..Surpassed
 */
#define PDM_STAT_CH7F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)

#define PDM_STAT_BSY_FIL_MASK                    (0x80000000U)
#define PDM_STAT_BSY_FIL_SHIFT                   (31U)
/*! BSY_FIL - Busy Flag
 *  0b1..MICFIL is running
 *  0b0..MICFIL is stopped
 */
#define PDM_STAT_BSY_FIL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
/*! @} */

/*! @name FIFO_CTRL - MICFIL FIFO Control */
/*! @{ */

#define PDM_FIFO_CTRL_FIFOWMK_MASK               (0x7U)
#define PDM_FIFO_CTRL_FIFOWMK_SHIFT              (0U)
/*! FIFOWMK - FIFO Watermark Control */
#define PDM_FIFO_CTRL_FIFOWMK(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/*! @} */

/*! @name FIFO_STAT - MICFIL FIFO Status */
/*! @{ */

#define PDM_FIFO_STAT_FIFOOVF0_MASK              (0x1U)
#define PDM_FIFO_STAT_FIFOOVF0_SHIFT             (0U)
/*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)

#define PDM_FIFO_STAT_FIFOOVF1_MASK              (0x2U)
#define PDM_FIFO_STAT_FIFOOVF1_SHIFT             (1U)
/*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)

#define PDM_FIFO_STAT_FIFOOVF2_MASK              (0x4U)
#define PDM_FIFO_STAT_FIFOOVF2_SHIFT             (2U)
/*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)

#define PDM_FIFO_STAT_FIFOOVF3_MASK              (0x8U)
#define PDM_FIFO_STAT_FIFOOVF3_SHIFT             (3U)
/*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)

#define PDM_FIFO_STAT_FIFOOVF4_MASK              (0x10U)
#define PDM_FIFO_STAT_FIFOOVF4_SHIFT             (4U)
/*! FIFOOVF4 - FIFO Overflow Exception Flag for Channel 4
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)

#define PDM_FIFO_STAT_FIFOOVF5_MASK              (0x20U)
#define PDM_FIFO_STAT_FIFOOVF5_SHIFT             (5U)
/*! FIFOOVF5 - FIFO Overflow Exception Flag for Channel 5
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)

#define PDM_FIFO_STAT_FIFOOVF6_MASK              (0x40U)
#define PDM_FIFO_STAT_FIFOOVF6_SHIFT             (6U)
/*! FIFOOVF6 - FIFO Overflow Exception Flag for Channel 6
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)

#define PDM_FIFO_STAT_FIFOOVF7_MASK              (0x80U)
#define PDM_FIFO_STAT_FIFOOVF7_SHIFT             (7U)
/*! FIFOOVF7 - FIFO Overflow Exception Flag for Channel 7
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)

#define PDM_FIFO_STAT_FIFOUND0_MASK              (0x100U)
#define PDM_FIFO_STAT_FIFOUND0_SHIFT             (8U)
/*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0
 *  0b0..No exception by FIFO underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)

#define PDM_FIFO_STAT_FIFOUND1_MASK              (0x200U)
#define PDM_FIFO_STAT_FIFOUND1_SHIFT             (9U)
/*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1
 *  0b0..No exception by FIFO underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)

#define PDM_FIFO_STAT_FIFOUND2_MASK              (0x400U)
#define PDM_FIFO_STAT_FIFOUND2_SHIFT             (10U)
/*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2
 *  0b0..No exception by FIFO underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)

#define PDM_FIFO_STAT_FIFOUND3_MASK              (0x800U)
#define PDM_FIFO_STAT_FIFOUND3_SHIFT             (11U)
/*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3
 *  0b0..No exception by FIFO underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)

#define PDM_FIFO_STAT_FIFOUND4_MASK              (0x1000U)
#define PDM_FIFO_STAT_FIFOUND4_SHIFT             (12U)
/*! FIFOUND4 - FIFO Underflow Exception Flag for Channel 4
 *  0b0..No exception by FIFO underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)

#define PDM_FIFO_STAT_FIFOUND5_MASK              (0x2000U)
#define PDM_FIFO_STAT_FIFOUND5_SHIFT             (13U)
/*! FIFOUND5 - FIFO Underflow Exception Flag for Channel 5
 *  0b0..No exception by FIFO underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)

#define PDM_FIFO_STAT_FIFOUND6_MASK              (0x4000U)
#define PDM_FIFO_STAT_FIFOUND6_SHIFT             (14U)
/*! FIFOUND6 - FIFO Underflow Exception Flag for Channel 6
 *  0b0..No exception by FIFO underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)

#define PDM_FIFO_STAT_FIFOUND7_MASK              (0x8000U)
#define PDM_FIFO_STAT_FIFOUND7_SHIFT             (15U)
/*! FIFOUND7 - FIFO Underflow Exception Flag for Channel 7
 *  0b0..No exception by FIFO underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
/*! @} */

/*! @name DATACH - MICFIL Output Result */
/*! @{ */

#define PDM_DATACH_DATA_MASK                     (0xFFFFFFFFU)
#define PDM_DATACH_DATA_SHIFT                    (0U)
/*! DATA - Channel n Data */
#define PDM_DATACH_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
/*! @} */

/* The count of PDM_DATACH */
#define PDM_DATACH_COUNT                         (8U)

/*! @name DC_CTRL - MICFIL DC Remover Control */
/*! @{ */

#define PDM_DC_CTRL_DCCONFIG0_MASK               (0x3U)
#define PDM_DC_CTRL_DCCONFIG0_SHIFT              (0U)
/*! DCCONFIG0 - Channel 0 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
 *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
 *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
 */
#define PDM_DC_CTRL_DCCONFIG0(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)

#define PDM_DC_CTRL_DCCONFIG1_MASK               (0xCU)
#define PDM_DC_CTRL_DCCONFIG1_SHIFT              (2U)
/*! DCCONFIG1 - Channel 1 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
 *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
 *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
 */
#define PDM_DC_CTRL_DCCONFIG1(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)

#define PDM_DC_CTRL_DCCONFIG2_MASK               (0x30U)
#define PDM_DC_CTRL_DCCONFIG2_SHIFT              (4U)
/*! DCCONFIG2 - Channel 2 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
 *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
 *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
 */
#define PDM_DC_CTRL_DCCONFIG2(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)

#define PDM_DC_CTRL_DCCONFIG3_MASK               (0xC0U)
#define PDM_DC_CTRL_DCCONFIG3_SHIFT              (6U)
/*! DCCONFIG3 - Channel 3 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
 *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
 *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
 */
#define PDM_DC_CTRL_DCCONFIG3(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)

#define PDM_DC_CTRL_DCCONFIG4_MASK               (0x300U)
#define PDM_DC_CTRL_DCCONFIG4_SHIFT              (8U)
/*! DCCONFIG4 - Channel 4 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
 *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
 *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
 */
#define PDM_DC_CTRL_DCCONFIG4(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)

#define PDM_DC_CTRL_DCCONFIG5_MASK               (0xC00U)
#define PDM_DC_CTRL_DCCONFIG5_SHIFT              (10U)
/*! DCCONFIG5 - Channel 5 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
 *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
 *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
 */
#define PDM_DC_CTRL_DCCONFIG5(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)

#define PDM_DC_CTRL_DCCONFIG6_MASK               (0x3000U)
#define PDM_DC_CTRL_DCCONFIG6_SHIFT              (12U)
/*! DCCONFIG6 - Channel 6 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
 *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
 *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
 */
#define PDM_DC_CTRL_DCCONFIG6(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)

#define PDM_DC_CTRL_DCCONFIG7_MASK               (0xC000U)
#define PDM_DC_CTRL_DCCONFIG7_SHIFT              (14U)
/*! DCCONFIG7 - Channel 7 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
 *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
 *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
 */
#define PDM_DC_CTRL_DCCONFIG7(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
/*! @} */

/*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */
/*! @{ */

#define PDM_DC_OUT_CTRL_DCCONFIG0_MASK           (0x3U)
#define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT          (0U)
/*! DCCONFIG0 - Channel 0 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (FS = 48 kHz)
 *  0b01..13.3 Hz (FS = 48 kHz)
 *  0b10..40 Hz (FS = 48 kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG0(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG1_MASK           (0xCU)
#define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT          (2U)
/*! DCCONFIG1 - Channel 1 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (FS = 48 kHz)
 *  0b01..13.3 Hz (FS = 48 kHz)
 *  0b10..40 Hz (FS = 48 kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG1(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG2_MASK           (0x30U)
#define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT          (4U)
/*! DCCONFIG2 - Channel 2 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (FS = 48 kHz)
 *  0b01..13.3 Hz (FS = 48 kHz)
 *  0b10..40 Hz (FS = 48 kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG2(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG3_MASK           (0xC0U)
#define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT          (6U)
/*! DCCONFIG3 - Channel 3 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (FS = 48 kHz)
 *  0b01..13.3 Hz (FS = 48 kHz)
 *  0b10..40 Hz (FS = 48 kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG3(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG4_MASK           (0x300U)
#define PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT          (8U)
/*! DCCONFIG4 - Channel 4 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (FS = 48 kHz)
 *  0b01..13.3 Hz (FS = 48 kHz)
 *  0b10..40 Hz (FS = 48 kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG4(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG4_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG5_MASK           (0xC00U)
#define PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT          (10U)
/*! DCCONFIG5 - Channel 5 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (FS = 48 kHz)
 *  0b01..13.3 Hz (FS = 48 kHz)
 *  0b10..40 Hz (FS = 48 kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG5(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG5_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG6_MASK           (0x3000U)
#define PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT          (12U)
/*! DCCONFIG6 - Channel 6 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (FS = 48 kHz)
 *  0b01..13.3 Hz (FS = 48 kHz)
 *  0b10..40 Hz (FS = 48 kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG6(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG6_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG7_MASK           (0xC000U)
#define PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT          (14U)
/*! DCCONFIG7 - Channel 7 DC Remover Configuration
 *  0b11..DC remover is bypassed
 *  0b00..20 Hz (FS = 48 kHz)
 *  0b01..13.3 Hz (FS = 48 kHz)
 *  0b10..40 Hz (FS = 48 kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG7(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG7_MASK)
/*! @} */

/*! @name RANGE_CTRL - MICFIL Range Control */
/*! @{ */

#define PDM_RANGE_CTRL_RANGEADJ0_MASK            (0xFU)
#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT           (0U)
/*! RANGEADJ0 - Channel 0 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)

#define PDM_RANGE_CTRL_RANGEADJ1_MASK            (0xF0U)
#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT           (4U)
/*! RANGEADJ1 - Channel 1 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)

#define PDM_RANGE_CTRL_RANGEADJ2_MASK            (0xF00U)
#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT           (8U)
/*! RANGEADJ2 - Channel 2 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)

#define PDM_RANGE_CTRL_RANGEADJ3_MASK            (0xF000U)
#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT           (12U)
/*! RANGEADJ3 - Channel 3 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)

#define PDM_RANGE_CTRL_RANGEADJ4_MASK            (0xF0000U)
#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT           (16U)
/*! RANGEADJ4 - Channel 4 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)

#define PDM_RANGE_CTRL_RANGEADJ5_MASK            (0xF00000U)
#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT           (20U)
/*! RANGEADJ5 - Channel 5 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)

#define PDM_RANGE_CTRL_RANGEADJ6_MASK            (0xF000000U)
#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT           (24U)
/*! RANGEADJ6 - Channel 6 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)

#define PDM_RANGE_CTRL_RANGEADJ7_MASK            (0xF0000000U)
#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT           (28U)
/*! RANGEADJ7 - Channel 7 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
/*! @} */

/*! @name RANGE_STAT - MICFIL Range Status */
/*! @{ */

#define PDM_RANGE_STAT_RANGEOVF0_MASK            (0x1U)
#define PDM_RANGE_STAT_RANGEOVF0_SHIFT           (0U)
/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)

#define PDM_RANGE_STAT_RANGEOVF1_MASK            (0x2U)
#define PDM_RANGE_STAT_RANGEOVF1_SHIFT           (1U)
/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)

#define PDM_RANGE_STAT_RANGEOVF2_MASK            (0x4U)
#define PDM_RANGE_STAT_RANGEOVF2_SHIFT           (2U)
/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)

#define PDM_RANGE_STAT_RANGEOVF3_MASK            (0x8U)
#define PDM_RANGE_STAT_RANGEOVF3_SHIFT           (3U)
/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)

#define PDM_RANGE_STAT_RANGEOVF4_MASK            (0x10U)
#define PDM_RANGE_STAT_RANGEOVF4_SHIFT           (4U)
/*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)

#define PDM_RANGE_STAT_RANGEOVF5_MASK            (0x20U)
#define PDM_RANGE_STAT_RANGEOVF5_SHIFT           (5U)
/*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)

#define PDM_RANGE_STAT_RANGEOVF6_MASK            (0x40U)
#define PDM_RANGE_STAT_RANGEOVF6_SHIFT           (6U)
/*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)

#define PDM_RANGE_STAT_RANGEOVF7_MASK            (0x80U)
#define PDM_RANGE_STAT_RANGEOVF7_SHIFT           (7U)
/*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)

#define PDM_RANGE_STAT_RANGEUNF0_MASK            (0x10000U)
#define PDM_RANGE_STAT_RANGEUNF0_SHIFT           (16U)
/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)

#define PDM_RANGE_STAT_RANGEUNF1_MASK            (0x20000U)
#define PDM_RANGE_STAT_RANGEUNF1_SHIFT           (17U)
/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)

#define PDM_RANGE_STAT_RANGEUNF2_MASK            (0x40000U)
#define PDM_RANGE_STAT_RANGEUNF2_SHIFT           (18U)
/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)

#define PDM_RANGE_STAT_RANGEUNF3_MASK            (0x80000U)
#define PDM_RANGE_STAT_RANGEUNF3_SHIFT           (19U)
/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)

#define PDM_RANGE_STAT_RANGEUNF4_MASK            (0x100000U)
#define PDM_RANGE_STAT_RANGEUNF4_SHIFT           (20U)
/*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)

#define PDM_RANGE_STAT_RANGEUNF5_MASK            (0x200000U)
#define PDM_RANGE_STAT_RANGEUNF5_SHIFT           (21U)
/*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)

#define PDM_RANGE_STAT_RANGEUNF6_MASK            (0x400000U)
#define PDM_RANGE_STAT_RANGEUNF6_SHIFT           (22U)
/*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)

#define PDM_RANGE_STAT_RANGEUNF7_MASK            (0x800000U)
#define PDM_RANGE_STAT_RANGEUNF7_SHIFT           (23U)
/*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
/*! @} */

/*! @name FSYNC_CTRL - Frame Synchronization Control */
/*! @{ */

#define PDM_FSYNC_CTRL_FSYNCLEN_MASK             (0xFFFFFFFFU)
#define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT            (0U)
/*! FSYNCLEN - Frame Synchronization Window Length */
#define PDM_FSYNC_CTRL_FSYNCLEN(x)               (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK)
/*! @} */

/*! @name VERID - Version ID */
/*! @{ */

#define PDM_VERID_FEATURE_MASK                   (0xFFFFU)
#define PDM_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number */
#define PDM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK)

#define PDM_VERID_MINOR_MASK                     (0xFF0000U)
#define PDM_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define PDM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK)

#define PDM_VERID_MAJOR_MASK                     (0xFF000000U)
#define PDM_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define PDM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define PDM_PARAM_NPAIR_MASK                     (0xFU)
#define PDM_PARAM_NPAIR_SHIFT                    (0U)
/*! NPAIR - Number of Microphone Pairs
 *  0b0000..None
 *  0b0001..1 pair
 *  0b0010..2 pairs
 *  0b0011-0b1110.....
 *  0b1111..15 pairs
 */
#define PDM_PARAM_NPAIR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK)

#define PDM_PARAM_FIFO_PTRWID_MASK               (0xF0U)
#define PDM_PARAM_FIFO_PTRWID_SHIFT              (4U)
/*! FIFO_PTRWID - FIFO Pointer Width
 *  0b0000..0 bits
 *  0b0001..1 bit
 *  0b0010..2 bits
 *  0b0011-0b1110.....
 *  0b1111..15 bits
 */
#define PDM_PARAM_FIFO_PTRWID(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK)

#define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK         (0x100U)
#define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT        (8U)
/*! FIL_OUT_WIDTH_24B - Filter Output Width
 *  0b0..16 bits
 *  0b1..24 bits
 */
#define PDM_PARAM_FIL_OUT_WIDTH_24B(x)           (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK)

#define PDM_PARAM_LOW_POWER_MASK                 (0x200U)
#define PDM_PARAM_LOW_POWER_SHIFT                (9U)
/*! LOW_POWER - Low-Power Decimation Filter
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_PARAM_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK)

#define PDM_PARAM_DC_BYPASS_MASK                 (0x400U)
#define PDM_PARAM_DC_BYPASS_SHIFT                (10U)
/*! DC_BYPASS - Input DC Remover Bypass
 *  0b0..Active
 *  0b1..Disabled
 */
#define PDM_PARAM_DC_BYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK)

#define PDM_PARAM_DC_OUT_BYPASS_MASK             (0x800U)
#define PDM_PARAM_DC_OUT_BYPASS_SHIFT            (11U)
/*! DC_OUT_BYPASS - Output DC Remover Bypass
 *  0b0..Active
 *  0b1..Disabled
 */
#define PDM_PARAM_DC_OUT_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK)

#define PDM_PARAM_HWVAD_MASK                     (0x10000U)
#define PDM_PARAM_HWVAD_SHIFT                    (16U)
/*! HWVAD - HWVAD Active
 *  0b0..Disabled
 *  0b1..Active
 */
#define PDM_PARAM_HWVAD(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_SHIFT)) & PDM_PARAM_HWVAD_MASK)

#define PDM_PARAM_HWVAD_ENERGY_MODE_MASK         (0x20000U)
#define PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT        (17U)
/*! HWVAD_ENERGY_MODE - HWVAD Energy Mode Active
 *  0b0..Disabled
 *  0b1..Active
 */
#define PDM_PARAM_HWVAD_ENERGY_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT)) & PDM_PARAM_HWVAD_ENERGY_MODE_MASK)

#define PDM_PARAM_HWVAD_ZCD_MASK                 (0x80000U)
#define PDM_PARAM_HWVAD_ZCD_SHIFT                (19U)
/*! HWVAD_ZCD - HWVAD ZCD Active
 *  0b0..Disabled
 *  0b1..Active
 */
#define PDM_PARAM_HWVAD_ZCD(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ZCD_SHIFT)) & PDM_PARAM_HWVAD_ZCD_MASK)

#define PDM_PARAM_NUM_HWVAD_MASK                 (0xF000000U)
#define PDM_PARAM_NUM_HWVAD_SHIFT                (24U)
/*! NUM_HWVAD - Number of HWVADs */
#define PDM_PARAM_NUM_HWVAD(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NUM_HWVAD_SHIFT)) & PDM_PARAM_NUM_HWVAD_MASK)
/*! @} */

/*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control */
/*! @{ */

#define PDM_VAD0_CTRL_1_VADEN_MASK               (0x1U)
#define PDM_VAD0_CTRL_1_VADEN_SHIFT              (0U)
/*! VADEN - HWVAD Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_VAD0_CTRL_1_VADEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)

#define PDM_VAD0_CTRL_1_VADRST_MASK              (0x2U)
#define PDM_VAD0_CTRL_1_VADRST_SHIFT             (1U)
/*! VADRST - HWVAD Reset */
#define PDM_VAD0_CTRL_1_VADRST(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)

#define PDM_VAD0_CTRL_1_VADIE_MASK               (0x4U)
#define PDM_VAD0_CTRL_1_VADIE_SHIFT              (2U)
/*! VADIE - Interruption Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_VAD0_CTRL_1_VADIE(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)

#define PDM_VAD0_CTRL_1_VADERIE_MASK             (0x8U)
#define PDM_VAD0_CTRL_1_VADERIE_SHIFT            (3U)
/*! VADERIE - Error Interruption Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_VAD0_CTRL_1_VADERIE(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)

#define PDM_VAD0_CTRL_1_VADST10_MASK             (0x10U)
#define PDM_VAD0_CTRL_1_VADST10_SHIFT            (4U)
/*! VADST10 - Internal Filters Initialization
 *  0b0..Normal operation
 *  0b1..Filters initialized
 */
#define PDM_VAD0_CTRL_1_VADST10(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)

#define PDM_VAD0_CTRL_1_VADINITT_MASK            (0x1F00U)
#define PDM_VAD0_CTRL_1_VADINITT_SHIFT           (8U)
/*! VADINITT - Initialization Time
 *  0b00000..0
 *  0b00001..1
 *  0b00010-0b11110.....
 *  0b11111..31
 */
#define PDM_VAD0_CTRL_1_VADINITT(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)

#define PDM_VAD0_CTRL_1_VADCICOSR_MASK           (0xF0000U)
#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT          (16U)
/*! VADCICOSR - CIC Oversampling Rate */
#define PDM_VAD0_CTRL_1_VADCICOSR(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)

#define PDM_VAD0_CTRL_1_VADCHSEL_MASK            (0x7000000U)
#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT           (24U)
/*! VADCHSEL - Channel Selector
 *  0b000..PDM Microphone 0 Left
 *  0b001..PDM Microphone 0 Right
 *  0b010..PDM Microphone 1 Left
 *  0b011-0b101.....
 *  0b110..PDM Microphone 3 Left
 *  0b111..PDM Microphone 3 Right
 */
#define PDM_VAD0_CTRL_1_VADCHSEL(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
/*! @} */

/*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control */
/*! @{ */

#define PDM_VAD0_CTRL_2_VADHPF_MASK              (0x3U)
#define PDM_VAD0_CTRL_2_VADHPF_SHIFT             (0U)
/*! VADHPF - High-Pass Filter
 *  0b00..Filter bypassed
 *  0b01..Cut-off frequency at 1750 Hz
 *  0b10..Cut-off frequency at 215 Hz
 *  0b11..Cut-off frequency at 102 Hz
 */
#define PDM_VAD0_CTRL_2_VADHPF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)

#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK          (0xF00U)
#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT         (8U)
/*! VADINPGAIN - Input Gain
 *  0b0000..No shift
 *  0b0001..Shift 1 bit to the left
 *  0b0010..Shift 2 bits to the left
 *  0b0011-0b0110.....
 *  0b0111..Shift 7 bits to the left
 *  0b1000..Shift 8 bits to the right
 *  0b1001..Shift 7 bits to the right
 *  0b1010-0b1110.....
 *  0b1111..Shift 1 bits to the right
 */
#define PDM_VAD0_CTRL_2_VADINPGAIN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)

#define PDM_VAD0_CTRL_2_VADFRAMET_MASK           (0x3F0000U)
#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT          (16U)
/*! VADFRAMET - Frame Time
 *  0b000000..1
 *  0b000001..2
 *  0b000010-0b111110.....
 *  0b111111..63
 */
#define PDM_VAD0_CTRL_2_VADFRAMET(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)

#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK          (0x10000000U)
#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT         (28U)
/*! VADFOUTDIS - Force Output Disable
 *  0b0..Enables
 *  0b1..Disables
 */
#define PDM_VAD0_CTRL_2_VADFOUTDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)

#define PDM_VAD0_CTRL_2_VADPREFEN_MASK           (0x40000000U)
#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT          (30U)
/*! VADPREFEN - Pre Filter Enable
 *  0b0..Pre-filter bypassed
 *  0b1..Pre-filter enabled
 */
#define PDM_VAD0_CTRL_2_VADPREFEN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)

#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK          (0x80000000U)
#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT         (31U)
/*! VADFRENDIS - Frame Energy Disable
 *  0b1..Disables
 *  0b0..Enables
 */
#define PDM_VAD0_CTRL_2_VADFRENDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
/*! @} */

/*! @name VAD0_STAT - Voice Activity Detector 0 Status */
/*! @{ */

#define PDM_VAD0_STAT_VADIF_MASK                 (0x1U)
#define PDM_VAD0_STAT_VADIF_SHIFT                (0U)
/*! VADIF - Interrupt Flag
 *  0b0..Not detected
 *  0b1..Detected
 */
#define PDM_VAD0_STAT_VADIF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)

#define PDM_VAD0_STAT_VADINSATF_MASK             (0x10000U)
#define PDM_VAD0_STAT_VADINSATF_SHIFT            (16U)
/*! VADINSATF - Input Saturation Flag
 *  0b0..No exception
 *  0b1..Exception
 */
#define PDM_VAD0_STAT_VADINSATF(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)

#define PDM_VAD0_STAT_VADINITF_MASK              (0x80000000U)
#define PDM_VAD0_STAT_VADINITF_SHIFT             (31U)
/*! VADINITF - Initialization Flag
 *  0b0..Not being initialized
 *  0b1..Being initialized
 */
#define PDM_VAD0_STAT_VADINITF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
/*! @} */

/*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */
/*! @{ */

#define PDM_VAD0_SCONFIG_VADSGAIN_MASK           (0xFU)
#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT          (0U)
/*! VADSGAIN - Signal Gain
 *  0b0000, 0b0001..Multiplier = 1
 *  0b0010..Multiplier = 2
 *  0b0011-0b1110.....
 *  0b1111..Multiplier = 15
 */
#define PDM_VAD0_SCONFIG_VADSGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)

#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK          (0x40000000U)
#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT         (30U)
/*! VADSMAXEN - Signal Maximum Enable
 *  0b0..Maximum block bypassed
 *  0b1..Maximum block enabled
 */
#define PDM_VAD0_SCONFIG_VADSMAXEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)

#define PDM_VAD0_SCONFIG_VADSFILEN_MASK          (0x80000000U)
#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT         (31U)
/*! VADSFILEN - Signal Filter Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_VAD0_SCONFIG_VADSFILEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/*! @} */

/*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */
/*! @{ */

#define PDM_VAD0_NCONFIG_VADNGAIN_MASK           (0xFU)
#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT          (0U)
/*! VADNGAIN - Noise Gain
 *  0b0000, 0b0001..Multiplier = 1
 *  0b0010..Multiplier = 2
 *  0b0011-0b1110.....
 *  0b1111..Multiplier = 15
 */
#define PDM_VAD0_NCONFIG_VADNGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)

#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK         (0x1F00U)
#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT        (8U)
/*! VADNFILADJ - Noise Filter Adjustment
 *  0b00000..0
 *  0b00001..1
 *  0b00010-0b11110.....
 *  0b11111..31
 */
#define PDM_VAD0_NCONFIG_VADNFILADJ(x)           (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)

#define PDM_VAD0_NCONFIG_VADNOREN_MASK           (0x10000000U)
#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT          (28U)
/*! VADNOREN - Noise OR Enable
 *  0b0..Not decimated
 *  0b1..Decimated
 */
#define PDM_VAD0_NCONFIG_VADNOREN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)

#define PDM_VAD0_NCONFIG_VADNDECEN_MASK          (0x20000000U)
#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT         (29U)
/*! VADNDECEN - Noise Decimation Enable
 *  0b0..Not decimated
 *  0b1..Decimated
 */
#define PDM_VAD0_NCONFIG_VADNDECEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)

#define PDM_VAD0_NCONFIG_VADNMINEN_MASK          (0x40000000U)
#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT         (30U)
/*! VADNMINEN - Noise Minimum Enable
 *  0b0..Minimum block bypassed
 *  0b1..Minimum block enabled
 */
#define PDM_VAD0_NCONFIG_VADNMINEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)

#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK        (0x80000000U)
#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT       (31U)
/*! VADNFILAUTO - Noise Filter Auto
 *  0b0..Always enabled
 *  0b1..Enabled or disabled based on voice activity information
 */
#define PDM_VAD0_NCONFIG_VADNFILAUTO(x)          (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
/*! @} */

/*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */
/*! @{ */

#define PDM_VAD0_NDATA_VADNDATA_MASK             (0xFFFFU)
#define PDM_VAD0_NDATA_VADNDATA_SHIFT            (0U)
/*! VADNDATA - Noise Data */
#define PDM_VAD0_NDATA_VADNDATA(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
/*! @} */

/*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */
/*! @{ */

#define PDM_VAD0_ZCD_VADZCDEN_MASK               (0x1U)
#define PDM_VAD0_ZCD_VADZCDEN_SHIFT              (0U)
/*! VADZCDEN - ZCD Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_VAD0_ZCD_VADZCDEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)

#define PDM_VAD0_ZCD_VADZCDAUTO_MASK             (0x4U)
#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT            (2U)
/*! VADZCDAUTO - ZCD Automatic Threshold
 *  0b0..Disables
 *  0b1..Enables
 */
#define PDM_VAD0_ZCD_VADZCDAUTO(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)

#define PDM_VAD0_ZCD_VADZCDAND_MASK              (0x10U)
#define PDM_VAD0_ZCD_VADZCDAND_SHIFT             (4U)
/*! VADZCDAND - ZCD AND Behavior
 *  0b0..OR
 *  0b1..AND
 */
#define PDM_VAD0_ZCD_VADZCDAND(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)

#define PDM_VAD0_ZCD_VADZCDADJ_MASK              (0xF00U)
#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT             (8U)
/*! VADZCDADJ - ZCD Adjustment
 *  0b0000..0
 *  0b0001..1
 *  0b0010-0b1110.....
 *  0b1111..15
 */
#define PDM_VAD0_ZCD_VADZCDADJ(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)

#define PDM_VAD0_ZCD_VADZCDTH_MASK               (0x3FF0000U)
#define PDM_VAD0_ZCD_VADZCDTH_SHIFT              (16U)
/*! VADZCDTH - ZCD Threshold */
#define PDM_VAD0_ZCD_VADZCDTH(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PDM_Register_Masks */


/* PDM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PDM base address */
  #define PDM_BASE                                 (0x5020E000u)
  /** Peripheral PDM base address */
  #define PDM_BASE_NS                              (0x4020E000u)
  /** Peripheral PDM base pointer */
  #define PDM                                      ((PDM_Type *)PDM_BASE)
  /** Peripheral PDM base pointer */
  #define PDM_NS                                   ((PDM_Type *)PDM_BASE_NS)
  /** Array initializer of PDM peripheral base addresses */
  #define PDM_BASE_ADDRS                           { PDM_BASE }
  /** Array initializer of PDM peripheral base pointers */
  #define PDM_BASE_PTRS                            { PDM }
  /** Array initializer of PDM peripheral base addresses */
  #define PDM_BASE_ADDRS_NS                        { PDM_BASE_NS }
  /** Array initializer of PDM peripheral base pointers */
  #define PDM_BASE_PTRS_NS                         { PDM_NS }
#else
  /** Peripheral PDM base address */
  #define PDM_BASE                                 (0x4020E000u)
  /** Peripheral PDM base pointer */
  #define PDM                                      ((PDM_Type *)PDM_BASE)
  /** Array initializer of PDM peripheral base addresses */
  #define PDM_BASE_ADDRS                           { PDM_BASE }
  /** Array initializer of PDM peripheral base pointers */
  #define PDM_BASE_PTRS                            { PDM }
#endif

/*!
 * @}
 */ /* end of group PDM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PINT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
 * @{
 */

/** PINT - Register Layout Typedef */
typedef struct {
  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode, offset: 0x0 */
  __IO uint32_t IENR;                              /**< Pin Interrupt Level or Rising-Edge Interrupt Enable, offset: 0x4 */
  __IO uint32_t SIENR;                             /**< Pin Interrupt Level or Rising-Edge Interrupt Set, offset: 0x8 */
  __IO uint32_t CIENR;                             /**< Pin Interrupt Level (Rising-Edge Interrupt) Clear, offset: 0xC */
  __IO uint32_t IENF;                              /**< Pin Interrupt Active Level or Falling-Edge Interrupt Enable, offset: 0x10 */
  __IO uint32_t SIENF;                             /**< Pin Interrupt Active Level or Falling-Edge Interrupt Set, offset: 0x14 */
  __IO uint32_t CIENF;                             /**< Pin Interrupt Active Level or Falling-Edge Interrupt Clear, offset: 0x18 */
  __IO uint32_t RISE;                              /**< Pin Interrupt Rising Edge, offset: 0x1C */
  __IO uint32_t FALL;                              /**< Pin Interrupt Falling Edge, offset: 0x20 */
  __IO uint32_t IST;                               /**< Pin Interrupt Status, offset: 0x24 */
  __IO uint32_t PMCTRL;                            /**< Pattern-Match Interrupt Control, offset: 0x28 */
  __IO uint32_t PMSRC;                             /**< Pattern-Match Interrupt Bit-Slice Source, offset: 0x2C */
  __IO uint32_t PMCFG;                             /**< Pattern-Match Interrupt Bit Slice Configuration, offset: 0x30 */
} PINT_Type;

/* ----------------------------------------------------------------------------
   -- PINT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PINT_Register_Masks PINT Register Masks
 * @{
 */

/*! @name ISEL - Pin Interrupt Mode */
/*! @{ */

#define PINT_ISEL_PMODE_MASK                     (0xFFU)
#define PINT_ISEL_PMODE_SHIFT                    (0U)
/*! PMODE - Interrupt mode
 *  0b00000000..In bit n configures the interrupt to be edge-sensitive
 *  0b00000001..In bit n configures the interrupt to be level-sensitive
 */
#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
/*! @} */

/*! @name IENR - Pin Interrupt Level or Rising-Edge Interrupt Enable */
/*! @{ */

#define PINT_IENR_ENRL_MASK                      (0xFFU)
#define PINT_IENR_ENRL_SHIFT                     (0U)
/*! ENRL - Enables Interrupt
 *  0b00000000..In bit n disables the corresponding interrupt
 *  0b00000001..In bit n enables the corresponding interrupt
 */
#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
/*! @} */

/*! @name SIENR - Pin Interrupt Level or Rising-Edge Interrupt Set */
/*! @{ */

#define PINT_SIENR_SETENRL_MASK                  (0xFFU)
#define PINT_SIENR_SETENRL_SHIFT                 (0U)
/*! SETENRL - Configures IENR
 *  0b00000000..No operation for interrupt n
 *  0b00000001..Enable rising edge or level interrupt for interrupt n
 */
#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
/*! @} */

/*! @name CIENR - Pin Interrupt Level (Rising-Edge Interrupt) Clear */
/*! @{ */

#define PINT_CIENR_CENRL_MASK                    (0xFFU)
#define PINT_CIENR_CENRL_SHIFT                   (0U)
/*! CENRL - Clear bits in IENR
 *  0b00000000..No operation
 *  0b00000001..Disable rising edge or level interrupt
 */
#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
/*! @} */

/*! @name IENF - Pin Interrupt Active Level or Falling-Edge Interrupt Enable */
/*! @{ */

#define PINT_IENF_ENAF_MASK                      (0xFFU)
#define PINT_IENF_ENAF_SHIFT                     (0U)
/*! ENAF - Enables Interrupt
 *  0b00000000..Disable (set active interrupt level LOW)
 *  0b00000001..Enable (set active interrupt level HIGH)
 */
#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
/*! @} */

/*! @name SIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Set */
/*! @{ */

#define PINT_SIENF_SETENAF_MASK                  (0xFFU)
#define PINT_SIENF_SETENAF_SHIFT                 (0U)
/*! SETENAF
 *  0b00000000..Writes 0 to IENF.
 *  0b00000001..Select HIGH-active interrupt or enable falling-edge interrupt
 */
#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
/*! @} */

/*! @name CIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Clear */
/*! @{ */

#define PINT_CIENF_CENAF_MASK                    (0xFFU)
#define PINT_CIENF_CENAF_SHIFT                   (0U)
/*! CENAF - Writes 0 to IENF
 *  0b00000000..No operation
 *  0b00000001..LOW-active interrupt selected or falling-edge interrupt disabled
 */
#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
/*! @} */

/*! @name RISE - Pin Interrupt Rising Edge */
/*! @{ */

#define PINT_RISE_RDET_MASK                      (0xFFU)
#define PINT_RISE_RDET_SHIFT                     (0U)
/*! RDET - Rising-Edge Detect
 *  0b00000000..Read 0- No rising edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation
 *  0b00000001..Read 1- Rising edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear rising-edge detection for this pin
 */
#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
/*! @} */

/*! @name FALL - Pin Interrupt Falling Edge */
/*! @{ */

#define PINT_FALL_FDET_MASK                      (0xFFU)
#define PINT_FALL_FDET_SHIFT                     (0U)
/*! FDET - Falling-Edge Detect
 *  0b00000000..Read 0- No falling edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation
 *  0b00000001..Read 1- Falling edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear falling-edge detection for this bit
 */
#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
/*! @} */

/*! @name IST - Pin Interrupt Status */
/*! @{ */

#define PINT_IST_PSTAT_MASK                      (0xFFU)
#define PINT_IST_PSTAT_SHIFT                     (0U)
/*! PSTAT - Pin Interrupt Status
 *  0b00000000..Read 0- Interrupt is not requested, Write 0- No operation
 *  0b00000001..Read 1- Interrupt is requested, Write 1 (edge-sensitive)- clear rising- and falling-edge detection
 *              for this pin, Write 1 (level-sensitive)- switch the active level for this pin in
 */
#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
/*! @} */

/*! @name PMCTRL - Pattern-Match Interrupt Control */
/*! @{ */

#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function
 *    or by the pattern-match function. If this value is 0b, interrupts are driven in response to the
 *    standard pin interrupt function. If this value is 1b, interrupts are driven in response to
 *    pattern matches.
 *  0b0..Pin interrupt
 *  0b1..Pattern match
 */
#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)

#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified
 *    Boolean expression evaluates to true. If this value is 0b, RXEV output to the CPU is disabled. If
 *    this value is 1b, RXEV output to the CPU is enabled.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)

#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
/*! PMAT - Pattern Matches
 *  0b00000001..The corresponding product term is matched by the current state of the appropriate inputs
 */
#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
/*! @} */

/*! @name PMSRC - Pattern-Match Interrupt Bit-Slice Source */
/*! @{ */

#define PINT_PMSRC_SRC0_MASK                     (0x700U)
#define PINT_PMSRC_SRC0_SHIFT                    (8U)
/*! SRC0 - Selects the input source for bit slice 0
 *  0b000..Input 0 (selects the pin identified in PINT_TRIG0)
 *  0b001..Input 1 (selects the pin identified in PINT_TRIG1)
 *  0b010..Input 2 (selects the pin identified in PINT_TRIG2)
 *  0b011..Input 3 (selects the pin identified in PINT_TRIG3)
 *  0b100..Input 4 (selects the pin identified in PINT_TRIG4)
 *  0b101..Input 5 (selects the pin identified in PINT_TRIG5)
 *  0b110..Input 6 (selects the pin identified in PINT_TRIG6)
 *  0b111..Input 7 (selects the pin identified in PINT_TRIG7)
 */
#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)

#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
#define PINT_PMSRC_SRC1_SHIFT                    (11U)
/*! SRC1 - Selects the input source for bit slice 1
 *  0b000..Input 0 (selects the pin identified in PINT_TRIG0)
 *  0b001..Input 1 (selects the pin identified in PINT_TRIG1)
 *  0b010..Input 2 (selects the pin identified in PINT_TRIG2)
 *  0b011..Input 3 (selects the pin identified in PINT_TRIG3)
 *  0b100..Input 4 (selects the pin identified in PINT_TRIG4)
 *  0b101..Input 5 (selects the pin identified in PINT_TRIG5)
 *  0b110..Input 6 (selects the pin identified in PINT_TRIG6)
 *  0b111..Input 7 (selects the pin identified in PINT_TRIG7)
 */
#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)

#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
#define PINT_PMSRC_SRC2_SHIFT                    (14U)
/*! SRC2 - Selects the input source for bit slice 2
 *  0b000..Input 0 (selects the pin identified in PINT_TRIG0)
 *  0b001..Input 1 (selects the pin identified in PINT_TRIG1)
 *  0b010..Input 2 (selects the pin identified in PINT_TRIG2)
 *  0b011..Input 3 (selects the pin identified in PINT_TRIG3)
 *  0b100..Input 4 (selects the pin identified in PINT_TRIG4)
 *  0b101..Input 5 (selects the pin identified in PINT_TRIG5)
 *  0b110..Input 6 (selects the pin identified in PINT_TRIG6)
 *  0b111..Input 7 (selects the pin identified in PINT_TRIG7)
 */
#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)

#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
#define PINT_PMSRC_SRC3_SHIFT                    (17U)
/*! SRC3 - Selects the input source for bit slice 3
 *  0b000..Input 0 (selects the pin identified in PINT_TRIG0)
 *  0b001..Input 1 (selects the pin identified in PINT_TRIG1)
 *  0b010..Input 2 (selects the pin identified in PINT_TRIG2)
 *  0b011..Input 3 (selects the pin identified in PINT_TRIG3)
 *  0b100..Input 4 (selects the pin identified in PINT_TRIG4)
 *  0b101..Input 5 (selects the pin identified in PINT_TRIG5)
 *  0b110..Input 6 (selects the pin identified in PINT_TRIG6)
 *  0b111..Input 7 (selects the pin identified in PINT_TRIG7)
 */
#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)

#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
#define PINT_PMSRC_SRC4_SHIFT                    (20U)
/*! SRC4 - Selects the input source for bit slice 4
 *  0b000..Input 0 (selects the pin identified in PINT_TRIG0)
 *  0b001..Input 1 (selects the pin identified in PINT_TRIG1)
 *  0b010..Input 2 (selects the pin identified in PINT_TRIG2)
 *  0b011..Input 3 (selects the pin identified in PINT_TRIG3)
 *  0b100..Input 4 (selects the pin identified in PINT_TRIG4)
 *  0b101..Input 5 (selects the pin identified in PINT_TRIG5)
 *  0b110..Input 6 (selects the pin identified in PINT_TRIG6)
 *  0b111..Input 7 (selects the pin identified in PINT_TRIG7)
 */
#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)

#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
#define PINT_PMSRC_SRC5_SHIFT                    (23U)
/*! SRC5 - Selects the input source for bit slice 5
 *  0b000..Input 0 (selects the pin identified in PINT_TRIG0)
 *  0b001..Input 1 (selects the pin identified in PINT_TRIG1)
 *  0b010..Input 2 (selects the pin identified in PINT_TRIG2)
 *  0b011..Input 3 (selects the pin identified in PINT_TRIG3)
 *  0b100..Input 4 (selects the pin identified in PINT_TRIG4)
 *  0b101..Input 5 (selects the pin identified in PINT_TRIG5)
 *  0b110..Input 6 (selects the pin identified in PINT_TRIG6)
 *  0b111..Input 7 (selects the pin identified in PINT_TRIG7)
 */
#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)

#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
#define PINT_PMSRC_SRC6_SHIFT                    (26U)
/*! SRC6 - Selects the input source for bit slice 6
 *  0b000..Input 0 (selects the pin identified in PINT_TRIG0)
 *  0b001..Input 1 (selects the pin identified in PINT_TRIG1)
 *  0b010..Input 2 (selects the pin identified in PINT_TRIG2)
 *  0b011..Input 3 (selects the pin identified in PINT_TRIG3)
 *  0b100..Input 4 (selects the pin identified in PINT_TRIG4)
 *  0b101..Input 5 (selects the pin identified in PINT_TRIG5)
 *  0b110..Input 6 (selects the pin identified in PINT_TRIG6)
 *  0b111..Input 7 (selects the pin identified in PINT_TRIG7)
 */
#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)

#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
#define PINT_PMSRC_SRC7_SHIFT                    (29U)
/*! SRC7 - Selects the input source for bit slice 7
 *  0b000..Input 0 (selects the pin identified in PINT_TRIG0)
 *  0b001..Input 1 (selects the pin identified in PINT_TRIG1)
 *  0b010..Input 2 (selects the pin identified in PINT_TRIG2)
 *  0b011..Input 3 (selects the pin identified in PINT_TRIG3)
 *  0b100..Input 4 (selects the pin identified in PINT_TRIG4)
 *  0b101..Input 5 (selects the pin identified in PINT_TRIG5)
 *  0b110..Input 6 (selects the pin identified in PINT_TRIG6)
 *  0b111..Input 7 (selects the pin identified in PINT_TRIG7)
 */
#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
/*! @} */

/*! @name PMCFG - Pattern-Match Interrupt Bit Slice Configuration */
/*! @{ */

#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. Slice 0 is not an endpoint. Slice 0 is
 *    the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the
 *    minterm evaluates as true.
 *  0b0..No effect
 *  0b1..Endpoint
 */
#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)

#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. Slice 1 is not an endpoint. Slice 1 is
 *    the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the
 *    minterm evaluates as true.
 *  0b0..No effect
 *  0b1..Endpoint
 */
#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)

#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. Slice 2 is not an endpoint. Slice 2 is
 *    the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the
 *    minterm evaluates as true.
 *  0b0..No effect
 *  0b1..Endpoint
 */
#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)

#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. Slice 3 is not an endpoint. Slice 3 is
 *    the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the
 *    minterm evaluates as true.
 *  0b0..No effect
 *  0b1..Endpoint
 */
#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)

#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. Slice 4 is not an endpoint. Slice 4 is
 *    the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the
 *    minterm evaluates as true.
 *  0b0..No effect
 *  0b1..Endpoint
 */
#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)

#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. Slice 5 is not an endpoint. Slice 5 is
 *    the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the
 *    minterm evaluates as true.
 *  0b0..No effect
 *  0b1..Endpoint
 */
#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)

#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. Slice 6 is not an endpoint. Slice 6 is
 *    the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the
 *    minterm evaluates as true.
 *  0b0..No effect
 *  0b1..Endpoint
 */
#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)

#define PINT_PMCFG_CFG0_MASK                     (0x700U)
#define PINT_PMCFG_CFG0_SHIFT                    (8U)
/*! CFG0 - Match Configuration
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge
 *  0b010..Sticky falling edge
 *  0b011..Sticky rising or falling edge
 *  0b100..High level
 *  0b101..Low level
 *  0b110..Constant 0
 *  0b111..Event (Nonsticky rising or falling edge)
 */
#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)

#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
#define PINT_PMCFG_CFG1_SHIFT                    (11U)
/*! CFG1 - Match Configuration
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge
 *  0b010..Sticky falling edge
 *  0b011..Sticky rising or falling edge
 *  0b100..High level
 *  0b101..Low level
 *  0b110..Constant 0
 *  0b111..Event (Nonsticky rising or falling edge)
 */
#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)

#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
#define PINT_PMCFG_CFG2_SHIFT                    (14U)
/*! CFG2 - Match Configuration
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge
 *  0b010..Sticky falling edge
 *  0b011..Sticky rising or falling edge
 *  0b100..High level
 *  0b101..Low level
 *  0b110..Constant 0
 *  0b111..Event (Nonsticky rising or falling edge)
 */
#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)

#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
#define PINT_PMCFG_CFG3_SHIFT                    (17U)
/*! CFG3 - Match Configuration
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge
 *  0b010..Sticky falling edge
 *  0b011..Sticky rising or falling edge
 *  0b100..High level
 *  0b101..Low level
 *  0b110..Constant 0
 *  0b111..Event (Nonsticky rising or falling edge)
 */
#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)

#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
#define PINT_PMCFG_CFG4_SHIFT                    (20U)
/*! CFG4 - Match Configuration
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge
 *  0b010..Sticky falling edge
 *  0b011..Sticky rising or falling edge
 *  0b100..High level
 *  0b101..Low level
 *  0b110..Constant 0
 *  0b111..Event (Nonsticky rising or falling edge)
 */
#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)

#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
#define PINT_PMCFG_CFG5_SHIFT                    (23U)
/*! CFG5 - Match Configuration
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge
 *  0b010..Sticky falling edge
 *  0b011..Sticky rising or falling edge
 *  0b100..High level
 *  0b101..Low level
 *  0b110..Constant 0
 *  0b111..Event (Nonsticky rising or falling edge)
 */
#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)

#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
#define PINT_PMCFG_CFG6_SHIFT                    (26U)
/*! CFG6 - Match Configuration
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge
 *  0b010..Sticky falling edge
 *  0b011..Sticky rising or falling edge
 *  0b100..High level
 *  0b101..Low level
 *  0b110..Constant 0
 *  0b111..Event (Nonsticky rising or falling edge)
 */
#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)

#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
#define PINT_PMCFG_CFG7_SHIFT                    (29U)
/*! CFG7 - Match Configuration
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge
 *  0b010..Sticky falling edge
 *  0b011..Sticky rising or falling edge
 *  0b100..High level
 *  0b101..Low level
 *  0b110..Constant 0
 *  0b111..Event (Nonsticky rising or falling edge)
 */
#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PINT_Register_Masks */


/* PINT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PINT0 base address */
  #define PINT0_BASE                               (0x50025000u)
  /** Peripheral PINT0 base address */
  #define PINT0_BASE_NS                            (0x40025000u)
  /** Peripheral PINT0 base pointer */
  #define PINT0                                    ((PINT_Type *)PINT0_BASE)
  /** Peripheral PINT0 base pointer */
  #define PINT0_NS                                 ((PINT_Type *)PINT0_BASE_NS)
  /** Array initializer of PINT peripheral base addresses */
  #define PINT_BASE_ADDRS                          { PINT0_BASE }
  /** Array initializer of PINT peripheral base pointers */
  #define PINT_BASE_PTRS                           { PINT0 }
  /** Array initializer of PINT peripheral base addresses */
  #define PINT_BASE_ADDRS_NS                       { PINT0_BASE_NS }
  /** Array initializer of PINT peripheral base pointers */
  #define PINT_BASE_PTRS_NS                        { PINT0_NS }
#else
  /** Peripheral PINT0 base address */
  #define PINT0_BASE                               (0x40025000u)
  /** Peripheral PINT0 base pointer */
  #define PINT0                                    ((PINT_Type *)PINT0_BASE)
  /** Array initializer of PINT peripheral base addresses */
  #define PINT_BASE_ADDRS                          { PINT0_BASE }
  /** Array initializer of PINT peripheral base pointers */
  #define PINT_BASE_PTRS                           { PINT0 }
#endif
/** Interrupt vectors for the PINT peripheral type */
#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }

/*!
 * @}
 */ /* end of group PINT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PKC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer
 * @{
 */

/** PKC - Register Layout Typedef */
typedef struct {
  __I  uint32_t PKC_STATUS;                        /**< Status Register, offset: 0x0 */
  __IO uint32_t PKC_CTRL;                          /**< Control Register, offset: 0x4 */
  __IO uint32_t PKC_CFG;                           /**< Configuration register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t PKC_MODE1;                         /**< Mode register, parameter set 1, offset: 0x10 */
  __IO uint32_t PKC_XYPTR1;                        /**< X+Y pointer register, parameter set 1, offset: 0x14 */
  __IO uint32_t PKC_ZRPTR1;                        /**< Z+R pointer register, parameter set 1, offset: 0x18 */
  __IO uint32_t PKC_LEN1;                          /**< Length register, parameter set 1, offset: 0x1C */
  __IO uint32_t PKC_MODE2;                         /**< Mode register, parameter set 2, offset: 0x20 */
  __IO uint32_t PKC_XYPTR2;                        /**< X+Y pointer register, parameter set 2, offset: 0x24 */
  __IO uint32_t PKC_ZRPTR2;                        /**< Z+R pointer register, parameter set 2, offset: 0x28 */
  __IO uint32_t PKC_LEN2;                          /**< Length register, parameter set 2, offset: 0x2C */
       uint8_t RESERVED_1[16];
  __IO uint32_t PKC_UPTR;                          /**< Universal pointer FUP program, offset: 0x40 */
  __IO uint32_t PKC_UPTRT;                         /**< Universal pointer FUP table, offset: 0x44 */
  __IO uint32_t PKC_ULEN;                          /**< Universal pointer length, offset: 0x48 */
       uint8_t RESERVED_2[4];
  __IO uint32_t PKC_MCDATA;                        /**< MC pattern data interface, offset: 0x50 */
       uint8_t RESERVED_3[12];
  __I  uint32_t PKC_VERSION;                       /**< PKC version register, offset: 0x60 */
       uint8_t RESERVED_4[3916];
  __O  uint32_t PKC_SOFT_RST;                      /**< Software reset, offset: 0xFB0 */
       uint8_t RESERVED_5[12];
  __I  uint32_t PKC_ACCESS_ERR;                    /**< Access Error, offset: 0xFC0 */
  __O  uint32_t PKC_ACCESS_ERR_CLR;                /**< Clear Access Error, offset: 0xFC4 */
       uint8_t RESERVED_6[16];
  __O  uint32_t PKC_INT_CLR_ENABLE;                /**< Interrupt enable clear, offset: 0xFD8 */
  __O  uint32_t PKC_INT_SET_ENABLE;                /**< Interrupt enable set, offset: 0xFDC */
  __I  uint32_t PKC_INT_STATUS;                    /**< Interrupt status, offset: 0xFE0 */
  __I  uint32_t PKC_INT_ENABLE;                    /**< Interrupt enable, offset: 0xFE4 */
  __O  uint32_t PKC_INT_CLR_STATUS;                /**< Interrupt status clear, offset: 0xFE8 */
  __O  uint32_t PKC_INT_SET_STATUS;                /**< Interrupt status set, offset: 0xFEC */
       uint8_t RESERVED_7[12];
  __I  uint32_t PKC_MODULE_ID;                     /**< Module ID, offset: 0xFFC */
} PKC_Type;

/* ----------------------------------------------------------------------------
   -- PKC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PKC_Register_Masks PKC Register Masks
 * @{
 */

/*! @name PKC_STATUS - Status Register */
/*! @{ */

#define PKC_PKC_STATUS_ACTIV_MASK                (0x1U)
#define PKC_PKC_STATUS_ACTIV_SHIFT               (0U)
/*! ACTIV - PKC ACTIV */
#define PKC_PKC_STATUS_ACTIV(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK)

#define PKC_PKC_STATUS_CARRY_MASK                (0x2U)
#define PKC_PKC_STATUS_CARRY_SHIFT               (1U)
/*! CARRY - Carry overflow flag */
#define PKC_PKC_STATUS_CARRY(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK)

#define PKC_PKC_STATUS_ZERO_MASK                 (0x4U)
#define PKC_PKC_STATUS_ZERO_SHIFT                (2U)
/*! ZERO - Zero result flag */
#define PKC_PKC_STATUS_ZERO(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK)

#define PKC_PKC_STATUS_GOANY_MASK                (0x8U)
#define PKC_PKC_STATUS_GOANY_SHIFT               (3U)
/*! GOANY - Combined GO status flag */
#define PKC_PKC_STATUS_GOANY(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK)

#define PKC_PKC_STATUS_LOCKED_MASK               (0x60U)
#define PKC_PKC_STATUS_LOCKED_SHIFT              (5U)
/*! LOCKED - Parameter set locked */
#define PKC_PKC_STATUS_LOCKED(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK)
/*! @} */

/*! @name PKC_CTRL - Control Register */
/*! @{ */

#define PKC_PKC_CTRL_RESET_MASK                  (0x1U)
#define PKC_PKC_CTRL_RESET_SHIFT                 (0U)
/*! RESET - PKC reset control bit */
#define PKC_PKC_CTRL_RESET(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK)

#define PKC_PKC_CTRL_STOP_MASK                   (0x2U)
#define PKC_PKC_CTRL_STOP_SHIFT                  (1U)
/*! STOP - Freeze PKC calculation */
#define PKC_PKC_CTRL_STOP(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK)

#define PKC_PKC_CTRL_GOD1_MASK                   (0x4U)
#define PKC_PKC_CTRL_GOD1_SHIFT                  (2U)
/*! GOD1 - Control bit to start direct operation using parameter set 1 */
#define PKC_PKC_CTRL_GOD1(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK)

#define PKC_PKC_CTRL_GOD2_MASK                   (0x8U)
#define PKC_PKC_CTRL_GOD2_SHIFT                  (3U)
/*! GOD2 - Control bit to start direct operation using parameter set 2 */
#define PKC_PKC_CTRL_GOD2(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK)

#define PKC_PKC_CTRL_GOM1_MASK                   (0x10U)
#define PKC_PKC_CTRL_GOM1_SHIFT                  (4U)
/*! GOM1 - Control bit to start MC pattern using parameter set 1 */
#define PKC_PKC_CTRL_GOM1(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK)

#define PKC_PKC_CTRL_GOM2_MASK                   (0x20U)
#define PKC_PKC_CTRL_GOM2_SHIFT                  (5U)
/*! GOM2 - Control bit to start MC pattern using parameter set 2 */
#define PKC_PKC_CTRL_GOM2(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK)

#define PKC_PKC_CTRL_GOU_MASK                    (0x40U)
#define PKC_PKC_CTRL_GOU_SHIFT                   (6U)
/*! GOU - Control bit to start pipe operation */
#define PKC_PKC_CTRL_GOU(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK)

#define PKC_PKC_CTRL_GF2CONV_MASK                (0x80U)
#define PKC_PKC_CTRL_GF2CONV_SHIFT               (7U)
/*! GF2CONV - Convert to GF2 calculation modes */
#define PKC_PKC_CTRL_GF2CONV(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK)

#define PKC_PKC_CTRL_CLRCACHE_MASK               (0x100U)
#define PKC_PKC_CTRL_CLRCACHE_SHIFT              (8U)
/*! CLRCACHE - Clear universal pointer cache */
#define PKC_PKC_CTRL_CLRCACHE(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK)

#define PKC_PKC_CTRL_CACHE_EN_MASK               (0x200U)
#define PKC_PKC_CTRL_CACHE_EN_SHIFT              (9U)
/*! CACHE_EN - Enable universal pointer cache */
#define PKC_PKC_CTRL_CACHE_EN(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK)

#define PKC_PKC_CTRL_REDMUL_MASK                 (0xC00U)
#define PKC_PKC_CTRL_REDMUL_SHIFT                (10U)
/*! REDMUL - Reduced multiplier mode
 *  0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008
 *  0b01..Reserved - Error Generated if selected
 *  0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008
 *  0b11..Reserved - Error Generated if selected
 */
#define PKC_PKC_CTRL_REDMUL(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK)
/*! @} */

/*! @name PKC_CFG - Configuration register */
/*! @{ */

#define PKC_PKC_CFG_IDLEOP_MASK                  (0x1U)
#define PKC_PKC_CFG_IDLEOP_SHIFT                 (0U)
#define PKC_PKC_CFG_IDLEOP(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK)

#define PKC_PKC_CFG_RFU1_MASK                    (0x2U)
#define PKC_PKC_CFG_RFU1_SHIFT                   (1U)
#define PKC_PKC_CFG_RFU1(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK)

#define PKC_PKC_CFG_RFU2_MASK                    (0x4U)
#define PKC_PKC_CFG_RFU2_SHIFT                   (2U)
#define PKC_PKC_CFG_RFU2(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK)

#define PKC_PKC_CFG_CLKRND_MASK                  (0x8U)
#define PKC_PKC_CFG_CLKRND_SHIFT                 (3U)
#define PKC_PKC_CFG_CLKRND(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK)

#define PKC_PKC_CFG_REDMULNOISE_MASK             (0x10U)
#define PKC_PKC_CFG_REDMULNOISE_SHIFT            (4U)
#define PKC_PKC_CFG_REDMULNOISE(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK)

#define PKC_PKC_CFG_RNDDLY_MASK                  (0xE0U)
#define PKC_PKC_CFG_RNDDLY_SHIFT                 (5U)
#define PKC_PKC_CFG_RNDDLY(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK)

#define PKC_PKC_CFG_SBXNOISE_MASK                (0x100U)
#define PKC_PKC_CFG_SBXNOISE_SHIFT               (8U)
#define PKC_PKC_CFG_SBXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK)

#define PKC_PKC_CFG_ALPNOISE_MASK                (0x200U)
#define PKC_PKC_CFG_ALPNOISE_SHIFT               (9U)
#define PKC_PKC_CFG_ALPNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK)

#define PKC_PKC_CFG_FMULNOISE_MASK               (0x400U)
#define PKC_PKC_CFG_FMULNOISE_SHIFT              (10U)
#define PKC_PKC_CFG_FMULNOISE(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK)
/*! @} */

/*! @name PKC_MODE1 - Mode register, parameter set 1 */
/*! @{ */

#define PKC_PKC_MODE1_MODE_MASK                  (0xFFU)
#define PKC_PKC_MODE1_MODE_SHIFT                 (0U)
/*! MODE - Calculation Mode / MC Start address */
#define PKC_PKC_MODE1_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK)
/*! @} */

/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */
/*! @{ */

#define PKC_PKC_XYPTR1_XPTR_MASK                 (0xFFFFU)
#define PKC_PKC_XYPTR1_XPTR_SHIFT                (0U)
/*! XPTR - Start address of X operand in PKCRAM with byte granularity */
#define PKC_PKC_XYPTR1_XPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK)

#define PKC_PKC_XYPTR1_YPTR_MASK                 (0xFFFF0000U)
#define PKC_PKC_XYPTR1_YPTR_SHIFT                (16U)
/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */
#define PKC_PKC_XYPTR1_YPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK)
/*! @} */

/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */
/*! @{ */

#define PKC_PKC_ZRPTR1_ZPTR_MASK                 (0xFFFFU)
#define PKC_PKC_ZRPTR1_ZPTR_SHIFT                (0U)
/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */
#define PKC_PKC_ZRPTR1_ZPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK)

#define PKC_PKC_ZRPTR1_RPTR_MASK                 (0xFFFF0000U)
#define PKC_PKC_ZRPTR1_RPTR_SHIFT                (16U)
/*! RPTR - Start address of R result in PKCRAM with byte granularity */
#define PKC_PKC_ZRPTR1_RPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK)
/*! @} */

/*! @name PKC_LEN1 - Length register, parameter set 1 */
/*! @{ */

#define PKC_PKC_LEN1_LEN_MASK                    (0xFFFFU)
#define PKC_PKC_LEN1_LEN_SHIFT                   (0U)
/*! LEN - Operand length */
#define PKC_PKC_LEN1_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK)

#define PKC_PKC_LEN1_MCLEN_MASK                  (0xFFFF0000U)
#define PKC_PKC_LEN1_MCLEN_SHIFT                 (16U)
/*! MCLEN - Loop counter for microcode pattern */
#define PKC_PKC_LEN1_MCLEN(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK)
/*! @} */

/*! @name PKC_MODE2 - Mode register, parameter set 2 */
/*! @{ */

#define PKC_PKC_MODE2_MODE_MASK                  (0xFFU)
#define PKC_PKC_MODE2_MODE_SHIFT                 (0U)
/*! MODE - Calculation Mode / MC Start address */
#define PKC_PKC_MODE2_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK)
/*! @} */

/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */
/*! @{ */

#define PKC_PKC_XYPTR2_XPTR_MASK                 (0xFFFFU)
#define PKC_PKC_XYPTR2_XPTR_SHIFT                (0U)
/*! XPTR - Start address of X operand in PKCRAM with byte granularity */
#define PKC_PKC_XYPTR2_XPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK)

#define PKC_PKC_XYPTR2_YPTR_MASK                 (0xFFFF0000U)
#define PKC_PKC_XYPTR2_YPTR_SHIFT                (16U)
/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */
#define PKC_PKC_XYPTR2_YPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK)
/*! @} */

/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */
/*! @{ */

#define PKC_PKC_ZRPTR2_ZPTR_MASK                 (0xFFFFU)
#define PKC_PKC_ZRPTR2_ZPTR_SHIFT                (0U)
/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */
#define PKC_PKC_ZRPTR2_ZPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPTR_SHIFT)) & PKC_PKC_ZRPTR2_ZPTR_MASK)

#define PKC_PKC_ZRPTR2_RPTR_MASK                 (0xFFFF0000U)
#define PKC_PKC_ZRPTR2_RPTR_SHIFT                (16U)
/*! RPTR - Start address of R result in PKCRAM with byte granularity */
#define PKC_PKC_ZRPTR2_RPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK)
/*! @} */

/*! @name PKC_LEN2 - Length register, parameter set 2 */
/*! @{ */

#define PKC_PKC_LEN2_LEN_MASK                    (0xFFFFU)
#define PKC_PKC_LEN2_LEN_SHIFT                   (0U)
/*! LEN - Operand length */
#define PKC_PKC_LEN2_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK)

#define PKC_PKC_LEN2_MCLEN_MASK                  (0xFFFF0000U)
#define PKC_PKC_LEN2_MCLEN_SHIFT                 (16U)
/*! MCLEN - Loop counter for microcode pattern */
#define PKC_PKC_LEN2_MCLEN(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK)
/*! @} */

/*! @name PKC_UPTR - Universal pointer FUP program */
/*! @{ */

#define PKC_PKC_UPTR_PTR_MASK                    (0xFFFFFFFFU)
#define PKC_PKC_UPTR_PTR_SHIFT                   (0U)
/*! PTR - Pointer to start address of PKC FUP program */
#define PKC_PKC_UPTR_PTR(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK)
/*! @} */

/*! @name PKC_UPTRT - Universal pointer FUP table */
/*! @{ */

#define PKC_PKC_UPTRT_PTR_MASK                   (0xFFFFFFFFU)
#define PKC_PKC_UPTRT_PTR_SHIFT                  (0U)
/*! PTR - Pointer to start address of PKC FUP table */
#define PKC_PKC_UPTRT_PTR(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK)
/*! @} */

/*! @name PKC_ULEN - Universal pointer length */
/*! @{ */

#define PKC_PKC_ULEN_LEN_MASK                    (0xFFU)
#define PKC_PKC_ULEN_LEN_SHIFT                   (0U)
/*! LEN - Length of universal pointer calculation */
#define PKC_PKC_ULEN_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK)
/*! @} */

/*! @name PKC_MCDATA - MC pattern data interface */
/*! @{ */

#define PKC_PKC_MCDATA_MCDATA_MASK               (0xFFFFFFFFU)
#define PKC_PKC_MCDATA_MCDATA_SHIFT              (0U)
/*! MCDATA - Microcode read/write data */
#define PKC_PKC_MCDATA_MCDATA(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK)
/*! @} */

/*! @name PKC_VERSION - PKC version register */
/*! @{ */

#define PKC_PKC_VERSION_MULSIZE_MASK             (0x3U)
#define PKC_PKC_VERSION_MULSIZE_SHIFT            (0U)
/*! MULSIZE
 *  0b01..32-bit multiplier
 *  0b10..64-bit multiplier
 *  0b11..128-bit multiplier
 *  0b01..64-bit multiplier
 *  0b10..128-bit multiplier
 */
#define PKC_PKC_VERSION_MULSIZE(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK)

#define PKC_PKC_VERSION_MCAVAIL_MASK             (0x4U)
#define PKC_PKC_VERSION_MCAVAIL_SHIFT            (2U)
#define PKC_PKC_VERSION_MCAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK)

#define PKC_PKC_VERSION_UPAVAIL_MASK             (0x8U)
#define PKC_PKC_VERSION_UPAVAIL_SHIFT            (3U)
#define PKC_PKC_VERSION_UPAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK)

#define PKC_PKC_VERSION_UPCACHEAVAIL_MASK        (0x10U)
#define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT       (4U)
#define PKC_PKC_VERSION_UPCACHEAVAIL(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK)

#define PKC_PKC_VERSION_GF2AVAIL_MASK            (0x20U)
#define PKC_PKC_VERSION_GF2AVAIL_SHIFT           (5U)
#define PKC_PKC_VERSION_GF2AVAIL(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK)

#define PKC_PKC_VERSION_PARAMNUM_MASK            (0xC0U)
#define PKC_PKC_VERSION_PARAMNUM_SHIFT           (6U)
#define PKC_PKC_VERSION_PARAMNUM(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK)

#define PKC_PKC_VERSION_SBX0AVAIL_MASK           (0x100U)
#define PKC_PKC_VERSION_SBX0AVAIL_SHIFT          (8U)
#define PKC_PKC_VERSION_SBX0AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK)

#define PKC_PKC_VERSION_SBX1AVAIL_MASK           (0x200U)
#define PKC_PKC_VERSION_SBX1AVAIL_SHIFT          (9U)
#define PKC_PKC_VERSION_SBX1AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK)

#define PKC_PKC_VERSION_SBX2AVAIL_MASK           (0x400U)
#define PKC_PKC_VERSION_SBX2AVAIL_SHIFT          (10U)
#define PKC_PKC_VERSION_SBX2AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK)

#define PKC_PKC_VERSION_SBX3AVAIL_MASK           (0x800U)
#define PKC_PKC_VERSION_SBX3AVAIL_SHIFT          (11U)
#define PKC_PKC_VERSION_SBX3AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK)

#define PKC_PKC_VERSION_MCRECONF_SIZE_MASK       (0xFF000U)
#define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT      (12U)
#define PKC_PKC_VERSION_MCRECONF_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK)
/*! @} */

/*! @name PKC_SOFT_RST - Software reset */
/*! @{ */

#define PKC_PKC_SOFT_RST_SOFT_RST_MASK           (0x1U)
#define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT          (0U)
#define PKC_PKC_SOFT_RST_SOFT_RST(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK)
/*! @} */

/*! @name PKC_ACCESS_ERR - Access Error */
/*! @{ */

#define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK        (0x1U)
#define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT       (0U)
/*! APB_NOTAV - APB Error */
#define PKC_PKC_ACCESS_ERR_APB_NOTAV(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK)

#define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK        (0x2U)
#define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT       (1U)
/*! APB_WRGMD - APB Error */
#define PKC_PKC_ACCESS_ERR_APB_WRGMD(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK)

#define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK       (0xF0U)
#define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT      (4U)
#define PKC_PKC_ACCESS_ERR_APB_MASTER(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK)

#define PKC_PKC_ACCESS_ERR_AHB_MASK              (0x400U)
#define PKC_PKC_ACCESS_ERR_AHB_SHIFT             (10U)
/*! AHB - AHB Error */
#define PKC_PKC_ACCESS_ERR_AHB(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK)

#define PKC_PKC_ACCESS_ERR_PKCC_MASK             (0x10000U)
#define PKC_PKC_ACCESS_ERR_PKCC_SHIFT            (16U)
#define PKC_PKC_ACCESS_ERR_PKCC(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK)

#define PKC_PKC_ACCESS_ERR_FDET_MASK             (0x20000U)
#define PKC_PKC_ACCESS_ERR_FDET_SHIFT            (17U)
#define PKC_PKC_ACCESS_ERR_FDET(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK)

#define PKC_PKC_ACCESS_ERR_CTRL_MASK             (0x40000U)
#define PKC_PKC_ACCESS_ERR_CTRL_SHIFT            (18U)
#define PKC_PKC_ACCESS_ERR_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK)

#define PKC_PKC_ACCESS_ERR_UCRC_MASK             (0x80000U)
#define PKC_PKC_ACCESS_ERR_UCRC_SHIFT            (19U)
#define PKC_PKC_ACCESS_ERR_UCRC(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK)
/*! @} */

/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */
/*! @{ */

#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK      (0x1U)
#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT     (0U)
#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK)
/*! @} */

/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */
/*! @{ */

#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK     (0x1U)
#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT    (0U)
#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x)       (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK)
/*! @} */

/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */
/*! @{ */

#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK     (0x1U)
#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT    (0U)
#define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x)       (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK)
/*! @} */

/*! @name PKC_INT_STATUS - Interrupt status */
/*! @{ */

#define PKC_PKC_INT_STATUS_INT_PDONE_MASK        (0x1U)
#define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT       (0U)
/*! INT_PDONE - End-of-computation status flag */
#define PKC_PKC_INT_STATUS_INT_PDONE(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK)
/*! @} */

/*! @name PKC_INT_ENABLE - Interrupt enable */
/*! @{ */

#define PKC_PKC_INT_ENABLE_EN_PDONE_MASK         (0x1U)
#define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT        (0U)
/*! EN_PDONE - PDONE interrupt enable flag */
#define PKC_PKC_INT_ENABLE_EN_PDONE(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK)
/*! @} */

/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */
/*! @{ */

#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK    (0x1U)
#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT   (0U)
#define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK)
/*! @} */

/*! @name PKC_INT_SET_STATUS - Interrupt status set */
/*! @{ */

#define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK    (0x1U)
#define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT   (0U)
#define PKC_PKC_INT_SET_STATUS_INT_PDONE(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK)
/*! @} */

/*! @name PKC_MODULE_ID - Module ID */
/*! @{ */

#define PKC_PKC_MODULE_ID_SIZE_MASK              (0xFFU)
#define PKC_PKC_MODULE_ID_SIZE_SHIFT             (0U)
#define PKC_PKC_MODULE_ID_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK)

#define PKC_PKC_MODULE_ID_MINOR_REV_MASK         (0xF00U)
#define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT        (8U)
#define PKC_PKC_MODULE_ID_MINOR_REV(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK)

#define PKC_PKC_MODULE_ID_MAJOR_REV_MASK         (0xF000U)
#define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT        (12U)
#define PKC_PKC_MODULE_ID_MAJOR_REV(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK)

#define PKC_PKC_MODULE_ID_ID_MASK                (0xFFFF0000U)
#define PKC_PKC_MODULE_ID_ID_SHIFT               (16U)
#define PKC_PKC_MODULE_ID_ID(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PKC_Register_Masks */


/* PKC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PKC base address */
  #define PKC_BASE                                 (0x50011000u)
  /** Peripheral PKC base address */
  #define PKC_BASE_NS                              (0x40011000u)
  /** Peripheral PKC base pointer */
  #define PKC                                      ((PKC_Type *)PKC_BASE)
  /** Peripheral PKC base pointer */
  #define PKC_NS                                   ((PKC_Type *)PKC_BASE_NS)
  /** Array initializer of PKC peripheral base addresses */
  #define PKC_BASE_ADDRS                           { PKC_BASE }
  /** Array initializer of PKC peripheral base pointers */
  #define PKC_BASE_PTRS                            { PKC }
  /** Array initializer of PKC peripheral base addresses */
  #define PKC_BASE_ADDRS_NS                        { PKC_BASE_NS }
  /** Array initializer of PKC peripheral base pointers */
  #define PKC_BASE_PTRS_NS                         { PKC_NS }
#else
  /** Peripheral PKC base address */
  #define PKC_BASE                                 (0x40011000u)
  /** Peripheral PKC base pointer */
  #define PKC                                      ((PKC_Type *)PKC_BASE)
  /** Array initializer of PKC peripheral base addresses */
  #define PKC_BASE_ADDRS                           { PKC_BASE }
  /** Array initializer of PKC peripheral base pointers */
  #define PKC_BASE_PTRS                            { PKC }
#endif

/*!
 * @}
 */ /* end of group PKC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PMC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
 * @{
 */

/** PMC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< PMC Version and Feature ID, offset: 0x0 */
  __I  uint32_t STATUS;                            /**< PMC Status, offset: 0x4 */
  __IO uint32_t FLAGS;                             /**< PMC Flags in Compute Domain, offset: 0x8 */
  __IO uint32_t CTRL;                              /**< Control, offset: 0xC */
  __IO uint32_t INTRCTRL;                          /**< Interrupt Control in Compute Domain, offset: 0x10 */
       uint8_t RESERVED_0[12];
  __IO uint32_t DCDCVSEL;                          /**< DCDC Voltage Selection, offset: 0x20 */
  __IO uint32_t LDOVDD2VSEL;                       /**< LDO VDD2 Voltage Selection, offset: 0x24 */
  __IO uint32_t LDOVDD1VSEL;                       /**< LDO VDD1 Voltage Selection, offset: 0x28 */
  __IO uint32_t LVDVDDNCTRL;                       /**< VDDN LVD Control, offset: 0x2C */
  __IO uint32_t LVDVDD2CTRL;                       /**< VDD2 LVD Control, offset: 0x30 */
  __IO uint32_t LVDVDD1CTRL;                       /**< VDD1 LVD Control, offset: 0x34 */
  __IO uint32_t PORCTRL;                           /**< Power-on Reset Control, offset: 0x38 */
       uint8_t RESERVED_1[4];
  __IO uint32_t BBCTRL;                            /**< Body Bias Control, offset: 0x40 */
  __IO uint32_t TSENSOR;                           /**< Temperature Sensor Control, offset: 0x44 */
       uint8_t RESERVED_2[8];
  __IO uint32_t WAKEUP;                            /**< Wake-up Configuration for Compute Domain, offset: 0x50 */
       uint8_t RESERVED_3[16];
  __IO uint32_t POWERCFG;                          /**< Power Configuration, offset: 0x64 */
  __IO uint32_t PADVRANGE;                         /**< 3 V Capable VDDIO Range Select, offset: 0x68 */
  __IO uint32_t PADCFG;                            /**< IO Bank State Configuration, offset: 0x6C */
       uint8_t RESERVED_4[48];
  __IO uint32_t PDRUNCFG0;                         /**< PD Run Configuration 0 in Compute Domain, offset: 0xA0 */
  __IO uint32_t PDRUNCFG1;                         /**< PD Run Configuration 1 in Compute Domain, offset: 0xA4 */
  __IO uint32_t PDRUNCFG2;                         /**< PD Run Configuration 2 in Compute Domain, offset: 0xA8 */
  __IO uint32_t PDRUNCFG3;                         /**< PD Run Configuration 3 in Compute Domain, offset: 0xAC */
  __IO uint32_t PDRUNCFG4;                         /**< PD Run Configuration 4 in Compute Domain, offset: 0xB0 */
  __IO uint32_t PDRUNCFG5;                         /**< PD Run Configuration 5 in Compute Domain, offset: 0xB4 */
  __IO uint32_t PDSLEEPCFG0;                       /**< PD Sleep Configuration 0 in Compute Domain, offset: 0xB8 */
  __IO uint32_t PDSLEEPCFG1;                       /**< PD Sleep Configuration 1 in Compute Domain, offset: 0xBC */
  __IO uint32_t PDSLEEPCFG2;                       /**< PD Sleep Configuration 2 in Compute Domain, offset: 0xC0 */
  __IO uint32_t PDSLEEPCFG3;                       /**< PD Sleep Configuration 3 in Compute Domain, offset: 0xC4 */
  __IO uint32_t PDSLEEPCFG4;                       /**< PD Sleep Configuration 4 in Compute Domain, offset: 0xC8 */
  __IO uint32_t PDSLEEPCFG5;                       /**< PD Sleep Configuration 5 in Compute Domain, offset: 0xCC */
  __I  uint32_t PDCFGSTATUS0;                      /**< PD Configuration Status 0, offset: 0xD0 */
  __I  uint32_t PDCFGSTATUS1;                      /**< PD Configuration Status 1, offset: 0xD4 */
  __I  uint32_t PDCFGSTATUS2;                      /**< PD Configuration Status 2, offset: 0xD8 */
  __I  uint32_t PDCFGSTATUS3;                      /**< PD Configuration Status 3, offset: 0xDC */
  __I  uint32_t PDCFGSTATUS4;                      /**< PD Configuration Status 4, offset: 0xE0 */
  __I  uint32_t PDCFGSTATUS5;                      /**< PD Configuration Status 5, offset: 0xE4 */
  __IO uint32_t PDWAKECFG;                         /**< PD Wake-up Configuration for Compute Domain, offset: 0xE8 */
  __IO uint32_t PWRFLAGS;                          /**< Power Domain Flags for Compute Domain, offset: 0xEC */
} PMC_Type;

/* ----------------------------------------------------------------------------
   -- PMC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PMC_Register_Masks PMC Register Masks
 * @{
 */

/*! @name VERID - PMC Version and Feature ID */
/*! @{ */

#define PMC_VERID_FEATURE_MASK                   (0xFFFFU)
#define PMC_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Identification Number */
#define PMC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_VERID_FEATURE_SHIFT)) & PMC_VERID_FEATURE_MASK)

#define PMC_VERID_MINOR_MASK                     (0xFF0000U)
#define PMC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define PMC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_VERID_MINOR_SHIFT)) & PMC_VERID_MINOR_MASK)

#define PMC_VERID_MAJOR_MASK                     (0xFF000000U)
#define PMC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define PMC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_VERID_MAJOR_SHIFT)) & PMC_VERID_MAJOR_MASK)
/*! @} */

/*! @name STATUS - PMC Status */
/*! @{ */

#define PMC_STATUS_BUSY_MASK                     (0x1U)
#define PMC_STATUS_BUSY_SHIFT                    (0U)
/*! BUSY - Finite State Machine Status
 *  0b1..PMC state machine is busy
 *  0b0..PMC state machines are idle
 */
#define PMC_STATUS_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BUSY_SHIFT)) & PMC_STATUS_BUSY_MASK)

#define PMC_STATUS_LVDVDD1_MASK                  (0x40000U)
#define PMC_STATUS_LVDVDD1_SHIFT                 (18U)
/*! LVDVDD1 - VDD1 Low-Voltage Detector
 *  0b1..Detector is tripped
 *  0b0..Detector is not tripped
 */
#define PMC_STATUS_LVDVDD1(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_LVDVDD1_SHIFT)) & PMC_STATUS_LVDVDD1_MASK)

#define PMC_STATUS_LVDVDD2_MASK                  (0x80000U)
#define PMC_STATUS_LVDVDD2_SHIFT                 (19U)
/*! LVDVDD2 - VDD2 Low-Voltage Detector
 *  0b1..Detector is tripped
 *  0b0..Detector is not tripped
 */
#define PMC_STATUS_LVDVDD2(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_LVDVDD2_SHIFT)) & PMC_STATUS_LVDVDD2_MASK)

#define PMC_STATUS_LVDVDDN_MASK                  (0x100000U)
#define PMC_STATUS_LVDVDDN_SHIFT                 (20U)
/*! LVDVDDN - VDDN Low-Voltage Detector
 *  0b1..Detector is tripped
 *  0b0..Detector is not tripped
 */
#define PMC_STATUS_LVDVDDN(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_LVDVDDN_SHIFT)) & PMC_STATUS_LVDVDDN_MASK)

#define PMC_STATUS_HVDVDD1_MASK                  (0x200000U)
#define PMC_STATUS_HVDVDD1_SHIFT                 (21U)
/*! HVDVDD1 - VDD1 High-Voltage Detector
 *  0b1..Detector is tripped
 *  0b0..Detector is not tripped
 */
#define PMC_STATUS_HVDVDD1(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_HVDVDD1_SHIFT)) & PMC_STATUS_HVDVDD1_MASK)

#define PMC_STATUS_HVDVDD2_MASK                  (0x400000U)
#define PMC_STATUS_HVDVDD2_SHIFT                 (22U)
/*! HVDVDD2 - VDD2 High-Voltage Detector
 *  0b1..Detector is tripped
 *  0b0..Detector is not tripped
 */
#define PMC_STATUS_HVDVDD2(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_HVDVDD2_SHIFT)) & PMC_STATUS_HVDVDD2_MASK)

#define PMC_STATUS_HVDVDDN_MASK                  (0x800000U)
#define PMC_STATUS_HVDVDDN_SHIFT                 (23U)
/*! HVDVDDN - VDDN High-Voltage Detector
 *  0b1..Detector is tripped
 *  0b0..Detector is not tripped
 */
#define PMC_STATUS_HVDVDDN(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_HVDVDDN_SHIFT)) & PMC_STATUS_HVDVDDN_MASK)

#define PMC_STATUS_HVD1V8_MASK                   (0x1000000U)
#define PMC_STATUS_HVD1V8_SHIFT                  (24U)
/*! HVD1V8 - VDD1V8 High-Voltage Detector
 *  0b1..Detector is tripped
 *  0b0..Detector is not tripped
 */
#define PMC_STATUS_HVD1V8(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_HVD1V8_SHIFT)) & PMC_STATUS_HVD1V8_MASK)

#define PMC_STATUS_RTCWKUP_MASK                  (0x2000000U)
#define PMC_STATUS_RTCWKUP_SHIFT                 (25U)
/*! RTCWKUP - RTC Wake-up
 *  0b1..Compute RTC wake-up is asserted
 *  0b0..Compute RTC wake-up is not active
 */
#define PMC_STATUS_RTCWKUP(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_RTCWKUP_SHIFT)) & PMC_STATUS_RTCWKUP_MASK)

#define PMC_STATUS_INTN_MASK                     (0x8000000U)
#define PMC_STATUS_INTN_SHIFT                    (27U)
/*! INTN - PMIC_IRQN Interrupt Input
 *  0b1..Asserted. Pin is low
 *  0b0..Negated. Pin is high
 */
#define PMC_STATUS_INTN(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_INTN_SHIFT)) & PMC_STATUS_INTN_MASK)

#define PMC_STATUS_DSSENS_MASK                   (0x20000000U)
#define PMC_STATUS_DSSENS_SHIFT                  (29U)
/*! DSSENS - CPU1 Deep Sleep
 *  0b1..CPU1 is in Deep Sleep mode
 *  0b0..CPU1 is in Active mode
 */
#define PMC_STATUS_DSSENS(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_DSSENS_SHIFT)) & PMC_STATUS_DSSENS_MASK)
/*! @} */

/*! @name FLAGS - PMC Flags in Compute Domain */
/*! @{ */

#define PMC_FLAGS_DSALLF_MASK                    (0x1U)
#define PMC_FLAGS_DSALLF_SHIFT                   (0U)
/*! DSALLF - Deep Sleep Flag
 *  0b0..CPU0 and CPU1 are not in Deep Sleep mode at the same time
 *  0b1..CPU0 and CPU1 have both been in Deep Sleep mode at the same time
 */
#define PMC_FLAGS_DSALLF(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_DSALLF_SHIFT)) & PMC_FLAGS_DSALLF_MASK)

#define PMC_FLAGS_ITRCRF_MASK                    (0x2U)
#define PMC_FLAGS_ITRCRF_SHIFT                   (1U)
/*! ITRCRF - ITRC RAM ZEROIZE Flag
 *  0b0..Not detected
 *  0b1..ITRC RAM ZEROIZE detected
 */
#define PMC_FLAGS_ITRCRF(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_ITRCRF_SHIFT)) & PMC_FLAGS_ITRCRF_MASK)

#define PMC_FLAGS_BBSR1EF_MASK                   (0x4U)
#define PMC_FLAGS_BBSR1EF_SHIFT                  (2U)
/*! BBSR1EF - VDD1 SRAM Body Bias Error Flag
 *  0b0..No SRAM body bias error
 *  0b1..SRAM body bias error detected
 */
#define PMC_FLAGS_BBSR1EF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_BBSR1EF_SHIFT)) & PMC_FLAGS_BBSR1EF_MASK)

#define PMC_FLAGS_BBSR2EF_MASK                   (0x8U)
#define PMC_FLAGS_BBSR2EF_SHIFT                  (3U)
/*! BBSR2EF - VDD2 SRAM Body Bias Error Flag
 *  0b0..No SRAM body bias error
 *  0b1..SRAM body bias error detected
 */
#define PMC_FLAGS_BBSR2EF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_BBSR2EF_SHIFT)) & PMC_FLAGS_BBSR2EF_MASK)

#define PMC_FLAGS_BB1EF_MASK                     (0x10U)
#define PMC_FLAGS_BB1EF_SHIFT                    (4U)
/*! BB1EF - VDD1 Body Bias Error Flag
 *  0b0..No body bias error
 *  0b1..Body bias error detected
 */
#define PMC_FLAGS_BB1EF(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_BB1EF_SHIFT)) & PMC_FLAGS_BB1EF_MASK)

#define PMC_FLAGS_BB2EF_MASK                     (0x20U)
#define PMC_FLAGS_BB2EF_SHIFT                    (5U)
/*! BB2EF - VDD2 Body Bias Error Flag
 *  0b0..No body bias error
 *  0b1..Body bias error detected
 */
#define PMC_FLAGS_BB2EF(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_BB2EF_SHIFT)) & PMC_FLAGS_BB2EF_MASK)

#define PMC_FLAGS_BBNEF_MASK                     (0x40U)
#define PMC_FLAGS_BBNEF_SHIFT                    (6U)
/*! BBNEF - VDDN Body Bias Error Flag
 *  0b0..No body bias error
 *  0b1..Body bias error detected
 */
#define PMC_FLAGS_BBNEF(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_BBNEF_SHIFT)) & PMC_FLAGS_BBNEF_MASK)

#define PMC_FLAGS_SCP1OCF_MASK                   (0x80U)
#define PMC_FLAGS_SCP1OCF_SHIFT                  (7U)
/*! SCP1OCF - SCPC VDD1 Overcurrent Flag
 *  0b0..No overcurrent event detected
 *  0b1..Overcurrent event detected
 */
#define PMC_FLAGS_SCP1OCF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_SCP1OCF_SHIFT)) & PMC_FLAGS_SCP1OCF_MASK)

#define PMC_FLAGS_SCP2OCF_MASK                   (0x100U)
#define PMC_FLAGS_SCP2OCF_SHIFT                  (8U)
/*! SCP2OCF - SCPC VDD2 Overcurrent Flag
 *  0b0..No overcurrent event detected
 *  0b1..Overcurrent event detected
 */
#define PMC_FLAGS_SCP2OCF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_SCP2OCF_SHIFT)) & PMC_FLAGS_SCP2OCF_MASK)

#define PMC_FLAGS_DCHPOCF_MASK                   (0x200U)
#define PMC_FLAGS_DCHPOCF_SHIFT                  (9U)
/*! DCHPOCF - DCDC High-Power Mode Overcurrent Flag
 *  0b0..No overcurrent event detected
 *  0b1..Overcurrent event detected
 */
#define PMC_FLAGS_DCHPOCF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_DCHPOCF_SHIFT)) & PMC_FLAGS_DCHPOCF_MASK)

#define PMC_FLAGS_DCLPOCF_MASK                   (0x400U)
#define PMC_FLAGS_DCLPOCF_SHIFT                  (10U)
/*! DCLPOCF - DCDC Low-Power Mode Overcurrent Flag
 *  0b0..No overcurrent event detected
 *  0b1..Overcurrent event detected
 */
#define PMC_FLAGS_DCLPOCF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_DCLPOCF_SHIFT)) & PMC_FLAGS_DCLPOCF_MASK)

#define PMC_FLAGS_PORVDD1F_MASK                  (0x800U)
#define PMC_FLAGS_PORVDD1F_SHIFT                 (11U)
/*! PORVDD1F - VDD1 Power-on Reset Flag
 *  0b0..POR status cleared
 *  0b1..POR status asserted
 */
#define PMC_FLAGS_PORVDD1F(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_PORVDD1F_SHIFT)) & PMC_FLAGS_PORVDD1F_MASK)

#define PMC_FLAGS_PORVDD2F_MASK                  (0x1000U)
#define PMC_FLAGS_PORVDD2F_SHIFT                 (12U)
/*! PORVDD2F - VDD2 Power-on Reset Flag
 *  0b0..POR status cleared
 *  0b1..POR status asserted
 */
#define PMC_FLAGS_PORVDD2F(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_PORVDD2F_SHIFT)) & PMC_FLAGS_PORVDD2F_MASK)

#define PMC_FLAGS_PORVDDNF_MASK                  (0x2000U)
#define PMC_FLAGS_PORVDDNF_SHIFT                 (13U)
/*! PORVDDNF - VDDN Power-on Reset Flag
 *  0b0..POR status cleared
 *  0b1..POR status asserted
 */
#define PMC_FLAGS_PORVDDNF(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_PORVDDNF_SHIFT)) & PMC_FLAGS_PORVDDNF_MASK)

#define PMC_FLAGS_POR1V8F_MASK                   (0x4000U)
#define PMC_FLAGS_POR1V8F_SHIFT                  (14U)
/*! POR1V8F - VDD1V8 Power-on Reset Flag
 *  0b0..POR status cleared
 *  0b1..POR status asserted
 */
#define PMC_FLAGS_POR1V8F(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_POR1V8F_SHIFT)) & PMC_FLAGS_POR1V8F_MASK)

#define PMC_FLAGS_PORAO18F_MASK                  (0x8000U)
#define PMC_FLAGS_PORAO18F_SHIFT                 (15U)
/*! PORAO18F - VDD1V8_AO Power-on Reset Flag
 *  0b0..POR status cleared
 *  0b1..POR status asserted
 */
#define PMC_FLAGS_PORAO18F(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_PORAO18F_SHIFT)) & PMC_FLAGS_PORAO18F_MASK)

#define PMC_FLAGS_AGDET1F_MASK                   (0x10000U)
#define PMC_FLAGS_AGDET1F_SHIFT                  (16U)
/*! AGDET1F - VDD1 Glitch Detector Flag
 *  0b0..Glitch detector status cleared
 *  0b1..Glitch detector status asserted
 */
#define PMC_FLAGS_AGDET1F(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_AGDET1F_SHIFT)) & PMC_FLAGS_AGDET1F_MASK)

#define PMC_FLAGS_AGDET2F_MASK                   (0x20000U)
#define PMC_FLAGS_AGDET2F_SHIFT                  (17U)
/*! AGDET2F - VDD2 Glitch Detector Flag
 *  0b0..Glitch detector status cleared
 *  0b1..Glitch detector status asserted
 */
#define PMC_FLAGS_AGDET2F(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_AGDET2F_SHIFT)) & PMC_FLAGS_AGDET2F_MASK)

#define PMC_FLAGS_LVDVDD1F_MASK                  (0x40000U)
#define PMC_FLAGS_LVDVDD1F_SHIFT                 (18U)
/*! LVDVDD1F - VDD1 Low-Voltage Detector Flag
 *  0b0..Low-voltage detector status cleared
 *  0b1..Low-voltage detector status asserted
 */
#define PMC_FLAGS_LVDVDD1F(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_LVDVDD1F_SHIFT)) & PMC_FLAGS_LVDVDD1F_MASK)

#define PMC_FLAGS_LVDVDD2F_MASK                  (0x80000U)
#define PMC_FLAGS_LVDVDD2F_SHIFT                 (19U)
/*! LVDVDD2F - VDD2 Low-Voltage Detector Flag
 *  0b0..Low-voltage detector status cleared
 *  0b1..Low-voltage detector status asserted
 */
#define PMC_FLAGS_LVDVDD2F(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_LVDVDD2F_SHIFT)) & PMC_FLAGS_LVDVDD2F_MASK)

#define PMC_FLAGS_LVDVDDNF_MASK                  (0x100000U)
#define PMC_FLAGS_LVDVDDNF_SHIFT                 (20U)
/*! LVDVDDNF - VDDN Low-Voltage Detector Flag
 *  0b0..Low-voltage detector status cleared
 *  0b1..Low-voltage detector status asserted
 */
#define PMC_FLAGS_LVDVDDNF(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_LVDVDDNF_SHIFT)) & PMC_FLAGS_LVDVDDNF_MASK)

#define PMC_FLAGS_HVDVDD1F_MASK                  (0x200000U)
#define PMC_FLAGS_HVDVDD1F_SHIFT                 (21U)
/*! HVDVDD1F - VDD1 High-Voltage Detector Flag
 *  0b0..High-voltage detector status cleared
 *  0b1..High-voltage detector status asserted
 */
#define PMC_FLAGS_HVDVDD1F(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_HVDVDD1F_SHIFT)) & PMC_FLAGS_HVDVDD1F_MASK)

#define PMC_FLAGS_HVDVDD2F_MASK                  (0x400000U)
#define PMC_FLAGS_HVDVDD2F_SHIFT                 (22U)
/*! HVDVDD2F - VDD2 High-Voltage Detector Flag
 *  0b0..High-voltage detector status cleared
 *  0b1..High-voltage detector status asserted
 */
#define PMC_FLAGS_HVDVDD2F(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_HVDVDD2F_SHIFT)) & PMC_FLAGS_HVDVDD2F_MASK)

#define PMC_FLAGS_HVDVDDNF_MASK                  (0x800000U)
#define PMC_FLAGS_HVDVDDNF_SHIFT                 (23U)
/*! HVDVDDNF - VDDN High-Voltage Detector Flag
 *  0b0..High-voltage detector status cleared
 *  0b1..High-voltage detector status asserted
 */
#define PMC_FLAGS_HVDVDDNF(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_HVDVDDNF_SHIFT)) & PMC_FLAGS_HVDVDDNF_MASK)

#define PMC_FLAGS_HVD1V8F_MASK                   (0x1000000U)
#define PMC_FLAGS_HVD1V8F_SHIFT                  (24U)
/*! HVD1V8F - VDD1V8 High-Voltage Detector Flag
 *  0b0..High-voltage detector status cleared
 *  0b1..High-voltage detector status asserted
 */
#define PMC_FLAGS_HVD1V8F(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_HVD1V8F_SHIFT)) & PMC_FLAGS_HVD1V8F_MASK)

#define PMC_FLAGS_RTCF_MASK                      (0x2000000U)
#define PMC_FLAGS_RTCF_SHIFT                     (25U)
/*! RTCF - RTC Flag
 *  0b0..RTC status cleared
 *  0b1..RTC status asserted
 */
#define PMC_FLAGS_RTCF(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_RTCF_SHIFT)) & PMC_FLAGS_RTCF_MASK)

#define PMC_FLAGS_AUTOWKF_MASK                   (0x4000000U)
#define PMC_FLAGS_AUTOWKF_SHIFT                  (26U)
/*! AUTOWKF - Auto Wake-up Flag
 *  0b0..Auto wake-up status cleared
 *  0b1..Auto wake-up status asserted
 */
#define PMC_FLAGS_AUTOWKF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_AUTOWKF_SHIFT)) & PMC_FLAGS_AUTOWKF_MASK)

#define PMC_FLAGS_INTNF_MASK                     (0x8000000U)
#define PMC_FLAGS_INTNF_SHIFT                    (27U)
/*! INTNF - PMIC_IRQN Interrupt Pin Flag
 *  0b0..Interrupt pin status cleared
 *  0b1..Interrupt pin status asserted
 */
#define PMC_FLAGS_INTNF(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_INTNF_SHIFT)) & PMC_FLAGS_INTNF_MASK)

#define PMC_FLAGS_RESETNF_MASK                   (0x10000000U)
#define PMC_FLAGS_RESETNF_SHIFT                  (28U)
/*! RESETNF - Reset Pin Flag
 *  0b0..Reset pin status cleared
 *  0b1..Reset pin status asserted
 */
#define PMC_FLAGS_RESETNF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_RESETNF_SHIFT)) & PMC_FLAGS_RESETNF_MASK)

#define PMC_FLAGS_DSSENSF_MASK                   (0x20000000U)
#define PMC_FLAGS_DSSENSF_SHIFT                  (29U)
/*! DSSENSF - CPU1 Deep Sleep Mode Flag
 *  0b0..CPU1 Deep Sleep cleared
 *  0b1..CPU1 Deep Sleep asserted
 */
#define PMC_FLAGS_DSSENSF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_DSSENSF_SHIFT)) & PMC_FLAGS_DSSENSF_MASK)

#define PMC_FLAGS_DSCOMPF_MASK                   (0x40000000U)
#define PMC_FLAGS_DSCOMPF_SHIFT                  (30U)
/*! DSCOMPF - CPU0 Deep Sleep Flag
 *  0b0..CPU0 Deep Sleep cleared
 *  0b1..CPU0 Deep Sleep asserted
 */
#define PMC_FLAGS_DSCOMPF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_DSCOMPF_SHIFT)) & PMC_FLAGS_DSCOMPF_MASK)

#define PMC_FLAGS_DEEPPDF_MASK                   (0x80000000U)
#define PMC_FLAGS_DEEPPDF_SHIFT                  (31U)
/*! DEEPPDF - DPD Wake-up Flag
 *  0b0..DPD wake-up cleared
 *  0b1..DPD wake-up asserted
 */
#define PMC_FLAGS_DEEPPDF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_DEEPPDF_SHIFT)) & PMC_FLAGS_DEEPPDF_MASK)
/*! @} */

/*! @name CTRL - Control */
/*! @{ */

#define PMC_CTRL_APPLYCFG_MASK                   (0x1U)
#define PMC_CTRL_APPLYCFG_SHIFT                  (0U)
/*! APPLYCFG - Apply Configure for PMC0
 *  0b1..Start configuration change, or operation has not completed
 *  0b0..Operation is done
 */
#define PMC_CTRL_APPLYCFG(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_APPLYCFG_SHIFT)) & PMC_CTRL_APPLYCFG_MASK)

#define PMC_CTRL_AGDET1RE_MASK                   (0x10000U)
#define PMC_CTRL_AGDET1RE_SHIFT                  (16U)
/*! AGDET1RE - VDD1 Glitch Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_AGDET1RE(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_AGDET1RE_SHIFT)) & PMC_CTRL_AGDET1RE_MASK)

#define PMC_CTRL_AGDET2RE_MASK                   (0x20000U)
#define PMC_CTRL_AGDET2RE_SHIFT                  (17U)
/*! AGDET2RE - VDD2 Glitch Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_AGDET2RE(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_AGDET2RE_SHIFT)) & PMC_CTRL_AGDET2RE_MASK)

#define PMC_CTRL_LVD1RE_MASK                     (0x40000U)
#define PMC_CTRL_LVD1RE_SHIFT                    (18U)
/*! LVD1RE - VDD1 Low-Voltage Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_LVD1RE(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_LVD1RE_SHIFT)) & PMC_CTRL_LVD1RE_MASK)

#define PMC_CTRL_LVD2RE_MASK                     (0x80000U)
#define PMC_CTRL_LVD2RE_SHIFT                    (19U)
/*! LVD2RE - VDD2 Low-Voltage Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_LVD2RE(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_LVD2RE_SHIFT)) & PMC_CTRL_LVD2RE_MASK)

#define PMC_CTRL_LVDNRE_MASK                     (0x100000U)
#define PMC_CTRL_LVDNRE_SHIFT                    (20U)
/*! LVDNRE - VDDN Low-Voltage Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_LVDNRE(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_LVDNRE_SHIFT)) & PMC_CTRL_LVDNRE_MASK)

#define PMC_CTRL_HVDV1RE_MASK                    (0x200000U)
#define PMC_CTRL_HVDV1RE_SHIFT                   (21U)
/*! HVDV1RE - VDD1 High-Voltage Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_HVDV1RE(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_HVDV1RE_SHIFT)) & PMC_CTRL_HVDV1RE_MASK)

#define PMC_CTRL_HVDV2RE_MASK                    (0x400000U)
#define PMC_CTRL_HVDV2RE_SHIFT                   (22U)
/*! HVDV2RE - VDD2 High-Voltage Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_HVDV2RE(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_HVDV2RE_SHIFT)) & PMC_CTRL_HVDV2RE_MASK)

#define PMC_CTRL_HVDVNRE_MASK                    (0x800000U)
#define PMC_CTRL_HVDVNRE_SHIFT                   (23U)
/*! HVDVNRE - VDDN High-Voltage Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_HVDVNRE(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_HVDVNRE_SHIFT)) & PMC_CTRL_HVDVNRE_MASK)

#define PMC_CTRL_HVD1V8RE_MASK                   (0x1000000U)
#define PMC_CTRL_HVD1V8RE_SHIFT                  (24U)
/*! HVD1V8RE - VDD1V8 High-Voltage Detector Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_CTRL_HVD1V8RE(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_HVD1V8RE_SHIFT)) & PMC_CTRL_HVD1V8RE_MASK)
/*! @} */

/*! @name INTRCTRL - Interrupt Control in Compute Domain */
/*! @{ */

#define PMC_INTRCTRL_BBSR1EIE_MASK               (0x4U)
#define PMC_INTRCTRL_BBSR1EIE_SHIFT              (2U)
/*! BBSR1EIE - VDD1 SRAM Body Bias Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_BBSR1EIE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_BBSR1EIE_SHIFT)) & PMC_INTRCTRL_BBSR1EIE_MASK)

#define PMC_INTRCTRL_BBSR2EIE_MASK               (0x8U)
#define PMC_INTRCTRL_BBSR2EIE_SHIFT              (3U)
/*! BBSR2EIE - VDD2 SRAM Body Bias Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_BBSR2EIE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_BBSR2EIE_SHIFT)) & PMC_INTRCTRL_BBSR2EIE_MASK)

#define PMC_INTRCTRL_BB1EIE_MASK                 (0x10U)
#define PMC_INTRCTRL_BB1EIE_SHIFT                (4U)
/*! BB1EIE - VDD1 Body Bias Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_BB1EIE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_BB1EIE_SHIFT)) & PMC_INTRCTRL_BB1EIE_MASK)

#define PMC_INTRCTRL_BB2EIE_MASK                 (0x20U)
#define PMC_INTRCTRL_BB2EIE_SHIFT                (5U)
/*! BB2EIE - VDD2 Body Bias Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_BB2EIE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_BB2EIE_SHIFT)) & PMC_INTRCTRL_BB2EIE_MASK)

#define PMC_INTRCTRL_BBNEIE_MASK                 (0x40U)
#define PMC_INTRCTRL_BBNEIE_SHIFT                (6U)
/*! BBNEIE - VDDN Body Bias Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_BBNEIE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_BBNEIE_SHIFT)) & PMC_INTRCTRL_BBNEIE_MASK)

#define PMC_INTRCTRL_SCP1OCIE_MASK               (0x80U)
#define PMC_INTRCTRL_SCP1OCIE_SHIFT              (7U)
/*! SCP1OCIE - SCPC VDD1 Overcurrent Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_SCP1OCIE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_SCP1OCIE_SHIFT)) & PMC_INTRCTRL_SCP1OCIE_MASK)

#define PMC_INTRCTRL_SCP2OCIE_MASK               (0x100U)
#define PMC_INTRCTRL_SCP2OCIE_SHIFT              (8U)
/*! SCP2OCIE - SCPC VDD2 Overcurrent Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_SCP2OCIE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_SCP2OCIE_SHIFT)) & PMC_INTRCTRL_SCP2OCIE_MASK)

#define PMC_INTRCTRL_DCHPOCIE_MASK               (0x200U)
#define PMC_INTRCTRL_DCHPOCIE_SHIFT              (9U)
/*! DCHPOCIE - DCDC High-Power Overcurrent Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_DCHPOCIE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_DCHPOCIE_SHIFT)) & PMC_INTRCTRL_DCHPOCIE_MASK)

#define PMC_INTRCTRL_DCLPOCIE_MASK               (0x400U)
#define PMC_INTRCTRL_DCLPOCIE_SHIFT              (10U)
/*! DCLPOCIE - DCDC Low-Power Overcurrent Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_DCLPOCIE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_DCLPOCIE_SHIFT)) & PMC_INTRCTRL_DCLPOCIE_MASK)

#define PMC_INTRCTRL_AGDET1IE_MASK               (0x10000U)
#define PMC_INTRCTRL_AGDET1IE_SHIFT              (16U)
/*! AGDET1IE - VDD1 Glitch Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_AGDET1IE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_AGDET1IE_SHIFT)) & PMC_INTRCTRL_AGDET1IE_MASK)

#define PMC_INTRCTRL_AGDET2IE_MASK               (0x20000U)
#define PMC_INTRCTRL_AGDET2IE_SHIFT              (17U)
/*! AGDET2IE - VDD2 Glitch Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_AGDET2IE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_AGDET2IE_SHIFT)) & PMC_INTRCTRL_AGDET2IE_MASK)

#define PMC_INTRCTRL_LVD1IE_MASK                 (0x40000U)
#define PMC_INTRCTRL_LVD1IE_SHIFT                (18U)
/*! LVD1IE - VDD1 Low-Voltage Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_LVD1IE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_LVD1IE_SHIFT)) & PMC_INTRCTRL_LVD1IE_MASK)

#define PMC_INTRCTRL_LVD2IE_MASK                 (0x80000U)
#define PMC_INTRCTRL_LVD2IE_SHIFT                (19U)
/*! LVD2IE - VDD2 Low-Voltage Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_LVD2IE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_LVD2IE_SHIFT)) & PMC_INTRCTRL_LVD2IE_MASK)

#define PMC_INTRCTRL_LVDNIE_MASK                 (0x100000U)
#define PMC_INTRCTRL_LVDNIE_SHIFT                (20U)
/*! LVDNIE - VDDN Low-Voltage Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_LVDNIE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_LVDNIE_SHIFT)) & PMC_INTRCTRL_LVDNIE_MASK)

#define PMC_INTRCTRL_HVD1IE_MASK                 (0x200000U)
#define PMC_INTRCTRL_HVD1IE_SHIFT                (21U)
/*! HVD1IE - VDD1 High-Voltage Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_HVD1IE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_HVD1IE_SHIFT)) & PMC_INTRCTRL_HVD1IE_MASK)

#define PMC_INTRCTRL_HVD2IE_MASK                 (0x400000U)
#define PMC_INTRCTRL_HVD2IE_SHIFT                (22U)
/*! HVD2IE - VDD2 High-Voltage Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_HVD2IE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_HVD2IE_SHIFT)) & PMC_INTRCTRL_HVD2IE_MASK)

#define PMC_INTRCTRL_HVDNIE_MASK                 (0x800000U)
#define PMC_INTRCTRL_HVDNIE_SHIFT                (23U)
/*! HVDNIE - VDDN High-Voltage Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_HVDNIE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_HVDNIE_SHIFT)) & PMC_INTRCTRL_HVDNIE_MASK)

#define PMC_INTRCTRL_HVD1V8IE_MASK               (0x1000000U)
#define PMC_INTRCTRL_HVD1V8IE_SHIFT              (24U)
/*! HVD1V8IE - VDD1V8 High-Voltage Detector Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_HVD1V8IE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_HVD1V8IE_SHIFT)) & PMC_INTRCTRL_HVD1V8IE_MASK)

#define PMC_INTRCTRL_AUTOWKIE_MASK               (0x4000000U)
#define PMC_INTRCTRL_AUTOWKIE_SHIFT              (26U)
/*! AUTOWKIE - Auto Wake-up Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_AUTOWKIE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_AUTOWKIE_SHIFT)) & PMC_INTRCTRL_AUTOWKIE_MASK)

#define PMC_INTRCTRL_INTNIE_MASK                 (0x8000000U)
#define PMC_INTRCTRL_INTNIE_SHIFT                (27U)
/*! INTNIE - PMIC_IRQN PAD Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_INTNIE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_INTNIE_SHIFT)) & PMC_INTRCTRL_INTNIE_MASK)

#define PMC_INTRCTRL_DSSENSIE_MASK               (0x20000000U)
#define PMC_INTRCTRL_DSSENSIE_SHIFT              (29U)
/*! DSSENSIE - CPU1 Deep Sleep Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PMC_INTRCTRL_DSSENSIE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_INTRCTRL_DSSENSIE_SHIFT)) & PMC_INTRCTRL_DSSENSIE_MASK)
/*! @} */

/*! @name DCDCVSEL - DCDC Voltage Selection */
/*! @{ */

#define PMC_DCDCVSEL_VSEL0_MASK                  (0x7FU)
#define PMC_DCDCVSEL_VSEL0_SHIFT                 (0U)
/*! VSEL0 - DCDC Voltage Level 0
 *  0b0000000..0.50 V
 *  0b0100000..0.70 V
 *  0b1000000..0.90 V
 *  0b1100000..1.10 V
 *  0b1101000..1.15 V (maximum)
 *  0b1111111..1.15 V (clipped)
 */
#define PMC_DCDCVSEL_VSEL0(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDCVSEL_VSEL0_SHIFT)) & PMC_DCDCVSEL_VSEL0_MASK)

#define PMC_DCDCVSEL_VSEL1_MASK                  (0x7F00U)
#define PMC_DCDCVSEL_VSEL1_SHIFT                 (8U)
/*! VSEL1 - DCDC Voltage Level 1
 *  0b0000000..0.50 V
 *  0b0100000..0.70 V
 *  0b1000000..0.90 V
 *  0b1100000..1.10 V
 *  0b1101000..1.15 V (maximum)
 *  0b1111111..1.15 V (clipped)
 */
#define PMC_DCDCVSEL_VSEL1(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDCVSEL_VSEL1_SHIFT)) & PMC_DCDCVSEL_VSEL1_MASK)
/*! @} */

/*! @name LDOVDD2VSEL - LDO VDD2 Voltage Selection */
/*! @{ */

#define PMC_LDOVDD2VSEL_VSEL0_MASK               (0x3FU)
#define PMC_LDOVDD2VSEL_VSEL0_SHIFT              (0U)
/*! VSEL0 - LDO VDD2 Voltage Level 0
 *  0b000000..0.45 V
 *  0b010000..0.65 V
 *  0b100000..0.85 V
 *  0b110000..1.05 V
 *  0b111000..1.15 V (maximum)
 *  0b111111..1.15 V (clipped)
 */
#define PMC_LDOVDD2VSEL_VSEL0(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOVDD2VSEL_VSEL0_SHIFT)) & PMC_LDOVDD2VSEL_VSEL0_MASK)

#define PMC_LDOVDD2VSEL_VSEL1_MASK               (0x3F00U)
#define PMC_LDOVDD2VSEL_VSEL1_SHIFT              (8U)
/*! VSEL1 - LDO VDD2 Voltage Level 1
 *  0b000000..0.45 V
 *  0b010000..0.65 V
 *  0b100000..0.85 V
 *  0b110000..1.05 V
 *  0b111000..1.15 V (maximum)
 *  0b111111..1.15 V (clipped)
 */
#define PMC_LDOVDD2VSEL_VSEL1(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOVDD2VSEL_VSEL1_SHIFT)) & PMC_LDOVDD2VSEL_VSEL1_MASK)

#define PMC_LDOVDD2VSEL_VSEL2_MASK               (0x3F0000U)
#define PMC_LDOVDD2VSEL_VSEL2_SHIFT              (16U)
/*! VSEL2 - LDO VDD2 Voltage Level 2
 *  0b000000..0.45 V
 *  0b010000..0.65 V
 *  0b100000..0.85 V
 *  0b110000..1.05 V
 *  0b111000..1.15 V (maximum)
 *  0b111111..1.15 V (clipped)
 */
#define PMC_LDOVDD2VSEL_VSEL2(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOVDD2VSEL_VSEL2_SHIFT)) & PMC_LDOVDD2VSEL_VSEL2_MASK)

#define PMC_LDOVDD2VSEL_VSEL3_MASK               (0x3F000000U)
#define PMC_LDOVDD2VSEL_VSEL3_SHIFT              (24U)
/*! VSEL3 - LDO VDD2 Voltage Level 3
 *  0b000000..0.45 V
 *  0b010000..0.65 V
 *  0b100000..0.85 V
 *  0b110000..1.05 V
 *  0b111000..1.15 V (maximum)
 *  0b111111..1.15 V (clipped)
 */
#define PMC_LDOVDD2VSEL_VSEL3(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOVDD2VSEL_VSEL3_SHIFT)) & PMC_LDOVDD2VSEL_VSEL3_MASK)
/*! @} */

/*! @name LDOVDD1VSEL - LDO VDD1 Voltage Selection */
/*! @{ */

#define PMC_LDOVDD1VSEL_VSEL0_MASK               (0x3FU)
#define PMC_LDOVDD1VSEL_VSEL0_SHIFT              (0U)
/*! VSEL0 - LDO VDD1 Voltage Level 0
 *  0b000000..0.45 V
 *  0b010000..0.65 V
 *  0b100000..0.85 V
 *  0b110000..1.05 V
 *  0b111000..1.15 V (maximum)
 *  0b111111..1.15 V (clipped)
 */
#define PMC_LDOVDD1VSEL_VSEL0(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOVDD1VSEL_VSEL0_SHIFT)) & PMC_LDOVDD1VSEL_VSEL0_MASK)

#define PMC_LDOVDD1VSEL_VSEL1_MASK               (0x3F00U)
#define PMC_LDOVDD1VSEL_VSEL1_SHIFT              (8U)
/*! VSEL1 - LDO VDD1 Voltage Level 1
 *  0b000000..0.45 V
 *  0b010000..0.65 V
 *  0b100000..0.85 V
 *  0b110000..1.05 V
 *  0b111000..1.15 V (maximum)
 *  0b111111..1.15 V (clipped)
 */
#define PMC_LDOVDD1VSEL_VSEL1(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOVDD1VSEL_VSEL1_SHIFT)) & PMC_LDOVDD1VSEL_VSEL1_MASK)

#define PMC_LDOVDD1VSEL_VSEL2_MASK               (0x3F0000U)
#define PMC_LDOVDD1VSEL_VSEL2_SHIFT              (16U)
/*! VSEL2 - LDO VDD1 Voltage Level 2
 *  0b000000..0.45 V
 *  0b010000..0.65 V
 *  0b100000..0.85 V
 *  0b110000..1.05 V
 *  0b111000..1.15 V (maximum)
 *  0b111111..1.15 V (clipped)
 */
#define PMC_LDOVDD1VSEL_VSEL2(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOVDD1VSEL_VSEL2_SHIFT)) & PMC_LDOVDD1VSEL_VSEL2_MASK)

#define PMC_LDOVDD1VSEL_VSEL3_MASK               (0x3F000000U)
#define PMC_LDOVDD1VSEL_VSEL3_SHIFT              (24U)
/*! VSEL3 - LDO VDD1 Voltage Level 3
 *  0b000000..0.45 V
 *  0b010000..0.65 V
 *  0b100000..0.85 V
 *  0b110000..1.05 V
 *  0b111000..1.15 V (maximum)
 *  0b111111..1.15 V (clipped)
 */
#define PMC_LDOVDD1VSEL_VSEL3(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOVDD1VSEL_VSEL3_SHIFT)) & PMC_LDOVDD1VSEL_VSEL3_MASK)
/*! @} */

/*! @name LVDVDDNCTRL - VDDN LVD Control */
/*! @{ */

#define PMC_LVDVDDNCTRL_LVL0_MASK                (0x3FU)
#define PMC_LVDVDDNCTRL_LVL0_SHIFT               (0U)
/*! LVL0 - LVD Level 0 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDDNCTRL_LVL0(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDDNCTRL_LVL0_SHIFT)) & PMC_LVDVDDNCTRL_LVL0_MASK)

#define PMC_LVDVDDNCTRL_LVL1_MASK                (0x3F00U)
#define PMC_LVDVDDNCTRL_LVL1_SHIFT               (8U)
/*! LVL1 - LVD Level 1 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDDNCTRL_LVL1(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDDNCTRL_LVL1_SHIFT)) & PMC_LVDVDDNCTRL_LVL1_MASK)
/*! @} */

/*! @name LVDVDD2CTRL - VDD2 LVD Control */
/*! @{ */

#define PMC_LVDVDD2CTRL_LVL0_MASK                (0x3FU)
#define PMC_LVDVDD2CTRL_LVL0_SHIFT               (0U)
/*! LVL0 - LVD Level 0 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDD2CTRL_LVL0(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDD2CTRL_LVL0_SHIFT)) & PMC_LVDVDD2CTRL_LVL0_MASK)

#define PMC_LVDVDD2CTRL_LVL1_MASK                (0x3F00U)
#define PMC_LVDVDD2CTRL_LVL1_SHIFT               (8U)
/*! LVL1 - LVD Level 1 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDD2CTRL_LVL1(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDD2CTRL_LVL1_SHIFT)) & PMC_LVDVDD2CTRL_LVL1_MASK)

#define PMC_LVDVDD2CTRL_LVL2_MASK                (0x3F0000U)
#define PMC_LVDVDD2CTRL_LVL2_SHIFT               (16U)
/*! LVL2 - LVD Level 2 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDD2CTRL_LVL2(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDD2CTRL_LVL2_SHIFT)) & PMC_LVDVDD2CTRL_LVL2_MASK)

#define PMC_LVDVDD2CTRL_LVL3_MASK                (0x3F000000U)
#define PMC_LVDVDD2CTRL_LVL3_SHIFT               (24U)
/*! LVL3 - LVD Level 3 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDD2CTRL_LVL3(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDD2CTRL_LVL3_SHIFT)) & PMC_LVDVDD2CTRL_LVL3_MASK)
/*! @} */

/*! @name LVDVDD1CTRL - VDD1 LVD Control */
/*! @{ */

#define PMC_LVDVDD1CTRL_LVL0_MASK                (0x3FU)
#define PMC_LVDVDD1CTRL_LVL0_SHIFT               (0U)
/*! LVL0 - Level 0 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDD1CTRL_LVL0(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDD1CTRL_LVL0_SHIFT)) & PMC_LVDVDD1CTRL_LVL0_MASK)

#define PMC_LVDVDD1CTRL_LVL1_MASK                (0x3F00U)
#define PMC_LVDVDD1CTRL_LVL1_SHIFT               (8U)
/*! LVL1 - Level 1 Voltage */
#define PMC_LVDVDD1CTRL_LVL1(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDD1CTRL_LVL1_SHIFT)) & PMC_LVDVDD1CTRL_LVL1_MASK)

#define PMC_LVDVDD1CTRL_LVL2_MASK                (0x3F0000U)
#define PMC_LVDVDD1CTRL_LVL2_SHIFT               (16U)
/*! LVL2 - Level 2 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDD1CTRL_LVL2(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDD1CTRL_LVL2_SHIFT)) & PMC_LVDVDD1CTRL_LVL2_MASK)

#define PMC_LVDVDD1CTRL_LVL3_MASK                (0x3F000000U)
#define PMC_LVDVDD1CTRL_LVL3_SHIFT               (24U)
/*! LVL3 - Level 3 Voltage
 *  0b000000..0.50 V
 *  0b010000..0.66 V
 *  0b100000..0.82 V
 *  0b110000..0.98 V
 *  0b111111..1.13 V
 */
#define PMC_LVDVDD1CTRL_LVL3(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LVDVDD1CTRL_LVL3_SHIFT)) & PMC_LVDVDD1CTRL_LVL3_MASK)
/*! @} */

/*! @name PORCTRL - Power-on Reset Control */
/*! @{ */

#define PMC_PORCTRL_VDD1LVL_MASK                 (0x1FU)
#define PMC_PORCTRL_VDD1LVL_SHIFT                (0U)
/*! VDD1LVL - POR Level in VDD1 Domain
 *  0b00000..0.40 V
 *  0b01000..0.48 V
 *  0b10000..0.56 V
 *  0b11000..0.64 V
 *  0b11111..0.72 V
 */
#define PMC_PORCTRL_VDD1LVL(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PORCTRL_VDD1LVL_SHIFT)) & PMC_PORCTRL_VDD1LVL_MASK)

#define PMC_PORCTRL_VDD2LVL_MASK                 (0x1F00U)
#define PMC_PORCTRL_VDD2LVL_SHIFT                (8U)
/*! VDD2LVL - POR Level in VDD2 Domain
 *  0b00000..0.40 V
 *  0b01000..0.48 V
 *  0b10000..0.56 V
 *  0b11000..0.64 V
 *  0b11111..0.72 V
 */
#define PMC_PORCTRL_VDD2LVL(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PORCTRL_VDD2LVL_SHIFT)) & PMC_PORCTRL_VDD2LVL_MASK)

#define PMC_PORCTRL_VDDNLVL_MASK                 (0x1F0000U)
#define PMC_PORCTRL_VDDNLVL_SHIFT                (16U)
/*! VDDNLVL - POR Level in VDDN Domain
 *  0b00000..0.40 V
 *  0b01000..0.48 V
 *  0b10000..0.56 V
 *  0b11000..0.64 V
 *  0b11111..0.72 V
 */
#define PMC_PORCTRL_VDDNLVL(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PORCTRL_VDDNLVL_SHIFT)) & PMC_PORCTRL_VDDNLVL_MASK)
/*! @} */

/*! @name BBCTRL - Body Bias Control */
/*! @{ */

#define PMC_BBCTRL_RBB1LVL_MASK                  (0x1U)
#define PMC_BBCTRL_RBB1LVL_SHIFT                 (0U)
/*! RBB1LVL - Reverse Body Bias Voltage for VDD1 Domain
 *  0b1..Voltage is set to 1.3 V
 *  0b0..Voltage is set to 1.0 V
 */
#define PMC_BBCTRL_RBB1LVL(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_BBCTRL_RBB1LVL_SHIFT)) & PMC_BBCTRL_RBB1LVL_MASK)

#define PMC_BBCTRL_RBB2LVL_MASK                  (0x100U)
#define PMC_BBCTRL_RBB2LVL_SHIFT                 (8U)
/*! RBB2LVL - Reverse Body Bias Voltage for VDD2 Domain
 *  0b1..Voltage is set to 1.3 V
 *  0b0..Voltage is set to 1.0 V
 */
#define PMC_BBCTRL_RBB2LVL(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_BBCTRL_RBB2LVL_SHIFT)) & PMC_BBCTRL_RBB2LVL_MASK)

#define PMC_BBCTRL_RBBNLVL_MASK                  (0x10000U)
#define PMC_BBCTRL_RBBNLVL_SHIFT                 (16U)
/*! RBBNLVL - Reverse Body Bias Voltage for VDDN Domain
 *  0b0..Voltage is set to 1.0 V
 *  0b1..Voltage is set to 1.3 V
 */
#define PMC_BBCTRL_RBBNLVL(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_BBCTRL_RBBNLVL_SHIFT)) & PMC_BBCTRL_RBBNLVL_MASK)
/*! @} */

/*! @name TSENSOR - Temperature Sensor Control */
/*! @{ */

#define PMC_TSENSOR_TSENSM_MASK                  (0xFU)
#define PMC_TSENSOR_TSENSM_SHIFT                 (0U)
/*! TSENSM - Temperature Sensor Mode Select
 *  0b0000..Perform AD conversion and record C*_000
 *  0b0001..Perform AD conversion and record C*_001
 *  0b0010..Perform AD conversion and record C*_010
 *  0b0011..Perform AD conversion and record C*_011
 *  0b0100..Perform AD conversion and record CM_100
 *  0b0101..Perform AD conversion and record C*_101
 *  0b0110..Perform AD conversion and record C*_110
 *  0b0111..Perform AD conversion and record C*_111
 */
#define PMC_TSENSOR_TSENSM(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_TSENSOR_TSENSM_SHIFT)) & PMC_TSENSOR_TSENSM_MASK)
/*! @} */

/*! @name WAKEUP - Wake-up Configuration for Compute Domain */
/*! @{ */

#define PMC_WAKEUP_WAKETIME_MASK                 (0xFFFFU)
#define PMC_WAKEUP_WAKETIME_SHIFT                (0U)
/*! WAKETIME - Wake-up Timer */
#define PMC_WAKEUP_WAKETIME(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUP_WAKETIME_SHIFT)) & PMC_WAKEUP_WAKETIME_MASK)

#define PMC_WAKEUP_WKSRCEN_MASK                  (0x3F0000U)
#define PMC_WAKEUP_WKSRCEN_SHIFT                 (16U)
/*! WKSRCEN - Wake-up Source Enable
 *  0b000001..Wake-up enabled
 *  0b000000..Wake-up disabled
 */
#define PMC_WAKEUP_WKSRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUP_WKSRCEN_SHIFT)) & PMC_WAKEUP_WKSRCEN_MASK)

#define PMC_WAKEUP_WKSRCF_MASK                   (0x3F000000U)
#define PMC_WAKEUP_WKSRCF_SHIFT                  (24U)
/*! WKSRCF - Wake-up Source Flags
 *  0b000001..Source has triggered a wake-up
 *  0b000000..No wake-up from source
 */
#define PMC_WAKEUP_WKSRCF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUP_WKSRCF_SHIFT)) & PMC_WAKEUP_WKSRCF_MASK)
/*! @} */

/*! @name POWERCFG - Power Configuration */
/*! @{ */

#define PMC_POWERCFG_FDSCP1PD_MASK               (0x1U)
#define PMC_POWERCFG_FDSCP1PD_SHIFT              (0U)
/*! FDSCP1PD - SCPC VDD1 Power Down in FDSR Mode
 *  0b0..Not powered down
 *  0b1..Powered down
 */
#define PMC_POWERCFG_FDSCP1PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_FDSCP1PD_SHIFT)) & PMC_POWERCFG_FDSCP1PD_MASK)

#define PMC_POWERCFG_FDSCP2PD_MASK               (0x2U)
#define PMC_POWERCFG_FDSCP2PD_SHIFT              (1U)
/*! FDSCP2PD - SCPC VDD2 Power Down in FDSR Mode
 *  0b0..Not powered down
 *  0b1..Powered down
 */
#define PMC_POWERCFG_FDSCP2PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_FDSCP2PD_SHIFT)) & PMC_POWERCFG_FDSCP2PD_MASK)

#define PMC_POWERCFG_FDLDO1PD_MASK               (0x10U)
#define PMC_POWERCFG_FDLDO1PD_SHIFT              (4U)
/*! FDLDO1PD - LDO VDD1 Power Down in FDSR Mode
 *  0b0..Not powered down
 *  0b1..Powered down
 */
#define PMC_POWERCFG_FDLDO1PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_FDLDO1PD_SHIFT)) & PMC_POWERCFG_FDLDO1PD_MASK)

#define PMC_POWERCFG_FDLDO2PD_MASK               (0x20U)
#define PMC_POWERCFG_FDLDO2PD_SHIFT              (5U)
/*! FDLDO2PD - LDO VDD2 Power Down in FDSR Mode
 *  0b0..Not powered down
 *  0b1..Powered down
 */
#define PMC_POWERCFG_FDLDO2PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_FDLDO2PD_SHIFT)) & PMC_POWERCFG_FDLDO2PD_MASK)

#define PMC_POWERCFG_FDDCPD_MASK                 (0x40U)
#define PMC_POWERCFG_FDDCPD_SHIFT                (6U)
/*! FDDCPD - DCDC Power Down in FDSR Mode
 *  0b0..Not powered down
 *  0b1..Powered down
 */
#define PMC_POWERCFG_FDDCPD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_FDDCPD_SHIFT)) & PMC_POWERCFG_FDDCPD_MASK)

#define PMC_POWERCFG_SCPCPD_MASK                 (0x80U)
#define PMC_POWERCFG_SCPCPD_SHIFT                (7U)
/*! SCPCPD - SCPC Power Down
 *  0b0..Not powered down in FDSR mode, except in FDSR mode when [FDSCPnPD] = 1
 *  0b1..Powered down (until the next cold reset)
 */
#define PMC_POWERCFG_SCPCPD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_SCPCPD_SHIFT)) & PMC_POWERCFG_SCPCPD_MASK)

#define PMC_POWERCFG_LDO1PD_MASK                 (0x100U)
#define PMC_POWERCFG_LDO1PD_SHIFT                (8U)
/*! LDO1PD - LDO VDD1 Power Down
 *  0b0..Not powered down, except in FDSR mode when [FDLDO1PD] = 1, or in DPD or FDPD mode
 *  0b1..Powered down (until the next cold reset)
 */
#define PMC_POWERCFG_LDO1PD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_LDO1PD_SHIFT)) & PMC_POWERCFG_LDO1PD_MASK)

#define PMC_POWERCFG_LDO2PD_MASK                 (0x200U)
#define PMC_POWERCFG_LDO2PD_SHIFT                (9U)
/*! LDO2PD - LDO VDD2 Power Down
 *  0b0..Not powered down, except in FDSR mode when [FDLDO2PD] = 1, or in DPD or FDPD mode
 *  0b1..Powered down (until the next cold reset)
 */
#define PMC_POWERCFG_LDO2PD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_LDO2PD_SHIFT)) & PMC_POWERCFG_LDO2PD_MASK)

#define PMC_POWERCFG_DCDCPD_MASK                 (0x1000U)
#define PMC_POWERCFG_DCDCPD_SHIFT                (12U)
/*! DCDCPD - DCDC Power Down
 *  0b0..Not powered down, except in FDSR mode when [FDDCPD] = 1, or in DPD or FDPD mode
 *  0b1..Powered down (until the next cold reset)
 */
#define PMC_POWERCFG_DCDCPD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_DCDCPD_SHIFT)) & PMC_POWERCFG_DCDCPD_MASK)

#define PMC_POWERCFG_FDPDBGLP_MASK               (0x1000000U)
#define PMC_POWERCFG_FDPDBGLP_SHIFT              (24U)
/*! FDPDBGLP - Force Band Gap during FDPD Mode to LP Mode
 *  0b0..Enables band gap to high-power mode during FDPD mode and wakes up if VDD1V8 POR is asserted then negated
 *  0b1..Enables band gap to low-power mode during FDPD mode and will not wake up on VDD1V8 POR negation. RTC, PMIC_IRQN, or reset is used as wake-up
 */
#define PMC_POWERCFG_FDPDBGLP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_FDPDBGLP_SHIFT)) & PMC_POWERCFG_FDPDBGLP_MASK)

#define PMC_POWERCFG_MODEDLY_MASK                (0xF0000000U)
#define PMC_POWERCFG_MODEDLY_SHIFT               (28U)
/*! MODEDLY - Mode Delay
 *  0b0000..250 ns
 *  0b0001..500 ns
 *  0b0010..1000 ns
 *  0b0011..2000 ns
 *  0b0100..4000 ns
 *  0b0101..8000 ns
 *  0b0110..16 us
 *  0b0111..32 us
 *  0b1000..64 us
 *  0b1001..128 us
 *  0b1010..256 us
 *  0b1011..512 us
 *  0b1100..1024 us
 *  0b1101..2048 us
 *  0b1110..4096 us
 *  0b1111..8192 us
 */
#define PMC_POWERCFG_MODEDLY(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_POWERCFG_MODEDLY_SHIFT)) & PMC_POWERCFG_MODEDLY_MASK)
/*! @} */

/*! @name PADVRANGE - 3 V Capable VDDIO Range Select */
/*! @{ */

#define PMC_PADVRANGE_VRANGE_MASK                (0x3U)
#define PMC_PADVRANGE_VRANGE_SHIFT               (0U)
/*! VRANGE - 3 V Capable IO Bank VDDIO Range Select
 *  0b11..Reserved
 *  0b10..3.00 - 3.6 V, supply detector off
 *  0b01..1.71 - 1.98 V, supply detector off
 *  0b00..Continuous mode. Allows 1.71 - 3.6 V range but consumes static current.
 */
#define PMC_PADVRANGE_VRANGE(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PADVRANGE_VRANGE_SHIFT)) & PMC_PADVRANGE_VRANGE_MASK)
/*! @} */

/*! @name PADCFG - IO Bank State Configuration */
/*! @{ */

#define PMC_PADCFG_ISOCTRL_MASK                  (0xFFU)
#define PMC_PADCFG_ISOCTRL_SHIFT                 (0U)
/*! ISOCTRL - IO bank State Retain Control
 *  0bxxxxxxx1..Port 0/1/3 is in retain mode
 *  0bxxxxxx1x..Port 2 is in retain mode
 *  0bxxxxx1xx..Port 4 is in retain mode
 *  0bxxxx1xxx..Port 5 is in retain mode
 *  0bxxx1xxxx..Port 6 is in retain mode
 *  0bxx1xxxxx..Port 7 is in retain mode
 *  0bx1xxxxxx..Port 8/9/10 is in retain mode
 *  0b1xxxxxxx..PMIC_I2C is in retain mode
 *  0b00000000..IO bank is controllable
 */
#define PMC_PADCFG_ISOCTRL(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_PADCFG_ISOCTRL_SHIFT)) & PMC_PADCFG_ISOCTRL_MASK)

#define PMC_PADCFG_ISOHOLD_MASK                  (0xFF00U)
#define PMC_PADCFG_ISOHOLD_SHIFT                 (8U)
/*! ISOHOLD - IO Bank Isolation Hold
 *  0bxxxxxxx1..Port 0/1/3 is retained/isolated on wake-up from FDSR/DPD mode. Software must clear [ISOCTRL] bit 0 to regain control
 *  0bxxxxxx1x..Port 2 is retained/isolated on wake-up from FDSR/DPD mode. Software must clear [ISOCTRL] bit 1 to regain control
 *  0bxxxxx1xx..Port 4 is retained/isolated on wake-up from FDSR/DPD mode. Software must clear [ISOCTRL] bit 2 to regain control
 *  0bxxxx1xxx..Port 5 is retained/isolated on wake-up from FDSR/DPD mode. Software must clear [ISOCTRL] bit 3 to regain control
 *  0bxxx1xxxx..Port 6 is retained/isolated on wake-up from FDSR/DPD mode. Software must clear [ISOCTRL] bit 4 to regain control
 *  0bxx1xxxxx..Port 7 is retained/isolated on wake-up from FDSR/DPD mode. Software must clear [ISOCTRL] bit 5 to regain control
 *  0bx1xxxxxx..Port 8/9/10 is retained/isolated on wake-up from FDSR/DPD mode. Software must clear [ISOCTRL] bit 6 to regain control
 *  0b1xxxxxxx..PMIC_I2C is retained/isolated on wake-up from FDSR/DPD mode. Software must clear [ISOCTRL] bit 7 to regain control
 *  0b00000000..IO bank is controllable on wake-up from FDSR/DPD mode
 */
#define PMC_PADCFG_ISOHOLD(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_PADCFG_ISOHOLD_SHIFT)) & PMC_PADCFG_ISOHOLD_MASK)

#define PMC_PADCFG_RSTCTRL_MASK                  (0xFF0000U)
#define PMC_PADCFG_RSTCTRL_SHIFT                 (16U)
/*! RSTCTRL - Reset Control
 *  0bxxxxxxx1..Port 0/1/3 reset = tristate
 *  0bxxxxxx1x..Port 2 reset = tristate
 *  0bxxxxx1xx..Port 4 reset = tristate
 *  0bxxxx1xxx..Port 5 reset = tristate
 *  0bxxx1xxxx..Port 6 reset = tristate
 *  0bxx1xxxxx..Port 7 reset = tristate
 *  0bx1xxxxxx..Port 8/9/10 reset = tristate
 *  0b1xxxxxxx..PMIC_I2C reset = tristate
 *  0b00000000..IO banks are not reset
 */
#define PMC_PADCFG_RSTCTRL(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_PADCFG_RSTCTRL_SHIFT)) & PMC_PADCFG_RSTCTRL_MASK)
/*! @} */

/*! @name PDRUNCFG0 - PD Run Configuration 0 in Compute Domain */
/*! @{ */

#define PMC_PDRUNCFG0_PMICMODE_MASK              (0x3U)
#define PMC_PDRUNCFG0_PMICMODE_SHIFT             (0U)
/*! PMICMODE - PMIC Power Mode Select
 *  0b11..Drives PMIC_MODE pins to 3h
 *  0b10..Drives PMIC_MODE pins to 2h
 *  0b01..Drives PMIC_MODE pins to 1h
 *  0b00..Drives PMIC_MODE pins to 0h
 */
#define PMC_PDRUNCFG0_PMICMODE(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PMICMODE_SHIFT)) & PMC_PDRUNCFG0_PMICMODE_MASK)

#define PMC_PDRUNCFG0_V2NMED_DSR_MASK            (0x40U)
#define PMC_PDRUNCFG0_V2NMED_DSR_SHIFT           (6U)
/*! V2NMED_DSR - Power Switch and DSR for VDD2 and VDDN Media
 *  0b1..Enables VDD2 and VDDN media domains in DSR mode
 *  0b0..Powers on VDD2 and VDDN media domains
 */
#define PMC_PDRUNCFG0_V2NMED_DSR(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_V2NMED_DSR_SHIFT)) & PMC_PDRUNCFG0_V2NMED_DSR_MASK)

#define PMC_PDRUNCFG0_VNCOM_DSR_MASK             (0x100U)
#define PMC_PDRUNCFG0_VNCOM_DSR_SHIFT            (8U)
/*! VNCOM_DSR - Power Switch and DSR for VDDN_COM
 *  0b1..Enables VDDN_COM domain in DSR mode
 *  0b0..Powers on VDDN_COM domain
 */
#define PMC_PDRUNCFG0_VNCOM_DSR(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_VNCOM_DSR_SHIFT)) & PMC_PDRUNCFG0_VNCOM_DSR_MASK)

#define PMC_PDRUNCFG0_V2DSP_PD_MASK              (0x200U)
#define PMC_PDRUNCFG0_V2DSP_PD_SHIFT             (9U)
/*! V2DSP_PD - Power Down VDD2_DSP
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG0_V2DSP_PD(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_V2DSP_PD_SHIFT)) & PMC_PDRUNCFG0_V2DSP_PD_MASK)

#define PMC_PDRUNCFG0_V2MIPI_PD_MASK             (0x400U)
#define PMC_PDRUNCFG0_V2MIPI_PD_SHIFT            (10U)
/*! V2MIPI_PD - Power Down MIPI PHY in VDD2 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG0_V2MIPI_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_V2MIPI_PD_SHIFT)) & PMC_PDRUNCFG0_V2MIPI_PD_MASK)

#define PMC_PDRUNCFG0_DCDC_LP_MASK               (0x1000U)
#define PMC_PDRUNCFG0_DCDC_LP_SHIFT              (12U)
/*! DCDC_LP - DCDC Low-Power Mode
 *  0b1..Enables DCDC in low-power mode
 *  0b0..Enables DCDC in high-power mode
 */
#define PMC_PDRUNCFG0_DCDC_LP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_DCDC_LP_SHIFT)) & PMC_PDRUNCFG0_DCDC_LP_MASK)

#define PMC_PDRUNCFG0_DCDC_VSEL_MASK             (0x2000U)
#define PMC_PDRUNCFG0_DCDC_VSEL_SHIFT            (13U)
/*! DCDC_VSEL - Select DCDC Voltage
 *  0b1..Selects DCDCVSEL[VSEL1] level
 *  0b0..Selects DCDCVSEL[VSEL0] level
 */
#define PMC_PDRUNCFG0_DCDC_VSEL(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_DCDC_VSEL_SHIFT)) & PMC_PDRUNCFG0_DCDC_VSEL_MASK)

#define PMC_PDRUNCFG0_LDO1_MODE_MASK             (0xC000U)
#define PMC_PDRUNCFG0_LDO1_MODE_SHIFT            (14U)
/*! LDO1_MODE - LDO VDD1 Mode
 *  0b10, 0b11..Low-power mode
 *  0b01..High-power mode
 *  0b00..Bypass mode
 */
#define PMC_PDRUNCFG0_LDO1_MODE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_LDO1_MODE_SHIFT)) & PMC_PDRUNCFG0_LDO1_MODE_MASK)

#define PMC_PDRUNCFG0_LDO1_VSEL_MASK             (0x30000U)
#define PMC_PDRUNCFG0_LDO1_VSEL_SHIFT            (16U)
/*! LDO1_VSEL - LDO VDD1 Voltage Select
 *  0b00..Selects LDOVDD1VSEL[VSEL0] and LVDVDD1CTRL[LVL0] level
 *  0b01..Selects LDOVDD1VSEL[VSEL1] and LVDVDD1CTRL[LVL1] level
 *  0b10..Selects LDOVDD1VSEL[VSEL2] and LVDVDD1CTRL[LVL2] level
 *  0b11..Selects LDOVDD1VSEL[VSEL3] and LVDVDD1CTRL[LVL3] level
 */
#define PMC_PDRUNCFG0_LDO1_VSEL(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_LDO1_VSEL_SHIFT)) & PMC_PDRUNCFG0_LDO1_VSEL_MASK)

#define PMC_PDRUNCFG0_LDO2_MODE_MASK             (0xC0000U)
#define PMC_PDRUNCFG0_LDO2_MODE_SHIFT            (18U)
/*! LDO2_MODE - LDO VDD2 Mode
 *  0b10, 0b11..Low-power mode
 *  0b01..High-power mode
 *  0b00..Bypass mode
 */
#define PMC_PDRUNCFG0_LDO2_MODE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_LDO2_MODE_SHIFT)) & PMC_PDRUNCFG0_LDO2_MODE_MASK)

#define PMC_PDRUNCFG0_LDO2_VSEL_MASK             (0x300000U)
#define PMC_PDRUNCFG0_LDO2_VSEL_SHIFT            (20U)
/*! LDO2_VSEL - Select LDO VDD2 Voltage
 *  0b00..Selects LDOVDD2VSEL[VSEL0] and LVDVDD2CTRL[LVL0] level
 *  0b01..Selects LDOVDD2VSEL[VSEL1] and LVDVDD2CTRL[LVL1] level
 *  0b10..Selects LDOVDD2VSEL[VSEL2] and LVDVDD2CTRL[LVL2] level
 *  0b11..Selects LDOVDD2VSEL[VSEL3] and LVDVDD2CTRL[LVL3] level
 */
#define PMC_PDRUNCFG0_LDO2_VSEL(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_LDO2_VSEL_SHIFT)) & PMC_PDRUNCFG0_LDO2_VSEL_MASK)

#define PMC_PDRUNCFG0_RBB1_PD_MASK               (0x400000U)
#define PMC_PDRUNCFG0_RBB1_PD_SHIFT              (22U)
/*! RBB1_PD - Power Down RBB in VDD1
 *  0b0..If PDRUNCFG0[AFBB1_PD] = 1, power on. Else power down
 *  0b1..Power down
 */
#define PMC_PDRUNCFG0_RBB1_PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_RBB1_PD_SHIFT)) & PMC_PDRUNCFG0_RBB1_PD_MASK)

#define PMC_PDRUNCFG0_AFBB1_PD_MASK              (0x800000U)
#define PMC_PDRUNCFG0_AFBB1_PD_SHIFT             (23U)
/*! AFBB1_PD - Power Down AFBB in VDD1 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG0_AFBB1_PD(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_AFBB1_PD_SHIFT)) & PMC_PDRUNCFG0_AFBB1_PD_MASK)

#define PMC_PDRUNCFG0_RBB2_PD_MASK               (0x1000000U)
#define PMC_PDRUNCFG0_RBB2_PD_SHIFT              (24U)
/*! RBB2_PD - Power Down RBB in VDD2 Domain
 *  0b1..Power down
 *  0b0..If PDRUNCFG0[AFBB2_PD] = 1, power on. Else power down
 */
#define PMC_PDRUNCFG0_RBB2_PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_RBB2_PD_SHIFT)) & PMC_PDRUNCFG0_RBB2_PD_MASK)

#define PMC_PDRUNCFG0_AFBB2_PD_MASK              (0x2000000U)
#define PMC_PDRUNCFG0_AFBB2_PD_SHIFT             (25U)
/*! AFBB2_PD - Power Down AFBB in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG0_AFBB2_PD(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_AFBB2_PD_SHIFT)) & PMC_PDRUNCFG0_AFBB2_PD_MASK)

#define PMC_PDRUNCFG0_RBBN_PD_MASK               (0x4000000U)
#define PMC_PDRUNCFG0_RBBN_PD_SHIFT              (26U)
/*! RBBN_PD - Power Down RBB in VDDN Domain
 *  0b0..If PDRUNCFG0[AFBBN_PD] = 1, power on. Else power down
 *  0b1..Power down
 */
#define PMC_PDRUNCFG0_RBBN_PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_RBBN_PD_SHIFT)) & PMC_PDRUNCFG0_RBBN_PD_MASK)

#define PMC_PDRUNCFG0_AFBBN_PD_MASK              (0x8000000U)
#define PMC_PDRUNCFG0_AFBBN_PD_SHIFT             (27U)
/*! AFBBN_PD - Power Down AFBB in VDDN Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG0_AFBBN_PD(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_AFBBN_PD_SHIFT)) & PMC_PDRUNCFG0_AFBBN_PD_MASK)

#define PMC_PDRUNCFG0_RBBSR1_PD_MASK             (0x10000000U)
#define PMC_PDRUNCFG0_RBBSR1_PD_SHIFT            (28U)
/*! RBBSR1_PD - Power Down SRAM RBB in VDD1 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG0_RBBSR1_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_RBBSR1_PD_SHIFT)) & PMC_PDRUNCFG0_RBBSR1_PD_MASK)

#define PMC_PDRUNCFG0_RBBSR2_PD_MASK             (0x20000000U)
#define PMC_PDRUNCFG0_RBBSR2_PD_SHIFT            (29U)
/*! RBBSR2_PD - Power Down SRAM RBB in VDD2 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG0_RBBSR2_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_RBBSR2_PD_SHIFT)) & PMC_PDRUNCFG0_RBBSR2_PD_MASK)

#define PMC_PDRUNCFG0_AFBBSR2_PD_MASK            (0x80000000U)
#define PMC_PDRUNCFG0_AFBBSR2_PD_SHIFT           (31U)
/*! AFBBSR2_PD - Power Down SRAM AFBB in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG0_AFBBSR2_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_AFBBSR2_PD_SHIFT)) & PMC_PDRUNCFG0_AFBBSR2_PD_MASK)
/*! @} */

/*! @name PDRUNCFG1 - PD Run Configuration 1 in Compute Domain */
/*! @{ */

#define PMC_PDRUNCFG1_TEMP_PD_MASK               (0x1U)
#define PMC_PDRUNCFG1_TEMP_PD_SHIFT              (0U)
/*! TEMP_PD - Power Down PMC Temperature Sensor
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG1_TEMP_PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_TEMP_PD_SHIFT)) & PMC_PDRUNCFG1_TEMP_PD_MASK)

#define PMC_PDRUNCFG1_PMCREF_LP_MASK             (0x2U)
#define PMC_PDRUNCFG1_PMCREF_LP_SHIFT            (1U)
/*! PMCREF_LP - PMC References in Low-Power Mode
 *  0b1..Sets PMC references in low-power mode if not overridden by any *_PD bits
 *  0b0..Sets PMC references in high-power mode
 */
#define PMC_PDRUNCFG1_PMCREF_LP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PMCREF_LP_SHIFT)) & PMC_PDRUNCFG1_PMCREF_LP_MASK)

#define PMC_PDRUNCFG1_HVD1V8_PD_MASK             (0x4U)
#define PMC_PDRUNCFG1_HVD1V8_PD_SHIFT            (2U)
/*! HVD1V8_PD - HVD Power Down
 *  0b1..Power down
 *  0b0..Power on. In this case, PMC references will be in high-power mode
 */
#define PMC_PDRUNCFG1_HVD1V8_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_HVD1V8_PD_SHIFT)) & PMC_PDRUNCFG1_HVD1V8_PD_MASK)

#define PMC_PDRUNCFG1_POR1_LP_MASK               (0x8U)
#define PMC_PDRUNCFG1_POR1_LP_SHIFT              (3U)
/*! POR1_LP - POR Low-Power Mode in VDD1 Domain
 *  0b1..Sets POR in low-power mode
 *  0b0..Sets POR in high-power mode. In this case, PMC references will be in high-power mode
 */
#define PMC_PDRUNCFG1_POR1_LP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_POR1_LP_SHIFT)) & PMC_PDRUNCFG1_POR1_LP_MASK)

#define PMC_PDRUNCFG1_LVD1_LP_MASK               (0x10U)
#define PMC_PDRUNCFG1_LVD1_LP_SHIFT              (4U)
/*! LVD1_LP - LVD Low-Power Mode in VDD1 Domain
 *  0b0..Sets LVD in high-power mode. In this case, PMC references will be in high-power mode
 *  0b1..Sets LVD in low-power mode
 */
#define PMC_PDRUNCFG1_LVD1_LP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_LVD1_LP_SHIFT)) & PMC_PDRUNCFG1_LVD1_LP_MASK)

#define PMC_PDRUNCFG1_HVD1_PD_MASK               (0x20U)
#define PMC_PDRUNCFG1_HVD1_PD_SHIFT              (5U)
/*! HVD1_PD - Power Down HVD in VDD1 Domain
 *  0b1..Power down
 *  0b0..Power on. In this case, PMC references will be in high-power mode
 */
#define PMC_PDRUNCFG1_HVD1_PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_HVD1_PD_SHIFT)) & PMC_PDRUNCFG1_HVD1_PD_MASK)

#define PMC_PDRUNCFG1_AGDET1_PD_MASK             (0x40U)
#define PMC_PDRUNCFG1_AGDET1_PD_SHIFT            (6U)
/*! AGDET1_PD - Power Down AGDET in VDD1 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG1_AGDET1_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_AGDET1_PD_SHIFT)) & PMC_PDRUNCFG1_AGDET1_PD_MASK)

#define PMC_PDRUNCFG1_POR2_LP_MASK               (0x80U)
#define PMC_PDRUNCFG1_POR2_LP_SHIFT              (7U)
/*! POR2_LP - POR Low-Power Mode in VDD2 Domain
 *  0b1..Sets POR in low-power mode
 *  0b0..Sets POR in high-power mode. In this case, PMC references will be in high-power mode
 */
#define PMC_PDRUNCFG1_POR2_LP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_POR2_LP_SHIFT)) & PMC_PDRUNCFG1_POR2_LP_MASK)

#define PMC_PDRUNCFG1_LVD2_LP_MASK               (0x100U)
#define PMC_PDRUNCFG1_LVD2_LP_SHIFT              (8U)
/*! LVD2_LP - LVD Low-Power Mode in VDD2 Domain
 *  0b1..Sets LVD in low-power mode
 *  0b0..Sets LVD in high-power mode. In this case, PMC references will be in high-power mode
 */
#define PMC_PDRUNCFG1_LVD2_LP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_LVD2_LP_SHIFT)) & PMC_PDRUNCFG1_LVD2_LP_MASK)

#define PMC_PDRUNCFG1_HVD2_PD_MASK               (0x200U)
#define PMC_PDRUNCFG1_HVD2_PD_SHIFT              (9U)
/*! HVD2_PD - Power Down HVD in VDD2 Domain
 *  0b0..Power on. In this case, PMC references will be in high-power mode
 *  0b1..Power down
 */
#define PMC_PDRUNCFG1_HVD2_PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_HVD2_PD_SHIFT)) & PMC_PDRUNCFG1_HVD2_PD_MASK)

#define PMC_PDRUNCFG1_AGDET2_PD_MASK             (0x400U)
#define PMC_PDRUNCFG1_AGDET2_PD_SHIFT            (10U)
/*! AGDET2_PD - Power Down AGDET in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG1_AGDET2_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_AGDET2_PD_SHIFT)) & PMC_PDRUNCFG1_AGDET2_PD_MASK)

#define PMC_PDRUNCFG1_PORN_LP_MASK               (0x800U)
#define PMC_PDRUNCFG1_PORN_LP_SHIFT              (11U)
/*! PORN_LP - POR Low-Power Mode in VDDN Domain
 *  0b0..Sets POR in high-power mode. In this case, PMC references will be in high-power mode
 *  0b1..Sets POR in low-power mode
 */
#define PMC_PDRUNCFG1_PORN_LP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PORN_LP_SHIFT)) & PMC_PDRUNCFG1_PORN_LP_MASK)

#define PMC_PDRUNCFG1_LVDN_LP_MASK               (0x1000U)
#define PMC_PDRUNCFG1_LVDN_LP_SHIFT              (12U)
/*! LVDN_LP - LVD Low-Power Mode in VDDN Domain
 *  0b0..Sets LVD in high-power mode. In this case, PMC references will be in high-power mode
 *  0b1..Sets LVD in low-power mode
 */
#define PMC_PDRUNCFG1_LVDN_LP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_LVDN_LP_SHIFT)) & PMC_PDRUNCFG1_LVDN_LP_MASK)

#define PMC_PDRUNCFG1_HVDN_PD_MASK               (0x2000U)
#define PMC_PDRUNCFG1_HVDN_PD_SHIFT              (13U)
/*! HVDN_PD - Power Down HVD in VDDN Domain
 *  0b1..Power down
 *  0b0..Power on. In this case, PMC references will be in high-power mode
 */
#define PMC_PDRUNCFG1_HVDN_PD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_HVDN_PD_SHIFT)) & PMC_PDRUNCFG1_HVDN_PD_MASK)

#define PMC_PDRUNCFG1_OTP_PD_MASK                (0x8000U)
#define PMC_PDRUNCFG1_OTP_PD_SHIFT               (15U)
/*! OTP_PD - Power Down OTP
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG1_OTP_PD(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_OTP_PD_SHIFT)) & PMC_PDRUNCFG1_OTP_PD_MASK)

#define PMC_PDRUNCFG1_ROM_PD_MASK                (0x10000U)
#define PMC_PDRUNCFG1_ROM_PD_SHIFT               (16U)
/*! ROM_PD - Power Down ROM
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG1_ROM_PD(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_ROM_PD_SHIFT)) & PMC_PDRUNCFG1_ROM_PD_MASK)
/*! @} */

/*! @name PDRUNCFG2 - PD Run Configuration 2 in Compute Domain */
/*! @{ */

#define PMC_PDRUNCFG2_SRAM1_MASK                 (0x2U)
#define PMC_PDRUNCFG2_SRAM1_SHIFT                (1U)
/*! SRAM1 - Power Down RAM Partition 1 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM1(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM1_SHIFT)) & PMC_PDRUNCFG2_SRAM1_MASK)

#define PMC_PDRUNCFG2_SRAM2_MASK                 (0x4U)
#define PMC_PDRUNCFG2_SRAM2_SHIFT                (2U)
/*! SRAM2 - Power Down RAM Partition 2 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM2(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM2_SHIFT)) & PMC_PDRUNCFG2_SRAM2_MASK)

#define PMC_PDRUNCFG2_SRAM3_MASK                 (0x8U)
#define PMC_PDRUNCFG2_SRAM3_SHIFT                (3U)
/*! SRAM3 - Power Down RAM Partition 3 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM3(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM3_SHIFT)) & PMC_PDRUNCFG2_SRAM3_MASK)

#define PMC_PDRUNCFG2_SRAM4_MASK                 (0x10U)
#define PMC_PDRUNCFG2_SRAM4_SHIFT                (4U)
/*! SRAM4 - Power Down RAM Partition 4 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM4(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM4_SHIFT)) & PMC_PDRUNCFG2_SRAM4_MASK)

#define PMC_PDRUNCFG2_SRAM5_MASK                 (0x20U)
#define PMC_PDRUNCFG2_SRAM5_SHIFT                (5U)
/*! SRAM5 - Power Down RAM Partition 5 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM5(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM5_SHIFT)) & PMC_PDRUNCFG2_SRAM5_MASK)

#define PMC_PDRUNCFG2_SRAM6_MASK                 (0x40U)
#define PMC_PDRUNCFG2_SRAM6_SHIFT                (6U)
/*! SRAM6 - Power Down RAM Partition 6 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM6(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM6_SHIFT)) & PMC_PDRUNCFG2_SRAM6_MASK)

#define PMC_PDRUNCFG2_SRAM7_MASK                 (0x80U)
#define PMC_PDRUNCFG2_SRAM7_SHIFT                (7U)
/*! SRAM7 - Power Down RAM Partition 7 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM7(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM7_SHIFT)) & PMC_PDRUNCFG2_SRAM7_MASK)

#define PMC_PDRUNCFG2_SRAM8_MASK                 (0x100U)
#define PMC_PDRUNCFG2_SRAM8_SHIFT                (8U)
/*! SRAM8 - Power Down RAM Partition 8 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM8(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM8_SHIFT)) & PMC_PDRUNCFG2_SRAM8_MASK)

#define PMC_PDRUNCFG2_SRAM9_MASK                 (0x200U)
#define PMC_PDRUNCFG2_SRAM9_SHIFT                (9U)
/*! SRAM9 - Power Down RAM Partition 9 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM9(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM9_SHIFT)) & PMC_PDRUNCFG2_SRAM9_MASK)

#define PMC_PDRUNCFG2_SRAM10_MASK                (0x400U)
#define PMC_PDRUNCFG2_SRAM10_SHIFT               (10U)
/*! SRAM10 - Power Down RAM Partition 10 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM10(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM10_SHIFT)) & PMC_PDRUNCFG2_SRAM10_MASK)

#define PMC_PDRUNCFG2_SRAM11_MASK                (0x800U)
#define PMC_PDRUNCFG2_SRAM11_SHIFT               (11U)
/*! SRAM11 - Power Down RAM Partition 11 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM11(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM11_SHIFT)) & PMC_PDRUNCFG2_SRAM11_MASK)

#define PMC_PDRUNCFG2_SRAM12_MASK                (0x1000U)
#define PMC_PDRUNCFG2_SRAM12_SHIFT               (12U)
/*! SRAM12 - Power Down RAM Partition 12 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM12(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM12_SHIFT)) & PMC_PDRUNCFG2_SRAM12_MASK)

#define PMC_PDRUNCFG2_SRAM13_MASK                (0x2000U)
#define PMC_PDRUNCFG2_SRAM13_SHIFT               (13U)
/*! SRAM13 - Power Down RAM Partition 13 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM13(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM13_SHIFT)) & PMC_PDRUNCFG2_SRAM13_MASK)

#define PMC_PDRUNCFG2_SRAM14_MASK                (0x4000U)
#define PMC_PDRUNCFG2_SRAM14_SHIFT               (14U)
/*! SRAM14 - Power Down RAM Partition 14 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM14(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM14_SHIFT)) & PMC_PDRUNCFG2_SRAM14_MASK)

#define PMC_PDRUNCFG2_SRAM15_MASK                (0x8000U)
#define PMC_PDRUNCFG2_SRAM15_SHIFT               (15U)
/*! SRAM15 - Power Down RAM Partition 15 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM15(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM15_SHIFT)) & PMC_PDRUNCFG2_SRAM15_MASK)

#define PMC_PDRUNCFG2_SRAM16_MASK                (0x10000U)
#define PMC_PDRUNCFG2_SRAM16_SHIFT               (16U)
/*! SRAM16 - Power Down RAM Partition 16 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM16(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM16_SHIFT)) & PMC_PDRUNCFG2_SRAM16_MASK)

#define PMC_PDRUNCFG2_SRAM17_MASK                (0x20000U)
#define PMC_PDRUNCFG2_SRAM17_SHIFT               (17U)
/*! SRAM17 - Power Down RAM Partition 17 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM17(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM17_SHIFT)) & PMC_PDRUNCFG2_SRAM17_MASK)

#define PMC_PDRUNCFG2_SRAM18_MASK                (0x40000U)
#define PMC_PDRUNCFG2_SRAM18_SHIFT               (18U)
/*! SRAM18 - Power Down RAM Partition 18 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM18(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM18_SHIFT)) & PMC_PDRUNCFG2_SRAM18_MASK)

#define PMC_PDRUNCFG2_SRAM19_MASK                (0x80000U)
#define PMC_PDRUNCFG2_SRAM19_SHIFT               (19U)
/*! SRAM19 - Power Down RAM Partition 19 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM19(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM19_SHIFT)) & PMC_PDRUNCFG2_SRAM19_MASK)

#define PMC_PDRUNCFG2_SRAM20_MASK                (0x100000U)
#define PMC_PDRUNCFG2_SRAM20_SHIFT               (20U)
/*! SRAM20 - Power Down RAM Partition 20 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM20(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM20_SHIFT)) & PMC_PDRUNCFG2_SRAM20_MASK)

#define PMC_PDRUNCFG2_SRAM21_MASK                (0x200000U)
#define PMC_PDRUNCFG2_SRAM21_SHIFT               (21U)
/*! SRAM21 - Power Down RAM Partition 21 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM21(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM21_SHIFT)) & PMC_PDRUNCFG2_SRAM21_MASK)

#define PMC_PDRUNCFG2_SRAM22_MASK                (0x400000U)
#define PMC_PDRUNCFG2_SRAM22_SHIFT               (22U)
/*! SRAM22 - Power Down RAM Partition 22 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM22(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM22_SHIFT)) & PMC_PDRUNCFG2_SRAM22_MASK)

#define PMC_PDRUNCFG2_SRAM23_MASK                (0x800000U)
#define PMC_PDRUNCFG2_SRAM23_SHIFT               (23U)
/*! SRAM23 - Power Down RAM Partition 23 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM23(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM23_SHIFT)) & PMC_PDRUNCFG2_SRAM23_MASK)

#define PMC_PDRUNCFG2_SRAM24_MASK                (0x1000000U)
#define PMC_PDRUNCFG2_SRAM24_SHIFT               (24U)
/*! SRAM24 - Power Down RAM Partition 24 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM24(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM24_SHIFT)) & PMC_PDRUNCFG2_SRAM24_MASK)

#define PMC_PDRUNCFG2_SRAM25_MASK                (0x2000000U)
#define PMC_PDRUNCFG2_SRAM25_SHIFT               (25U)
/*! SRAM25 - Power Down RAM Partition 25 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM25(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM25_SHIFT)) & PMC_PDRUNCFG2_SRAM25_MASK)

#define PMC_PDRUNCFG2_SRAM26_MASK                (0x4000000U)
#define PMC_PDRUNCFG2_SRAM26_SHIFT               (26U)
/*! SRAM26 - Power Down RAM Partition 26 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM26(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM26_SHIFT)) & PMC_PDRUNCFG2_SRAM26_MASK)

#define PMC_PDRUNCFG2_SRAM27_MASK                (0x8000000U)
#define PMC_PDRUNCFG2_SRAM27_SHIFT               (27U)
/*! SRAM27 - Power Down RAM Partition 27 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM27(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM27_SHIFT)) & PMC_PDRUNCFG2_SRAM27_MASK)

#define PMC_PDRUNCFG2_SRAM28_MASK                (0x10000000U)
#define PMC_PDRUNCFG2_SRAM28_SHIFT               (28U)
/*! SRAM28 - Power Down RAM Partition 28 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM28(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM28_SHIFT)) & PMC_PDRUNCFG2_SRAM28_MASK)

#define PMC_PDRUNCFG2_SRAM29_MASK                (0x20000000U)
#define PMC_PDRUNCFG2_SRAM29_SHIFT               (29U)
/*! SRAM29 - Power Down RAM Partition 29 Array
 *  0b1..Power down
 *  0b0..Array power on, periphery power controlled by PD*CFG3
 */
#define PMC_PDRUNCFG2_SRAM29(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG2_SRAM29_SHIFT)) & PMC_PDRUNCFG2_SRAM29_MASK)
/*! @} */

/*! @name PDRUNCFG3 - PD Run Configuration 3 in Compute Domain */
/*! @{ */

#define PMC_PDRUNCFG3_SRAM1_MASK                 (0x2U)
#define PMC_PDRUNCFG3_SRAM1_SHIFT                (1U)
/*! SRAM1 - Power Down RAM Partition 1 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 1 is 0.
 */
#define PMC_PDRUNCFG3_SRAM1(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM1_SHIFT)) & PMC_PDRUNCFG3_SRAM1_MASK)

#define PMC_PDRUNCFG3_SRAM2_MASK                 (0x4U)
#define PMC_PDRUNCFG3_SRAM2_SHIFT                (2U)
/*! SRAM2 - Power Down RAM Partition 2 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 2 is 0.
 */
#define PMC_PDRUNCFG3_SRAM2(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM2_SHIFT)) & PMC_PDRUNCFG3_SRAM2_MASK)

#define PMC_PDRUNCFG3_SRAM3_MASK                 (0x8U)
#define PMC_PDRUNCFG3_SRAM3_SHIFT                (3U)
/*! SRAM3 - Power Down RAM Partition 3 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 3 is 0.
 */
#define PMC_PDRUNCFG3_SRAM3(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM3_SHIFT)) & PMC_PDRUNCFG3_SRAM3_MASK)

#define PMC_PDRUNCFG3_SRAM4_MASK                 (0x10U)
#define PMC_PDRUNCFG3_SRAM4_SHIFT                (4U)
/*! SRAM4 - Power Down RAM Partition 4 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 4 is 0.
 */
#define PMC_PDRUNCFG3_SRAM4(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM4_SHIFT)) & PMC_PDRUNCFG3_SRAM4_MASK)

#define PMC_PDRUNCFG3_SRAM5_MASK                 (0x20U)
#define PMC_PDRUNCFG3_SRAM5_SHIFT                (5U)
/*! SRAM5 - Power Down RAM Partition 5 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 5 is 0.
 */
#define PMC_PDRUNCFG3_SRAM5(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM5_SHIFT)) & PMC_PDRUNCFG3_SRAM5_MASK)

#define PMC_PDRUNCFG3_SRAM6_MASK                 (0x40U)
#define PMC_PDRUNCFG3_SRAM6_SHIFT                (6U)
/*! SRAM6 - Power Down RAM Partition 6 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 6 is 0.
 */
#define PMC_PDRUNCFG3_SRAM6(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM6_SHIFT)) & PMC_PDRUNCFG3_SRAM6_MASK)

#define PMC_PDRUNCFG3_SRAM7_MASK                 (0x80U)
#define PMC_PDRUNCFG3_SRAM7_SHIFT                (7U)
/*! SRAM7 - Power Down RAM Partition 7 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 7 is 0.
 */
#define PMC_PDRUNCFG3_SRAM7(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM7_SHIFT)) & PMC_PDRUNCFG3_SRAM7_MASK)

#define PMC_PDRUNCFG3_SRAM8_MASK                 (0x100U)
#define PMC_PDRUNCFG3_SRAM8_SHIFT                (8U)
/*! SRAM8 - Power Down RAM Partition 8 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 8 is 0.
 */
#define PMC_PDRUNCFG3_SRAM8(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM8_SHIFT)) & PMC_PDRUNCFG3_SRAM8_MASK)

#define PMC_PDRUNCFG3_SRAM9_MASK                 (0x200U)
#define PMC_PDRUNCFG3_SRAM9_SHIFT                (9U)
/*! SRAM9 - Power Down RAM Partition 9 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 9 is 0.
 */
#define PMC_PDRUNCFG3_SRAM9(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM9_SHIFT)) & PMC_PDRUNCFG3_SRAM9_MASK)

#define PMC_PDRUNCFG3_SRAM10_MASK                (0x400U)
#define PMC_PDRUNCFG3_SRAM10_SHIFT               (10U)
/*! SRAM10 - Power Down RAM Partition 10 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 10 is 0.
 */
#define PMC_PDRUNCFG3_SRAM10(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM10_SHIFT)) & PMC_PDRUNCFG3_SRAM10_MASK)

#define PMC_PDRUNCFG3_SRAM11_MASK                (0x800U)
#define PMC_PDRUNCFG3_SRAM11_SHIFT               (11U)
/*! SRAM11 - Power Down RAM Partition 11 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 11 is 0.
 */
#define PMC_PDRUNCFG3_SRAM11(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM11_SHIFT)) & PMC_PDRUNCFG3_SRAM11_MASK)

#define PMC_PDRUNCFG3_SRAM12_MASK                (0x1000U)
#define PMC_PDRUNCFG3_SRAM12_SHIFT               (12U)
/*! SRAM12 - Power Down RAM Partition 12 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 12 is 0.
 */
#define PMC_PDRUNCFG3_SRAM12(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM12_SHIFT)) & PMC_PDRUNCFG3_SRAM12_MASK)

#define PMC_PDRUNCFG3_SRAM13_MASK                (0x2000U)
#define PMC_PDRUNCFG3_SRAM13_SHIFT               (13U)
/*! SRAM13 - Power Down RAM Partition 13 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 13 is 0.
 */
#define PMC_PDRUNCFG3_SRAM13(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM13_SHIFT)) & PMC_PDRUNCFG3_SRAM13_MASK)

#define PMC_PDRUNCFG3_SRAM14_MASK                (0x4000U)
#define PMC_PDRUNCFG3_SRAM14_SHIFT               (14U)
/*! SRAM14 - Power Down RAM Partition 14 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 14 is 0.
 */
#define PMC_PDRUNCFG3_SRAM14(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM14_SHIFT)) & PMC_PDRUNCFG3_SRAM14_MASK)

#define PMC_PDRUNCFG3_SRAM15_MASK                (0x8000U)
#define PMC_PDRUNCFG3_SRAM15_SHIFT               (15U)
/*! SRAM15 - Power Down RAM Partition 15 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 15 is 0.
 */
#define PMC_PDRUNCFG3_SRAM15(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM15_SHIFT)) & PMC_PDRUNCFG3_SRAM15_MASK)

#define PMC_PDRUNCFG3_SRAM16_MASK                (0x10000U)
#define PMC_PDRUNCFG3_SRAM16_SHIFT               (16U)
/*! SRAM16 - Power Down RAM Partition 16 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 16 is 0.
 */
#define PMC_PDRUNCFG3_SRAM16(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM16_SHIFT)) & PMC_PDRUNCFG3_SRAM16_MASK)

#define PMC_PDRUNCFG3_SRAM17_MASK                (0x20000U)
#define PMC_PDRUNCFG3_SRAM17_SHIFT               (17U)
/*! SRAM17 - Power Down RAM Partition 17 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 17 is 0.
 */
#define PMC_PDRUNCFG3_SRAM17(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM17_SHIFT)) & PMC_PDRUNCFG3_SRAM17_MASK)

#define PMC_PDRUNCFG3_SRAM18_MASK                (0x40000U)
#define PMC_PDRUNCFG3_SRAM18_SHIFT               (18U)
/*! SRAM18 - Power Down RAM Partition 18 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 18 is 0.
 */
#define PMC_PDRUNCFG3_SRAM18(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM18_SHIFT)) & PMC_PDRUNCFG3_SRAM18_MASK)

#define PMC_PDRUNCFG3_SRAM19_MASK                (0x80000U)
#define PMC_PDRUNCFG3_SRAM19_SHIFT               (19U)
/*! SRAM19 - Power Down RAM Partition 19 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 19 is 0.
 */
#define PMC_PDRUNCFG3_SRAM19(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM19_SHIFT)) & PMC_PDRUNCFG3_SRAM19_MASK)

#define PMC_PDRUNCFG3_SRAM20_MASK                (0x100000U)
#define PMC_PDRUNCFG3_SRAM20_SHIFT               (20U)
/*! SRAM20 - Power Down RAM Partition 20 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 20 is 0.
 */
#define PMC_PDRUNCFG3_SRAM20(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM20_SHIFT)) & PMC_PDRUNCFG3_SRAM20_MASK)

#define PMC_PDRUNCFG3_SRAM21_MASK                (0x200000U)
#define PMC_PDRUNCFG3_SRAM21_SHIFT               (21U)
/*! SRAM21 - Power Down RAM Partition 21 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 21 is 0.
 */
#define PMC_PDRUNCFG3_SRAM21(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM21_SHIFT)) & PMC_PDRUNCFG3_SRAM21_MASK)

#define PMC_PDRUNCFG3_SRAM22_MASK                (0x400000U)
#define PMC_PDRUNCFG3_SRAM22_SHIFT               (22U)
/*! SRAM22 - Power Down RAM Partition 22 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 22 is 0.
 */
#define PMC_PDRUNCFG3_SRAM22(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM22_SHIFT)) & PMC_PDRUNCFG3_SRAM22_MASK)

#define PMC_PDRUNCFG3_SRAM23_MASK                (0x800000U)
#define PMC_PDRUNCFG3_SRAM23_SHIFT               (23U)
/*! SRAM23 - Power Down RAM Partition 23 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 23 is 0.
 */
#define PMC_PDRUNCFG3_SRAM23(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM23_SHIFT)) & PMC_PDRUNCFG3_SRAM23_MASK)

#define PMC_PDRUNCFG3_SRAM24_MASK                (0x1000000U)
#define PMC_PDRUNCFG3_SRAM24_SHIFT               (24U)
/*! SRAM24 - Power Down RAM Partition 24 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 24 is 0.
 */
#define PMC_PDRUNCFG3_SRAM24(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM24_SHIFT)) & PMC_PDRUNCFG3_SRAM24_MASK)

#define PMC_PDRUNCFG3_SRAM25_MASK                (0x2000000U)
#define PMC_PDRUNCFG3_SRAM25_SHIFT               (25U)
/*! SRAM25 - Power Down RAM Partition 25 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 25 is 0.
 */
#define PMC_PDRUNCFG3_SRAM25(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM25_SHIFT)) & PMC_PDRUNCFG3_SRAM25_MASK)

#define PMC_PDRUNCFG3_SRAM26_MASK                (0x4000000U)
#define PMC_PDRUNCFG3_SRAM26_SHIFT               (26U)
/*! SRAM26 - Power Down RAM Partition 26 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 26 is 0.
 */
#define PMC_PDRUNCFG3_SRAM26(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM26_SHIFT)) & PMC_PDRUNCFG3_SRAM26_MASK)

#define PMC_PDRUNCFG3_SRAM27_MASK                (0x8000000U)
#define PMC_PDRUNCFG3_SRAM27_SHIFT               (27U)
/*! SRAM27 - Power Down RAM Partition 27 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 27 is 0.
 */
#define PMC_PDRUNCFG3_SRAM27(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM27_SHIFT)) & PMC_PDRUNCFG3_SRAM27_MASK)

#define PMC_PDRUNCFG3_SRAM28_MASK                (0x10000000U)
#define PMC_PDRUNCFG3_SRAM28_SHIFT               (28U)
/*! SRAM28 - Power Down RAM Partition 28 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 28 is 0.
 */
#define PMC_PDRUNCFG3_SRAM28(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM28_SHIFT)) & PMC_PDRUNCFG3_SRAM28_MASK)

#define PMC_PDRUNCFG3_SRAM29_MASK                (0x20000000U)
#define PMC_PDRUNCFG3_SRAM29_SHIFT               (29U)
/*! SRAM29 - Power Down RAM Partition 29 Periphery
 *  0b1..Power down
 *  0b0..Power on when the corresponding array SRAM 29 is 0.
 */
#define PMC_PDRUNCFG3_SRAM29(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG3_SRAM29_SHIFT)) & PMC_PDRUNCFG3_SRAM29_MASK)
/*! @} */

/*! @name PDRUNCFG4 - PD Run Configuration 4 in Compute Domain */
/*! @{ */

#define PMC_PDRUNCFG4_SDHC0_SRAM_MASK            (0x1U)
#define PMC_PDRUNCFG4_SDHC0_SRAM_SHIFT           (0U)
/*! SDHC0_SRAM - uSDHC0 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_SDHC0_SRAM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_SDHC0_SRAM_SHIFT)) & PMC_PDRUNCFG4_SDHC0_SRAM_MASK)

#define PMC_PDRUNCFG4_SDHC1_SRAM_MASK            (0x2U)
#define PMC_PDRUNCFG4_SDHC1_SRAM_SHIFT           (1U)
/*! SDHC1_SRAM - uSDHC1 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_SDHC1_SRAM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_SDHC1_SRAM_SHIFT)) & PMC_PDRUNCFG4_SDHC1_SRAM_MASK)

#define PMC_PDRUNCFG4_USB0_SRAM_MASK             (0x4U)
#define PMC_PDRUNCFG4_USB0_SRAM_SHIFT            (2U)
/*! USB0_SRAM - USB0 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_USB0_SRAM(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_USB0_SRAM_SHIFT)) & PMC_PDRUNCFG4_USB0_SRAM_MASK)

#define PMC_PDRUNCFG4_USB1_SRAM_MASK             (0x8U)
#define PMC_PDRUNCFG4_USB1_SRAM_SHIFT            (3U)
/*! USB1_SRAM - USB1 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_USB1_SRAM(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_USB1_SRAM_SHIFT)) & PMC_PDRUNCFG4_USB1_SRAM_MASK)

#define PMC_PDRUNCFG4_JPEG_MASK                  (0x10U)
#define PMC_PDRUNCFG4_JPEG_SHIFT                 (4U)
/*! JPEG - JPEGDEC
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_JPEG(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_JPEG_SHIFT)) & PMC_PDRUNCFG4_JPEG_MASK)

#define PMC_PDRUNCFG4_PNG_MASK                   (0x20U)
#define PMC_PDRUNCFG4_PNG_SHIFT                  (5U)
/*! PNG - PNGDEC
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_PNG(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_PNG_SHIFT)) & PMC_PDRUNCFG4_PNG_MASK)

#define PMC_PDRUNCFG4_MIPI_MASK                  (0x40U)
#define PMC_PDRUNCFG4_MIPI_SHIFT                 (6U)
/*! MIPI - MIPI PHY
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_MIPI(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_MIPI_SHIFT)) & PMC_PDRUNCFG4_MIPI_MASK)

#define PMC_PDRUNCFG4_GPU_MASK                   (0x80U)
#define PMC_PDRUNCFG4_GPU_SHIFT                  (7U)
/*! GPU - VGPU
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_GPU(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_GPU_SHIFT)) & PMC_PDRUNCFG4_GPU_MASK)

#define PMC_PDRUNCFG4_DMA2_3_MASK                (0x100U)
#define PMC_PDRUNCFG4_DMA2_3_SHIFT               (8U)
/*! DMA2_3 - DMA2 and DMA3
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_DMA2_3(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_DMA2_3_SHIFT)) & PMC_PDRUNCFG4_DMA2_3_MASK)

#define PMC_PDRUNCFG4_DMA0_1_P_E_MASK            (0x200U)
#define PMC_PDRUNCFG4_DMA0_1_P_E_SHIFT           (9U)
/*! DMA0_1_P_E - DMA0-1, PKC, and ETF
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_DMA0_1_P_E(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_DMA0_1_P_E_SHIFT)) & PMC_PDRUNCFG4_DMA0_1_P_E_MASK)

#define PMC_PDRUNCFG4_CPU0_CCACHE_MASK           (0x400U)
#define PMC_PDRUNCFG4_CPU0_CCACHE_SHIFT          (10U)
/*! CPU0_CCACHE - CPU0 Code Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_CPU0_CCACHE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_CPU0_CCACHE_SHIFT)) & PMC_PDRUNCFG4_CPU0_CCACHE_MASK)

#define PMC_PDRUNCFG4_CPU0_SCACHE_MASK           (0x800U)
#define PMC_PDRUNCFG4_CPU0_SCACHE_SHIFT          (11U)
/*! CPU0_SCACHE - CPU0 System Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_CPU0_SCACHE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_CPU0_SCACHE_SHIFT)) & PMC_PDRUNCFG4_CPU0_SCACHE_MASK)

#define PMC_PDRUNCFG4_DSP_ICACHE_MASK            (0x1000U)
#define PMC_PDRUNCFG4_DSP_ICACHE_SHIFT           (12U)
/*! DSP_ICACHE - HiFi4 Instruction Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_DSP_ICACHE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_DSP_ICACHE_SHIFT)) & PMC_PDRUNCFG4_DSP_ICACHE_MASK)

#define PMC_PDRUNCFG4_DSP_DCACHE_MASK            (0x2000U)
#define PMC_PDRUNCFG4_DSP_DCACHE_SHIFT           (13U)
/*! DSP_DCACHE - HiFi4 Data Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_DSP_DCACHE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_DSP_DCACHE_SHIFT)) & PMC_PDRUNCFG4_DSP_DCACHE_MASK)

#define PMC_PDRUNCFG4_DSP_ITCM_MASK              (0x4000U)
#define PMC_PDRUNCFG4_DSP_ITCM_SHIFT             (14U)
/*! DSP_ITCM - HiFi4 Instruction TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_DSP_ITCM(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_DSP_ITCM_SHIFT)) & PMC_PDRUNCFG4_DSP_ITCM_MASK)

#define PMC_PDRUNCFG4_DSP_DTCM_MASK              (0x8000U)
#define PMC_PDRUNCFG4_DSP_DTCM_SHIFT             (15U)
/*! DSP_DTCM - HiFi4 Data TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_DSP_DTCM(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_DSP_DTCM_SHIFT)) & PMC_PDRUNCFG4_DSP_DTCM_MASK)

#define PMC_PDRUNCFG4_EZH_TCM_MASK               (0x10000U)
#define PMC_PDRUNCFG4_EZH_TCM_SHIFT              (16U)
/*! EZH_TCM - EZH-V TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_EZH_TCM(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_EZH_TCM_SHIFT)) & PMC_PDRUNCFG4_EZH_TCM_MASK)

#define PMC_PDRUNCFG4_NPU_MASK                   (0x20000U)
#define PMC_PDRUNCFG4_NPU_SHIFT                  (17U)
/*! NPU - NPU
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_NPU(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_NPU_SHIFT)) & PMC_PDRUNCFG4_NPU_MASK)

#define PMC_PDRUNCFG4_XSPI0_MASK                 (0x40000U)
#define PMC_PDRUNCFG4_XSPI0_SHIFT                (18U)
/*! XSPI0 - XSPI0, MMU0, and Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_XSPI0(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_XSPI0_SHIFT)) & PMC_PDRUNCFG4_XSPI0_MASK)

#define PMC_PDRUNCFG4_XSPI1_MASK                 (0x80000U)
#define PMC_PDRUNCFG4_XSPI1_SHIFT                (19U)
/*! XSPI1 - XSPI1, MMU1, and Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_XSPI1(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_XSPI1_SHIFT)) & PMC_PDRUNCFG4_XSPI1_MASK)

#define PMC_PDRUNCFG4_XSPI2_MASK                 (0x100000U)
#define PMC_PDRUNCFG4_XSPI2_SHIFT                (20U)
/*! XSPI2 - XSPI2 and MMU2
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG4_XSPI2(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_XSPI2_SHIFT)) & PMC_PDRUNCFG4_XSPI2_MASK)

#define PMC_PDRUNCFG4_LCD_MASK                   (0x200000U)
#define PMC_PDRUNCFG4_LCD_SHIFT                  (21U)
/*! LCD - LCDIF
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG4_LCD(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_LCD_SHIFT)) & PMC_PDRUNCFG4_LCD_MASK)

#define PMC_PDRUNCFG4_OCOTP_MASK                 (0x400000U)
#define PMC_PDRUNCFG4_OCOTP_SHIFT                (22U)
/*! OCOTP - OCOTP Shadow SRAM
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG4_OCOTP(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG4_OCOTP_SHIFT)) & PMC_PDRUNCFG4_OCOTP_MASK)
/*! @} */

/*! @name PDRUNCFG5 - PD Run Configuration 5 in Compute Domain */
/*! @{ */

#define PMC_PDRUNCFG5_SDHC0_SRAM_MASK            (0x1U)
#define PMC_PDRUNCFG5_SDHC0_SRAM_SHIFT           (0U)
/*! SDHC0_SRAM - uSDHC0 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_SDHC0_SRAM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_SDHC0_SRAM_SHIFT)) & PMC_PDRUNCFG5_SDHC0_SRAM_MASK)

#define PMC_PDRUNCFG5_SDHC1_SRAM_MASK            (0x2U)
#define PMC_PDRUNCFG5_SDHC1_SRAM_SHIFT           (1U)
/*! SDHC1_SRAM - uSDHC1 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_SDHC1_SRAM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_SDHC1_SRAM_SHIFT)) & PMC_PDRUNCFG5_SDHC1_SRAM_MASK)

#define PMC_PDRUNCFG5_USB0_SRAM_MASK             (0x4U)
#define PMC_PDRUNCFG5_USB0_SRAM_SHIFT            (2U)
/*! USB0_SRAM - USB0 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_USB0_SRAM(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_USB0_SRAM_SHIFT)) & PMC_PDRUNCFG5_USB0_SRAM_MASK)

#define PMC_PDRUNCFG5_USB1_SRAM_MASK             (0x8U)
#define PMC_PDRUNCFG5_USB1_SRAM_SHIFT            (3U)
/*! USB1_SRAM - USB1 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_USB1_SRAM(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_USB1_SRAM_SHIFT)) & PMC_PDRUNCFG5_USB1_SRAM_MASK)

#define PMC_PDRUNCFG5_JPEG_MASK                  (0x10U)
#define PMC_PDRUNCFG5_JPEG_SHIFT                 (4U)
/*! JPEG - JPEGDEC
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_JPEG(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_JPEG_SHIFT)) & PMC_PDRUNCFG5_JPEG_MASK)

#define PMC_PDRUNCFG5_PNG_MASK                   (0x20U)
#define PMC_PDRUNCFG5_PNG_SHIFT                  (5U)
/*! PNG - PNGDEC
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_PNG(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_PNG_SHIFT)) & PMC_PDRUNCFG5_PNG_MASK)

#define PMC_PDRUNCFG5_MIPI_MASK                  (0x40U)
#define PMC_PDRUNCFG5_MIPI_SHIFT                 (6U)
/*! MIPI - MIPI PHY
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_MIPI(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_MIPI_SHIFT)) & PMC_PDRUNCFG5_MIPI_MASK)

#define PMC_PDRUNCFG5_GPU_MASK                   (0x80U)
#define PMC_PDRUNCFG5_GPU_SHIFT                  (7U)
/*! GPU - VGPU
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_GPU(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_GPU_SHIFT)) & PMC_PDRUNCFG5_GPU_MASK)

#define PMC_PDRUNCFG5_DMA2_3_MASK                (0x100U)
#define PMC_PDRUNCFG5_DMA2_3_SHIFT               (8U)
/*! DMA2_3 - DMA2 and DMA3
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_DMA2_3(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_DMA2_3_SHIFT)) & PMC_PDRUNCFG5_DMA2_3_MASK)

#define PMC_PDRUNCFG5_DMA0_1_P_E_MASK            (0x200U)
#define PMC_PDRUNCFG5_DMA0_1_P_E_SHIFT           (9U)
/*! DMA0_1_P_E - DMA0-1, PKC, and ETF
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_DMA0_1_P_E(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_DMA0_1_P_E_SHIFT)) & PMC_PDRUNCFG5_DMA0_1_P_E_MASK)

#define PMC_PDRUNCFG5_CPU0_CCACHE_MASK           (0x400U)
#define PMC_PDRUNCFG5_CPU0_CCACHE_SHIFT          (10U)
/*! CPU0_CCACHE - CPU0 Code Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_CPU0_CCACHE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_CPU0_CCACHE_SHIFT)) & PMC_PDRUNCFG5_CPU0_CCACHE_MASK)

#define PMC_PDRUNCFG5_CPU0_SCACHE_MASK           (0x800U)
#define PMC_PDRUNCFG5_CPU0_SCACHE_SHIFT          (11U)
/*! CPU0_SCACHE - CPU0 System Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_CPU0_SCACHE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_CPU0_SCACHE_SHIFT)) & PMC_PDRUNCFG5_CPU0_SCACHE_MASK)

#define PMC_PDRUNCFG5_DSP_ICACHE_MASK            (0x1000U)
#define PMC_PDRUNCFG5_DSP_ICACHE_SHIFT           (12U)
/*! DSP_ICACHE - HiFi4 Instruction Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_DSP_ICACHE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_DSP_ICACHE_SHIFT)) & PMC_PDRUNCFG5_DSP_ICACHE_MASK)

#define PMC_PDRUNCFG5_DSP_DCACHE_MASK            (0x2000U)
#define PMC_PDRUNCFG5_DSP_DCACHE_SHIFT           (13U)
/*! DSP_DCACHE - HiFi4 Data Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_DSP_DCACHE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_DSP_DCACHE_SHIFT)) & PMC_PDRUNCFG5_DSP_DCACHE_MASK)

#define PMC_PDRUNCFG5_DSP_ITCM_MASK              (0x4000U)
#define PMC_PDRUNCFG5_DSP_ITCM_SHIFT             (14U)
/*! DSP_ITCM - HiFi4 Instruction TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_DSP_ITCM(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_DSP_ITCM_SHIFT)) & PMC_PDRUNCFG5_DSP_ITCM_MASK)

#define PMC_PDRUNCFG5_DSP_DTCM_MASK              (0x8000U)
#define PMC_PDRUNCFG5_DSP_DTCM_SHIFT             (15U)
/*! DSP_DTCM - HiFi4 Data TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_DSP_DTCM(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_DSP_DTCM_SHIFT)) & PMC_PDRUNCFG5_DSP_DTCM_MASK)

#define PMC_PDRUNCFG5_EZH_TCM_MASK               (0x10000U)
#define PMC_PDRUNCFG5_EZH_TCM_SHIFT              (16U)
/*! EZH_TCM - EZH-V TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_EZH_TCM(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_EZH_TCM_SHIFT)) & PMC_PDRUNCFG5_EZH_TCM_MASK)

#define PMC_PDRUNCFG5_NPU_MASK                   (0x20000U)
#define PMC_PDRUNCFG5_NPU_SHIFT                  (17U)
/*! NPU - NPU
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_NPU(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_NPU_SHIFT)) & PMC_PDRUNCFG5_NPU_MASK)

#define PMC_PDRUNCFG5_XSPI0_MASK                 (0x40000U)
#define PMC_PDRUNCFG5_XSPI0_SHIFT                (18U)
/*! XSPI0 - XSPI0, MMU0, and Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_XSPI0(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_XSPI0_SHIFT)) & PMC_PDRUNCFG5_XSPI0_MASK)

#define PMC_PDRUNCFG5_XSPI1_MASK                 (0x80000U)
#define PMC_PDRUNCFG5_XSPI1_SHIFT                (19U)
/*! XSPI1 - XSPI1, MMU1, and Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_XSPI1(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_XSPI1_SHIFT)) & PMC_PDRUNCFG5_XSPI1_MASK)

#define PMC_PDRUNCFG5_XSPI2_MASK                 (0x100000U)
#define PMC_PDRUNCFG5_XSPI2_SHIFT                (20U)
/*! XSPI2 - XSPI2 and MMU2
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDRUNCFG5_XSPI2(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_XSPI2_SHIFT)) & PMC_PDRUNCFG5_XSPI2_MASK)

#define PMC_PDRUNCFG5_LCD_MASK                   (0x200000U)
#define PMC_PDRUNCFG5_LCD_SHIFT                  (21U)
/*! LCD - LCDIF
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG5_LCD(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_LCD_SHIFT)) & PMC_PDRUNCFG5_LCD_MASK)

#define PMC_PDRUNCFG5_OCOTP_MASK                 (0x400000U)
#define PMC_PDRUNCFG5_OCOTP_SHIFT                (22U)
/*! OCOTP - OCOTP Shadow SRAM
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDRUNCFG5_OCOTP(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG5_OCOTP_SHIFT)) & PMC_PDRUNCFG5_OCOTP_MASK)
/*! @} */

/*! @name PDSLEEPCFG0 - PD Sleep Configuration 0 in Compute Domain */
/*! @{ */

#define PMC_PDSLEEPCFG0_PMICMODE_MASK            (0x3U)
#define PMC_PDSLEEPCFG0_PMICMODE_SHIFT           (0U)
/*! PMICMODE - PMIC Mode
 *  0b11..Drives PMIC_MODE pins to 3h
 *  0b10..Drives PMIC_MODE pins to 2h
 *  0b01..Drives PMIC_MODE pins to 1h
 *  0b00..Drives PMIC_MODE pins to 0h
 */
#define PMC_PDSLEEPCFG0_PMICMODE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PMICMODE_SHIFT)) & PMC_PDSLEEPCFG0_PMICMODE_MASK)

#define PMC_PDSLEEPCFG0_FDSR_MASK                (0x4U)
#define PMC_PDSLEEPCFG0_FDSR_SHIFT               (2U)
/*! FDSR - Full Deep Sleep Retention (FDSR) Mode
 *  0b1..All core domains in DSR or Power Down mode
 *  0b0..All power switch states controlled by their respective PD*CFG bits
 */
#define PMC_PDSLEEPCFG0_FDSR(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_FDSR_SHIFT)) & PMC_PDSLEEPCFG0_FDSR_MASK)

#define PMC_PDSLEEPCFG0_DPD_MASK                 (0x8U)
#define PMC_PDSLEEPCFG0_DPD_SHIFT                (3U)
/*! DPD - Deep Power Down (DPD) Mode
 *  0b1..Enables DPD mode
 *  0b0..Disables
 */
#define PMC_PDSLEEPCFG0_DPD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_DPD_SHIFT)) & PMC_PDSLEEPCFG0_DPD_MASK)

#define PMC_PDSLEEPCFG0_FDPD_MASK                (0x10U)
#define PMC_PDSLEEPCFG0_FDPD_SHIFT               (4U)
/*! FDPD - Full Deep Power Down (FDPD) Mode
 *  0b1..Enables FDPD mode
 *  0b0..Disables
 */
#define PMC_PDSLEEPCFG0_FDPD(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_FDPD_SHIFT)) & PMC_PDSLEEPCFG0_FDPD_MASK)

#define PMC_PDSLEEPCFG0_V2COMP_DSR_MASK          (0x20U)
#define PMC_PDSLEEPCFG0_V2COMP_DSR_SHIFT         (5U)
/*! V2COMP_DSR - Power Switch and DSR Enable in VDD2_COMP Domain
 *  0b1..Enables DSR mode in VDD2_COMP
 *  0b0..Powers on VDD2_COMP
 */
#define PMC_PDSLEEPCFG0_V2COMP_DSR(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_V2COMP_DSR_SHIFT)) & PMC_PDSLEEPCFG0_V2COMP_DSR_MASK)

#define PMC_PDSLEEPCFG0_V2NMED_DSR_MASK          (0x40U)
#define PMC_PDSLEEPCFG0_V2NMED_DSR_SHIFT         (6U)
/*! V2NMED_DSR - Power Switch and DSR Enable in VDD2_MEDIA and VDDN_MEDIA Domains
 *  0b1..Enables DSR mode in VDD2_MEDIA and VDDN_MEDIA
 *  0b0..Powers on VDD2_MEDIA and VDDN_MEDIA
 */
#define PMC_PDSLEEPCFG0_V2NMED_DSR(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_V2NMED_DSR_SHIFT)) & PMC_PDSLEEPCFG0_V2NMED_DSR_MASK)

#define PMC_PDSLEEPCFG0_V2COM_DSR_MASK           (0x80U)
#define PMC_PDSLEEPCFG0_V2COM_DSR_SHIFT          (7U)
/*! V2COM_DSR - Power Switch and DSR Enable in VDD2_COM Domain
 *  0b1..Enables DSR mode in VDD2_COM
 *  0b0..Powers on VDD2_COM
 */
#define PMC_PDSLEEPCFG0_V2COM_DSR(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_V2COM_DSR_SHIFT)) & PMC_PDSLEEPCFG0_V2COM_DSR_MASK)

#define PMC_PDSLEEPCFG0_VNCOM_DSR_MASK           (0x100U)
#define PMC_PDSLEEPCFG0_VNCOM_DSR_SHIFT          (8U)
/*! VNCOM_DSR - Power Switch and DSR Enable in VDDN_COM Domain
 *  0b1..Enables DSR mode in VDDN_COM
 *  0b0..Powers on VDDN_COM
 */
#define PMC_PDSLEEPCFG0_VNCOM_DSR(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_VNCOM_DSR_SHIFT)) & PMC_PDSLEEPCFG0_VNCOM_DSR_MASK)

#define PMC_PDSLEEPCFG0_V2DSP_PD_MASK            (0x200U)
#define PMC_PDSLEEPCFG0_V2DSP_PD_SHIFT           (9U)
/*! V2DSP_PD - Power Down VDD2_DSP
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG0_V2DSP_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_V2DSP_PD_SHIFT)) & PMC_PDSLEEPCFG0_V2DSP_PD_MASK)

#define PMC_PDSLEEPCFG0_V2MIPI_PD_MASK           (0x400U)
#define PMC_PDSLEEPCFG0_V2MIPI_PD_SHIFT          (10U)
/*! V2MIPI_PD - Power Down MIPI PHY in VDD2 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG0_V2MIPI_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_V2MIPI_PD_SHIFT)) & PMC_PDSLEEPCFG0_V2MIPI_PD_MASK)

#define PMC_PDSLEEPCFG0_DCDC_LP_MASK             (0x1000U)
#define PMC_PDSLEEPCFG0_DCDC_LP_SHIFT            (12U)
/*! DCDC_LP - DCDC Low Power
 *  0b1..Sets DCDC in low-power mode
 *  0b0..Sets DCDC in high-power mode
 */
#define PMC_PDSLEEPCFG0_DCDC_LP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_DCDC_LP_SHIFT)) & PMC_PDSLEEPCFG0_DCDC_LP_MASK)

#define PMC_PDSLEEPCFG0_DCDC_VSEL_MASK           (0x2000U)
#define PMC_PDSLEEPCFG0_DCDC_VSEL_SHIFT          (13U)
/*! DCDC_VSEL - DCDC Voltage Select
 *  0b1..Selects DCDCVSEL[VSEL1] level
 *  0b0..Selects DCDCVSEL[VSEL0] level
 */
#define PMC_PDSLEEPCFG0_DCDC_VSEL(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_DCDC_VSEL_SHIFT)) & PMC_PDSLEEPCFG0_DCDC_VSEL_MASK)

#define PMC_PDSLEEPCFG0_LDO1_MODE_MASK           (0xC000U)
#define PMC_PDSLEEPCFG0_LDO1_MODE_SHIFT          (14U)
/*! LDO1_MODE - LDO VDD1 Regulator Mode
 *  0b10, 0b11..Low-power mode
 *  0b01..High-power mode
 *  0b00..Bypass mode
 */
#define PMC_PDSLEEPCFG0_LDO1_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_LDO1_MODE_SHIFT)) & PMC_PDSLEEPCFG0_LDO1_MODE_MASK)

#define PMC_PDSLEEPCFG0_LDO1_VSEL_MASK           (0x30000U)
#define PMC_PDSLEEPCFG0_LDO1_VSEL_SHIFT          (16U)
/*! LDO1_VSEL - LDO VDD1 Voltage Select
 *  0b00..Selects LDOVDD1VSEL[VSEL0] and LVDVDD1CTRL[LVL0] level
 *  0b01..Selects LDOVDD1VSEL[VSEL1] and LVDVDD1CTRL[LVL1] level
 *  0b10..Selects LDOVDD1VSEL[VSEL2] and LVDVDD1CTRL[LVL2] level
 *  0b11..Selects LDOVDD1VSEL[VSEL3] and LVDVDD1CTRL[LVL3] level
 */
#define PMC_PDSLEEPCFG0_LDO1_VSEL(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_LDO1_VSEL_SHIFT)) & PMC_PDSLEEPCFG0_LDO1_VSEL_MASK)

#define PMC_PDSLEEPCFG0_LDO2_MODE_MASK           (0xC0000U)
#define PMC_PDSLEEPCFG0_LDO2_MODE_SHIFT          (18U)
/*! LDO2_MODE - LDO VDD2 Regulator Mode
 *  0b10, 0b11..Low-power mode
 *  0b01..High-power mode
 *  0b00..Bypass mode
 */
#define PMC_PDSLEEPCFG0_LDO2_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_LDO2_MODE_SHIFT)) & PMC_PDSLEEPCFG0_LDO2_MODE_MASK)

#define PMC_PDSLEEPCFG0_LDO2_VSEL_MASK           (0x300000U)
#define PMC_PDSLEEPCFG0_LDO2_VSEL_SHIFT          (20U)
/*! LDO2_VSEL - LDO VDD2 Voltage Select
 *  0b00..Selects LDOVDD2VSEL[VSEL0] and LVDVDD2CTRL[LVL0] level
 *  0b01..Selects LDOVDD2VSEL[VSEL1] and LVDVDD2CTRL[LVL1] level
 *  0b10..Selects LDOVDD2VSEL[VSEL2] and LVDVDD2CTRL[LVL2] level
 *  0b11..Selects LDOVDD2VSEL[VSEL3] and LVDVDD2CTRL[LVL3] level
 */
#define PMC_PDSLEEPCFG0_LDO2_VSEL(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_LDO2_VSEL_SHIFT)) & PMC_PDSLEEPCFG0_LDO2_VSEL_MASK)

#define PMC_PDSLEEPCFG0_RBB1_PD_MASK             (0x400000U)
#define PMC_PDSLEEPCFG0_RBB1_PD_SHIFT            (22U)
/*! RBB1_PD - Power Down RBB in VDD1 Domain
 *  0b0..If PDSLEEPCFG0[AFBB1_PD] = 1, power on. Else power down
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG0_RBB1_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_RBB1_PD_SHIFT)) & PMC_PDSLEEPCFG0_RBB1_PD_MASK)

#define PMC_PDSLEEPCFG0_AFBB1_PD_MASK            (0x800000U)
#define PMC_PDSLEEPCFG0_AFBB1_PD_SHIFT           (23U)
/*! AFBB1_PD - Power Down AFBB in VDD1 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG0_AFBB1_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_AFBB1_PD_SHIFT)) & PMC_PDSLEEPCFG0_AFBB1_PD_MASK)

#define PMC_PDSLEEPCFG0_RBB2_PD_MASK             (0x1000000U)
#define PMC_PDSLEEPCFG0_RBB2_PD_SHIFT            (24U)
/*! RBB2_PD - Power Down RBB in VDD2 Domain
 *  0b1..Power down
 *  0b0..If PDSLEEPCFG0[AFBB2_PD] = 1, power on. Else power down
 */
#define PMC_PDSLEEPCFG0_RBB2_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_RBB2_PD_SHIFT)) & PMC_PDSLEEPCFG0_RBB2_PD_MASK)

#define PMC_PDSLEEPCFG0_AFBB2_PD_MASK            (0x2000000U)
#define PMC_PDSLEEPCFG0_AFBB2_PD_SHIFT           (25U)
/*! AFBB2_PD - Power Down AFBB in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG0_AFBB2_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_AFBB2_PD_SHIFT)) & PMC_PDSLEEPCFG0_AFBB2_PD_MASK)

#define PMC_PDSLEEPCFG0_RBBN_PD_MASK             (0x4000000U)
#define PMC_PDSLEEPCFG0_RBBN_PD_SHIFT            (26U)
/*! RBBN_PD - Power Down RBB in VDDN Domain
 *  0b0..If PDSLEEPCFG0[AFBBN_PD] = 1, power on. Else power down
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG0_RBBN_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_RBBN_PD_SHIFT)) & PMC_PDSLEEPCFG0_RBBN_PD_MASK)

#define PMC_PDSLEEPCFG0_AFBBN_PD_MASK            (0x8000000U)
#define PMC_PDSLEEPCFG0_AFBBN_PD_SHIFT           (27U)
/*! AFBBN_PD - Power Down AFBB in VDDN Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG0_AFBBN_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_AFBBN_PD_SHIFT)) & PMC_PDSLEEPCFG0_AFBBN_PD_MASK)

#define PMC_PDSLEEPCFG0_RBBSR1_PD_MASK           (0x10000000U)
#define PMC_PDSLEEPCFG0_RBBSR1_PD_SHIFT          (28U)
/*! RBBSR1_PD - Power Down SRAM RBB in VDD1 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG0_RBBSR1_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_RBBSR1_PD_SHIFT)) & PMC_PDSLEEPCFG0_RBBSR1_PD_MASK)

#define PMC_PDSLEEPCFG0_RBBSR2_PD_MASK           (0x20000000U)
#define PMC_PDSLEEPCFG0_RBBSR2_PD_SHIFT          (29U)
/*! RBBSR2_PD - Power Down SRAM RBB in VDD2 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG0_RBBSR2_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_RBBSR2_PD_SHIFT)) & PMC_PDSLEEPCFG0_RBBSR2_PD_MASK)

#define PMC_PDSLEEPCFG0_AFBBSR2_PD_MASK          (0x80000000U)
#define PMC_PDSLEEPCFG0_AFBBSR2_PD_SHIFT         (31U)
/*! AFBBSR2_PD - Power Down SRAM AFBB in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG0_AFBBSR2_PD(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_AFBBSR2_PD_SHIFT)) & PMC_PDSLEEPCFG0_AFBBSR2_PD_MASK)
/*! @} */

/*! @name PDSLEEPCFG1 - PD Sleep Configuration 1 in Compute Domain */
/*! @{ */

#define PMC_PDSLEEPCFG1_TEMP_PD_MASK             (0x1U)
#define PMC_PDSLEEPCFG1_TEMP_PD_SHIFT            (0U)
/*! TEMP_PD - PMC Temperature Sensor Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG1_TEMP_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_TEMP_PD_SHIFT)) & PMC_PDSLEEPCFG1_TEMP_PD_MASK)

#define PMC_PDSLEEPCFG1_PMCREF_LP_MASK           (0x2U)
#define PMC_PDSLEEPCFG1_PMCREF_LP_SHIFT          (1U)
/*! PMCREF_LP - PMC References Low Power
 *  0b1..Low-power mode if not overridden by any *_PD bits
 *  0b0..High-power mode
 */
#define PMC_PDSLEEPCFG1_PMCREF_LP(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PMCREF_LP_SHIFT)) & PMC_PDSLEEPCFG1_PMCREF_LP_MASK)

#define PMC_PDSLEEPCFG1_HVD1V8_PD_MASK           (0x4U)
#define PMC_PDSLEEPCFG1_HVD1V8_PD_SHIFT          (2U)
/*! HVD1V8_PD - HVD VDD1V8 Power Down
 *  0b1..Power down
 *  0b0..Power on. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 */
#define PMC_PDSLEEPCFG1_HVD1V8_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_HVD1V8_PD_SHIFT)) & PMC_PDSLEEPCFG1_HVD1V8_PD_MASK)

#define PMC_PDSLEEPCFG1_POR1_LP_MASK             (0x8U)
#define PMC_PDSLEEPCFG1_POR1_LP_SHIFT            (3U)
/*! POR1_LP - POR Low Power in VDD1 Domain
 *  0b1..Low-power mode
 *  0b0..High-power mode. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 */
#define PMC_PDSLEEPCFG1_POR1_LP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_POR1_LP_SHIFT)) & PMC_PDSLEEPCFG1_POR1_LP_MASK)

#define PMC_PDSLEEPCFG1_LVD1_LP_MASK             (0x10U)
#define PMC_PDSLEEPCFG1_LVD1_LP_SHIFT            (4U)
/*! LVD1_LP - LVD Low power in VDD1 Domain
 *  0b0..High-power mode. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 *  0b1..Low-power mode
 */
#define PMC_PDSLEEPCFG1_LVD1_LP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_LVD1_LP_SHIFT)) & PMC_PDSLEEPCFG1_LVD1_LP_MASK)

#define PMC_PDSLEEPCFG1_HVD1_PD_MASK             (0x20U)
#define PMC_PDSLEEPCFG1_HVD1_PD_SHIFT            (5U)
/*! HVD1_PD - HVD Power Down in VDD1 Domain
 *  0b1..Power down
 *  0b0..Power on. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 */
#define PMC_PDSLEEPCFG1_HVD1_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_HVD1_PD_SHIFT)) & PMC_PDSLEEPCFG1_HVD1_PD_MASK)

#define PMC_PDSLEEPCFG1_AGDET1_PD_MASK           (0x40U)
#define PMC_PDSLEEPCFG1_AGDET1_PD_SHIFT          (6U)
/*! AGDET1_PD - AGDET Power Down in VDD1 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG1_AGDET1_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_AGDET1_PD_SHIFT)) & PMC_PDSLEEPCFG1_AGDET1_PD_MASK)

#define PMC_PDSLEEPCFG1_POR2_LP_MASK             (0x80U)
#define PMC_PDSLEEPCFG1_POR2_LP_SHIFT            (7U)
/*! POR2_LP - POR Low power in VDD2 Domain
 *  0b0..High-power mode. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 *  0b1..Low-power mode
 */
#define PMC_PDSLEEPCFG1_POR2_LP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_POR2_LP_SHIFT)) & PMC_PDSLEEPCFG1_POR2_LP_MASK)

#define PMC_PDSLEEPCFG1_LVD2_LP_MASK             (0x100U)
#define PMC_PDSLEEPCFG1_LVD2_LP_SHIFT            (8U)
/*! LVD2_LP - LVD Low power in VDD2 Domain
 *  0b1..Low-power mode
 *  0b0..High-power mode. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 */
#define PMC_PDSLEEPCFG1_LVD2_LP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_LVD2_LP_SHIFT)) & PMC_PDSLEEPCFG1_LVD2_LP_MASK)

#define PMC_PDSLEEPCFG1_HVD2_PD_MASK             (0x200U)
#define PMC_PDSLEEPCFG1_HVD2_PD_SHIFT            (9U)
/*! HVD2_PD - HVD Power Down in VDD2 Domain
 *  0b0..Power on. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG1_HVD2_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_HVD2_PD_SHIFT)) & PMC_PDSLEEPCFG1_HVD2_PD_MASK)

#define PMC_PDSLEEPCFG1_AGDET2_PD_MASK           (0x400U)
#define PMC_PDSLEEPCFG1_AGDET2_PD_SHIFT          (10U)
/*! AGDET2_PD - AGDET Power Down in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG1_AGDET2_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_AGDET2_PD_SHIFT)) & PMC_PDSLEEPCFG1_AGDET2_PD_MASK)

#define PMC_PDSLEEPCFG1_PORN_LP_MASK             (0x800U)
#define PMC_PDSLEEPCFG1_PORN_LP_SHIFT            (11U)
/*! PORN_LP - POR Low Power in VDDN Domain
 *  0b0..High-power mode. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 *  0b1..Low-power mode
 */
#define PMC_PDSLEEPCFG1_PORN_LP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PORN_LP_SHIFT)) & PMC_PDSLEEPCFG1_PORN_LP_MASK)

#define PMC_PDSLEEPCFG1_LVDN_LP_MASK             (0x1000U)
#define PMC_PDSLEEPCFG1_LVDN_LP_SHIFT            (12U)
/*! LVDN_LP - LVD Low power in VDDN Domain
 *  0b0..High-power mode. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 *  0b1..Low-power mode
 */
#define PMC_PDSLEEPCFG1_LVDN_LP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_LVDN_LP_SHIFT)) & PMC_PDSLEEPCFG1_LVDN_LP_MASK)

#define PMC_PDSLEEPCFG1_HVDN_PD_MASK             (0x2000U)
#define PMC_PDSLEEPCFG1_HVDN_PD_SHIFT            (13U)
/*! HVDN_PD - HVD Power Down in VDDN Domain
 *  0b1..Power down
 *  0b0..Power on. In this case the aggregated PDCFGSTATUS1[PMCREF_LP] bit will be in high-power mode
 */
#define PMC_PDSLEEPCFG1_HVDN_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_HVDN_PD_SHIFT)) & PMC_PDSLEEPCFG1_HVDN_PD_MASK)

#define PMC_PDSLEEPCFG1_OTP_PD_MASK              (0x8000U)
#define PMC_PDSLEEPCFG1_OTP_PD_SHIFT             (15U)
/*! OTP_PD - OTP Power Down in VDD2 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG1_OTP_PD(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_OTP_PD_SHIFT)) & PMC_PDSLEEPCFG1_OTP_PD_MASK)

#define PMC_PDSLEEPCFG1_ROM_PD_MASK              (0x10000U)
#define PMC_PDSLEEPCFG1_ROM_PD_SHIFT             (16U)
/*! ROM_PD - ROM Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG1_ROM_PD(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_ROM_PD_SHIFT)) & PMC_PDSLEEPCFG1_ROM_PD_MASK)

#define PMC_PDSLEEPCFG1_SRAMSLEEP_MASK           (0x80000000U)
#define PMC_PDSLEEPCFG1_SRAMSLEEP_SHIFT          (31U)
/*! SRAMSLEEP - SRAM Sleep Mode
 *  0b0..Normal
 *  0b1..Sleep
 */
#define PMC_PDSLEEPCFG1_SRAMSLEEP(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_SRAMSLEEP_SHIFT)) & PMC_PDSLEEPCFG1_SRAMSLEEP_MASK)
/*! @} */

/*! @name PDSLEEPCFG2 - PD Sleep Configuration 2 in Compute Domain */
/*! @{ */

#define PMC_PDSLEEPCFG2_SRAM0_MASK               (0x1U)
#define PMC_PDSLEEPCFG2_SRAM0_SHIFT              (0U)
/*! SRAM0 - RAM Partition 0 Array Power Down
 *  0b1..Powers down RAM Partition 0 array and periphery
 *  0b0..Powers on RAM Partition 0 array
 */
#define PMC_PDSLEEPCFG2_SRAM0(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM0_SHIFT)) & PMC_PDSLEEPCFG2_SRAM0_MASK)

#define PMC_PDSLEEPCFG2_SRAM1_MASK               (0x2U)
#define PMC_PDSLEEPCFG2_SRAM1_SHIFT              (1U)
/*! SRAM1 - RAM Partition 1 Array Power Down
 *  0b1..Powers down RAM Partition 1 array and periphery
 *  0b0..Powers on RAM Partition 1 array
 */
#define PMC_PDSLEEPCFG2_SRAM1(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM1_SHIFT)) & PMC_PDSLEEPCFG2_SRAM1_MASK)

#define PMC_PDSLEEPCFG2_SRAM2_MASK               (0x4U)
#define PMC_PDSLEEPCFG2_SRAM2_SHIFT              (2U)
/*! SRAM2 - RAM Partition 2 Array Power Down
 *  0b1..Powers down RAM Partition 2 array and periphery
 *  0b0..Powers on RAM Partition 2 array
 */
#define PMC_PDSLEEPCFG2_SRAM2(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM2_SHIFT)) & PMC_PDSLEEPCFG2_SRAM2_MASK)

#define PMC_PDSLEEPCFG2_SRAM3_MASK               (0x8U)
#define PMC_PDSLEEPCFG2_SRAM3_SHIFT              (3U)
/*! SRAM3 - RAM Partition 3 Array Power Down
 *  0b1..Powers down RAM Partition 3 array and periphery
 *  0b0..Powers on RAM Partition 3 array
 */
#define PMC_PDSLEEPCFG2_SRAM3(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM3_SHIFT)) & PMC_PDSLEEPCFG2_SRAM3_MASK)

#define PMC_PDSLEEPCFG2_SRAM4_MASK               (0x10U)
#define PMC_PDSLEEPCFG2_SRAM4_SHIFT              (4U)
/*! SRAM4 - RAM Partition 4 Array Power Down
 *  0b1..Powers down RAM Partition 4 array and periphery
 *  0b0..Powers on RAM Partition 4 array
 */
#define PMC_PDSLEEPCFG2_SRAM4(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM4_SHIFT)) & PMC_PDSLEEPCFG2_SRAM4_MASK)

#define PMC_PDSLEEPCFG2_SRAM5_MASK               (0x20U)
#define PMC_PDSLEEPCFG2_SRAM5_SHIFT              (5U)
/*! SRAM5 - RAM Partition 5 Array Power Down
 *  0b1..Powers down RAM Partition 5 array and periphery
 *  0b0..Powers on RAM Partition 5 array
 */
#define PMC_PDSLEEPCFG2_SRAM5(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM5_SHIFT)) & PMC_PDSLEEPCFG2_SRAM5_MASK)

#define PMC_PDSLEEPCFG2_SRAM6_MASK               (0x40U)
#define PMC_PDSLEEPCFG2_SRAM6_SHIFT              (6U)
/*! SRAM6 - RAM Partition 6 Array Power Down
 *  0b1..Powers down RAM Partition 6 array and periphery
 *  0b0..Powers on RAM Partition 6 array
 */
#define PMC_PDSLEEPCFG2_SRAM6(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM6_SHIFT)) & PMC_PDSLEEPCFG2_SRAM6_MASK)

#define PMC_PDSLEEPCFG2_SRAM7_MASK               (0x80U)
#define PMC_PDSLEEPCFG2_SRAM7_SHIFT              (7U)
/*! SRAM7 - RAM Partition 7 Array Power Down
 *  0b1..Powers down RAM Partition 7 array and periphery
 *  0b0..Powers on RAM Partition 7 array
 */
#define PMC_PDSLEEPCFG2_SRAM7(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM7_SHIFT)) & PMC_PDSLEEPCFG2_SRAM7_MASK)

#define PMC_PDSLEEPCFG2_SRAM8_MASK               (0x100U)
#define PMC_PDSLEEPCFG2_SRAM8_SHIFT              (8U)
/*! SRAM8 - RAM Partition 8 Array Power Down
 *  0b1..Powers down RAM Partition 8 array and periphery
 *  0b0..Powers on RAM Partition 8 array
 */
#define PMC_PDSLEEPCFG2_SRAM8(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM8_SHIFT)) & PMC_PDSLEEPCFG2_SRAM8_MASK)

#define PMC_PDSLEEPCFG2_SRAM9_MASK               (0x200U)
#define PMC_PDSLEEPCFG2_SRAM9_SHIFT              (9U)
/*! SRAM9 - RAM Partition 9 Array Power Down
 *  0b1..Powers down RAM Partition 9 array and periphery
 *  0b0..Powers on RAM Partition 9 array
 */
#define PMC_PDSLEEPCFG2_SRAM9(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM9_SHIFT)) & PMC_PDSLEEPCFG2_SRAM9_MASK)

#define PMC_PDSLEEPCFG2_SRAM10_MASK              (0x400U)
#define PMC_PDSLEEPCFG2_SRAM10_SHIFT             (10U)
/*! SRAM10 - RAM Partition 10 Array Power Down
 *  0b1..Powers down RAM Partition 10 array and periphery
 *  0b0..Powers on RAM Partition 10 array
 */
#define PMC_PDSLEEPCFG2_SRAM10(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM10_SHIFT)) & PMC_PDSLEEPCFG2_SRAM10_MASK)

#define PMC_PDSLEEPCFG2_SRAM11_MASK              (0x800U)
#define PMC_PDSLEEPCFG2_SRAM11_SHIFT             (11U)
/*! SRAM11 - RAM Partition 11 Array Power Down
 *  0b1..Powers down RAM Partition 11 array and periphery
 *  0b0..Powers on RAM Partition 11 array
 */
#define PMC_PDSLEEPCFG2_SRAM11(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM11_SHIFT)) & PMC_PDSLEEPCFG2_SRAM11_MASK)

#define PMC_PDSLEEPCFG2_SRAM12_MASK              (0x1000U)
#define PMC_PDSLEEPCFG2_SRAM12_SHIFT             (12U)
/*! SRAM12 - RAM Partition 12 Array Power Down
 *  0b1..Powers down RAM Partition 12 array and periphery
 *  0b0..Powers on RAM Partition 12 array
 */
#define PMC_PDSLEEPCFG2_SRAM12(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM12_SHIFT)) & PMC_PDSLEEPCFG2_SRAM12_MASK)

#define PMC_PDSLEEPCFG2_SRAM13_MASK              (0x2000U)
#define PMC_PDSLEEPCFG2_SRAM13_SHIFT             (13U)
/*! SRAM13 - RAM Partition 13 Array Power Down
 *  0b1..Powers down RAM Partition 13 array and periphery
 *  0b0..Powers on RAM Partition 13 array
 */
#define PMC_PDSLEEPCFG2_SRAM13(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM13_SHIFT)) & PMC_PDSLEEPCFG2_SRAM13_MASK)

#define PMC_PDSLEEPCFG2_SRAM14_MASK              (0x4000U)
#define PMC_PDSLEEPCFG2_SRAM14_SHIFT             (14U)
/*! SRAM14 - RAM Partition 14 Array Power Down
 *  0b1..Powers down RAM Partition 14 array and periphery
 *  0b0..Powers on RAM Partition 14 array
 */
#define PMC_PDSLEEPCFG2_SRAM14(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM14_SHIFT)) & PMC_PDSLEEPCFG2_SRAM14_MASK)

#define PMC_PDSLEEPCFG2_SRAM15_MASK              (0x8000U)
#define PMC_PDSLEEPCFG2_SRAM15_SHIFT             (15U)
/*! SRAM15 - RAM Partition 15 Array Power Down
 *  0b1..Powers down RAM Partition 15 array and periphery
 *  0b0..Powers on RAM Partition 15 array
 */
#define PMC_PDSLEEPCFG2_SRAM15(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM15_SHIFT)) & PMC_PDSLEEPCFG2_SRAM15_MASK)

#define PMC_PDSLEEPCFG2_SRAM16_MASK              (0x10000U)
#define PMC_PDSLEEPCFG2_SRAM16_SHIFT             (16U)
/*! SRAM16 - RAM Partition 16 Array Power Down
 *  0b1..Powers down RAM Partition 16 array and periphery
 *  0b0..Powers on RAM Partition 16 array
 */
#define PMC_PDSLEEPCFG2_SRAM16(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM16_SHIFT)) & PMC_PDSLEEPCFG2_SRAM16_MASK)

#define PMC_PDSLEEPCFG2_SRAM17_MASK              (0x20000U)
#define PMC_PDSLEEPCFG2_SRAM17_SHIFT             (17U)
/*! SRAM17 - RAM Partition 17 Array Power Down
 *  0b1..Powers down RAM Partition 17 array and periphery
 *  0b0..Powers on RAM Partition 17 array
 */
#define PMC_PDSLEEPCFG2_SRAM17(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM17_SHIFT)) & PMC_PDSLEEPCFG2_SRAM17_MASK)

#define PMC_PDSLEEPCFG2_SRAM18_MASK              (0x40000U)
#define PMC_PDSLEEPCFG2_SRAM18_SHIFT             (18U)
/*! SRAM18 - RAM Partition 18 Array Power Down
 *  0b1..Powers down RAM Partition 18 array and periphery
 *  0b0..Powers on RAM Partition 18 array
 */
#define PMC_PDSLEEPCFG2_SRAM18(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM18_SHIFT)) & PMC_PDSLEEPCFG2_SRAM18_MASK)

#define PMC_PDSLEEPCFG2_SRAM19_MASK              (0x80000U)
#define PMC_PDSLEEPCFG2_SRAM19_SHIFT             (19U)
/*! SRAM19 - RAM Partition 19 Array Power Down
 *  0b1..Powers down RAM Partition 19 array and periphery
 *  0b0..Powers on RAM Partition 19 array
 */
#define PMC_PDSLEEPCFG2_SRAM19(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM19_SHIFT)) & PMC_PDSLEEPCFG2_SRAM19_MASK)

#define PMC_PDSLEEPCFG2_SRAM20_MASK              (0x100000U)
#define PMC_PDSLEEPCFG2_SRAM20_SHIFT             (20U)
/*! SRAM20 - RAM Partition 20 Array Power Down
 *  0b1..Powers down RAM Partition 20 array and periphery
 *  0b0..Powers on RAM Partition 20 array
 */
#define PMC_PDSLEEPCFG2_SRAM20(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM20_SHIFT)) & PMC_PDSLEEPCFG2_SRAM20_MASK)

#define PMC_PDSLEEPCFG2_SRAM21_MASK              (0x200000U)
#define PMC_PDSLEEPCFG2_SRAM21_SHIFT             (21U)
/*! SRAM21 - RAM Partition 21 Array Power Down
 *  0b1..Powers down RAM Partition 21 array and periphery
 *  0b0..Powers on RAM Partition 21 array
 */
#define PMC_PDSLEEPCFG2_SRAM21(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM21_SHIFT)) & PMC_PDSLEEPCFG2_SRAM21_MASK)

#define PMC_PDSLEEPCFG2_SRAM22_MASK              (0x400000U)
#define PMC_PDSLEEPCFG2_SRAM22_SHIFT             (22U)
/*! SRAM22 - RAM Partition 22 Array Power Down
 *  0b1..Powers down RAM Partition 22 array and periphery
 *  0b0..Powers on RAM Partition 22 array
 */
#define PMC_PDSLEEPCFG2_SRAM22(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM22_SHIFT)) & PMC_PDSLEEPCFG2_SRAM22_MASK)

#define PMC_PDSLEEPCFG2_SRAM23_MASK              (0x800000U)
#define PMC_PDSLEEPCFG2_SRAM23_SHIFT             (23U)
/*! SRAM23 - RAM Partition 23 Array Power Down
 *  0b1..Powers down RAM Partition 23 array and periphery
 *  0b0..Powers on RAM Partition 23 array
 */
#define PMC_PDSLEEPCFG2_SRAM23(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM23_SHIFT)) & PMC_PDSLEEPCFG2_SRAM23_MASK)

#define PMC_PDSLEEPCFG2_SRAM24_MASK              (0x1000000U)
#define PMC_PDSLEEPCFG2_SRAM24_SHIFT             (24U)
/*! SRAM24 - RAM Partition 24 Array Power Down
 *  0b1..Powers down RAM Partition 24 array and periphery
 *  0b0..Powers on RAM Partition 24 array
 */
#define PMC_PDSLEEPCFG2_SRAM24(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM24_SHIFT)) & PMC_PDSLEEPCFG2_SRAM24_MASK)

#define PMC_PDSLEEPCFG2_SRAM25_MASK              (0x2000000U)
#define PMC_PDSLEEPCFG2_SRAM25_SHIFT             (25U)
/*! SRAM25 - RAM Partition 25 Array Power Down
 *  0b1..Powers down RAM Partition 25 array and periphery
 *  0b0..Powers on RAM Partition 25 array
 */
#define PMC_PDSLEEPCFG2_SRAM25(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM25_SHIFT)) & PMC_PDSLEEPCFG2_SRAM25_MASK)

#define PMC_PDSLEEPCFG2_SRAM26_MASK              (0x4000000U)
#define PMC_PDSLEEPCFG2_SRAM26_SHIFT             (26U)
/*! SRAM26 - RAM Partition 26 Array Power Down
 *  0b1..Powers down RAM Partition 26 array and periphery
 *  0b0..Powers on RAM Partition 26 array
 */
#define PMC_PDSLEEPCFG2_SRAM26(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM26_SHIFT)) & PMC_PDSLEEPCFG2_SRAM26_MASK)

#define PMC_PDSLEEPCFG2_SRAM27_MASK              (0x8000000U)
#define PMC_PDSLEEPCFG2_SRAM27_SHIFT             (27U)
/*! SRAM27 - RAM Partition 27 Array Power Down
 *  0b1..Powers down RAM Partition 27 array and periphery
 *  0b0..Powers on RAM Partition 27 array
 */
#define PMC_PDSLEEPCFG2_SRAM27(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM27_SHIFT)) & PMC_PDSLEEPCFG2_SRAM27_MASK)

#define PMC_PDSLEEPCFG2_SRAM28_MASK              (0x10000000U)
#define PMC_PDSLEEPCFG2_SRAM28_SHIFT             (28U)
/*! SRAM28 - RAM Partition 28 Array Power Down
 *  0b1..Powers down RAM Partition 28 array and periphery
 *  0b0..Powers on RAM Partition 28 array
 */
#define PMC_PDSLEEPCFG2_SRAM28(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM28_SHIFT)) & PMC_PDSLEEPCFG2_SRAM28_MASK)

#define PMC_PDSLEEPCFG2_SRAM29_MASK              (0x20000000U)
#define PMC_PDSLEEPCFG2_SRAM29_SHIFT             (29U)
/*! SRAM29 - RAM Partition 29 Array Power Down
 *  0b1..Powers down RAM Partition 29 array and periphery
 *  0b0..Powers on RAM Partition 29 array
 */
#define PMC_PDSLEEPCFG2_SRAM29(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG2_SRAM29_SHIFT)) & PMC_PDSLEEPCFG2_SRAM29_MASK)
/*! @} */

/*! @name PDSLEEPCFG3 - PD Sleep Configuration 3 in Compute Domain */
/*! @{ */

#define PMC_PDSLEEPCFG3_SRAM0_MASK               (0x1U)
#define PMC_PDSLEEPCFG3_SRAM0_SHIFT              (0U)
/*! SRAM0 - RAM Partition 0 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM0(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM0_SHIFT)) & PMC_PDSLEEPCFG3_SRAM0_MASK)

#define PMC_PDSLEEPCFG3_SRAM1_MASK               (0x2U)
#define PMC_PDSLEEPCFG3_SRAM1_SHIFT              (1U)
/*! SRAM1 - RAM Partition 1 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM1(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM1_SHIFT)) & PMC_PDSLEEPCFG3_SRAM1_MASK)

#define PMC_PDSLEEPCFG3_SRAM2_MASK               (0x4U)
#define PMC_PDSLEEPCFG3_SRAM2_SHIFT              (2U)
/*! SRAM2 - RAM Partition 2 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM2(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM2_SHIFT)) & PMC_PDSLEEPCFG3_SRAM2_MASK)

#define PMC_PDSLEEPCFG3_SRAM3_MASK               (0x8U)
#define PMC_PDSLEEPCFG3_SRAM3_SHIFT              (3U)
/*! SRAM3 - RAM Partition 3 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM3(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM3_SHIFT)) & PMC_PDSLEEPCFG3_SRAM3_MASK)

#define PMC_PDSLEEPCFG3_SRAM4_MASK               (0x10U)
#define PMC_PDSLEEPCFG3_SRAM4_SHIFT              (4U)
/*! SRAM4 - RAM Partition 4 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM4(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM4_SHIFT)) & PMC_PDSLEEPCFG3_SRAM4_MASK)

#define PMC_PDSLEEPCFG3_SRAM5_MASK               (0x20U)
#define PMC_PDSLEEPCFG3_SRAM5_SHIFT              (5U)
/*! SRAM5 - RAM Partition 5 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM5(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM5_SHIFT)) & PMC_PDSLEEPCFG3_SRAM5_MASK)

#define PMC_PDSLEEPCFG3_SRAM6_MASK               (0x40U)
#define PMC_PDSLEEPCFG3_SRAM6_SHIFT              (6U)
/*! SRAM6 - RAM Partition 6 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM6(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM6_SHIFT)) & PMC_PDSLEEPCFG3_SRAM6_MASK)

#define PMC_PDSLEEPCFG3_SRAM7_MASK               (0x80U)
#define PMC_PDSLEEPCFG3_SRAM7_SHIFT              (7U)
/*! SRAM7 - RAM Partition 7 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM7(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM7_SHIFT)) & PMC_PDSLEEPCFG3_SRAM7_MASK)

#define PMC_PDSLEEPCFG3_SRAM8_MASK               (0x100U)
#define PMC_PDSLEEPCFG3_SRAM8_SHIFT              (8U)
/*! SRAM8 - RAM Partition 8 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM8(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM8_SHIFT)) & PMC_PDSLEEPCFG3_SRAM8_MASK)

#define PMC_PDSLEEPCFG3_SRAM9_MASK               (0x200U)
#define PMC_PDSLEEPCFG3_SRAM9_SHIFT              (9U)
/*! SRAM9 - RAM Partition 9 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM9(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM9_SHIFT)) & PMC_PDSLEEPCFG3_SRAM9_MASK)

#define PMC_PDSLEEPCFG3_SRAM10_MASK              (0x400U)
#define PMC_PDSLEEPCFG3_SRAM10_SHIFT             (10U)
/*! SRAM10 - RAM Partition 10 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM10(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM10_SHIFT)) & PMC_PDSLEEPCFG3_SRAM10_MASK)

#define PMC_PDSLEEPCFG3_SRAM11_MASK              (0x800U)
#define PMC_PDSLEEPCFG3_SRAM11_SHIFT             (11U)
/*! SRAM11 - RAM Partition 11 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM11(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM11_SHIFT)) & PMC_PDSLEEPCFG3_SRAM11_MASK)

#define PMC_PDSLEEPCFG3_SRAM12_MASK              (0x1000U)
#define PMC_PDSLEEPCFG3_SRAM12_SHIFT             (12U)
/*! SRAM12 - RAM Partition 12 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM12(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM12_SHIFT)) & PMC_PDSLEEPCFG3_SRAM12_MASK)

#define PMC_PDSLEEPCFG3_SRAM13_MASK              (0x2000U)
#define PMC_PDSLEEPCFG3_SRAM13_SHIFT             (13U)
/*! SRAM13 - RAM Partition 13 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM13(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM13_SHIFT)) & PMC_PDSLEEPCFG3_SRAM13_MASK)

#define PMC_PDSLEEPCFG3_SRAM14_MASK              (0x4000U)
#define PMC_PDSLEEPCFG3_SRAM14_SHIFT             (14U)
/*! SRAM14 - RAM Partition 14 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM14(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM14_SHIFT)) & PMC_PDSLEEPCFG3_SRAM14_MASK)

#define PMC_PDSLEEPCFG3_SRAM15_MASK              (0x8000U)
#define PMC_PDSLEEPCFG3_SRAM15_SHIFT             (15U)
/*! SRAM15 - RAM Partition 15 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM15(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM15_SHIFT)) & PMC_PDSLEEPCFG3_SRAM15_MASK)

#define PMC_PDSLEEPCFG3_SRAM16_MASK              (0x10000U)
#define PMC_PDSLEEPCFG3_SRAM16_SHIFT             (16U)
/*! SRAM16 - RAM Partition 16 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM16(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM16_SHIFT)) & PMC_PDSLEEPCFG3_SRAM16_MASK)

#define PMC_PDSLEEPCFG3_SRAM17_MASK              (0x20000U)
#define PMC_PDSLEEPCFG3_SRAM17_SHIFT             (17U)
/*! SRAM17 - RAM Partition 17 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM17(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM17_SHIFT)) & PMC_PDSLEEPCFG3_SRAM17_MASK)

#define PMC_PDSLEEPCFG3_SRAM18_MASK              (0x40000U)
#define PMC_PDSLEEPCFG3_SRAM18_SHIFT             (18U)
/*! SRAM18 - RAM Partition 18 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM18(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM18_SHIFT)) & PMC_PDSLEEPCFG3_SRAM18_MASK)

#define PMC_PDSLEEPCFG3_SRAM19_MASK              (0x80000U)
#define PMC_PDSLEEPCFG3_SRAM19_SHIFT             (19U)
/*! SRAM19 - RAM Partition 19 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM19(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM19_SHIFT)) & PMC_PDSLEEPCFG3_SRAM19_MASK)

#define PMC_PDSLEEPCFG3_SRAM20_MASK              (0x100000U)
#define PMC_PDSLEEPCFG3_SRAM20_SHIFT             (20U)
/*! SRAM20 - RAM Partition 20 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM20(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM20_SHIFT)) & PMC_PDSLEEPCFG3_SRAM20_MASK)

#define PMC_PDSLEEPCFG3_SRAM21_MASK              (0x200000U)
#define PMC_PDSLEEPCFG3_SRAM21_SHIFT             (21U)
/*! SRAM21 - RAM Partition 21 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM21(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM21_SHIFT)) & PMC_PDSLEEPCFG3_SRAM21_MASK)

#define PMC_PDSLEEPCFG3_SRAM22_MASK              (0x400000U)
#define PMC_PDSLEEPCFG3_SRAM22_SHIFT             (22U)
/*! SRAM22 - RAM Partition 22 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM22(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM22_SHIFT)) & PMC_PDSLEEPCFG3_SRAM22_MASK)

#define PMC_PDSLEEPCFG3_SRAM23_MASK              (0x800000U)
#define PMC_PDSLEEPCFG3_SRAM23_SHIFT             (23U)
/*! SRAM23 - RAM Partition 23 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM23(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM23_SHIFT)) & PMC_PDSLEEPCFG3_SRAM23_MASK)

#define PMC_PDSLEEPCFG3_SRAM24_MASK              (0x1000000U)
#define PMC_PDSLEEPCFG3_SRAM24_SHIFT             (24U)
/*! SRAM24 - RAM Partition 24 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM24(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM24_SHIFT)) & PMC_PDSLEEPCFG3_SRAM24_MASK)

#define PMC_PDSLEEPCFG3_SRAM25_MASK              (0x2000000U)
#define PMC_PDSLEEPCFG3_SRAM25_SHIFT             (25U)
/*! SRAM25 - RAM Partition 25 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM25(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM25_SHIFT)) & PMC_PDSLEEPCFG3_SRAM25_MASK)

#define PMC_PDSLEEPCFG3_SRAM26_MASK              (0x4000000U)
#define PMC_PDSLEEPCFG3_SRAM26_SHIFT             (26U)
/*! SRAM26 - RAM Partition 26 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM26(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM26_SHIFT)) & PMC_PDSLEEPCFG3_SRAM26_MASK)

#define PMC_PDSLEEPCFG3_SRAM27_MASK              (0x8000000U)
#define PMC_PDSLEEPCFG3_SRAM27_SHIFT             (27U)
/*! SRAM27 - RAM Partition 27 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM27(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM27_SHIFT)) & PMC_PDSLEEPCFG3_SRAM27_MASK)

#define PMC_PDSLEEPCFG3_SRAM28_MASK              (0x10000000U)
#define PMC_PDSLEEPCFG3_SRAM28_SHIFT             (28U)
/*! SRAM28 - RAM Partition 28 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM28(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM28_SHIFT)) & PMC_PDSLEEPCFG3_SRAM28_MASK)

#define PMC_PDSLEEPCFG3_SRAM29_MASK              (0x20000000U)
#define PMC_PDSLEEPCFG3_SRAM29_SHIFT             (29U)
/*! SRAM29 - RAM Partition 29 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG3_SRAM29(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG3_SRAM29_SHIFT)) & PMC_PDSLEEPCFG3_SRAM29_MASK)
/*! @} */

/*! @name PDSLEEPCFG4 - PD Sleep Configuration 4 in Compute Domain */
/*! @{ */

#define PMC_PDSLEEPCFG4_SDHC0_SRAM_MASK          (0x1U)
#define PMC_PDSLEEPCFG4_SDHC0_SRAM_SHIFT         (0U)
/*! SDHC0_SRAM - uSDHC0 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_SDHC0_SRAM(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_SDHC0_SRAM_SHIFT)) & PMC_PDSLEEPCFG4_SDHC0_SRAM_MASK)

#define PMC_PDSLEEPCFG4_SDHC1_SRAM_MASK          (0x2U)
#define PMC_PDSLEEPCFG4_SDHC1_SRAM_SHIFT         (1U)
/*! SDHC1_SRAM - uSDHC1 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_SDHC1_SRAM(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_SDHC1_SRAM_SHIFT)) & PMC_PDSLEEPCFG4_SDHC1_SRAM_MASK)

#define PMC_PDSLEEPCFG4_USB0_SRAM_MASK           (0x4U)
#define PMC_PDSLEEPCFG4_USB0_SRAM_SHIFT          (2U)
/*! USB0_SRAM - USB0 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_USB0_SRAM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_USB0_SRAM_SHIFT)) & PMC_PDSLEEPCFG4_USB0_SRAM_MASK)

#define PMC_PDSLEEPCFG4_USB1_SRAM_MASK           (0x8U)
#define PMC_PDSLEEPCFG4_USB1_SRAM_SHIFT          (3U)
/*! USB1_SRAM - USB1 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_USB1_SRAM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_USB1_SRAM_SHIFT)) & PMC_PDSLEEPCFG4_USB1_SRAM_MASK)

#define PMC_PDSLEEPCFG4_JPEG_MASK                (0x10U)
#define PMC_PDSLEEPCFG4_JPEG_SHIFT               (4U)
/*! JPEG - JPEGDEC
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_JPEG(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_JPEG_SHIFT)) & PMC_PDSLEEPCFG4_JPEG_MASK)

#define PMC_PDSLEEPCFG4_PNG_MASK                 (0x20U)
#define PMC_PDSLEEPCFG4_PNG_SHIFT                (5U)
/*! PNG - PNGDEC
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_PNG(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_PNG_SHIFT)) & PMC_PDSLEEPCFG4_PNG_MASK)

#define PMC_PDSLEEPCFG4_MIPI_MASK                (0x40U)
#define PMC_PDSLEEPCFG4_MIPI_SHIFT               (6U)
/*! MIPI - MIPI PHY
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_MIPI(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_MIPI_SHIFT)) & PMC_PDSLEEPCFG4_MIPI_MASK)

#define PMC_PDSLEEPCFG4_GPU_MASK                 (0x80U)
#define PMC_PDSLEEPCFG4_GPU_SHIFT                (7U)
/*! GPU - VGPU
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_GPU(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)

#define PMC_PDSLEEPCFG4_DMA2_3_MASK              (0x100U)
#define PMC_PDSLEEPCFG4_DMA2_3_SHIFT             (8U)
/*! DMA2_3 - DMA2 and DMA3
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_DMA2_3(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_DMA2_3_SHIFT)) & PMC_PDSLEEPCFG4_DMA2_3_MASK)

#define PMC_PDSLEEPCFG4_DMA0_1_P_E_MASK          (0x200U)
#define PMC_PDSLEEPCFG4_DMA0_1_P_E_SHIFT         (9U)
/*! DMA0_1_P_E - DMA0-1, PKC, and ETF
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_DMA0_1_P_E(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_DMA0_1_P_E_SHIFT)) & PMC_PDSLEEPCFG4_DMA0_1_P_E_MASK)

#define PMC_PDSLEEPCFG4_CPU0_CCACHE_MASK         (0x400U)
#define PMC_PDSLEEPCFG4_CPU0_CCACHE_SHIFT        (10U)
/*! CPU0_CCACHE - CPU0 Code Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_CPU0_CCACHE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_CPU0_CCACHE_SHIFT)) & PMC_PDSLEEPCFG4_CPU0_CCACHE_MASK)

#define PMC_PDSLEEPCFG4_CPU0_SCACHE_MASK         (0x800U)
#define PMC_PDSLEEPCFG4_CPU0_SCACHE_SHIFT        (11U)
/*! CPU0_SCACHE - CPU0 System Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_CPU0_SCACHE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_CPU0_SCACHE_SHIFT)) & PMC_PDSLEEPCFG4_CPU0_SCACHE_MASK)

#define PMC_PDSLEEPCFG4_DSP_ICACHE_MASK          (0x1000U)
#define PMC_PDSLEEPCFG4_DSP_ICACHE_SHIFT         (12U)
/*! DSP_ICACHE - HiFi4 Instruction Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_DSP_ICACHE(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_DSP_ICACHE_SHIFT)) & PMC_PDSLEEPCFG4_DSP_ICACHE_MASK)

#define PMC_PDSLEEPCFG4_DSP_DCACHE_MASK          (0x2000U)
#define PMC_PDSLEEPCFG4_DSP_DCACHE_SHIFT         (13U)
/*! DSP_DCACHE - HiFi4 Data Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_DSP_DCACHE(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_DSP_DCACHE_SHIFT)) & PMC_PDSLEEPCFG4_DSP_DCACHE_MASK)

#define PMC_PDSLEEPCFG4_DSP_ITCM_MASK            (0x4000U)
#define PMC_PDSLEEPCFG4_DSP_ITCM_SHIFT           (14U)
/*! DSP_ITCM - HiFi4 Instruction TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_DSP_ITCM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_DSP_ITCM_SHIFT)) & PMC_PDSLEEPCFG4_DSP_ITCM_MASK)

#define PMC_PDSLEEPCFG4_DSP_DTCM_MASK            (0x8000U)
#define PMC_PDSLEEPCFG4_DSP_DTCM_SHIFT           (15U)
/*! DSP_DTCM - HiFi4 Data TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_DSP_DTCM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_DSP_DTCM_SHIFT)) & PMC_PDSLEEPCFG4_DSP_DTCM_MASK)

#define PMC_PDSLEEPCFG4_EZH_TCM_MASK             (0x10000U)
#define PMC_PDSLEEPCFG4_EZH_TCM_SHIFT            (16U)
/*! EZH_TCM - EZH-V TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_EZH_TCM(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_EZH_TCM_SHIFT)) & PMC_PDSLEEPCFG4_EZH_TCM_MASK)

#define PMC_PDSLEEPCFG4_NPU_MASK                 (0x20000U)
#define PMC_PDSLEEPCFG4_NPU_SHIFT                (17U)
/*! NPU - NPU
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_NPU(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_NPU_SHIFT)) & PMC_PDSLEEPCFG4_NPU_MASK)

#define PMC_PDSLEEPCFG4_XSPI0_MASK               (0x40000U)
#define PMC_PDSLEEPCFG4_XSPI0_SHIFT              (18U)
/*! XSPI0 - XSPI0, MMU0, and Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_XSPI0(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_XSPI0_SHIFT)) & PMC_PDSLEEPCFG4_XSPI0_MASK)

#define PMC_PDSLEEPCFG4_XSPI1_MASK               (0x80000U)
#define PMC_PDSLEEPCFG4_XSPI1_SHIFT              (19U)
/*! XSPI1 - XSPI1, MMU1, and Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_XSPI1(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_XSPI1_SHIFT)) & PMC_PDSLEEPCFG4_XSPI1_MASK)

#define PMC_PDSLEEPCFG4_XSPI2_MASK               (0x100000U)
#define PMC_PDSLEEPCFG4_XSPI2_SHIFT              (20U)
/*! XSPI2 - XSPI2 and MMU2
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG4_XSPI2(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_XSPI2_SHIFT)) & PMC_PDSLEEPCFG4_XSPI2_MASK)

#define PMC_PDSLEEPCFG4_LCD_MASK                 (0x200000U)
#define PMC_PDSLEEPCFG4_LCD_SHIFT                (21U)
/*! LCD - LCDIF
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG4_LCD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_LCD_SHIFT)) & PMC_PDSLEEPCFG4_LCD_MASK)

#define PMC_PDSLEEPCFG4_OCOTP_MASK               (0x400000U)
#define PMC_PDSLEEPCFG4_OCOTP_SHIFT              (22U)
/*! OCOTP - OCOTP Shadow SRAM
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG4_OCOTP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_OCOTP_SHIFT)) & PMC_PDSLEEPCFG4_OCOTP_MASK)
/*! @} */

/*! @name PDSLEEPCFG5 - PD Sleep Configuration 5 in Compute Domain */
/*! @{ */

#define PMC_PDSLEEPCFG5_SDHC0_SRAM_MASK          (0x1U)
#define PMC_PDSLEEPCFG5_SDHC0_SRAM_SHIFT         (0U)
/*! SDHC0_SRAM - uSDHC0 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_SDHC0_SRAM(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_SDHC0_SRAM_SHIFT)) & PMC_PDSLEEPCFG5_SDHC0_SRAM_MASK)

#define PMC_PDSLEEPCFG5_SDHC1_SRAM_MASK          (0x2U)
#define PMC_PDSLEEPCFG5_SDHC1_SRAM_SHIFT         (1U)
/*! SDHC1_SRAM - uSDHC1 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_SDHC1_SRAM(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_SDHC1_SRAM_SHIFT)) & PMC_PDSLEEPCFG5_SDHC1_SRAM_MASK)

#define PMC_PDSLEEPCFG5_USB0_SRAM_MASK           (0x4U)
#define PMC_PDSLEEPCFG5_USB0_SRAM_SHIFT          (2U)
/*! USB0_SRAM - USB0 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_USB0_SRAM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_USB0_SRAM_SHIFT)) & PMC_PDSLEEPCFG5_USB0_SRAM_MASK)

#define PMC_PDSLEEPCFG5_USB1_SRAM_MASK           (0x8U)
#define PMC_PDSLEEPCFG5_USB1_SRAM_SHIFT          (3U)
/*! USB1_SRAM - USB1 SRAM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_USB1_SRAM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_USB1_SRAM_SHIFT)) & PMC_PDSLEEPCFG5_USB1_SRAM_MASK)

#define PMC_PDSLEEPCFG5_JPEG_MASK                (0x10U)
#define PMC_PDSLEEPCFG5_JPEG_SHIFT               (4U)
/*! JPEG - JPEGDEC
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_JPEG(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_JPEG_SHIFT)) & PMC_PDSLEEPCFG5_JPEG_MASK)

#define PMC_PDSLEEPCFG5_PNG_MASK                 (0x20U)
#define PMC_PDSLEEPCFG5_PNG_SHIFT                (5U)
/*! PNG - PNGDEC
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_PNG(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_PNG_SHIFT)) & PMC_PDSLEEPCFG5_PNG_MASK)

#define PMC_PDSLEEPCFG5_MIPI_MASK                (0x40U)
#define PMC_PDSLEEPCFG5_MIPI_SHIFT               (6U)
/*! MIPI - MIPI PHY
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_MIPI(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_MIPI_SHIFT)) & PMC_PDSLEEPCFG5_MIPI_MASK)

#define PMC_PDSLEEPCFG5_GPU_MASK                 (0x80U)
#define PMC_PDSLEEPCFG5_GPU_SHIFT                (7U)
/*! GPU - VGPU
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_GPU(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_GPU_SHIFT)) & PMC_PDSLEEPCFG5_GPU_MASK)

#define PMC_PDSLEEPCFG5_DMA2_3_MASK              (0x100U)
#define PMC_PDSLEEPCFG5_DMA2_3_SHIFT             (8U)
/*! DMA2_3 - DMA2 and DMA3
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_DMA2_3(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_DMA2_3_SHIFT)) & PMC_PDSLEEPCFG5_DMA2_3_MASK)

#define PMC_PDSLEEPCFG5_DMA0_1_P_E_MASK          (0x200U)
#define PMC_PDSLEEPCFG5_DMA0_1_P_E_SHIFT         (9U)
/*! DMA0_1_P_E - DMA0-1, PKC, and ETF
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_DMA0_1_P_E(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_DMA0_1_P_E_SHIFT)) & PMC_PDSLEEPCFG5_DMA0_1_P_E_MASK)

#define PMC_PDSLEEPCFG5_CPU0_CCACHE_MASK         (0x400U)
#define PMC_PDSLEEPCFG5_CPU0_CCACHE_SHIFT        (10U)
/*! CPU0_CCACHE - CPU0 Code Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_CPU0_CCACHE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_CPU0_CCACHE_SHIFT)) & PMC_PDSLEEPCFG5_CPU0_CCACHE_MASK)

#define PMC_PDSLEEPCFG5_CPU0_SCACHE_MASK         (0x800U)
#define PMC_PDSLEEPCFG5_CPU0_SCACHE_SHIFT        (11U)
/*! CPU0_SCACHE - CPU0 System Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_CPU0_SCACHE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_CPU0_SCACHE_SHIFT)) & PMC_PDSLEEPCFG5_CPU0_SCACHE_MASK)

#define PMC_PDSLEEPCFG5_DSP_ICACHE_MASK          (0x1000U)
#define PMC_PDSLEEPCFG5_DSP_ICACHE_SHIFT         (12U)
/*! DSP_ICACHE - HiFi4 Instruction Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_DSP_ICACHE(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_DSP_ICACHE_SHIFT)) & PMC_PDSLEEPCFG5_DSP_ICACHE_MASK)

#define PMC_PDSLEEPCFG5_DSP_DCACHE_MASK          (0x2000U)
#define PMC_PDSLEEPCFG5_DSP_DCACHE_SHIFT         (13U)
/*! DSP_DCACHE - HiFi4 Data Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_DSP_DCACHE(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_DSP_DCACHE_SHIFT)) & PMC_PDSLEEPCFG5_DSP_DCACHE_MASK)

#define PMC_PDSLEEPCFG5_DSP_ITCM_MASK            (0x4000U)
#define PMC_PDSLEEPCFG5_DSP_ITCM_SHIFT           (14U)
/*! DSP_ITCM - HiFi4 Instruction TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_DSP_ITCM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_DSP_ITCM_SHIFT)) & PMC_PDSLEEPCFG5_DSP_ITCM_MASK)

#define PMC_PDSLEEPCFG5_DSP_DTCM_MASK            (0x8000U)
#define PMC_PDSLEEPCFG5_DSP_DTCM_SHIFT           (15U)
/*! DSP_DTCM - HiFi4 Data TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_DSP_DTCM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_DSP_DTCM_SHIFT)) & PMC_PDSLEEPCFG5_DSP_DTCM_MASK)

#define PMC_PDSLEEPCFG5_EZH_TCM_MASK             (0x10000U)
#define PMC_PDSLEEPCFG5_EZH_TCM_SHIFT            (16U)
/*! EZH_TCM - EZH-V TCM
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_EZH_TCM(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_EZH_TCM_SHIFT)) & PMC_PDSLEEPCFG5_EZH_TCM_MASK)

#define PMC_PDSLEEPCFG5_NPU_MASK                 (0x20000U)
#define PMC_PDSLEEPCFG5_NPU_SHIFT                (17U)
/*! NPU - NPU
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_NPU(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_NPU_SHIFT)) & PMC_PDSLEEPCFG5_NPU_MASK)

#define PMC_PDSLEEPCFG5_XSPI0_MASK               (0x40000U)
#define PMC_PDSLEEPCFG5_XSPI0_SHIFT              (18U)
/*! XSPI0 - XSPI0, MMU0, and Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_XSPI0(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_XSPI0_SHIFT)) & PMC_PDSLEEPCFG5_XSPI0_MASK)

#define PMC_PDSLEEPCFG5_XSPI1_MASK               (0x80000U)
#define PMC_PDSLEEPCFG5_XSPI1_SHIFT              (19U)
/*! XSPI1 - XSPI1, MMU1, and Cache
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_XSPI1(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_XSPI1_SHIFT)) & PMC_PDSLEEPCFG5_XSPI1_MASK)

#define PMC_PDSLEEPCFG5_XSPI2_MASK               (0x100000U)
#define PMC_PDSLEEPCFG5_XSPI2_SHIFT              (20U)
/*! XSPI2 - XSPI2 and MMU2
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDSLEEPCFG5_XSPI2(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_XSPI2_SHIFT)) & PMC_PDSLEEPCFG5_XSPI2_MASK)

#define PMC_PDSLEEPCFG5_LCD_MASK                 (0x200000U)
#define PMC_PDSLEEPCFG5_LCD_SHIFT                (21U)
/*! LCD - LCDIF
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG5_LCD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_LCD_SHIFT)) & PMC_PDSLEEPCFG5_LCD_MASK)

#define PMC_PDSLEEPCFG5_OCOTP_MASK               (0x400000U)
#define PMC_PDSLEEPCFG5_OCOTP_SHIFT              (22U)
/*! OCOTP - OCOTP Shadow SRAM
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDSLEEPCFG5_OCOTP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG5_OCOTP_SHIFT)) & PMC_PDSLEEPCFG5_OCOTP_MASK)
/*! @} */

/*! @name PDCFGSTATUS0 - PD Configuration Status 0 */
/*! @{ */

#define PMC_PDCFGSTATUS0_PMICMODE_MASK           (0x3U)
#define PMC_PDCFGSTATUS0_PMICMODE_SHIFT          (0U)
/*! PMICMODE - PMIC_MODE Output Value
 *  0b00..PMIC_MODE[1:0] pins = 00
 *  0b01..PMIC_MODE[1:0] pins = 01
 *  0b10..PMIC_MODE[1:0] pins = 10
 *  0b11..PMIC_MODE[1:0] pins = 11
 */
#define PMC_PDCFGSTATUS0_PMICMODE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_PMICMODE_SHIFT)) & PMC_PDCFGSTATUS0_PMICMODE_MASK)

#define PMC_PDCFGSTATUS0_FDSR_MASK               (0x4U)
#define PMC_PDCFGSTATUS0_FDSR_SHIFT              (2U)
/*! FDSR - FDSR Mode
 *  0b1..All core domains are in FDSR mode or power down
 *  0b0..Power switches and DSR status are determined by the single power domain controls
 */
#define PMC_PDCFGSTATUS0_FDSR(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_FDSR_SHIFT)) & PMC_PDCFGSTATUS0_FDSR_MASK)

#define PMC_PDCFGSTATUS0_DPD_MASK                (0x8U)
#define PMC_PDCFGSTATUS0_DPD_SHIFT               (3U)
/*! DPD - DPD Mode
 *  0b1..Activates isolation and correct sequencing for DPD mode
 *  0b0..Enables
 */
#define PMC_PDCFGSTATUS0_DPD(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_DPD_SHIFT)) & PMC_PDCFGSTATUS0_DPD_MASK)

#define PMC_PDCFGSTATUS0_FDPD_MASK               (0x10U)
#define PMC_PDCFGSTATUS0_FDPD_SHIFT              (4U)
/*! FDPD - FDPD Mode
 *  0b1..Activates isolation and correct sequencing for FDPD mode
 *  0b0..Enables
 */
#define PMC_PDCFGSTATUS0_FDPD(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_FDPD_SHIFT)) & PMC_PDCFGSTATUS0_FDPD_MASK)

#define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK         (0x20U)
#define PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT        (5U)
/*! V2COMP_DSR - DSR of VDD2_COMP Domain
 *  0b1..DSR mode
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_V2COMP_DSR(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)

#define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK         (0x40U)
#define PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT        (6U)
/*! V2NMED_DSR - DSR of VDD2_MEDIA and VDDN_MEDIA Domains
 *  0b1..DSR mode
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_V2NMED_DSR(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)

#define PMC_PDCFGSTATUS0_V2COM_DSR_MASK          (0x80U)
#define PMC_PDCFGSTATUS0_V2COM_DSR_SHIFT         (7U)
/*! V2COM_DSR - DSR of VDD2_COM Domain
 *  0b1..DSR mode
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_V2COM_DSR(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COM_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COM_DSR_MASK)

#define PMC_PDCFGSTATUS0_VNCOM_DSR_MASK          (0x100U)
#define PMC_PDCFGSTATUS0_VNCOM_DSR_SHIFT         (8U)
/*! VNCOM_DSR - DSR of VDDN_COM Domain
 *  0b1..DSR mode
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_VNCOM_DSR(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_VNCOM_DSR_SHIFT)) & PMC_PDCFGSTATUS0_VNCOM_DSR_MASK)

#define PMC_PDCFGSTATUS0_V2DSP_PD_MASK           (0x200U)
#define PMC_PDCFGSTATUS0_V2DSP_PD_SHIFT          (9U)
/*! V2DSP_PD - HiFi4 Power Down
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS0_V2DSP_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2DSP_PD_SHIFT)) & PMC_PDCFGSTATUS0_V2DSP_PD_MASK)

#define PMC_PDCFGSTATUS0_V2MIPI_PD_MASK          (0x400U)
#define PMC_PDCFGSTATUS0_V2MIPI_PD_SHIFT         (10U)
/*! V2MIPI_PD - MIPI PHY Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_V2MIPI_PD(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2MIPI_PD_SHIFT)) & PMC_PDCFGSTATUS0_V2MIPI_PD_MASK)

#define PMC_PDCFGSTATUS0_DCDC_LP_MASK            (0x1000U)
#define PMC_PDCFGSTATUS0_DCDC_LP_SHIFT           (12U)
/*! DCDC_LP - DCDC Low Power
 *  0b1..DCDC in low-power mode
 *  0b0..DCDC in high-power mode
 */
#define PMC_PDCFGSTATUS0_DCDC_LP(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_DCDC_LP_SHIFT)) & PMC_PDCFGSTATUS0_DCDC_LP_MASK)

#define PMC_PDCFGSTATUS0_DCDC_VSEL_MASK          (0x2000U)
#define PMC_PDCFGSTATUS0_DCDC_VSEL_SHIFT         (13U)
/*! DCDC_VSEL - DCDC Voltage Selection
 *  0b1..[VSEL1] level selected
 *  0b0..[VSEL0] level selected
 */
#define PMC_PDCFGSTATUS0_DCDC_VSEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_DCDC_VSEL_SHIFT)) & PMC_PDCFGSTATUS0_DCDC_VSEL_MASK)

#define PMC_PDCFGSTATUS0_LDO1_MODE_MASK          (0xC000U)
#define PMC_PDCFGSTATUS0_LDO1_MODE_SHIFT         (14U)
/*! LDO1_MODE - LDO VDD1 Regulator Mode
 *  0b10, 0b11..LDO VDD1 is in low-power mode
 *  0b01..LDO VDD1 is in high-power mode
 *  0b00..LDO VDD1 is in bypass mode
 */
#define PMC_PDCFGSTATUS0_LDO1_MODE(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_LDO1_MODE_SHIFT)) & PMC_PDCFGSTATUS0_LDO1_MODE_MASK)

#define PMC_PDCFGSTATUS0_LDO1_VSEL_MASK          (0x30000U)
#define PMC_PDCFGSTATUS0_LDO1_VSEL_SHIFT         (16U)
/*! LDO1_VSEL - LDO VDD1 Voltage Selection
 *  0b00..LDOVDD1VSEL[VSEL0] and LVDVDD1CTRL[LVL0] level selected (lowest voltage)
 *  0b01..LDOVDD1VSEL[VSEL1] and LVDVDD1CTRL[LVL1] level selected
 *  0b10..LDOVDD1VSEL[VSEL2] and LVDVDD1CTRL[LVL2] level selected
 *  0b11..LDOVDD1VSEL[VSEL3] and LVDVDD1CTRL[LVL3] level selected (highest voltage)
 */
#define PMC_PDCFGSTATUS0_LDO1_VSEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_LDO1_VSEL_SHIFT)) & PMC_PDCFGSTATUS0_LDO1_VSEL_MASK)

#define PMC_PDCFGSTATUS0_LDO2_MODE_MASK          (0xC0000U)
#define PMC_PDCFGSTATUS0_LDO2_MODE_SHIFT         (18U)
/*! LDO2_MODE - LDO VDD2 Regulator Mode
 *  0b10, 0b11..LDO VDD2 is in low-power mode
 *  0b01..LDO VDD2 is in high-power mode
 *  0b00..LDO VDD1 is in bypass mode
 */
#define PMC_PDCFGSTATUS0_LDO2_MODE(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_LDO2_MODE_SHIFT)) & PMC_PDCFGSTATUS0_LDO2_MODE_MASK)

#define PMC_PDCFGSTATUS0_LDO2_VSEL_MASK          (0x300000U)
#define PMC_PDCFGSTATUS0_LDO2_VSEL_SHIFT         (20U)
/*! LDO2_VSEL - LDO VDD2 Voltage Selection
 *  0b00..LDOVDD2VSEL[VSEL0] and LVDVDD2CTRL[LVL0] level selected (lowest voltage)
 *  0b01..LDOVDD2VSEL[VSEL1] and LVDVDD2CTRL[LVL1] level selected
 *  0b10..LDOVDD2VSEL[VSEL2] and LVDVDD2CTRL[LVL2] level selected
 *  0b11..LDOVDD2VSEL[VSEL3] and LVDVDD2CTRL[LVL3] level selected (highest voltage)
 */
#define PMC_PDCFGSTATUS0_LDO2_VSEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_LDO2_VSEL_SHIFT)) & PMC_PDCFGSTATUS0_LDO2_VSEL_MASK)

#define PMC_PDCFGSTATUS0_RBB1_PD_MASK            (0x400000U)
#define PMC_PDCFGSTATUS0_RBB1_PD_SHIFT           (22U)
/*! RBB1_PD - Power Down RBB in VDD1 domain
 *  0b0..Enables RBB if the aggregated value of [AFBB1_PD] = 1, otherwise RBB is disabled
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS0_RBB1_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_RBB1_PD_SHIFT)) & PMC_PDCFGSTATUS0_RBB1_PD_MASK)

#define PMC_PDCFGSTATUS0_AFBB1_PD_MASK           (0x800000U)
#define PMC_PDCFGSTATUS0_AFBB1_PD_SHIFT          (23U)
/*! AFBB1_PD - AFBB Power Down in VDD1 domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_AFBB1_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_AFBB1_PD_SHIFT)) & PMC_PDCFGSTATUS0_AFBB1_PD_MASK)

#define PMC_PDCFGSTATUS0_RBB2_PD_MASK            (0x1000000U)
#define PMC_PDCFGSTATUS0_RBB2_PD_SHIFT           (24U)
/*! RBB2_PD - RBB Power Down in VDD2 domain
 *  0b1..Power down
 *  0b0..Enables RBB if the aggregated value of [AFBB2_PD] = 1, otherwise RBB is disabled
 */
#define PMC_PDCFGSTATUS0_RBB2_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_RBB2_PD_SHIFT)) & PMC_PDCFGSTATUS0_RBB2_PD_MASK)

#define PMC_PDCFGSTATUS0_AFBB2_PD_MASK           (0x2000000U)
#define PMC_PDCFGSTATUS0_AFBB2_PD_SHIFT          (25U)
/*! AFBB2_PD - AFBB Power Down in VDD2 domain
 *  0b0..Power
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS0_AFBB2_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_AFBB2_PD_SHIFT)) & PMC_PDCFGSTATUS0_AFBB2_PD_MASK)

#define PMC_PDCFGSTATUS0_RBBN_PD_MASK            (0x4000000U)
#define PMC_PDCFGSTATUS0_RBBN_PD_SHIFT           (26U)
/*! RBBN_PD - RBB Power Down in VDDN domain
 *  0b0..Enables RBB if the aggregated value of [AFBBN_PD] = 1, otherwise RBB is disabled
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS0_RBBN_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_RBBN_PD_SHIFT)) & PMC_PDCFGSTATUS0_RBBN_PD_MASK)

#define PMC_PDCFGSTATUS0_AFBBN_PD_MASK           (0x8000000U)
#define PMC_PDCFGSTATUS0_AFBBN_PD_SHIFT          (27U)
/*! AFBBN_PD - AFBB Power Down in VDDN domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_AFBBN_PD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_AFBBN_PD_SHIFT)) & PMC_PDCFGSTATUS0_AFBBN_PD_MASK)

#define PMC_PDCFGSTATUS0_RBBSR1_PD_MASK          (0x10000000U)
#define PMC_PDCFGSTATUS0_RBBSR1_PD_SHIFT         (28U)
/*! RBBSR1_PD - Power Down SRAM RBB in VDD1 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS0_RBBSR1_PD(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_RBBSR1_PD_SHIFT)) & PMC_PDCFGSTATUS0_RBBSR1_PD_MASK)

#define PMC_PDCFGSTATUS0_RBBSR2_PD_MASK          (0x20000000U)
#define PMC_PDCFGSTATUS0_RBBSR2_PD_SHIFT         (29U)
/*! RBBSR2_PD - SRAM RBB Power Down in VDD2 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_RBBSR2_PD(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_RBBSR2_PD_SHIFT)) & PMC_PDCFGSTATUS0_RBBSR2_PD_MASK)

#define PMC_PDCFGSTATUS0_AFBBSR1_PD_MASK         (0x40000000U)
#define PMC_PDCFGSTATUS0_AFBBSR1_PD_SHIFT        (30U)
/*! AFBBSR1_PD - SRAM AFBB Power Down in VDD1 Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS0_AFBBSR1_PD(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_AFBBSR1_PD_SHIFT)) & PMC_PDCFGSTATUS0_AFBBSR1_PD_MASK)

#define PMC_PDCFGSTATUS0_AFBBSR2_PD_MASK         (0x80000000U)
#define PMC_PDCFGSTATUS0_AFBBSR2_PD_SHIFT        (31U)
/*! AFBBSR2_PD - SRAM AFBB Power Down in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS0_AFBBSR2_PD(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_AFBBSR2_PD_SHIFT)) & PMC_PDCFGSTATUS0_AFBBSR2_PD_MASK)
/*! @} */

/*! @name PDCFGSTATUS1 - PD Configuration Status 1 */
/*! @{ */

#define PMC_PDCFGSTATUS1_TEMP_PD_MASK            (0x1U)
#define PMC_PDCFGSTATUS1_TEMP_PD_SHIFT           (0U)
/*! TEMP_PD - PMC Temperature Sensor Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS1_TEMP_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_TEMP_PD_SHIFT)) & PMC_PDCFGSTATUS1_TEMP_PD_MASK)

#define PMC_PDCFGSTATUS1_PMCREF_LP_MASK          (0x2U)
#define PMC_PDCFGSTATUS1_PMCREF_LP_SHIFT         (1U)
/*! PMCREF_LP - PMC References Low Power
 *  0b1..Low-power mode
 *  0b0..High-power mode
 */
#define PMC_PDCFGSTATUS1_PMCREF_LP(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_PMCREF_LP_SHIFT)) & PMC_PDCFGSTATUS1_PMCREF_LP_MASK)

#define PMC_PDCFGSTATUS1_HVD1V8_PD_MASK          (0x4U)
#define PMC_PDCFGSTATUS1_HVD1V8_PD_SHIFT         (2U)
/*! HVD1V8_PD - HVD Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS1_HVD1V8_PD(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_HVD1V8_PD_SHIFT)) & PMC_PDCFGSTATUS1_HVD1V8_PD_MASK)

#define PMC_PDCFGSTATUS1_POR1_LP_MASK            (0x8U)
#define PMC_PDCFGSTATUS1_POR1_LP_SHIFT           (3U)
/*! POR1_LP - POR Low Power in VDD1 Domain
 *  0b0..High power
 *  0b1..Low power
 */
#define PMC_PDCFGSTATUS1_POR1_LP(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_POR1_LP_SHIFT)) & PMC_PDCFGSTATUS1_POR1_LP_MASK)

#define PMC_PDCFGSTATUS1_LVD1_LP_MASK            (0x10U)
#define PMC_PDCFGSTATUS1_LVD1_LP_SHIFT           (4U)
/*! LVD1_LP - LVD Low Power in VDD1 Domain
 *  0b1..Low power
 *  0b0..High power
 */
#define PMC_PDCFGSTATUS1_LVD1_LP(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_LVD1_LP_SHIFT)) & PMC_PDCFGSTATUS1_LVD1_LP_MASK)

#define PMC_PDCFGSTATUS1_HVD1_PD_MASK            (0x20U)
#define PMC_PDCFGSTATUS1_HVD1_PD_SHIFT           (5U)
/*! HVD1_PD - HVD Power Down in VDD1 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS1_HVD1_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_HVD1_PD_SHIFT)) & PMC_PDCFGSTATUS1_HVD1_PD_MASK)

#define PMC_PDCFGSTATUS1_AGDET1_PD_MASK          (0x40U)
#define PMC_PDCFGSTATUS1_AGDET1_PD_SHIFT         (6U)
/*! AGDET1_PD - AGDET Power Down in VDD1 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS1_AGDET1_PD(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_AGDET1_PD_SHIFT)) & PMC_PDCFGSTATUS1_AGDET1_PD_MASK)

#define PMC_PDCFGSTATUS1_POR2_LP_MASK            (0x80U)
#define PMC_PDCFGSTATUS1_POR2_LP_SHIFT           (7U)
/*! POR2_LP - POR Low Power in VDD2 Domain
 *  0b0..High power
 *  0b1..Low power
 */
#define PMC_PDCFGSTATUS1_POR2_LP(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_POR2_LP_SHIFT)) & PMC_PDCFGSTATUS1_POR2_LP_MASK)

#define PMC_PDCFGSTATUS1_LVD2_LP_MASK            (0x100U)
#define PMC_PDCFGSTATUS1_LVD2_LP_SHIFT           (8U)
/*! LVD2_LP - LVD Low Power in VDD2 Domain
 *  0b1..Low power
 *  0b0..High power
 */
#define PMC_PDCFGSTATUS1_LVD2_LP(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_LVD2_LP_SHIFT)) & PMC_PDCFGSTATUS1_LVD2_LP_MASK)

#define PMC_PDCFGSTATUS1_HVD2_PD_MASK            (0x200U)
#define PMC_PDCFGSTATUS1_HVD2_PD_SHIFT           (9U)
/*! HVD2_PD - HVD Power Down in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS1_HVD2_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_HVD2_PD_SHIFT)) & PMC_PDCFGSTATUS1_HVD2_PD_MASK)

#define PMC_PDCFGSTATUS1_AGDET2_PD_MASK          (0x400U)
#define PMC_PDCFGSTATUS1_AGDET2_PD_SHIFT         (10U)
/*! AGDET2_PD - AGDET Power Down in VDD2 Domain
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS1_AGDET2_PD(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_AGDET2_PD_SHIFT)) & PMC_PDCFGSTATUS1_AGDET2_PD_MASK)

#define PMC_PDCFGSTATUS1_PORN_LP_MASK            (0x800U)
#define PMC_PDCFGSTATUS1_PORN_LP_SHIFT           (11U)
/*! PORN_LP - POR Low Power in VDDN Domain
 *  0b0..High power
 *  0b1..Low power
 */
#define PMC_PDCFGSTATUS1_PORN_LP(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_PORN_LP_SHIFT)) & PMC_PDCFGSTATUS1_PORN_LP_MASK)

#define PMC_PDCFGSTATUS1_LVDN_LP_MASK            (0x1000U)
#define PMC_PDCFGSTATUS1_LVDN_LP_SHIFT           (12U)
/*! LVDN_LP - LVD Low Power in VDDN Domain
 *  0b0..High power
 *  0b1..Low power
 */
#define PMC_PDCFGSTATUS1_LVDN_LP(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_LVDN_LP_SHIFT)) & PMC_PDCFGSTATUS1_LVDN_LP_MASK)

#define PMC_PDCFGSTATUS1_HVDN_PD_MASK            (0x2000U)
#define PMC_PDCFGSTATUS1_HVDN_PD_SHIFT           (13U)
/*! HVDN_PD - HVD Power Down in VDDN Domain
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS1_HVDN_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_HVDN_PD_SHIFT)) & PMC_PDCFGSTATUS1_HVDN_PD_MASK)

#define PMC_PDCFGSTATUS1_OTP_PD_MASK             (0x8000U)
#define PMC_PDCFGSTATUS1_OTP_PD_SHIFT            (15U)
/*! OTP_PD - OTP Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS1_OTP_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_OTP_PD_SHIFT)) & PMC_PDCFGSTATUS1_OTP_PD_MASK)

#define PMC_PDCFGSTATUS1_ROM_PD_MASK             (0x10000U)
#define PMC_PDCFGSTATUS1_ROM_PD_SHIFT            (16U)
/*! ROM_PD - ROM Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS1_ROM_PD(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_ROM_PD_SHIFT)) & PMC_PDCFGSTATUS1_ROM_PD_MASK)

#define PMC_PDCFGSTATUS1_SRAMSLEEP_MASK          (0x80000000U)
#define PMC_PDCFGSTATUS1_SRAMSLEEP_SHIFT         (31U)
/*! SRAMSLEEP - SRAM Sleep Mode
 *  0b0..Normal
 *  0b1..Sleep
 */
#define PMC_PDCFGSTATUS1_SRAMSLEEP(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS1_SRAMSLEEP_SHIFT)) & PMC_PDCFGSTATUS1_SRAMSLEEP_MASK)
/*! @} */

/*! @name PDCFGSTATUS2 - PD Configuration Status 2 */
/*! @{ */

#define PMC_PDCFGSTATUS2_SRAM0_MASK              (0x1U)
#define PMC_PDCFGSTATUS2_SRAM0_SHIFT             (0U)
/*! SRAM0 - RAM Partition 0 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM0(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM0_SHIFT)) & PMC_PDCFGSTATUS2_SRAM0_MASK)

#define PMC_PDCFGSTATUS2_SRAM1_MASK              (0x2U)
#define PMC_PDCFGSTATUS2_SRAM1_SHIFT             (1U)
/*! SRAM1 - RAM Partition 1 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM1(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM1_SHIFT)) & PMC_PDCFGSTATUS2_SRAM1_MASK)

#define PMC_PDCFGSTATUS2_SRAM2_MASK              (0x4U)
#define PMC_PDCFGSTATUS2_SRAM2_SHIFT             (2U)
/*! SRAM2 - RAM Partition 2 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM2(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM2_SHIFT)) & PMC_PDCFGSTATUS2_SRAM2_MASK)

#define PMC_PDCFGSTATUS2_SRAM3_MASK              (0x8U)
#define PMC_PDCFGSTATUS2_SRAM3_SHIFT             (3U)
/*! SRAM3 - RAM Partition 3 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM3(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM3_SHIFT)) & PMC_PDCFGSTATUS2_SRAM3_MASK)

#define PMC_PDCFGSTATUS2_SRAM4_MASK              (0x10U)
#define PMC_PDCFGSTATUS2_SRAM4_SHIFT             (4U)
/*! SRAM4 - RAM Partition 4 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM4(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM4_SHIFT)) & PMC_PDCFGSTATUS2_SRAM4_MASK)

#define PMC_PDCFGSTATUS2_SRAM5_MASK              (0x20U)
#define PMC_PDCFGSTATUS2_SRAM5_SHIFT             (5U)
/*! SRAM5 - RAM Partition 5 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM5(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM5_SHIFT)) & PMC_PDCFGSTATUS2_SRAM5_MASK)

#define PMC_PDCFGSTATUS2_SRAM6_MASK              (0x40U)
#define PMC_PDCFGSTATUS2_SRAM6_SHIFT             (6U)
/*! SRAM6 - RAM Partition 6 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM6(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM6_SHIFT)) & PMC_PDCFGSTATUS2_SRAM6_MASK)

#define PMC_PDCFGSTATUS2_SRAM7_MASK              (0x80U)
#define PMC_PDCFGSTATUS2_SRAM7_SHIFT             (7U)
/*! SRAM7 - RAM Partition 7 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM7(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM7_SHIFT)) & PMC_PDCFGSTATUS2_SRAM7_MASK)

#define PMC_PDCFGSTATUS2_SRAM8_MASK              (0x100U)
#define PMC_PDCFGSTATUS2_SRAM8_SHIFT             (8U)
/*! SRAM8 - RAM Partition 8 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM8(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM8_SHIFT)) & PMC_PDCFGSTATUS2_SRAM8_MASK)

#define PMC_PDCFGSTATUS2_SRAM9_MASK              (0x200U)
#define PMC_PDCFGSTATUS2_SRAM9_SHIFT             (9U)
/*! SRAM9 - RAM Partition 9 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM9(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM9_SHIFT)) & PMC_PDCFGSTATUS2_SRAM9_MASK)

#define PMC_PDCFGSTATUS2_SRAM10_MASK             (0x400U)
#define PMC_PDCFGSTATUS2_SRAM10_SHIFT            (10U)
/*! SRAM10 - RAM Partition 10 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM10(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM10_SHIFT)) & PMC_PDCFGSTATUS2_SRAM10_MASK)

#define PMC_PDCFGSTATUS2_SRAM11_MASK             (0x800U)
#define PMC_PDCFGSTATUS2_SRAM11_SHIFT            (11U)
/*! SRAM11 - RAM Partition 11 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM11(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM11_SHIFT)) & PMC_PDCFGSTATUS2_SRAM11_MASK)

#define PMC_PDCFGSTATUS2_SRAM12_MASK             (0x1000U)
#define PMC_PDCFGSTATUS2_SRAM12_SHIFT            (12U)
/*! SRAM12 - RAM Partition 12 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM12(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM12_SHIFT)) & PMC_PDCFGSTATUS2_SRAM12_MASK)

#define PMC_PDCFGSTATUS2_SRAM13_MASK             (0x2000U)
#define PMC_PDCFGSTATUS2_SRAM13_SHIFT            (13U)
/*! SRAM13 - RAM Partition 13 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM13(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM13_SHIFT)) & PMC_PDCFGSTATUS2_SRAM13_MASK)

#define PMC_PDCFGSTATUS2_SRAM14_MASK             (0x4000U)
#define PMC_PDCFGSTATUS2_SRAM14_SHIFT            (14U)
/*! SRAM14 - RAM Partition 14 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM14(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM14_SHIFT)) & PMC_PDCFGSTATUS2_SRAM14_MASK)

#define PMC_PDCFGSTATUS2_SRAM15_MASK             (0x8000U)
#define PMC_PDCFGSTATUS2_SRAM15_SHIFT            (15U)
/*! SRAM15 - RAM Partition 15 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM15(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM15_SHIFT)) & PMC_PDCFGSTATUS2_SRAM15_MASK)

#define PMC_PDCFGSTATUS2_SRAM16_MASK             (0x10000U)
#define PMC_PDCFGSTATUS2_SRAM16_SHIFT            (16U)
/*! SRAM16 - RAM Partition 16 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM16(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM16_SHIFT)) & PMC_PDCFGSTATUS2_SRAM16_MASK)

#define PMC_PDCFGSTATUS2_SRAM17_MASK             (0x20000U)
#define PMC_PDCFGSTATUS2_SRAM17_SHIFT            (17U)
/*! SRAM17 - RAM Partition 17 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM17(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM17_SHIFT)) & PMC_PDCFGSTATUS2_SRAM17_MASK)

#define PMC_PDCFGSTATUS2_SRAM18_MASK             (0x40000U)
#define PMC_PDCFGSTATUS2_SRAM18_SHIFT            (18U)
/*! SRAM18 - RAM Partition 18 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM18(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM18_SHIFT)) & PMC_PDCFGSTATUS2_SRAM18_MASK)

#define PMC_PDCFGSTATUS2_SRAM19_MASK             (0x80000U)
#define PMC_PDCFGSTATUS2_SRAM19_SHIFT            (19U)
/*! SRAM19 - RAM Partition 19 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM19(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM19_SHIFT)) & PMC_PDCFGSTATUS2_SRAM19_MASK)

#define PMC_PDCFGSTATUS2_SRAM20_MASK             (0x100000U)
#define PMC_PDCFGSTATUS2_SRAM20_SHIFT            (20U)
/*! SRAM20 - RAM Partition 20 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM20(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM20_SHIFT)) & PMC_PDCFGSTATUS2_SRAM20_MASK)

#define PMC_PDCFGSTATUS2_SRAM21_MASK             (0x200000U)
#define PMC_PDCFGSTATUS2_SRAM21_SHIFT            (21U)
/*! SRAM21 - RAM Partition 21 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM21(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM21_SHIFT)) & PMC_PDCFGSTATUS2_SRAM21_MASK)

#define PMC_PDCFGSTATUS2_SRAM22_MASK             (0x400000U)
#define PMC_PDCFGSTATUS2_SRAM22_SHIFT            (22U)
/*! SRAM22 - RAM Partition 22 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM22(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM22_SHIFT)) & PMC_PDCFGSTATUS2_SRAM22_MASK)

#define PMC_PDCFGSTATUS2_SRAM23_MASK             (0x800000U)
#define PMC_PDCFGSTATUS2_SRAM23_SHIFT            (23U)
/*! SRAM23 - RAM Partition 23 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM23(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM23_SHIFT)) & PMC_PDCFGSTATUS2_SRAM23_MASK)

#define PMC_PDCFGSTATUS2_SRAM24_MASK             (0x1000000U)
#define PMC_PDCFGSTATUS2_SRAM24_SHIFT            (24U)
/*! SRAM24 - RAM Partition 24 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM24(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM24_SHIFT)) & PMC_PDCFGSTATUS2_SRAM24_MASK)

#define PMC_PDCFGSTATUS2_SRAM25_MASK             (0x2000000U)
#define PMC_PDCFGSTATUS2_SRAM25_SHIFT            (25U)
/*! SRAM25 - RAM Partition 25 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM25(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM25_SHIFT)) & PMC_PDCFGSTATUS2_SRAM25_MASK)

#define PMC_PDCFGSTATUS2_SRAM26_MASK             (0x4000000U)
#define PMC_PDCFGSTATUS2_SRAM26_SHIFT            (26U)
/*! SRAM26 - RAM Partition 26 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM26(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM26_SHIFT)) & PMC_PDCFGSTATUS2_SRAM26_MASK)

#define PMC_PDCFGSTATUS2_SRAM27_MASK             (0x8000000U)
#define PMC_PDCFGSTATUS2_SRAM27_SHIFT            (27U)
/*! SRAM27 - RAM Partition 27 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM27(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM27_SHIFT)) & PMC_PDCFGSTATUS2_SRAM27_MASK)

#define PMC_PDCFGSTATUS2_SRAM28_MASK             (0x10000000U)
#define PMC_PDCFGSTATUS2_SRAM28_SHIFT            (28U)
/*! SRAM28 - RAM Partition 28 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM28(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM28_SHIFT)) & PMC_PDCFGSTATUS2_SRAM28_MASK)

#define PMC_PDCFGSTATUS2_SRAM29_MASK             (0x20000000U)
#define PMC_PDCFGSTATUS2_SRAM29_SHIFT            (29U)
/*! SRAM29 - RAM Partition 29 Array Power Down
 *  0b1..Array and periphery were powered down
 *  0b0..Array was powered on
 */
#define PMC_PDCFGSTATUS2_SRAM29(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS2_SRAM29_SHIFT)) & PMC_PDCFGSTATUS2_SRAM29_MASK)
/*! @} */

/*! @name PDCFGSTATUS3 - PD Configuration Status 3 */
/*! @{ */

#define PMC_PDCFGSTATUS3_SRAM0_MASK              (0x1U)
#define PMC_PDCFGSTATUS3_SRAM0_SHIFT             (0U)
/*! SRAM0 - RAM Partition 0 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM0(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM0_SHIFT)) & PMC_PDCFGSTATUS3_SRAM0_MASK)

#define PMC_PDCFGSTATUS3_SRAM1_MASK              (0x2U)
#define PMC_PDCFGSTATUS3_SRAM1_SHIFT             (1U)
/*! SRAM1 - RAM Partition 1 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM1(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM1_SHIFT)) & PMC_PDCFGSTATUS3_SRAM1_MASK)

#define PMC_PDCFGSTATUS3_SRAM2_MASK              (0x4U)
#define PMC_PDCFGSTATUS3_SRAM2_SHIFT             (2U)
/*! SRAM2 - RAM Partition 2 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM2(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM2_SHIFT)) & PMC_PDCFGSTATUS3_SRAM2_MASK)

#define PMC_PDCFGSTATUS3_SRAM3_MASK              (0x8U)
#define PMC_PDCFGSTATUS3_SRAM3_SHIFT             (3U)
/*! SRAM3 - RAM Partition 3 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM3(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM3_SHIFT)) & PMC_PDCFGSTATUS3_SRAM3_MASK)

#define PMC_PDCFGSTATUS3_SRAM4_MASK              (0x10U)
#define PMC_PDCFGSTATUS3_SRAM4_SHIFT             (4U)
/*! SRAM4 - RAM Partition 4 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM4(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM4_SHIFT)) & PMC_PDCFGSTATUS3_SRAM4_MASK)

#define PMC_PDCFGSTATUS3_SRAM5_MASK              (0x20U)
#define PMC_PDCFGSTATUS3_SRAM5_SHIFT             (5U)
/*! SRAM5 - RAM Partition 5 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM5(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM5_SHIFT)) & PMC_PDCFGSTATUS3_SRAM5_MASK)

#define PMC_PDCFGSTATUS3_SRAM6_MASK              (0x40U)
#define PMC_PDCFGSTATUS3_SRAM6_SHIFT             (6U)
/*! SRAM6 - RAM Partition 6 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM6(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM6_SHIFT)) & PMC_PDCFGSTATUS3_SRAM6_MASK)

#define PMC_PDCFGSTATUS3_SRAM7_MASK              (0x80U)
#define PMC_PDCFGSTATUS3_SRAM7_SHIFT             (7U)
/*! SRAM7 - RAM Partition 7 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM7(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM7_SHIFT)) & PMC_PDCFGSTATUS3_SRAM7_MASK)

#define PMC_PDCFGSTATUS3_SRAM8_MASK              (0x100U)
#define PMC_PDCFGSTATUS3_SRAM8_SHIFT             (8U)
/*! SRAM8 - RAM Partition 8 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM8(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM8_SHIFT)) & PMC_PDCFGSTATUS3_SRAM8_MASK)

#define PMC_PDCFGSTATUS3_SRAM9_MASK              (0x200U)
#define PMC_PDCFGSTATUS3_SRAM9_SHIFT             (9U)
/*! SRAM9 - RAM Partition 9 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM9(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM9_SHIFT)) & PMC_PDCFGSTATUS3_SRAM9_MASK)

#define PMC_PDCFGSTATUS3_SRAM10_MASK             (0x400U)
#define PMC_PDCFGSTATUS3_SRAM10_SHIFT            (10U)
/*! SRAM10 - RAM Partition 10 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM10(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM10_SHIFT)) & PMC_PDCFGSTATUS3_SRAM10_MASK)

#define PMC_PDCFGSTATUS3_SRAM11_MASK             (0x800U)
#define PMC_PDCFGSTATUS3_SRAM11_SHIFT            (11U)
/*! SRAM11 - RAM Partition 11 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM11(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM11_SHIFT)) & PMC_PDCFGSTATUS3_SRAM11_MASK)

#define PMC_PDCFGSTATUS3_SRAM12_MASK             (0x1000U)
#define PMC_PDCFGSTATUS3_SRAM12_SHIFT            (12U)
/*! SRAM12 - RAM Partition 12 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM12(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM12_SHIFT)) & PMC_PDCFGSTATUS3_SRAM12_MASK)

#define PMC_PDCFGSTATUS3_SRAM13_MASK             (0x2000U)
#define PMC_PDCFGSTATUS3_SRAM13_SHIFT            (13U)
/*! SRAM13 - RAM Partition 13 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM13(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM13_SHIFT)) & PMC_PDCFGSTATUS3_SRAM13_MASK)

#define PMC_PDCFGSTATUS3_SRAM14_MASK             (0x4000U)
#define PMC_PDCFGSTATUS3_SRAM14_SHIFT            (14U)
/*! SRAM14 - RAM Partition 14 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM14(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM14_SHIFT)) & PMC_PDCFGSTATUS3_SRAM14_MASK)

#define PMC_PDCFGSTATUS3_SRAM15_MASK             (0x8000U)
#define PMC_PDCFGSTATUS3_SRAM15_SHIFT            (15U)
/*! SRAM15 - RAM Partition 15 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM15(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM15_SHIFT)) & PMC_PDCFGSTATUS3_SRAM15_MASK)

#define PMC_PDCFGSTATUS3_SRAM16_MASK             (0x10000U)
#define PMC_PDCFGSTATUS3_SRAM16_SHIFT            (16U)
/*! SRAM16 - RAM Partition 16 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM16(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM16_SHIFT)) & PMC_PDCFGSTATUS3_SRAM16_MASK)

#define PMC_PDCFGSTATUS3_SRAM17_MASK             (0x20000U)
#define PMC_PDCFGSTATUS3_SRAM17_SHIFT            (17U)
/*! SRAM17 - RAM Partition 17 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM17(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM17_SHIFT)) & PMC_PDCFGSTATUS3_SRAM17_MASK)

#define PMC_PDCFGSTATUS3_SRAM18_MASK             (0x40000U)
#define PMC_PDCFGSTATUS3_SRAM18_SHIFT            (18U)
/*! SRAM18 - RAM Partition 18 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM18(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM18_SHIFT)) & PMC_PDCFGSTATUS3_SRAM18_MASK)

#define PMC_PDCFGSTATUS3_SRAM19_MASK             (0x80000U)
#define PMC_PDCFGSTATUS3_SRAM19_SHIFT            (19U)
/*! SRAM19 - RAM Partition 19 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM19(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM19_SHIFT)) & PMC_PDCFGSTATUS3_SRAM19_MASK)

#define PMC_PDCFGSTATUS3_SRAM20_MASK             (0x100000U)
#define PMC_PDCFGSTATUS3_SRAM20_SHIFT            (20U)
/*! SRAM20 - RAM Partition 20 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM20(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM20_SHIFT)) & PMC_PDCFGSTATUS3_SRAM20_MASK)

#define PMC_PDCFGSTATUS3_SRAM21_MASK             (0x200000U)
#define PMC_PDCFGSTATUS3_SRAM21_SHIFT            (21U)
/*! SRAM21 - RAM Partition 21 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM21(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM21_SHIFT)) & PMC_PDCFGSTATUS3_SRAM21_MASK)

#define PMC_PDCFGSTATUS3_SRAM22_MASK             (0x400000U)
#define PMC_PDCFGSTATUS3_SRAM22_SHIFT            (22U)
/*! SRAM22 - RAM Partition 22 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM22(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM22_SHIFT)) & PMC_PDCFGSTATUS3_SRAM22_MASK)

#define PMC_PDCFGSTATUS3_SRAM23_MASK             (0x800000U)
#define PMC_PDCFGSTATUS3_SRAM23_SHIFT            (23U)
/*! SRAM23 - RAM Partition 23 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM23(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM23_SHIFT)) & PMC_PDCFGSTATUS3_SRAM23_MASK)

#define PMC_PDCFGSTATUS3_SRAM24_MASK             (0x1000000U)
#define PMC_PDCFGSTATUS3_SRAM24_SHIFT            (24U)
/*! SRAM24 - RAM Partition 24 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM24(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM24_SHIFT)) & PMC_PDCFGSTATUS3_SRAM24_MASK)

#define PMC_PDCFGSTATUS3_SRAM25_MASK             (0x2000000U)
#define PMC_PDCFGSTATUS3_SRAM25_SHIFT            (25U)
/*! SRAM25 - RAM Partition 25 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM25(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM25_SHIFT)) & PMC_PDCFGSTATUS3_SRAM25_MASK)

#define PMC_PDCFGSTATUS3_SRAM26_MASK             (0x4000000U)
#define PMC_PDCFGSTATUS3_SRAM26_SHIFT            (26U)
/*! SRAM26 - RAM Partition 26 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM26(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM26_SHIFT)) & PMC_PDCFGSTATUS3_SRAM26_MASK)

#define PMC_PDCFGSTATUS3_SRAM27_MASK             (0x8000000U)
#define PMC_PDCFGSTATUS3_SRAM27_SHIFT            (27U)
/*! SRAM27 - RAM Partition 27 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM27(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM27_SHIFT)) & PMC_PDCFGSTATUS3_SRAM27_MASK)

#define PMC_PDCFGSTATUS3_SRAM28_MASK             (0x10000000U)
#define PMC_PDCFGSTATUS3_SRAM28_SHIFT            (28U)
/*! SRAM28 - RAM Partition 28 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM28(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM28_SHIFT)) & PMC_PDCFGSTATUS3_SRAM28_MASK)

#define PMC_PDCFGSTATUS3_SRAM29_MASK             (0x20000000U)
#define PMC_PDCFGSTATUS3_SRAM29_SHIFT            (29U)
/*! SRAM29 - RAM Partition 29 Periphery Power Down
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS3_SRAM29(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS3_SRAM29_SHIFT)) & PMC_PDCFGSTATUS3_SRAM29_MASK)
/*! @} */

/*! @name PDCFGSTATUS4 - PD Configuration Status 4 */
/*! @{ */

#define PMC_PDCFGSTATUS4_SDHC0_SRAM_MASK         (0x1U)
#define PMC_PDCFGSTATUS4_SDHC0_SRAM_SHIFT        (0U)
/*! SDHC0_SRAM - uSDHC0 RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_SDHC0_SRAM(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_SDHC0_SRAM_SHIFT)) & PMC_PDCFGSTATUS4_SDHC0_SRAM_MASK)

#define PMC_PDCFGSTATUS4_SDHC1_SRAM_MASK         (0x2U)
#define PMC_PDCFGSTATUS4_SDHC1_SRAM_SHIFT        (1U)
/*! SDHC1_SRAM - uSDHC1 RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_SDHC1_SRAM(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_SDHC1_SRAM_SHIFT)) & PMC_PDCFGSTATUS4_SDHC1_SRAM_MASK)

#define PMC_PDCFGSTATUS4_USB0_SRAM_MASK          (0x4U)
#define PMC_PDCFGSTATUS4_USB0_SRAM_SHIFT         (2U)
/*! USB0_SRAM - USB0 RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_USB0_SRAM(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_USB0_SRAM_SHIFT)) & PMC_PDCFGSTATUS4_USB0_SRAM_MASK)

#define PMC_PDCFGSTATUS4_USB1_SRAM_MASK          (0x8U)
#define PMC_PDCFGSTATUS4_USB1_SRAM_SHIFT         (3U)
/*! USB1_SRAM - USB1 RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_USB1_SRAM(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_USB1_SRAM_SHIFT)) & PMC_PDCFGSTATUS4_USB1_SRAM_MASK)

#define PMC_PDCFGSTATUS4_JPEG_MASK               (0x10U)
#define PMC_PDCFGSTATUS4_JPEG_SHIFT              (4U)
/*! JPEG - JPEGDEC RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_JPEG(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_JPEG_SHIFT)) & PMC_PDCFGSTATUS4_JPEG_MASK)

#define PMC_PDCFGSTATUS4_PNG_MASK                (0x20U)
#define PMC_PDCFGSTATUS4_PNG_SHIFT               (5U)
/*! PNG - PNGDEC RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_PNG(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_PNG_SHIFT)) & PMC_PDCFGSTATUS4_PNG_MASK)

#define PMC_PDCFGSTATUS4_MIPI_MASK               (0x40U)
#define PMC_PDCFGSTATUS4_MIPI_SHIFT              (6U)
/*! MIPI - MIPI PHY RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_MIPI(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_MIPI_SHIFT)) & PMC_PDCFGSTATUS4_MIPI_MASK)

#define PMC_PDCFGSTATUS4_GPU_MASK                (0x80U)
#define PMC_PDCFGSTATUS4_GPU_SHIFT               (7U)
/*! GPU - VGPU RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_GPU(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_GPU_SHIFT)) & PMC_PDCFGSTATUS4_GPU_MASK)

#define PMC_PDCFGSTATUS4_DMA2_3_MASK             (0x100U)
#define PMC_PDCFGSTATUS4_DMA2_3_SHIFT            (8U)
/*! DMA2_3 - DMA2 and DMA3 RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_DMA2_3(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_DMA2_3_SHIFT)) & PMC_PDCFGSTATUS4_DMA2_3_MASK)

#define PMC_PDCFGSTATUS4_DMA0_1_P_E_MASK         (0x200U)
#define PMC_PDCFGSTATUS4_DMA0_1_P_E_SHIFT        (9U)
/*! DMA0_1_P_E - DMA0-1, PKC, and ETF RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_DMA0_1_P_E(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_DMA0_1_P_E_SHIFT)) & PMC_PDCFGSTATUS4_DMA0_1_P_E_MASK)

#define PMC_PDCFGSTATUS4_CPU0_CCACHE_MASK        (0x400U)
#define PMC_PDCFGSTATUS4_CPU0_CCACHE_SHIFT       (10U)
/*! CPU0_CCACHE - CPU0 Code Cache RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_CPU0_CCACHE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_CPU0_CCACHE_SHIFT)) & PMC_PDCFGSTATUS4_CPU0_CCACHE_MASK)

#define PMC_PDCFGSTATUS4_CPU0_SCACHE_MASK        (0x800U)
#define PMC_PDCFGSTATUS4_CPU0_SCACHE_SHIFT       (11U)
/*! CPU0_SCACHE - CPU0 System Cache RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_CPU0_SCACHE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_CPU0_SCACHE_SHIFT)) & PMC_PDCFGSTATUS4_CPU0_SCACHE_MASK)

#define PMC_PDCFGSTATUS4_DSP_ICACHE_MASK         (0x1000U)
#define PMC_PDCFGSTATUS4_DSP_ICACHE_SHIFT        (12U)
/*! DSP_ICACHE - HiFi4 Instruction Cache RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_DSP_ICACHE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_DSP_ICACHE_SHIFT)) & PMC_PDCFGSTATUS4_DSP_ICACHE_MASK)

#define PMC_PDCFGSTATUS4_DSP_DCACHE_MASK         (0x2000U)
#define PMC_PDCFGSTATUS4_DSP_DCACHE_SHIFT        (13U)
/*! DSP_DCACHE - HiFi4 Data Cache RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_DSP_DCACHE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_DSP_DCACHE_SHIFT)) & PMC_PDCFGSTATUS4_DSP_DCACHE_MASK)

#define PMC_PDCFGSTATUS4_DSP_ITCM_MASK           (0x4000U)
#define PMC_PDCFGSTATUS4_DSP_ITCM_SHIFT          (14U)
/*! DSP_ITCM - HiFi4 Instruction TCM RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_DSP_ITCM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_DSP_ITCM_SHIFT)) & PMC_PDCFGSTATUS4_DSP_ITCM_MASK)

#define PMC_PDCFGSTATUS4_DSP_DTCM_MASK           (0x8000U)
#define PMC_PDCFGSTATUS4_DSP_DTCM_SHIFT          (15U)
/*! DSP_DTCM - HiFi4 Data TCM RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_DSP_DTCM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_DSP_DTCM_SHIFT)) & PMC_PDCFGSTATUS4_DSP_DTCM_MASK)

#define PMC_PDCFGSTATUS4_EZH_TCM_MASK            (0x10000U)
#define PMC_PDCFGSTATUS4_EZH_TCM_SHIFT           (16U)
/*! EZH_TCM - EZH-V TCM RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_EZH_TCM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_EZH_TCM_SHIFT)) & PMC_PDCFGSTATUS4_EZH_TCM_MASK)

#define PMC_PDCFGSTATUS4_NPU_MASK                (0x20000U)
#define PMC_PDCFGSTATUS4_NPU_SHIFT               (17U)
/*! NPU - NPU RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_NPU(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_NPU_SHIFT)) & PMC_PDCFGSTATUS4_NPU_MASK)

#define PMC_PDCFGSTATUS4_XSPI0_MASK              (0x40000U)
#define PMC_PDCFGSTATUS4_XSPI0_SHIFT             (18U)
/*! XSPI0 - XSPI0, MMU0, and Cache RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_XSPI0(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_XSPI0_SHIFT)) & PMC_PDCFGSTATUS4_XSPI0_MASK)

#define PMC_PDCFGSTATUS4_XSPI1_MASK              (0x80000U)
#define PMC_PDCFGSTATUS4_XSPI1_SHIFT             (19U)
/*! XSPI1 - XSPI1, MMU1, and Cache RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_XSPI1(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_XSPI1_SHIFT)) & PMC_PDCFGSTATUS4_XSPI1_MASK)

#define PMC_PDCFGSTATUS4_XSPI2_MASK              (0x100000U)
#define PMC_PDCFGSTATUS4_XSPI2_SHIFT             (20U)
/*! XSPI2 - XSPI2 and MMU2 RAMs Array
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS4_XSPI2(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_XSPI2_SHIFT)) & PMC_PDCFGSTATUS4_XSPI2_MASK)

#define PMC_PDCFGSTATUS4_LCD_MASK                (0x200000U)
#define PMC_PDCFGSTATUS4_LCD_SHIFT               (21U)
/*! LCD - LCDIF Controller RAMs Array
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS4_LCD(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_LCD_SHIFT)) & PMC_PDCFGSTATUS4_LCD_MASK)

#define PMC_PDCFGSTATUS4_OCOTP_MASK              (0x400000U)
#define PMC_PDCFGSTATUS4_OCOTP_SHIFT             (22U)
/*! OCOTP - OCOTP Shadow SRAM
 *  0b1..Array Power Down
 *  0b0..Array Powered
 */
#define PMC_PDCFGSTATUS4_OCOTP(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS4_OCOTP_SHIFT)) & PMC_PDCFGSTATUS4_OCOTP_MASK)
/*! @} */

/*! @name PDCFGSTATUS5 - PD Configuration Status 5 */
/*! @{ */

#define PMC_PDCFGSTATUS5_SDHC0_SRAM_MASK         (0x1U)
#define PMC_PDCFGSTATUS5_SDHC0_SRAM_SHIFT        (0U)
/*! SDHC0_SRAM - uSDHC0 RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_SDHC0_SRAM(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_SDHC0_SRAM_SHIFT)) & PMC_PDCFGSTATUS5_SDHC0_SRAM_MASK)

#define PMC_PDCFGSTATUS5_SDHC1_SRAM_MASK         (0x2U)
#define PMC_PDCFGSTATUS5_SDHC1_SRAM_SHIFT        (1U)
/*! SDHC1_SRAM - uSDHC1 RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_SDHC1_SRAM(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_SDHC1_SRAM_SHIFT)) & PMC_PDCFGSTATUS5_SDHC1_SRAM_MASK)

#define PMC_PDCFGSTATUS5_USB0_SRAM_MASK          (0x4U)
#define PMC_PDCFGSTATUS5_USB0_SRAM_SHIFT         (2U)
/*! USB0_SRAM - USB0 RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_USB0_SRAM(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_USB0_SRAM_SHIFT)) & PMC_PDCFGSTATUS5_USB0_SRAM_MASK)

#define PMC_PDCFGSTATUS5_USB1_SRAM_MASK          (0x8U)
#define PMC_PDCFGSTATUS5_USB1_SRAM_SHIFT         (3U)
/*! USB1_SRAM - USB1 RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_USB1_SRAM(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_USB1_SRAM_SHIFT)) & PMC_PDCFGSTATUS5_USB1_SRAM_MASK)

#define PMC_PDCFGSTATUS5_JPEG_MASK               (0x10U)
#define PMC_PDCFGSTATUS5_JPEG_SHIFT              (4U)
/*! JPEG - JPEGDEC RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_JPEG(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_JPEG_SHIFT)) & PMC_PDCFGSTATUS5_JPEG_MASK)

#define PMC_PDCFGSTATUS5_PNG_MASK                (0x20U)
#define PMC_PDCFGSTATUS5_PNG_SHIFT               (5U)
/*! PNG - PNGDEC RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_PNG(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_PNG_SHIFT)) & PMC_PDCFGSTATUS5_PNG_MASK)

#define PMC_PDCFGSTATUS5_MIPI_MASK               (0x40U)
#define PMC_PDCFGSTATUS5_MIPI_SHIFT              (6U)
/*! MIPI - MIPI PHY RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_MIPI(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_MIPI_SHIFT)) & PMC_PDCFGSTATUS5_MIPI_MASK)

#define PMC_PDCFGSTATUS5_GPU_MASK                (0x80U)
#define PMC_PDCFGSTATUS5_GPU_SHIFT               (7U)
/*! GPU - VGPU RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_GPU(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_GPU_SHIFT)) & PMC_PDCFGSTATUS5_GPU_MASK)

#define PMC_PDCFGSTATUS5_DMA2_3_MASK             (0x100U)
#define PMC_PDCFGSTATUS5_DMA2_3_SHIFT            (8U)
/*! DMA2_3 - DMA2 and DMA3 RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_DMA2_3(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_DMA2_3_SHIFT)) & PMC_PDCFGSTATUS5_DMA2_3_MASK)

#define PMC_PDCFGSTATUS5_DMA0_1_P_E_MASK         (0x200U)
#define PMC_PDCFGSTATUS5_DMA0_1_P_E_SHIFT        (9U)
/*! DMA0_1_P_E - DMA0-1, PKC, and ETF RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_DMA0_1_P_E(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_DMA0_1_P_E_SHIFT)) & PMC_PDCFGSTATUS5_DMA0_1_P_E_MASK)

#define PMC_PDCFGSTATUS5_CPU0_CCACHE_MASK        (0x400U)
#define PMC_PDCFGSTATUS5_CPU0_CCACHE_SHIFT       (10U)
/*! CPU0_CCACHE - CPU0 Code Cache RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_CPU0_CCACHE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_CPU0_CCACHE_SHIFT)) & PMC_PDCFGSTATUS5_CPU0_CCACHE_MASK)

#define PMC_PDCFGSTATUS5_CPU0_SCACHE_MASK        (0x800U)
#define PMC_PDCFGSTATUS5_CPU0_SCACHE_SHIFT       (11U)
/*! CPU0_SCACHE - CPU0 System Cache RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_CPU0_SCACHE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_CPU0_SCACHE_SHIFT)) & PMC_PDCFGSTATUS5_CPU0_SCACHE_MASK)

#define PMC_PDCFGSTATUS5_DSP_ICACHE_MASK         (0x1000U)
#define PMC_PDCFGSTATUS5_DSP_ICACHE_SHIFT        (12U)
/*! DSP_ICACHE - HiFi4 Instruction Cache RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_DSP_ICACHE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_DSP_ICACHE_SHIFT)) & PMC_PDCFGSTATUS5_DSP_ICACHE_MASK)

#define PMC_PDCFGSTATUS5_DSP_DCACHE_MASK         (0x2000U)
#define PMC_PDCFGSTATUS5_DSP_DCACHE_SHIFT        (13U)
/*! DSP_DCACHE - HiFi4 Data Cache RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_DSP_DCACHE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_DSP_DCACHE_SHIFT)) & PMC_PDCFGSTATUS5_DSP_DCACHE_MASK)

#define PMC_PDCFGSTATUS5_DSP_ITCM_MASK           (0x4000U)
#define PMC_PDCFGSTATUS5_DSP_ITCM_SHIFT          (14U)
/*! DSP_ITCM - HiFi4 Instruction TCM RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_DSP_ITCM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_DSP_ITCM_SHIFT)) & PMC_PDCFGSTATUS5_DSP_ITCM_MASK)

#define PMC_PDCFGSTATUS5_DSP_DTCM_MASK           (0x8000U)
#define PMC_PDCFGSTATUS5_DSP_DTCM_SHIFT          (15U)
/*! DSP_DTCM - HiFi4 Data TCM RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_DSP_DTCM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_DSP_DTCM_SHIFT)) & PMC_PDCFGSTATUS5_DSP_DTCM_MASK)

#define PMC_PDCFGSTATUS5_EZH_TCM_MASK            (0x10000U)
#define PMC_PDCFGSTATUS5_EZH_TCM_SHIFT           (16U)
/*! EZH_TCM - EZH-V TCM RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_EZH_TCM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_EZH_TCM_SHIFT)) & PMC_PDCFGSTATUS5_EZH_TCM_MASK)

#define PMC_PDCFGSTATUS5_NPU_MASK                (0x20000U)
#define PMC_PDCFGSTATUS5_NPU_SHIFT               (17U)
/*! NPU - NPU RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_NPU(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)

#define PMC_PDCFGSTATUS5_XSPI0_MASK              (0x40000U)
#define PMC_PDCFGSTATUS5_XSPI0_SHIFT             (18U)
/*! XSPI0 - XSPI0, MMU0, and Cache RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_XSPI0(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_XSPI0_SHIFT)) & PMC_PDCFGSTATUS5_XSPI0_MASK)

#define PMC_PDCFGSTATUS5_XSPI1_MASK              (0x80000U)
#define PMC_PDCFGSTATUS5_XSPI1_SHIFT             (19U)
/*! XSPI1 - XSPI1, MMU1, and Cache RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_XSPI1(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_XSPI1_SHIFT)) & PMC_PDCFGSTATUS5_XSPI1_MASK)

#define PMC_PDCFGSTATUS5_XSPI2_MASK              (0x100000U)
#define PMC_PDCFGSTATUS5_XSPI2_SHIFT             (20U)
/*! XSPI2 - XSPI2 and MMU2 RAMs Periphery
 *  0b0..Power on
 *  0b1..Power down
 */
#define PMC_PDCFGSTATUS5_XSPI2(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_XSPI2_SHIFT)) & PMC_PDCFGSTATUS5_XSPI2_MASK)

#define PMC_PDCFGSTATUS5_LCD_MASK                (0x200000U)
#define PMC_PDCFGSTATUS5_LCD_SHIFT               (21U)
/*! LCD - LCDIF Controller RAMs Periphery
 *  0b1..Power down
 *  0b0..Power on
 */
#define PMC_PDCFGSTATUS5_LCD(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_LCD_SHIFT)) & PMC_PDCFGSTATUS5_LCD_MASK)

#define PMC_PDCFGSTATUS5_OCOTP_MASK              (0x400000U)
#define PMC_PDCFGSTATUS5_OCOTP_SHIFT             (22U)
/*! OCOTP - OCOTP Shadow SRAM
 *  0b1..Array Power Down
 *  0b0..Array Powered
 */
#define PMC_PDCFGSTATUS5_OCOTP(x)                (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_OCOTP_SHIFT)) & PMC_PDCFGSTATUS5_OCOTP_MASK)
/*! @} */

/*! @name PDWAKECFG - PD Wake-up Configuration for Compute Domain */
/*! @{ */

#define PMC_PDWAKECFG_RBB1KP_MASK                (0x1U)
#define PMC_PDWAKECFG_RBB1KP_SHIFT               (0U)
/*! RBB1KP - RBB Wake-up in VDD1 Domain
 *  0b0..Do not copy during Deep Sleep
 *  0b1..Copy during Deep Sleep
 */
#define PMC_PDWAKECFG_RBB1KP(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDWAKECFG_RBB1KP_SHIFT)) & PMC_PDWAKECFG_RBB1KP_MASK)

#define PMC_PDWAKECFG_RBB2KP_MASK                (0x2U)
#define PMC_PDWAKECFG_RBB2KP_SHIFT               (1U)
/*! RBB2KP - RBB Wake-up in VDD2 Domain
 *  0b0..Do not copy during Deep Sleep
 *  0b1..Copy during Deep Sleep
 */
#define PMC_PDWAKECFG_RBB2KP(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDWAKECFG_RBB2KP_SHIFT)) & PMC_PDWAKECFG_RBB2KP_MASK)

#define PMC_PDWAKECFG_RBBNKP_MASK                (0x4U)
#define PMC_PDWAKECFG_RBBNKP_SHIFT               (2U)
/*! RBBNKP - RBB Wake-up in VDDN Domain
 *  0b0..Do not copy during Deep Sleep
 *  0b1..Copy during Deep Sleep
 */
#define PMC_PDWAKECFG_RBBNKP(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PDWAKECFG_RBBNKP_SHIFT)) & PMC_PDWAKECFG_RBBNKP_MASK)

#define PMC_PDWAKECFG_AFBB1KP_MASK               (0x100U)
#define PMC_PDWAKECFG_AFBB1KP_SHIFT              (8U)
/*! AFBB1KP - AFBB Wake-up in VDD1 Domain
 *  0b0..Do not copy during Deep Sleep
 *  0b1..Copy during Deep Sleep
 */
#define PMC_PDWAKECFG_AFBB1KP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDWAKECFG_AFBB1KP_SHIFT)) & PMC_PDWAKECFG_AFBB1KP_MASK)

#define PMC_PDWAKECFG_AFBB2KP_MASK               (0x200U)
#define PMC_PDWAKECFG_AFBB2KP_SHIFT              (9U)
/*! AFBB2KP - AFBB Wake-up in VDD2 Domain
 *  0b0..Do not copy during Deep Sleep
 *  0b1..Copy during Deep Sleep
 */
#define PMC_PDWAKECFG_AFBB2KP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDWAKECFG_AFBB2KP_SHIFT)) & PMC_PDWAKECFG_AFBB2KP_MASK)

#define PMC_PDWAKECFG_AFBBNKP_MASK               (0x400U)
#define PMC_PDWAKECFG_AFBBNKP_SHIFT              (10U)
/*! AFBBNKP - AFBB Wake-up in VDDN Domain
 *  0b0..Do not copy during Deep Sleep
 *  0b1..Copy during Deep Sleep
 */
#define PMC_PDWAKECFG_AFBBNKP(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_PDWAKECFG_AFBBNKP_SHIFT)) & PMC_PDWAKECFG_AFBBNKP_MASK)
/*! @} */

/*! @name PWRFLAGS - Power Domain Flags for Compute Domain */
/*! @{ */

#define PMC_PWRFLAGS_V1SENSF_MASK                (0x1U)
#define PMC_PWRFLAGS_V1SENSF_SHIFT               (0U)
/*! V1SENSF - VDD1_SENSE Domain Flag
 *  0b1..DSR event occurred
 *  0b0..No DSR event occurred
 */
#define PMC_PWRFLAGS_V1SENSF(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PWRFLAGS_V1SENSF_SHIFT)) & PMC_PWRFLAGS_V1SENSF_MASK)

#define PMC_PWRFLAGS_V2COMPF_MASK                (0x2U)
#define PMC_PWRFLAGS_V2COMPF_SHIFT               (1U)
/*! V2COMPF - VDD2_COMP Domain Flag
 *  0b1..DSR event occurred
 *  0b0..No DSR event occurred
 */
#define PMC_PWRFLAGS_V2COMPF(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PWRFLAGS_V2COMPF_SHIFT)) & PMC_PWRFLAGS_V2COMPF_MASK)

#define PMC_PWRFLAGS_V2NMEDF_MASK                (0x4U)
#define PMC_PWRFLAGS_V2NMEDF_SHIFT               (2U)
/*! V2NMEDF - VDD2_MEDIA and VDDN_MEDIA Domain Flag
 *  0b1..DSR event occurred
 *  0b0..No DSR event occurred
 */
#define PMC_PWRFLAGS_V2NMEDF(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PWRFLAGS_V2NMEDF_SHIFT)) & PMC_PWRFLAGS_V2NMEDF_MASK)

#define PMC_PWRFLAGS_V2COMF_MASK                 (0x8U)
#define PMC_PWRFLAGS_V2COMF_SHIFT                (3U)
/*! V2COMF - VDD2_COM Domain Flag
 *  0b1..DSR event occurred
 *  0b0..No DSR event occurred
 */
#define PMC_PWRFLAGS_V2COMF(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PWRFLAGS_V2COMF_SHIFT)) & PMC_PWRFLAGS_V2COMF_MASK)

#define PMC_PWRFLAGS_VNCOMF_MASK                 (0x10U)
#define PMC_PWRFLAGS_VNCOMF_SHIFT                (4U)
/*! VNCOMF - VDDN_COM Domain Flag
 *  0b1..DSR event occurred
 *  0b0..No DSR event occurred
 */
#define PMC_PWRFLAGS_VNCOMF(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PWRFLAGS_VNCOMF_SHIFT)) & PMC_PWRFLAGS_VNCOMF_MASK)

#define PMC_PWRFLAGS_V2DSPF_MASK                 (0x20U)
#define PMC_PWRFLAGS_V2DSPF_SHIFT                (5U)
/*! V2DSPF - VDD2_DSP Domain Flag
 *  0b1..Power-down event occurred
 *  0b0..No power-down event occurred
 */
#define PMC_PWRFLAGS_V2DSPF(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PWRFLAGS_V2DSPF_SHIFT)) & PMC_PWRFLAGS_V2DSPF_MASK)

#define PMC_PWRFLAGS_V2MIPIF_MASK                (0x40U)
#define PMC_PWRFLAGS_V2MIPIF_SHIFT               (6U)
/*! V2MIPIF - VDD2_MIPI Domain Flag
 *  0b1..Power-down event occurred
 *  0b0..No power-down event occurred
 */
#define PMC_PWRFLAGS_V2MIPIF(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_PWRFLAGS_V2MIPIF_SHIFT)) & PMC_PWRFLAGS_V2MIPIF_MASK)

#define PMC_PWRFLAGS_V2OTPF_MASK                 (0x80U)
#define PMC_PWRFLAGS_V2OTPF_SHIFT                (7U)
/*! V2OTPF - VDD2_OTP Domain Flag
 *  0b1..Power-down event occurred
 *  0b0..No power-down event occurred
 */
#define PMC_PWRFLAGS_V2OTPF(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_PWRFLAGS_V2OTPF_SHIFT)) & PMC_PWRFLAGS_V2OTPF_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PMC_Register_Masks */


/* PMC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PMC0 base address */
  #define PMC0_BASE                                (0x5020F000u)
  /** Peripheral PMC0 base address */
  #define PMC0_BASE_NS                             (0x4020F000u)
  /** Peripheral PMC0 base pointer */
  #define PMC0                                     ((PMC_Type *)PMC0_BASE)
  /** Peripheral PMC0 base pointer */
  #define PMC0_NS                                  ((PMC_Type *)PMC0_BASE_NS)
  /** Array initializer of PMC peripheral base addresses */
  #define PMC_BASE_ADDRS                           { PMC0_BASE }
  /** Array initializer of PMC peripheral base pointers */
  #define PMC_BASE_PTRS                            { PMC0 }
  /** Array initializer of PMC peripheral base addresses */
  #define PMC_BASE_ADDRS_NS                        { PMC0_BASE_NS }
  /** Array initializer of PMC peripheral base pointers */
  #define PMC_BASE_PTRS_NS                         { PMC0_NS }
#else
  /** Peripheral PMC0 base address */
  #define PMC0_BASE                                (0x4020F000u)
  /** Peripheral PMC0 base pointer */
  #define PMC0                                     ((PMC_Type *)PMC0_BASE)
  /** Array initializer of PMC peripheral base addresses */
  #define PMC_BASE_ADDRS                           { PMC0_BASE }
  /** Array initializer of PMC peripheral base pointers */
  #define PMC_BASE_PTRS                            { PMC0 }
#endif

/*!
 * @}
 */ /* end of group PMC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PNGDEC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PNGDEC_Peripheral_Access_Layer PNGDEC Peripheral Access Layer
 * @{
 */

/** PNGDEC - Register Layout Typedef */
typedef struct {
  __IO uint32_t GLB_CTRL;                          /**< Global Control, offset: 0x0 */
  __IO uint32_t DMA_TRIG;                          /**< DMA Trigger, offset: 0x4 */
  __IO uint32_t CNT_CTRL_CLR;                      /**< Count Control Clear, offset: 0x8 */
       uint8_t RESERVED_0[20];
  __IO uint32_t ENC_DATA_DMA_SRC_ADDR;             /**< Encode Data Source Address, offset: 0x20 */
  __IO uint32_t ENC_DATA_DMA_SRC_LEN;              /**< Encode Data Source Length, offset: 0x24 */
  __IO uint32_t DEC_PIXEL_DMA_DES_ADDR;            /**< Decode Pixel Destination Address, offset: 0x28 */
  __I  uint32_t DEC_PIXEL_DMA_DES_LEN;             /**< Decode Pixel Destination Length, offset: 0x2C */
  __IO uint32_t DEC_ANC_DMA_DES_ADDR;              /**< Decode Ancillary Destination Address, offset: 0x30 */
  __I  uint32_t DEC_ANC_DMA_DES_LEN;               /**< Decode Ancillary Destination Length, offset: 0x34 */
       uint8_t RESERVED_1[72];
  __IO uint32_t DEC_INT_STS;                       /**< Decode Interrupt Status, offset: 0x80 */
  __IO uint32_t DEC_INT_STS_EN;                    /**< Interrupt Enable, offset: 0x84 */
       uint8_t RESERVED_2[24];
  __I  uint32_t AXI3_ENC_DATA_RD_BYTE_CNT;         /**< AXI3 Encoded Data Read Bytes Counter, offset: 0xA0 */
  __I  uint32_t AXI3_DEC_PIXEL_WR_BYTE_CNT;        /**< AXI3 Decoded Pixel Write Bytes Counter, offset: 0xA4 */
  __I  uint32_t AXI3_DEC_ANC_WR_BYTE_CNT;          /**< AXI3 Decode Ancillary Write Bytes Counter, offset: 0xA8 */
} PNGDEC_Type;

/* ----------------------------------------------------------------------------
   -- PNGDEC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PNGDEC_Register_Masks PNGDEC Register Masks
 * @{
 */

/*! @name GLB_CTRL - Global Control */
/*! @{ */

#define PNGDEC_GLB_CTRL_DEC_EN_MASK              (0x1U)
#define PNGDEC_GLB_CTRL_DEC_EN_SHIFT             (0U)
/*! DEC_EN - Decode Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_GLB_CTRL_DEC_EN(x)                (((uint32_t)(((uint32_t)(x)) << PNGDEC_GLB_CTRL_DEC_EN_SHIFT)) & PNGDEC_GLB_CTRL_DEC_EN_MASK)

#define PNGDEC_GLB_CTRL_ANC_DROP_EN_MASK         (0x2U)
#define PNGDEC_GLB_CTRL_ANC_DROP_EN_SHIFT        (1U)
/*! ANC_DROP_EN - Ancillary Data Drop Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_GLB_CTRL_ANC_DROP_EN(x)           (((uint32_t)(((uint32_t)(x)) << PNGDEC_GLB_CTRL_ANC_DROP_EN_SHIFT)) & PNGDEC_GLB_CTRL_ANC_DROP_EN_MASK)

#define PNGDEC_GLB_CTRL_DMA_SW_LOGIC_RST_EN_MASK (0x4U)
#define PNGDEC_GLB_CTRL_DMA_SW_LOGIC_RST_EN_SHIFT (2U)
/*! DMA_SW_LOGIC_RST_EN - DMA Software Logic Reset Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_GLB_CTRL_DMA_SW_LOGIC_RST_EN(x)   (((uint32_t)(((uint32_t)(x)) << PNGDEC_GLB_CTRL_DMA_SW_LOGIC_RST_EN_SHIFT)) & PNGDEC_GLB_CTRL_DMA_SW_LOGIC_RST_EN_MASK)

#define PNGDEC_GLB_CTRL_IPCORE_SW_LOGIC_RST_EN_MASK (0x8U)
#define PNGDEC_GLB_CTRL_IPCORE_SW_LOGIC_RST_EN_SHIFT (3U)
/*! IPCORE_SW_LOGIC_RST_EN - Core Software Logic Reset Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_GLB_CTRL_IPCORE_SW_LOGIC_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_GLB_CTRL_IPCORE_SW_LOGIC_RST_EN_SHIFT)) & PNGDEC_GLB_CTRL_IPCORE_SW_LOGIC_RST_EN_MASK)
/*! @} */

/*! @name DMA_TRIG - DMA Trigger */
/*! @{ */

#define PNGDEC_DMA_TRIG_DMA_TRIG_MASK            (0x1U)
#define PNGDEC_DMA_TRIG_DMA_TRIG_SHIFT           (0U)
/*! DMA_TRIG - DMA Trigger
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DMA_TRIG_DMA_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << PNGDEC_DMA_TRIG_DMA_TRIG_SHIFT)) & PNGDEC_DMA_TRIG_DMA_TRIG_MASK)
/*! @} */

/*! @name CNT_CTRL_CLR - Count Control Clear */
/*! @{ */

#define PNGDEC_CNT_CTRL_CLR_CNT_CTRL_CLR_MASK    (0x1U)
#define PNGDEC_CNT_CTRL_CLR_CNT_CTRL_CLR_SHIFT   (0U)
/*! CNT_CTRL_CLR - Count Control Clear
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_CNT_CTRL_CLR_CNT_CTRL_CLR(x)      (((uint32_t)(((uint32_t)(x)) << PNGDEC_CNT_CTRL_CLR_CNT_CTRL_CLR_SHIFT)) & PNGDEC_CNT_CTRL_CLR_CNT_CTRL_CLR_MASK)
/*! @} */

/*! @name ENC_DATA_DMA_SRC_ADDR - Encode Data Source Address */
/*! @{ */

#define PNGDEC_ENC_DATA_DMA_SRC_ADDR_SRC_ADDR_MASK (0xFFFFFFFFU)
#define PNGDEC_ENC_DATA_DMA_SRC_ADDR_SRC_ADDR_SHIFT (0U)
/*! SRC_ADDR - Source Address */
#define PNGDEC_ENC_DATA_DMA_SRC_ADDR_SRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_ENC_DATA_DMA_SRC_ADDR_SRC_ADDR_SHIFT)) & PNGDEC_ENC_DATA_DMA_SRC_ADDR_SRC_ADDR_MASK)
/*! @} */

/*! @name ENC_DATA_DMA_SRC_LEN - Encode Data Source Length */
/*! @{ */

#define PNGDEC_ENC_DATA_DMA_SRC_LEN_SRC_LEN_MASK (0xFFFFFFFFU)
#define PNGDEC_ENC_DATA_DMA_SRC_LEN_SRC_LEN_SHIFT (0U)
/*! SRC_LEN - Source Length */
#define PNGDEC_ENC_DATA_DMA_SRC_LEN_SRC_LEN(x)   (((uint32_t)(((uint32_t)(x)) << PNGDEC_ENC_DATA_DMA_SRC_LEN_SRC_LEN_SHIFT)) & PNGDEC_ENC_DATA_DMA_SRC_LEN_SRC_LEN_MASK)
/*! @} */

/*! @name DEC_PIXEL_DMA_DES_ADDR - Decode Pixel Destination Address */
/*! @{ */

#define PNGDEC_DEC_PIXEL_DMA_DES_ADDR_PIXEL_DES_ADDR_MASK (0xFFFFFFFFU)
#define PNGDEC_DEC_PIXEL_DMA_DES_ADDR_PIXEL_DES_ADDR_SHIFT (0U)
/*! PIXEL_DES_ADDR - Pixel Destination Address */
#define PNGDEC_DEC_PIXEL_DMA_DES_ADDR_PIXEL_DES_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_PIXEL_DMA_DES_ADDR_PIXEL_DES_ADDR_SHIFT)) & PNGDEC_DEC_PIXEL_DMA_DES_ADDR_PIXEL_DES_ADDR_MASK)
/*! @} */

/*! @name DEC_PIXEL_DMA_DES_LEN - Decode Pixel Destination Length */
/*! @{ */

#define PNGDEC_DEC_PIXEL_DMA_DES_LEN_PIXEL_DES_LEN_MASK (0xFFFFFFFFU)
#define PNGDEC_DEC_PIXEL_DMA_DES_LEN_PIXEL_DES_LEN_SHIFT (0U)
/*! PIXEL_DES_LEN - Pixel Destination Length */
#define PNGDEC_DEC_PIXEL_DMA_DES_LEN_PIXEL_DES_LEN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_PIXEL_DMA_DES_LEN_PIXEL_DES_LEN_SHIFT)) & PNGDEC_DEC_PIXEL_DMA_DES_LEN_PIXEL_DES_LEN_MASK)
/*! @} */

/*! @name DEC_ANC_DMA_DES_ADDR - Decode Ancillary Destination Address */
/*! @{ */

#define PNGDEC_DEC_ANC_DMA_DES_ADDR_ANC_DES_ADDR_MASK (0xFFFFFFFFU)
#define PNGDEC_DEC_ANC_DMA_DES_ADDR_ANC_DES_ADDR_SHIFT (0U)
/*! ANC_DES_ADDR - Ancillary Destination Address */
#define PNGDEC_DEC_ANC_DMA_DES_ADDR_ANC_DES_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_ANC_DMA_DES_ADDR_ANC_DES_ADDR_SHIFT)) & PNGDEC_DEC_ANC_DMA_DES_ADDR_ANC_DES_ADDR_MASK)
/*! @} */

/*! @name DEC_ANC_DMA_DES_LEN - Decode Ancillary Destination Length */
/*! @{ */

#define PNGDEC_DEC_ANC_DMA_DES_LEN_ANC_DES_LEN_MASK (0xFFFFFFFFU)
#define PNGDEC_DEC_ANC_DMA_DES_LEN_ANC_DES_LEN_SHIFT (0U)
/*! ANC_DES_LEN - Ancillary Destination Length */
#define PNGDEC_DEC_ANC_DMA_DES_LEN_ANC_DES_LEN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_ANC_DMA_DES_LEN_ANC_DES_LEN_SHIFT)) & PNGDEC_DEC_ANC_DMA_DES_LEN_ANC_DES_LEN_MASK)
/*! @} */

/*! @name DEC_INT_STS - Decode Interrupt Status */
/*! @{ */

#define PNGDEC_DEC_INT_STS_ERR_ADLER_MASK        (0x1U)
#define PNGDEC_DEC_INT_STS_ERR_ADLER_SHIFT       (0U)
/*! ERR_ADLER - ADLER-32 Checksum Error
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ERR_ADLER(x)          (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ERR_ADLER_SHIFT)) & PNGDEC_DEC_INT_STS_ERR_ADLER_MASK)

#define PNGDEC_DEC_INT_STS_ERR_CRC_MASK          (0x2U)
#define PNGDEC_DEC_INT_STS_ERR_CRC_SHIFT         (1U)
/*! ERR_CRC - CRC Error
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ERR_CRC(x)            (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ERR_CRC_SHIFT)) & PNGDEC_DEC_INT_STS_ERR_CRC_MASK)

#define PNGDEC_DEC_INT_STS_ERR_PNG_HEADER_MASK   (0x4U)
#define PNGDEC_DEC_INT_STS_ERR_PNG_HEADER_SHIFT  (2U)
/*! ERR_PNG_HEADER - PNG Header Error
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ERR_PNG_HEADER(x)     (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ERR_PNG_HEADER_SHIFT)) & PNGDEC_DEC_INT_STS_ERR_PNG_HEADER_MASK)

#define PNGDEC_DEC_INT_STS_ERR_BTYPE_MASK        (0x8U)
#define PNGDEC_DEC_INT_STS_ERR_BTYPE_SHIFT       (3U)
/*! ERR_BTYPE - B-type Error (Block Encoding Type Error in IDAT Chunk)
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ERR_BTYPE(x)          (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ERR_BTYPE_SHIFT)) & PNGDEC_DEC_INT_STS_ERR_BTYPE_MASK)

#define PNGDEC_DEC_INT_STS_ERR_ZLIB_HEADER_MASK  (0x10U)
#define PNGDEC_DEC_INT_STS_ERR_ZLIB_HEADER_SHIFT (4U)
/*! ERR_ZLIB_HEADER - Zlib Header Error
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ERR_ZLIB_HEADER(x)    (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ERR_ZLIB_HEADER_SHIFT)) & PNGDEC_DEC_INT_STS_ERR_ZLIB_HEADER_MASK)

#define PNGDEC_DEC_INT_STS_ERR_BITDEPTH_MASK     (0x20U)
#define PNGDEC_DEC_INT_STS_ERR_BITDEPTH_SHIFT    (5U)
/*! ERR_BITDEPTH - Bit Depth Error
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ERR_BITDEPTH(x)       (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ERR_BITDEPTH_SHIFT)) & PNGDEC_DEC_INT_STS_ERR_BITDEPTH_MASK)

#define PNGDEC_DEC_INT_STS_ERR_INTERLACE_MASK    (0x40U)
#define PNGDEC_DEC_INT_STS_ERR_INTERLACE_SHIFT   (6U)
/*! ERR_INTERLACE - Interlace Error
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ERR_INTERLACE(x)      (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ERR_INTERLACE_SHIFT)) & PNGDEC_DEC_INT_STS_ERR_INTERLACE_MASK)

#define PNGDEC_DEC_INT_STS_ERR_WIDTH_MASK        (0x80U)
#define PNGDEC_DEC_INT_STS_ERR_WIDTH_SHIFT       (7U)
/*! ERR_WIDTH - Width Error
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ERR_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ERR_WIDTH_SHIFT)) & PNGDEC_DEC_INT_STS_ERR_WIDTH_MASK)

#define PNGDEC_DEC_INT_STS_ENC_DATA_DMA_DONE_MASK (0x100U)
#define PNGDEC_DEC_INT_STS_ENC_DATA_DMA_DONE_SHIFT (8U)
/*! ENC_DATA_DMA_DONE - Encoded Data and DMA Copy Done
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_ENC_DATA_DMA_DONE(x)  (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_ENC_DATA_DMA_DONE_SHIFT)) & PNGDEC_DEC_INT_STS_ENC_DATA_DMA_DONE_MASK)

#define PNGDEC_DEC_INT_STS_DEC_PIXEL_DMA_DONE_MASK (0x200U)
#define PNGDEC_DEC_INT_STS_DEC_PIXEL_DMA_DONE_SHIFT (9U)
/*! DEC_PIXEL_DMA_DONE - Decode Pixel and DMA Copy Done
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_DEC_PIXEL_DMA_DONE(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_DEC_PIXEL_DMA_DONE_SHIFT)) & PNGDEC_DEC_INT_STS_DEC_PIXEL_DMA_DONE_MASK)

#define PNGDEC_DEC_INT_STS_DEC_ANC_DMA_DONE_MASK (0x400U)
#define PNGDEC_DEC_INT_STS_DEC_ANC_DMA_DONE_SHIFT (10U)
/*! DEC_ANC_DMA_DONE - Ancillary Decode and DMA Copy Done Flag
 *  0b0..No interrupt occurred.
 *  0b1..Interrupt occurred.
 *  0b0..No effect
 *  0b1..Clears status flag.
 */
#define PNGDEC_DEC_INT_STS_DEC_ANC_DMA_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_DEC_ANC_DMA_DONE_SHIFT)) & PNGDEC_DEC_INT_STS_DEC_ANC_DMA_DONE_MASK)
/*! @} */

/*! @name DEC_INT_STS_EN - Interrupt Enable */
/*! @{ */

#define PNGDEC_DEC_INT_STS_EN_ERR_ADLER_EN_MASK  (0x1U)
#define PNGDEC_DEC_INT_STS_EN_ERR_ADLER_EN_SHIFT (0U)
/*! ERR_ADLER_EN - ADLER-32 Checksum Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ERR_ADLER_EN(x)    (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ERR_ADLER_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ERR_ADLER_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_ERR_CRC_EN_MASK    (0x2U)
#define PNGDEC_DEC_INT_STS_EN_ERR_CRC_EN_SHIFT   (1U)
/*! ERR_CRC_EN - CRC Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ERR_CRC_EN(x)      (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ERR_CRC_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ERR_CRC_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_ERR_PNG_HEADER_EN_MASK (0x4U)
#define PNGDEC_DEC_INT_STS_EN_ERR_PNG_HEADER_EN_SHIFT (2U)
/*! ERR_PNG_HEADER_EN - PNG Header Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ERR_PNG_HEADER_EN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ERR_PNG_HEADER_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ERR_PNG_HEADER_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_ERR_BTYPE_EN_MASK  (0x8U)
#define PNGDEC_DEC_INT_STS_EN_ERR_BTYPE_EN_SHIFT (3U)
/*! ERR_BTYPE_EN - B-Type Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ERR_BTYPE_EN(x)    (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ERR_BTYPE_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ERR_BTYPE_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_ERR_ZLIB_HEADER_EN_MASK (0x10U)
#define PNGDEC_DEC_INT_STS_EN_ERR_ZLIB_HEADER_EN_SHIFT (4U)
/*! ERR_ZLIB_HEADER_EN - Zlib Header Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ERR_ZLIB_HEADER_EN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ERR_ZLIB_HEADER_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ERR_ZLIB_HEADER_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_ERR_BITDEPTH_EN_MASK (0x20U)
#define PNGDEC_DEC_INT_STS_EN_ERR_BITDEPTH_EN_SHIFT (5U)
/*! ERR_BITDEPTH_EN - Bit Depth Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ERR_BITDEPTH_EN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ERR_BITDEPTH_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ERR_BITDEPTH_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_ERR_INTERLACE_EN_MASK (0x40U)
#define PNGDEC_DEC_INT_STS_EN_ERR_INTERLACE_EN_SHIFT (6U)
/*! ERR_INTERLACE_EN - Interlace Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ERR_INTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ERR_INTERLACE_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ERR_INTERLACE_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_ERR_WIDTH_EN_MASK  (0x80U)
#define PNGDEC_DEC_INT_STS_EN_ERR_WIDTH_EN_SHIFT (7U)
/*! ERR_WIDTH_EN - Width Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ERR_WIDTH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ERR_WIDTH_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ERR_WIDTH_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_ENC_DATA_DMA_DONE_EN_MASK (0x100U)
#define PNGDEC_DEC_INT_STS_EN_ENC_DATA_DMA_DONE_EN_SHIFT (8U)
/*! ENC_DATA_DMA_DONE_EN - Encoded Data and DMA Copy Done Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_ENC_DATA_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_ENC_DATA_DMA_DONE_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_ENC_DATA_DMA_DONE_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_DEC_PIXEL_DMA_DONE_EN_MASK (0x200U)
#define PNGDEC_DEC_INT_STS_EN_DEC_PIXEL_DMA_DONE_EN_SHIFT (9U)
/*! DEC_PIXEL_DMA_DONE_EN - Decode Pixel and DMA Copy Done Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_DEC_PIXEL_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_DEC_PIXEL_DMA_DONE_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_DEC_PIXEL_DMA_DONE_EN_MASK)

#define PNGDEC_DEC_INT_STS_EN_DEC_ANC_DMA_DONE_EN_MASK (0x400U)
#define PNGDEC_DEC_INT_STS_EN_DEC_ANC_DMA_DONE_EN_SHIFT (10U)
/*! DEC_ANC_DMA_DONE_EN - Ancillary Decode and DMA Copy Done Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define PNGDEC_DEC_INT_STS_EN_DEC_ANC_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_DEC_INT_STS_EN_DEC_ANC_DMA_DONE_EN_SHIFT)) & PNGDEC_DEC_INT_STS_EN_DEC_ANC_DMA_DONE_EN_MASK)
/*! @} */

/*! @name AXI3_ENC_DATA_RD_BYTE_CNT - AXI3 Encoded Data Read Bytes Counter */
/*! @{ */

#define PNGDEC_AXI3_ENC_DATA_RD_BYTE_CNT_AXI3_ENC_RD_BYTE_MASK (0xFFFFFFFFU)
#define PNGDEC_AXI3_ENC_DATA_RD_BYTE_CNT_AXI3_ENC_RD_BYTE_SHIFT (0U)
/*! AXI3_ENC_RD_BYTE - AXI3 Encoded Data Read Bytes */
#define PNGDEC_AXI3_ENC_DATA_RD_BYTE_CNT_AXI3_ENC_RD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_AXI3_ENC_DATA_RD_BYTE_CNT_AXI3_ENC_RD_BYTE_SHIFT)) & PNGDEC_AXI3_ENC_DATA_RD_BYTE_CNT_AXI3_ENC_RD_BYTE_MASK)
/*! @} */

/*! @name AXI3_DEC_PIXEL_WR_BYTE_CNT - AXI3 Decoded Pixel Write Bytes Counter */
/*! @{ */

#define PNGDEC_AXI3_DEC_PIXEL_WR_BYTE_CNT_AXI3_PIXEL_WR_BYTE_MASK (0xFFFFFFFFU)
#define PNGDEC_AXI3_DEC_PIXEL_WR_BYTE_CNT_AXI3_PIXEL_WR_BYTE_SHIFT (0U)
/*! AXI3_PIXEL_WR_BYTE - AXI3 Pixel Write Bytes */
#define PNGDEC_AXI3_DEC_PIXEL_WR_BYTE_CNT_AXI3_PIXEL_WR_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_AXI3_DEC_PIXEL_WR_BYTE_CNT_AXI3_PIXEL_WR_BYTE_SHIFT)) & PNGDEC_AXI3_DEC_PIXEL_WR_BYTE_CNT_AXI3_PIXEL_WR_BYTE_MASK)
/*! @} */

/*! @name AXI3_DEC_ANC_WR_BYTE_CNT - AXI3 Decode Ancillary Write Bytes Counter */
/*! @{ */

#define PNGDEC_AXI3_DEC_ANC_WR_BYTE_CNT_AXI3_ANC_WR_BYTE_MASK (0xFFFFFFFFU)
#define PNGDEC_AXI3_DEC_ANC_WR_BYTE_CNT_AXI3_ANC_WR_BYTE_SHIFT (0U)
/*! AXI3_ANC_WR_BYTE - AXI3 Ancillary Write Bytes */
#define PNGDEC_AXI3_DEC_ANC_WR_BYTE_CNT_AXI3_ANC_WR_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PNGDEC_AXI3_DEC_ANC_WR_BYTE_CNT_AXI3_ANC_WR_BYTE_SHIFT)) & PNGDEC_AXI3_DEC_ANC_WR_BYTE_CNT_AXI3_ANC_WR_BYTE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PNGDEC_Register_Masks */


/* PNGDEC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PNGDEC base address */
  #define PNGDEC_BASE                              (0x500A7000u)
  /** Peripheral PNGDEC base address */
  #define PNGDEC_BASE_NS                           (0x400A7000u)
  /** Peripheral PNGDEC base pointer */
  #define PNGDEC                                   ((PNGDEC_Type *)PNGDEC_BASE)
  /** Peripheral PNGDEC base pointer */
  #define PNGDEC_NS                                ((PNGDEC_Type *)PNGDEC_BASE_NS)
  /** Array initializer of PNGDEC peripheral base addresses */
  #define PNGDEC_BASE_ADDRS                        { PNGDEC_BASE }
  /** Array initializer of PNGDEC peripheral base pointers */
  #define PNGDEC_BASE_PTRS                         { PNGDEC }
  /** Array initializer of PNGDEC peripheral base addresses */
  #define PNGDEC_BASE_ADDRS_NS                     { PNGDEC_BASE_NS }
  /** Array initializer of PNGDEC peripheral base pointers */
  #define PNGDEC_BASE_PTRS_NS                      { PNGDEC_NS }
#else
  /** Peripheral PNGDEC base address */
  #define PNGDEC_BASE                              (0x400A7000u)
  /** Peripheral PNGDEC base pointer */
  #define PNGDEC                                   ((PNGDEC_Type *)PNGDEC_BASE)
  /** Array initializer of PNGDEC peripheral base addresses */
  #define PNGDEC_BASE_ADDRS                        { PNGDEC_BASE }
  /** Array initializer of PNGDEC peripheral base pointers */
  #define PNGDEC_BASE_PTRS                         { PNGDEC }
#endif

/*!
 * @}
 */ /* end of group PNGDEC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PUF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
 * @{
 */

/** PUF - Register Layout Typedef */
typedef struct {
  __IO uint32_t CR;                                /**< Control, offset: 0x0 */
  __I  uint32_t ORR;                               /**< Operation Result, offset: 0x4 */
  __IO uint32_t SR;                                /**< Status, offset: 0x8 */
  __I  uint32_t AR;                                /**< Allow, offset: 0xC */
  __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x10 */
  __IO uint32_t IMR;                               /**< Interrupt Mask, offset: 0x14 */
  __IO uint32_t ISR;                               /**< Interrupt Status, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t DATA_DEST;                         /**< Data Destination, offset: 0x20 */
       uint8_t RESERVED_1[124];
  __O  uint32_t DIR;                               /**< Data Input, offset: 0xA0 */
       uint8_t RESERVED_2[4];
  __I  uint32_t DOR;                               /**< Data Output, offset: 0xA8 */
       uint8_t RESERVED_3[20];
  __IO uint32_t MISC;                              /**< Miscellaneous, offset: 0xC0 */
       uint8_t RESERVED_4[12];
  __IO uint32_t IF_SR;                             /**< Interface Status, offset: 0xD0 */
       uint8_t RESERVED_5[8];
  __I  uint32_t PSR;                               /**< PUF Score, offset: 0xDC */
  __I  uint32_t HW_RUC0;                           /**< Hardware Restrict User Context 0, offset: 0xE0 */
  __I  uint32_t HW_RUC1;                           /**< Hardware Restrict User Context 1, offset: 0xE4 */
       uint8_t RESERVED_6[12];
  __I  uint32_t HW_INFO;                           /**< Hardware Information, offset: 0xF4 */
  __I  uint32_t HW_ID;                             /**< Hardware Identifier, offset: 0xF8 */
  __I  uint32_t HW_VER;                            /**< Hardware Version, offset: 0xFC */
  __IO uint32_t CONFIG;                            /**< PUF command blocking configuration, offset: 0x100 */
  __IO uint32_t SEC_LOCK;                          /**< Security level lock, offset: 0x104 */
  __IO uint32_t APP_CTX_MASK;                      /**< Application defined context mask, offset: 0x108 */
  __IO uint32_t PUF_MEM_CTRL;                      /**< PUF mem control, offset: 0x10C */
} PUF_Type;

/* ----------------------------------------------------------------------------
   -- PUF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PUF_Register_Masks PUF Register Masks
 * @{
 */

/*! @name CR - Control */
/*! @{ */

#define PUF_CR_ZEROIZE_MASK                      (0x1U)
#define PUF_CR_ZEROIZE_SHIFT                     (0U)
/*! ZEROIZE - Zeroize operation
 *  0b0..Does not begin zeroize operation (disabled).
 *  0b1..Begins the zeroize operation (enabled).
 */
#define PUF_CR_ZEROIZE(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK)

#define PUF_CR_ENROLL_MASK                       (0x2U)
#define PUF_CR_ENROLL_SHIFT                      (1U)
/*! ENROLL - Enroll operation
 *  0b0..Does not begin enroll operation (disabled).
 *  0b1..Begins the enroll operation (enabled).
 */
#define PUF_CR_ENROLL(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK)

#define PUF_CR_START_MASK                        (0x4U)
#define PUF_CR_START_SHIFT                       (2U)
/*! START - Start operation
 *  0b0..Does not begin start operation (disabled).
 *  0b1..Begins the start operation (enabled).
 */
#define PUF_CR_START(x)                          (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK)

#define PUF_CR_RECONSTRUCT_MASK                  (0x8U)
#define PUF_CR_RECONSTRUCT_SHIFT                 (3U)
/*! RECONSTRUCT - Reconstruct operation
 *  0b0..Reconstruct operation disabled
 *  0b1..Reconstruct operation enabled
 */
#define PUF_CR_RECONSTRUCT(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_CR_RECONSTRUCT_SHIFT)) & PUF_CR_RECONSTRUCT_MASK)

#define PUF_CR_STOP_MASK                         (0x20U)
#define PUF_CR_STOP_SHIFT                        (5U)
/*! STOP - Stop operation
 *  0b0..Stop operation disabled
 *  0b1..Stop operation enabled
 */
#define PUF_CR_STOP(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK)

#define PUF_CR_GET_KEY_MASK                      (0x40U)
#define PUF_CR_GET_KEY_SHIFT                     (6U)
/*! GET_KEY - Get Key operation
 *  0b0..Get Key operation disabled
 *  0b1..Get Key operation enabled
 */
#define PUF_CR_GET_KEY(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK)

#define PUF_CR_UNWRAP_MASK                       (0x80U)
#define PUF_CR_UNWRAP_SHIFT                      (7U)
/*! UNWRAP - Unwrap operation
 *  0b0..Unwrap operation disabled
 *  0b1..Unwrap operation enabled
 */
#define PUF_CR_UNWRAP(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK)

#define PUF_CR_WRAP_GENERATED_RANDOM_MASK        (0x100U)
#define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT       (8U)
/*! WRAP_GENERATED_RANDOM - Wrap Generated Random operation
 *  0b0..Wrap generated random operation disabled
 *  0b1..Wrap generated random operation enabled
 */
#define PUF_CR_WRAP_GENERATED_RANDOM(x)          (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK)

#define PUF_CR_WRAP_MASK                         (0x200U)
#define PUF_CR_WRAP_SHIFT                        (9U)
/*! WRAP - Wrap operation
 *  0b0..Wrap operation disabled
 *  0b1..Wrap operation enabled
 */
#define PUF_CR_WRAP(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK)

#define PUF_CR_GENERATE_RANDOM_MASK              (0x8000U)
#define PUF_CR_GENERATE_RANDOM_SHIFT             (15U)
/*! GENERATE_RANDOM - Generate Random operation
 *  0b0..Generate Random operation disabled
 *  0b1..Generate Random operation enabled
 */
#define PUF_CR_GENERATE_RANDOM(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK)

#define PUF_CR_TEST_MEMORY_MASK                  (0x40000000U)
#define PUF_CR_TEST_MEMORY_SHIFT                 (30U)
/*! TEST_MEMORY - Test memory operation
 *  0b0..Test memory operation is disabled.
 *  0b1..Test memory operation is enabled.
 */
#define PUF_CR_TEST_MEMORY(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_MEMORY_SHIFT)) & PUF_CR_TEST_MEMORY_MASK)

#define PUF_CR_TEST_PUF_MASK                     (0x80000000U)
#define PUF_CR_TEST_PUF_SHIFT                    (31U)
/*! TEST_PUF - Test PUF operation
 *  0b0..Test PUF operation is disabled.
 *  0b1..Test PUF operation is enabled.
 */
#define PUF_CR_TEST_PUF(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK)
/*! @} */

/*! @name ORR - Operation Result */
/*! @{ */

#define PUF_ORR_RESULT_CODE_MASK                 (0xFFU)
#define PUF_ORR_RESULT_CODE_SHIFT                (0U)
/*! RESULT_CODE - Result code of last operation
 *  0b00000000..Indicates that the last operation was successful or operation is in progress.
 *  0b11110000..Indicates that the AC is not for the current product/version.
 *  0b11110001..Indicates that the AC in the second phase is not for the current product/version.
 *  0b11110010..Indicates that the AC is corrupted.
 *  0b11110011..Indicates that the AC in the second phase is corrupted.
 *  0b11110100..Indicates that the authentication of the provided AC failed.
 *  0b11110101..Indicates that the authentication of the provided AC failed in the second phase.
 *  0b11110110..Indicates that the SRAM PUF quality verification fails.
 *  0b11110111..Indicates that the incorrect or unsupported context is provided.
 *  0b11111000..Indicates that a data destination was set that is not allowed according to other settings and the current PUF state.
 *  0b11111111..Indicates that the PUF SRAM access has failed.
 */
#define PUF_ORR_RESULT_CODE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK)

#define PUF_ORR_LAST_OPERATION_MASK              (0xFF000000U)
#define PUF_ORR_LAST_OPERATION_SHIFT             (24U)
/*! LAST_OPERATION - Last operation type
 *  0b00000000..Indicates that the operation is in progress.
 *  0b00000001..Indicates that the last operation was Enroll.
 *  0b00000010..Indicates that the last operation was Start.
 *  0b00000011..Indicates that the last operation was Reconstruct
 *  0b00000101..Indicates that the last operation was Stop.
 *  0b00000110..Indicates that the last operation was Get Key.
 *  0b00000111..Indicates that the last operation was Unwrap.
 *  0b00001000..Indicates that the last operation was Wrap Generated Random.
 *  0b00001001..Indicates that the last operation was Wrap.
 *  0b00001111..Indicates that the last operation was Generate Random.
 *  0b00011110..Indicates that the last operation was Test Memory.
 *  0b00011111..Indicates that the last operation was Test PUF.
 *  0b00100000..Indicates that the last operation was Initialization.
 *  0b00101111..Indicates that the last operation was Zeroize.
 */
#define PUF_ORR_LAST_OPERATION(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK)
/*! @} */

/*! @name SR - Status */
/*! @{ */

#define PUF_SR_BUSY_MASK                         (0x1U)
#define PUF_SR_BUSY_SHIFT                        (0U)
/*! BUSY - Operation in progress
 *  0b0..Indicates no operation is performed and the hardware is idle
 *  0b1..Indicates the operation is in progress and the hardware is busy
 */
#define PUF_SR_BUSY(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK)

#define PUF_SR_OK_MASK                           (0x2U)
#define PUF_SR_OK_SHIFT                          (1U)
/*! OK - Last operation successful
 *  0b0..Resets value, no special meaning
 *  0b1..Indicates that the last operation is successful
 */
#define PUF_SR_OK(x)                             (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK)

#define PUF_SR_ERROR_MASK                        (0x4U)
#define PUF_SR_ERROR_SHIFT                       (2U)
/*! ERROR - Last operation failed
 *  0b0..Resets value, no special meaning
 *  0b1..Indicates that the last operation failed
 */
#define PUF_SR_ERROR(x)                          (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK)

#define PUF_SR_ZEROIZED_MASK                     (0x8U)
#define PUF_SR_ZEROIZED_SHIFT                    (3U)
/*! ZEROIZED - Zeroized or Locked state
 *  0b0..Indicates that the state is not locked
 *  0b1..Indicates that the state is zeroized or locked
 */
#define PUF_SR_ZEROIZED(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK)

#define PUF_SR_REJECTED_MASK                     (0x10U)
#define PUF_SR_REJECTED_SHIFT                    (4U)
/*! REJECTED - Operation rejected
 *  0b0..Indicates that the last command was not rejected
 *  0b1..Indicates that the last command was rejected
 */
#define PUF_SR_REJECTED(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK)

#define PUF_SR_DI_REQUEST_MASK                   (0x20U)
#define PUF_SR_DI_REQUEST_SHIFT                  (5U)
/*! DI_REQUEST - Indicates the request for data in transfer via the DIR register
 *  0b0..Indicates no request for data in transfer through DIR register
 *  0b1..Indicates the request for data in transfer through DIR register
 */
#define PUF_SR_DI_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK)

#define PUF_SR_DO_REQUEST_MASK                   (0x40U)
#define PUF_SR_DO_REQUEST_SHIFT                  (6U)
/*! DO_REQUEST - Indicates the request for data out transfer via the DOR register
 *  0b0..Indicates no request for data out transfer through DOR register
 *  0b1..Indicates the request for data out transfer through DOR register
 */
#define PUF_SR_DO_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK)
/*! @} */

/*! @name AR - Allow */
/*! @{ */

#define PUF_AR_ALLOW_ENROLL_MASK                 (0x2U)
#define PUF_AR_ALLOW_ENROLL_SHIFT                (1U)
/*! ALLOW_ENROLL - Enroll operation
 *  0b0..Indicates that the Enroll operation is not allowed
 *  0b1..Indicates that the Enroll operation is allowed
 */
#define PUF_AR_ALLOW_ENROLL(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK)

#define PUF_AR_ALLOW_START_MASK                  (0x4U)
#define PUF_AR_ALLOW_START_SHIFT                 (2U)
/*! ALLOW_START - Start operation
 *  0b0..Indicates that the Start operation is not allowed
 *  0b1..Indicates that the Start operation is allowed
 */
#define PUF_AR_ALLOW_START(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK)

#define PUF_AR_ALLOW_RECONSTRUCT_MASK            (0x8U)
#define PUF_AR_ALLOW_RECONSTRUCT_SHIFT           (3U)
/*! ALLOW_RECONSTRUCT - Reconstruct operation
 *  0b0..Indicates that the Reconstruct operation is not allowed
 *  0b1..Indicates that the Reconstruct operation is allowed
 */
#define PUF_AR_ALLOW_RECONSTRUCT(x)              (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_RECONSTRUCT_SHIFT)) & PUF_AR_ALLOW_RECONSTRUCT_MASK)

#define PUF_AR_ALLOW_STOP_MASK                   (0x20U)
#define PUF_AR_ALLOW_STOP_SHIFT                  (5U)
/*! ALLOW_STOP - Stop operation
 *  0b0..Indicates that the Stop operation is not allowed
 *  0b1..Indicates that the Stop operation is allowed
 */
#define PUF_AR_ALLOW_STOP(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK)

#define PUF_AR_ALLOW_GET_KEY_MASK                (0x40U)
#define PUF_AR_ALLOW_GET_KEY_SHIFT               (6U)
/*! ALLOW_GET_KEY - Get Key operation
 *  0b0..Indicates that the Get Key operation is not allowed
 *  0b1..Indicates that the Get Key operation is allowed
 */
#define PUF_AR_ALLOW_GET_KEY(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK)

#define PUF_AR_ALLOW_UNWRAP_MASK                 (0x80U)
#define PUF_AR_ALLOW_UNWRAP_SHIFT                (7U)
/*! ALLOW_UNWRAP - Unwrap operation
 *  0b0..Indicates that the Unwrap operation is not allowed
 *  0b1..Indicates that the Unwrap operation is allowed
 */
#define PUF_AR_ALLOW_UNWRAP(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK)

#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK  (0x100U)
#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U)
/*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation
 *  0b0..Indicates that the Wrap Generated Random operation is not allowed
 *  0b1..Indicates that the Wrap Generated Random operation is allowed
 */
#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x)    (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK)

#define PUF_AR_ALLOW_WRAP_MASK                   (0x200U)
#define PUF_AR_ALLOW_WRAP_SHIFT                  (9U)
/*! ALLOW_WRAP - Wrap operation
 *  0b0..Indicates that the Wrap operation is not allowed
 *  0b1..Indicates that the Wrap operation is allowed
 */
#define PUF_AR_ALLOW_WRAP(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK)

#define PUF_AR_ALLOW_GENERATE_RANDOM_MASK        (0x8000U)
#define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT       (15U)
/*! ALLOW_GENERATE_RANDOM - Generate Random operation
 *  0b0..Indicates that the Generate Random operation is not allowed
 *  0b1..Indicates that the Generate Random operation is allowed
 */
#define PUF_AR_ALLOW_GENERATE_RANDOM(x)          (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK)

#define PUF_AR_ALLOW_TEST_MEMORY_MASK            (0x40000000U)
#define PUF_AR_ALLOW_TEST_MEMORY_SHIFT           (30U)
/*! ALLOW_TEST_MEMORY
 *  0b0..Indicates that the Test Memory operation is not allowed
 *  0b1..Indicates that the Test Memory operation is allowed
 */
#define PUF_AR_ALLOW_TEST_MEMORY(x)              (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_MEMORY_SHIFT)) & PUF_AR_ALLOW_TEST_MEMORY_MASK)

#define PUF_AR_ALLOW_TEST_PUF_MASK               (0x80000000U)
#define PUF_AR_ALLOW_TEST_PUF_SHIFT              (31U)
/*! ALLOW_TEST_PUF - Test PUF operation
 *  0b0..Test PUF operation is not allowed
 *  0b1..Test PUF operation is allowed
 */
#define PUF_AR_ALLOW_TEST_PUF(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK)
/*! @} */

/*! @name IER - Interrupt Enable */
/*! @{ */

#define PUF_IER_INT_EN_MASK                      (0x1U)
#define PUF_IER_INT_EN_SHIFT                     (0U)
/*! INT_EN - Interrupt enable
 *  0b0..Disables all PUF interrupts
 *  0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register
 */
#define PUF_IER_INT_EN(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK)
/*! @} */

/*! @name IMR - Interrupt Mask */
/*! @{ */

#define PUF_IMR_INT_EN_BUSY_MASK                 (0x1U)
#define PUF_IMR_INT_EN_BUSY_SHIFT                (0U)
/*! INT_EN_BUSY - Busy interrupt
 *  0b0..Disables the busy interrupt
 *  0b1..Enables the busy interrupt
 */
#define PUF_IMR_INT_EN_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK)

#define PUF_IMR_INT_EN_OK_MASK                   (0x2U)
#define PUF_IMR_INT_EN_OK_SHIFT                  (1U)
/*! INT_EN_OK - Ok interrupt
 *  0b0..Disables the Ok interrupt
 *  0b1..Enables the Ok interrupt
 */
#define PUF_IMR_INT_EN_OK(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK)

#define PUF_IMR_INT_EN_ERROR_MASK                (0x4U)
#define PUF_IMR_INT_EN_ERROR_SHIFT               (2U)
/*! INT_EN_ERROR - Error interrupt
 *  0b0..Disables the error interrupt
 *  0b1..Enables the error interrupt
 */
#define PUF_IMR_INT_EN_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK)

#define PUF_IMR_INT_EN_ZEROIZED_MASK             (0x8U)
#define PUF_IMR_INT_EN_ZEROIZED_SHIFT            (3U)
/*! INT_EN_ZEROIZED - Zeroized interrupt
 *  0b0..Disables the zeroized interrupt
 *  0b1..Enables the zeroized interrupt
 */
#define PUF_IMR_INT_EN_ZEROIZED(x)               (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK)

#define PUF_IMR_INT_EN_REJECTED_MASK             (0x10U)
#define PUF_IMR_INT_EN_REJECTED_SHIFT            (4U)
/*! INT_EN_REJECTED - Rejected interrupt
 *  0b0..Disables the rejected interrupt
 *  0b1..Enables the rejected interrupt
 */
#define PUF_IMR_INT_EN_REJECTED(x)               (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK)

#define PUF_IMR_INT_EN_DI_REQUEST_MASK           (0x20U)
#define PUF_IMR_INT_EN_DI_REQUEST_SHIFT          (5U)
/*! INT_EN_DI_REQUEST - Data in request interrupt
 *  0b0..Disables the data in request interrupt
 *  0b1..Enables the data in request interrupt
 */
#define PUF_IMR_INT_EN_DI_REQUEST(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK)

#define PUF_IMR_INT_EN_DO_REQUEST_MASK           (0x40U)
#define PUF_IMR_INT_EN_DO_REQUEST_SHIFT          (6U)
/*! INT_EN_DO_REQUEST - Data out request interrupt
 *  0b0..Disables the data out request interrupt
 *  0b1..Enables the data out request interrupt
 */
#define PUF_IMR_INT_EN_DO_REQUEST(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK)
/*! @} */

/*! @name ISR - Interrupt Status */
/*! @{ */

#define PUF_ISR_INT_BUSY_MASK                    (0x1U)
#define PUF_ISR_INT_BUSY_SHIFT                   (0U)
/*! INT_BUSY - Negative edge occurred on Busy
 *  0b0..Does not have busy interrupt
 *  0b1..int_busy (an operation has completed) interrupt appears
 */
#define PUF_ISR_INT_BUSY(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK)

#define PUF_ISR_INT_OK_MASK                      (0x2U)
#define PUF_ISR_INT_OK_SHIFT                     (1U)
/*! INT_OK - Positive edge occurred on Ok
 *  0b0..Does not have OK interrupt
 *  0b1..int_ok (an operation has successfully completed) interrupt appears
 */
#define PUF_ISR_INT_OK(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK)

#define PUF_ISR_INT_ERROR_MASK                   (0x4U)
#define PUF_ISR_INT_ERROR_SHIFT                  (2U)
/*! INT_ERROR - Positive edge occurred on Error
 *  0b0..Does not have error interrupt
 *  0b1..int_error (an operation failed) interrupt appears
 */
#define PUF_ISR_INT_ERROR(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK)

#define PUF_ISR_INT_ZEROIZED_MASK                (0x8U)
#define PUF_ISR_INT_ZEROIZED_SHIFT               (3U)
/*! INT_ZEROIZED - Positive edge occurred on Zeroized
 *  0b0..Does not have zeroized interrupt
 *  0b1..zeroized (PUF has moved to the zeroized or locked state) interrupt appears
 */
#define PUF_ISR_INT_ZEROIZED(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK)

#define PUF_ISR_INT_REJECTED_MASK                (0x10U)
#define PUF_ISR_INT_REJECTED_SHIFT               (4U)
/*! INT_REJECTED - Positive edge occurred on Rejected
 *  0b0..Does not have rejected interrupt
 *  0b1..rejected (a command was rejected) interrupt appears
 */
#define PUF_ISR_INT_REJECTED(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK)

#define PUF_ISR_INT_DI_REQUEST_MASK              (0x20U)
#define PUF_ISR_INT_DI_REQUEST_SHIFT             (5U)
/*! INT_DI_REQUEST - Positive edge occurred on di_request
 *  0b0..Does not have di_request interrupt
 *  0b1..di_request (data in transfer is requested through the DIR register) interrupt appears
 */
#define PUF_ISR_INT_DI_REQUEST(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK)

#define PUF_ISR_INT_DO_REQUEST_MASK              (0x40U)
#define PUF_ISR_INT_DO_REQUEST_SHIFT             (6U)
/*! INT_DO_REQUEST - Positive edge occurred on do_request
 *  0b0..Does not have do_request interrupt
 *  0b1..do_request (data out transfer is requested through the DOR register) interrupt appears
 */
#define PUF_ISR_INT_DO_REQUEST(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK)
/*! @} */

/*! @name DATA_DEST - Data Destination */
/*! @{ */

#define PUF_DATA_DEST_DEST_DOR_MASK              (0x1U)
#define PUF_DATA_DEST_DEST_DOR_SHIFT             (0U)
/*! DEST_DOR - Key available via the DOR register
 *  0b0..Key is unavailable through DOR register. If DEST_DOR is set to 0, you can set DEST_SO to 1 to make key available
 *  0b1..Key is available through DOR register
 */
#define PUF_DATA_DEST_DEST_DOR(x)                (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_DOR_SHIFT)) & PUF_DATA_DEST_DEST_DOR_MASK)

#define PUF_DATA_DEST_DEST_SO_MASK               (0x2U)
#define PUF_DATA_DEST_DEST_SO_SHIFT              (1U)
/*! DEST_SO - Key available to ELS
 *  0b0..Key is unavailable through HW bus to ELS. If DEST_SO is set to 0, you can set DEST_DOR to 1 to make key available
 *  0b1..Key is available through HW bus to ELS
 */
#define PUF_DATA_DEST_DEST_SO(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_SO_SHIFT)) & PUF_DATA_DEST_DEST_SO_MASK)
/*! @} */

/*! @name DIR - Data Input */
/*! @{ */

#define PUF_DIR_DI_MASK                          (0xFFFFFFFFU)
#define PUF_DIR_DI_SHIFT                         (0U)
/*! DI - Input data */
#define PUF_DIR_DI(x)                            (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK)
/*! @} */

/*! @name DOR - Data Output */
/*! @{ */

#define PUF_DOR_DO_MASK                          (0xFFFFFFFFU)
#define PUF_DOR_DO_SHIFT                         (0U)
/*! DO - Output data */
#define PUF_DOR_DO(x)                            (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK)
/*! @} */

/*! @name MISC - Miscellaneous */
/*! @{ */

#define PUF_MISC_DATA_ENDIANNESS_MASK            (0x1U)
#define PUF_MISC_DATA_ENDIANNESS_SHIFT           (0U)
/*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR:
 *  0b0..Little endian
 *  0b1..Big endian (default)
 */
#define PUF_MISC_DATA_ENDIANNESS(x)              (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK)
/*! @} */

/*! @name IF_SR - Interface Status */
/*! @{ */

#define PUF_IF_SR_APB_ERROR_MASK                 (0x1U)
#define PUF_IF_SR_APB_ERROR_SHIFT                (0U)
/*! APB_ERROR - APB error
 *  0b0..No APB error has occurred
 *  0b1..Indicates an APB error has occurred
 */
#define PUF_IF_SR_APB_ERROR(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK)
/*! @} */

/*! @name PSR - PUF Score */
/*! @{ */

#define PUF_PSR_PUF_SCORE_MASK                   (0xFU)
#define PUF_PSR_PUF_SCORE_SHIFT                  (0U)
/*! PUF_SCORE - Provides the PUF score obtained during the last Test PUF, Enroll or Start operation. */
#define PUF_PSR_PUF_SCORE(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK)
/*! @} */

/*! @name HW_RUC0 - Hardware Restrict User Context 0 */
/*! @{ */

#define PUF_HW_RUC0_LC_STATE_MASK                (0xFFU)
#define PUF_HW_RUC0_LC_STATE_SHIFT               (0U)
/*! lc_state - Current life cycle state of the device. */
#define PUF_HW_RUC0_LC_STATE(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK)

#define PUF_HW_RUC0_BOOT_STATE_MASK              (0xFFFF00U)
#define PUF_HW_RUC0_BOOT_STATE_SHIFT             (8U)
/*! boot_state - Reflects current temporal boot status. */
#define PUF_HW_RUC0_BOOT_STATE(x)                (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK)

#define PUF_HW_RUC0_CPU0_DEBUG_MASK              (0x1000000U)
#define PUF_HW_RUC0_CPU0_DEBUG_SHIFT             (24U)
/*! cpu0_debug - Cortex-M33 (CPU0) debug status */
#define PUF_HW_RUC0_CPU0_DEBUG(x)                (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK)

#define PUF_HW_RUC0_DSP_DEBUG_MASK               (0x4000000U)
#define PUF_HW_RUC0_DSP_DEBUG_SHIFT              (26U)
/*! dsp_debug - DSP debug status.
 *  0b0..No external debugger is connected to the device at least once after power on reset has occurred
 *  0b1..Indicates an external debugger is connected to the device at least once after power on reset has occurred
 */
#define PUF_HW_RUC0_DSP_DEBUG(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_DSP_DEBUG_SHIFT)) & PUF_HW_RUC0_DSP_DEBUG_MASK)

#define PUF_HW_RUC0_ACCESS_LEVEL_MASK            (0xF0000000U)
#define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT           (28U)
/*! access_level - Reflects current TrustZone security level of the CPU. */
#define PUF_HW_RUC0_ACCESS_LEVEL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/*! @} */

/*! @name HW_RUC1 - Hardware Restrict User Context 1 */
/*! @{ */

#define PUF_HW_RUC1_APP_CTX_MASK                 (0xFFFFFFFFU)
#define PUF_HW_RUC1_APP_CTX_SHIFT                (0U)
/*! APP_CTX - Restrict user context 1 */
#define PUF_HW_RUC1_APP_CTX(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK)
/*! @} */

/*! @name HW_INFO - Hardware Information */
/*! @{ */

#define PUF_HW_INFO_CONFIG_WRAP_MASK             (0x1000000U)
#define PUF_HW_INFO_CONFIG_WRAP_SHIFT            (24U)
/*! CONFIG_WRAP - Wrap configuration
 *  0b0..Indicates that Wrap is not included
 *  0b1..Indicates that Wrap is included
 */
#define PUF_HW_INFO_CONFIG_WRAP(x)               (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK)

#define PUF_HW_INFO_CONFIG_TYPE_MASK             (0xF0000000U)
#define PUF_HW_INFO_CONFIG_TYPE_SHIFT            (28U)
/*! CONFIG_TYPE - PUF configuration
 *  0b0001..Indicates that PUF configuration is Safe.
 *  0b0010..Indicates that PUF configuration is Plus.
 */
#define PUF_HW_INFO_CONFIG_TYPE(x)               (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK)
/*! @} */

/*! @name HW_ID - Hardware Identifier */
/*! @{ */

#define PUF_HW_ID_HW_ID_MASK                     (0xFFFFFFFFU)
#define PUF_HW_ID_HW_ID_SHIFT                    (0U)
/*! HW_ID - Provides the hardware identifier. IP level has ID, which has 32 bits to record current hardware identifier */
#define PUF_HW_ID_HW_ID(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK)
/*! @} */

/*! @name HW_VER - Hardware Version */
/*! @{ */

#define PUF_HW_VER_HW_REV_MASK                   (0xFFU)
#define PUF_HW_VER_HW_REV_SHIFT                  (0U)
/*! HW_REV - Provides the hardware version, patch part */
#define PUF_HW_VER_HW_REV(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK)

#define PUF_HW_VER_HW_VERSION_MINOR_MASK         (0xFF00U)
#define PUF_HW_VER_HW_VERSION_MINOR_SHIFT        (8U)
/*! HW_VERSION_MINOR - Provides the hardware version, minor part */
#define PUF_HW_VER_HW_VERSION_MINOR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK)

#define PUF_HW_VER_HW_VERSION_MAJOR_MASK         (0xFF0000U)
#define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT        (16U)
/*! HW_VERSION_MAJOR - Provides the hardware version, major part */
#define PUF_HW_VER_HW_VERSION_MAJOR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK)
/*! @} */

/*! @name CONFIG - PUF command blocking configuration */
/*! @{ */

#define PUF_CONFIG_DIS_PUF_ENROLL_MASK           (0x2U)
#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT          (1U)
/*! DIS_PUF_ENROLL - Disable PUF enroll command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_ENROLL(x)             (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK)

#define PUF_CONFIG_DIS_PUF_START_MASK            (0x4U)
#define PUF_CONFIG_DIS_PUF_START_SHIFT           (2U)
/*! DIS_PUF_START - Disable PUF start command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_START(x)              (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK)

#define PUF_CONFIG_DIS_PUF_RECONSTRUCT_MASK      (0x8U)
#define PUF_CONFIG_DIS_PUF_RECONSTRUCT_SHIFT     (3U)
/*! DIS_PUF_RECONSTRUCT - Disable PUF reconstruct command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_RECONSTRUCT(x)        (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_RECONSTRUCT_SHIFT)) & PUF_CONFIG_DIS_PUF_RECONSTRUCT_MASK)

#define PUF_CONFIG_DIS_PUF_STOP_MASK             (0x20U)
#define PUF_CONFIG_DIS_PUF_STOP_SHIFT            (5U)
/*! DIS_PUF_STOP - Disable PUF stop command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_STOP(x)               (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK)

#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK          (0x40U)
#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT         (6U)
/*! DIS_PUF_GET_KEY - Disable PUF get key command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_GET_KEY(x)            (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK)

#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK       (0x80U)
#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT      (7U)
/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK)

#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK     (0x100U)
#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT    (8U)
/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x)       (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK)

#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK         (0x200U)
#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT        (9U)
/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x)           (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK)

#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U)
#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U)
/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command
 *  0b0..Command enabled
 *  0b1..Command disabled
 */
#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x)  (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK)

#define PUF_CONFIG_DIS_PUF_TEST_MEMORY_MASK      (0x40000000U)
#define PUF_CONFIG_DIS_PUF_TEST_MEMORY_SHIFT     (30U)
/*! DIS_PUF_TEST_MEMORY - Disable PUF test memory command */
#define PUF_CONFIG_DIS_PUF_TEST_MEMORY(x)        (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_MEMORY_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MEMORY_MASK)

#define PUF_CONFIG_DIS_PUF_TEST_MASK             (0x80000000U)
#define PUF_CONFIG_DIS_PUF_TEST_SHIFT            (31U)
/*! DIS_PUF_TEST - Disable PUF test command */
#define PUF_CONFIG_DIS_PUF_TEST(x)               (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK)
/*! @} */

/*! @name SEC_LOCK - Security level lock */
/*! @{ */

#define PUF_SEC_LOCK_SEC_LEVEL_MASK              (0x3U)
#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT             (0U)
/*! SEC_LEVEL - Security Level
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define PUF_SEC_LOCK_SEC_LEVEL(x)                (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK)

#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK    (0xCU)
#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT   (2U)
/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level
 *  0b11..Non-secure and non-privileged Master
 *  0b10..Non-secure and privileged Master
 *  0b01..Secure and non-privileged Master
 *  0b00..Secure and privileged Master
 */
#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x)      (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK)

#define PUF_SEC_LOCK_PATTERN_MASK                (0xFFF0U)
#define PUF_SEC_LOCK_PATTERN_SHIFT               (4U)
/*! PATTERN - Pattern */
#define PUF_SEC_LOCK_PATTERN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK)
/*! @} */

/*! @name APP_CTX_MASK - Application defined context mask */
/*! @{ */

#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK       (0xFFFFFFFFU)
#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT      (0U)
/*! APP_CTX_MASK - Application defined context */
#define PUF_APP_CTX_MASK_APP_CTX_MASK(x)         (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK)
/*! @} */

/*! @name PUF_MEM_CTRL - PUF mem control */
/*! @{ */

#define PUF_PUF_MEM_CTRL_POWERON_MASK            (0x1U)
#define PUF_PUF_MEM_CTRL_POWERON_SHIFT           (0U)
/*! POWERON - PUF mem power on
 *  0b0..PUF mem power off
 *  0b1..PUF mem power on
 */
#define PUF_PUF_MEM_CTRL_POWERON(x)              (((uint32_t)(((uint32_t)(x)) << PUF_PUF_MEM_CTRL_POWERON_SHIFT)) & PUF_PUF_MEM_CTRL_POWERON_MASK)

#define PUF_PUF_MEM_CTRL_CLK_GATE_EN_MASK        (0x2U)
#define PUF_PUF_MEM_CTRL_CLK_GATE_EN_SHIFT       (1U)
/*! CLK_GATE_EN - PUF mem clock gating enable
 *  0b1..PUF mem clock is gated by chip select
 *  0b0..PUF mem clock gating disable
 */
#define PUF_PUF_MEM_CTRL_CLK_GATE_EN(x)          (((uint32_t)(((uint32_t)(x)) << PUF_PUF_MEM_CTRL_CLK_GATE_EN_SHIFT)) & PUF_PUF_MEM_CTRL_CLK_GATE_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PUF_Register_Masks */


/* PUF - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PUF base address */
  #define PUF_BASE                                 (0x50194000u)
  /** Peripheral PUF base address */
  #define PUF_BASE_NS                              (0x40194000u)
  /** Peripheral PUF base pointer */
  #define PUF                                      ((PUF_Type *)PUF_BASE)
  /** Peripheral PUF base pointer */
  #define PUF_NS                                   ((PUF_Type *)PUF_BASE_NS)
  /** Peripheral PUF_ALIAS1 base address */
  #define PUF_ALIAS1_BASE                          (0x50195000u)
  /** Peripheral PUF_ALIAS1 base address */
  #define PUF_ALIAS1_BASE_NS                       (0x40195000u)
  /** Peripheral PUF_ALIAS1 base pointer */
  #define PUF_ALIAS1                               ((PUF_Type *)PUF_ALIAS1_BASE)
  /** Peripheral PUF_ALIAS1 base pointer */
  #define PUF_ALIAS1_NS                            ((PUF_Type *)PUF_ALIAS1_BASE_NS)
  /** Peripheral PUF_ALIAS2 base address */
  #define PUF_ALIAS2_BASE                          (0x50196000u)
  /** Peripheral PUF_ALIAS2 base address */
  #define PUF_ALIAS2_BASE_NS                       (0x40196000u)
  /** Peripheral PUF_ALIAS2 base pointer */
  #define PUF_ALIAS2                               ((PUF_Type *)PUF_ALIAS2_BASE)
  /** Peripheral PUF_ALIAS2 base pointer */
  #define PUF_ALIAS2_NS                            ((PUF_Type *)PUF_ALIAS2_BASE_NS)
  /** Peripheral PUF_ALIAS3 base address */
  #define PUF_ALIAS3_BASE                          (0x50197000u)
  /** Peripheral PUF_ALIAS3 base address */
  #define PUF_ALIAS3_BASE_NS                       (0x40197000u)
  /** Peripheral PUF_ALIAS3 base pointer */
  #define PUF_ALIAS3                               ((PUF_Type *)PUF_ALIAS3_BASE)
  /** Peripheral PUF_ALIAS3 base pointer */
  #define PUF_ALIAS3_NS                            ((PUF_Type *)PUF_ALIAS3_BASE_NS)
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS                           { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS                            { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_NS                        { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_NS                         { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS }
#else
  /** Peripheral PUF base address */
  #define PUF_BASE                                 (0x40194000u)
  /** Peripheral PUF base pointer */
  #define PUF                                      ((PUF_Type *)PUF_BASE)
  /** Peripheral PUF_ALIAS1 base address */
  #define PUF_ALIAS1_BASE                          (0x40195000u)
  /** Peripheral PUF_ALIAS1 base pointer */
  #define PUF_ALIAS1                               ((PUF_Type *)PUF_ALIAS1_BASE)
  /** Peripheral PUF_ALIAS2 base address */
  #define PUF_ALIAS2_BASE                          (0x40196000u)
  /** Peripheral PUF_ALIAS2 base pointer */
  #define PUF_ALIAS2                               ((PUF_Type *)PUF_ALIAS2_BASE)
  /** Peripheral PUF_ALIAS3 base address */
  #define PUF_ALIAS3_BASE                          (0x40197000u)
  /** Peripheral PUF_ALIAS3 base pointer */
  #define PUF_ALIAS3                               ((PUF_Type *)PUF_ALIAS3_BASE)
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS                           { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS                            { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 }
#endif

/*!
 * @}
 */ /* end of group PUF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PVTS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PVTS_Peripheral_Access_Layer PVTS Peripheral Access Layer
 * @{
 */

/** PVTS - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x80 */
    __IO uint32_t RED_DEL_CTRL;                      /**< Red Delay Control, array offset: 0x0, array step: 0x80 */
         uint8_t RESERVED_0[8];
    __IO uint32_t RED_ALERT_CNT;                     /**< Red Alert Counter, array offset: 0xC, array step: 0x80 */
    __IO uint32_t RED_ALERT_CNT_CTRL;                /**< Red Alert Counter Control, array offset: 0x10, array step: 0x80 */
         uint8_t RESERVED_1[12];
    __IO uint32_t AMBER_DEL_CTRL;                    /**< Amber Delay Control, array offset: 0x20, array step: 0x80 */
    __IO uint32_t AMBER_RING_OSC_CTRL;               /**< Amber Ring OSC Control, array offset: 0x24, array step: 0x80 */
    __I  uint32_t AMBER_RING_CNT;                    /**< Amber Ring OSC Counter, array offset: 0x28, array step: 0x80 */
    __IO uint32_t AMBER_ALERT_CNT;                   /**< Amber Alert Counter, array offset: 0x2C, array step: 0x80 */
    __IO uint32_t AMBER_ALERT_CNT_CTRL;              /**< Amber Alert Counter Control, array offset: 0x30, array step: 0x80 */
         uint8_t RESERVED_2[76];
  } PVT[2];
} PVTS_Type;

/* ----------------------------------------------------------------------------
   -- PVTS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PVTS_Register_Masks PVTS Register Masks
 * @{
 */

/*! @name RED_DEL_CTRL - Red Delay Control */
/*! @{ */

#define PVTS_RED_DEL_CTRL_DELAY0_MASK            (0x1FU)
#define PVTS_RED_DEL_CTRL_DELAY0_SHIFT           (0U)
/*! DELAY0 - Red Delay Section 0 */
#define PVTS_RED_DEL_CTRL_DELAY0(x)              (((uint32_t)(((uint32_t)(x)) << PVTS_RED_DEL_CTRL_DELAY0_SHIFT)) & PVTS_RED_DEL_CTRL_DELAY0_MASK)

#define PVTS_RED_DEL_CTRL_DELAY1_MASK            (0x3E0U)
#define PVTS_RED_DEL_CTRL_DELAY1_SHIFT           (5U)
/*! DELAY1 - Red Delay Section 1 */
#define PVTS_RED_DEL_CTRL_DELAY1(x)              (((uint32_t)(((uint32_t)(x)) << PVTS_RED_DEL_CTRL_DELAY1_SHIFT)) & PVTS_RED_DEL_CTRL_DELAY1_MASK)
/*! @} */

/* The count of PVTS_RED_DEL_CTRL */
#define PVTS_RED_DEL_CTRL_COUNT                  (2U)

/*! @name RED_ALERT_CNT - Red Alert Counter */
/*! @{ */

#define PVTS_RED_ALERT_CNT_CNT_MASK              (0xFFFFFU)
#define PVTS_RED_ALERT_CNT_CNT_SHIFT             (0U)
/*! CNT - Counter */
#define PVTS_RED_ALERT_CNT_CNT(x)                (((uint32_t)(((uint32_t)(x)) << PVTS_RED_ALERT_CNT_CNT_SHIFT)) & PVTS_RED_ALERT_CNT_CNT_MASK)
/*! @} */

/* The count of PVTS_RED_ALERT_CNT */
#define PVTS_RED_ALERT_CNT_COUNT                 (2U)

/*! @name RED_ALERT_CNT_CTRL - Red Alert Counter Control */
/*! @{ */

#define PVTS_RED_ALERT_CNT_CTRL_CNTEN_MASK       (0x1U)
#define PVTS_RED_ALERT_CNT_CTRL_CNTEN_SHIFT      (0U)
/*! CNTEN - Counter Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PVTS_RED_ALERT_CNT_CTRL_CNTEN(x)         (((uint32_t)(((uint32_t)(x)) << PVTS_RED_ALERT_CNT_CTRL_CNTEN_SHIFT)) & PVTS_RED_ALERT_CNT_CTRL_CNTEN_MASK)
/*! @} */

/* The count of PVTS_RED_ALERT_CNT_CTRL */
#define PVTS_RED_ALERT_CNT_CTRL_COUNT            (2U)

/*! @name AMBER_DEL_CTRL - Amber Delay Control */
/*! @{ */

#define PVTS_AMBER_DEL_CTRL_DELAY0_MASK          (0x1FU)
#define PVTS_AMBER_DEL_CTRL_DELAY0_SHIFT         (0U)
/*! DELAY0 - Amber Delay Section 0 */
#define PVTS_AMBER_DEL_CTRL_DELAY0(x)            (((uint32_t)(((uint32_t)(x)) << PVTS_AMBER_DEL_CTRL_DELAY0_SHIFT)) & PVTS_AMBER_DEL_CTRL_DELAY0_MASK)

#define PVTS_AMBER_DEL_CTRL_DELAY1_MASK          (0x3E0U)
#define PVTS_AMBER_DEL_CTRL_DELAY1_SHIFT         (5U)
/*! DELAY1 - Amber Delay Section 1 */
#define PVTS_AMBER_DEL_CTRL_DELAY1(x)            (((uint32_t)(((uint32_t)(x)) << PVTS_AMBER_DEL_CTRL_DELAY1_SHIFT)) & PVTS_AMBER_DEL_CTRL_DELAY1_MASK)
/*! @} */

/* The count of PVTS_AMBER_DEL_CTRL */
#define PVTS_AMBER_DEL_CTRL_COUNT                (2U)

/*! @name AMBER_RING_OSC_CTRL - Amber Ring OSC Control */
/*! @{ */

#define PVTS_AMBER_RING_OSC_CTRL_RINGOSCEN_MASK  (0x1U)
#define PVTS_AMBER_RING_OSC_CTRL_RINGOSCEN_SHIFT (0U)
/*! RINGOSCEN - Amber Ring Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PVTS_AMBER_RING_OSC_CTRL_RINGOSCEN(x)    (((uint32_t)(((uint32_t)(x)) << PVTS_AMBER_RING_OSC_CTRL_RINGOSCEN_SHIFT)) & PVTS_AMBER_RING_OSC_CTRL_RINGOSCEN_MASK)

#define PVTS_AMBER_RING_OSC_CTRL_CNTEN_MASK      (0x2U)
#define PVTS_AMBER_RING_OSC_CTRL_CNTEN_SHIFT     (1U)
/*! CNTEN - Amber Ring OSC Counter Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PVTS_AMBER_RING_OSC_CTRL_CNTEN(x)        (((uint32_t)(((uint32_t)(x)) << PVTS_AMBER_RING_OSC_CTRL_CNTEN_SHIFT)) & PVTS_AMBER_RING_OSC_CTRL_CNTEN_MASK)

#define PVTS_AMBER_RING_OSC_CTRL_CNTRST_MASK     (0x4U)
#define PVTS_AMBER_RING_OSC_CTRL_CNTRST_SHIFT    (2U)
/*! CNTRST - Amber Ring OSC Counter Reset
 *  0b0..Not resets
 *  0b1..Resets
 */
#define PVTS_AMBER_RING_OSC_CTRL_CNTRST(x)       (((uint32_t)(((uint32_t)(x)) << PVTS_AMBER_RING_OSC_CTRL_CNTRST_SHIFT)) & PVTS_AMBER_RING_OSC_CTRL_CNTRST_MASK)
/*! @} */

/* The count of PVTS_AMBER_RING_OSC_CTRL */
#define PVTS_AMBER_RING_OSC_CTRL_COUNT           (2U)

/*! @name AMBER_RING_CNT - Amber Ring OSC Counter */
/*! @{ */

#define PVTS_AMBER_RING_CNT_CNT_MASK             (0xFFFFFFFFU)
#define PVTS_AMBER_RING_CNT_CNT_SHIFT            (0U)
/*! CNT - Counter */
#define PVTS_AMBER_RING_CNT_CNT(x)               (((uint32_t)(((uint32_t)(x)) << PVTS_AMBER_RING_CNT_CNT_SHIFT)) & PVTS_AMBER_RING_CNT_CNT_MASK)
/*! @} */

/* The count of PVTS_AMBER_RING_CNT */
#define PVTS_AMBER_RING_CNT_COUNT                (2U)

/*! @name AMBER_ALERT_CNT - Amber Alert Counter */
/*! @{ */

#define PVTS_AMBER_ALERT_CNT_CNT_MASK            (0xFFFFFU)
#define PVTS_AMBER_ALERT_CNT_CNT_SHIFT           (0U)
/*! CNT - Counter */
#define PVTS_AMBER_ALERT_CNT_CNT(x)              (((uint32_t)(((uint32_t)(x)) << PVTS_AMBER_ALERT_CNT_CNT_SHIFT)) & PVTS_AMBER_ALERT_CNT_CNT_MASK)
/*! @} */

/* The count of PVTS_AMBER_ALERT_CNT */
#define PVTS_AMBER_ALERT_CNT_COUNT               (2U)

/*! @name AMBER_ALERT_CNT_CTRL - Amber Alert Counter Control */
/*! @{ */

#define PVTS_AMBER_ALERT_CNT_CTRL_CNTEN_MASK     (0x1U)
#define PVTS_AMBER_ALERT_CNT_CTRL_CNTEN_SHIFT    (0U)
/*! CNTEN - Counter Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define PVTS_AMBER_ALERT_CNT_CTRL_CNTEN(x)       (((uint32_t)(((uint32_t)(x)) << PVTS_AMBER_ALERT_CNT_CTRL_CNTEN_SHIFT)) & PVTS_AMBER_ALERT_CNT_CTRL_CNTEN_MASK)
/*! @} */

/* The count of PVTS_AMBER_ALERT_CNT_CTRL */
#define PVTS_AMBER_ALERT_CNT_CTRL_COUNT          (2U)


/*!
 * @}
 */ /* end of group PVTS_Register_Masks */


/* PVTS - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PVTS0 base address */
  #define PVTS0_BASE                               (0x50005000u)
  /** Peripheral PVTS0 base address */
  #define PVTS0_BASE_NS                            (0x40005000u)
  /** Peripheral PVTS0 base pointer */
  #define PVTS0                                    ((PVTS_Type *)PVTS0_BASE)
  /** Peripheral PVTS0 base pointer */
  #define PVTS0_NS                                 ((PVTS_Type *)PVTS0_BASE_NS)
  /** Array initializer of PVTS peripheral base addresses */
  #define PVTS_BASE_ADDRS                          { PVTS0_BASE }
  /** Array initializer of PVTS peripheral base pointers */
  #define PVTS_BASE_PTRS                           { PVTS0 }
  /** Array initializer of PVTS peripheral base addresses */
  #define PVTS_BASE_ADDRS_NS                       { PVTS0_BASE_NS }
  /** Array initializer of PVTS peripheral base pointers */
  #define PVTS_BASE_PTRS_NS                        { PVTS0_NS }
#else
  /** Peripheral PVTS0 base address */
  #define PVTS0_BASE                               (0x40005000u)
  /** Peripheral PVTS0 base pointer */
  #define PVTS0                                    ((PVTS_Type *)PVTS0_BASE)
  /** Array initializer of PVTS peripheral base addresses */
  #define PVTS_BASE_ADDRS                          { PVTS0_BASE }
  /** Array initializer of PVTS peripheral base pointers */
  #define PVTS_BASE_PTRS                           { PVTS0 }
#endif

/*!
 * @}
 */ /* end of group PVTS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ROMCP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ROMCP_Peripheral_Access_Layer ROMCP Peripheral Access Layer
 * @{
 */

/** ROMCP - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[180];
  __IO uint32_t ROMPATCHD[16];                     /**< Data Registers, array offset: 0xB4, array step: 0x4 */
  __IO uint32_t ROMPATCHCNTL;                      /**< Control Register, offset: 0xF4 */
       uint32_t ROMPATCHENH;                       /**< Enable Register High, offset: 0xF8 */
  __IO uint32_t ROMPATCHENL;                       /**< Enable Register Low, offset: 0xFC */
  __IO uint32_t ROMPATCHA[32];                     /**< Address Registers, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[136];
  __IO uint32_t ROMPATCHSR;                        /**< Status Register, offset: 0x208 */
} ROMCP_Type;

/* ----------------------------------------------------------------------------
   -- ROMCP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ROMCP_Register_Masks ROMCP Register Masks
 * @{
 */

/*! @name ROMPATCHD - Data Registers */
/*! @{ */

#define ROMCP_ROMPATCHD_DATAX_MASK               (0xFFFFFFFFU)
#define ROMCP_ROMPATCHD_DATAX_SHIFT              (0U)
/*! DATAX - Data Fix Registers */
#define ROMCP_ROMPATCHD_DATAX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHD_DATAX_SHIFT)) & ROMCP_ROMPATCHD_DATAX_MASK)
/*! @} */

/* The count of ROMCP_ROMPATCHD */
#define ROMCP_ROMPATCHD_COUNT                    (16U)

/*! @name ROMPATCHCNTL - Control Register */
/*! @{ */

#define ROMCP_ROMPATCHCNTL_DATAFIX0_MASK         (0x1U)
#define ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT        (0U)
/*! DATAFIX0 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX0(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX0_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX1_MASK         (0x2U)
#define ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT        (1U)
/*! DATAFIX1 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX1(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX1_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX2_MASK         (0x4U)
#define ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT        (2U)
/*! DATAFIX2 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX2(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX2_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX3_MASK         (0x8U)
#define ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT        (3U)
/*! DATAFIX3 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX3(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX3_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX4_MASK         (0x10U)
#define ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT        (4U)
/*! DATAFIX4 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX4(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX4_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX5_MASK         (0x20U)
#define ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT        (5U)
/*! DATAFIX5 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX5(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX5_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX6_MASK         (0x40U)
#define ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT        (6U)
/*! DATAFIX6 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX6(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX6_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX7_MASK         (0x80U)
#define ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT        (7U)
/*! DATAFIX7 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX7(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX7_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX8_MASK         (0x100U)
#define ROMCP_ROMPATCHCNTL_DATAFIX8_SHIFT        (8U)
/*! DATAFIX8 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX8(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX8_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX8_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX9_MASK         (0x200U)
#define ROMCP_ROMPATCHCNTL_DATAFIX9_SHIFT        (9U)
/*! DATAFIX9 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX9(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX9_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX9_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX10_MASK        (0x400U)
#define ROMCP_ROMPATCHCNTL_DATAFIX10_SHIFT       (10U)
/*! DATAFIX10 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX10(x)          (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX10_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX10_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX11_MASK        (0x800U)
#define ROMCP_ROMPATCHCNTL_DATAFIX11_SHIFT       (11U)
/*! DATAFIX11 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX11(x)          (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX11_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX11_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX12_MASK        (0x1000U)
#define ROMCP_ROMPATCHCNTL_DATAFIX12_SHIFT       (12U)
/*! DATAFIX12 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX12(x)          (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX12_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX12_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX13_MASK        (0x2000U)
#define ROMCP_ROMPATCHCNTL_DATAFIX13_SHIFT       (13U)
/*! DATAFIX13 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX13(x)          (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX13_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX13_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX14_MASK        (0x4000U)
#define ROMCP_ROMPATCHCNTL_DATAFIX14_SHIFT       (14U)
/*! DATAFIX14 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX14(x)          (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX14_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX14_MASK)

#define ROMCP_ROMPATCHCNTL_DATAFIX15_MASK        (0x8000U)
#define ROMCP_ROMPATCHCNTL_DATAFIX15_SHIFT       (15U)
/*! DATAFIX15 - Data Fix Enable
 *  0b0..Trigger an opcode patch
 *  0b1..Trigger a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX15(x)          (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX15_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX15_MASK)

#define ROMCP_ROMPATCHCNTL_DIS_MASK              (0x20000000U)
#define ROMCP_ROMPATCHCNTL_DIS_SHIFT             (29U)
/*! DIS - Patch Disable
 *  0b0..Does not affect any Patch operations (default)
 *  0b1..Disables all Patch operations: data fixing and opcode patching
 */
#define ROMCP_ROMPATCHCNTL_DIS(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DIS_SHIFT)) & ROMCP_ROMPATCHCNTL_DIS_MASK)

#define ROMCP_ROMPATCHCNTL_LK_MASK               (0x80000000U)
#define ROMCP_ROMPATCHCNTL_LK_SHIFT              (31U)
/*! LK - Register Lock
 *  0b0..All registers remain accessible (unlocked).
 *  0b1..Lock access to all registers. All ROMCP register accesses are treated as read-as-zero, except for this LK
 *       bit which reads as set. All writes are ignored.
 */
#define ROMCP_ROMPATCHCNTL_LK(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_LK_SHIFT)) & ROMCP_ROMPATCHCNTL_LK_MASK)
/*! @} */

/*! @name ROMPATCHENL - Enable Register Low */
/*! @{ */

#define ROMCP_ROMPATCHENL_ENABLE_MASK            (0xFFFFFFFFU)
#define ROMCP_ROMPATCHENL_ENABLE_SHIFT           (0U)
/*! ENABLE - Enable Address Comparator
 *  0b00000000000000000000000000000000..Address comparator is disabled
 *  0b00000000000000000000000000000001..Address comparator is enabled; after the associated address is matched, the ROMC will trigger a opcode patch or data fix event.
 */
#define ROMCP_ROMPATCHENL_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE_MASK)
/*! @} */

/*! @name ROMPATCHA - Address Registers */
/*! @{ */

#define ROMCP_ROMPATCHA_THUMBX_MASK              (0x1U)
#define ROMCP_ROMPATCHA_THUMBX_SHIFT             (0U)
/*! THUMBX - THUMB Comparator Select
 *  0b0..ARM patch
 *  0b1..THUMB patch (ignore if a data fix)
 */
#define ROMCP_ROMPATCHA_THUMBX(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_THUMBX_SHIFT)) & ROMCP_ROMPATCHA_THUMBX_MASK)

#define ROMCP_ROMPATCHA_ADDRX_MASK               (0x7FFFFEU)
#define ROMCP_ROMPATCHA_ADDRX_SHIFT              (1U)
/*! ADDRX - Address Comparator Registers */
#define ROMCP_ROMPATCHA_ADDRX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_ADDRX_SHIFT)) & ROMCP_ROMPATCHA_ADDRX_MASK)
/*! @} */

/* The count of ROMCP_ROMPATCHA */
#define ROMCP_ROMPATCHA_COUNT                    (32U)

/*! @name ROMPATCHSR - Status Register */
/*! @{ */

#define ROMCP_ROMPATCHSR_SOURCE_MASK             (0x3FU)
#define ROMCP_ROMPATCHSR_SOURCE_SHIFT            (0U)
/*! SOURCE - ROMCP Source Number
 *  0b000000..Address Comparator 0 matched
 *  0b000001..Address Comparator 1 matched
 *  0b001111..Address Comparator 15 matched
 */
#define ROMCP_ROMPATCHSR_SOURCE(x)               (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SOURCE_SHIFT)) & ROMCP_ROMPATCHSR_SOURCE_MASK)

#define ROMCP_ROMPATCHSR_SW_MASK                 (0x20000U)
#define ROMCP_ROMPATCHSR_SW_SHIFT                (17U)
/*! SW - ROMCP AHB Multiple Address Comparator Match Indicator
 *  0b0..No event or comparator collisions have occurred
 *  0b1..A collision has occurred
 */
#define ROMCP_ROMPATCHSR_SW(x)                   (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SW_SHIFT)) & ROMCP_ROMPATCHSR_SW_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ROMCP_Register_Masks */


/* ROMCP - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ROMCP base address */
  #define ROMCP_BASE                               (0x50182000u)
  /** Peripheral ROMCP base address */
  #define ROMCP_BASE_NS                            (0x40182000u)
  /** Peripheral ROMCP base pointer */
  #define ROMCP                                    ((ROMCP_Type *)ROMCP_BASE)
  /** Peripheral ROMCP base pointer */
  #define ROMCP_NS                                 ((ROMCP_Type *)ROMCP_BASE_NS)
  /** Array initializer of ROMCP peripheral base addresses */
  #define ROMCP_BASE_ADDRS                         { ROMCP_BASE }
  /** Array initializer of ROMCP peripheral base pointers */
  #define ROMCP_BASE_PTRS                          { ROMCP }
  /** Array initializer of ROMCP peripheral base addresses */
  #define ROMCP_BASE_ADDRS_NS                      { ROMCP_BASE_NS }
  /** Array initializer of ROMCP peripheral base pointers */
  #define ROMCP_BASE_PTRS_NS                       { ROMCP_NS }
#else
  /** Peripheral ROMCP base address */
  #define ROMCP_BASE                               (0x40182000u)
  /** Peripheral ROMCP base pointer */
  #define ROMCP                                    ((ROMCP_Type *)ROMCP_BASE)
  /** Array initializer of ROMCP peripheral base addresses */
  #define ROMCP_BASE_ADDRS                         { ROMCP_BASE }
  /** Array initializer of ROMCP peripheral base pointers */
  #define ROMCP_BASE_PTRS                          { ROMCP }
#endif

/*!
 * @}
 */ /* end of group ROMCP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RSTCTL0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL0_Peripheral_Access_Layer RSTCTL0 Peripheral Access Layer
 * @{
 */

/** RSTCTL0 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4];
  __I  uint32_t DOMRSTSTAT;                        /**< Domain Reset Status, offset: 0x4 */
       uint8_t RESERVED_1[8];
  __IO uint32_t PRSTCTL0;                          /**< Common Domain Peripheral Reset Control 0, offset: 0x10 */
  __IO uint32_t PRSTCTL1;                          /**< Compute Domain Peripheral Reset Control 1, offset: 0x14 */
  __IO uint32_t PRSTCTL2;                          /**< Compute Domain Peripheral Reset Control 2, offset: 0x18 */
  __IO uint32_t PRSTCTL3;                          /**< Compute Domain Peripheral Reset Control 3, offset: 0x1C */
  __IO uint32_t PRSTCTL4;                          /**< Compute Domain Peripheral Reset Control 4, offset: 0x20 */
  __IO uint32_t PRSTCTL5;                          /**< DSP Domain Peripheral Reset Control 5, offset: 0x24 */
       uint8_t RESERVED_2[24];
  __O  uint32_t PRSTCTL0_SET;                      /**< Common Domain Peripheral Reset Control 0 SET, offset: 0x40 */
  __O  uint32_t PRSTCTL1_SET;                      /**< Compute Domain Peripheral Reset Control 1 SET, offset: 0x44 */
  __O  uint32_t PRSTCTL2_SET;                      /**< Compute Domain Peripheral Reset Control 2 SET, offset: 0x48 */
  __O  uint32_t PRSTCTL3_SET;                      /**< Compute Domain Peripheral Reset Control 3 SET, offset: 0x4C */
  __O  uint32_t PRSTCTL4_SET;                      /**< Compute Domain Peripheral Reset Control 4 SET, offset: 0x50 */
  __O  uint32_t PRSTCTL5_SET;                      /**< DSP Domain Peripheral Reset Control 5 SET, offset: 0x54 */
       uint8_t RESERVED_3[24];
  __O  uint32_t PRSTCTL0_CLR;                      /**< Common Domain Peripheral Reset Control 0 CLR, offset: 0x70 */
  __O  uint32_t PRSTCTL1_CLR;                      /**< Compute Domain Peripheral Reset Control 1 CLR, offset: 0x74 */
  __O  uint32_t PRSTCTL2_CLR;                      /**< Compute Domain Peripheral Reset Control 2 CLR, offset: 0x78 */
  __O  uint32_t PRSTCTL3_CLR;                      /**< Compute Domain Peripheral Reset Control 3 CLR, offset: 0x7C */
  __O  uint32_t PRSTCTL4_CLR;                      /**< Compute Domain Peripheral Reset Control 4 CLR, offset: 0x80 */
  __O  uint32_t PRSTCTL5_CLR;                      /**< DSP Domain Peripheral Reset Control 5 CLR, offset: 0x84 */
} RSTCTL0_Type;

/* ----------------------------------------------------------------------------
   -- RSTCTL0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL0_Register_Masks RSTCTL0 Register Masks
 * @{
 */

/*! @name DOMRSTSTAT - Domain Reset Status */
/*! @{ */

#define RSTCTL0_DOMRSTSTAT_SENSE_STAT_MASK       (0x1U)
#define RSTCTL0_DOMRSTSTAT_SENSE_STAT_SHIFT      (0U)
/*! SENSE_STAT - VDD1_SENSE Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL0_DOMRSTSTAT_SENSE_STAT(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_DOMRSTSTAT_SENSE_STAT_SHIFT)) & RSTCTL0_DOMRSTSTAT_SENSE_STAT_MASK)

#define RSTCTL0_DOMRSTSTAT_COM2_STAT_MASK        (0x2U)
#define RSTCTL0_DOMRSTSTAT_COM2_STAT_SHIFT       (1U)
/*! COM2_STAT - VDD2_COM (Main) Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL0_DOMRSTSTAT_COM2_STAT(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_DOMRSTSTAT_COM2_STAT_SHIFT)) & RSTCTL0_DOMRSTSTAT_COM2_STAT_MASK)

#define RSTCTL0_DOMRSTSTAT_COMN_STAT_MASK        (0x4U)
#define RSTCTL0_DOMRSTSTAT_COMN_STAT_SHIFT       (2U)
/*! COMN_STAT - VDDN_COM Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL0_DOMRSTSTAT_COMN_STAT(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_DOMRSTSTAT_COMN_STAT_SHIFT)) & RSTCTL0_DOMRSTSTAT_COMN_STAT_MASK)

#define RSTCTL0_DOMRSTSTAT_COMP_STAT_MASK        (0x8U)
#define RSTCTL0_DOMRSTSTAT_COMP_STAT_SHIFT       (3U)
/*! COMP_STAT - VDD2_COMP Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL0_DOMRSTSTAT_COMP_STAT(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_DOMRSTSTAT_COMP_STAT_SHIFT)) & RSTCTL0_DOMRSTSTAT_COMP_STAT_MASK)

#define RSTCTL0_DOMRSTSTAT_DSP_STAT_MASK         (0x10U)
#define RSTCTL0_DOMRSTSTAT_DSP_STAT_SHIFT        (4U)
/*! DSP_STAT - VDD2_DSP Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL0_DOMRSTSTAT_DSP_STAT(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_DOMRSTSTAT_DSP_STAT_SHIFT)) & RSTCTL0_DOMRSTSTAT_DSP_STAT_MASK)

#define RSTCTL0_DOMRSTSTAT_MEDIA_STAT_MASK       (0x20U)
#define RSTCTL0_DOMRSTSTAT_MEDIA_STAT_SHIFT      (5U)
/*! MEDIA_STAT - VDD2_MEDIA Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL0_DOMRSTSTAT_MEDIA_STAT(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_DOMRSTSTAT_MEDIA_STAT_SHIFT)) & RSTCTL0_DOMRSTSTAT_MEDIA_STAT_MASK)
/*! @} */

/*! @name PRSTCTL0 - Common Domain Peripheral Reset Control 0 */
/*! @{ */

#define RSTCTL0_PRSTCTL0_IOPCTL0_MASK            (0x40U)
#define RSTCTL0_PRSTCTL0_IOPCTL0_SHIFT           (6U)
/*! IOPCTL0 - IOPCTL0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL0_IOPCTL0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_IOPCTL0_SHIFT)) & RSTCTL0_PRSTCTL0_IOPCTL0_MASK)
/*! @} */

/*! @name PRSTCTL1 - Compute Domain Peripheral Reset Control 1 */
/*! @{ */

#define RSTCTL0_PRSTCTL1_ELS_MASK                (0x1U)
#define RSTCTL0_PRSTCTL1_ELS_SHIFT               (0U)
/*! ELS - ELS Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL1_ELS(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ELS_SHIFT)) & RSTCTL0_PRSTCTL1_ELS_MASK)
/*! @} */

/*! @name PRSTCTL2 - Compute Domain Peripheral Reset Control 2 */
/*! @{ */

#define RSTCTL0_PRSTCTL2_EDMA0_MASK              (0x20U)
#define RSTCTL0_PRSTCTL2_EDMA0_SHIFT             (5U)
/*! eDMA0 - eDMA0 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_EDMA0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_EDMA0_SHIFT)) & RSTCTL0_PRSTCTL2_EDMA0_MASK)

#define RSTCTL0_PRSTCTL2_EDMA1_MASK              (0x40U)
#define RSTCTL0_PRSTCTL2_EDMA1_SHIFT             (6U)
/*! eDMA1 - eDMA1 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_EDMA1(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_EDMA1_SHIFT)) & RSTCTL0_PRSTCTL2_EDMA1_MASK)

#define RSTCTL0_PRSTCTL2_PKC_MASK                (0x100U)
#define RSTCTL0_PRSTCTL2_PKC_SHIFT               (8U)
/*! PKC - PKC Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_PKC(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_PKC_SHIFT)) & RSTCTL0_PRSTCTL2_PKC_MASK)

#define RSTCTL0_PRSTCTL2_XSPI0_MASK              (0x400U)
#define RSTCTL0_PRSTCTL2_XSPI0_SHIFT             (10U)
/*! XSPI0 - XSPI0 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_XSPI0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_XSPI0_SHIFT)) & RSTCTL0_PRSTCTL2_XSPI0_MASK)

#define RSTCTL0_PRSTCTL2_XSPI1_MASK              (0x800U)
#define RSTCTL0_PRSTCTL2_XSPI1_SHIFT             (11U)
/*! XSPI1 - XSPI1 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_XSPI1(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_XSPI1_SHIFT)) & RSTCTL0_PRSTCTL2_XSPI1_MASK)

#define RSTCTL0_PRSTCTL2_GPIO0_MASK              (0x40000U)
#define RSTCTL0_PRSTCTL2_GPIO0_SHIFT             (18U)
/*! GPIO0 - GPIO0 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_GPIO0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_GPIO0_SHIFT)) & RSTCTL0_PRSTCTL2_GPIO0_MASK)

#define RSTCTL0_PRSTCTL2_GPIO1_MASK              (0x80000U)
#define RSTCTL0_PRSTCTL2_GPIO1_SHIFT             (19U)
/*! GPIO1 - GPIO1 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_GPIO1(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_GPIO1_SHIFT)) & RSTCTL0_PRSTCTL2_GPIO1_MASK)

#define RSTCTL0_PRSTCTL2_GPIO2_MASK              (0x100000U)
#define RSTCTL0_PRSTCTL2_GPIO2_SHIFT             (20U)
/*! GPIO2 - GPIO2 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_GPIO2(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_GPIO2_SHIFT)) & RSTCTL0_PRSTCTL2_GPIO2_MASK)

#define RSTCTL0_PRSTCTL2_GPIO3_MASK              (0x200000U)
#define RSTCTL0_PRSTCTL2_GPIO3_SHIFT             (21U)
/*! GPIO3 - GPIO3 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_GPIO3(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_GPIO3_SHIFT)) & RSTCTL0_PRSTCTL2_GPIO3_MASK)

#define RSTCTL0_PRSTCTL2_GPIO4_MASK              (0x400000U)
#define RSTCTL0_PRSTCTL2_GPIO4_SHIFT             (22U)
/*! GPIO4 - GPIO4 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_GPIO4(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_GPIO4_SHIFT)) & RSTCTL0_PRSTCTL2_GPIO4_MASK)

#define RSTCTL0_PRSTCTL2_GPIO5_MASK              (0x800000U)
#define RSTCTL0_PRSTCTL2_GPIO5_SHIFT             (23U)
/*! GPIO5 - GPIO5 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_GPIO5(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_GPIO5_SHIFT)) & RSTCTL0_PRSTCTL2_GPIO5_MASK)

#define RSTCTL0_PRSTCTL2_GPIO6_MASK              (0x1000000U)
#define RSTCTL0_PRSTCTL2_GPIO6_SHIFT             (24U)
/*! GPIO6 - GPIO6 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_GPIO6(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_GPIO6_SHIFT)) & RSTCTL0_PRSTCTL2_GPIO6_MASK)

#define RSTCTL0_PRSTCTL2_GPIO7_MASK              (0x2000000U)
#define RSTCTL0_PRSTCTL2_GPIO7_SHIFT             (25U)
/*! GPIO7 - GPIO7 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_GPIO7(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_GPIO7_SHIFT)) & RSTCTL0_PRSTCTL2_GPIO7_MASK)

#define RSTCTL0_PRSTCTL2_SCT0_MASK               (0x4000000U)
#define RSTCTL0_PRSTCTL2_SCT0_SHIFT              (26U)
/*! SCT0 - SCT0 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_SCT0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SCT0_SHIFT)) & RSTCTL0_PRSTCTL2_SCT0_MASK)

#define RSTCTL0_PRSTCTL2_LP_FLEXCOMM0_MASK       (0x40000000U)
#define RSTCTL0_PRSTCTL2_LP_FLEXCOMM0_SHIFT      (30U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_LP_FLEXCOMM0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_LP_FLEXCOMM0_SHIFT)) & RSTCTL0_PRSTCTL2_LP_FLEXCOMM0_MASK)

#define RSTCTL0_PRSTCTL2_LP_FLEXCOMM1_MASK       (0x80000000U)
#define RSTCTL0_PRSTCTL2_LP_FLEXCOMM1_SHIFT      (31U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL0_PRSTCTL2_LP_FLEXCOMM1(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_LP_FLEXCOMM1_SHIFT)) & RSTCTL0_PRSTCTL2_LP_FLEXCOMM1_MASK)
/*! @} */

/*! @name PRSTCTL3 - Compute Domain Peripheral Reset Control 3 */
/*! @{ */

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM2_MASK       (0x1U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM2_SHIFT      (0U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM2(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM2_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM2_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM3_MASK       (0x2U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM3_SHIFT      (1U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM3(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM3_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM3_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM4_MASK       (0x4U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM4_SHIFT      (2U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM4(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM4_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM4_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM5_MASK       (0x8U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM5_SHIFT      (3U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM5(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM5_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM5_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM6_MASK       (0x10U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM6_SHIFT      (4U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM6(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM6_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM6_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM7_MASK       (0x20U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM7_SHIFT      (5U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM7(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM7_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM7_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM8_MASK       (0x40U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM8_SHIFT      (6U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM8(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM8_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM8_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM9_MASK       (0x80U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM9_SHIFT      (7U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM9(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM9_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM9_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM10_MASK      (0x100U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM10_SHIFT     (8U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM10(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM10_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM10_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM11_MASK      (0x200U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM11_SHIFT     (9U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM11(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM11_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM11_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM12_MASK      (0x400U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM12_SHIFT     (10U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM12(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM12_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM12_MASK)

#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM13_MASK      (0x800U)
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM13_SHIFT     (11U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_LP_FLEXCOMM13(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_LP_FLEXCOMM13_SHIFT)) & RSTCTL0_PRSTCTL3_LP_FLEXCOMM13_MASK)

#define RSTCTL0_PRSTCTL3_SAI0_MASK               (0x2000U)
#define RSTCTL0_PRSTCTL3_SAI0_SHIFT              (13U)
/*! SAI0 - SAI0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SAI0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SAI0_SHIFT)) & RSTCTL0_PRSTCTL3_SAI0_MASK)

#define RSTCTL0_PRSTCTL3_SAI1_MASK               (0x4000U)
#define RSTCTL0_PRSTCTL3_SAI1_SHIFT              (14U)
/*! SAI1 - SAI1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SAI1(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SAI1_SHIFT)) & RSTCTL0_PRSTCTL3_SAI1_MASK)

#define RSTCTL0_PRSTCTL3_SAI2_MASK               (0x8000U)
#define RSTCTL0_PRSTCTL3_SAI2_SHIFT              (15U)
/*! SAI2 - SAI2 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SAI2(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SAI2_SHIFT)) & RSTCTL0_PRSTCTL3_SAI2_MASK)

#define RSTCTL0_PRSTCTL3_I3C0_MASK               (0x10000U)
#define RSTCTL0_PRSTCTL3_I3C0_SHIFT              (16U)
/*! I3C0 - I3C0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_I3C0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_I3C0_MASK)

#define RSTCTL0_PRSTCTL3_I3C1_MASK               (0x20000U)
#define RSTCTL0_PRSTCTL3_I3C1_SHIFT              (17U)
/*! I3C1 - I3C1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_I3C1(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_I3C1_SHIFT)) & RSTCTL0_PRSTCTL3_I3C1_MASK)

#define RSTCTL0_PRSTCTL3_CRC0_MASK               (0x40000U)
#define RSTCTL0_PRSTCTL3_CRC0_SHIFT              (18U)
/*! CRC0 - CRC0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_CRC0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CRC0_SHIFT)) & RSTCTL0_PRSTCTL3_CRC0_MASK)

#define RSTCTL0_PRSTCTL3_CTIMER0_MASK            (0x200000U)
#define RSTCTL0_PRSTCTL3_CTIMER0_SHIFT           (21U)
/*! CTIMER0 - CTIMER0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_CTIMER0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CTIMER0_SHIFT)) & RSTCTL0_PRSTCTL3_CTIMER0_MASK)

#define RSTCTL0_PRSTCTL3_CTIMER1_MASK            (0x400000U)
#define RSTCTL0_PRSTCTL3_CTIMER1_SHIFT           (22U)
/*! CTIMER1 - CTIMER1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_CTIMER1(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CTIMER1_SHIFT)) & RSTCTL0_PRSTCTL3_CTIMER1_MASK)

#define RSTCTL0_PRSTCTL3_CTIMER2_MASK            (0x800000U)
#define RSTCTL0_PRSTCTL3_CTIMER2_SHIFT           (23U)
/*! CTIMER2 - CTIMER2 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_CTIMER2(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CTIMER2_SHIFT)) & RSTCTL0_PRSTCTL3_CTIMER2_MASK)

#define RSTCTL0_PRSTCTL3_CTIMER3_MASK            (0x1000000U)
#define RSTCTL0_PRSTCTL3_CTIMER3_SHIFT           (24U)
/*! CTIMER3 - CTIMER3 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_CTIMER3(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CTIMER3_SHIFT)) & RSTCTL0_PRSTCTL3_CTIMER3_MASK)

#define RSTCTL0_PRSTCTL3_CTIMER4_MASK            (0x2000000U)
#define RSTCTL0_PRSTCTL3_CTIMER4_SHIFT           (25U)
/*! CTIMER4 - CTIMER4 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_CTIMER4(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CTIMER4_SHIFT)) & RSTCTL0_PRSTCTL3_CTIMER4_MASK)

#define RSTCTL0_PRSTCTL3_MRT0_MASK               (0x4000000U)
#define RSTCTL0_PRSTCTL3_MRT0_SHIFT              (26U)
/*! MRT0 - MRT0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_MRT0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_MRT0_SHIFT)) & RSTCTL0_PRSTCTL3_MRT0_MASK)

#define RSTCTL0_PRSTCTL3_UTICK0_MASK             (0x8000000U)
#define RSTCTL0_PRSTCTL3_UTICK0_SHIFT            (27U)
/*! UTICK0 - UTICK0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_UTICK0(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL3_UTICK0_MASK)

#define RSTCTL0_PRSTCTL3_SEMA42_4_MASK           (0x40000000U)
#define RSTCTL0_PRSTCTL3_SEMA42_4_SHIFT          (30U)
/*! SEMA42_4 - SEMA42_4 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SEMA42_4(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SEMA42_4_SHIFT)) & RSTCTL0_PRSTCTL3_SEMA42_4_MASK)

#define RSTCTL0_PRSTCTL3_MU4_MASK                (0x80000000U)
#define RSTCTL0_PRSTCTL3_MU4_SHIFT               (31U)
/*! MU4 - MU4 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_MU4(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_MU4_SHIFT)) & RSTCTL0_PRSTCTL3_MU4_MASK)
/*! @} */

/*! @name PRSTCTL4 - Compute Domain Peripheral Reset Control 4 */
/*! @{ */

#define RSTCTL0_PRSTCTL4_CMX_PERFMON2_MASK       (0x1U)
#define RSTCTL0_PRSTCTL4_CMX_PERFMON2_SHIFT      (0U)
/*! CMX_PERFMON2 - CMX_PERFMON2 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_CMX_PERFMON2(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CMX_PERFMON2_SHIFT)) & RSTCTL0_PRSTCTL4_CMX_PERFMON2_MASK)

#define RSTCTL0_PRSTCTL4_CMX_PERFMON3_MASK       (0x2U)
#define RSTCTL0_PRSTCTL4_CMX_PERFMON3_SHIFT      (1U)
/*! CMX_PERFMON3 - CMX_PERFMON3 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_CMX_PERFMON3(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CMX_PERFMON3_SHIFT)) & RSTCTL0_PRSTCTL4_CMX_PERFMON3_MASK)

#define RSTCTL0_PRSTCTL4_SAFO_SGI_MASK           (0x4U)
#define RSTCTL0_PRSTCTL4_SAFO_SGI_SHIFT          (2U)
/*! SAFO_SGI - SAFO_SGI Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SAFO_SGI(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SAFO_SGI_SHIFT)) & RSTCTL0_PRSTCTL4_SAFO_SGI_MASK)

#define RSTCTL0_PRSTCTL4_PINT0_MASK              (0x20U)
#define RSTCTL0_PRSTCTL4_PINT0_SHIFT             (5U)
/*! PINT0 - PINT0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_PINT0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_PINT0_SHIFT)) & RSTCTL0_PRSTCTL4_PINT0_MASK)

#define RSTCTL0_PRSTCTL4_INPUTMUX0_MASK          (0x80U)
#define RSTCTL0_PRSTCTL4_INPUTMUX0_SHIFT         (7U)
/*! INPUTMUX0 - INPUTMUX0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_INPUTMUX0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_INPUTMUX0_SHIFT)) & RSTCTL0_PRSTCTL4_INPUTMUX0_MASK)

#define RSTCTL0_PRSTCTL4_FREQME0_MASK            (0x100U)
#define RSTCTL0_PRSTCTL4_FREQME0_SHIFT           (8U)
/*! FREQME0 - FREQME Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_FREQME0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_FREQME0_SHIFT)) & RSTCTL0_PRSTCTL4_FREQME0_MASK)

#define RSTCTL0_PRSTCTL4_CMX_PERFMON0_MASK       (0x400U)
#define RSTCTL0_PRSTCTL4_CMX_PERFMON0_SHIFT      (10U)
/*! CMX_PERFMON0 - CMX_PERFMON0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_CMX_PERFMON0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CMX_PERFMON0_SHIFT)) & RSTCTL0_PRSTCTL4_CMX_PERFMON0_MASK)

#define RSTCTL0_PRSTCTL4_CMX_PERFMON1_MASK       (0x800U)
#define RSTCTL0_PRSTCTL4_CMX_PERFMON1_SHIFT      (11U)
/*! CMX_PERFMON1 - CMX_PERFMON1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_CMX_PERFMON1(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CMX_PERFMON1_SHIFT)) & RSTCTL0_PRSTCTL4_CMX_PERFMON1_MASK)

#define RSTCTL0_PRSTCTL4_NPU0_MASK               (0x1000U)
#define RSTCTL0_PRSTCTL4_NPU0_SHIFT              (12U)
/*! NPU0 - NPU0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_NPU0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_NPU0_SHIFT)) & RSTCTL0_PRSTCTL4_NPU0_MASK)
/*! @} */

/*! @name PRSTCTL5 - DSP Domain Peripheral Reset Control 5 */
/*! @{ */

#define RSTCTL0_PRSTCTL5_HIFI4_MASK              (0x1U)
#define RSTCTL0_PRSTCTL5_HIFI4_SHIFT             (0U)
/*! HiFi4 - HiFi4 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL5_HIFI4(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL5_HIFI4_SHIFT)) & RSTCTL0_PRSTCTL5_HIFI4_MASK)

#define RSTCTL0_PRSTCTL5_HIFI4_DEBUG_MASK        (0x4U)
#define RSTCTL0_PRSTCTL5_HIFI4_DEBUG_SHIFT       (2U)
/*! HiFi4_DEBUG - HiFi4 Debug Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL5_HIFI4_DEBUG(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL5_HIFI4_DEBUG_SHIFT)) & RSTCTL0_PRSTCTL5_HIFI4_DEBUG_MASK)
/*! @} */

/*! @name PRSTCTL0_SET - Common Domain Peripheral Reset Control 0 SET */
/*! @{ */

#define RSTCTL0_PRSTCTL0_SET_IOPCTL0_MASK        (0x40U)
#define RSTCTL0_PRSTCTL0_SET_IOPCTL0_SHIFT       (6U)
/*! IOPCTL0 - IOPCTL0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL0_SET_IOPCTL0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_IOPCTL0_SHIFT)) & RSTCTL0_PRSTCTL0_SET_IOPCTL0_MASK)
/*! @} */

/*! @name PRSTCTL1_SET - Compute Domain Peripheral Reset Control 1 SET */
/*! @{ */

#define RSTCTL0_PRSTCTL1_SET_ELS_MASK            (0x1U)
#define RSTCTL0_PRSTCTL1_SET_ELS_SHIFT           (0U)
/*! ELS - ELS Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL1_SET_ELS(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ELS_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ELS_MASK)
/*! @} */

/*! @name PRSTCTL2_SET - Compute Domain Peripheral Reset Control 2 SET */
/*! @{ */

#define RSTCTL0_PRSTCTL2_SET_EDMA0_MASK          (0x20U)
#define RSTCTL0_PRSTCTL2_SET_EDMA0_SHIFT         (5U)
/*! eDMA0 - eDMA0 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_EDMA0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_EDMA0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_EDMA0_MASK)

#define RSTCTL0_PRSTCTL2_SET_EDMA1_MASK          (0x40U)
#define RSTCTL0_PRSTCTL2_SET_EDMA1_SHIFT         (6U)
/*! eDMA1 - eDMA1 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_EDMA1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_EDMA1_SHIFT)) & RSTCTL0_PRSTCTL2_SET_EDMA1_MASK)

#define RSTCTL0_PRSTCTL2_SET_PKC_MASK            (0x100U)
#define RSTCTL0_PRSTCTL2_SET_PKC_SHIFT           (8U)
/*! PKC - PKC Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_PKC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_PKC_SHIFT)) & RSTCTL0_PRSTCTL2_SET_PKC_MASK)

#define RSTCTL0_PRSTCTL2_SET_XSPI0_MASK          (0x400U)
#define RSTCTL0_PRSTCTL2_SET_XSPI0_SHIFT         (10U)
/*! XSPI0 - XSPI0 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_XSPI0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_XSPI0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_XSPI0_MASK)

#define RSTCTL0_PRSTCTL2_SET_XSPI1_MASK          (0x800U)
#define RSTCTL0_PRSTCTL2_SET_XSPI1_SHIFT         (11U)
/*! XSPI1 - XSPI1 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_XSPI1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_XSPI1_SHIFT)) & RSTCTL0_PRSTCTL2_SET_XSPI1_MASK)

#define RSTCTL0_PRSTCTL2_SET_GPIO0_MASK          (0x40000U)
#define RSTCTL0_PRSTCTL2_SET_GPIO0_SHIFT         (18U)
/*! GPIO0 - GPIO0 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_GPIO0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_GPIO0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_GPIO0_MASK)

#define RSTCTL0_PRSTCTL2_SET_GPIO1_MASK          (0x80000U)
#define RSTCTL0_PRSTCTL2_SET_GPIO1_SHIFT         (19U)
/*! GPIO1 - GPIO1 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_GPIO1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_GPIO1_SHIFT)) & RSTCTL0_PRSTCTL2_SET_GPIO1_MASK)

#define RSTCTL0_PRSTCTL2_SET_GPIO2_MASK          (0x100000U)
#define RSTCTL0_PRSTCTL2_SET_GPIO2_SHIFT         (20U)
/*! GPIO2 - GPIO2 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_GPIO2(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_GPIO2_SHIFT)) & RSTCTL0_PRSTCTL2_SET_GPIO2_MASK)

#define RSTCTL0_PRSTCTL2_SET_GPIO3_MASK          (0x200000U)
#define RSTCTL0_PRSTCTL2_SET_GPIO3_SHIFT         (21U)
/*! GPIO3 - GPIO3 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_GPIO3(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_GPIO3_SHIFT)) & RSTCTL0_PRSTCTL2_SET_GPIO3_MASK)

#define RSTCTL0_PRSTCTL2_SET_GPIO4_MASK          (0x400000U)
#define RSTCTL0_PRSTCTL2_SET_GPIO4_SHIFT         (22U)
/*! GPIO4 - GPIO4 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_GPIO4(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_GPIO4_SHIFT)) & RSTCTL0_PRSTCTL2_SET_GPIO4_MASK)

#define RSTCTL0_PRSTCTL2_SET_GPIO5_MASK          (0x800000U)
#define RSTCTL0_PRSTCTL2_SET_GPIO5_SHIFT         (23U)
/*! GPIO5 - GPIO5 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_GPIO5(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_GPIO5_SHIFT)) & RSTCTL0_PRSTCTL2_SET_GPIO5_MASK)

#define RSTCTL0_PRSTCTL2_SET_GPIO6_MASK          (0x1000000U)
#define RSTCTL0_PRSTCTL2_SET_GPIO6_SHIFT         (24U)
/*! GPIO6 - GPIO6 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_GPIO6(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_GPIO6_SHIFT)) & RSTCTL0_PRSTCTL2_SET_GPIO6_MASK)

#define RSTCTL0_PRSTCTL2_SET_GPIO7_MASK          (0x2000000U)
#define RSTCTL0_PRSTCTL2_SET_GPIO7_SHIFT         (25U)
/*! GPIO7 - GPIO7 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_GPIO7(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_GPIO7_SHIFT)) & RSTCTL0_PRSTCTL2_SET_GPIO7_MASK)

#define RSTCTL0_PRSTCTL2_SET_SCT0_MASK           (0x4000000U)
#define RSTCTL0_PRSTCTL2_SET_SCT0_SHIFT          (26U)
/*! SCT0 - SCT0 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_SCT0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_SCT0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_SCT0_MASK)

#define RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM0_MASK   (0x40000000U)
#define RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM0_SHIFT  (30U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM0(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM0_MASK)

#define RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM1_MASK   (0x80000000U)
#define RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM1_SHIFT  (31U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM1(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM1_SHIFT)) & RSTCTL0_PRSTCTL2_SET_LP_FLEXCOMM1_MASK)
/*! @} */

/*! @name PRSTCTL3_SET - Compute Domain Peripheral Reset Control 3 SET */
/*! @{ */

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM2_MASK   (0x1U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM2_SHIFT  (0U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM2(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM2_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM2_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM3_MASK   (0x2U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM3_SHIFT  (1U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM3(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM3_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM3_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM4_MASK   (0x4U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM4_SHIFT  (2U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM4(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM4_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM4_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM5_MASK   (0x8U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM5_SHIFT  (3U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM5(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM5_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM5_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM6_MASK   (0x10U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM6_SHIFT  (4U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM6(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM6_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM6_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM7_MASK   (0x20U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM7_SHIFT  (5U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM7(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM7_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM7_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM8_MASK   (0x40U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM8_SHIFT  (6U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM8(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM8_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM8_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM9_MASK   (0x80U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM9_SHIFT  (7U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM9(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM9_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM9_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM10_MASK  (0x100U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM10_SHIFT (8U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM10(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM10_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM10_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM11_MASK  (0x200U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM11_SHIFT (9U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM11(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM11_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM11_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM12_MASK  (0x400U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM12_SHIFT (10U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM12(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM12_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM12_MASK)

#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM13_MASK  (0x800U)
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM13_SHIFT (11U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM13(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM13_SHIFT)) & RSTCTL0_PRSTCTL3_SET_LP_FLEXCOMM13_MASK)

#define RSTCTL0_PRSTCTL3_SET_SAI0_MASK           (0x2000U)
#define RSTCTL0_PRSTCTL3_SET_SAI0_SHIFT          (13U)
/*! SAI0 - SAI0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_SAI0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_SAI0_SHIFT)) & RSTCTL0_PRSTCTL3_SET_SAI0_MASK)

#define RSTCTL0_PRSTCTL3_SET_SAI1_MASK           (0x4000U)
#define RSTCTL0_PRSTCTL3_SET_SAI1_SHIFT          (14U)
/*! SAI1 - SAI1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_SAI1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_SAI1_SHIFT)) & RSTCTL0_PRSTCTL3_SET_SAI1_MASK)

#define RSTCTL0_PRSTCTL3_SET_SAI2_MASK           (0x8000U)
#define RSTCTL0_PRSTCTL3_SET_SAI2_SHIFT          (15U)
/*! SAI2 - SAI2 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_SAI2(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_SAI2_SHIFT)) & RSTCTL0_PRSTCTL3_SET_SAI2_MASK)

#define RSTCTL0_PRSTCTL3_SET_I3C0_MASK           (0x10000U)
#define RSTCTL0_PRSTCTL3_SET_I3C0_SHIFT          (16U)
/*! I3C0 - I3C0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_I3C0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_SET_I3C0_MASK)

#define RSTCTL0_PRSTCTL3_SET_I3C1_MASK           (0x20000U)
#define RSTCTL0_PRSTCTL3_SET_I3C1_SHIFT          (17U)
/*! I3C1 - I3C1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_I3C1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_I3C1_SHIFT)) & RSTCTL0_PRSTCTL3_SET_I3C1_MASK)

#define RSTCTL0_PRSTCTL3_SET_CRC0_MASK           (0x40000U)
#define RSTCTL0_PRSTCTL3_SET_CRC0_SHIFT          (18U)
/*! CRC0 - CRC0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_CRC0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_CRC0_SHIFT)) & RSTCTL0_PRSTCTL3_SET_CRC0_MASK)

#define RSTCTL0_PRSTCTL3_SET_CTIMER0_MASK        (0x200000U)
#define RSTCTL0_PRSTCTL3_SET_CTIMER0_SHIFT       (21U)
/*! CTIMER0 - CTIMER0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_CTIMER0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_CTIMER0_SHIFT)) & RSTCTL0_PRSTCTL3_SET_CTIMER0_MASK)

#define RSTCTL0_PRSTCTL3_SET_CTIMER1_MASK        (0x400000U)
#define RSTCTL0_PRSTCTL3_SET_CTIMER1_SHIFT       (22U)
/*! CTIMER1 - CTIMER1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_CTIMER1(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_CTIMER1_SHIFT)) & RSTCTL0_PRSTCTL3_SET_CTIMER1_MASK)

#define RSTCTL0_PRSTCTL3_SET_CTIMER2_MASK        (0x800000U)
#define RSTCTL0_PRSTCTL3_SET_CTIMER2_SHIFT       (23U)
/*! CTIMER2 - CTIMER2 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_CTIMER2(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_CTIMER2_SHIFT)) & RSTCTL0_PRSTCTL3_SET_CTIMER2_MASK)

#define RSTCTL0_PRSTCTL3_SET_CTIMER3_MASK        (0x1000000U)
#define RSTCTL0_PRSTCTL3_SET_CTIMER3_SHIFT       (24U)
/*! CTIMER3 - CTIMER3 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_CTIMER3(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_CTIMER3_SHIFT)) & RSTCTL0_PRSTCTL3_SET_CTIMER3_MASK)

#define RSTCTL0_PRSTCTL3_SET_CTIMER4_MASK        (0x2000000U)
#define RSTCTL0_PRSTCTL3_SET_CTIMER4_SHIFT       (25U)
/*! CTIMER4 - CTIMER4 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_CTIMER4(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_CTIMER4_SHIFT)) & RSTCTL0_PRSTCTL3_SET_CTIMER4_MASK)

#define RSTCTL0_PRSTCTL3_SET_MRT0_MASK           (0x4000000U)
#define RSTCTL0_PRSTCTL3_SET_MRT0_SHIFT          (26U)
/*! MRT0 - MRT0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_MRT0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_MRT0_SHIFT)) & RSTCTL0_PRSTCTL3_SET_MRT0_MASK)

#define RSTCTL0_PRSTCTL3_SET_UTICK0_MASK         (0x8000000U)
#define RSTCTL0_PRSTCTL3_SET_UTICK0_SHIFT        (27U)
/*! UTICK0 - UTICK0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_UTICK0(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL3_SET_UTICK0_MASK)

#define RSTCTL0_PRSTCTL3_SET_SEMA42_4_MASK       (0x40000000U)
#define RSTCTL0_PRSTCTL3_SET_SEMA42_4_SHIFT      (30U)
/*! SEMA42_4 - SEMA42_4 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_SEMA42_4(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_SEMA42_4_SHIFT)) & RSTCTL0_PRSTCTL3_SET_SEMA42_4_MASK)

#define RSTCTL0_PRSTCTL3_SET_MU4_MASK            (0x80000000U)
#define RSTCTL0_PRSTCTL3_SET_MU4_SHIFT           (31U)
/*! MU4 - MU4 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL3_SET_MU4(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_SET_MU4_SHIFT)) & RSTCTL0_PRSTCTL3_SET_MU4_MASK)
/*! @} */

/*! @name PRSTCTL4_SET - Compute Domain Peripheral Reset Control 4 SET */
/*! @{ */

#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON2_MASK   (0x1U)
#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON2_SHIFT  (0U)
/*! CMX_PERFMON2 - CMX_PERFMON2 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON2(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_CMX_PERFMON2_SHIFT)) & RSTCTL0_PRSTCTL4_SET_CMX_PERFMON2_MASK)

#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON3_MASK   (0x2U)
#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON3_SHIFT  (1U)
/*! CMX_PERFMON3 - CMX_PERFMON3 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON3(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_CMX_PERFMON3_SHIFT)) & RSTCTL0_PRSTCTL4_SET_CMX_PERFMON3_MASK)

#define RSTCTL0_PRSTCTL4_SET_SAFO_SGI_MASK       (0x4U)
#define RSTCTL0_PRSTCTL4_SET_SAFO_SGI_SHIFT      (2U)
/*! SAFO_SGI - SAFO_SGI Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_SAFO_SGI(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_SAFO_SGI_SHIFT)) & RSTCTL0_PRSTCTL4_SET_SAFO_SGI_MASK)

#define RSTCTL0_PRSTCTL4_SET_PINT0_MASK          (0x20U)
#define RSTCTL0_PRSTCTL4_SET_PINT0_SHIFT         (5U)
/*! PINT0 - PINT0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_PINT0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_PINT0_SHIFT)) & RSTCTL0_PRSTCTL4_SET_PINT0_MASK)

#define RSTCTL0_PRSTCTL4_SET_INPUTMUX0_MASK      (0x80U)
#define RSTCTL0_PRSTCTL4_SET_INPUTMUX0_SHIFT     (7U)
/*! INPUTMUX0 - INPUTMUX0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_INPUTMUX0(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_INPUTMUX0_SHIFT)) & RSTCTL0_PRSTCTL4_SET_INPUTMUX0_MASK)

#define RSTCTL0_PRSTCTL4_SET_FREQME0_MASK        (0x100U)
#define RSTCTL0_PRSTCTL4_SET_FREQME0_SHIFT       (8U)
/*! FREQME0 - FREQME0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_FREQME0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_FREQME0_SHIFT)) & RSTCTL0_PRSTCTL4_SET_FREQME0_MASK)

#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON0_MASK   (0x400U)
#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON0_SHIFT  (10U)
/*! CMX_PERFMON0 - CMX_PERFMON0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON0(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_CMX_PERFMON0_SHIFT)) & RSTCTL0_PRSTCTL4_SET_CMX_PERFMON0_MASK)

#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON1_MASK   (0x800U)
#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON1_SHIFT  (11U)
/*! CMX_PERFMON1 - CMX_PERFMON1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_CMX_PERFMON1(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_CMX_PERFMON1_SHIFT)) & RSTCTL0_PRSTCTL4_SET_CMX_PERFMON1_MASK)

#define RSTCTL0_PRSTCTL4_SET_NPU0_MASK           (0x1000U)
#define RSTCTL0_PRSTCTL4_SET_NPU0_SHIFT          (12U)
/*! NPU0 - NPU0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL4_SET_NPU0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_SET_NPU0_SHIFT)) & RSTCTL0_PRSTCTL4_SET_NPU0_MASK)
/*! @} */

/*! @name PRSTCTL5_SET - DSP Domain Peripheral Reset Control 5 SET */
/*! @{ */

#define RSTCTL0_PRSTCTL5_SET_HIFI4_MASK          (0x1U)
#define RSTCTL0_PRSTCTL5_SET_HIFI4_SHIFT         (0U)
/*! HiFi4 - HiFi4 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL5_SET_HIFI4(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL5_SET_HIFI4_SHIFT)) & RSTCTL0_PRSTCTL5_SET_HIFI4_MASK)

#define RSTCTL0_PRSTCTL5_SET_HIFI4_DEBUG_MASK    (0x4U)
#define RSTCTL0_PRSTCTL5_SET_HIFI4_DEBUG_SHIFT   (2U)
/*! HiFi4_DEBUG - HiFi4 Debug Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL0_PRSTCTL5_SET_HIFI4_DEBUG(x)      (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL5_SET_HIFI4_DEBUG_SHIFT)) & RSTCTL0_PRSTCTL5_SET_HIFI4_DEBUG_MASK)
/*! @} */

/*! @name PRSTCTL0_CLR - Common Domain Peripheral Reset Control 0 CLR */
/*! @{ */

#define RSTCTL0_PRSTCTL0_CLR_IOPCTL0_MASK        (0x40U)
#define RSTCTL0_PRSTCTL0_CLR_IOPCTL0_SHIFT       (6U)
/*! IOPCTL0 - IOPCTL0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL0_CLR_IOPCTL0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_IOPCTL0_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_IOPCTL0_MASK)
/*! @} */

/*! @name PRSTCTL1_CLR - Compute Domain Peripheral Reset Control 1 CLR */
/*! @{ */

#define RSTCTL0_PRSTCTL1_CLR_ELS_MASK            (0x1U)
#define RSTCTL0_PRSTCTL1_CLR_ELS_SHIFT           (0U)
/*! ELS - ELS Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL1_CLR_ELS(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ELS_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ELS_MASK)
/*! @} */

/*! @name PRSTCTL2_CLR - Compute Domain Peripheral Reset Control 2 CLR */
/*! @{ */

#define RSTCTL0_PRSTCTL2_CLR_EDMA0_MASK          (0x20U)
#define RSTCTL0_PRSTCTL2_CLR_EDMA0_SHIFT         (5U)
/*! eDMA0 - eDMA0 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_EDMA0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_EDMA0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_EDMA0_MASK)

#define RSTCTL0_PRSTCTL2_CLR_EDMA1_MASK          (0x40U)
#define RSTCTL0_PRSTCTL2_CLR_EDMA1_SHIFT         (6U)
/*! eDMA1 - eDMA1 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_EDMA1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_EDMA1_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_EDMA1_MASK)

#define RSTCTL0_PRSTCTL2_CLR_PKC_MASK            (0x100U)
#define RSTCTL0_PRSTCTL2_CLR_PKC_SHIFT           (8U)
/*! PKC - PKC Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_PKC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_PKC_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_PKC_MASK)

#define RSTCTL0_PRSTCTL2_CLR_XSPI0_MASK          (0x400U)
#define RSTCTL0_PRSTCTL2_CLR_XSPI0_SHIFT         (10U)
/*! XSPI0 - XSPI0 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_XSPI0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_XSPI0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_XSPI0_MASK)

#define RSTCTL0_PRSTCTL2_CLR_XSPI1_MASK          (0x800U)
#define RSTCTL0_PRSTCTL2_CLR_XSPI1_SHIFT         (11U)
/*! XSPI1 - XSPI1 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_XSPI1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_XSPI1_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_XSPI1_MASK)

#define RSTCTL0_PRSTCTL2_CLR_GPIO0_MASK          (0x40000U)
#define RSTCTL0_PRSTCTL2_CLR_GPIO0_SHIFT         (18U)
/*! GPIO0 - GPIO0 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_GPIO0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_GPIO0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_GPIO0_MASK)

#define RSTCTL0_PRSTCTL2_CLR_GPIO1_MASK          (0x80000U)
#define RSTCTL0_PRSTCTL2_CLR_GPIO1_SHIFT         (19U)
/*! GPIO1 - GPIO1 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_GPIO1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_GPIO1_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_GPIO1_MASK)

#define RSTCTL0_PRSTCTL2_CLR_GPIO2_MASK          (0x100000U)
#define RSTCTL0_PRSTCTL2_CLR_GPIO2_SHIFT         (20U)
/*! GPIO2 - GPIO2 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_GPIO2(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_GPIO2_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_GPIO2_MASK)

#define RSTCTL0_PRSTCTL2_CLR_GPIO3_MASK          (0x200000U)
#define RSTCTL0_PRSTCTL2_CLR_GPIO3_SHIFT         (21U)
/*! GPIO3 - GPIO3 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_GPIO3(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_GPIO3_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_GPIO3_MASK)

#define RSTCTL0_PRSTCTL2_CLR_GPIO4_MASK          (0x400000U)
#define RSTCTL0_PRSTCTL2_CLR_GPIO4_SHIFT         (22U)
/*! GPIO4 - GPIO4 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_GPIO4(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_GPIO4_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_GPIO4_MASK)

#define RSTCTL0_PRSTCTL2_CLR_GPIO5_MASK          (0x800000U)
#define RSTCTL0_PRSTCTL2_CLR_GPIO5_SHIFT         (23U)
/*! GPIO5 - GPIO5 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_GPIO5(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_GPIO5_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_GPIO5_MASK)

#define RSTCTL0_PRSTCTL2_CLR_GPIO6_MASK          (0x1000000U)
#define RSTCTL0_PRSTCTL2_CLR_GPIO6_SHIFT         (24U)
/*! GPIO6 - GPIO6 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_GPIO6(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_GPIO6_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_GPIO6_MASK)

#define RSTCTL0_PRSTCTL2_CLR_GPIO7_MASK          (0x2000000U)
#define RSTCTL0_PRSTCTL2_CLR_GPIO7_SHIFT         (25U)
/*! GPIO7 - GPIO7 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_GPIO7(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_GPIO7_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_GPIO7_MASK)

#define RSTCTL0_PRSTCTL2_CLR_SCT0_MASK           (0x4000000U)
#define RSTCTL0_PRSTCTL2_CLR_SCT0_SHIFT          (26U)
/*! SCT0 - SCT0 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_SCT0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_SCT0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_SCT0_MASK)

#define RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM0_MASK   (0x40000000U)
#define RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM0_SHIFT  (30U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM0(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM0_MASK)

#define RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM1_MASK   (0x80000000U)
#define RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM1_SHIFT  (31U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM1(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM1_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_LP_FLEXCOMM1_MASK)
/*! @} */

/*! @name PRSTCTL3_CLR - Compute Domain Peripheral Reset Control 3 CLR */
/*! @{ */

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM2_MASK   (0x1U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM2_SHIFT  (0U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM2(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM2_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM2_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM3_MASK   (0x2U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM3_SHIFT  (1U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM3(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM3_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM3_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM4_MASK   (0x4U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM4_SHIFT  (2U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM4(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM4_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM4_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM5_MASK   (0x8U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM5_SHIFT  (3U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM5(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM5_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM5_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM6_MASK   (0x10U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM6_SHIFT  (4U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM6(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM6_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM6_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM7_MASK   (0x20U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM7_SHIFT  (5U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM7(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM7_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM7_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM8_MASK   (0x40U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM8_SHIFT  (6U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM8(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM8_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM8_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM9_MASK   (0x80U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM9_SHIFT  (7U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM9(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM9_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM9_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM10_MASK  (0x100U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM10_SHIFT (8U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM10(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM10_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM10_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM11_MASK  (0x200U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM11_SHIFT (9U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM11(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM11_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM11_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM12_MASK  (0x400U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM12_SHIFT (10U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM12(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM12_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM12_MASK)

#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM13_MASK  (0x800U)
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM13_SHIFT (11U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM13(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM13_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_LP_FLEXCOMM13_MASK)

#define RSTCTL0_PRSTCTL3_CLR_SAI0_MASK           (0x2000U)
#define RSTCTL0_PRSTCTL3_CLR_SAI0_SHIFT          (13U)
/*! SAI0 - SAI0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_SAI0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_SAI0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_SAI0_MASK)

#define RSTCTL0_PRSTCTL3_CLR_SAI1_MASK           (0x4000U)
#define RSTCTL0_PRSTCTL3_CLR_SAI1_SHIFT          (14U)
/*! SAI1 - SAI1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_SAI1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_SAI1_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_SAI1_MASK)

#define RSTCTL0_PRSTCTL3_CLR_SAI2_MASK           (0x8000U)
#define RSTCTL0_PRSTCTL3_CLR_SAI2_SHIFT          (15U)
/*! SAI2 - SAI2 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_SAI2(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_SAI2_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_SAI2_MASK)

#define RSTCTL0_PRSTCTL3_CLR_I3C0_MASK           (0x10000U)
#define RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT          (16U)
/*! I3C0 - I3C0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_I3C0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C0_MASK)

#define RSTCTL0_PRSTCTL3_CLR_I3C1_MASK           (0x20000U)
#define RSTCTL0_PRSTCTL3_CLR_I3C1_SHIFT          (17U)
/*! I3C1 - I3C1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_I3C1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_I3C1_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_I3C1_MASK)

#define RSTCTL0_PRSTCTL3_CLR_CRC0_MASK           (0x40000U)
#define RSTCTL0_PRSTCTL3_CLR_CRC0_SHIFT          (18U)
/*! CRC0 - CRC0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_CRC0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_CRC0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_CRC0_MASK)

#define RSTCTL0_PRSTCTL3_CLR_CTIMER0_MASK        (0x200000U)
#define RSTCTL0_PRSTCTL3_CLR_CTIMER0_SHIFT       (21U)
/*! CTIMER0 - CTIMER0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_CTIMER0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_CTIMER0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_CTIMER0_MASK)

#define RSTCTL0_PRSTCTL3_CLR_CTIMER1_MASK        (0x400000U)
#define RSTCTL0_PRSTCTL3_CLR_CTIMER1_SHIFT       (22U)
/*! CTIMER1 - CTIMER1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_CTIMER1(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_CTIMER1_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_CTIMER1_MASK)

#define RSTCTL0_PRSTCTL3_CLR_CTIMER2_MASK        (0x800000U)
#define RSTCTL0_PRSTCTL3_CLR_CTIMER2_SHIFT       (23U)
/*! CTIMER2 - CTIMER2 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_CTIMER2(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_CTIMER2_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_CTIMER2_MASK)

#define RSTCTL0_PRSTCTL3_CLR_CTIMER3_MASK        (0x1000000U)
#define RSTCTL0_PRSTCTL3_CLR_CTIMER3_SHIFT       (24U)
/*! CTIMER3 - CTIMER3 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_CTIMER3(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_CTIMER3_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_CTIMER3_MASK)

#define RSTCTL0_PRSTCTL3_CLR_CTIMER4_MASK        (0x2000000U)
#define RSTCTL0_PRSTCTL3_CLR_CTIMER4_SHIFT       (25U)
/*! CTIMER4 - CTIMER4 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_CTIMER4(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_CTIMER4_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_CTIMER4_MASK)

#define RSTCTL0_PRSTCTL3_CLR_MRT0_MASK           (0x4000000U)
#define RSTCTL0_PRSTCTL3_CLR_MRT0_SHIFT          (26U)
/*! MRT0 - MRT0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_MRT0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_MRT0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_MRT0_MASK)

#define RSTCTL0_PRSTCTL3_CLR_UTICK0_MASK         (0x8000000U)
#define RSTCTL0_PRSTCTL3_CLR_UTICK0_SHIFT        (27U)
/*! UTICK0 - UTICK0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_UTICK0(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_UTICK0_MASK)

#define RSTCTL0_PRSTCTL3_CLR_SEMA42_4_MASK       (0x40000000U)
#define RSTCTL0_PRSTCTL3_CLR_SEMA42_4_SHIFT      (30U)
/*! SEMA42_4 - SEMA42_4 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_SEMA42_4(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_SEMA42_4_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_SEMA42_4_MASK)

#define RSTCTL0_PRSTCTL3_CLR_MU4_MASK            (0x80000000U)
#define RSTCTL0_PRSTCTL3_CLR_MU4_SHIFT           (31U)
/*! MU4 - MU4 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL3_CLR_MU4(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL3_CLR_MU4_SHIFT)) & RSTCTL0_PRSTCTL3_CLR_MU4_MASK)
/*! @} */

/*! @name PRSTCTL4_CLR - Compute Domain Peripheral Reset Control 4 CLR */
/*! @{ */

#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON2_MASK   (0x1U)
#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON2_SHIFT  (0U)
/*! CMX_PERFMON2 - CMX_PERFMON2 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON2(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON2_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON2_MASK)

#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON3_MASK   (0x2U)
#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON3_SHIFT  (1U)
/*! CMX_PERFMON3 - CMX_PERFMON3 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON3(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON3_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON3_MASK)

#define RSTCTL0_PRSTCTL4_CLR_SAFO_SGI_MASK       (0x4U)
#define RSTCTL0_PRSTCTL4_CLR_SAFO_SGI_SHIFT      (2U)
/*! SAFO_SGI - SAFO_SGI Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_SAFO_SGI(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_SAFO_SGI_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_SAFO_SGI_MASK)

#define RSTCTL0_PRSTCTL4_CLR_PINT0_MASK          (0x20U)
#define RSTCTL0_PRSTCTL4_CLR_PINT0_SHIFT         (5U)
/*! PINT0 - PINT0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_PINT0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_PINT0_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_PINT0_MASK)

#define RSTCTL0_PRSTCTL4_CLR_INPUTMUX0_MASK      (0x80U)
#define RSTCTL0_PRSTCTL4_CLR_INPUTMUX0_SHIFT     (7U)
/*! INPUTMUX0 - INPUTMUX0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_INPUTMUX0(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_INPUTMUX0_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_INPUTMUX0_MASK)

#define RSTCTL0_PRSTCTL4_CLR_FREQME0_MASK        (0x100U)
#define RSTCTL0_PRSTCTL4_CLR_FREQME0_SHIFT       (8U)
/*! FREQME0 - FREQME0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_FREQME0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_FREQME0_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_FREQME0_MASK)

#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON0_MASK   (0x400U)
#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON0_SHIFT  (10U)
/*! CMX_PERFMON0 - CMX_PERFMON0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON0(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON0_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON0_MASK)

#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON1_MASK   (0x800U)
#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON1_SHIFT  (11U)
/*! CMX_PERFMON1 - CMX_PERFMON1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON1(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON1_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_CMX_PERFMON1_MASK)

#define RSTCTL0_PRSTCTL4_CLR_NPU0_MASK           (0x1000U)
#define RSTCTL0_PRSTCTL4_CLR_NPU0_SHIFT          (12U)
/*! NPU0 - NPU0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL4_CLR_NPU0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL4_CLR_NPU0_SHIFT)) & RSTCTL0_PRSTCTL4_CLR_NPU0_MASK)
/*! @} */

/*! @name PRSTCTL5_CLR - DSP Domain Peripheral Reset Control 5 CLR */
/*! @{ */

#define RSTCTL0_PRSTCTL5_CLR_HIFI4_MASK          (0x1U)
#define RSTCTL0_PRSTCTL5_CLR_HIFI4_SHIFT         (0U)
/*! HiFi4 - HiFi4 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL5_CLR_HIFI4(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL5_CLR_HIFI4_SHIFT)) & RSTCTL0_PRSTCTL5_CLR_HIFI4_MASK)

#define RSTCTL0_PRSTCTL5_CLR_VDD2_DSP_DEBUG_MASK (0x4U)
#define RSTCTL0_PRSTCTL5_CLR_VDD2_DSP_DEBUG_SHIFT (2U)
/*! VDD2_DSP_DEBUG - HiFi4 Debug Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL0_PRSTCTL5_CLR_VDD2_DSP_DEBUG(x)   (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL5_CLR_VDD2_DSP_DEBUG_SHIFT)) & RSTCTL0_PRSTCTL5_CLR_VDD2_DSP_DEBUG_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RSTCTL0_Register_Masks */


/* RSTCTL0 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RSTCTL0 base address */
  #define RSTCTL0_BASE                             (0x50000000u)
  /** Peripheral RSTCTL0 base address */
  #define RSTCTL0_BASE_NS                          (0x40000000u)
  /** Peripheral RSTCTL0 base pointer */
  #define RSTCTL0                                  ((RSTCTL0_Type *)RSTCTL0_BASE)
  /** Peripheral RSTCTL0 base pointer */
  #define RSTCTL0_NS                               ((RSTCTL0_Type *)RSTCTL0_BASE_NS)
  /** Array initializer of RSTCTL0 peripheral base addresses */
  #define RSTCTL0_BASE_ADDRS                       { RSTCTL0_BASE }
  /** Array initializer of RSTCTL0 peripheral base pointers */
  #define RSTCTL0_BASE_PTRS                        { RSTCTL0 }
  /** Array initializer of RSTCTL0 peripheral base addresses */
  #define RSTCTL0_BASE_ADDRS_NS                    { RSTCTL0_BASE_NS }
  /** Array initializer of RSTCTL0 peripheral base pointers */
  #define RSTCTL0_BASE_PTRS_NS                     { RSTCTL0_NS }
#else
  /** Peripheral RSTCTL0 base address */
  #define RSTCTL0_BASE                             (0x40000000u)
  /** Peripheral RSTCTL0 base pointer */
  #define RSTCTL0                                  ((RSTCTL0_Type *)RSTCTL0_BASE)
  /** Array initializer of RSTCTL0 peripheral base addresses */
  #define RSTCTL0_BASE_ADDRS                       { RSTCTL0_BASE }
  /** Array initializer of RSTCTL0 peripheral base pointers */
  #define RSTCTL0_BASE_PTRS                        { RSTCTL0 }
#endif

/*!
 * @}
 */ /* end of group RSTCTL0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RSTCTL2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL2_Peripheral_Access_Layer RSTCTL2 Peripheral Access Layer
 * @{
 */

/** RSTCTL2 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PRSTCTL0;                          /**< VDDN Domain Peripheral Reset Control 0, offset: 0x10 */
       uint8_t RESERVED_1[44];
  __O  uint32_t PRSTCTL0_SET;                      /**< VDDN Domain Peripheral Reset Control 0 SET, offset: 0x40 */
       uint8_t RESERVED_2[44];
  __O  uint32_t PRSTCTL0_CLR;                      /**< VDDN Domain Peripheral Reset Control 0 CLR, offset: 0x70 */
} RSTCTL2_Type;

/* ----------------------------------------------------------------------------
   -- RSTCTL2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL2_Register_Masks RSTCTL2 Register Masks
 * @{
 */

/*! @name PRSTCTL0 - VDDN Domain Peripheral Reset Control 0 */
/*! @{ */

#define RSTCTL2_PRSTCTL0_IOPCTL2_MASK            (0x2U)
#define RSTCTL2_PRSTCTL0_IOPCTL2_SHIFT           (1U)
/*! IOPCTL2 - IOPCTL2 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL2_PRSTCTL0_IOPCTL2(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL2_PRSTCTL0_IOPCTL2_SHIFT)) & RSTCTL2_PRSTCTL0_IOPCTL2_MASK)
/*! @} */

/*! @name PRSTCTL0_SET - VDDN Domain Peripheral Reset Control 0 SET */
/*! @{ */

#define RSTCTL2_PRSTCTL0_SET_IOPCTL2_MASK        (0x2U)
#define RSTCTL2_PRSTCTL0_SET_IOPCTL2_SHIFT       (1U)
/*! IOPCTL2 - IOPCTL2 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL2_PRSTCTL0_SET_IOPCTL2(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL2_PRSTCTL0_SET_IOPCTL2_SHIFT)) & RSTCTL2_PRSTCTL0_SET_IOPCTL2_MASK)
/*! @} */

/*! @name PRSTCTL0_CLR - VDDN Domain Peripheral Reset Control 0 CLR */
/*! @{ */

#define RSTCTL2_PRSTCTL0_CLR_IOPCTL2_MASK        (0x2U)
#define RSTCTL2_PRSTCTL0_CLR_IOPCTL2_SHIFT       (1U)
/*! IOPCTL2 - IOPCTL2 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL2_PRSTCTL0_CLR_IOPCTL2(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL2_PRSTCTL0_CLR_IOPCTL2_SHIFT)) & RSTCTL2_PRSTCTL0_CLR_IOPCTL2_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RSTCTL2_Register_Masks */


/* RSTCTL2 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RSTCTL2 base address */
  #define RSTCTL2_BASE                             (0x50067000u)
  /** Peripheral RSTCTL2 base address */
  #define RSTCTL2_BASE_NS                          (0x40067000u)
  /** Peripheral RSTCTL2 base pointer */
  #define RSTCTL2                                  ((RSTCTL2_Type *)RSTCTL2_BASE)
  /** Peripheral RSTCTL2 base pointer */
  #define RSTCTL2_NS                               ((RSTCTL2_Type *)RSTCTL2_BASE_NS)
  /** Array initializer of RSTCTL2 peripheral base addresses */
  #define RSTCTL2_BASE_ADDRS                       { RSTCTL2_BASE }
  /** Array initializer of RSTCTL2 peripheral base pointers */
  #define RSTCTL2_BASE_PTRS                        { RSTCTL2 }
  /** Array initializer of RSTCTL2 peripheral base addresses */
  #define RSTCTL2_BASE_ADDRS_NS                    { RSTCTL2_BASE_NS }
  /** Array initializer of RSTCTL2 peripheral base pointers */
  #define RSTCTL2_BASE_PTRS_NS                     { RSTCTL2_NS }
#else
  /** Peripheral RSTCTL2 base address */
  #define RSTCTL2_BASE                             (0x40067000u)
  /** Peripheral RSTCTL2 base pointer */
  #define RSTCTL2                                  ((RSTCTL2_Type *)RSTCTL2_BASE)
  /** Array initializer of RSTCTL2 peripheral base addresses */
  #define RSTCTL2_BASE_ADDRS                       { RSTCTL2_BASE }
  /** Array initializer of RSTCTL2 peripheral base pointers */
  #define RSTCTL2_BASE_PTRS                        { RSTCTL2 }
#endif

/*!
 * @}
 */ /* end of group RSTCTL2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RSTCTL3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL3_Peripheral_Access_Layer RSTCTL3 Peripheral Access Layer
 * @{
 */

/** RSTCTL3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t SYSRSTSTAT;                        /**< System Reset Status, offset: 0x0 */
  __I  uint32_t DOMRSTSTAT;                        /**< Domain Reset Status, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t PRSTCTL0;                          /**< Sense Domain Peripheral Reset Control 0, offset: 0x10 */
  __IO uint32_t PRSTCTL1;                          /**< Sense Domain Peripheral Reset Control 1, offset: 0x14 */
       uint8_t RESERVED_1[40];
  __O  uint32_t PRSTCTL0_SET;                      /**< Sense Domain Peripheral Reset Control 0 SET, offset: 0x40 */
  __O  uint32_t PRSTCTL1_SET;                      /**< Sense Domain Peripheral Reset Control 1 SET, offset: 0x44 */
       uint8_t RESERVED_2[40];
  __O  uint32_t PRSTCTL0_CLR;                      /**< Sense Domain Peripheral Reset Control 0 CLR, offset: 0x70 */
  __O  uint32_t PRSTCTL1_CLR;                      /**< Sense Peripheral Reset Control 1 CLR, offset: 0x74 */
} RSTCTL3_Type;

/* ----------------------------------------------------------------------------
   -- RSTCTL3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL3_Register_Masks RSTCTL3 Register Masks
 * @{
 */

/*! @name SYSRSTSTAT - System Reset Status */
/*! @{ */

#define RSTCTL3_SYSRSTSTAT_VDD_POR_MASK          (0x1U)
#define RSTCTL3_SYSRSTSTAT_VDD_POR_SHIFT         (0U)
/*! VDD_POR - VDD Power-On Reset (POR)
 *  0b0..No VDD POR event is detected.
 *  0b1..VDD POR event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_VDD_POR(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_VDD_POR_SHIFT)) & RSTCTL3_SYSRSTSTAT_VDD_POR_MASK)

#define RSTCTL3_SYSRSTSTAT_RESETN_RESET_MASK     (0x2U)
#define RSTCTL3_SYSRSTSTAT_RESETN_RESET_SHIFT    (1U)
/*! RESETN_RESET - RESETN Reset
 *  0b0..No RESETN event is detected
 *  0b1..RESETN event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_RESETN_RESET(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_RESETN_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_RESETN_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_ISP_AP_RESET_MASK     (0x4U)
#define RSTCTL3_SYSRSTSTAT_ISP_AP_RESET_SHIFT    (2U)
/*! ISP_AP_RESET - ISP_AP (Debug Mailbox) Reset
 *  0b0..No ISP_AP reset event is detected.
 *  0b1..ISP_AP reset is detected.
 */
#define RSTCTL3_SYSRSTSTAT_ISP_AP_RESET(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ISP_AP_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ISP_AP_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK    (0x8U)
#define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT   (3U)
/*! ITRC_SW_RESET - ITRC_SW (Intrusion and Tamper Response Controller SW) Reset
 *  0b0..No ITRC_SW reset event is detected.
 *  0b1..ITRC_SW reset is detected.
 */
#define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET(x)      (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_CPU0_RESET_MASK       (0x10U)
#define RSTCTL3_SYSRSTSTAT_CPU0_RESET_SHIFT      (4U)
/*! CPU0_RESET - CPU0 Reset
 *  0b0..No CPU0 reset event is detected.
 *  0b1..CPU0 reset is detected.
 */
#define RSTCTL3_SYSRSTSTAT_CPU0_RESET(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_CPU0_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_CPU0_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_CPU1_RESET_MASK       (0x20U)
#define RSTCTL3_SYSRSTSTAT_CPU1_RESET_SHIFT      (5U)
/*! CPU1_RESET - CPU1 Reset
 *  0b0..No CPU1 reset event is detected.
 *  0b1..CPU1 reset is detected.
 */
#define RSTCTL3_SYSRSTSTAT_CPU1_RESET(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_CPU1_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_CPU1_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_WWDT0_RESET_MASK      (0x40U)
#define RSTCTL3_SYSRSTSTAT_WWDT0_RESET_SHIFT     (6U)
/*! WWDT0_RESET - WWDT0 Reset
 *  0b0..No WWDT0 reset event is detected.
 *  0b1..WWDT0 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_WWDT0_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_WWDT0_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_WWDT0_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_WWDT1_RESET_MASK      (0x80U)
#define RSTCTL3_SYSRSTSTAT_WWDT1_RESET_SHIFT     (7U)
/*! WWDT1_RESET - WWDT1 Reset
 *  0b0..No WWDT1 reset event is detected
 *  0b1..WWDT1 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_WWDT1_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_WWDT1_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_WWDT1_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_WWDT2_RESET_MASK      (0x100U)
#define RSTCTL3_SYSRSTSTAT_WWDT2_RESET_SHIFT     (8U)
/*! WWDT2_RESET - WWDT2 Reset
 *  0b0..No WWDT2 reset event is detected.
 *  0b1..WWDT2 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_WWDT2_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_WWDT2_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_WWDT2_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_WWDT3_RESET_MASK      (0x200U)
#define RSTCTL3_SYSRSTSTAT_WWDT3_RESET_SHIFT     (9U)
/*! WWDT3_RESET - WWDT3 Reset
 *  0b0..No WWDT3 reset event is detected.
 *  0b1..WWDT3 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_WWDT3_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_WWDT3_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_WWDT3_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_CDOG0_RESET_MASK      (0x400U)
#define RSTCTL3_SYSRSTSTAT_CDOG0_RESET_SHIFT     (10U)
/*! CDOG0_RESET - CDOG0 Reset
 *  0b0..No CDOG0 reset event is detected.
 *  0b1..CDOG0 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_CDOG0_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_CDOG0_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_CDOG0_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_CDOG1_RESET_MASK      (0x800U)
#define RSTCTL3_SYSRSTSTAT_CDOG1_RESET_SHIFT     (11U)
/*! CDOG1_RESET - CDOG1 Reset
 *  0b0..No CDOG1 reset event is detected.
 *  0b1..CDOG1 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_CDOG1_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_CDOG1_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_CDOG1_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_CDOG2_RESET_MASK      (0x1000U)
#define RSTCTL3_SYSRSTSTAT_CDOG2_RESET_SHIFT     (12U)
/*! CDOG2_RESET - CDOG2 Reset
 *  0b0..No CDOG2 reset event is detected.
 *  0b1..CDOG2 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_CDOG2_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_CDOG2_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_CDOG2_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_CDOG3_RESET_MASK      (0x2000U)
#define RSTCTL3_SYSRSTSTAT_CDOG3_RESET_SHIFT     (13U)
/*! CDOG3_RESET - CDOG3 Reset
 *  0b0..No CDOG3 reset event is detected.
 *  0b1..CDOG3 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_CDOG3_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_CDOG3_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_CDOG3_RESET_MASK)

#define RSTCTL3_SYSRSTSTAT_CDOG4_RESET_MASK      (0x4000U)
#define RSTCTL3_SYSRSTSTAT_CDOG4_RESET_SHIFT     (14U)
/*! CDOG4_RESET - CDOG4 Reset
 *  0b0..No CDOG4 reset event is detected.
 *  0b1..CDOG4 reset event is detected.
 */
#define RSTCTL3_SYSRSTSTAT_CDOG4_RESET(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_CDOG4_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_CDOG4_RESET_MASK)
/*! @} */

/*! @name DOMRSTSTAT - Domain Reset Status */
/*! @{ */

#define RSTCTL3_DOMRSTSTAT_VDD1_SENSE_STAT_MASK  (0x1U)
#define RSTCTL3_DOMRSTSTAT_VDD1_SENSE_STAT_SHIFT (0U)
/*! VDD1_SENSE_STAT - VDD1_SENSE Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL3_DOMRSTSTAT_VDD1_SENSE_STAT(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL3_DOMRSTSTAT_VDD1_SENSE_STAT_SHIFT)) & RSTCTL3_DOMRSTSTAT_VDD1_SENSE_STAT_MASK)

#define RSTCTL3_DOMRSTSTAT_COM2_STAT_MASK        (0x2U)
#define RSTCTL3_DOMRSTSTAT_COM2_STAT_SHIFT       (1U)
/*! COM2_STAT - VDD2_COM (Main) Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL3_DOMRSTSTAT_COM2_STAT(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL3_DOMRSTSTAT_COM2_STAT_SHIFT)) & RSTCTL3_DOMRSTSTAT_COM2_STAT_MASK)

#define RSTCTL3_DOMRSTSTAT_COMN_STAT_MASK        (0x4U)
#define RSTCTL3_DOMRSTSTAT_COMN_STAT_SHIFT       (2U)
/*! COMN_STAT - VDDN_COM Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL3_DOMRSTSTAT_COMN_STAT(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL3_DOMRSTSTAT_COMN_STAT_SHIFT)) & RSTCTL3_DOMRSTSTAT_COMN_STAT_MASK)

#define RSTCTL3_DOMRSTSTAT_COMP_STAT_MASK        (0x8U)
#define RSTCTL3_DOMRSTSTAT_COMP_STAT_SHIFT       (3U)
/*! COMP_STAT - VDD2_COMP Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL3_DOMRSTSTAT_COMP_STAT(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL3_DOMRSTSTAT_COMP_STAT_SHIFT)) & RSTCTL3_DOMRSTSTAT_COMP_STAT_MASK)

#define RSTCTL3_DOMRSTSTAT_DSP_STAT_MASK         (0x10U)
#define RSTCTL3_DOMRSTSTAT_DSP_STAT_SHIFT        (4U)
/*! DSP_STAT - VDD2_DSP Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL3_DOMRSTSTAT_DSP_STAT(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL3_DOMRSTSTAT_DSP_STAT_SHIFT)) & RSTCTL3_DOMRSTSTAT_DSP_STAT_MASK)

#define RSTCTL3_DOMRSTSTAT_MEDIA_STAT_MASK       (0x20U)
#define RSTCTL3_DOMRSTSTAT_MEDIA_STAT_SHIFT      (5U)
/*! MEDIA_STAT - VDD2_MEDIA Domain Reset State
 *  0b0..The domain is in reset state.
 *  0b1..The domain is in normal run state.
 */
#define RSTCTL3_DOMRSTSTAT_MEDIA_STAT(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL3_DOMRSTSTAT_MEDIA_STAT_SHIFT)) & RSTCTL3_DOMRSTSTAT_MEDIA_STAT_MASK)
/*! @} */

/*! @name PRSTCTL0 - Sense Domain Peripheral Reset Control 0 */
/*! @{ */

#define RSTCTL3_PRSTCTL0_IOPCTL1_MASK            (0x1U)
#define RSTCTL3_PRSTCTL0_IOPCTL1_SHIFT           (0U)
/*! IOPCTL1 - IOPCTL1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL0_IOPCTL1(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL0_IOPCTL1_SHIFT)) & RSTCTL3_PRSTCTL0_IOPCTL1_MASK)

#define RSTCTL3_PRSTCTL0_CPU1_MASK               (0x80000000U)
#define RSTCTL3_PRSTCTL0_CPU1_SHIFT              (31U)
/*! CPU1 - CPU1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL0_CPU1(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL0_CPU1_SHIFT)) & RSTCTL3_PRSTCTL0_CPU1_MASK)
/*! @} */

/*! @name PRSTCTL1 - Sense Domain Peripheral Reset Control 1 */
/*! @{ */

#define RSTCTL3_PRSTCTL1_MU0_MASK                (0x2U)
#define RSTCTL3_PRSTCTL1_MU0_SHIFT               (1U)
/*! MU0 - MU0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_MU0(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_MU0_SHIFT)) & RSTCTL3_PRSTCTL1_MU0_MASK)

#define RSTCTL3_PRSTCTL1_MU1_MASK                (0x4U)
#define RSTCTL3_PRSTCTL1_MU1_SHIFT               (2U)
/*! MU1 - MU1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_MU1(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_MU1_SHIFT)) & RSTCTL3_PRSTCTL1_MU1_MASK)

#define RSTCTL3_PRSTCTL1_MU2_MASK                (0x8U)
#define RSTCTL3_PRSTCTL1_MU2_SHIFT               (3U)
/*! MU2 - MU2 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_MU2(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_MU2_SHIFT)) & RSTCTL3_PRSTCTL1_MU2_MASK)

#define RSTCTL3_PRSTCTL1_SEMA42_0_MASK           (0x20U)
#define RSTCTL3_PRSTCTL1_SEMA42_0_SHIFT          (5U)
/*! SEMA42_0 - SEMA42_0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SEMA42_0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SEMA42_0_SHIFT)) & RSTCTL3_PRSTCTL1_SEMA42_0_MASK)

#define RSTCTL3_PRSTCTL1_ADC0_MASK               (0x40U)
#define RSTCTL3_PRSTCTL1_ADC0_SHIFT              (6U)
/*! ADC0 - ADC0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_ADC0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_ADC0_SHIFT)) & RSTCTL3_PRSTCTL1_ADC0_MASK)

#define RSTCTL3_PRSTCTL1_SDADC_MASK              (0x80U)
#define RSTCTL3_PRSTCTL1_SDADC_SHIFT             (7U)
/*! SDADC - SDADC Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SDADC(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SDADC_SHIFT)) & RSTCTL3_PRSTCTL1_SDADC_MASK)

#define RSTCTL3_PRSTCTL1_ACMP0_MASK              (0x100U)
#define RSTCTL3_PRSTCTL1_ACMP0_SHIFT             (8U)
/*! ACMP0 - ACMP0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_ACMP0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_ACMP0_SHIFT)) & RSTCTL3_PRSTCTL1_ACMP0_MASK)

#define RSTCTL3_PRSTCTL1_MICFIL_MASK             (0x200U)
#define RSTCTL3_PRSTCTL1_MICFIL_SHIFT            (9U)
/*! MICFIL - MICFIL Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_MICFIL(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_MICFIL_SHIFT)) & RSTCTL3_PRSTCTL1_MICFIL_MASK)

#define RSTCTL3_PRSTCTL1_INPUTMUX1_MASK          (0x4000U)
#define RSTCTL3_PRSTCTL1_INPUTMUX1_SHIFT         (14U)
/*! INPUTMUX1 - INPUTMUX1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_INPUTMUX1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_INPUTMUX1_SHIFT)) & RSTCTL3_PRSTCTL1_INPUTMUX1_MASK)

#define RSTCTL3_PRSTCTL1_LPI2C15_MASK            (0x40000U)
#define RSTCTL3_PRSTCTL1_LPI2C15_SHIFT           (18U)
/*! LPI2C15 - LPI2C15 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_LPI2C15(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_LPI2C15_SHIFT)) & RSTCTL3_PRSTCTL1_LPI2C15_MASK)
/*! @} */

/*! @name PRSTCTL0_SET - Sense Domain Peripheral Reset Control 0 SET */
/*! @{ */

#define RSTCTL3_PRSTCTL0_SET_IOPCTL1_MASK        (0x1U)
#define RSTCTL3_PRSTCTL0_SET_IOPCTL1_SHIFT       (0U)
/*! IOPCTL1 - IOPCTL1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL0_SET_IOPCTL1(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL0_SET_IOPCTL1_SHIFT)) & RSTCTL3_PRSTCTL0_SET_IOPCTL1_MASK)

#define RSTCTL3_PRSTCTL0_SET_CPU1_MASK           (0x80000000U)
#define RSTCTL3_PRSTCTL0_SET_CPU1_SHIFT          (31U)
/*! CPU1 - CPU1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL0_SET_CPU1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL0_SET_CPU1_SHIFT)) & RSTCTL3_PRSTCTL0_SET_CPU1_MASK)
/*! @} */

/*! @name PRSTCTL1_SET - Sense Domain Peripheral Reset Control 1 SET */
/*! @{ */

#define RSTCTL3_PRSTCTL1_SET_MU0_MASK            (0x2U)
#define RSTCTL3_PRSTCTL1_SET_MU0_SHIFT           (1U)
/*! MU0 - MU0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_MU0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_MU0_SHIFT)) & RSTCTL3_PRSTCTL1_SET_MU0_MASK)

#define RSTCTL3_PRSTCTL1_SET_MU1_MASK            (0x4U)
#define RSTCTL3_PRSTCTL1_SET_MU1_SHIFT           (2U)
/*! MU1 - MU1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_MU1(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_MU1_SHIFT)) & RSTCTL3_PRSTCTL1_SET_MU1_MASK)

#define RSTCTL3_PRSTCTL1_SET_MU2_MASK            (0x8U)
#define RSTCTL3_PRSTCTL1_SET_MU2_SHIFT           (3U)
/*! MU2 - MU2 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_MU2(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_MU2_SHIFT)) & RSTCTL3_PRSTCTL1_SET_MU2_MASK)

#define RSTCTL3_PRSTCTL1_SET_SEMA42_0_MASK       (0x20U)
#define RSTCTL3_PRSTCTL1_SET_SEMA42_0_SHIFT      (5U)
/*! SEMA42_0 - SEMA42_0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_SEMA42_0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_SEMA42_0_SHIFT)) & RSTCTL3_PRSTCTL1_SET_SEMA42_0_MASK)

#define RSTCTL3_PRSTCTL1_SET_ADC0_MASK           (0x40U)
#define RSTCTL3_PRSTCTL1_SET_ADC0_SHIFT          (6U)
/*! ADC0 - ADC0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_ADC0_SHIFT)) & RSTCTL3_PRSTCTL1_SET_ADC0_MASK)

#define RSTCTL3_PRSTCTL1_SET_SDADC_MASK          (0x80U)
#define RSTCTL3_PRSTCTL1_SET_SDADC_SHIFT         (7U)
/*! SDADC - SDADC Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_SDADC(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_SDADC_SHIFT)) & RSTCTL3_PRSTCTL1_SET_SDADC_MASK)

#define RSTCTL3_PRSTCTL1_SET_ACMP0_MASK          (0x100U)
#define RSTCTL3_PRSTCTL1_SET_ACMP0_SHIFT         (8U)
/*! ACMP0 - ACMP0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_ACMP0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_ACMP0_SHIFT)) & RSTCTL3_PRSTCTL1_SET_ACMP0_MASK)

#define RSTCTL3_PRSTCTL1_SET_MICFIL_MASK         (0x200U)
#define RSTCTL3_PRSTCTL1_SET_MICFIL_SHIFT        (9U)
/*! MICFIL - MICFIL Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_MICFIL(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_MICFIL_SHIFT)) & RSTCTL3_PRSTCTL1_SET_MICFIL_MASK)

#define RSTCTL3_PRSTCTL1_SET_INPUTMUX1_MASK      (0x4000U)
#define RSTCTL3_PRSTCTL1_SET_INPUTMUX1_SHIFT     (14U)
/*! INPUTMUX1 - INPUTMUX1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_INPUTMUX1(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_INPUTMUX1_SHIFT)) & RSTCTL3_PRSTCTL1_SET_INPUTMUX1_MASK)

#define RSTCTL3_PRSTCTL1_SET_LPI2C15_MASK        (0x40000U)
#define RSTCTL3_PRSTCTL1_SET_LPI2C15_SHIFT       (18U)
/*! LPI2C15 - LPI2C15 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL3_PRSTCTL1_SET_LPI2C15(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_SET_LPI2C15_SHIFT)) & RSTCTL3_PRSTCTL1_SET_LPI2C15_MASK)
/*! @} */

/*! @name PRSTCTL0_CLR - Sense Domain Peripheral Reset Control 0 CLR */
/*! @{ */

#define RSTCTL3_PRSTCTL0_CLR_IOPCTL1_MASK        (0x1U)
#define RSTCTL3_PRSTCTL0_CLR_IOPCTL1_SHIFT       (0U)
/*! IOPCTL1 - IOPCTL1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL0_CLR_IOPCTL1(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL0_CLR_IOPCTL1_SHIFT)) & RSTCTL3_PRSTCTL0_CLR_IOPCTL1_MASK)

#define RSTCTL3_PRSTCTL0_CLR_CPU1_MASK           (0x80000000U)
#define RSTCTL3_PRSTCTL0_CLR_CPU1_SHIFT          (31U)
/*! CPU1 - CPU1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL0_CLR_CPU1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL0_CLR_CPU1_SHIFT)) & RSTCTL3_PRSTCTL0_CLR_CPU1_MASK)
/*! @} */

/*! @name PRSTCTL1_CLR - Sense Peripheral Reset Control 1 CLR */
/*! @{ */

#define RSTCTL3_PRSTCTL1_CLR_MU0_MASK            (0x2U)
#define RSTCTL3_PRSTCTL1_CLR_MU0_SHIFT           (1U)
/*! MU0 - MU0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_MU0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_MU0_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_MU0_MASK)

#define RSTCTL3_PRSTCTL1_CLR_MU1_MASK            (0x4U)
#define RSTCTL3_PRSTCTL1_CLR_MU1_SHIFT           (2U)
/*! MU1 - MU1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_MU1(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_MU1_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_MU1_MASK)

#define RSTCTL3_PRSTCTL1_CLR_MU2_MASK            (0x8U)
#define RSTCTL3_PRSTCTL1_CLR_MU2_SHIFT           (3U)
/*! MU2 - MU2 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_MU2(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_MU2_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_MU2_MASK)

#define RSTCTL3_PRSTCTL1_CLR_SEMA42_0_MASK       (0x20U)
#define RSTCTL3_PRSTCTL1_CLR_SEMA42_0_SHIFT      (5U)
/*! SEMA42_0 - SEMA42_0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_SEMA42_0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_SEMA42_0_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_SEMA42_0_MASK)

#define RSTCTL3_PRSTCTL1_CLR_ADC0_MASK           (0x40U)
#define RSTCTL3_PRSTCTL1_CLR_ADC0_SHIFT          (6U)
/*! ADC0 - ADC0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_ADC0_MASK)

#define RSTCTL3_PRSTCTL1_CLR_SDADC_MASK          (0x80U)
#define RSTCTL3_PRSTCTL1_CLR_SDADC_SHIFT         (7U)
/*! SDADC - SDADC Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_SDADC(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_SDADC_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_SDADC_MASK)

#define RSTCTL3_PRSTCTL1_CLR_ACMP0_MASK          (0x100U)
#define RSTCTL3_PRSTCTL1_CLR_ACMP0_SHIFT         (8U)
/*! ACMP0 - ACMP0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_ACMP0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_ACMP0_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_ACMP0_MASK)

#define RSTCTL3_PRSTCTL1_CLR_MICFIL_MASK         (0x200U)
#define RSTCTL3_PRSTCTL1_CLR_MICFIL_SHIFT        (9U)
/*! MICFIL - MICFIL Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_MICFIL(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_MICFIL_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_MICFIL_MASK)

#define RSTCTL3_PRSTCTL1_CLR_INPUTMUX1_MASK      (0x4000U)
#define RSTCTL3_PRSTCTL1_CLR_INPUTMUX1_SHIFT     (14U)
/*! INPUTMUX1 - INPUTMUX1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_INPUTMUX1(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_INPUTMUX1_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_INPUTMUX1_MASK)

#define RSTCTL3_PRSTCTL1_CLR_LPI2C15_MASK        (0x40000U)
#define RSTCTL3_PRSTCTL1_CLR_LPI2C15_SHIFT       (18U)
/*! LPI2C15 - LPI2C15 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL3_PRSTCTL1_CLR_LPI2C15(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL3_PRSTCTL1_CLR_LPI2C15_SHIFT)) & RSTCTL3_PRSTCTL1_CLR_LPI2C15_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RSTCTL3_Register_Masks */


/* RSTCTL3 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RSTCTL3 base address */
  #define RSTCTL3_BASE                             (0x50060000u)
  /** Peripheral RSTCTL3 base address */
  #define RSTCTL3_BASE_NS                          (0x40060000u)
  /** Peripheral RSTCTL3 base pointer */
  #define RSTCTL3                                  ((RSTCTL3_Type *)RSTCTL3_BASE)
  /** Peripheral RSTCTL3 base pointer */
  #define RSTCTL3_NS                               ((RSTCTL3_Type *)RSTCTL3_BASE_NS)
  /** Array initializer of RSTCTL3 peripheral base addresses */
  #define RSTCTL3_BASE_ADDRS                       { RSTCTL3_BASE }
  /** Array initializer of RSTCTL3 peripheral base pointers */
  #define RSTCTL3_BASE_PTRS                        { RSTCTL3 }
  /** Array initializer of RSTCTL3 peripheral base addresses */
  #define RSTCTL3_BASE_ADDRS_NS                    { RSTCTL3_BASE_NS }
  /** Array initializer of RSTCTL3 peripheral base pointers */
  #define RSTCTL3_BASE_PTRS_NS                     { RSTCTL3_NS }
#else
  /** Peripheral RSTCTL3 base address */
  #define RSTCTL3_BASE                             (0x40060000u)
  /** Peripheral RSTCTL3 base pointer */
  #define RSTCTL3                                  ((RSTCTL3_Type *)RSTCTL3_BASE)
  /** Array initializer of RSTCTL3 peripheral base addresses */
  #define RSTCTL3_BASE_ADDRS                       { RSTCTL3_BASE }
  /** Array initializer of RSTCTL3 peripheral base pointers */
  #define RSTCTL3_BASE_PTRS                        { RSTCTL3 }
#endif

/*!
 * @}
 */ /* end of group RSTCTL3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RSTCTL4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL4_Peripheral_Access_Layer RSTCTL4 Peripheral Access Layer
 * @{
 */

/** RSTCTL4 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PRSTCTL0;                          /**< Media Domain Peripheral Reset Control 0, offset: 0x10 */
  __IO uint32_t PRSTCTL1;                          /**< Media Domain (Interface) Peripheral Reset Control 1, offset: 0x14 */
       uint8_t RESERVED_1[40];
  __O  uint32_t PRSTCTL0_SET;                      /**< Media Domain Peripheral Reset Control 0 SET, offset: 0x40 */
  __O  uint32_t PRSTCTL1_SET;                      /**< Media Domain (Interface) Peripheral Reset Control 1 SET, offset: 0x44 */
       uint8_t RESERVED_2[40];
  __O  uint32_t PRSTCTL0_CLR;                      /**< Media Domain Peripheral Reset Control 0 CLR, offset: 0x70 */
  __O  uint32_t PRSTCTL1_CLR;                      /**< Media Domain (Interface) Peripheral Reset Control 1 CLR, offset: 0x74 */
} RSTCTL4_Type;

/* ----------------------------------------------------------------------------
   -- RSTCTL4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL4_Register_Masks RSTCTL4 Register Masks
 * @{
 */

/*! @name PRSTCTL0 - Media Domain Peripheral Reset Control 0 */
/*! @{ */

#define RSTCTL4_PRSTCTL0_VGPU_MASK               (0x4U)
#define RSTCTL4_PRSTCTL0_VGPU_SHIFT              (2U)
/*! VGPU - VGPU Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_VGPU(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_VGPU_SHIFT)) & RSTCTL4_PRSTCTL0_VGPU_MASK)

#define RSTCTL4_PRSTCTL0_LCDIF_MASK              (0x8U)
#define RSTCTL4_PRSTCTL0_LCDIF_SHIFT             (3U)
/*! LCDIF - LCDIF Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_LCDIF(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_LCDIF_SHIFT)) & RSTCTL4_PRSTCTL0_LCDIF_MASK)

#define RSTCTL4_PRSTCTL0_MIPI_DSI_HOST_MASK      (0x10U)
#define RSTCTL4_PRSTCTL0_MIPI_DSI_HOST_SHIFT     (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_MIPI_DSI_HOST(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_MIPI_DSI_HOST_SHIFT)) & RSTCTL4_PRSTCTL0_MIPI_DSI_HOST_MASK)

#define RSTCTL4_PRSTCTL0_EZHV_MASK               (0x20U)
#define RSTCTL4_PRSTCTL0_EZHV_SHIFT              (5U)
/*! EZHV - EZHV Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_EZHV(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_EZHV_SHIFT)) & RSTCTL4_PRSTCTL0_EZHV_MASK)

#define RSTCTL4_PRSTCTL0_JPEGDEC_MASK            (0x40U)
#define RSTCTL4_PRSTCTL0_JPEGDEC_SHIFT           (6U)
/*! JPEGDEC - JPEGDEC Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_JPEGDEC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_JPEGDEC_SHIFT)) & RSTCTL4_PRSTCTL0_JPEGDEC_MASK)

#define RSTCTL4_PRSTCTL0_PNGDEC_MASK             (0x80U)
#define RSTCTL4_PRSTCTL0_PNGDEC_SHIFT            (7U)
/*! PNGDEC - PNGDEC Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_PNGDEC(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_PNGDEC_SHIFT)) & RSTCTL4_PRSTCTL0_PNGDEC_MASK)

#define RSTCTL4_PRSTCTL0_XSPI2_MASK              (0x100U)
#define RSTCTL4_PRSTCTL0_XSPI2_SHIFT             (8U)
/*! XSPI2 - XSPI2 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_XSPI2(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_XSPI2_SHIFT)) & RSTCTL4_PRSTCTL0_XSPI2_MASK)

#define RSTCTL4_PRSTCTL0_LPSPI14_MASK            (0x2000U)
#define RSTCTL4_PRSTCTL0_LPSPI14_SHIFT           (13U)
/*! LPSPI14 - LPSPI14 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_LPSPI14(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_LPSPI14_SHIFT)) & RSTCTL4_PRSTCTL0_LPSPI14_MASK)

#define RSTCTL4_PRSTCTL0_LPSPI16_MASK            (0x4000U)
#define RSTCTL4_PRSTCTL0_LPSPI16_SHIFT           (14U)
/*! LPSPI16 - LPSPI16 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_LPSPI16(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_LPSPI16_SHIFT)) & RSTCTL4_PRSTCTL0_LPSPI16_MASK)

#define RSTCTL4_PRSTCTL0_FLEXIO0_MASK            (0x8000U)
#define RSTCTL4_PRSTCTL0_FLEXIO0_SHIFT           (15U)
/*! FLEXIO0 - FLEXIO0 Reset
 *  0b1..Sets reset.
 *  0b0..Clears reset.
 */
#define RSTCTL4_PRSTCTL0_FLEXIO0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_FLEXIO0_SHIFT)) & RSTCTL4_PRSTCTL0_FLEXIO0_MASK)
/*! @} */

/*! @name PRSTCTL1 - Media Domain (Interface) Peripheral Reset Control 1 */
/*! @{ */

#define RSTCTL4_PRSTCTL1_USB0_MASK               (0x1U)
#define RSTCTL4_PRSTCTL1_USB0_SHIFT              (0U)
/*! USB0 - USB0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_USB0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_USB0_SHIFT)) & RSTCTL4_PRSTCTL1_USB0_MASK)

#define RSTCTL4_PRSTCTL1_USBPHY0_MASK            (0x2U)
#define RSTCTL4_PRSTCTL1_USBPHY0_SHIFT           (1U)
/*! USBPHY0 - USBPHY0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_USBPHY0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_USBPHY0_SHIFT)) & RSTCTL4_PRSTCTL1_USBPHY0_MASK)

#define RSTCTL4_PRSTCTL1_USB1_MASK               (0x4U)
#define RSTCTL4_PRSTCTL1_USB1_SHIFT              (2U)
/*! USB1 - USB1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_USB1(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_USB1_SHIFT)) & RSTCTL4_PRSTCTL1_USB1_MASK)

#define RSTCTL4_PRSTCTL1_USDHC0_MASK             (0x10U)
#define RSTCTL4_PRSTCTL1_USDHC0_SHIFT            (4U)
/*! uSDHC0 - uSDHC0 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_USDHC0(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_USDHC0_SHIFT)) & RSTCTL4_PRSTCTL1_USDHC0_MASK)

#define RSTCTL4_PRSTCTL1_USDHC1_MASK             (0x20U)
#define RSTCTL4_PRSTCTL1_USDHC1_SHIFT            (5U)
/*! uSDHC1 - uSDHC1 Reset
 *  0b0..Clears reset.
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_USDHC1(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_USDHC1_SHIFT)) & RSTCTL4_PRSTCTL1_USDHC1_MASK)
/*! @} */

/*! @name PRSTCTL0_SET - Media Domain Peripheral Reset Control 0 SET */
/*! @{ */

#define RSTCTL4_PRSTCTL0_SET_VGPU_MASK           (0x4U)
#define RSTCTL4_PRSTCTL0_SET_VGPU_SHIFT          (2U)
/*! VGPU - VGPU Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_VGPU(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_VGPU_SHIFT)) & RSTCTL4_PRSTCTL0_SET_VGPU_MASK)

#define RSTCTL4_PRSTCTL0_SET_LCDIF_MASK          (0x8U)
#define RSTCTL4_PRSTCTL0_SET_LCDIF_SHIFT         (3U)
/*! LCDIF - LCDIF Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_LCDIF(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_LCDIF_SHIFT)) & RSTCTL4_PRSTCTL0_SET_LCDIF_MASK)

#define RSTCTL4_PRSTCTL0_SET_MIPI_DSI_HOST_MASK  (0x10U)
#define RSTCTL4_PRSTCTL0_SET_MIPI_DSI_HOST_SHIFT (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_MIPI_DSI_HOST(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_MIPI_DSI_HOST_SHIFT)) & RSTCTL4_PRSTCTL0_SET_MIPI_DSI_HOST_MASK)

#define RSTCTL4_PRSTCTL0_SET_EZHV_MASK           (0x20U)
#define RSTCTL4_PRSTCTL0_SET_EZHV_SHIFT          (5U)
/*! EZHV - EZHV Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_EZHV(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_EZHV_SHIFT)) & RSTCTL4_PRSTCTL0_SET_EZHV_MASK)

#define RSTCTL4_PRSTCTL0_SET_JPEGDEC_MASK        (0x40U)
#define RSTCTL4_PRSTCTL0_SET_JPEGDEC_SHIFT       (6U)
/*! JPEGDEC - JPEGDEC Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_JPEGDEC(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_JPEGDEC_SHIFT)) & RSTCTL4_PRSTCTL0_SET_JPEGDEC_MASK)

#define RSTCTL4_PRSTCTL0_SET_PNGDEC_MASK         (0x80U)
#define RSTCTL4_PRSTCTL0_SET_PNGDEC_SHIFT        (7U)
/*! PNGDEC - PNGDEC Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_PNGDEC(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_PNGDEC_SHIFT)) & RSTCTL4_PRSTCTL0_SET_PNGDEC_MASK)

#define RSTCTL4_PRSTCTL0_SET_XSPI2_MASK          (0x100U)
#define RSTCTL4_PRSTCTL0_SET_XSPI2_SHIFT         (8U)
/*! XSPI2 - XSPI2 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_XSPI2(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_XSPI2_SHIFT)) & RSTCTL4_PRSTCTL0_SET_XSPI2_MASK)

#define RSTCTL4_PRSTCTL0_SET_LPSPI14_MASK        (0x2000U)
#define RSTCTL4_PRSTCTL0_SET_LPSPI14_SHIFT       (13U)
/*! LPSPI14 - LPSPI14 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_LPSPI14(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_LPSPI14_SHIFT)) & RSTCTL4_PRSTCTL0_SET_LPSPI14_MASK)

#define RSTCTL4_PRSTCTL0_SET_LPSPI16_MASK        (0x4000U)
#define RSTCTL4_PRSTCTL0_SET_LPSPI16_SHIFT       (14U)
/*! LPSPI16 - LPSPI16 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_LPSPI16(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_LPSPI16_SHIFT)) & RSTCTL4_PRSTCTL0_SET_LPSPI16_MASK)

#define RSTCTL4_PRSTCTL0_SET_FLEXIO0_MASK        (0x8000U)
#define RSTCTL4_PRSTCTL0_SET_FLEXIO0_SHIFT       (15U)
/*! FLEXIO0 - FLEXIO0 Reset
 *  0b1..Sets reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_SET_FLEXIO0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_SET_FLEXIO0_SHIFT)) & RSTCTL4_PRSTCTL0_SET_FLEXIO0_MASK)
/*! @} */

/*! @name PRSTCTL1_SET - Media Domain (Interface) Peripheral Reset Control 1 SET */
/*! @{ */

#define RSTCTL4_PRSTCTL1_SET_USB0_MASK           (0x1U)
#define RSTCTL4_PRSTCTL1_SET_USB0_SHIFT          (0U)
/*! USB0 - USB0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_SET_USB0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_SET_USB0_SHIFT)) & RSTCTL4_PRSTCTL1_SET_USB0_MASK)

#define RSTCTL4_PRSTCTL1_SET_USBPHY0_MASK        (0x2U)
#define RSTCTL4_PRSTCTL1_SET_USBPHY0_SHIFT       (1U)
/*! USBPHY0 - USBPHY0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_SET_USBPHY0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_SET_USBPHY0_SHIFT)) & RSTCTL4_PRSTCTL1_SET_USBPHY0_MASK)

#define RSTCTL4_PRSTCTL1_SET_USB1_MASK           (0x4U)
#define RSTCTL4_PRSTCTL1_SET_USB1_SHIFT          (2U)
/*! USB1 - USB1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_SET_USB1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_SET_USB1_SHIFT)) & RSTCTL4_PRSTCTL1_SET_USB1_MASK)

#define RSTCTL4_PRSTCTL1_SET_USDHC0_MASK         (0x10U)
#define RSTCTL4_PRSTCTL1_SET_USDHC0_SHIFT        (4U)
/*! uSDHC0 - uSDHC0 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_SET_USDHC0(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_SET_USDHC0_SHIFT)) & RSTCTL4_PRSTCTL1_SET_USDHC0_MASK)

#define RSTCTL4_PRSTCTL1_SET_USDHC1_MASK         (0x20U)
#define RSTCTL4_PRSTCTL1_SET_USDHC1_SHIFT        (5U)
/*! uSDHC1 - uSDHC1 Reset
 *  0b0..No effect
 *  0b1..Sets reset.
 */
#define RSTCTL4_PRSTCTL1_SET_USDHC1(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_SET_USDHC1_SHIFT)) & RSTCTL4_PRSTCTL1_SET_USDHC1_MASK)
/*! @} */

/*! @name PRSTCTL0_CLR - Media Domain Peripheral Reset Control 0 CLR */
/*! @{ */

#define RSTCTL4_PRSTCTL0_CLR_VGPU_MASK           (0x4U)
#define RSTCTL4_PRSTCTL0_CLR_VGPU_SHIFT          (2U)
/*! VGPU - VGPU Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_VGPU(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_VGPU_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_VGPU_MASK)

#define RSTCTL4_PRSTCTL0_CLR_LCDIF_MASK          (0x8U)
#define RSTCTL4_PRSTCTL0_CLR_LCDIF_SHIFT         (3U)
/*! LCDIF - LCDIF Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_LCDIF(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_LCDIF_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_LCDIF_MASK)

#define RSTCTL4_PRSTCTL0_CLR_MIPI_DSI_HOST_MASK  (0x10U)
#define RSTCTL4_PRSTCTL0_CLR_MIPI_DSI_HOST_SHIFT (4U)
/*! MIPI_DSI_HOST - MIPI_DSI_HOST Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_MIPI_DSI_HOST(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_MIPI_DSI_HOST_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_MIPI_DSI_HOST_MASK)

#define RSTCTL4_PRSTCTL0_CLR_EZHV_MASK           (0x20U)
#define RSTCTL4_PRSTCTL0_CLR_EZHV_SHIFT          (5U)
/*! EZHV - EZHV Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_EZHV(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_EZHV_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_EZHV_MASK)

#define RSTCTL4_PRSTCTL0_CLR_JPEGDEC_MASK        (0x40U)
#define RSTCTL4_PRSTCTL0_CLR_JPEGDEC_SHIFT       (6U)
/*! JPEGDEC - JPEGDEC Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_JPEGDEC(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_JPEGDEC_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_JPEGDEC_MASK)

#define RSTCTL4_PRSTCTL0_CLR_PNGDEC_MASK         (0x80U)
#define RSTCTL4_PRSTCTL0_CLR_PNGDEC_SHIFT        (7U)
/*! PNGDEC - PNGDEC Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_PNGDEC(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_PNGDEC_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_PNGDEC_MASK)

#define RSTCTL4_PRSTCTL0_CLR_XSPI2_MASK          (0x100U)
#define RSTCTL4_PRSTCTL0_CLR_XSPI2_SHIFT         (8U)
/*! XSPI2 - XSPI2 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_XSPI2(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_XSPI2_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_XSPI2_MASK)

#define RSTCTL4_PRSTCTL0_CLR_LPSPI14_MASK        (0x2000U)
#define RSTCTL4_PRSTCTL0_CLR_LPSPI14_SHIFT       (13U)
/*! LPSPI14 - LPSPI14 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_LPSPI14(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_LPSPI14_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_LPSPI14_MASK)

#define RSTCTL4_PRSTCTL0_CLR_LPSPI16_MASK        (0x4000U)
#define RSTCTL4_PRSTCTL0_CLR_LPSPI16_SHIFT       (14U)
/*! LPSPI16 - LPSPI16 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_LPSPI16(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_LPSPI16_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_LPSPI16_MASK)

#define RSTCTL4_PRSTCTL0_CLR_FLEXIO0_MASK        (0x8000U)
#define RSTCTL4_PRSTCTL0_CLR_FLEXIO0_SHIFT       (15U)
/*! FLEXIO0 - FLEXIO0 Reset
 *  0b1..Clears reset.
 *  0b0..No effect
 */
#define RSTCTL4_PRSTCTL0_CLR_FLEXIO0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL0_CLR_FLEXIO0_SHIFT)) & RSTCTL4_PRSTCTL0_CLR_FLEXIO0_MASK)
/*! @} */

/*! @name PRSTCTL1_CLR - Media Domain (Interface) Peripheral Reset Control 1 CLR */
/*! @{ */

#define RSTCTL4_PRSTCTL1_CLR_USB0_MASK           (0x1U)
#define RSTCTL4_PRSTCTL1_CLR_USB0_SHIFT          (0U)
/*! USB0 - USB0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL4_PRSTCTL1_CLR_USB0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_CLR_USB0_SHIFT)) & RSTCTL4_PRSTCTL1_CLR_USB0_MASK)

#define RSTCTL4_PRSTCTL1_CLR_USBPHY0_MASK        (0x2U)
#define RSTCTL4_PRSTCTL1_CLR_USBPHY0_SHIFT       (1U)
/*! USBPHY0 - USBPHY0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL4_PRSTCTL1_CLR_USBPHY0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_CLR_USBPHY0_SHIFT)) & RSTCTL4_PRSTCTL1_CLR_USBPHY0_MASK)

#define RSTCTL4_PRSTCTL1_CLR_USB1_MASK           (0x4U)
#define RSTCTL4_PRSTCTL1_CLR_USB1_SHIFT          (2U)
/*! USB1 - USB1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL4_PRSTCTL1_CLR_USB1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_CLR_USB1_SHIFT)) & RSTCTL4_PRSTCTL1_CLR_USB1_MASK)

#define RSTCTL4_PRSTCTL1_CLR_USDHC0_MASK         (0x10U)
#define RSTCTL4_PRSTCTL1_CLR_USDHC0_SHIFT        (4U)
/*! uSDHC0 - uSDHC0 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL4_PRSTCTL1_CLR_USDHC0(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_CLR_USDHC0_SHIFT)) & RSTCTL4_PRSTCTL1_CLR_USDHC0_MASK)

#define RSTCTL4_PRSTCTL1_CLR_USDHC1_MASK         (0x20U)
#define RSTCTL4_PRSTCTL1_CLR_USDHC1_SHIFT        (5U)
/*! uSDHC1 - uSDHC1 Reset
 *  0b0..No effect
 *  0b1..Clears reset.
 */
#define RSTCTL4_PRSTCTL1_CLR_USDHC1(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL4_PRSTCTL1_CLR_USDHC1_SHIFT)) & RSTCTL4_PRSTCTL1_CLR_USDHC1_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RSTCTL4_Register_Masks */


/* RSTCTL4 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RSTCTL4 base address */
  #define RSTCTL4_BASE                             (0x500A0000u)
  /** Peripheral RSTCTL4 base address */
  #define RSTCTL4_BASE_NS                          (0x400A0000u)
  /** Peripheral RSTCTL4 base pointer */
  #define RSTCTL4                                  ((RSTCTL4_Type *)RSTCTL4_BASE)
  /** Peripheral RSTCTL4 base pointer */
  #define RSTCTL4_NS                               ((RSTCTL4_Type *)RSTCTL4_BASE_NS)
  /** Array initializer of RSTCTL4 peripheral base addresses */
  #define RSTCTL4_BASE_ADDRS                       { RSTCTL4_BASE }
  /** Array initializer of RSTCTL4 peripheral base pointers */
  #define RSTCTL4_BASE_PTRS                        { RSTCTL4 }
  /** Array initializer of RSTCTL4 peripheral base addresses */
  #define RSTCTL4_BASE_ADDRS_NS                    { RSTCTL4_BASE_NS }
  /** Array initializer of RSTCTL4 peripheral base pointers */
  #define RSTCTL4_BASE_PTRS_NS                     { RSTCTL4_NS }
#else
  /** Peripheral RSTCTL4 base address */
  #define RSTCTL4_BASE                             (0x400A0000u)
  /** Peripheral RSTCTL4 base pointer */
  #define RSTCTL4                                  ((RSTCTL4_Type *)RSTCTL4_BASE)
  /** Array initializer of RSTCTL4 peripheral base addresses */
  #define RSTCTL4_BASE_ADDRS                       { RSTCTL4_BASE }
  /** Array initializer of RSTCTL4 peripheral base pointers */
  #define RSTCTL4_BASE_PTRS                        { RSTCTL4 }
#endif

/*!
 * @}
 */ /* end of group RSTCTL4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RTC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
 * @{
 */

/** RTC - Register Layout Typedef */
typedef struct {
  __IO uint16_t YEARMON;                           /**< Year and Month Counters, offset: 0x0 */
  __IO uint16_t DAYS;                              /**< Days and Day-of-Week Counters, offset: 0x2 */
  __IO uint16_t HOURMIN;                           /**< Hours and Minutes Counters, offset: 0x4 */
  __IO uint16_t SECONDS;                           /**< Seconds Counters, offset: 0x6 */
  __IO uint16_t ALM_YEARMON;                       /**< Year and Months Alarm, offset: 0x8 */
  __IO uint16_t ALM_DAYS;                          /**< Days Alarm, offset: 0xA */
  __IO uint16_t ALM_HOURMIN;                       /**< Hours and Minutes Alarm, offset: 0xC */
  __IO uint16_t ALM_SECONDS;                       /**< Seconds Alarm, offset: 0xE */
  __IO uint16_t CTRL;                              /**< Control, offset: 0x10 */
  __IO uint16_t STATUS;                            /**< Status, offset: 0x12 */
  __IO uint16_t ISR;                               /**< Interrupt Status, offset: 0x14 */
  __IO uint16_t IER;                               /**< Interrupt Enable, offset: 0x16 */
       uint8_t RESERVED_0[4];
  __I  uint16_t RTC_TEST2;                         /**< Sub Second Counter, offset: 0x1C */
       uint8_t RESERVED_1[4];
  __IO uint16_t DST_HOUR;                          /**< Daylight Saving Hour, offset: 0x22 */
  __IO uint16_t DST_MONTH;                         /**< Daylight Saving Month, offset: 0x24 */
  __IO uint16_t DST_DAY;                           /**< Daylight Saving Day, offset: 0x26 */
  __IO uint16_t COMPEN;                            /**< Compensation, offset: 0x28 */
       uint8_t RESERVED_2[3030];
  __IO uint32_t WAKE_TIMER_CTRL;                   /**< Wake Timer Control (CPU0), offset: 0xC00 */
       uint8_t RESERVED_3[8];
  __IO uint32_t WAKE_TIMER_CNT;                    /**< Wake Timer 0 Counter (CPU0), offset: 0xC0C */
} RTC_Type;

/* ----------------------------------------------------------------------------
   -- RTC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RTC_Register_Masks RTC Register Masks
 * @{
 */

/*! @name YEARMON - Year and Month Counters */
/*! @{ */

#define RTC_YEARMON_MON_CNT_MASK                 (0xFU)
#define RTC_YEARMON_MON_CNT_SHIFT                (0U)
/*! MON_CNT - Month Counter
 *  0b0000, 0b1101, 0b1110, 0b1111..Illegal Value
 *  0b0001..January
 *  0b0010..February
 *  0b0011..March
 *  0b0100..April
 *  0b0101..May
 *  0b0110..June
 *  0b0111..July
 *  0b1000..August
 *  0b1001..September
 *  0b1010..October
 *  0b1011..November
 *  0b1100..December
 */
#define RTC_YEARMON_MON_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK)

#define RTC_YEARMON_YROFST_MASK                  (0xFF00U)
#define RTC_YEARMON_YROFST_SHIFT                 (8U)
/*! YROFST - Year Offset Count Value */
#define RTC_YEARMON_YROFST(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK)
/*! @} */

/*! @name DAYS - Days and Day-of-Week Counters */
/*! @{ */

#define RTC_DAYS_DAY_CNT_MASK                    (0x1FU)
#define RTC_DAYS_DAY_CNT_SHIFT                   (0U)
/*! DAY_CNT - Days Counter Value */
#define RTC_DAYS_DAY_CNT(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK)

#define RTC_DAYS_DOW_MASK                        (0x700U)
#define RTC_DAYS_DOW_SHIFT                       (8U)
/*! DOW - Day of Week Counter Value
 *  0b000..Sunday
 *  0b001..Monday
 *  0b010..Tuesday
 *  0b011..Wednesday
 *  0b100..Thursday
 *  0b101..Friday
 *  0b110..Saturday
 *  0b111..
 */
#define RTC_DAYS_DOW(x)                          (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK)
/*! @} */

/*! @name HOURMIN - Hours and Minutes Counters */
/*! @{ */

#define RTC_HOURMIN_MIN_CNT_MASK                 (0x3FU)
#define RTC_HOURMIN_MIN_CNT_SHIFT                (0U)
/*! MIN_CNT - Minutes Counter Value */
#define RTC_HOURMIN_MIN_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK)

#define RTC_HOURMIN_HOUR_CNT_MASK                (0x1F00U)
#define RTC_HOURMIN_HOUR_CNT_SHIFT               (8U)
/*! HOUR_CNT - Hours Counter Value */
#define RTC_HOURMIN_HOUR_CNT(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK)
/*! @} */

/*! @name SECONDS - Seconds Counters */
/*! @{ */

#define RTC_SECONDS_SEC_CNT_MASK                 (0x3FU)
#define RTC_SECONDS_SEC_CNT_SHIFT                (0U)
/*! SEC_CNT - Seconds Counter Value */
#define RTC_SECONDS_SEC_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK)
/*! @} */

/*! @name ALM_YEARMON - Year and Months Alarm */
/*! @{ */

#define RTC_ALM_YEARMON_ALM_MON_MASK             (0xFU)
#define RTC_ALM_YEARMON_ALM_MON_SHIFT            (0U)
/*! ALM_MON - Months Value for Alarm */
#define RTC_ALM_YEARMON_ALM_MON(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK)

#define RTC_ALM_YEARMON_ALM_YEAR_MASK            (0xFF00U)
#define RTC_ALM_YEARMON_ALM_YEAR_SHIFT           (8U)
/*! ALM_YEAR - Year Value for Alarm */
#define RTC_ALM_YEARMON_ALM_YEAR(x)              (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK)
/*! @} */

/*! @name ALM_DAYS - Days Alarm */
/*! @{ */

#define RTC_ALM_DAYS_ALM_DAY_MASK                (0x1FU)
#define RTC_ALM_DAYS_ALM_DAY_SHIFT               (0U)
/*! ALM_DAY - Days Value for Alarm */
#define RTC_ALM_DAYS_ALM_DAY(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK)
/*! @} */

/*! @name ALM_HOURMIN - Hours and Minutes Alarm */
/*! @{ */

#define RTC_ALM_HOURMIN_ALM_MIN_MASK             (0x3FU)
#define RTC_ALM_HOURMIN_ALM_MIN_SHIFT            (0U)
/*! ALM_MIN - Minutes Value for Alarm */
#define RTC_ALM_HOURMIN_ALM_MIN(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK)

#define RTC_ALM_HOURMIN_ALM_HOUR_MASK            (0x1F00U)
#define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT           (8U)
/*! ALM_HOUR - Hours Value for Alarm */
#define RTC_ALM_HOURMIN_ALM_HOUR(x)              (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK)
/*! @} */

/*! @name ALM_SECONDS - Seconds Alarm */
/*! @{ */

#define RTC_ALM_SECONDS_ALM_SEC_MASK             (0x3FU)
#define RTC_ALM_SECONDS_ALM_SEC_SHIFT            (0U)
/*! ALM_SEC - Seconds Alarm Value */
#define RTC_ALM_SECONDS_ALM_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK)

#define RTC_ALM_SECONDS_DEC_SEC_MASK             (0x100U)
#define RTC_ALM_SECONDS_DEC_SEC_SHIFT            (8U)
/*! DEC_SEC - Decrement Seconds Counter by 1. */
#define RTC_ALM_SECONDS_DEC_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK)

#define RTC_ALM_SECONDS_INC_SEC_MASK             (0x200U)
#define RTC_ALM_SECONDS_INC_SEC_SHIFT            (9U)
/*! INC_SEC - Increment Seconds Counter by 1. */
#define RTC_ALM_SECONDS_INC_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK)
/*! @} */

/*! @name CTRL - Control */
/*! @{ */

#define RTC_CTRL_FINEEN_MASK                     (0x1U)
#define RTC_CTRL_FINEEN_SHIFT                    (0U)
/*! FINEEN - Fine Compensation Enable
 *  0b1..Fine compensation is enabled.
 *  0b0..Fine compensation is disabled
 */
#define RTC_CTRL_FINEEN(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK)

#define RTC_CTRL_COMP_EN_MASK                    (0x2U)
#define RTC_CTRL_COMP_EN_SHIFT                   (1U)
/*! COMP_EN - Compensation Enable
 *  0b0..Coarse compensation is disabled.
 *  0b1..Coarse compensation is enabled.
 */
#define RTC_CTRL_COMP_EN(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK)

#define RTC_CTRL_ALM_MATCH_MASK                  (0xCU)
#define RTC_CTRL_ALM_MATCH_SHIFT                 (2U)
/*! ALM_MATCH - Alarm Match
 *  0b00..Only seconds, minutes, and hours matched.
 *  0b01..Only seconds, minutes, hours, and days matched.
 *  0b10..Only seconds, minutes, hours, days, and months matched.
 *  0b11..Only seconds, minutes, hours, days, months, and year (offset) matched.
 */
#define RTC_CTRL_ALM_MATCH(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK)

#define RTC_CTRL_DST_EN_MASK                     (0x40U)
#define RTC_CTRL_DST_EN_SHIFT                    (6U)
/*! DST_EN - Daylight Saving Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define RTC_CTRL_DST_EN(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK)

#define RTC_CTRL_SWR_MASK                        (0x100U)
#define RTC_CTRL_SWR_SHIFT                       (8U)
/*! SWR - Software Reset
 *  0b0..Software Reset cleared
 *  0b1..Software Reset asserted
 */
#define RTC_CTRL_SWR(x)                          (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK)

#define RTC_CTRL_CLKO_DIS_MASK                   (0x400U)
#define RTC_CTRL_CLKO_DIS_SHIFT                  (10U)
/*! CLKO_DIS - Clock Output Disable
 *  0b0..The selected clock is output to other peripherals.
 *  0b1..The selected clock is not output to other peripherals.
 */
#define RTC_CTRL_CLKO_DIS(x)                     (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKO_DIS_SHIFT)) & RTC_CTRL_CLKO_DIS_MASK)

#define RTC_CTRL_CLKOUT_MASK                     (0x6000U)
#define RTC_CTRL_CLKOUT_SHIFT                    (13U)
/*! CLKOUT - RTC Clock Output Selection
 *  0b00..No output clock
 *  0b01..Fine 1 Hz clock with both precise edges
 *  0b10..32.768 kHz clock
 *  0b11..Coarse 1 Hz clock with both precise edges
 */
#define RTC_CTRL_CLKOUT(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK)
/*! @} */

/*! @name STATUS - Status */
/*! @{ */

#define RTC_STATUS_INVAL_BIT_MASK                (0x1U)
#define RTC_STATUS_INVAL_BIT_SHIFT               (0U)
/*! INVAL_BIT - Invalidate CPU Read/Write Access
 *  0b0..Time and date counters can be read or written. Time and date is valid.
 *  0b1..Time and date counter values are changing or time and date is invalid and cannot be read or written.
 */
#define RTC_STATUS_INVAL_BIT(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK)

#define RTC_STATUS_WRITE_PROT_EN_MASK            (0x2U)
#define RTC_STATUS_WRITE_PROT_EN_SHIFT           (1U)
/*! WRITE_PROT_EN - Write Protect Enable Status
 *  0b0..Registers are unlocked and can be accessed.
 *  0b1..Registers are locked and in read-only mode.
 */
#define RTC_STATUS_WRITE_PROT_EN(x)              (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK)

#define RTC_STATUS_CMP_INT_MASK                  (0x20U)
#define RTC_STATUS_CMP_INT_SHIFT                 (5U)
/*! CMP_INT - Compensation Interval */
#define RTC_STATUS_CMP_INT(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK)

#define RTC_STATUS_WE_MASK                       (0xC0U)
#define RTC_STATUS_WE_SHIFT                      (6U)
/*! WE - Write Enable
 *  0b10..Enable Write Protection - Registers are locked.
 */
#define RTC_STATUS_WE(x)                         (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK)

#define RTC_STATUS_BUS_ERR_MASK                  (0x100U)
#define RTC_STATUS_BUS_ERR_SHIFT                 (8U)
/*! BUS_ERR - Bus Error
 *  0b0..Read and write accesses are normal.
 *  0b1..Read or write accesses occurred when STATUS[INVAL_BIT] was asserted.
 */
#define RTC_STATUS_BUS_ERR(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK)

#define RTC_STATUS_CMP_DONE_MASK                 (0x800U)
#define RTC_STATUS_CMP_DONE_SHIFT                (11U)
/*! CMP_DONE - Compensation Done
 *  0b0..Compensation busy or not enabled
 *  0b1..Compensation completed
 */
#define RTC_STATUS_CMP_DONE(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK)
/*! @} */

/*! @name ISR - Interrupt Status */
/*! @{ */

#define RTC_ISR_ALM_IS_MASK                      (0x4U)
#define RTC_ISR_ALM_IS_SHIFT                     (2U)
/*! ALM_IS - Alarm Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_ALM_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK)

#define RTC_ISR_DAY_IS_MASK                      (0x8U)
#define RTC_ISR_DAY_IS_SHIFT                     (3U)
/*! DAY_IS - Days Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_DAY_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK)

#define RTC_ISR_HOUR_IS_MASK                     (0x10U)
#define RTC_ISR_HOUR_IS_SHIFT                    (4U)
/*! HOUR_IS - Hours Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_HOUR_IS(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK)

#define RTC_ISR_MIN_IS_MASK                      (0x20U)
#define RTC_ISR_MIN_IS_SHIFT                     (5U)
/*! MIN_IS - Minutes Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_MIN_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK)

#define RTC_ISR_IS_1HZ_MASK                      (0x40U)
#define RTC_ISR_IS_1HZ_SHIFT                     (6U)
/*! IS_1HZ - 1 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_1HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK)

#define RTC_ISR_IS_2HZ_MASK                      (0x80U)
#define RTC_ISR_IS_2HZ_SHIFT                     (7U)
/*! IS_2HZ - 2 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_2HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK)

#define RTC_ISR_IS_4HZ_MASK                      (0x100U)
#define RTC_ISR_IS_4HZ_SHIFT                     (8U)
/*! IS_4HZ - 4 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_4HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK)

#define RTC_ISR_IS_8HZ_MASK                      (0x200U)
#define RTC_ISR_IS_8HZ_SHIFT                     (9U)
/*! IS_8HZ - 8 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_8HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK)

#define RTC_ISR_IS_16HZ_MASK                     (0x400U)
#define RTC_ISR_IS_16HZ_SHIFT                    (10U)
/*! IS_16HZ - 16 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_16HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK)

#define RTC_ISR_IS_32HZ_MASK                     (0x800U)
#define RTC_ISR_IS_32HZ_SHIFT                    (11U)
/*! IS_32HZ - 32 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_32HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK)

#define RTC_ISR_IS_64HZ_MASK                     (0x1000U)
#define RTC_ISR_IS_64HZ_SHIFT                    (12U)
/*! IS_64HZ - 64 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_64HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK)

#define RTC_ISR_IS_128HZ_MASK                    (0x2000U)
#define RTC_ISR_IS_128HZ_SHIFT                   (13U)
/*! IS_128HZ - 128 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_128HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK)

#define RTC_ISR_IS_256HZ_MASK                    (0x4000U)
#define RTC_ISR_IS_256HZ_SHIFT                   (14U)
/*! IS_256HZ - 256 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_256HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK)

#define RTC_ISR_IS_512HZ_MASK                    (0x8000U)
#define RTC_ISR_IS_512HZ_SHIFT                   (15U)
/*! IS_512HZ - 512 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_512HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK)
/*! @} */

/*! @name IER - Interrupt Enable */
/*! @{ */

#define RTC_IER_ALM_IE_MASK                      (0x4U)
#define RTC_IER_ALM_IE_SHIFT                     (2U)
/*! ALM_IE - Alarm Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_ALM_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK)

#define RTC_IER_DAY_IE_MASK                      (0x8U)
#define RTC_IER_DAY_IE_SHIFT                     (3U)
/*! DAY_IE - Days Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_DAY_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK)

#define RTC_IER_HOUR_IE_MASK                     (0x10U)
#define RTC_IER_HOUR_IE_SHIFT                    (4U)
/*! HOUR_IE - Hours Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_HOUR_IE(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK)

#define RTC_IER_MIN_IE_MASK                      (0x20U)
#define RTC_IER_MIN_IE_SHIFT                     (5U)
/*! MIN_IE - Minutes Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_MIN_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK)

#define RTC_IER_IE_1HZ_MASK                      (0x40U)
#define RTC_IER_IE_1HZ_SHIFT                     (6U)
/*! IE_1HZ - 1 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_1HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK)

#define RTC_IER_IE_2HZ_MASK                      (0x80U)
#define RTC_IER_IE_2HZ_SHIFT                     (7U)
/*! IE_2HZ - 2 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_2HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK)

#define RTC_IER_IE_4HZ_MASK                      (0x100U)
#define RTC_IER_IE_4HZ_SHIFT                     (8U)
/*! IE_4HZ - 4 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_4HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK)

#define RTC_IER_IE_8HZ_MASK                      (0x200U)
#define RTC_IER_IE_8HZ_SHIFT                     (9U)
/*! IE_8HZ - 8 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_8HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK)

#define RTC_IER_IE_16HZ_MASK                     (0x400U)
#define RTC_IER_IE_16HZ_SHIFT                    (10U)
/*! IE_16HZ - 16 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_16HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK)

#define RTC_IER_IE_32HZ_MASK                     (0x800U)
#define RTC_IER_IE_32HZ_SHIFT                    (11U)
/*! IE_32HZ - 32 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_32HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK)

#define RTC_IER_IE_64HZ_MASK                     (0x1000U)
#define RTC_IER_IE_64HZ_SHIFT                    (12U)
/*! IE_64HZ - 64 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_64HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK)

#define RTC_IER_IE_128HZ_MASK                    (0x2000U)
#define RTC_IER_IE_128HZ_SHIFT                   (13U)
/*! IE_128HZ - 128 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_128HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK)

#define RTC_IER_IE_256HZ_MASK                    (0x4000U)
#define RTC_IER_IE_256HZ_SHIFT                   (14U)
/*! IE_256HZ - 256 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_256HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK)

#define RTC_IER_IE_512HZ_MASK                    (0x8000U)
#define RTC_IER_IE_512HZ_SHIFT                   (15U)
/*! IE_512HZ - 512 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_512HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK)
/*! @} */

/*! @name RTC_TEST2 - Sub Second Counter */
/*! @{ */

#define RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK      (0xFFFFU)
#define RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT     (0U)
/*! SUB_SECOND_COUNT - Sub Second Counter Value */
#define RTC_RTC_TEST2_SUB_SECOND_COUNT(x)        (((uint16_t)(((uint16_t)(x)) << RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT)) & RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK)
/*! @} */

/*! @name DST_HOUR - Daylight Saving Hour */
/*! @{ */

#define RTC_DST_HOUR_DST_END_HOUR_MASK           (0x1FU)
#define RTC_DST_HOUR_DST_END_HOUR_SHIFT          (0U)
/*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value */
#define RTC_DST_HOUR_DST_END_HOUR(x)             (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK)

#define RTC_DST_HOUR_DST_START_HOUR_MASK         (0x1F00U)
#define RTC_DST_HOUR_DST_START_HOUR_SHIFT        (8U)
/*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value */
#define RTC_DST_HOUR_DST_START_HOUR(x)           (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK)
/*! @} */

/*! @name DST_MONTH - Daylight Saving Month */
/*! @{ */

#define RTC_DST_MONTH_DST_END_MONTH_MASK         (0xFU)
#define RTC_DST_MONTH_DST_END_MONTH_SHIFT        (0U)
/*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value */
#define RTC_DST_MONTH_DST_END_MONTH(x)           (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK)

#define RTC_DST_MONTH_DST_START_MONTH_MASK       (0xF00U)
#define RTC_DST_MONTH_DST_START_MONTH_SHIFT      (8U)
/*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value */
#define RTC_DST_MONTH_DST_START_MONTH(x)         (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK)
/*! @} */

/*! @name DST_DAY - Daylight Saving Day */
/*! @{ */

#define RTC_DST_DAY_DST_END_DAY_MASK             (0x1FU)
#define RTC_DST_DAY_DST_END_DAY_SHIFT            (0U)
/*! DST_END_DAY - Daylight Saving Time (DST) Day End Value */
#define RTC_DST_DAY_DST_END_DAY(x)               (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK)

#define RTC_DST_DAY_DST_START_DAY_MASK           (0x1F00U)
#define RTC_DST_DAY_DST_START_DAY_SHIFT          (8U)
/*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value */
#define RTC_DST_DAY_DST_START_DAY(x)             (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK)
/*! @} */

/*! @name COMPEN - Compensation */
/*! @{ */

#define RTC_COMPEN_COMPEN_VAL_MASK               (0xFFFFU)
#define RTC_COMPEN_COMPEN_VAL_SHIFT              (0U)
/*! COMPEN_VAL - Compensation Value */
#define RTC_COMPEN_COMPEN_VAL(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK)
/*! @} */

/*! @name WAKE_TIMER_CTRL - Wake Timer Control (CPU0) */
/*! @{ */

#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK       (0x2U)
#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT      (1U)
/*! WAKE_FLAG - Wake Timer 0 Status Flag
 *  0b0..Not time out
 *  0b1..Time out.
 */
#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x)         (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK)

#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK  (0x4U)
#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U)
/*! CLR_WAKE_TIMER - Clear Wake Timer 0
 *  0b0..No effect.
 *  0b1..Clear.
 */
#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK)

#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK     (0x10U)
#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT    (4U)
/*! OSC_DIV_ENA - OSC Divide Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x)       (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK)

#define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK         (0x20U)
#define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT        (5U)
/*! INTR_EN - Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define RTC_WAKE_TIMER_CTRL_INTR_EN(x)           (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK)

#define RTC_WAKE_TIMER_CTRL_LOFRQCLK_SRC_EN_MASK (0x10000000U)
#define RTC_WAKE_TIMER_CTRL_LOFRQCLK_SRC_EN_SHIFT (28U)
/*! LOFRQCLK_SRC_EN - Low Frequency Clock Source Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define RTC_WAKE_TIMER_CTRL_LOFRQCLK_SRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_LOFRQCLK_SRC_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_LOFRQCLK_SRC_EN_MASK)

#define RTC_WAKE_TIMER_CTRL_SHUTOFF_OSC32_MASK   (0x80000000U)
#define RTC_WAKE_TIMER_CTRL_SHUTOFF_OSC32_SHIFT  (31U)
/*! SHUTOFF_OSC32 - Shut off OSC32KNP
 *  0b0..Enable
 *  0b1..Disable
 */
#define RTC_WAKE_TIMER_CTRL_SHUTOFF_OSC32(x)     (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_SHUTOFF_OSC32_SHIFT)) & RTC_WAKE_TIMER_CTRL_SHUTOFF_OSC32_MASK)
/*! @} */

/*! @name WAKE_TIMER_CNT - Wake Timer 0 Counter (CPU0) */
/*! @{ */

#define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK         (0xFFFFFFFFU)
#define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT        (0U)
/*! WAKE_CNT - Wake Counter 0 Value */
#define RTC_WAKE_TIMER_CNT_WAKE_CNT(x)           (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RTC_Register_Masks */


/* RTC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RTC0 base address */
  #define RTC0_BASE                                (0x50068000u)
  /** Peripheral RTC0 base address */
  #define RTC0_BASE_NS                             (0x40068000u)
  /** Peripheral RTC0 base pointer */
  #define RTC0                                     ((RTC_Type *)RTC0_BASE)
  /** Peripheral RTC0 base pointer */
  #define RTC0_NS                                  ((RTC_Type *)RTC0_BASE_NS)
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS                           { RTC0_BASE }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS                            { RTC0 }
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS_NS                        { RTC0_BASE_NS }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS_NS                         { RTC0_NS }
#else
  /** Peripheral RTC0 base address */
  #define RTC0_BASE                                (0x40068000u)
  /** Peripheral RTC0 base pointer */
  #define RTC0                                     ((RTC_Type *)RTC0_BASE)
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS                           { RTC0_BASE }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS                            { RTC0 }
#endif

/*!
 * @}
 */ /* end of group RTC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
 * @{
 */

/** SCT - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONFIG;                            /**< SCT Configuration, offset: 0x0 */
  union {                                          /* offset: 0x4 */
    struct {                                         /* offset: 0x4 */
      __IO uint16_t CTRLL;                             /**< SCT_CTRLL register, offset: 0x4 */
      __IO uint16_t CTRLH;                             /**< SCT_CTRLH register, offset: 0x6 */
    } CTRL_ACCESS16BIT;
    __IO uint32_t CTRL;                              /**< SCT Control, offset: 0x4 */
  };
  union {                                          /* offset: 0x8 */
    struct {                                         /* offset: 0x8 */
      __IO uint16_t LIMITL;                            /**< SCT_LIMITL register, offset: 0x8 */
      __IO uint16_t LIMITH;                            /**< SCT_LIMITH register, offset: 0xA */
    } LIMIT_ACCESS16BIT;
    __IO uint32_t LIMIT;                             /**< SCT Limit Event Select, offset: 0x8 */
  };
  union {                                          /* offset: 0xC */
    struct {                                         /* offset: 0xC */
      __IO uint16_t HALTL;                             /**< SCT_HALTL register, offset: 0xC */
      __IO uint16_t HALTH;                             /**< SCT_HALTH register, offset: 0xE */
    } HALT_ACCESS16BIT;
    __IO uint32_t HALT;                              /**< Halt Event Select, offset: 0xC */
  };
  union {                                          /* offset: 0x10 */
    struct {                                         /* offset: 0x10 */
      __IO uint16_t STOPL;                             /**< SCT_STOPL register, offset: 0x10 */
      __IO uint16_t STOPH;                             /**< SCT_STOPH register, offset: 0x12 */
    } STOP_ACCESS16BIT;
    __IO uint32_t STOP;                              /**< Stop Event Select, offset: 0x10 */
  };
  union {                                          /* offset: 0x14 */
    struct {                                         /* offset: 0x14 */
      __IO uint16_t STARTL;                            /**< SCT_STARTL register, offset: 0x14 */
      __IO uint16_t STARTH;                            /**< SCT_STARTH register, offset: 0x16 */
    } START_ACCESS16BIT;
    __IO uint32_t START;                             /**< Start Event Select, offset: 0x14 */
  };
  __IO uint32_t DITHER;                            /**< Dither Condition, offset: 0x18 */
       uint8_t RESERVED_0[36];
  union {                                          /* offset: 0x40 */
    struct {                                         /* offset: 0x40 */
      __IO uint16_t COUNTL;                            /**< SCT_COUNTL register, offset: 0x40 */
      __IO uint16_t COUNTH;                            /**< SCT_COUNTH register, offset: 0x42 */
    } COUNT_ACCESS16BIT;
    __IO uint32_t COUNT;                             /**< Counter Value, offset: 0x40 */
  };
  union {                                          /* offset: 0x44 */
    struct {                                         /* offset: 0x44 */
      __IO uint16_t STATEL;                            /**< SCT_STATEL register, offset: 0x44 */
      __IO uint16_t STATEH;                            /**< SCT_STATEH register, offset: 0x46 */
    } STATE_ACCESS16BIT;
    __IO uint32_t STATE;                             /**< State Variable, offset: 0x44 */
  };
  __I  uint32_t INPUT;                             /**< Input State, offset: 0x48 */
  union {                                          /* offset: 0x4C */
    struct {                                         /* offset: 0x4C */
      __IO uint16_t REGMODEL;                          /**< SCT_REGMODEL register, offset: 0x4C */
      __IO uint16_t REGMODEH;                          /**< SCT_REGMODEH register, offset: 0x4E */
    } REGMODE_ACCESS16BIT;
    __IO uint32_t REGMODE;                           /**< Match and Capture Register Mode, offset: 0x4C */
  };
  __IO uint32_t OUTPUT;                            /**< Output State, offset: 0x50 */
  __IO uint32_t OUTPUTDIRCTRL;                     /**< Output Counter Direction Control, offset: 0x54 */
  __IO uint32_t RES;                               /**< Output Conflict Resolution, offset: 0x58 */
  __IO uint32_t DMAREQ0;                           /**< DMA Request 0, offset: 0x5C */
  __IO uint32_t DMAREQ1;                           /**< DMA Request 1, offset: 0x60 */
       uint8_t RESERVED_1[140];
  __IO uint32_t EVEN;                              /**< Event Interrupt Enable, offset: 0xF0 */
  __IO uint32_t EVFLAG;                            /**< Event Flag, offset: 0xF4 */
  __IO uint32_t CONEN;                             /**< Conflict Interrupt Enable, offset: 0xF8 */
  __IO uint32_t CONFLAG;                           /**< Conflict Flag, offset: 0xFC */
  union {                                          /* offset: 0x100 */
    union {                                          /* offset: 0x100, array step: 0x4 */
      struct {                                         /* offset: 0x100, array step: 0x4 */
        __IO uint16_t CAPL;                              /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
        __IO uint16_t CAPH;                              /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
      } CAP_ACCESS16BIT[16];
      __IO uint32_t CAP[16];                           /**< Capture Value, array offset: 0x100, array step: 0x4 */
    };
    union {                                          /* offset: 0x100, array step: 0x4 */
      struct {                                         /* offset: 0x100, array step: 0x4 */
        __IO uint16_t MATCHL;                            /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
        __IO uint16_t MATCHH;                            /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
      } MATCH_ACCESS16BIT[16];
      __IO uint32_t MATCH[16];                         /**< Match Value, array offset: 0x100, array step: 0x4 */
    };
  };
  __IO uint32_t FRACMAT[6];                        /**< Fractional Match, array offset: 0x140, array step: 0x4 */
       uint8_t RESERVED_2[168];
  union {                                          /* offset: 0x200 */
    union {                                          /* offset: 0x200, array step: 0x4 */
      struct {                                         /* offset: 0x200, array step: 0x4 */
        __IO uint16_t CAPCTRLL;                          /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
        __IO uint16_t CAPCTRLH;                          /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
      } CAPCTRL_ACCESS16BIT[16];
      __IO uint32_t CAPCTRL[16];                       /**< Capture Control, array offset: 0x200, array step: 0x4 */
    };
    union {                                          /* offset: 0x200, array step: 0x4 */
      struct {                                         /* offset: 0x200, array step: 0x4 */
        __IO uint16_t MATCHRELL;                         /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
        __IO uint16_t MATCHRELH;                         /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
      } MATCHREL_ACCESS16BIT[16];
      __IO uint32_t MATCHREL[16];                      /**< Match Reload Value, array offset: 0x200, array step: 0x4 */
    };
  };
  __IO uint32_t FRACMATREL[6];                     /**< Fractional Match Reload, array offset: 0x240, array step: 0x4 */
       uint8_t RESERVED_3[168];
  struct {                                         /* offset: 0x300, array step: 0x8 */
    __IO uint32_t STATE;                             /**< Event n State, array offset: 0x300, array step: 0x8 */
    __IO uint32_t CTRL;                              /**< Event n Control, array offset: 0x304, array step: 0x8 */
  } EV[16];
       uint8_t RESERVED_4[384];
  struct {                                         /* offset: 0x500, array step: 0x8 */
    __IO uint32_t SET;                               /**< Output n Set, array offset: 0x500, array step: 0x8 */
    __IO uint32_t CLR;                               /**< Output n Clear, array offset: 0x504, array step: 0x8 */
  } OUT[10];
} SCT_Type;

/* ----------------------------------------------------------------------------
   -- SCT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCT_Register_Masks SCT Register Masks
 * @{
 */

/*! @name CONFIG - SCT Configuration */
/*! @{ */

#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
/*! UNIFY - SCT Operation
 *  0b0..Dual counters, COUNTER_L and COUNTER_H
 *  0b1..Unified counter
 */
#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)

#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
/*! CLKMODE - SCT Clock Mode
 *  0b00..System Clock mode
 *  0b01..Sampled System Clock mode
 *  0b10..SCT Input Clock mode
 *  0b11..Asynchronous mode
 */
#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)

#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
/*! CKSEL - SCT Clock Select
 *  0b0000..Rising edges on input 0
 *  0b0001..Falling edges on input 0
 *  0b0010..Rising edges on input 1
 *  0b0011..Falling edges on input 1
 *  0b0100..Rising edges on input 2
 *  0b0101..Falling edges on input 2
 *  0b0110..Rising edges on input 3
 *  0b0111..Falling edges on input 3
 *  0b1000..Rising edges on input 4
 *  0b1001..Falling edges on input 4
 *  0b1010..Rising edges on input 5
 *  0b1011..Falling edges on input 5
 *  0b1100..Rising edges on input 6
 *  0b1101..Falling edges on input 6
 *  0b1110..Rising edges on input 7
 *  0b1111..Falling edges on input 7
 */
#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)

#define SCT_CONFIG_NORELOAD_L_MASK               (0x80U)
#define SCT_CONFIG_NORELOAD_L_SHIFT              (7U)
/*! NORELOAD_L - No Reload Lower Match
 *  0b0..Reloaded
 *  0b1..Not reloaded
 */
#define SCT_CONFIG_NORELOAD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)

#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
/*! NORELOAD_H - No Reload Higher Match
 *  0b0..Reloaded
 *  0b1..Not reloaded
 */
#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)

#define SCT_CONFIG_INSYNC_MASK                   (0x1FE00U)
#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
/*! INSYNC - Input Synchronization */
#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)

#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
/*! AUTOLIMIT_L - Auto Limit Lower
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)

#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
/*! AUTOLIMIT_H - Auto Limit Higher
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
/*! @} */

/*! @name CTRLL - SCT_CTRLL register */
/*! @{ */

#define SCT_CTRLL_DOWN_L_MASK                    (0x1U)
#define SCT_CTRLL_DOWN_L_SHIFT                   (0U)
/*! DOWN_L - Down Counter Low
 *  0b0..Up
 *  0b1..Down
 */
#define SCT_CTRLL_DOWN_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)

#define SCT_CTRLL_STOP_L_MASK                    (0x2U)
#define SCT_CTRLL_STOP_L_SHIFT                   (1U)
/*! STOP_L - Stop Counter Low
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SCT_CTRLL_STOP_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)

#define SCT_CTRLL_HALT_L_MASK                    (0x4U)
#define SCT_CTRLL_HALT_L_SHIFT                   (2U)
/*! HALT_L - Halt Counter Low
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SCT_CTRLL_HALT_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)

#define SCT_CTRLL_CLRCTR_L_MASK                  (0x8U)
#define SCT_CTRLL_CLRCTR_L_SHIFT                 (3U)
/*! CLRCTR_L - Clear Counter Low */
#define SCT_CTRLL_CLRCTR_L(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)

#define SCT_CTRLL_BIDIR_L_MASK                   (0x10U)
#define SCT_CTRLL_BIDIR_L_SHIFT                  (4U)
/*! BIDIR_L - Bidirectional Select Low
 *  0b0..Up
 *  0b1..Up-down
 */
#define SCT_CTRLL_BIDIR_L(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)

#define SCT_CTRLL_PRE_L_MASK                     (0x1FE0U)
#define SCT_CTRLL_PRE_L_SHIFT                    (5U)
/*! PRE_L - Prescaler for Low Counter */
#define SCT_CTRLL_PRE_L(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
/*! @} */

/*! @name CTRLH - SCT_CTRLH register */
/*! @{ */

#define SCT_CTRLH_DOWN_H_MASK                    (0x1U)
#define SCT_CTRLH_DOWN_H_SHIFT                   (0U)
/*! DOWN_H - Down Counter High
 *  0b0..Up
 *  0b1..Down
 */
#define SCT_CTRLH_DOWN_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)

#define SCT_CTRLH_STOP_H_MASK                    (0x2U)
#define SCT_CTRLH_STOP_H_SHIFT                   (1U)
/*! STOP_H - Stop Counter High
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SCT_CTRLH_STOP_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)

#define SCT_CTRLH_HALT_H_MASK                    (0x4U)
#define SCT_CTRLH_HALT_H_SHIFT                   (2U)
/*! HALT_H - Halt Counter High
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRLH_HALT_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)

#define SCT_CTRLH_CLRCTR_H_MASK                  (0x8U)
#define SCT_CTRLH_CLRCTR_H_SHIFT                 (3U)
/*! CLRCTR_H - Clear Counter High */
#define SCT_CTRLH_CLRCTR_H(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)

#define SCT_CTRLH_BIDIR_H_MASK                   (0x10U)
#define SCT_CTRLH_BIDIR_H_SHIFT                  (4U)
/*! BIDIR_H - Bidirectional Select High
 *  0b0..Up
 *  0b1..Up-down
 */
#define SCT_CTRLH_BIDIR_H(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)

#define SCT_CTRLH_PRE_H_MASK                     (0x1FE0U)
#define SCT_CTRLH_PRE_H_SHIFT                    (5U)
/*! PRE_H - Prescaler for High Counter */
#define SCT_CTRLH_PRE_H(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
/*! @} */

/*! @name CTRL - SCT Control */
/*! @{ */

#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
/*! DOWN_L - Down Counter Low
 *  0b0..Up
 *  0b1..Down
 */
#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)

#define SCT_CTRL_STOP_L_MASK                     (0x2U)
#define SCT_CTRL_STOP_L_SHIFT                    (1U)
/*! STOP_L - Stop Counter Low
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)

#define SCT_CTRL_HALT_L_MASK                     (0x4U)
#define SCT_CTRL_HALT_L_SHIFT                    (2U)
/*! HALT_L - Halt Counter Low
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)

#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
/*! CLRCTR_L - Clear Counter Low */
#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)

#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
/*! BIDIR_L - Bidirectional Select Low
 *  0b0..Up
 *  0b1..Up-down
 */
#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)

#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
#define SCT_CTRL_PRE_L_SHIFT                     (5U)
/*! PRE_L - Prescaler for Low Counter */
#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)

#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
/*! DOWN_H - Down Counter High
 *  0b0..Up
 *  0b1..Down
 */
#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)

#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
#define SCT_CTRL_STOP_H_SHIFT                    (17U)
/*! STOP_H - Stop Counter High
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)

#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
#define SCT_CTRL_HALT_H_SHIFT                    (18U)
/*! HALT_H - Halt Counter High
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)

#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
/*! CLRCTR_H - Clear Counter High */
#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)

#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
/*! BIDIR_H - Bidirectional Select High
 *  0b0..Up
 *  0b1..Up-down
 */
#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)

#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
#define SCT_CTRL_PRE_H_SHIFT                     (21U)
/*! PRE_H - Prescaler for High Counter */
#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
/*! @} */

/*! @name LIMITL - SCT_LIMITL register */
/*! @{ */

#define SCT_LIMITL_LIMITL_MASK                   (0xFFFFU)
#define SCT_LIMITL_LIMITL_SHIFT                  (0U)
#define SCT_LIMITL_LIMITL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
/*! @} */

/*! @name LIMITH - SCT_LIMITH register */
/*! @{ */

#define SCT_LIMITH_LIMITH_MASK                   (0xFFFFU)
#define SCT_LIMITH_LIMITH_SHIFT                  (0U)
#define SCT_LIMITH_LIMITH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
/*! @} */

/*! @name LIMIT - SCT Limit Event Select */
/*! @{ */

#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
/*! LIMMSK_L - Limit Event Counter Low */
#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)

#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
/*! LIMMSK_H - Limit Event Counter High */
#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
/*! @} */

/*! @name HALTL - SCT_HALTL register */
/*! @{ */

#define SCT_HALTL_HALTL_MASK                     (0xFFFFU)
#define SCT_HALTL_HALTL_SHIFT                    (0U)
#define SCT_HALTL_HALTL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
/*! @} */

/*! @name HALTH - SCT_HALTH register */
/*! @{ */

#define SCT_HALTH_HALTH_MASK                     (0xFFFFU)
#define SCT_HALTH_HALTH_SHIFT                    (0U)
#define SCT_HALTH_HALTH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
/*! @} */

/*! @name HALT - Halt Event Select */
/*! @{ */

#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
/*! HALTMSK_L - Halt Event Low */
#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)

#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
/*! HALTMSK_H - Halt Event High */
#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
/*! @} */

/*! @name STOPL - SCT_STOPL register */
/*! @{ */

#define SCT_STOPL_STOPL_MASK                     (0xFFFFU)
#define SCT_STOPL_STOPL_SHIFT                    (0U)
#define SCT_STOPL_STOPL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
/*! @} */

/*! @name STOPH - SCT_STOPH register */
/*! @{ */

#define SCT_STOPH_STOPH_MASK                     (0xFFFFU)
#define SCT_STOPH_STOPH_SHIFT                    (0U)
#define SCT_STOPH_STOPH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
/*! @} */

/*! @name STOP - Stop Event Select */
/*! @{ */

#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
/*! STOPMSK_L - Stop Event Low */
#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)

#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
/*! STOPMSK_H - Stop Event High */
#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
/*! @} */

/*! @name STARTL - SCT_STARTL register */
/*! @{ */

#define SCT_STARTL_STARTL_MASK                   (0xFFFFU)
#define SCT_STARTL_STARTL_SHIFT                  (0U)
#define SCT_STARTL_STARTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
/*! @} */

/*! @name STARTH - SCT_STARTH register */
/*! @{ */

#define SCT_STARTH_STARTH_MASK                   (0xFFFFU)
#define SCT_STARTH_STARTH_SHIFT                  (0U)
#define SCT_STARTH_STARTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
/*! @} */

/*! @name START - Start Event Select */
/*! @{ */

#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
#define SCT_START_STARTMSK_L_SHIFT               (0U)
/*! STARTMSK_L - Start Event Low */
#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)

#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
#define SCT_START_STARTMSK_H_SHIFT               (16U)
/*! STARTMSK_H - Start Event High */
#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
/*! @} */

/*! @name DITHER - Dither Condition */
/*! @{ */

#define SCT_DITHER_DITHER_L_MASK                 (0xFFFFU)
#define SCT_DITHER_DITHER_L_SHIFT                (0U)
/*! DITHER_L - Dither Low */
#define SCT_DITHER_DITHER_L(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_L_SHIFT)) & SCT_DITHER_DITHER_L_MASK)

#define SCT_DITHER_DITHER_H_MASK                 (0xFFFF0000U)
#define SCT_DITHER_DITHER_H_SHIFT                (16U)
/*! DITHER_H - Dither High */
#define SCT_DITHER_DITHER_H(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_H_SHIFT)) & SCT_DITHER_DITHER_H_MASK)
/*! @} */

/*! @name COUNTL - SCT_COUNTL register */
/*! @{ */

#define SCT_COUNTL_COUNTL_MASK                   (0xFFFFU)
#define SCT_COUNTL_COUNTL_SHIFT                  (0U)
#define SCT_COUNTL_COUNTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
/*! @} */

/*! @name COUNTH - SCT_COUNTH register */
/*! @{ */

#define SCT_COUNTH_COUNTH_MASK                   (0xFFFFU)
#define SCT_COUNTH_COUNTH_SHIFT                  (0U)
#define SCT_COUNTH_COUNTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
/*! @} */

/*! @name COUNT - Counter Value */
/*! @{ */

#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
#define SCT_COUNT_CTR_L_SHIFT                    (0U)
/*! CTR_L - Counter Low */
#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)

#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
#define SCT_COUNT_CTR_H_SHIFT                    (16U)
/*! CTR_H - Counter High */
#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
/*! @} */

/*! @name STATEL - SCT_STATEL register */
/*! @{ */

#define SCT_STATEL_STATEL_MASK                   (0xFFFFU)
#define SCT_STATEL_STATEL_SHIFT                  (0U)
#define SCT_STATEL_STATEL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
/*! @} */

/*! @name STATEH - SCT_STATEH register */
/*! @{ */

#define SCT_STATEH_STATEH_MASK                   (0xFFFFU)
#define SCT_STATEH_STATEH_SHIFT                  (0U)
#define SCT_STATEH_STATEH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
/*! @} */

/*! @name STATE - State Variable */
/*! @{ */

#define SCT_STATE_STATE_L_MASK                   (0x1FU)
#define SCT_STATE_STATE_L_SHIFT                  (0U)
/*! STATE_L - State Variable Low */
#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)

#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
#define SCT_STATE_STATE_H_SHIFT                  (16U)
/*! STATE_H - State Variable High */
#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
/*! @} */

/*! @name INPUT - Input State */
/*! @{ */

#define SCT_INPUT_AIN0_MASK                      (0x1U)
#define SCT_INPUT_AIN0_SHIFT                     (0U)
/*! AIN0 - Input 0 state */
#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)

#define SCT_INPUT_AIN1_MASK                      (0x2U)
#define SCT_INPUT_AIN1_SHIFT                     (1U)
/*! AIN1 - Input 1 state */
#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)

#define SCT_INPUT_AIN2_MASK                      (0x4U)
#define SCT_INPUT_AIN2_SHIFT                     (2U)
/*! AIN2 - Input 2 state */
#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)

#define SCT_INPUT_AIN3_MASK                      (0x8U)
#define SCT_INPUT_AIN3_SHIFT                     (3U)
/*! AIN3 - Input 3 state */
#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)

#define SCT_INPUT_AIN4_MASK                      (0x10U)
#define SCT_INPUT_AIN4_SHIFT                     (4U)
/*! AIN4 - Input 4 state */
#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)

#define SCT_INPUT_AIN5_MASK                      (0x20U)
#define SCT_INPUT_AIN5_SHIFT                     (5U)
/*! AIN5 - Input 5 state */
#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)

#define SCT_INPUT_AIN6_MASK                      (0x40U)
#define SCT_INPUT_AIN6_SHIFT                     (6U)
/*! AIN6 - Input 6 state */
#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)

#define SCT_INPUT_AIN7_MASK                      (0x80U)
#define SCT_INPUT_AIN7_SHIFT                     (7U)
/*! AIN7 - Input 7 state */
#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)

#define SCT_INPUT_AIN8_MASK                      (0x100U)
#define SCT_INPUT_AIN8_SHIFT                     (8U)
/*! AIN8 - Input 8 state */
#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)

#define SCT_INPUT_AIN9_MASK                      (0x200U)
#define SCT_INPUT_AIN9_SHIFT                     (9U)
/*! AIN9 - Input 9 state */
#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)

#define SCT_INPUT_AIN10_MASK                     (0x400U)
#define SCT_INPUT_AIN10_SHIFT                    (10U)
/*! AIN10 - Input 10 state */
#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)

#define SCT_INPUT_AIN11_MASK                     (0x800U)
#define SCT_INPUT_AIN11_SHIFT                    (11U)
/*! AIN11 - Input 11 state */
#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)

#define SCT_INPUT_AIN12_MASK                     (0x1000U)
#define SCT_INPUT_AIN12_SHIFT                    (12U)
/*! AIN12 - Input 12 state */
#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)

#define SCT_INPUT_AIN13_MASK                     (0x2000U)
#define SCT_INPUT_AIN13_SHIFT                    (13U)
/*! AIN13 - Input 13 state */
#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)

#define SCT_INPUT_AIN14_MASK                     (0x4000U)
#define SCT_INPUT_AIN14_SHIFT                    (14U)
/*! AIN14 - Input 14 state */
#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)

#define SCT_INPUT_AIN15_MASK                     (0x8000U)
#define SCT_INPUT_AIN15_SHIFT                    (15U)
/*! AIN15 - Input 15 state */
#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)

#define SCT_INPUT_SIN0_MASK                      (0x10000U)
#define SCT_INPUT_SIN0_SHIFT                     (16U)
/*! SIN0 - Input 0 state */
#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)

#define SCT_INPUT_SIN1_MASK                      (0x20000U)
#define SCT_INPUT_SIN1_SHIFT                     (17U)
/*! SIN1 - Input 1 state */
#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)

#define SCT_INPUT_SIN2_MASK                      (0x40000U)
#define SCT_INPUT_SIN2_SHIFT                     (18U)
/*! SIN2 - Input 2 state */
#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)

#define SCT_INPUT_SIN3_MASK                      (0x80000U)
#define SCT_INPUT_SIN3_SHIFT                     (19U)
/*! SIN3 - Input 3 state */
#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)

#define SCT_INPUT_SIN4_MASK                      (0x100000U)
#define SCT_INPUT_SIN4_SHIFT                     (20U)
/*! SIN4 - Input 4 state */
#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)

#define SCT_INPUT_SIN5_MASK                      (0x200000U)
#define SCT_INPUT_SIN5_SHIFT                     (21U)
/*! SIN5 - Input 5 state */
#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)

#define SCT_INPUT_SIN6_MASK                      (0x400000U)
#define SCT_INPUT_SIN6_SHIFT                     (22U)
/*! SIN6 - Input 6 state */
#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)

#define SCT_INPUT_SIN7_MASK                      (0x800000U)
#define SCT_INPUT_SIN7_SHIFT                     (23U)
/*! SIN7 - Input 7 state */
#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)

#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
#define SCT_INPUT_SIN8_SHIFT                     (24U)
/*! SIN8 - Input 8 state */
#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)

#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
#define SCT_INPUT_SIN9_SHIFT                     (25U)
/*! SIN9 - Input 9 state */
#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)

#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
#define SCT_INPUT_SIN10_SHIFT                    (26U)
/*! SIN10 - Input 10 state */
#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)

#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
#define SCT_INPUT_SIN11_SHIFT                    (27U)
/*! SIN11 - Input 11 state */
#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)

#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
#define SCT_INPUT_SIN12_SHIFT                    (28U)
/*! SIN12 - Input 12 state */
#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)

#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
#define SCT_INPUT_SIN13_SHIFT                    (29U)
/*! SIN13 - Input 13 state */
#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)

#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
#define SCT_INPUT_SIN14_SHIFT                    (30U)
/*! SIN14 - Input 14 state */
#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)

#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
#define SCT_INPUT_SIN15_SHIFT                    (31U)
/*! SIN15 - Input 15 state */
#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
/*! @} */

/*! @name REGMODEL - SCT_REGMODEL register */
/*! @{ */

#define SCT_REGMODEL_REGMODEL_MASK               (0xFFFFU)
#define SCT_REGMODEL_REGMODEL_SHIFT              (0U)
/*! REGMODEL
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODEL_REGMODEL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)

#define SCT_REGMODEL_REGMOD_L_MASK               (0xFFFFU)
#define SCT_REGMODEL_REGMOD_L_SHIFT              (0U)
#define SCT_REGMODEL_REGMOD_L(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_L_SHIFT)) & SCT_REGMODEL_REGMOD_L_MASK)

#define SCT_REGMODEL_REGMOD_H_MASK               (0xFFFF0000U)
#define SCT_REGMODEL_REGMOD_H_SHIFT              (16U)
#define SCT_REGMODEL_REGMOD_H(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_H_SHIFT)) & SCT_REGMODEL_REGMOD_H_MASK)
/*! @} */

/*! @name REGMODEH - SCT_REGMODEH register */
/*! @{ */

#define SCT_REGMODEH_REGMODEH_MASK               (0xFFFFU)
#define SCT_REGMODEH_REGMODEH_SHIFT              (0U)
/*! REGMODEH
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODEH_REGMODEH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)

#define SCT_REGMODEH_REGMOD_L_MASK               (0xFFFFU)
#define SCT_REGMODEH_REGMOD_L_SHIFT              (0U)
#define SCT_REGMODEH_REGMOD_L(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_L_SHIFT)) & SCT_REGMODEH_REGMOD_L_MASK)

#define SCT_REGMODEH_REGMOD_H_MASK               (0xFFFF0000U)
#define SCT_REGMODEH_REGMOD_H_SHIFT              (16U)
#define SCT_REGMODEH_REGMOD_H(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_H_SHIFT)) & SCT_REGMODEH_REGMOD_H_MASK)
/*! @} */

/*! @name REGMODE - Match and Capture Register Mode */
/*! @{ */

#define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
#define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
#define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)

#define SCT_REGMODE_REGMOD_L0_MASK               (0x1U)
#define SCT_REGMODE_REGMOD_L0_SHIFT              (0U)
/*! REGMOD_L0 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK)

#define SCT_REGMODE_REGMOD_L1_MASK               (0x2U)
#define SCT_REGMODE_REGMOD_L1_SHIFT              (1U)
/*! REGMOD_L1 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK)

#define SCT_REGMODE_REGMOD_L2_MASK               (0x4U)
#define SCT_REGMODE_REGMOD_L2_SHIFT              (2U)
/*! REGMOD_L2 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK)

#define SCT_REGMODE_REGMOD_L3_MASK               (0x8U)
#define SCT_REGMODE_REGMOD_L3_SHIFT              (3U)
/*! REGMOD_L3 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK)

#define SCT_REGMODE_REGMOD_L4_MASK               (0x10U)
#define SCT_REGMODE_REGMOD_L4_SHIFT              (4U)
/*! REGMOD_L4 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK)

#define SCT_REGMODE_REGMOD_L5_MASK               (0x20U)
#define SCT_REGMODE_REGMOD_L5_SHIFT              (5U)
/*! REGMOD_L5 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK)

#define SCT_REGMODE_REGMOD_L6_MASK               (0x40U)
#define SCT_REGMODE_REGMOD_L6_SHIFT              (6U)
/*! REGMOD_L6 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK)

#define SCT_REGMODE_REGMOD_L7_MASK               (0x80U)
#define SCT_REGMODE_REGMOD_L7_SHIFT              (7U)
/*! REGMOD_L7 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK)

#define SCT_REGMODE_REGMOD_L8_MASK               (0x100U)
#define SCT_REGMODE_REGMOD_L8_SHIFT              (8U)
/*! REGMOD_L8 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK)

#define SCT_REGMODE_REGMOD_L9_MASK               (0x200U)
#define SCT_REGMODE_REGMOD_L9_SHIFT              (9U)
/*! REGMOD_L9 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK)

#define SCT_REGMODE_REGMOD_L10_MASK              (0x400U)
#define SCT_REGMODE_REGMOD_L10_SHIFT             (10U)
/*! REGMOD_L10 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK)

#define SCT_REGMODE_REGMOD_L11_MASK              (0x800U)
#define SCT_REGMODE_REGMOD_L11_SHIFT             (11U)
/*! REGMOD_L11 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK)

#define SCT_REGMODE_REGMOD_L12_MASK              (0x1000U)
#define SCT_REGMODE_REGMOD_L12_SHIFT             (12U)
/*! REGMOD_L12 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK)

#define SCT_REGMODE_REGMOD_L13_MASK              (0x2000U)
#define SCT_REGMODE_REGMOD_L13_SHIFT             (13U)
/*! REGMOD_L13 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK)

#define SCT_REGMODE_REGMOD_L14_MASK              (0x4000U)
#define SCT_REGMODE_REGMOD_L14_SHIFT             (14U)
/*! REGMOD_L14 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK)

#define SCT_REGMODE_REGMOD_L15_MASK              (0x8000U)
#define SCT_REGMODE_REGMOD_L15_SHIFT             (15U)
/*! REGMOD_L15 - Register Mode Low
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_L15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK)

#define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
#define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
#define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)

#define SCT_REGMODE_REGMOD_H0_MASK               (0x10000U)
#define SCT_REGMODE_REGMOD_H0_SHIFT              (16U)
/*! REGMOD_H0 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK)

#define SCT_REGMODE_REGMOD_H1_MASK               (0x20000U)
#define SCT_REGMODE_REGMOD_H1_SHIFT              (17U)
/*! REGMOD_H1 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK)

#define SCT_REGMODE_REGMOD_H2_MASK               (0x40000U)
#define SCT_REGMODE_REGMOD_H2_SHIFT              (18U)
/*! REGMOD_H2 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK)

#define SCT_REGMODE_REGMOD_H3_MASK               (0x80000U)
#define SCT_REGMODE_REGMOD_H3_SHIFT              (19U)
/*! REGMOD_H3 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK)

#define SCT_REGMODE_REGMOD_H4_MASK               (0x100000U)
#define SCT_REGMODE_REGMOD_H4_SHIFT              (20U)
/*! REGMOD_H4 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK)

#define SCT_REGMODE_REGMOD_H5_MASK               (0x200000U)
#define SCT_REGMODE_REGMOD_H5_SHIFT              (21U)
/*! REGMOD_H5 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK)

#define SCT_REGMODE_REGMOD_H6_MASK               (0x400000U)
#define SCT_REGMODE_REGMOD_H6_SHIFT              (22U)
/*! REGMOD_H6 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK)

#define SCT_REGMODE_REGMOD_H7_MASK               (0x800000U)
#define SCT_REGMODE_REGMOD_H7_SHIFT              (23U)
/*! REGMOD_H7 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK)

#define SCT_REGMODE_REGMOD_H8_MASK               (0x1000000U)
#define SCT_REGMODE_REGMOD_H8_SHIFT              (24U)
/*! REGMOD_H8 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK)

#define SCT_REGMODE_REGMOD_H9_MASK               (0x2000000U)
#define SCT_REGMODE_REGMOD_H9_SHIFT              (25U)
/*! REGMOD_H9 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK)

#define SCT_REGMODE_REGMOD_H10_MASK              (0x4000000U)
#define SCT_REGMODE_REGMOD_H10_SHIFT             (26U)
/*! REGMOD_H10 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK)

#define SCT_REGMODE_REGMOD_H11_MASK              (0x8000000U)
#define SCT_REGMODE_REGMOD_H11_SHIFT             (27U)
/*! REGMOD_H11 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK)

#define SCT_REGMODE_REGMOD_H12_MASK              (0x10000000U)
#define SCT_REGMODE_REGMOD_H12_SHIFT             (28U)
/*! REGMOD_H12 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK)

#define SCT_REGMODE_REGMOD_H13_MASK              (0x20000000U)
#define SCT_REGMODE_REGMOD_H13_SHIFT             (29U)
/*! REGMOD_H13 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK)

#define SCT_REGMODE_REGMOD_H14_MASK              (0x40000000U)
#define SCT_REGMODE_REGMOD_H14_SHIFT             (30U)
/*! REGMOD_H14 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK)

#define SCT_REGMODE_REGMOD_H15_MASK              (0x80000000U)
#define SCT_REGMODE_REGMOD_H15_SHIFT             (31U)
/*! REGMOD_H15 - Register Mode High
 *  0b0..Match
 *  0b1..Capture
 */
#define SCT_REGMODE_REGMOD_H15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK)
/*! @} */

/*! @name OUTPUT - Output State */
/*! @{ */

#define SCT_OUTPUT_OUT0_MASK                     (0x1U)
#define SCT_OUTPUT_OUT0_SHIFT                    (0U)
/*! OUT0 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK)

#define SCT_OUTPUT_OUT1_MASK                     (0x2U)
#define SCT_OUTPUT_OUT1_SHIFT                    (1U)
/*! OUT1 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK)

#define SCT_OUTPUT_OUT2_MASK                     (0x4U)
#define SCT_OUTPUT_OUT2_SHIFT                    (2U)
/*! OUT2 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK)

#define SCT_OUTPUT_OUT3_MASK                     (0x8U)
#define SCT_OUTPUT_OUT3_SHIFT                    (3U)
/*! OUT3 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK)

#define SCT_OUTPUT_OUT4_MASK                     (0x10U)
#define SCT_OUTPUT_OUT4_SHIFT                    (4U)
/*! OUT4 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK)

#define SCT_OUTPUT_OUT5_MASK                     (0x20U)
#define SCT_OUTPUT_OUT5_SHIFT                    (5U)
/*! OUT5 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK)

#define SCT_OUTPUT_OUT6_MASK                     (0x40U)
#define SCT_OUTPUT_OUT6_SHIFT                    (6U)
/*! OUT6 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK)

#define SCT_OUTPUT_OUT7_MASK                     (0x80U)
#define SCT_OUTPUT_OUT7_SHIFT                    (7U)
/*! OUT7 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK)

#define SCT_OUTPUT_OUT8_MASK                     (0x100U)
#define SCT_OUTPUT_OUT8_SHIFT                    (8U)
/*! OUT8 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK)

#define SCT_OUTPUT_OUT9_MASK                     (0x200U)
#define SCT_OUTPUT_OUT9_SHIFT                    (9U)
/*! OUT9 - Output Low and High
 *  0b0..Forces the corresponding output low
 *  0b1..Forces the corresponding output high
 */
#define SCT_OUTPUT_OUT9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK)
/*! @} */

/*! @name OUTPUTDIRCTRL - Output Counter Direction Control */
/*! @{ */

#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
/*! SETCLR0 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
/*! SETCLR1 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
/*! SETCLR2 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
/*! SETCLR3 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
/*! SETCLR4 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
/*! SETCLR5 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
/*! SETCLR6 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
/*! SETCLR7 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
/*! SETCLR8 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
/*! SETCLR9 - Set and Clear Operation on Output
 *  0b00..Not dependent on the direction of any counter
 *  0b01..Reversed when counter L or the unified counter is counting down
 *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
 *  0b11..Reserved (do not program this value)
 */
#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
/*! @} */

/*! @name RES - Output Conflict Resolution */
/*! @{ */

#define SCT_RES_O0RES_MASK                       (0x3U)
#define SCT_RES_O0RES_SHIFT                      (0U)
/*! O0RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)

#define SCT_RES_O1RES_MASK                       (0xCU)
#define SCT_RES_O1RES_SHIFT                      (2U)
/*! O1RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)

#define SCT_RES_O2RES_MASK                       (0x30U)
#define SCT_RES_O2RES_SHIFT                      (4U)
/*! O2RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)

#define SCT_RES_O3RES_MASK                       (0xC0U)
#define SCT_RES_O3RES_SHIFT                      (6U)
/*! O3RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)

#define SCT_RES_O4RES_MASK                       (0x300U)
#define SCT_RES_O4RES_SHIFT                      (8U)
/*! O4RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)

#define SCT_RES_O5RES_MASK                       (0xC00U)
#define SCT_RES_O5RES_SHIFT                      (10U)
/*! O5RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)

#define SCT_RES_O6RES_MASK                       (0x3000U)
#define SCT_RES_O6RES_SHIFT                      (12U)
/*! O6RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)

#define SCT_RES_O7RES_MASK                       (0xC000U)
#define SCT_RES_O7RES_SHIFT                      (14U)
/*! O7RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)

#define SCT_RES_O8RES_MASK                       (0x30000U)
#define SCT_RES_O8RES_SHIFT                      (16U)
/*! O8RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)

#define SCT_RES_O9RES_MASK                       (0xC0000U)
#define SCT_RES_O9RES_SHIFT                      (18U)
/*! O9RES - Output Resolution
 *  0b00..No change
 *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
 *  0b11..Toggle output
 */
#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
/*! @} */

/*! @name DMAREQ0 - DMA Request 0 */
/*! @{ */

#define SCT_DMAREQ0_DEV_0_MASK                   (0x1U)
#define SCT_DMAREQ0_DEV_0_SHIFT                  (0U)
/*! DEV_0 - DMA Request Event */
#define SCT_DMAREQ0_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)

#define SCT_DMAREQ0_DEV_1_MASK                   (0x2U)
#define SCT_DMAREQ0_DEV_1_SHIFT                  (1U)
/*! DEV_1 - DMA Request Event */
#define SCT_DMAREQ0_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK)

#define SCT_DMAREQ0_DEV_2_MASK                   (0x4U)
#define SCT_DMAREQ0_DEV_2_SHIFT                  (2U)
/*! DEV_2 - DMA Request Event */
#define SCT_DMAREQ0_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK)

#define SCT_DMAREQ0_DEV_3_MASK                   (0x8U)
#define SCT_DMAREQ0_DEV_3_SHIFT                  (3U)
/*! DEV_3 - DMA Request Event */
#define SCT_DMAREQ0_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK)

#define SCT_DMAREQ0_DEV_4_MASK                   (0x10U)
#define SCT_DMAREQ0_DEV_4_SHIFT                  (4U)
/*! DEV_4 - DMA Request Event */
#define SCT_DMAREQ0_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK)

#define SCT_DMAREQ0_DEV_5_MASK                   (0x20U)
#define SCT_DMAREQ0_DEV_5_SHIFT                  (5U)
/*! DEV_5 - DMA Request Event */
#define SCT_DMAREQ0_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK)

#define SCT_DMAREQ0_DEV_6_MASK                   (0x40U)
#define SCT_DMAREQ0_DEV_6_SHIFT                  (6U)
/*! DEV_6 - DMA Request Event */
#define SCT_DMAREQ0_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK)

#define SCT_DMAREQ0_DEV_7_MASK                   (0x80U)
#define SCT_DMAREQ0_DEV_7_SHIFT                  (7U)
/*! DEV_7 - DMA Request Event */
#define SCT_DMAREQ0_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK)

#define SCT_DMAREQ0_DEV_8_MASK                   (0x100U)
#define SCT_DMAREQ0_DEV_8_SHIFT                  (8U)
/*! DEV_8 - DMA Request Event */
#define SCT_DMAREQ0_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK)

#define SCT_DMAREQ0_DEV_9_MASK                   (0x200U)
#define SCT_DMAREQ0_DEV_9_SHIFT                  (9U)
/*! DEV_9 - DMA Request Event */
#define SCT_DMAREQ0_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK)

#define SCT_DMAREQ0_DEV_10_MASK                  (0x400U)
#define SCT_DMAREQ0_DEV_10_SHIFT                 (10U)
/*! DEV_10 - DMA Request Event */
#define SCT_DMAREQ0_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK)

#define SCT_DMAREQ0_DEV_11_MASK                  (0x800U)
#define SCT_DMAREQ0_DEV_11_SHIFT                 (11U)
/*! DEV_11 - DMA Request Event */
#define SCT_DMAREQ0_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK)

#define SCT_DMAREQ0_DEV_12_MASK                  (0x1000U)
#define SCT_DMAREQ0_DEV_12_SHIFT                 (12U)
/*! DEV_12 - DMA Request Event */
#define SCT_DMAREQ0_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK)

#define SCT_DMAREQ0_DEV_13_MASK                  (0x2000U)
#define SCT_DMAREQ0_DEV_13_SHIFT                 (13U)
/*! DEV_13 - DMA Request Event */
#define SCT_DMAREQ0_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK)

#define SCT_DMAREQ0_DEV_14_MASK                  (0x4000U)
#define SCT_DMAREQ0_DEV_14_SHIFT                 (14U)
/*! DEV_14 - DMA Request Event */
#define SCT_DMAREQ0_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK)

#define SCT_DMAREQ0_DEV_15_MASK                  (0x8000U)
#define SCT_DMAREQ0_DEV_15_SHIFT                 (15U)
/*! DEV_15 - DMA Request Event */
#define SCT_DMAREQ0_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK)

#define SCT_DMAREQ0_DRL0_MASK                    (0x40000000U)
#define SCT_DMAREQ0_DRL0_SHIFT                   (30U)
/*! DRL0 - DMA Request Low 0 */
#define SCT_DMAREQ0_DRL0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)

#define SCT_DMAREQ0_DRQ0_MASK                    (0x80000000U)
#define SCT_DMAREQ0_DRQ0_SHIFT                   (31U)
/*! DRQ0 - DMA Request 0 State */
#define SCT_DMAREQ0_DRQ0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
/*! @} */

/*! @name DMAREQ1 - DMA Request 1 */
/*! @{ */

#define SCT_DMAREQ1_DEV_0_MASK                   (0x1U)
#define SCT_DMAREQ1_DEV_0_SHIFT                  (0U)
/*! DEV_0 - DMA Request Event */
#define SCT_DMAREQ1_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK)

#define SCT_DMAREQ1_DEV_1_MASK                   (0x2U)
#define SCT_DMAREQ1_DEV_1_SHIFT                  (1U)
/*! DEV_1 - DMA Request Event */
#define SCT_DMAREQ1_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)

#define SCT_DMAREQ1_DEV_2_MASK                   (0x4U)
#define SCT_DMAREQ1_DEV_2_SHIFT                  (2U)
/*! DEV_2 - DMA Request Event */
#define SCT_DMAREQ1_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK)

#define SCT_DMAREQ1_DEV_3_MASK                   (0x8U)
#define SCT_DMAREQ1_DEV_3_SHIFT                  (3U)
/*! DEV_3 - DMA Request Event */
#define SCT_DMAREQ1_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK)

#define SCT_DMAREQ1_DEV_4_MASK                   (0x10U)
#define SCT_DMAREQ1_DEV_4_SHIFT                  (4U)
/*! DEV_4 - DMA Request Event */
#define SCT_DMAREQ1_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK)

#define SCT_DMAREQ1_DEV_5_MASK                   (0x20U)
#define SCT_DMAREQ1_DEV_5_SHIFT                  (5U)
/*! DEV_5 - DMA Request Event */
#define SCT_DMAREQ1_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK)

#define SCT_DMAREQ1_DEV_6_MASK                   (0x40U)
#define SCT_DMAREQ1_DEV_6_SHIFT                  (6U)
/*! DEV_6 - DMA Request Event */
#define SCT_DMAREQ1_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK)

#define SCT_DMAREQ1_DEV_7_MASK                   (0x80U)
#define SCT_DMAREQ1_DEV_7_SHIFT                  (7U)
/*! DEV_7 - DMA Request Event */
#define SCT_DMAREQ1_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK)

#define SCT_DMAREQ1_DEV_8_MASK                   (0x100U)
#define SCT_DMAREQ1_DEV_8_SHIFT                  (8U)
/*! DEV_8 - DMA Request Event */
#define SCT_DMAREQ1_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK)

#define SCT_DMAREQ1_DEV_9_MASK                   (0x200U)
#define SCT_DMAREQ1_DEV_9_SHIFT                  (9U)
/*! DEV_9 - DMA Request Event */
#define SCT_DMAREQ1_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK)

#define SCT_DMAREQ1_DEV_10_MASK                  (0x400U)
#define SCT_DMAREQ1_DEV_10_SHIFT                 (10U)
/*! DEV_10 - DMA Request Event */
#define SCT_DMAREQ1_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK)

#define SCT_DMAREQ1_DEV_11_MASK                  (0x800U)
#define SCT_DMAREQ1_DEV_11_SHIFT                 (11U)
/*! DEV_11 - DMA Request Event */
#define SCT_DMAREQ1_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK)

#define SCT_DMAREQ1_DEV_12_MASK                  (0x1000U)
#define SCT_DMAREQ1_DEV_12_SHIFT                 (12U)
/*! DEV_12 - DMA Request Event */
#define SCT_DMAREQ1_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK)

#define SCT_DMAREQ1_DEV_13_MASK                  (0x2000U)
#define SCT_DMAREQ1_DEV_13_SHIFT                 (13U)
/*! DEV_13 - DMA Request Event */
#define SCT_DMAREQ1_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK)

#define SCT_DMAREQ1_DEV_14_MASK                  (0x4000U)
#define SCT_DMAREQ1_DEV_14_SHIFT                 (14U)
/*! DEV_14 - DMA Request Event */
#define SCT_DMAREQ1_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK)

#define SCT_DMAREQ1_DEV_15_MASK                  (0x8000U)
#define SCT_DMAREQ1_DEV_15_SHIFT                 (15U)
/*! DEV_15 - DMA Request Event */
#define SCT_DMAREQ1_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK)

#define SCT_DMAREQ1_DRL1_MASK                    (0x40000000U)
#define SCT_DMAREQ1_DRL1_SHIFT                   (30U)
/*! DRL1 - DMA Request Low 1 */
#define SCT_DMAREQ1_DRL1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)

#define SCT_DMAREQ1_DRQ1_MASK                    (0x80000000U)
#define SCT_DMAREQ1_DRQ1_SHIFT                   (31U)
/*! DRQ1 - DMA Request 1 State */
#define SCT_DMAREQ1_DRQ1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
/*! @} */

/*! @name EVEN - Event Interrupt Enable */
/*! @{ */

#define SCT_EVEN_IEN0_MASK                       (0x1U)
#define SCT_EVEN_IEN0_SHIFT                      (0U)
/*! IEN0 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN0(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK)

#define SCT_EVEN_IEN1_MASK                       (0x2U)
#define SCT_EVEN_IEN1_SHIFT                      (1U)
/*! IEN1 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN1(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK)

#define SCT_EVEN_IEN2_MASK                       (0x4U)
#define SCT_EVEN_IEN2_SHIFT                      (2U)
/*! IEN2 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN2(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK)

#define SCT_EVEN_IEN3_MASK                       (0x8U)
#define SCT_EVEN_IEN3_SHIFT                      (3U)
/*! IEN3 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN3(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK)

#define SCT_EVEN_IEN4_MASK                       (0x10U)
#define SCT_EVEN_IEN4_SHIFT                      (4U)
/*! IEN4 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN4(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK)

#define SCT_EVEN_IEN5_MASK                       (0x20U)
#define SCT_EVEN_IEN5_SHIFT                      (5U)
/*! IEN5 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN5(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK)

#define SCT_EVEN_IEN6_MASK                       (0x40U)
#define SCT_EVEN_IEN6_SHIFT                      (6U)
/*! IEN6 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN6(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK)

#define SCT_EVEN_IEN7_MASK                       (0x80U)
#define SCT_EVEN_IEN7_SHIFT                      (7U)
/*! IEN7 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN7(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK)

#define SCT_EVEN_IEN8_MASK                       (0x100U)
#define SCT_EVEN_IEN8_SHIFT                      (8U)
/*! IEN8 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN8(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK)

#define SCT_EVEN_IEN9_MASK                       (0x200U)
#define SCT_EVEN_IEN9_SHIFT                      (9U)
/*! IEN9 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN9(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK)

#define SCT_EVEN_IEN10_MASK                      (0x400U)
#define SCT_EVEN_IEN10_SHIFT                     (10U)
/*! IEN10 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN10(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK)

#define SCT_EVEN_IEN11_MASK                      (0x800U)
#define SCT_EVEN_IEN11_SHIFT                     (11U)
/*! IEN11 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN11(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK)

#define SCT_EVEN_IEN12_MASK                      (0x1000U)
#define SCT_EVEN_IEN12_SHIFT                     (12U)
/*! IEN12 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN12(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK)

#define SCT_EVEN_IEN13_MASK                      (0x2000U)
#define SCT_EVEN_IEN13_SHIFT                     (13U)
/*! IEN13 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN13(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK)

#define SCT_EVEN_IEN14_MASK                      (0x4000U)
#define SCT_EVEN_IEN14_SHIFT                     (14U)
/*! IEN14 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN14(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK)

#define SCT_EVEN_IEN15_MASK                      (0x8000U)
#define SCT_EVEN_IEN15_SHIFT                     (15U)
/*! IEN15 - Event Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SCT_EVEN_IEN15(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK)
/*! @} */

/*! @name EVFLAG - Event Flag */
/*! @{ */

#define SCT_EVFLAG_FLAG0_MASK                    (0x1U)
#define SCT_EVFLAG_FLAG0_SHIFT                   (0U)
/*! FLAG0 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK)

#define SCT_EVFLAG_FLAG1_MASK                    (0x2U)
#define SCT_EVFLAG_FLAG1_SHIFT                   (1U)
/*! FLAG1 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK)

#define SCT_EVFLAG_FLAG2_MASK                    (0x4U)
#define SCT_EVFLAG_FLAG2_SHIFT                   (2U)
/*! FLAG2 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG2(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK)

#define SCT_EVFLAG_FLAG3_MASK                    (0x8U)
#define SCT_EVFLAG_FLAG3_SHIFT                   (3U)
/*! FLAG3 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG3(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK)

#define SCT_EVFLAG_FLAG4_MASK                    (0x10U)
#define SCT_EVFLAG_FLAG4_SHIFT                   (4U)
/*! FLAG4 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG4(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK)

#define SCT_EVFLAG_FLAG5_MASK                    (0x20U)
#define SCT_EVFLAG_FLAG5_SHIFT                   (5U)
/*! FLAG5 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG5(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK)

#define SCT_EVFLAG_FLAG6_MASK                    (0x40U)
#define SCT_EVFLAG_FLAG6_SHIFT                   (6U)
/*! FLAG6 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG6(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK)

#define SCT_EVFLAG_FLAG7_MASK                    (0x80U)
#define SCT_EVFLAG_FLAG7_SHIFT                   (7U)
/*! FLAG7 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG7(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK)

#define SCT_EVFLAG_FLAG8_MASK                    (0x100U)
#define SCT_EVFLAG_FLAG8_SHIFT                   (8U)
/*! FLAG8 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG8(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK)

#define SCT_EVFLAG_FLAG9_MASK                    (0x200U)
#define SCT_EVFLAG_FLAG9_SHIFT                   (9U)
/*! FLAG9 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG9(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK)

#define SCT_EVFLAG_FLAG10_MASK                   (0x400U)
#define SCT_EVFLAG_FLAG10_SHIFT                  (10U)
/*! FLAG10 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG10(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK)

#define SCT_EVFLAG_FLAG11_MASK                   (0x800U)
#define SCT_EVFLAG_FLAG11_SHIFT                  (11U)
/*! FLAG11 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG11(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK)

#define SCT_EVFLAG_FLAG12_MASK                   (0x1000U)
#define SCT_EVFLAG_FLAG12_SHIFT                  (12U)
/*! FLAG12 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG12(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK)

#define SCT_EVFLAG_FLAG13_MASK                   (0x2000U)
#define SCT_EVFLAG_FLAG13_SHIFT                  (13U)
/*! FLAG13 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG13(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK)

#define SCT_EVFLAG_FLAG14_MASK                   (0x4000U)
#define SCT_EVFLAG_FLAG14_SHIFT                  (14U)
/*! FLAG14 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG14(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK)

#define SCT_EVFLAG_FLAG15_MASK                   (0x8000U)
#define SCT_EVFLAG_FLAG15_SHIFT                  (15U)
/*! FLAG15 - Event Flag
 *  0b0..No flag
 *  0b1..Event n flag
 */
#define SCT_EVFLAG_FLAG15(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK)
/*! @} */

/*! @name CONEN - Conflict Interrupt Enable */
/*! @{ */

#define SCT_CONEN_NCEN0_MASK                     (0x1U)
#define SCT_CONEN_NCEN0_SHIFT                    (0U)
/*! NCEN0 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK)

#define SCT_CONEN_NCEN1_MASK                     (0x2U)
#define SCT_CONEN_NCEN1_SHIFT                    (1U)
/*! NCEN1 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK)

#define SCT_CONEN_NCEN2_MASK                     (0x4U)
#define SCT_CONEN_NCEN2_SHIFT                    (2U)
/*! NCEN2 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK)

#define SCT_CONEN_NCEN3_MASK                     (0x8U)
#define SCT_CONEN_NCEN3_SHIFT                    (3U)
/*! NCEN3 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK)

#define SCT_CONEN_NCEN4_MASK                     (0x10U)
#define SCT_CONEN_NCEN4_SHIFT                    (4U)
/*! NCEN4 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK)

#define SCT_CONEN_NCEN5_MASK                     (0x20U)
#define SCT_CONEN_NCEN5_SHIFT                    (5U)
/*! NCEN5 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK)

#define SCT_CONEN_NCEN6_MASK                     (0x40U)
#define SCT_CONEN_NCEN6_SHIFT                    (6U)
/*! NCEN6 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK)

#define SCT_CONEN_NCEN7_MASK                     (0x80U)
#define SCT_CONEN_NCEN7_SHIFT                    (7U)
/*! NCEN7 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK)

#define SCT_CONEN_NCEN8_MASK                     (0x100U)
#define SCT_CONEN_NCEN8_SHIFT                    (8U)
/*! NCEN8 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK)

#define SCT_CONEN_NCEN9_MASK                     (0x200U)
#define SCT_CONEN_NCEN9_SHIFT                    (9U)
/*! NCEN9 - No Change Conflict Event and Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK)
/*! @} */

/*! @name CONFLAG - Conflict Flag */
/*! @{ */

#define SCT_CONFLAG_NCFLAG0_MASK                 (0x1U)
#define SCT_CONFLAG_NCFLAG0_SHIFT                (0U)
/*! NCFLAG0 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK)

#define SCT_CONFLAG_NCFLAG1_MASK                 (0x2U)
#define SCT_CONFLAG_NCFLAG1_SHIFT                (1U)
/*! NCFLAG1 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK)

#define SCT_CONFLAG_NCFLAG2_MASK                 (0x4U)
#define SCT_CONFLAG_NCFLAG2_SHIFT                (2U)
/*! NCFLAG2 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK)

#define SCT_CONFLAG_NCFLAG3_MASK                 (0x8U)
#define SCT_CONFLAG_NCFLAG3_SHIFT                (3U)
/*! NCFLAG3 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK)

#define SCT_CONFLAG_NCFLAG4_MASK                 (0x10U)
#define SCT_CONFLAG_NCFLAG4_SHIFT                (4U)
/*! NCFLAG4 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG4(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK)

#define SCT_CONFLAG_NCFLAG5_MASK                 (0x20U)
#define SCT_CONFLAG_NCFLAG5_SHIFT                (5U)
/*! NCFLAG5 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG5(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK)

#define SCT_CONFLAG_NCFLAG6_MASK                 (0x40U)
#define SCT_CONFLAG_NCFLAG6_SHIFT                (6U)
/*! NCFLAG6 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG6(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK)

#define SCT_CONFLAG_NCFLAG7_MASK                 (0x80U)
#define SCT_CONFLAG_NCFLAG7_SHIFT                (7U)
/*! NCFLAG7 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG7(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK)

#define SCT_CONFLAG_NCFLAG8_MASK                 (0x100U)
#define SCT_CONFLAG_NCFLAG8_SHIFT                (8U)
/*! NCFLAG8 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG8(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK)

#define SCT_CONFLAG_NCFLAG9_MASK                 (0x200U)
#define SCT_CONFLAG_NCFLAG9_SHIFT                (9U)
/*! NCFLAG9 - No Change Conflict Event Flag
 *  0b0..Did not occur
 *  0b1..Occurred
 */
#define SCT_CONFLAG_NCFLAG9(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK)

#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
/*! BUSERRL - Bus Error Low or Unified */
#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)

#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
/*! BUSERRH - Bus Error High */
#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
/*! @} */

/*! @name CAPL - SCT_CAPL register */
/*! @{ */

#define SCT_CAPL_CAPL_MASK                       (0xFFFFU)
#define SCT_CAPL_CAPL_SHIFT                      (0U)
#define SCT_CAPL_CAPL(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
/*! @} */

/* The count of SCT_CAPL */
#define SCT_CAPL_COUNT                           (16U)

/*! @name CAPH - SCT_CAPH register */
/*! @{ */

#define SCT_CAPH_CAPH_MASK                       (0xFFFFU)
#define SCT_CAPH_CAPH_SHIFT                      (0U)
#define SCT_CAPH_CAPH(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
/*! @} */

/* The count of SCT_CAPH */
#define SCT_CAPH_COUNT                           (16U)

/*! @name CAP - Capture Value */
/*! @{ */

#define SCT_CAP_CAPn_L_MASK                      (0xFFFFU)
#define SCT_CAP_CAPn_L_SHIFT                     (0U)
/*! CAPn_L - Capture Low */
#define SCT_CAP_CAPn_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)

#define SCT_CAP_CAPn_H_MASK                      (0xFFFF0000U)
#define SCT_CAP_CAPn_H_SHIFT                     (16U)
/*! CAPn_H - Capture High */
#define SCT_CAP_CAPn_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
/*! @} */

/* The count of SCT_CAP */
#define SCT_CAP_COUNT                            (16U)

/*! @name MATCHL - SCT_MATCHL register */
/*! @{ */

#define SCT_MATCHL_MATCHL_MASK                   (0xFFFFU)
#define SCT_MATCHL_MATCHL_SHIFT                  (0U)
#define SCT_MATCHL_MATCHL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
/*! @} */

/* The count of SCT_MATCHL */
#define SCT_MATCHL_COUNT                         (16U)

/*! @name MATCHH - SCT_MATCHH register */
/*! @{ */

#define SCT_MATCHH_MATCHH_MASK                   (0xFFFFU)
#define SCT_MATCHH_MATCHH_SHIFT                  (0U)
#define SCT_MATCHH_MATCHH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
/*! @} */

/* The count of SCT_MATCHH */
#define SCT_MATCHH_COUNT                         (16U)

/*! @name MATCH - Match Value */
/*! @{ */

#define SCT_MATCH_MATCHn_L_MASK                  (0xFFFFU)
#define SCT_MATCH_MATCHn_L_SHIFT                 (0U)
/*! MATCHn_L - Match Low */
#define SCT_MATCH_MATCHn_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)

#define SCT_MATCH_MATCHn_H_MASK                  (0xFFFF0000U)
#define SCT_MATCH_MATCHn_H_SHIFT                 (16U)
/*! MATCHn_H - Match High */
#define SCT_MATCH_MATCHn_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
/*! @} */

/* The count of SCT_MATCH */
#define SCT_MATCH_COUNT                          (16U)

/*! @name FRACMAT - Fractional Match */
/*! @{ */

#define SCT_FRACMAT_FRACMAT_L_MASK               (0xFU)
#define SCT_FRACMAT_FRACMAT_L_SHIFT              (0U)
/*! FRACMAT_L - Fractional Match Low */
#define SCT_FRACMAT_FRACMAT_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_L_SHIFT)) & SCT_FRACMAT_FRACMAT_L_MASK)

#define SCT_FRACMAT_FRACMAT_H_MASK               (0xF0000U)
#define SCT_FRACMAT_FRACMAT_H_SHIFT              (16U)
/*! FRACMAT_H - Fractional Match High */
#define SCT_FRACMAT_FRACMAT_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_H_SHIFT)) & SCT_FRACMAT_FRACMAT_H_MASK)
/*! @} */

/* The count of SCT_FRACMAT */
#define SCT_FRACMAT_COUNT                        (6U)

/*! @name CAPCTRLL - SCT_CAPCTRLL register */
/*! @{ */

#define SCT_CAPCTRLL_CAPCTRLL_MASK               (0xFFFFU)
#define SCT_CAPCTRLL_CAPCTRLL_SHIFT              (0U)
#define SCT_CAPCTRLL_CAPCTRLL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
/*! @} */

/* The count of SCT_CAPCTRLL */
#define SCT_CAPCTRLL_COUNT                       (16U)

/*! @name CAPCTRLH - SCT_CAPCTRLH register */
/*! @{ */

#define SCT_CAPCTRLH_CAPCTRLH_MASK               (0xFFFFU)
#define SCT_CAPCTRLH_CAPCTRLH_SHIFT              (0U)
#define SCT_CAPCTRLH_CAPCTRLH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
/*! @} */

/* The count of SCT_CAPCTRLH */
#define SCT_CAPCTRLH_COUNT                       (16U)

/*! @name SCTCAPCTRL_CAPCTRL - Capture Control */
/*! @{ */

#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK    (0xFFFFU)
#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT   (0U)
/*! CAPCONn_L - Capture Control Low */
#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L(x)      (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK)

#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK    (0xFFFF0000U)
#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT   (16U)
/*! CAPCONn_H - Capture Control High */
#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H(x)      (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK)
/*! @} */

/* The count of SCT_SCTCAPCTRL_CAPCTRL */
#define SCT_SCTCAPCTRL_CAPCTRL_COUNT             (16U)

/*! @name MATCHRELL - SCT_MATCHRELL register */
/*! @{ */

#define SCT_MATCHRELL_MATCHRELL_MASK             (0xFFFFU)
#define SCT_MATCHRELL_MATCHRELL_SHIFT            (0U)
#define SCT_MATCHRELL_MATCHRELL(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
/*! @} */

/* The count of SCT_MATCHRELL */
#define SCT_MATCHRELL_COUNT                      (16U)

/*! @name MATCHRELH - SCT_MATCHRELH register */
/*! @{ */

#define SCT_MATCHRELH_MATCHRELH_MASK             (0xFFFFU)
#define SCT_MATCHRELH_MATCHRELH_SHIFT            (0U)
#define SCT_MATCHRELH_MATCHRELH(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
/*! @} */

/* The count of SCT_MATCHRELH */
#define SCT_MATCHRELH_COUNT                      (16U)

/*! @name MATCHREL - Match Reload Value */
/*! @{ */

#define SCT_MATCHREL_RELOADn_L_MASK              (0xFFFFU)
#define SCT_MATCHREL_RELOADn_L_SHIFT             (0U)
/*! RELOADn_L - Reload Low */
#define SCT_MATCHREL_RELOADn_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)

#define SCT_MATCHREL_RELOADn_H_MASK              (0xFFFF0000U)
#define SCT_MATCHREL_RELOADn_H_SHIFT             (16U)
/*! RELOADn_H - Reload High */
#define SCT_MATCHREL_RELOADn_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
/*! @} */

/* The count of SCT_MATCHREL */
#define SCT_MATCHREL_COUNT                       (16U)

/*! @name FRACMATREL - Fractional Match Reload */
/*! @{ */

#define SCT_FRACMATREL_RELFRAC_L_MASK            (0xFU)
#define SCT_FRACMATREL_RELFRAC_L_SHIFT           (0U)
/*! RELFRAC_L - Reload Fractional Match Low */
#define SCT_FRACMATREL_RELFRAC_L(x)              (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_L_SHIFT)) & SCT_FRACMATREL_RELFRAC_L_MASK)

#define SCT_FRACMATREL_RELFRAC_H_MASK            (0xF0000U)
#define SCT_FRACMATREL_RELFRAC_H_SHIFT           (16U)
/*! RELFRAC_H - Reload Fractional Match High */
#define SCT_FRACMATREL_RELFRAC_H(x)              (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_H_SHIFT)) & SCT_FRACMATREL_RELFRAC_H_MASK)
/*! @} */

/* The count of SCT_FRACMATREL */
#define SCT_FRACMATREL_COUNT                     (6U)

/*! @name EV_STATE - Event n State */
/*! @{ */

#define SCT_EV_STATE_STATEMSKn_MASK              (0xFFFFFFFFU)
#define SCT_EV_STATE_STATEMSKn_SHIFT             (0U)
/*! STATEMSKn - Event State Mask */
#define SCT_EV_STATE_STATEMSKn(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
/*! @} */

/* The count of SCT_EV_STATE */
#define SCT_EV_STATE_COUNT                       (16U)

/*! @name EV_CTRL - Event n Control */
/*! @{ */

#define SCT_EV_CTRL_MATCHSEL_MASK                (0xFU)
#define SCT_EV_CTRL_MATCHSEL_SHIFT               (0U)
/*! MATCHSEL - Match Select */
#define SCT_EV_CTRL_MATCHSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)

#define SCT_EV_CTRL_HEVENT_MASK                  (0x10U)
#define SCT_EV_CTRL_HEVENT_SHIFT                 (4U)
/*! HEVENT - High Event
 *  0b0..Low counter (selects the L state and the L match register that the MATCHSEL field specifies)
 *  0b1..High counter (selects the H state and the H match register that the MATCHSEL field specifies)
 */
#define SCT_EV_CTRL_HEVENT(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)

#define SCT_EV_CTRL_OUTSEL_MASK                  (0x20U)
#define SCT_EV_CTRL_OUTSEL_SHIFT                 (5U)
/*! OUTSEL - Input and Output Select
 *  0b0..Inputs
 *  0b1..Outputs
 */
#define SCT_EV_CTRL_OUTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)

#define SCT_EV_CTRL_IOSEL_MASK                   (0x3C0U)
#define SCT_EV_CTRL_IOSEL_SHIFT                  (6U)
/*! IOSEL - Input or Output Signal Select */
#define SCT_EV_CTRL_IOSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)

#define SCT_EV_CTRL_IOCOND_MASK                  (0xC00U)
#define SCT_EV_CTRL_IOCOND_SHIFT                 (10U)
/*! IOCOND - Input or Output Condition
 *  0b00..Low
 *  0b01..Rise
 *  0b10..Fall
 *  0b11..High
 */
#define SCT_EV_CTRL_IOCOND(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)

#define SCT_EV_CTRL_COMBMODE_MASK                (0x3000U)
#define SCT_EV_CTRL_COMBMODE_SHIFT               (12U)
/*! COMBMODE - Combination Mode
 *  0b00..OR (the event occurs when either the specified match or I/O condition occurs)
 *  0b01..MATCH (uses the specified match only)
 *  0b10..IO (uses the specified I/O condition only)
 *  0b11..AND (the event occurs when the specified match and I/O condition occur simultaneously)
 */
#define SCT_EV_CTRL_COMBMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)

#define SCT_EV_CTRL_STATELD_MASK                 (0x4000U)
#define SCT_EV_CTRL_STATELD_SHIFT                (14U)
/*! STATELD - State Load
 *  0b0..Value of STATEV added to that of STATE (the carry out is ignored)
 *  0b1..Value of STATEV loaded into that of STATE
 */
#define SCT_EV_CTRL_STATELD(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)

#define SCT_EV_CTRL_STATEV_MASK                  (0xF8000U)
#define SCT_EV_CTRL_STATEV_SHIFT                 (15U)
/*! STATEV - State Value */
#define SCT_EV_CTRL_STATEV(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)

#define SCT_EV_CTRL_MATCHMEM_MASK                (0x100000U)
#define SCT_EV_CTRL_MATCHMEM_SHIFT               (20U)
/*! MATCHMEM - Match Mem */
#define SCT_EV_CTRL_MATCHMEM(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)

#define SCT_EV_CTRL_DIRECTION_MASK               (0x600000U)
#define SCT_EV_CTRL_DIRECTION_SHIFT              (21U)
/*! DIRECTION - Direction
 *  0b00..Direction independent (event triggered regardless of the count direction)
 *  0b01..Counting up (event triggered only during up-counting when CTRL[BIDIR] = 1)
 *  0b10..Counting down (event triggered only during down-counting when CTRL[BIDIR] = 1)
 *  0b11..Reserved
 */
#define SCT_EV_CTRL_DIRECTION(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
/*! @} */

/* The count of SCT_EV_CTRL */
#define SCT_EV_CTRL_COUNT                        (16U)

/*! @name OUT_SET - Output n Set */
/*! @{ */

#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
#define SCT_OUT_SET_SET_SHIFT                    (0U)
/*! SET - Set Output */
#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
/*! @} */

/* The count of SCT_OUT_SET */
#define SCT_OUT_SET_COUNT                        (10U)

/*! @name OUT_CLR - Output n Clear */
/*! @{ */

#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
/*! CLR - Clear Output */
#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
/*! @} */

/* The count of SCT_OUT_CLR */
#define SCT_OUT_CLR_COUNT                        (10U)


/*!
 * @}
 */ /* end of group SCT_Register_Masks */


/* SCT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SCT0 base address */
  #define SCT0_BASE                                (0x50114000u)
  /** Peripheral SCT0 base address */
  #define SCT0_BASE_NS                             (0x40114000u)
  /** Peripheral SCT0 base pointer */
  #define SCT0                                     ((SCT_Type *)SCT0_BASE)
  /** Peripheral SCT0 base pointer */
  #define SCT0_NS                                  ((SCT_Type *)SCT0_BASE_NS)
  /** Array initializer of SCT peripheral base addresses */
  #define SCT_BASE_ADDRS                           { SCT0_BASE }
  /** Array initializer of SCT peripheral base pointers */
  #define SCT_BASE_PTRS                            { SCT0 }
  /** Array initializer of SCT peripheral base addresses */
  #define SCT_BASE_ADDRS_NS                        { SCT0_BASE_NS }
  /** Array initializer of SCT peripheral base pointers */
  #define SCT_BASE_PTRS_NS                         { SCT0_NS }
#else
  /** Peripheral SCT0 base address */
  #define SCT0_BASE                                (0x40114000u)
  /** Peripheral SCT0 base pointer */
  #define SCT0                                     ((SCT_Type *)SCT0_BASE)
  /** Array initializer of SCT peripheral base addresses */
  #define SCT_BASE_ADDRS                           { SCT0_BASE }
  /** Array initializer of SCT peripheral base pointers */
  #define SCT_BASE_PTRS                            { SCT0 }
#endif

/*!
 * @}
 */ /* end of group SCT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SDADC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SDADC_Peripheral_Access_Layer SDADC Peripheral Access Layer
 * @{
 */

/** SDADC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __IO uint32_t ADC_CTL_0;                         /**< ADC Control 0, offset: 0x4 */
  __IO uint32_t ADC_CTL_1;                         /**< ADC Control 1, offset: 0x8 */
  __IO uint32_t ADC_CTL_2;                         /**< ADC Control 2, offset: 0xC */
  __IO uint32_t LDO_CTL;                           /**< LDO Control, offset: 0x10 */
  __IO uint32_t REF_CTL;                           /**< Reference Control, offset: 0x14 */
       uint8_t RESERVED_0[4];
  __IO uint32_t DECIMATOR_CTL_0;                   /**< Decimator Control 0, offset: 0x1C */
  __IO uint32_t DECIMATOR_CTL_1;                   /**< Decimator Control 1, offset: 0x20 */
  __IO uint32_t DECIMATOR_CTL_2;                   /**< Decimator Control 2, offset: 0x24 */
  __IO uint32_t DECIMATOR_CTL_3;                   /**< Decimator Control 3, offset: 0x28 */
  __IO uint32_t DECIMATOR_CTL_4;                   /**< Decimator Control 4, offset: 0x2C */
  __IO uint32_t DC_LOOP_CTL_0;                     /**< DC Loop Control 0, offset: 0x30 */
  __IO uint32_t DC_LOOP_CTL_1;                     /**< DC Loop Control 1, offset: 0x34 */
  __IO uint32_t FIFO_WR_RD_CTL;                    /**< FIFO Write Read Control, offset: 0x38 */
  __IO uint32_t FIFO_WATERMARK_CTL;                /**< FIFO Watermark Control, offset: 0x3C */
  __IO uint32_t FIFO_WATERMARK_ERROR_CTL;          /**< FIFO Watermark Error Control, offset: 0x40 */
  __I  uint32_t FIFO_WATERMARK_ERROR_ST;           /**< FIFO Watermark Error Status, offset: 0x44 */
  __I  uint32_t FIFO_0_P;                          /**< FIFO 0 P, offset: 0x48 */
  __I  uint32_t FIFO_0_N;                          /**< FIFO 0 N, offset: 0x4C */
  __I  uint32_t FIFO_1_P;                          /**< FIFO 1 P, offset: 0x50 */
  __I  uint32_t FIFO_1_N;                          /**< FIFO 1 N, offset: 0x54 */
  __I  uint32_t FIFO_2_P;                          /**< FIFO 2 P, offset: 0x58 */
  __I  uint32_t FIFO_2_N;                          /**< FIFO 2 N, offset: 0x5C */
  __I  uint32_t FIFO_3_P;                          /**< FIFO 3 P, offset: 0x60 */
  __I  uint32_t FIFO_3_N;                          /**< FIFO 3 N, offset: 0x64 */
       uint8_t RESERVED_1[4];
  __I  uint32_t FIFO_ENTRIES_AVAIL_0;              /**< FIFO Entries Availability 0, offset: 0x6C */
  __I  uint32_t FIFO_ENTRIES_AVAIL_1;              /**< FIFO Entries Availability 1, offset: 0x70 */
  __IO uint32_t FIFO_INTERRUPT;                    /**< FIFO Interrupt, offset: 0x74 */
} SDADC_Type;

/* ----------------------------------------------------------------------------
   -- SDADC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SDADC_Register_Masks SDADC Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define SDADC_VERID_MINOR_MASK                   (0xFF0000U)
#define SDADC_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number */
#define SDADC_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << SDADC_VERID_MINOR_SHIFT)) & SDADC_VERID_MINOR_MASK)

#define SDADC_VERID_MAJOR_MASK                   (0xFF000000U)
#define SDADC_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number */
#define SDADC_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << SDADC_VERID_MAJOR_SHIFT)) & SDADC_VERID_MAJOR_MASK)
/*! @} */

/*! @name ADC_CTL_0 - ADC Control 0 */
/*! @{ */

#define SDADC_ADC_CTL_0_COMP_ADCN_ENABLE_MASK    (0xFU)
#define SDADC_ADC_CTL_0_COMP_ADCN_ENABLE_SHIFT   (0U)
/*! COMP_ADCN_ENABLE - Compensation ADCn Enable
 *  0b1xxx..Enables for ADCn[3]
 *  0b0xxx..Disables for ADCn[3]
 *  0bx1xx..Enables for ADCn[2]
 *  0bx0xx..Disables for ADCn[2]
 *  0bxx1x..Enables for ADCn[1]
 *  0bxx0x..Disables for ADCn[1]
 *  0bxxx1..Enables for ADCn[0]
 *  0bxxx0..Disables for ADCn[0]
 */
#define SDADC_ADC_CTL_0_COMP_ADCN_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_0_COMP_ADCN_ENABLE_SHIFT)) & SDADC_ADC_CTL_0_COMP_ADCN_ENABLE_MASK)

#define SDADC_ADC_CTL_0_COMP_ADCP_ENABLE_MASK    (0xF0U)
#define SDADC_ADC_CTL_0_COMP_ADCP_ENABLE_SHIFT   (4U)
/*! COMP_ADCP_ENABLE - Compensation ADCp Enable
 *  0b1xxx..Enables for ADCp[3]
 *  0b0xxx..Disables for ADCp[3]
 *  0bx1xx..Enables for ADCp[2]
 *  0bx0xx..Disables for ADCp[2]
 *  0bxx1x..Enables for ADCp[1]
 *  0bxx0x..Disables for ADCp[1]
 *  0bxxx1..Enables for ADCp[0]
 *  0bxxx0..Disables for ADCp[0]
 */
#define SDADC_ADC_CTL_0_COMP_ADCP_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_0_COMP_ADCP_ENABLE_SHIFT)) & SDADC_ADC_CTL_0_COMP_ADCP_ENABLE_MASK)

#define SDADC_ADC_CTL_0_RST_AN_ADCN_MASK         (0xF00U)
#define SDADC_ADC_CTL_0_RST_AN_ADCN_SHIFT        (8U)
/*! RST_AN_ADCN - Reset ADCn
 *  0b0xxx..Reset for ADCn[3]
 *  0b1xxx..Operational for ADCn[3]
 *  0bx0xx..Reset for ADCn[2]
 *  0bx1xx..Operational for ADCn[2]
 *  0bxx0x..Reset for ADCn[1]
 *  0bxx1x..Operational for ADCn[1]
 *  0bxxx0..Reset for ADCn[0]
 *  0bxxx1..Operational for ADCn[0]
 */
#define SDADC_ADC_CTL_0_RST_AN_ADCN(x)           (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_0_RST_AN_ADCN_SHIFT)) & SDADC_ADC_CTL_0_RST_AN_ADCN_MASK)

#define SDADC_ADC_CTL_0_RST_AN_ADCP_MASK         (0xF000U)
#define SDADC_ADC_CTL_0_RST_AN_ADCP_SHIFT        (12U)
/*! RST_AN_ADCP - Reset ADCp
 *  0b0xxx..Reset for ADCp[3]
 *  0b1xxx..Operational for ADCp[3]
 *  0bx0xx..Reset for ADCp[2]
 *  0bx1xx..Operational for ADCp[2]
 *  0bxx0x..Reset for ADCp[1]
 *  0bxx1x..Operational for ADCp[1]
 *  0bxxx0..Reset for ADCp[0]
 *  0bxxx1..Operational for ADCp[0]
 */
#define SDADC_ADC_CTL_0_RST_AN_ADCP(x)           (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_0_RST_AN_ADCP_SHIFT)) & SDADC_ADC_CTL_0_RST_AN_ADCP_MASK)

#define SDADC_ADC_CTL_0_ADCN_POWER_ENABLE_MASK   (0xF000000U)
#define SDADC_ADC_CTL_0_ADCN_POWER_ENABLE_SHIFT  (24U)
/*! ADCN_POWER_ENABLE - ADCn Power Enable
 *  0b1xxx..Enables ADCn[3] and vin_n[3]
 *  0b0xxx..Disables ADCn[3] and vin_n[3]
 *  0bx1xx..Enables ADCn[2] and vin_n[2]
 *  0bx0xx..Disables ADCn[2] and vin_n[2]
 *  0bxx1x..Enables ADCn[1] and vin_n[1]
 *  0bxx0x..Disables ADCn[1] and vin_n[1]
 *  0bxxx1..Enables ADCn[0] and vin_n[0]
 *  0bxxx0..Disables ADCn[0] and vin_n[0]
 */
#define SDADC_ADC_CTL_0_ADCN_POWER_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_0_ADCN_POWER_ENABLE_SHIFT)) & SDADC_ADC_CTL_0_ADCN_POWER_ENABLE_MASK)

#define SDADC_ADC_CTL_0_ADCP_POWER_ENABLE_MASK   (0xF0000000U)
#define SDADC_ADC_CTL_0_ADCP_POWER_ENABLE_SHIFT  (28U)
/*! ADCP_POWER_ENABLE - ADCp Power Enable
 *  0b1xxx..Enables ADCp[3] and vin_p[3]
 *  0b0xxx..Disables ADCp[3] and vin_p[3]
 *  0bx1xx..Enables ADCp[2] and vin_p[2]
 *  0bx0xx..Disables ADCp[2] and vin_p[2]
 *  0bxx1x..Enables ADCp[1] and vin_p[1]
 *  0bxx0x..Disables ADCp[1] and vin_p[1]
 *  0bxxx1..Enables ADCp[0] and vin_p[0]
 *  0bxxx0..Disables ADCp[0] and vin_p[0]
 */
#define SDADC_ADC_CTL_0_ADCP_POWER_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_0_ADCP_POWER_ENABLE_SHIFT)) & SDADC_ADC_CTL_0_ADCP_POWER_ENABLE_MASK)
/*! @} */

/*! @name ADC_CTL_1 - ADC Control 1 */
/*! @{ */

#define SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE_MASK (0xF00U)
#define SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE_SHIFT (8U)
/*! DCLOOP_N_ANA_ENABLE - DC Loop N Analog Enable
 *  0b1xxx..Enables for ADCn[3]
 *  0b0xxx..Disables for ADCn[3]
 *  0bx1xx..Enables for ADCn[2]
 *  0bx0xx..Disables for ADCn[2]
 *  0bxx1x..Enables for ADCn[1]
 *  0bxx0x..Disables for ADCn[1]
 *  0bxxx1..Enables for ADCn[0]
 *  0bxxx0..Disables for ADCn[0]
 */
#define SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE_SHIFT)) & SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE_MASK)

#define SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE_MASK (0xF000U)
#define SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE_SHIFT (12U)
/*! DCLOOP_P_ANA_ENABLE - DC Loop P Analog Enable
 *  0b1xxx..Enables for ADCp[3]
 *  0b0xxx..Disables for ADCp[3]
 *  0bx1xx..Enables for ADCp[2]
 *  0bx0xx..Disables for ADCp[2]
 *  0bxx1x..Enables for ADCp[1]
 *  0bxx0x..Disables for ADCp[1]
 *  0bxxx1..Enables for ADCp[0]
 *  0bxxx0..Disables for ADCp[0]
 */
#define SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE_SHIFT)) & SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE_MASK)

#define SDADC_ADC_CTL_1_DIFF_ENABLE_MASK         (0xF000000U)
#define SDADC_ADC_CTL_1_DIFF_ENABLE_SHIFT        (24U)
/*! DIFF_ENABLE - Diff Enable
 *  0b1xxx..Configures ADCp[3] and ADCn[3] as differential pair input
 *  0b0xxx..ADCp[3] and ADCn[3] in SE mode
 *  0bx1xx..Configures ADCp[2] and ADCn[2] as differential pair input
 *  0bx0xx..ADCp[2] and ADCn[2] in SE mode
 *  0bxx1x..Configures ADCp[1] and ADCn[1] as differential pair input
 *  0bxx0x..ADCp[1] and ADCn[1] in SE mode
 *  0bxxx1..Configures ADCp[0] and ADCn[0] as differential pair input
 *  0bxxx0..ADCp[0] and ADCn[0] in SE mode
 */
#define SDADC_ADC_CTL_1_DIFF_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_1_DIFF_ENABLE_SHIFT)) & SDADC_ADC_CTL_1_DIFF_ENABLE_MASK)
/*! @} */

/*! @name ADC_CTL_2 - ADC Control 2 */
/*! @{ */

#define SDADC_ADC_CTL_2_SET_DITHER3_MASK         (0x70000U)
#define SDADC_ADC_CTL_2_SET_DITHER3_SHIFT        (16U)
/*! SET_DITHER3 - Set Dither 3
 *  0b000..Disables dither of ADCp[3] and ADCn[3].
 *  0b001-0b110..The higher the value, the stronger the dither
 *  0b111..Maximum dither amplitude for ADCp[3] and ADCn[3]
 */
#define SDADC_ADC_CTL_2_SET_DITHER3(x)           (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_2_SET_DITHER3_SHIFT)) & SDADC_ADC_CTL_2_SET_DITHER3_MASK)

#define SDADC_ADC_CTL_2_SET_DITHER2_MASK         (0x700000U)
#define SDADC_ADC_CTL_2_SET_DITHER2_SHIFT        (20U)
/*! SET_DITHER2 - Set Dither 2
 *  0b000..Disables dither of ADCp[2] and ADCn[2]
 *  0b001-0b110..The higher the value, the stronger the dither
 *  0b111..Maximum dither amplitude for ADCp[2] and ADCn[2]
 */
#define SDADC_ADC_CTL_2_SET_DITHER2(x)           (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_2_SET_DITHER2_SHIFT)) & SDADC_ADC_CTL_2_SET_DITHER2_MASK)

#define SDADC_ADC_CTL_2_SET_DITHER1_MASK         (0x7000000U)
#define SDADC_ADC_CTL_2_SET_DITHER1_SHIFT        (24U)
/*! SET_DITHER1 - Set Dither 1
 *  0b000..Disables dither of ADCp[1] and ADCn[1]
 *  0b001-0b110..The higher the value, the stronger the dither
 *  0b111..Maximum dither amplitude for ADCp[1] and ADCn[1]
 */
#define SDADC_ADC_CTL_2_SET_DITHER1(x)           (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_2_SET_DITHER1_SHIFT)) & SDADC_ADC_CTL_2_SET_DITHER1_MASK)

#define SDADC_ADC_CTL_2_SET_DITHER0_MASK         (0x70000000U)
#define SDADC_ADC_CTL_2_SET_DITHER0_SHIFT        (28U)
/*! SET_DITHER0 - Set Dither 0
 *  0b000..Disables dither of ADCp[0] and ADCn[0]
 *  0b001-0b110..The higher the value, the stronger the dither
 *  0b111..Maximum dither amplitude for ADCp[0] and ADCn[0]
 */
#define SDADC_ADC_CTL_2_SET_DITHER0(x)           (((uint32_t)(((uint32_t)(x)) << SDADC_ADC_CTL_2_SET_DITHER0_SHIFT)) & SDADC_ADC_CTL_2_SET_DITHER0_MASK)
/*! @} */

/*! @name LDO_CTL - LDO Control */
/*! @{ */

#define SDADC_LDO_CTL_LDO_SETTING_MASK           (0x3000U)
#define SDADC_LDO_CTL_LDO_SETTING_SHIFT          (12U)
/*! LDO_SETTING - LDO Setting
 *  0b00..To drive 1 SE or 1 Diff mode ADC (low power mode)
 *  0b01..To drive more than 1 ADCs
 *  0b10, 0b11..Not in use
 */
#define SDADC_LDO_CTL_LDO_SETTING(x)             (((uint32_t)(((uint32_t)(x)) << SDADC_LDO_CTL_LDO_SETTING_SHIFT)) & SDADC_LDO_CTL_LDO_SETTING_MASK)

#define SDADC_LDO_CTL_LDO_POWER_ENABLE_MASK      (0x100000U)
#define SDADC_LDO_CTL_LDO_POWER_ENABLE_SHIFT     (20U)
/*! LDO_POWER_ENABLE - LDO Power Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_LDO_CTL_LDO_POWER_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << SDADC_LDO_CTL_LDO_POWER_ENABLE_SHIFT)) & SDADC_LDO_CTL_LDO_POWER_ENABLE_MASK)
/*! @} */

/*! @name REF_CTL - Reference Control */
/*! @{ */

#define SDADC_REF_CTL_FAST_REF_ENABLE_MASK       (0x10000U)
#define SDADC_REF_CTL_FAST_REF_ENABLE_SHIFT      (16U)
/*! FAST_REF_ENABLE - Fast Reference Enable
 *  0b0..267 ms (retain mode) when bit20=0 | 38 ms (low noise) when bit20=1
 *  0b1..66.5 ms (low power) when bit20=0 | 1 ms (fast charging) when bit20=1
 */
#define SDADC_REF_CTL_FAST_REF_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << SDADC_REF_CTL_FAST_REF_ENABLE_SHIFT)) & SDADC_REF_CTL_FAST_REF_ENABLE_MASK)

#define SDADC_REF_CTL_PWR_FAST_REF_ENABLE_MASK   (0x100000U)
#define SDADC_REF_CTL_PWR_FAST_REF_ENABLE_SHIFT  (20U)
/*! PWR_FAST_REF_ENABLE - Power Fast Reference Enable
 *  0b0..267 ms (retain mode) when bit16=0 | 66.5 ms (low power) when bit16=1
 *  0b1..38 ms (low noise) when bit16=0 | 1 ms (fast charging) when bit16=1
 */
#define SDADC_REF_CTL_PWR_FAST_REF_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << SDADC_REF_CTL_PWR_FAST_REF_ENABLE_SHIFT)) & SDADC_REF_CTL_PWR_FAST_REF_ENABLE_MASK)

#define SDADC_REF_CTL_REF_POWER_ENABLE_MASK      (0x10000000U)
#define SDADC_REF_CTL_REF_POWER_ENABLE_SHIFT     (28U)
/*! REF_POWER_ENABLE - Reference Power Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_REF_CTL_REF_POWER_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << SDADC_REF_CTL_REF_POWER_ENABLE_SHIFT)) & SDADC_REF_CTL_REF_POWER_ENABLE_MASK)
/*! @} */

/*! @name DECIMATOR_CTL_0 - Decimator Control 0 */
/*! @{ */

#define SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE_MASK (0xF00U)
#define SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE_SHIFT (8U)
/*! POL_INV_P_ENABLE - Polarity Inverter P Enable
 *  0b0xxx..Disables at Decimator_p[3]
 *  0b1xxx..Enables at Decimator_p[3]
 *  0bx0xx..Disables at Decimator_p[2]
 *  0bx1xx..Enables at Decimator_p[2]
 *  0bxx0x..Disables at Decimator_p[1]
 *  0bxx1x..Enables at Decimator_p[1]
 *  0bxxx0..Disables at Decimator_p[0]
 *  0bxxx1..Enables at Decimator_p[0]
 */
#define SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE_SHIFT)) & SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE_MASK)

#define SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE_MASK (0xF000U)
#define SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE_SHIFT (12U)
/*! POL_INV_N_ENABLE - Polarity Inverter N Enable
 *  0b0xxx..Disables at Decimator_n[3]
 *  0b1xxx..Enables at Decimator_n[3]
 *  0bx0xx..Disables at Decimator_n[2]
 *  0bx1xx..Enables at Decimator_n[2]
 *  0bxx0x..Disables at Decimator_n[1]
 *  0bxx1x..Enables at Decimator_n[1]
 *  0bxxx0..Disables at Decimator_n[0]
 *  0bxxx1..Enables at Decimator_n[0]
 */
#define SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE_SHIFT)) & SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE_MASK)

#define SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE_MASK (0xF000000U)
#define SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE_SHIFT (24U)
/*! DCFILTI_P_ENABLE - Decimation Filter Input P Enable
 *  0b0xxx..Disables at Decimator_p[3]
 *  0b1xxx..Enables at Decimator_p[3]
 *  0bx0xx..Disables at Decimator_p[2]
 *  0bx1xx..Enables at Decimator_p[2]
 *  0bxx0x..Disables at Decimator_p[1]
 *  0bxx1x..Enables at Decimator_p[1]
 *  0bxxx0..Disables at Decimator_p[0]
 *  0bxxx1..Enables at Decimator_p[0]
 */
#define SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE_SHIFT)) & SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE_MASK)

#define SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE_MASK (0xF0000000U)
#define SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE_SHIFT (28U)
/*! DCFILTI_N_ENABLE - Decimation Filter Input N Enable
 *  0b0xxx..Disables at Decimator_n[3]
 *  0b1xxx..Enables at Decimator_n[3]
 *  0bx0xx..Disables at Decimator_n[2]
 *  0bx1xx..Enables at Decimator_n[2]
 *  0bxx0x..Disables at Decimator_n[1]
 *  0bxx1x..Enables at Decimator_n[1]
 *  0bxxx0..Disables at Decimator_n[0]
 *  0bxxx1..Enables at Decimator_n[0]
 */
#define SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE_SHIFT)) & SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE_MASK)
/*! @} */

/*! @name DECIMATOR_CTL_1 - Decimator Control 1 */
/*! @{ */

#define SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P_MASK (0xF00U)
#define SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P_SHIFT (8U)
/*! FUNC_LOCAL_RST_AN_DEC_P - Functional Local Reset for Decimator P
 *  0b0xxx..Reset for Decimator_p[3]
 *  0b1xxx..Operational for Decimator_p[3]
 *  0bx0xx..Reset for Decimator_p[2]
 *  0bx1xx..Operational for Decimator_p2]
 *  0bxx0x..Reset for Decimator_p[1]
 *  0bxx1x..Operational for Decimator_p[1]
 *  0bxxx0..Reset for Decimator_p[0]
 *  0bxxx1..Operational for Decimator_p[0]
 */
#define SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P_SHIFT)) & SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P_MASK)

#define SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N_MASK (0xF000U)
#define SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N_SHIFT (12U)
/*! FUNC_LOCAL_RST_AN_DEC_N - Functional Local Reset for Decimator N
 *  0b0xxx..Reset for Decimator_n[3]
 *  0b1xxx..Operational for Decimator_n[3]
 *  0bx0xx..Reset for Decimator_n[2]
 *  0bx1xx..Operational for Decimator_n[2]
 *  0bxx0x..Reset for Decimator_n[1]
 *  0bxx1x..Operational for Decimator_n[1]
 *  0bxxx0..Reset for Decimator_n[0]
 *  0bxxx1..Operational for Decimator_n[0]
 */
#define SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N_SHIFT)) & SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N_MASK)
/*! @} */

/*! @name DECIMATOR_CTL_2 - Decimator Control 2 */
/*! @{ */

#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_0_MASK  (0xFFU)
#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_0_SHIFT (0U)
/*! VOL_CTRL_P_0 - Volume Control P 0 */
#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_0(x)    (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_0_SHIFT)) & SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_0_MASK)

#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_0_MASK  (0xFF00U)
#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_0_SHIFT (8U)
/*! VOL_CTRL_N_0 - Volume Control N 0 */
#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_0(x)    (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_0_SHIFT)) & SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_0_MASK)

#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_1_MASK  (0xFF0000U)
#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_1_SHIFT (16U)
/*! VOL_CTRL_P_1 - Volume Control P 1 */
#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_1(x)    (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_1_SHIFT)) & SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_1_MASK)

#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_1_MASK  (0xFF000000U)
#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_1_SHIFT (24U)
/*! VOL_CTRL_N_1 - Volume Control N 1 */
#define SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_1(x)    (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_1_SHIFT)) & SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_1_MASK)
/*! @} */

/*! @name DECIMATOR_CTL_3 - Decimator Control 3 */
/*! @{ */

#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_2_MASK  (0xFFU)
#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_2_SHIFT (0U)
/*! VOL_CTRL_P_2 - Volume Control P 2 */
#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_2(x)    (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_2_SHIFT)) & SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_2_MASK)

#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_2_MASK  (0xFF00U)
#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_2_SHIFT (8U)
/*! VOL_CTRL_N_2 - Volume Control N 2 */
#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_2(x)    (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_2_SHIFT)) & SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_2_MASK)

#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_3_MASK  (0xFF0000U)
#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_3_SHIFT (16U)
/*! VOL_CTRL_P_3 - Volume Control P 3 */
#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_3(x)    (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_3_SHIFT)) & SDADC_DECIMATOR_CTL_3_VOL_CTRL_P_3_MASK)

#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_3_MASK  (0xFF000000U)
#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_3_SHIFT (24U)
/*! VOL_CTRL_N_3 - Volume Control N 3 */
#define SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_3(x)    (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_3_SHIFT)) & SDADC_DECIMATOR_CTL_3_VOL_CTRL_N_3_MASK)
/*! @} */

/*! @name DECIMATOR_CTL_4 - Decimator Control 4 */
/*! @{ */

#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_0_MASK (0x3U)
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_0_SHIFT (0U)
/*! SET_SPEED_P_0 - Set Speed P 0
 *  0b00..48 kHz
 *  0b01..32 kHz
 *  0b11..48 kHz
 *  0b10..16 kHz
 */
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_0(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_4_SET_SPEED_P_0_SHIFT)) & SDADC_DECIMATOR_CTL_4_SET_SPEED_P_0_MASK)

#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_0_MASK (0xCU)
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_0_SHIFT (2U)
/*! SET_SPEED_N_0 - Set Speed N 0
 *  0b00..48 kHz
 *  0b01..32 kHz
 *  0b11..48 kHz
 *  0b10..16 kHz
 */
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_0(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_4_SET_SPEED_N_0_SHIFT)) & SDADC_DECIMATOR_CTL_4_SET_SPEED_N_0_MASK)

#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_1_MASK (0x30U)
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_1_SHIFT (4U)
/*! SET_SPEED_P_1 - Set Speed P 1
 *  0b00..48 kHz
 *  0b01..32 kHz
 *  0b11..48 kHz
 *  0b10..16 kHz
 */
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_1(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_4_SET_SPEED_P_1_SHIFT)) & SDADC_DECIMATOR_CTL_4_SET_SPEED_P_1_MASK)

#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_1_MASK (0xC0U)
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_1_SHIFT (6U)
/*! SET_SPEED_N_1 - Set Speed N 1
 *  0b00..48 kHz
 *  0b01..32 kHz
 *  0b11..48 kHz
 *  0b10..16 kHz
 */
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_1(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_4_SET_SPEED_N_1_SHIFT)) & SDADC_DECIMATOR_CTL_4_SET_SPEED_N_1_MASK)

#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_2_MASK (0x300U)
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_2_SHIFT (8U)
/*! SET_SPEED_P_2 - Set Speed P 2
 *  0b00..48 kHz
 *  0b01..32 kHz
 *  0b11..48 kHz
 *  0b10..16 kHz
 */
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_2(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_4_SET_SPEED_P_2_SHIFT)) & SDADC_DECIMATOR_CTL_4_SET_SPEED_P_2_MASK)

#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_2_MASK (0xC00U)
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_2_SHIFT (10U)
/*! SET_SPEED_N_2 - Set Speed N 2
 *  0b00..48 kHz
 *  0b01..32 kHz
 *  0b11..48 kHz
 *  0b10..16 kHz
 */
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_2(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_4_SET_SPEED_N_2_SHIFT)) & SDADC_DECIMATOR_CTL_4_SET_SPEED_N_2_MASK)

#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_3_MASK (0x3000U)
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_3_SHIFT (12U)
/*! SET_SPEED_P_3 - Set Speed P 3
 *  0b00..48 kHz
 *  0b01..32 kHz
 *  0b11..48 kHz
 *  0b10..16 kHz
 */
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_P_3(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_4_SET_SPEED_P_3_SHIFT)) & SDADC_DECIMATOR_CTL_4_SET_SPEED_P_3_MASK)

#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_3_MASK (0xC000U)
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_3_SHIFT (14U)
/*! SET_SPEED_N_3 - Set Speed N 3
 *  0b00..48 kHz
 *  0b01..32 kHz
 *  0b11..48 kHz
 *  0b10..16 kHz
 */
#define SDADC_DECIMATOR_CTL_4_SET_SPEED_N_3(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DECIMATOR_CTL_4_SET_SPEED_N_3_SHIFT)) & SDADC_DECIMATOR_CTL_4_SET_SPEED_N_3_MASK)
/*! @} */

/*! @name DC_LOOP_CTL_0 - DC Loop Control 0 */
/*! @{ */

#define SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE_MASK (0xFU)
#define SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE_SHIFT (0U)
/*! DCLOOP_P_ENABLE - DC Loop P Enable
 *  0b1xxx..Enables filter_p[3]
 *  0b0xxx..Disables filter_p[3]
 *  0bx1xx..Enables filter_p[2]
 *  0bx0xx..Disables filter_p[2]
 *  0bxx1x..Enables filter_p[1]
 *  0bxx0x..Disables filter_p[1]
 *  0bxxx1..Enables filter_p[0]
 *  0bxxx0..Disables filter_p[0]
 */
#define SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE_SHIFT)) & SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE_MASK)

#define SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE_MASK (0xF0U)
#define SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE_SHIFT (4U)
/*! DCLOOP_N_ENABLE - DC Loop N Enable
 *  0b1xxx..Enables filter_n[3]
 *  0b0xxx..Disables filter_n[3]
 *  0bx1xx..Enables filter_n[2]
 *  0bx0xx..Disables filter_n[2]
 *  0bxx1x..Enables filter_n[1]
 *  0bxx0x..Disables filter_n[1]
 *  0bxxx1..Enables filter_n[0]
 *  0bxxx0..Disables filter_n[0]
 */
#define SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE_SHIFT)) & SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE_MASK)
/*! @} */

/*! @name DC_LOOP_CTL_1 - DC Loop Control 1 */
/*! @{ */

#define SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P_MASK (0xFU)
#define SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P_SHIFT (0U)
/*! FUNC_LOCAL_RST_AN_DCLOOP_P - Functional Local Reset DCloop_p
 *  0b1xxx..Operational for ADCp[3]
 *  0b0xxx..Reset for ADCp[3]
 *  0bx1xx..Operational for ADCp[2]
 *  0bx0xx..Reset for ADCp[2]
 *  0bxx1x..Operational for ADCp[1]
 *  0bxx0x..Reset for ADCp[1]
 *  0bxxx1..Operational for ADCp[0]
 *  0bxxx0..Reset for ADCp[0]
 */
#define SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P_SHIFT)) & SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P_MASK)

#define SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N_MASK (0xF0U)
#define SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N_SHIFT (4U)
/*! FUNC_LOCAL_RST_AN_DCLOOP_N - Functional Local Reset DCloop_n
 *  0b1xxx..Operational for ADCn[3]
 *  0b0xxx..Reset for ADCn[3]
 *  0bx1xx..Operational for ADCn[2]
 *  0bx0xx..Reset for ADCn[2]
 *  0bxx1x..Operational for ADCn[1]
 *  0bxx0x..Reset for ADCn[1]
 *  0bxxx1..Operational for ADCn[0]
 *  0bxxx0..Reset for ADCn[0]
 */
#define SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N_SHIFT)) & SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N_MASK)
/*! @} */

/*! @name FIFO_WR_RD_CTL - FIFO Write Read Control */
/*! @{ */

#define SDADC_FIFO_WR_RD_CTL_WR_0_P_RST_MASK     (0x10000U)
#define SDADC_FIFO_WR_RD_CTL_WR_0_P_RST_SHIFT    (16U)
/*! WR_0_P_RST - Write Reset for FIFO_0_P */
#define SDADC_FIFO_WR_RD_CTL_WR_0_P_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_WR_0_P_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_WR_0_P_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_RD_0_P_RST_MASK     (0x20000U)
#define SDADC_FIFO_WR_RD_CTL_RD_0_P_RST_SHIFT    (17U)
/*! RD_0_P_RST - Read Reset for FIFO_0_P */
#define SDADC_FIFO_WR_RD_CTL_RD_0_P_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_RD_0_P_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_RD_0_P_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_WR_0_N_RST_MASK     (0x40000U)
#define SDADC_FIFO_WR_RD_CTL_WR_0_N_RST_SHIFT    (18U)
/*! WR_0_N_RST - Write Reset for FIFO_0_N */
#define SDADC_FIFO_WR_RD_CTL_WR_0_N_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_WR_0_N_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_WR_0_N_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_RD_0_N_RST_MASK     (0x80000U)
#define SDADC_FIFO_WR_RD_CTL_RD_0_N_RST_SHIFT    (19U)
/*! RD_0_N_RST - Read Reset for FIFO_0_N */
#define SDADC_FIFO_WR_RD_CTL_RD_0_N_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_RD_0_N_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_RD_0_N_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_WR_1_P_RST_MASK     (0x100000U)
#define SDADC_FIFO_WR_RD_CTL_WR_1_P_RST_SHIFT    (20U)
/*! WR_1_P_RST - Write Reset for FIFO_1_P */
#define SDADC_FIFO_WR_RD_CTL_WR_1_P_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_WR_1_P_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_WR_1_P_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_RD_1_P_RST_MASK     (0x200000U)
#define SDADC_FIFO_WR_RD_CTL_RD_1_P_RST_SHIFT    (21U)
/*! RD_1_P_RST - Read Reset for FIFO_1_P */
#define SDADC_FIFO_WR_RD_CTL_RD_1_P_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_RD_1_P_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_RD_1_P_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_WR_1_N_RST_MASK     (0x400000U)
#define SDADC_FIFO_WR_RD_CTL_WR_1_N_RST_SHIFT    (22U)
/*! WR_1_N_RST - Write Reset for FIFO_1_N */
#define SDADC_FIFO_WR_RD_CTL_WR_1_N_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_WR_1_N_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_WR_1_N_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_RD_1_N_RST_MASK     (0x800000U)
#define SDADC_FIFO_WR_RD_CTL_RD_1_N_RST_SHIFT    (23U)
/*! RD_1_N_RST - Read Reset for FIFO_1_N */
#define SDADC_FIFO_WR_RD_CTL_RD_1_N_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_RD_1_N_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_RD_1_N_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_WR_2_P_RST_MASK     (0x1000000U)
#define SDADC_FIFO_WR_RD_CTL_WR_2_P_RST_SHIFT    (24U)
/*! WR_2_P_RST - Write Reset for FIFO_2_P */
#define SDADC_FIFO_WR_RD_CTL_WR_2_P_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_WR_2_P_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_WR_2_P_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_RD_2_P_RST_MASK     (0x2000000U)
#define SDADC_FIFO_WR_RD_CTL_RD_2_P_RST_SHIFT    (25U)
/*! RD_2_P_RST - Read Reset for FIFO_2_P */
#define SDADC_FIFO_WR_RD_CTL_RD_2_P_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_RD_2_P_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_RD_2_P_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_WR_2_N_RST_MASK     (0x4000000U)
#define SDADC_FIFO_WR_RD_CTL_WR_2_N_RST_SHIFT    (26U)
/*! WR_2_N_RST - Write Reset for FIFO_2_N */
#define SDADC_FIFO_WR_RD_CTL_WR_2_N_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_WR_2_N_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_WR_2_N_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_RD_2_N_RST_MASK     (0x8000000U)
#define SDADC_FIFO_WR_RD_CTL_RD_2_N_RST_SHIFT    (27U)
/*! RD_2_N_RST - Read Reset for FIFO_2_N */
#define SDADC_FIFO_WR_RD_CTL_RD_2_N_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_RD_2_N_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_RD_2_N_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_WR_3_P_RST_MASK     (0x10000000U)
#define SDADC_FIFO_WR_RD_CTL_WR_3_P_RST_SHIFT    (28U)
/*! WR_3_P_RST - Write Reset for FIFO_3_P */
#define SDADC_FIFO_WR_RD_CTL_WR_3_P_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_WR_3_P_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_WR_3_P_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_RD_3_P_RST_MASK     (0x20000000U)
#define SDADC_FIFO_WR_RD_CTL_RD_3_P_RST_SHIFT    (29U)
/*! RD_3_P_RST - Read Reset for FIFO_3_P */
#define SDADC_FIFO_WR_RD_CTL_RD_3_P_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_RD_3_P_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_RD_3_P_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_WR_3_N_RST_MASK     (0x40000000U)
#define SDADC_FIFO_WR_RD_CTL_WR_3_N_RST_SHIFT    (30U)
/*! WR_3_N_RST - Write Reset for FIFO_3_N */
#define SDADC_FIFO_WR_RD_CTL_WR_3_N_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_WR_3_N_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_WR_3_N_RST_MASK)

#define SDADC_FIFO_WR_RD_CTL_RD_3_N_RST_MASK     (0x80000000U)
#define SDADC_FIFO_WR_RD_CTL_RD_3_N_RST_SHIFT    (31U)
/*! RD_3_N_RST - Read Reset for FIFO_3_N */
#define SDADC_FIFO_WR_RD_CTL_RD_3_N_RST(x)       (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WR_RD_CTL_RD_3_N_RST_SHIFT)) & SDADC_FIFO_WR_RD_CTL_RD_3_N_RST_MASK)
/*! @} */

/*! @name FIFO_WATERMARK_CTL - FIFO Watermark Control */
/*! @{ */

#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_P_MASK (0xFU)
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_P_SHIFT (0U)
/*! WATERMARK_0_P - Watermark for FIFO_0_P */
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_P_SHIFT)) & SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_P_MASK)

#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_N_MASK (0xF0U)
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_N_SHIFT (4U)
/*! WATERMARK_0_N - Watermark for FIFO_0_N */
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_N_SHIFT)) & SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_N_MASK)

#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_P_MASK (0xF00U)
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_P_SHIFT (8U)
/*! WATERMARK_1_P - Watermark for FIFO_1_P */
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_P_SHIFT)) & SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_P_MASK)

#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_N_MASK (0xF000U)
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_N_SHIFT (12U)
/*! WATERMARK_1_N - Watermark for FIFO_1_N */
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_N_SHIFT)) & SDADC_FIFO_WATERMARK_CTL_WATERMARK_1_N_MASK)

#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_P_MASK (0xF0000U)
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_P_SHIFT (16U)
/*! WATERMARK_2_P - Watermark for FIFO_2_P */
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_P_SHIFT)) & SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_P_MASK)

#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_N_MASK (0xF00000U)
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_N_SHIFT (20U)
/*! WATERMARK_2_N - Watermark for FIFO_2_N */
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_N_SHIFT)) & SDADC_FIFO_WATERMARK_CTL_WATERMARK_2_N_MASK)

#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_P_MASK (0xF000000U)
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_P_SHIFT (24U)
/*! WATERMARK_3_P - Watermark for FIFO_3_P */
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_P_SHIFT)) & SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_P_MASK)

#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_N_MASK (0xF0000000U)
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_N_SHIFT (28U)
/*! WATERMARK_3_N - Watermark for FIFO_3_N */
#define SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_N_SHIFT)) & SDADC_FIFO_WATERMARK_CTL_WATERMARK_3_N_MASK)
/*! @} */

/*! @name FIFO_WATERMARK_ERROR_CTL - FIFO Watermark Error Control */
/*! @{ */

#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_P_EN_MASK (0x1U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_P_EN_SHIFT (0U)
/*! WM_0_P_EN - Watermark Enable for FIFO_0_P
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_P_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_P_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_P_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_N_EN_MASK (0x2U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_N_EN_SHIFT (1U)
/*! WM_0_N_EN - Watermark Enable for FIFO_0_N
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_N_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_N_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_N_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_P_EN_MASK (0x4U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_P_EN_SHIFT (2U)
/*! WM_1_P_EN - Watermark Enable for FIFO_1_P
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_P_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_P_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_P_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_N_EN_MASK (0x8U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_N_EN_SHIFT (3U)
/*! WM_1_N_EN - Watermark Enable for FIFO_1_N
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_N_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_N_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_N_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_P_EN_MASK (0x10U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_P_EN_SHIFT (4U)
/*! WM_2_P_EN - Watermark Enable for FIFO_2_P
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_P_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_P_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_P_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_N_EN_MASK (0x20U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_N_EN_SHIFT (5U)
/*! WM_2_N_EN - Watermark Enable for FIFO_2_N
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_N_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_N_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_N_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_P_EN_MASK (0x40U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_P_EN_SHIFT (6U)
/*! WM_3_P_EN - Watermark Enable for FIFO_3_P
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_P_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_P_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_P_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_N_EN_MASK (0x80U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_N_EN_SHIFT (7U)
/*! WM_3_N_EN - Watermark Enable for FIFO_3_N
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_N_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_N_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_N_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_P_EN_MASK (0x100U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_P_EN_SHIFT (8U)
/*! ERR_0_P_EN - Interrupt Enable for FIFO_0_P
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_P_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_P_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_P_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_N_EN_MASK (0x200U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_N_EN_SHIFT (9U)
/*! ERR_0_N_EN - Interrupt Enable for FIFO_0_N
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_N_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_N_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_N_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_P_EN_MASK (0x400U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_P_EN_SHIFT (10U)
/*! ERR_1_P_EN - Interrupt Enable for FIFO_1_P
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_P_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_P_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_P_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_N_EN_MASK (0x800U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_N_EN_SHIFT (11U)
/*! ERR_1_N_EN - Interrupt Enable for FIFO_1_N
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_N_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_N_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_N_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_P_EN_MASK (0x1000U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_P_EN_SHIFT (12U)
/*! ERR_2_P_EN - Interrupt Enable for FIFO_2_P
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_P_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_P_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_P_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_N_EN_MASK (0x2000U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_N_EN_SHIFT (13U)
/*! ERR_2_N_EN - Interrupt Enable for FIFO_2_N
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_N_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_N_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_N_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_P_EN_MASK (0x4000U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_P_EN_SHIFT (14U)
/*! ERR_3_P_EN - Interrupt Enable for FIFO_3_P
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_P_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_P_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_P_EN_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_N_EN_MASK (0x8000U)
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_N_EN_SHIFT (15U)
/*! ERR_3_N_EN - Interrupt Enable for FIFO_3_N
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_N_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_N_EN_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_N_EN_MASK)
/*! @} */

/*! @name FIFO_WATERMARK_ERROR_ST - FIFO Watermark Error Status */
/*! @{ */

#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_P_ST_MASK (0x1U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_P_ST_SHIFT (0U)
/*! WM_0_P_ST - Watermark Status for FIFO_0_P
 *  0b1..Watermark error
 *  0b0..No watermark error
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_P_ST(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_P_ST_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_P_ST_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_N_ST_MASK (0x2U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_N_ST_SHIFT (1U)
/*! WM_0_N_ST - Watermark Status for FIFO_0_N
 *  0b1..Watermark error
 *  0b0..No watermark error
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_N_ST(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_N_ST_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_N_ST_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_P_ST_MASK (0x4U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_P_ST_SHIFT (2U)
/*! WM_1_P_ST - Watermark Status for FIFO_1_P.
 *  0b1..Watermark error
 *  0b0..No watermark error
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_P_ST(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_P_ST_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_P_ST_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_N_ST_MASK (0x8U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_N_ST_SHIFT (3U)
/*! WM_1_N_ST - Watermark Status for FIFO_1_N
 *  0b1..Watermark error
 *  0b0..No watermark error
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_N_ST(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_N_ST_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_N_ST_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_P_ST_MASK (0x10U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_P_ST_SHIFT (4U)
/*! WM_2_P_ST - Watermark Status for FIFO_2_P
 *  0b1..Watermark error
 *  0b0..No watermark error
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_P_ST(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_P_ST_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_P_ST_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_N_ST_MASK (0x20U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_N_ST_SHIFT (5U)
/*! WM_2_N_ST - Watermark Status for FIFO_2_N
 *  0b1..Watermark error
 *  0b0..No watermark error
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_N_ST(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_N_ST_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_N_ST_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_P_ST_MASK (0x40U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_P_ST_SHIFT (6U)
/*! WM_3_P_ST - Watermark Status for FIFO_3_P
 *  0b1..Watermark error
 *  0b0..No watermark error
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_P_ST(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_P_ST_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_P_ST_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_N_ST_MASK (0x80U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_N_ST_SHIFT (7U)
/*! WM_3_N_ST - Watermark Status for FIFO_3_N
 *  0b1..Watermark error
 *  0b0..No watermark error
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_N_ST(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_N_ST_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_N_ST_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_P_MASK (0x100U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_P_SHIFT (8U)
/*! ERR_0_P - Interrupt from FIFO_0_P
 *  0b1..Interrupt
 *  0b0..No interrupt
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_P_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_P_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_N_MASK (0x200U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_N_SHIFT (9U)
/*! ERR_0_N - Interrupt from FIFO_0_N
 *  0b1..Interrupt
 *  0b0..No interrupt
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_N_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_N_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_P_MASK (0x400U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_P_SHIFT (10U)
/*! ERR_1_P - Interrupt from FIFO_1_P
 *  0b1..Interrupt
 *  0b0..No interrupt
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_P_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_P_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_N_MASK (0x800U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_N_SHIFT (11U)
/*! ERR_1_N - Interrupt from FIFO_1_N
 *  0b1..Interrupt
 *  0b0..No interrupt
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_N_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_N_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_P_MASK (0x1000U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_P_SHIFT (12U)
/*! ERR_2_P - Interrupt from FIFO_2_P
 *  0b1..Interrupt
 *  0b0..No interrupt
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_P_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_P_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_N_MASK (0x2000U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_N_SHIFT (13U)
/*! ERR_2_N - Interrupt from FIFO_2_N
 *  0b1..Interrupt
 *  0b0..No interrupt
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_N_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_N_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_P_MASK (0x4000U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_P_SHIFT (14U)
/*! ERR_3_P - Interrupt from FIFO_3_P
 *  0b1..Interrupt
 *  0b0..No interrupt
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_P(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_P_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_P_MASK)

#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_N_MASK (0x8000U)
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_N_SHIFT (15U)
/*! ERR_3_N - Interrupt from FIFO_3_N
 *  0b1..Interrupt
 *  0b0..No interrupt
 */
#define SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_N(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_N_SHIFT)) & SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_N_MASK)
/*! @} */

/*! @name FIFO_0_P - FIFO 0 P */
/*! @{ */

#define SDADC_FIFO_0_P_FIFO_0_P_MASK             (0xFFFFFFU)
#define SDADC_FIFO_0_P_FIFO_0_P_SHIFT            (0U)
/*! FIFO_0_P - FIFO_0_P Output Data */
#define SDADC_FIFO_0_P_FIFO_0_P(x)               (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_0_P_FIFO_0_P_SHIFT)) & SDADC_FIFO_0_P_FIFO_0_P_MASK)
/*! @} */

/*! @name FIFO_0_N - FIFO 0 N */
/*! @{ */

#define SDADC_FIFO_0_N_FIFO_0_N_MASK             (0xFFFFFFU)
#define SDADC_FIFO_0_N_FIFO_0_N_SHIFT            (0U)
/*! FIFO_0_N - FIFO_0_N Output Data */
#define SDADC_FIFO_0_N_FIFO_0_N(x)               (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_0_N_FIFO_0_N_SHIFT)) & SDADC_FIFO_0_N_FIFO_0_N_MASK)
/*! @} */

/*! @name FIFO_1_P - FIFO 1 P */
/*! @{ */

#define SDADC_FIFO_1_P_FIFO_1_P_MASK             (0xFFFFFFU)
#define SDADC_FIFO_1_P_FIFO_1_P_SHIFT            (0U)
/*! FIFO_1_P - FIFO_1_P Output Data */
#define SDADC_FIFO_1_P_FIFO_1_P(x)               (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_1_P_FIFO_1_P_SHIFT)) & SDADC_FIFO_1_P_FIFO_1_P_MASK)
/*! @} */

/*! @name FIFO_1_N - FIFO 1 N */
/*! @{ */

#define SDADC_FIFO_1_N_FIFO_1_N_MASK             (0xFFFFFFU)
#define SDADC_FIFO_1_N_FIFO_1_N_SHIFT            (0U)
/*! FIFO_1_N - FIFO_1_N Output Data */
#define SDADC_FIFO_1_N_FIFO_1_N(x)               (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_1_N_FIFO_1_N_SHIFT)) & SDADC_FIFO_1_N_FIFO_1_N_MASK)
/*! @} */

/*! @name FIFO_2_P - FIFO 2 P */
/*! @{ */

#define SDADC_FIFO_2_P_FIFO_2_P_MASK             (0xFFFFFFU)
#define SDADC_FIFO_2_P_FIFO_2_P_SHIFT            (0U)
/*! FIFO_2_P - FIFO_2_P Output Data */
#define SDADC_FIFO_2_P_FIFO_2_P(x)               (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_2_P_FIFO_2_P_SHIFT)) & SDADC_FIFO_2_P_FIFO_2_P_MASK)
/*! @} */

/*! @name FIFO_2_N - FIFO 2 N */
/*! @{ */

#define SDADC_FIFO_2_N_FIFO_2_N_MASK             (0xFFFFFFU)
#define SDADC_FIFO_2_N_FIFO_2_N_SHIFT            (0U)
/*! FIFO_2_N - FIFO_2_N Output Data */
#define SDADC_FIFO_2_N_FIFO_2_N(x)               (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_2_N_FIFO_2_N_SHIFT)) & SDADC_FIFO_2_N_FIFO_2_N_MASK)
/*! @} */

/*! @name FIFO_3_P - FIFO 3 P */
/*! @{ */

#define SDADC_FIFO_3_P_FIFO_3_P_MASK             (0xFFFFFFU)
#define SDADC_FIFO_3_P_FIFO_3_P_SHIFT            (0U)
/*! FIFO_3_P - FIFO_3_P Output Data */
#define SDADC_FIFO_3_P_FIFO_3_P(x)               (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_3_P_FIFO_3_P_SHIFT)) & SDADC_FIFO_3_P_FIFO_3_P_MASK)
/*! @} */

/*! @name FIFO_3_N - FIFO 3 N */
/*! @{ */

#define SDADC_FIFO_3_N_FIFO_3_N_MASK             (0xFFFFFFU)
#define SDADC_FIFO_3_N_FIFO_3_N_SHIFT            (0U)
/*! FIFO_3_N - FIFO_3_N Output Data */
#define SDADC_FIFO_3_N_FIFO_3_N(x)               (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_3_N_FIFO_3_N_SHIFT)) & SDADC_FIFO_3_N_FIFO_3_N_MASK)
/*! @} */

/*! @name FIFO_ENTRIES_AVAIL_0 - FIFO Entries Availability 0 */
/*! @{ */

#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_P_AVAIL_MASK (0x1FU)
#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_P_AVAIL_SHIFT (0U)
/*! FIFO_0_P_AVAIL - Entries Available for FIFO_0_P */
#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_P_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_P_AVAIL_SHIFT)) & SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_P_AVAIL_MASK)

#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_N_AVAIL_MASK (0x1F00U)
#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_N_AVAIL_SHIFT (8U)
/*! FIFO_0_N_AVAIL - Entries Available for FIFO_0_N */
#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_N_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_N_AVAIL_SHIFT)) & SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_N_AVAIL_MASK)

#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_P_AVAIL_MASK (0x1F0000U)
#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_P_AVAIL_SHIFT (16U)
/*! FIFO_1_P_AVAIL - Entries Available for FIFO_1_P */
#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_P_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_P_AVAIL_SHIFT)) & SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_P_AVAIL_MASK)

#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_N_AVAIL_MASK (0x1F000000U)
#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_N_AVAIL_SHIFT (24U)
/*! FIFO_1_N_AVAIL - Entries Available for FIFO_1_N */
#define SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_N_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_N_AVAIL_SHIFT)) & SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_1_N_AVAIL_MASK)
/*! @} */

/*! @name FIFO_ENTRIES_AVAIL_1 - FIFO Entries Availability 1 */
/*! @{ */

#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_P_AVAIL_MASK (0x1FU)
#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_P_AVAIL_SHIFT (0U)
/*! FIFO_2_P_AVAIL - Entries Available for FIFO_2_P */
#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_P_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_P_AVAIL_SHIFT)) & SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_P_AVAIL_MASK)

#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_N_AVAIL_MASK (0x1F00U)
#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_N_AVAIL_SHIFT (8U)
/*! FIFO_2_N_AVAIL - Entries Available for FIFO_2_N */
#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_N_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_N_AVAIL_SHIFT)) & SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_2_N_AVAIL_MASK)

#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_P_AVAIL_MASK (0x1F0000U)
#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_P_AVAIL_SHIFT (16U)
/*! FIFO_3_P_AVAIL - Entries Available for FIFO_3_P */
#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_P_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_P_AVAIL_SHIFT)) & SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_P_AVAIL_MASK)

#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_N_AVAIL_MASK (0x1F000000U)
#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_N_AVAIL_SHIFT (24U)
/*! FIFO_3_N_AVAIL - Entries Available for FIFO_3_N */
#define SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_N_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_N_AVAIL_SHIFT)) & SDADC_FIFO_ENTRIES_AVAIL_1_FIFO_3_N_AVAIL_MASK)
/*! @} */

/*! @name FIFO_INTERRUPT - FIFO Interrupt */
/*! @{ */

#define SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_MASK (0x1U)
#define SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_SHIFT (0U)
/*! FIFO_INTERRUPT - FIFO Interrupt */
#define SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT(x)   (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_SHIFT)) & SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_MASK)

#define SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_EN_MASK (0x2U)
#define SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_EN_SHIFT (1U)
/*! FIFO_INTERRUPT_EN - FIFO Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_EN_SHIFT)) & SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SDADC_Register_Masks */


/* SDADC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SDADC base address */
  #define SDADC_BASE                               (0x5020D000u)
  /** Peripheral SDADC base address */
  #define SDADC_BASE_NS                            (0x4020D000u)
  /** Peripheral SDADC base pointer */
  #define SDADC                                    ((SDADC_Type *)SDADC_BASE)
  /** Peripheral SDADC base pointer */
  #define SDADC_NS                                 ((SDADC_Type *)SDADC_BASE_NS)
  /** Array initializer of SDADC peripheral base addresses */
  #define SDADC_BASE_ADDRS                         { SDADC_BASE }
  /** Array initializer of SDADC peripheral base pointers */
  #define SDADC_BASE_PTRS                          { SDADC }
  /** Array initializer of SDADC peripheral base addresses */
  #define SDADC_BASE_ADDRS_NS                      { SDADC_BASE_NS }
  /** Array initializer of SDADC peripheral base pointers */
  #define SDADC_BASE_PTRS_NS                       { SDADC_NS }
#else
  /** Peripheral SDADC base address */
  #define SDADC_BASE                               (0x4020D000u)
  /** Peripheral SDADC base pointer */
  #define SDADC                                    ((SDADC_Type *)SDADC_BASE)
  /** Array initializer of SDADC peripheral base addresses */
  #define SDADC_BASE_ADDRS                         { SDADC_BASE }
  /** Array initializer of SDADC peripheral base pointers */
  #define SDADC_BASE_PTRS                          { SDADC }
#endif

/*!
 * @}
 */ /* end of group SDADC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SEMA42 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
 * @{
 */

/** SEMA42 - Register Layout Typedef */
typedef struct {
  __IO uint8_t GATE3;                              /**< Gate, offset: 0x0 */
  __IO uint8_t GATE2;                              /**< Gate, offset: 0x1 */
  __IO uint8_t GATE1;                              /**< Gate, offset: 0x2 */
  __IO uint8_t GATE0;                              /**< Gate, offset: 0x3 */
  __IO uint8_t GATE7;                              /**< Gate, offset: 0x4 */
  __IO uint8_t GATE6;                              /**< Gate, offset: 0x5 */
  __IO uint8_t GATE5;                              /**< Gate, offset: 0x6 */
  __IO uint8_t GATE4;                              /**< Gate, offset: 0x7 */
  __IO uint8_t GATE11;                             /**< Gate, offset: 0x8 */
  __IO uint8_t GATE10;                             /**< Gate, offset: 0x9 */
  __IO uint8_t GATE9;                              /**< Gate, offset: 0xA */
  __IO uint8_t GATE8;                              /**< Gate, offset: 0xB */
  __IO uint8_t GATE15;                             /**< Gate, offset: 0xC */
  __IO uint8_t GATE14;                             /**< Gate, offset: 0xD */
  __IO uint8_t GATE13;                             /**< Gate, offset: 0xE */
  __IO uint8_t GATE12;                             /**< Gate, offset: 0xF */
  __IO uint8_t GATE19;                             /**< Gate, offset: 0x10 */
  __IO uint8_t GATE18;                             /**< Gate, offset: 0x11 */
  __IO uint8_t GATE17;                             /**< Gate, offset: 0x12 */
  __IO uint8_t GATE16;                             /**< Gate, offset: 0x13 */
  __IO uint8_t GATE23;                             /**< Gate, offset: 0x14 */
  __IO uint8_t GATE22;                             /**< Gate, offset: 0x15 */
  __IO uint8_t GATE21;                             /**< Gate, offset: 0x16 */
  __IO uint8_t GATE20;                             /**< Gate, offset: 0x17 */
  __IO uint8_t GATE27;                             /**< Gate, offset: 0x18 */
  __IO uint8_t GATE26;                             /**< Gate, offset: 0x19 */
  __IO uint8_t GATE25;                             /**< Gate, offset: 0x1A */
  __IO uint8_t GATE24;                             /**< Gate, offset: 0x1B */
  __IO uint8_t GATE31;                             /**< Gate, offset: 0x1C */
  __IO uint8_t GATE30;                             /**< Gate, offset: 0x1D */
  __IO uint8_t GATE29;                             /**< Gate, offset: 0x1E */
  __IO uint8_t GATE28;                             /**< Gate, offset: 0x1F */
  __IO uint8_t GATE35;                             /**< Gate, offset: 0x20 */
  __IO uint8_t GATE34;                             /**< Gate, offset: 0x21 */
  __IO uint8_t GATE33;                             /**< Gate, offset: 0x22 */
  __IO uint8_t GATE32;                             /**< Gate, offset: 0x23 */
  __IO uint8_t GATE39;                             /**< Gate, offset: 0x24 */
  __IO uint8_t GATE38;                             /**< Gate, offset: 0x25 */
  __IO uint8_t GATE37;                             /**< Gate, offset: 0x26 */
  __IO uint8_t GATE36;                             /**< Gate, offset: 0x27 */
  __IO uint8_t GATE43;                             /**< Gate, offset: 0x28 */
  __IO uint8_t GATE42;                             /**< Gate, offset: 0x29 */
  __IO uint8_t GATE41;                             /**< Gate, offset: 0x2A */
  __IO uint8_t GATE40;                             /**< Gate, offset: 0x2B */
  __IO uint8_t GATE47;                             /**< Gate, offset: 0x2C */
  __IO uint8_t GATE46;                             /**< Gate, offset: 0x2D */
  __IO uint8_t GATE45;                             /**< Gate, offset: 0x2E */
  __IO uint8_t GATE44;                             /**< Gate, offset: 0x2F */
  __IO uint8_t GATE51;                             /**< Gate, offset: 0x30 */
  __IO uint8_t GATE50;                             /**< Gate, offset: 0x31 */
  __IO uint8_t GATE49;                             /**< Gate, offset: 0x32 */
  __IO uint8_t GATE48;                             /**< Gate, offset: 0x33 */
  __IO uint8_t GATE55;                             /**< Gate, offset: 0x34 */
  __IO uint8_t GATE54;                             /**< Gate, offset: 0x35 */
  __IO uint8_t GATE53;                             /**< Gate, offset: 0x36 */
  __IO uint8_t GATE52;                             /**< Gate, offset: 0x37 */
  __IO uint8_t GATE59;                             /**< Gate, offset: 0x38 */
  __IO uint8_t GATE58;                             /**< Gate, offset: 0x39 */
  __IO uint8_t GATE57;                             /**< Gate, offset: 0x3A */
  __IO uint8_t GATE56;                             /**< Gate, offset: 0x3B */
  __IO uint8_t GATE63;                             /**< Gate, offset: 0x3C */
  __IO uint8_t GATE62;                             /**< Gate, offset: 0x3D */
  __IO uint8_t GATE61;                             /**< Gate, offset: 0x3E */
  __IO uint8_t GATE60;                             /**< Gate, offset: 0x3F */
       uint8_t RESERVED_0[2];
  union {                                          /* offset: 0x42 */
    __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
    __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
  };
} SEMA42_Type;

/* ----------------------------------------------------------------------------
   -- SEMA42 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
 * @{
 */

/*! @name GATE3 - Gate */
/*! @{ */

#define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
/*! @} */

/*! @name GATE2 - Gate */
/*! @{ */

#define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
/*! @} */

/*! @name GATE1 - Gate */
/*! @{ */

#define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
/*! @} */

/*! @name GATE0 - Gate */
/*! @{ */

#define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
/*! @} */

/*! @name GATE7 - Gate */
/*! @{ */

#define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
/*! @} */

/*! @name GATE6 - Gate */
/*! @{ */

#define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
/*! @} */

/*! @name GATE5 - Gate */
/*! @{ */

#define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
/*! @} */

/*! @name GATE4 - Gate */
/*! @{ */

#define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
/*! @} */

/*! @name GATE11 - Gate */
/*! @{ */

#define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE11_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
/*! @} */

/*! @name GATE10 - Gate */
/*! @{ */

#define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE10_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
/*! @} */

/*! @name GATE9 - Gate */
/*! @{ */

#define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
/*! @} */

/*! @name GATE8 - Gate */
/*! @{ */

#define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
/*! @} */

/*! @name GATE15 - Gate */
/*! @{ */

#define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE15_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
/*! @} */

/*! @name GATE14 - Gate */
/*! @{ */

#define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE14_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
/*! @} */

/*! @name GATE13 - Gate */
/*! @{ */

#define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE13_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
/*! @} */

/*! @name GATE12 - Gate */
/*! @{ */

#define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE12_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
/*! @} */

/*! @name GATE19 - Gate */
/*! @{ */

#define SEMA42_GATE19_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE19_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE19_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE19_GTFSM_SHIFT)) & SEMA42_GATE19_GTFSM_MASK)
/*! @} */

/*! @name GATE18 - Gate */
/*! @{ */

#define SEMA42_GATE18_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE18_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE18_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE18_GTFSM_SHIFT)) & SEMA42_GATE18_GTFSM_MASK)
/*! @} */

/*! @name GATE17 - Gate */
/*! @{ */

#define SEMA42_GATE17_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE17_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE17_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE17_GTFSM_SHIFT)) & SEMA42_GATE17_GTFSM_MASK)
/*! @} */

/*! @name GATE16 - Gate */
/*! @{ */

#define SEMA42_GATE16_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE16_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE16_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE16_GTFSM_SHIFT)) & SEMA42_GATE16_GTFSM_MASK)
/*! @} */

/*! @name GATE23 - Gate */
/*! @{ */

#define SEMA42_GATE23_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE23_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE23_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE23_GTFSM_SHIFT)) & SEMA42_GATE23_GTFSM_MASK)
/*! @} */

/*! @name GATE22 - Gate */
/*! @{ */

#define SEMA42_GATE22_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE22_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE22_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE22_GTFSM_SHIFT)) & SEMA42_GATE22_GTFSM_MASK)
/*! @} */

/*! @name GATE21 - Gate */
/*! @{ */

#define SEMA42_GATE21_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE21_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE21_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE21_GTFSM_SHIFT)) & SEMA42_GATE21_GTFSM_MASK)
/*! @} */

/*! @name GATE20 - Gate */
/*! @{ */

#define SEMA42_GATE20_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE20_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE20_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE20_GTFSM_SHIFT)) & SEMA42_GATE20_GTFSM_MASK)
/*! @} */

/*! @name GATE27 - Gate */
/*! @{ */

#define SEMA42_GATE27_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE27_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE27_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE27_GTFSM_SHIFT)) & SEMA42_GATE27_GTFSM_MASK)
/*! @} */

/*! @name GATE26 - Gate */
/*! @{ */

#define SEMA42_GATE26_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE26_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE26_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE26_GTFSM_SHIFT)) & SEMA42_GATE26_GTFSM_MASK)
/*! @} */

/*! @name GATE25 - Gate */
/*! @{ */

#define SEMA42_GATE25_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE25_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE25_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE25_GTFSM_SHIFT)) & SEMA42_GATE25_GTFSM_MASK)
/*! @} */

/*! @name GATE24 - Gate */
/*! @{ */

#define SEMA42_GATE24_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE24_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE24_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE24_GTFSM_SHIFT)) & SEMA42_GATE24_GTFSM_MASK)
/*! @} */

/*! @name GATE31 - Gate */
/*! @{ */

#define SEMA42_GATE31_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE31_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE31_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE31_GTFSM_SHIFT)) & SEMA42_GATE31_GTFSM_MASK)
/*! @} */

/*! @name GATE30 - Gate */
/*! @{ */

#define SEMA42_GATE30_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE30_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE30_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE30_GTFSM_SHIFT)) & SEMA42_GATE30_GTFSM_MASK)
/*! @} */

/*! @name GATE29 - Gate */
/*! @{ */

#define SEMA42_GATE29_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE29_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE29_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE29_GTFSM_SHIFT)) & SEMA42_GATE29_GTFSM_MASK)
/*! @} */

/*! @name GATE28 - Gate */
/*! @{ */

#define SEMA42_GATE28_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE28_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE28_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE28_GTFSM_SHIFT)) & SEMA42_GATE28_GTFSM_MASK)
/*! @} */

/*! @name GATE35 - Gate */
/*! @{ */

#define SEMA42_GATE35_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE35_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE35_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE35_GTFSM_SHIFT)) & SEMA42_GATE35_GTFSM_MASK)
/*! @} */

/*! @name GATE34 - Gate */
/*! @{ */

#define SEMA42_GATE34_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE34_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE34_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE34_GTFSM_SHIFT)) & SEMA42_GATE34_GTFSM_MASK)
/*! @} */

/*! @name GATE33 - Gate */
/*! @{ */

#define SEMA42_GATE33_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE33_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE33_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE33_GTFSM_SHIFT)) & SEMA42_GATE33_GTFSM_MASK)
/*! @} */

/*! @name GATE32 - Gate */
/*! @{ */

#define SEMA42_GATE32_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE32_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE32_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE32_GTFSM_SHIFT)) & SEMA42_GATE32_GTFSM_MASK)
/*! @} */

/*! @name GATE39 - Gate */
/*! @{ */

#define SEMA42_GATE39_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE39_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE39_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE39_GTFSM_SHIFT)) & SEMA42_GATE39_GTFSM_MASK)
/*! @} */

/*! @name GATE38 - Gate */
/*! @{ */

#define SEMA42_GATE38_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE38_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE38_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE38_GTFSM_SHIFT)) & SEMA42_GATE38_GTFSM_MASK)
/*! @} */

/*! @name GATE37 - Gate */
/*! @{ */

#define SEMA42_GATE37_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE37_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE37_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE37_GTFSM_SHIFT)) & SEMA42_GATE37_GTFSM_MASK)
/*! @} */

/*! @name GATE36 - Gate */
/*! @{ */

#define SEMA42_GATE36_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE36_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE36_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE36_GTFSM_SHIFT)) & SEMA42_GATE36_GTFSM_MASK)
/*! @} */

/*! @name GATE43 - Gate */
/*! @{ */

#define SEMA42_GATE43_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE43_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE43_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE43_GTFSM_SHIFT)) & SEMA42_GATE43_GTFSM_MASK)
/*! @} */

/*! @name GATE42 - Gate */
/*! @{ */

#define SEMA42_GATE42_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE42_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE42_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE42_GTFSM_SHIFT)) & SEMA42_GATE42_GTFSM_MASK)
/*! @} */

/*! @name GATE41 - Gate */
/*! @{ */

#define SEMA42_GATE41_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE41_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE41_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE41_GTFSM_SHIFT)) & SEMA42_GATE41_GTFSM_MASK)
/*! @} */

/*! @name GATE40 - Gate */
/*! @{ */

#define SEMA42_GATE40_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE40_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE40_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE40_GTFSM_SHIFT)) & SEMA42_GATE40_GTFSM_MASK)
/*! @} */

/*! @name GATE47 - Gate */
/*! @{ */

#define SEMA42_GATE47_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE47_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE47_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE47_GTFSM_SHIFT)) & SEMA42_GATE47_GTFSM_MASK)
/*! @} */

/*! @name GATE46 - Gate */
/*! @{ */

#define SEMA42_GATE46_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE46_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE46_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE46_GTFSM_SHIFT)) & SEMA42_GATE46_GTFSM_MASK)
/*! @} */

/*! @name GATE45 - Gate */
/*! @{ */

#define SEMA42_GATE45_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE45_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE45_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE45_GTFSM_SHIFT)) & SEMA42_GATE45_GTFSM_MASK)
/*! @} */

/*! @name GATE44 - Gate */
/*! @{ */

#define SEMA42_GATE44_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE44_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE44_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE44_GTFSM_SHIFT)) & SEMA42_GATE44_GTFSM_MASK)
/*! @} */

/*! @name GATE51 - Gate */
/*! @{ */

#define SEMA42_GATE51_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE51_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE51_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE51_GTFSM_SHIFT)) & SEMA42_GATE51_GTFSM_MASK)
/*! @} */

/*! @name GATE50 - Gate */
/*! @{ */

#define SEMA42_GATE50_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE50_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE50_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE50_GTFSM_SHIFT)) & SEMA42_GATE50_GTFSM_MASK)
/*! @} */

/*! @name GATE49 - Gate */
/*! @{ */

#define SEMA42_GATE49_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE49_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE49_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE49_GTFSM_SHIFT)) & SEMA42_GATE49_GTFSM_MASK)
/*! @} */

/*! @name GATE48 - Gate */
/*! @{ */

#define SEMA42_GATE48_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE48_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE48_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE48_GTFSM_SHIFT)) & SEMA42_GATE48_GTFSM_MASK)
/*! @} */

/*! @name GATE55 - Gate */
/*! @{ */

#define SEMA42_GATE55_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE55_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE55_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE55_GTFSM_SHIFT)) & SEMA42_GATE55_GTFSM_MASK)
/*! @} */

/*! @name GATE54 - Gate */
/*! @{ */

#define SEMA42_GATE54_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE54_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE54_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE54_GTFSM_SHIFT)) & SEMA42_GATE54_GTFSM_MASK)
/*! @} */

/*! @name GATE53 - Gate */
/*! @{ */

#define SEMA42_GATE53_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE53_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE53_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE53_GTFSM_SHIFT)) & SEMA42_GATE53_GTFSM_MASK)
/*! @} */

/*! @name GATE52 - Gate */
/*! @{ */

#define SEMA42_GATE52_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE52_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE52_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE52_GTFSM_SHIFT)) & SEMA42_GATE52_GTFSM_MASK)
/*! @} */

/*! @name GATE59 - Gate */
/*! @{ */

#define SEMA42_GATE59_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE59_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE59_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE59_GTFSM_SHIFT)) & SEMA42_GATE59_GTFSM_MASK)
/*! @} */

/*! @name GATE58 - Gate */
/*! @{ */

#define SEMA42_GATE58_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE58_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE58_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE58_GTFSM_SHIFT)) & SEMA42_GATE58_GTFSM_MASK)
/*! @} */

/*! @name GATE57 - Gate */
/*! @{ */

#define SEMA42_GATE57_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE57_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE57_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE57_GTFSM_SHIFT)) & SEMA42_GATE57_GTFSM_MASK)
/*! @} */

/*! @name GATE56 - Gate */
/*! @{ */

#define SEMA42_GATE56_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE56_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE56_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE56_GTFSM_SHIFT)) & SEMA42_GATE56_GTFSM_MASK)
/*! @} */

/*! @name GATE63 - Gate */
/*! @{ */

#define SEMA42_GATE63_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE63_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE63_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE63_GTFSM_SHIFT)) & SEMA42_GATE63_GTFSM_MASK)
/*! @} */

/*! @name GATE62 - Gate */
/*! @{ */

#define SEMA42_GATE62_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE62_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE62_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE62_GTFSM_SHIFT)) & SEMA42_GATE62_GTFSM_MASK)
/*! @} */

/*! @name GATE61 - Gate */
/*! @{ */

#define SEMA42_GATE61_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE61_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE61_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE61_GTFSM_SHIFT)) & SEMA42_GATE61_GTFSM_MASK)
/*! @} */

/*! @name GATE60 - Gate */
/*! @{ */

#define SEMA42_GATE60_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE60_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE60_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE60_GTFSM_SHIFT)) & SEMA42_GATE60_GTFSM_MASK)
/*! @} */

/*! @name RSTGT_R - Reset Gate Read */
/*! @{ */

#define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
/*! RSTGTN - Reset Gate Number */
#define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)

#define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
#define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
/*! RSTGMS - Reset Gate Domain */
#define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)

#define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
#define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
/*! RSTGSM - Reset Gate Finite State Machine
 *  0b00..Idle, waiting for the first data pattern write.
 *  0b01..Waiting for the second data pattern write
 *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
 *        this machine returns to the idle (waiting for first data pattern write) state.
 *  0b11..This state encoding is never used and therefore reserved.
 */
#define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
/*! @} */

/*! @name RSTGT_W - Reset Gate Write */
/*! @{ */

#define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
/*! RSTGTN - Reset Gate Number */
#define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)

#define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
#define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
/*! RSTGDP - Reset Gate Data Pattern */
#define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SEMA42_Register_Masks */


/* SEMA42 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SEMA42_0 base address */
  #define SEMA42_0_BASE                            (0x50206000u)
  /** Peripheral SEMA42_0 base address */
  #define SEMA42_0_BASE_NS                         (0x40206000u)
  /** Peripheral SEMA42_0 base pointer */
  #define SEMA42_0                                 ((SEMA42_Type *)SEMA42_0_BASE)
  /** Peripheral SEMA42_0 base pointer */
  #define SEMA42_0_NS                              ((SEMA42_Type *)SEMA42_0_BASE_NS)
  /** Peripheral SEMA42_4 base address */
  #define SEMA42_4_BASE                            (0x5018A000u)
  /** Peripheral SEMA42_4 base address */
  #define SEMA42_4_BASE_NS                         (0x4018A000u)
  /** Peripheral SEMA42_4 base pointer */
  #define SEMA42_4                                 ((SEMA42_Type *)SEMA42_4_BASE)
  /** Peripheral SEMA42_4 base pointer */
  #define SEMA42_4_NS                              ((SEMA42_Type *)SEMA42_4_BASE_NS)
  /** Array initializer of SEMA42 peripheral base addresses */
  #define SEMA42_BASE_ADDRS                        { SEMA42_0_BASE, 0u, 0u, 0u, SEMA42_4_BASE }
  /** Array initializer of SEMA42 peripheral base pointers */
  #define SEMA42_BASE_PTRS                         { SEMA42_0, (SEMA42_Type *)0u, (SEMA42_Type *)0u, (SEMA42_Type *)0u, SEMA42_4 }
  /** Array initializer of SEMA42 peripheral base addresses */
  #define SEMA42_BASE_ADDRS_NS                     { SEMA42_0_BASE_NS, 0u, 0u, 0u, SEMA42_4_BASE_NS }
  /** Array initializer of SEMA42 peripheral base pointers */
  #define SEMA42_BASE_PTRS_NS                      { SEMA42_0_NS, (SEMA42_Type *)0u, (SEMA42_Type *)0u, (SEMA42_Type *)0u, SEMA42_4_NS }
#else
  /** Peripheral SEMA42_0 base address */
  #define SEMA42_0_BASE                            (0x40206000u)
  /** Peripheral SEMA42_0 base pointer */
  #define SEMA42_0                                 ((SEMA42_Type *)SEMA42_0_BASE)
  /** Peripheral SEMA42_4 base address */
  #define SEMA42_4_BASE                            (0x4018A000u)
  /** Peripheral SEMA42_4 base pointer */
  #define SEMA42_4                                 ((SEMA42_Type *)SEMA42_4_BASE)
  /** Array initializer of SEMA42 peripheral base addresses */
  #define SEMA42_BASE_ADDRS                        { SEMA42_0_BASE, 0u, 0u, 0u, SEMA42_4_BASE }
  /** Array initializer of SEMA42 peripheral base pointers */
  #define SEMA42_BASE_PTRS                         { SEMA42_0, (SEMA42_Type *)0u, (SEMA42_Type *)0u, (SEMA42_Type *)0u, SEMA42_4 }
#endif

/*!
 * @}
 */ /* end of group SEMA42_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SLEEPCON0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SLEEPCON0_Peripheral_Access_Layer SLEEPCON0 Peripheral Access Layer
 * @{
 */

/** SLEEPCON0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t SLEEPCFG;                          /**< Sleep Configuration, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t RUNCFG;                            /**< Run Configuration, offset: 0x10 */
       uint8_t RESERVED_1[12];
  __O  uint32_t RUNCFG_SET;                        /**< RUNCFG Set, offset: 0x20 */
       uint8_t RESERVED_2[12];
  __O  uint32_t RUNCFG_CLR;                        /**< RUNCFG Clear, offset: 0x30 */
       uint8_t RESERVED_3[44];
  __IO uint32_t WAKEUPEN0;                         /**< Wakeup Enable 0, offset: 0x60 */
  __IO uint32_t WAKEUPEN1;                         /**< Wakeup Enable 1, offset: 0x64 */
  __IO uint32_t WAKEUPEN2;                         /**< Wakeup Enable 2, offset: 0x68 */
  __IO uint32_t WAKEUPEN3;                         /**< Wakeup Enable 3, offset: 0x6C */
  __IO uint32_t WAKEUPEN4;                         /**< Wakeup Enable 4, offset: 0x70 */
       uint8_t RESERVED_4[44];
  __IO uint32_t WAKEUPEN0_SET;                     /**< Wakeup Enable 0 Set, offset: 0xA0 */
  __IO uint32_t WAKEUPEN1_SET;                     /**< Wakeup Enable 1 Set, offset: 0xA4 */
  __IO uint32_t WAKEUPEN2_SET;                     /**< Wakeup Enable 2 Set, offset: 0xA8 */
  __IO uint32_t WAKEUPEN3_SET;                     /**< Wakeup Enable 3 Set, offset: 0xAC */
  __IO uint32_t WAKEUPEN4_SET;                     /**< Wakeup Enable 4 Set, offset: 0xB0 */
       uint8_t RESERVED_5[76];
  __IO uint32_t WAKEUPEN0_CLR;                     /**< Wakeup Enable 0 Clear, offset: 0x100 */
  __IO uint32_t WAKEUPEN1_CLR;                     /**< Wakeup Enable 1 Clear, offset: 0x104 */
  __IO uint32_t WAKEUPEN2_CLR;                     /**< Wakeup Enable 2 Clear, offset: 0x108 */
  __IO uint32_t WAKEUPEN3_CLR;                     /**< Wakeup Enable 3 Clear, offset: 0x10C */
  __IO uint32_t WAKEUPEN4_CLR;                     /**< Wakeup Enable 4 Clear, offset: 0x110 */
       uint8_t RESERVED_6[80];
  __IO uint32_t PWRDOWN_WAIT;                      /**< Power Down Wait, offset: 0x164 */
       uint8_t RESERVED_7[40];
  __IO uint32_t HW_WAKE;                           /**< eDMA Wakeup Enable, offset: 0x190 */
  __O  uint32_t HW_WAKE_SET;                       /**< eDMA Wakeup Set, offset: 0x194 */
  __O  uint32_t HW_WAKE_CLR;                       /**< eDMA Wakeup Clear, offset: 0x198 */
       uint8_t RESERVED_8[4];
  __IO uint32_t SHARED_MASK0;                      /**< Shared Resources Mask, offset: 0x1A0 */
  __O  uint32_t SHARED_MASK0_SET;                  /**< Shared Resources Mask Set, offset: 0x1A4 */
  __O  uint32_t SHARED_MASK0_CLR;                  /**< Shared Resources Mask Clear, offset: 0x1A8 */
       uint8_t RESERVED_9[4];
  __IO uint32_t SHA_MED_CCTRL0;                    /**< Media Domain Shared Controller Low-power Control, offset: 0x1B0 */
  __IO uint32_t SHA_MED_TCTRL0;                    /**< Media Domain Shared Resources Target Low-power Control, offset: 0x1B4 */
       uint8_t RESERVED_10[4];
  __IO uint32_t SHA_SEN_TCTRL0;                    /**< Shared VDD1_SENSE Domain Targets Low-power Control, offset: 0x1BC */
  __IO uint32_t PRIVATE_CCTRL0;                    /**< Private Resources Controllers Low-power Control 0, offset: 0x1C0 */
  __IO uint32_t PRIVATE_TCTRL0;                    /**< Private Resources Targets Low-power Control 0, offset: 0x1C4 */
  __IO uint32_t PRIVATE_TCTRL1;                    /**< Private Resources Targets Low-power Control 1, offset: 0x1C8 */
  __IO uint32_t PRIVATE_TCTRL2;                    /**< Private Resources Targets Low-power Control 2, offset: 0x1CC */
  __I  uint32_t SHA_MED_CSTAT0;                    /**< Media Domain Shared Controllers Low-power Status, offset: 0x1D0 */
  __I  uint32_t SHA_MEDSEN_TSTAT0;                 /**< Media and Sense Domain Shared Targets Low-power Status, offset: 0x1D4 */
       uint8_t RESERVED_11[8];
  __I  uint32_t PRIVATE_CSTAT0;                    /**< Private Resources Controller Low-power Status, offset: 0x1E0 */
  __I  uint32_t PRIVATE_TSTAT0;                    /**< Private Resources Targets Low-power Status 0, offset: 0x1E4 */
  __I  uint32_t PRIVATE_TSTAT1;                    /**< Private Resources Targets Low-power Status 1, offset: 0x1E8 */
  __I  uint32_t LP_HINT0;                          /**< Low-Power Hints 0, offset: 0x1EC */
  __I  uint32_t LP_HINT1;                          /**< Low-Power Hints 1, offset: 0x1F0 */
  __I  uint32_t LP_DENY0;                          /**< Low-Power Request Deny Status 0, offset: 0x1F4 */
} SLEEPCON0_Type;

/* ----------------------------------------------------------------------------
   -- SLEEPCON0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SLEEPCON0_Register_Masks SLEEPCON0 Register Masks
 * @{
 */

/*! @name SLEEPCFG - Sleep Configuration */
/*! @{ */

#define SLEEPCON0_SLEEPCFG_COMP_MAINCLK_SHUTOFF_MASK (0x1U)
#define SLEEPCON0_SLEEPCFG_COMP_MAINCLK_SHUTOFF_SHIFT (0U)
/*! COMP_MAINCLK_SHUTOFF - VDD2_COMP Domain compute_main_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_SLEEPCFG_COMP_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_COMP_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_COMP_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_SLEEPCFG_SENSEP_MAINCLK_SHUTOFF_MASK (0x2U)
#define SLEEPCON0_SLEEPCFG_SENSEP_MAINCLK_SHUTOFF_SHIFT (1U)
/*! SENSEP_MAINCLK_SHUTOFF - VDD1_SENSE Domain sense_main_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_SLEEPCFG_SENSEP_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_SENSEP_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_SENSEP_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_SLEEPCFG_SENSES_MAINCLK_SHUTOFF_MASK (0x4U)
#define SLEEPCON0_SLEEPCFG_SENSES_MAINCLK_SHUTOFF_SHIFT (2U)
/*! SENSES_MAINCLK_SHUTOFF - VDD1_SENSE Domain sense_main_clk_1 Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_SLEEPCFG_SENSES_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_SENSES_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_SENSES_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK (0x8U)
#define SLEEPCON0_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT (3U)
/*! RAM0_CLK_SHUTOFF - RAM_ARBITER0 common_ram_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_SLEEPCFG_RAM0_CLK_SHUTOFF(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM0_CLK_SHUTOFF_MASK)

#define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK (0x10U)
#define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT (4U)
/*! RAM1_CLK_SHUTOFF - RAM_ARBITER1 sense_ram_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_RAM1_CLK_SHUTOFF_MASK)

#define SLEEPCON0_SLEEPCFG_COMN_MAINCLK_SHUTOFF_MASK (0x20U)
#define SLEEPCON0_SLEEPCFG_COMN_MAINCLK_SHUTOFF_SHIFT (5U)
/*! COMN_MAINCLK_SHUTOFF - VDDN_COM Domain common_vddn_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_SLEEPCFG_COMN_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_COMN_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_COMN_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_SLEEPCFG_MEDIA_MAINCLK_SHUTOFF_MASK (0x40U)
#define SLEEPCON0_SLEEPCFG_MEDIA_MAINCLK_SHUTOFF_SHIFT (6U)
/*! MEDIA_MAINCLK_SHUTOFF - VDD2_MEDIA and VDDN_MEDIA Domains media_main_clk and media_vddn_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_SLEEPCFG_MEDIA_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_MEDIA_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_SLEEPCFG_MEDIA_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_SLEEPCFG_XTAL_PD_MASK          (0x80U)
#define SLEEPCON0_SLEEPCFG_XTAL_PD_SHIFT         (7U)
/*! XTAL_PD - Xtal Oscillator Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_XTAL_PD(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_XTAL_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_XTAL_PD_MASK)

#define SLEEPCON0_SLEEPCFG_FRO0_PD_MASK          (0x100U)
#define SLEEPCON0_SLEEPCFG_FRO0_PD_SHIFT         (8U)
/*! FRO0_PD - FRO0 Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_FRO0_PD(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_FRO0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_FRO0_PD_MASK)

#define SLEEPCON0_SLEEPCFG_FRO1_PD_MASK          (0x200U)
#define SLEEPCON0_SLEEPCFG_FRO1_PD_SHIFT         (9U)
/*! FRO1_PD - FRO1 Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_FRO1_PD(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_FRO1_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_FRO1_PD_MASK)

#define SLEEPCON0_SLEEPCFG_FRO2_PD_MASK          (0x400U)
#define SLEEPCON0_SLEEPCFG_FRO2_PD_SHIFT         (10U)
/*! FRO2_PD - FRO2 Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_FRO2_PD(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_FRO2_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_FRO2_PD_MASK)

#define SLEEPCON0_SLEEPCFG_LPOSC_PD_MASK         (0x800U)
#define SLEEPCON0_SLEEPCFG_LPOSC_PD_SHIFT        (11U)
/*! LPOSC_PD - LPOSC Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_LPOSC_PD(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_LPOSC_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_LPOSC_PD_MASK)

#define SLEEPCON0_SLEEPCFG_PLLANA_PD_MASK        (0x1000U)
#define SLEEPCON0_SLEEPCFG_PLLANA_PD_SHIFT       (12U)
/*! PLLANA_PD - Main PLL Analog Function Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_PLLANA_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_PLLANA_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_PLLANA_PD_MASK)

#define SLEEPCON0_SLEEPCFG_PLLLDO_PD_MASK        (0x2000U)
#define SLEEPCON0_SLEEPCFG_PLLLDO_PD_SHIFT       (13U)
/*! PLLLDO_PD - Main PLL Internal Regulator Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_PLLLDO_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_PLLLDO_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_PLLLDO_PD_MASK)

#define SLEEPCON0_SLEEPCFG_AUDPLLANA_PD_MASK     (0x4000U)
#define SLEEPCON0_SLEEPCFG_AUDPLLANA_PD_SHIFT    (14U)
/*! AUDPLLANA_PD - Audio PLL Analog Function Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_AUDPLLANA_PD(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_AUDPLLANA_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_AUDPLLANA_PD_MASK)

#define SLEEPCON0_SLEEPCFG_AUDPLLLDO_PD_MASK     (0x8000U)
#define SLEEPCON0_SLEEPCFG_AUDPLLLDO_PD_SHIFT    (15U)
/*! AUDPLLLDO_PD - Audio PLL Internal Regulator Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_AUDPLLLDO_PD(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_AUDPLLLDO_PD_MASK)

#define SLEEPCON0_SLEEPCFG_ADC0_PD_MASK          (0x10000U)
#define SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT         (16U)
/*! ADC0_PD - ADC0 Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_SLEEPCFG_ADC0_PD(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_ADC0_PD_SHIFT)) & SLEEPCON0_SLEEPCFG_ADC0_PD_MASK)

#define SLEEPCON0_SLEEPCFG_FRO0_GATE_MASK        (0x20000000U)
#define SLEEPCON0_SLEEPCFG_FRO0_GATE_SHIFT       (29U)
/*! FRO0_GATE - FRO0 Gating
 *  0b0..Removes gating
 *  0b1..Applies gating
 */
#define SLEEPCON0_SLEEPCFG_FRO0_GATE(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_FRO0_GATE_SHIFT)) & SLEEPCON0_SLEEPCFG_FRO0_GATE_MASK)

#define SLEEPCON0_SLEEPCFG_FRO2_GATE_MASK        (0x80000000U)
#define SLEEPCON0_SLEEPCFG_FRO2_GATE_SHIFT       (31U)
/*! FRO2_GATE - FRO2 Gating
 *  0b0..Removes gating
 *  0b1..Applies gating
 */
#define SLEEPCON0_SLEEPCFG_FRO2_GATE(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SLEEPCFG_FRO2_GATE_SHIFT)) & SLEEPCON0_SLEEPCFG_FRO2_GATE_MASK)
/*! @} */

/*! @name RUNCFG - Run Configuration */
/*! @{ */

#define SLEEPCON0_RUNCFG_COMP_MAINCLK_SHUTOFF_MASK (0x1U)
#define SLEEPCON0_RUNCFG_COMP_MAINCLK_SHUTOFF_SHIFT (0U)
/*! COMP_MAINCLK_SHUTOFF - VDD2_COMP Domain compute_main_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_RUNCFG_COMP_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_COMP_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_COMP_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SENSEP_MAINCLK_SHUTOFF_MASK (0x2U)
#define SLEEPCON0_RUNCFG_SENSEP_MAINCLK_SHUTOFF_SHIFT (1U)
/*! SENSEP_MAINCLK_SHUTOFF - VDD1_SENSE Domain sense_main_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_RUNCFG_SENSEP_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SENSEP_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SENSEP_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SENSES_MAINCLK_SHUTOFF_MASK (0x4U)
#define SLEEPCON0_RUNCFG_SENSES_MAINCLK_SHUTOFF_SHIFT (2U)
/*! SENSES_MAINCLK_SHUTOFF - VDD1_SENSE Domain sense_main_clk_1 Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_RUNCFG_SENSES_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SENSES_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SENSES_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_RAM0_CLK_SHUTOFF_MASK   (0x8U)
#define SLEEPCON0_RUNCFG_RAM0_CLK_SHUTOFF_SHIFT  (3U)
/*! RAM0_CLK_SHUTOFF - RAM_ARBITER0 common_ram_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_RUNCFG_RAM0_CLK_SHUTOFF(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_RAM0_CLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_RAM1_CLK_SHUTOFF_MASK   (0x10U)
#define SLEEPCON0_RUNCFG_RAM1_CLK_SHUTOFF_SHIFT  (4U)
/*! RAM1_CLK_SHUTOFF - RAM_ARBITER1 sense_ram_clk shut off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_RUNCFG_RAM1_CLK_SHUTOFF(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_RAM1_CLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_COMN_MAINCLK_SHUTOFF_MASK (0x20U)
#define SLEEPCON0_RUNCFG_COMN_MAINCLK_SHUTOFF_SHIFT (5U)
/*! COMN_MAINCLK_SHUTOFF - VDDN_COM Domain common_vddn_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_RUNCFG_COMN_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_COMN_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_COMN_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_MEDIA_MAINCLK_SHUTOFF_MASK (0x40U)
#define SLEEPCON0_RUNCFG_MEDIA_MAINCLK_SHUTOFF_SHIFT (6U)
/*! MEDIA_MAINCLK_SHUTOFF - VDD2_MEDIA and VDDN_MEDIA Domains media_main_clk and media_vddn_clk Shut Off
 *  0b0..Turns on
 *  0b1..Turns off
 */
#define SLEEPCON0_RUNCFG_MEDIA_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_MEDIA_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_MEDIA_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_XTAL_PD_MASK            (0x80U)
#define SLEEPCON0_RUNCFG_XTAL_PD_SHIFT           (7U)
/*! XTAL_PD - Xtal Oscillator Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_XTAL_PD(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_XTAL_PD_SHIFT)) & SLEEPCON0_RUNCFG_XTAL_PD_MASK)

#define SLEEPCON0_RUNCFG_FRO0_PD_MASK            (0x100U)
#define SLEEPCON0_RUNCFG_FRO0_PD_SHIFT           (8U)
/*! FRO0_PD - FRO0 Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_FRO0_PD(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_FRO0_PD_SHIFT)) & SLEEPCON0_RUNCFG_FRO0_PD_MASK)

#define SLEEPCON0_RUNCFG_FRO1_PD_MASK            (0x200U)
#define SLEEPCON0_RUNCFG_FRO1_PD_SHIFT           (9U)
/*! FRO1_PD - FRO1 Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_FRO1_PD(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_FRO1_PD_SHIFT)) & SLEEPCON0_RUNCFG_FRO1_PD_MASK)

#define SLEEPCON0_RUNCFG_FRO2_PD_MASK            (0x400U)
#define SLEEPCON0_RUNCFG_FRO2_PD_SHIFT           (10U)
/*! FRO2_PD - FRO2 Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_FRO2_PD(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_FRO2_PD_SHIFT)) & SLEEPCON0_RUNCFG_FRO2_PD_MASK)

#define SLEEPCON0_RUNCFG_LPOSC_PD_MASK           (0x800U)
#define SLEEPCON0_RUNCFG_LPOSC_PD_SHIFT          (11U)
/*! LPOSC_PD - LPOSC Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_LPOSC_PD(x)             (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_LPOSC_PD_SHIFT)) & SLEEPCON0_RUNCFG_LPOSC_PD_MASK)

#define SLEEPCON0_RUNCFG_PLLANA_PD_MASK          (0x1000U)
#define SLEEPCON0_RUNCFG_PLLANA_PD_SHIFT         (12U)
/*! PLLANA_PD - Main PLL Analog Function Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_PLLANA_PD(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_PLLANA_PD_SHIFT)) & SLEEPCON0_RUNCFG_PLLANA_PD_MASK)

#define SLEEPCON0_RUNCFG_PLLLDO_PD_MASK          (0x2000U)
#define SLEEPCON0_RUNCFG_PLLLDO_PD_SHIFT         (13U)
/*! PLLLDO_PD - Main PLL Internal Regulator Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_PLLLDO_PD(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_PLLLDO_PD_SHIFT)) & SLEEPCON0_RUNCFG_PLLLDO_PD_MASK)

#define SLEEPCON0_RUNCFG_AUDPLLANA_PD_MASK       (0x4000U)
#define SLEEPCON0_RUNCFG_AUDPLLANA_PD_SHIFT      (14U)
/*! AUDPLLANA_PD - Audio PLL Analog Function Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_AUDPLLANA_PD(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_AUDPLLANA_PD_SHIFT)) & SLEEPCON0_RUNCFG_AUDPLLANA_PD_MASK)

#define SLEEPCON0_RUNCFG_AUDPLLLDO_PD_MASK       (0x8000U)
#define SLEEPCON0_RUNCFG_AUDPLLLDO_PD_SHIFT      (15U)
/*! AUDPLLLDO_PD - Audio PLL Internal Regulator Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_AUDPLLLDO_PD(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON0_RUNCFG_AUDPLLLDO_PD_MASK)

#define SLEEPCON0_RUNCFG_ADC0_PD_MASK            (0x10000U)
#define SLEEPCON0_RUNCFG_ADC0_PD_SHIFT           (16U)
/*! ADC0_PD - ADC0 Power Down
 *  0b0..Powers on
 *  0b1..Powers down
 */
#define SLEEPCON0_RUNCFG_ADC0_PD(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_ADC0_PD_SHIFT)) & SLEEPCON0_RUNCFG_ADC0_PD_MASK)

#define SLEEPCON0_RUNCFG_FRO0_GATE_MASK          (0x20000000U)
#define SLEEPCON0_RUNCFG_FRO0_GATE_SHIFT         (29U)
/*! FRO0_GATE - FRO0 Gating
 *  0b0..Removes gating
 *  0b1..Applies gating
 */
#define SLEEPCON0_RUNCFG_FRO0_GATE(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_FRO0_GATE_SHIFT)) & SLEEPCON0_RUNCFG_FRO0_GATE_MASK)

#define SLEEPCON0_RUNCFG_FRO2_GATE_MASK          (0x80000000U)
#define SLEEPCON0_RUNCFG_FRO2_GATE_SHIFT         (31U)
/*! FRO2_GATE - FRO2 Gating
 *  0b0..Removes gating
 *  0b1..Applies gating
 */
#define SLEEPCON0_RUNCFG_FRO2_GATE(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_FRO2_GATE_SHIFT)) & SLEEPCON0_RUNCFG_FRO2_GATE_MASK)
/*! @} */

/*! @name RUNCFG_SET - RUNCFG Set */
/*! @{ */

#define SLEEPCON0_RUNCFG_SET_COMP_MAINCLK_SHUTOFF_MASK (0x1U)
#define SLEEPCON0_RUNCFG_SET_COMP_MAINCLK_SHUTOFF_SHIFT (0U)
/*! COMP_MAINCLK_SHUTOFF - VDD2_COMP Domain compute_main_clk Shut off Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_COMP_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_COMP_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SET_COMP_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SET_SENSEP_MAINCLK_SHUTOFF_MASK (0x2U)
#define SLEEPCON0_RUNCFG_SET_SENSEP_MAINCLK_SHUTOFF_SHIFT (1U)
/*! SENSEP_MAINCLK_SHUTOFF - VDD1_SENSE Domain sense_main_clk Shut Off Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_SENSEP_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_SENSEP_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SET_SENSEP_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SET_SENSES_MAINCLK_SHUTOFF_MASK (0x4U)
#define SLEEPCON0_RUNCFG_SET_SENSES_MAINCLK_SHUTOFF_SHIFT (2U)
/*! SENSES_MAINCLK_SHUTOFF - VDD1_SENSE Domain sense_main_clk_1 Shut Off Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_SENSES_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_SENSES_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SET_SENSES_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SET_RAM0_CLK_SHUTOFF_MASK (0x8U)
#define SLEEPCON0_RUNCFG_SET_RAM0_CLK_SHUTOFF_SHIFT (3U)
/*! RAM0_CLK_SHUTOFF - RAM_ARBITER0 common_ram_clk Shut Off Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_RAM0_CLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SET_RAM0_CLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SET_RAM1_CLK_SHUTOFF_MASK (0x10U)
#define SLEEPCON0_RUNCFG_SET_RAM1_CLK_SHUTOFF_SHIFT (4U)
/*! RAM1_CLK_SHUTOFF - RAM_ARBITER1 sense_ram_clk Shut Off Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_RAM1_CLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SET_RAM1_CLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SET_COMN_MAINCLK_SHUTOFF_MASK (0x20U)
#define SLEEPCON0_RUNCFG_SET_COMN_MAINCLK_SHUTOFF_SHIFT (5U)
/*! COMN_MAINCLK_SHUTOFF - VDDN_COM Domain common_vddn_clk Shut Off Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_COMN_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_COMN_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SET_COMN_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SET_MEDIA_MAINCLK_SHUTOFF_MASK (0x40U)
#define SLEEPCON0_RUNCFG_SET_MEDIA_MAINCLK_SHUTOFF_SHIFT (6U)
/*! MEDIA_MAINCLK_SHUTOFF - VDD2_MEDIA and VDDN_MEDIA Domains media_main_clk and media_vddn_clk Shut Off Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_MEDIA_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_MEDIA_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_SET_MEDIA_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_SET_XTAL_PD_MASK        (0x80U)
#define SLEEPCON0_RUNCFG_SET_XTAL_PD_SHIFT       (7U)
/*! XTAL_PD - Xtal Oscillator Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_XTAL_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_XTAL_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_XTAL_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_FRO0_PD_MASK        (0x100U)
#define SLEEPCON0_RUNCFG_SET_FRO0_PD_SHIFT       (8U)
/*! FRO0_PD - FRO0 Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_FRO0_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_FRO0_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_FRO0_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_FRO1_PD_MASK        (0x200U)
#define SLEEPCON0_RUNCFG_SET_FRO1_PD_SHIFT       (9U)
/*! FRO1_PD - FRO1 Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_FRO1_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_FRO1_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_FRO1_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_FRO2_PD_MASK        (0x400U)
#define SLEEPCON0_RUNCFG_SET_FRO2_PD_SHIFT       (10U)
/*! FRO2_PD - FRO2 Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_FRO2_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_FRO2_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_FRO2_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_LPOSC_PD_MASK       (0x800U)
#define SLEEPCON0_RUNCFG_SET_LPOSC_PD_SHIFT      (11U)
/*! LPOSC_PD - LPOSC Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_LPOSC_PD(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_LPOSC_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_LPOSC_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_PLLANA_PD_MASK      (0x1000U)
#define SLEEPCON0_RUNCFG_SET_PLLANA_PD_SHIFT     (12U)
/*! PLLANA_PD - Main PLL Analog Function Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_PLLANA_PD(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_PLLANA_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_PLLANA_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_PLLLDO_PD_MASK      (0x2000U)
#define SLEEPCON0_RUNCFG_SET_PLLLDO_PD_SHIFT     (13U)
/*! PLLLDO_PD - Main PLL Internal Regulator Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_PLLLDO_PD(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_PLLLDO_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_PLLLDO_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_AUDPLLANA_PD_MASK   (0x4000U)
#define SLEEPCON0_RUNCFG_SET_AUDPLLANA_PD_SHIFT  (14U)
/*! AUDPLLANA_PD - Audio PLL Analog Function Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_AUDPLLANA_PD(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_AUDPLLANA_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_AUDPLLANA_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_AUDPLLLDO_PD_MASK   (0x8000U)
#define SLEEPCON0_RUNCFG_SET_AUDPLLLDO_PD_SHIFT  (15U)
/*! AUDPLLLDO_PD - Audio PLL Internal Regulator Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_AUDPLLLDO_PD(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_AUDPLLLDO_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_AUDPLLLDO_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_ADC0_PD_MASK        (0x10000U)
#define SLEEPCON0_RUNCFG_SET_ADC0_PD_SHIFT       (16U)
/*! ADC0_PD - ADC0 Power Down Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_ADC0_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_ADC0_PD_SHIFT)) & SLEEPCON0_RUNCFG_SET_ADC0_PD_MASK)

#define SLEEPCON0_RUNCFG_SET_FRO0_GATE_MASK      (0x20000000U)
#define SLEEPCON0_RUNCFG_SET_FRO0_GATE_SHIFT     (29U)
/*! FRO0_GATE - FRO0 Gating Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_FRO0_GATE(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_FRO0_GATE_SHIFT)) & SLEEPCON0_RUNCFG_SET_FRO0_GATE_MASK)

#define SLEEPCON0_RUNCFG_SET_FRO2_GATE_MASK      (0x80000000U)
#define SLEEPCON0_RUNCFG_SET_FRO2_GATE_SHIFT     (31U)
/*! FRO2_GATE - FRO2 Gating Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_RUNCFG_SET_FRO2_GATE(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_SET_FRO2_GATE_SHIFT)) & SLEEPCON0_RUNCFG_SET_FRO2_GATE_MASK)
/*! @} */

/*! @name RUNCFG_CLR - RUNCFG Clear */
/*! @{ */

#define SLEEPCON0_RUNCFG_CLR_COMP_MAINCLK_SHUTOFF_MASK (0x1U)
#define SLEEPCON0_RUNCFG_CLR_COMP_MAINCLK_SHUTOFF_SHIFT (0U)
/*! COMP_MAINCLK_SHUTOFF - VDD2_COMP Domain compute_main_clk Shut Off Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_COMP_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_COMP_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_CLR_COMP_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_CLR_SENSEP_MAINCLK_SHUTOFF_MASK (0x2U)
#define SLEEPCON0_RUNCFG_CLR_SENSEP_MAINCLK_SHUTOFF_SHIFT (1U)
/*! SENSEP_MAINCLK_SHUTOFF - VDD1_SENSE Domain sense_main_clk Shut Off Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_SENSEP_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_SENSEP_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_CLR_SENSEP_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_CLR_SENSES_MAINCLK_SHUTOFF_MASK (0x4U)
#define SLEEPCON0_RUNCFG_CLR_SENSES_MAINCLK_SHUTOFF_SHIFT (2U)
/*! SENSES_MAINCLK_SHUTOFF - VDD1_SENSE Domain sense_main_clk_1 Shut Off Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_SENSES_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_SENSES_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_CLR_SENSES_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_CLR_RAM0_CLK_SHUTOFF_MASK (0x8U)
#define SLEEPCON0_RUNCFG_CLR_RAM0_CLK_SHUTOFF_SHIFT (3U)
/*! RAM0_CLK_SHUTOFF - RAM_ARBITER0 common_ram_clk Shut Off Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_RAM0_CLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_RAM0_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_CLR_RAM0_CLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_CLR_RAM1_CLK_SHUTOFF_MASK (0x10U)
#define SLEEPCON0_RUNCFG_CLR_RAM1_CLK_SHUTOFF_SHIFT (4U)
/*! RAM1_CLK_SHUTOFF - RAM_ARBITER1 sense_ram_clk Shut Off Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_RAM1_CLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_RAM1_CLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_CLR_RAM1_CLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_CLR_COMN_MAINCLK_SHUTOFF_MASK (0x20U)
#define SLEEPCON0_RUNCFG_CLR_COMN_MAINCLK_SHUTOFF_SHIFT (5U)
/*! COMN_MAINCLK_SHUTOFF - VDDN_COM Domain common_vddn_clk Shut Off Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_COMN_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_COMN_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_CLR_COMN_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_CLR_MEDIA_MAINCLK_SHUTOFF_MASK (0x40U)
#define SLEEPCON0_RUNCFG_CLR_MEDIA_MAINCLK_SHUTOFF_SHIFT (6U)
/*! MEDIA_MAINCLK_SHUTOFF - VDD2_MEDIA and VDDN_MEDIA Domains media_main_clk and media_vddn_clk Shut Off Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_MEDIA_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_MEDIA_MAINCLK_SHUTOFF_SHIFT)) & SLEEPCON0_RUNCFG_CLR_MEDIA_MAINCLK_SHUTOFF_MASK)

#define SLEEPCON0_RUNCFG_CLR_XTAL_PD_MASK        (0x80U)
#define SLEEPCON0_RUNCFG_CLR_XTAL_PD_SHIFT       (7U)
/*! XTAL_PD - Xtal Oscillator Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_XTAL_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_XTAL_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_XTAL_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_FRO0_PD_MASK        (0x100U)
#define SLEEPCON0_RUNCFG_CLR_FRO0_PD_SHIFT       (8U)
/*! FRO0_PD - FRO0 Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_FRO0_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_FRO0_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_FRO0_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_FRO1_PD_MASK        (0x200U)
#define SLEEPCON0_RUNCFG_CLR_FRO1_PD_SHIFT       (9U)
/*! FRO1_PD - FRO1 Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_FRO1_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_FRO1_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_FRO1_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_FRO2_PD_MASK        (0x400U)
#define SLEEPCON0_RUNCFG_CLR_FRO2_PD_SHIFT       (10U)
/*! FRO2_PD - FRO2 Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_FRO2_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_FRO2_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_FRO2_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_LPOSC_PD_MASK       (0x800U)
#define SLEEPCON0_RUNCFG_CLR_LPOSC_PD_SHIFT      (11U)
/*! LPOSC_PD - LPOSC Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_LPOSC_PD(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_LPOSC_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_LPOSC_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_PLLANA_PD_MASK      (0x1000U)
#define SLEEPCON0_RUNCFG_CLR_PLLANA_PD_SHIFT     (12U)
/*! PLLANA_PD - Main PLL Analog Function Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_PLLANA_PD(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_PLLANA_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_PLLANA_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_PLLLDO_PD_MASK      (0x2000U)
#define SLEEPCON0_RUNCFG_CLR_PLLLDO_PD_SHIFT     (13U)
/*! PLLLDO_PD - Main PLL Internal Regulator Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_PLLLDO_PD(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_PLLLDO_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_PLLLDO_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_AUDPLLANA_PD_MASK   (0x4000U)
#define SLEEPCON0_RUNCFG_CLR_AUDPLLANA_PD_SHIFT  (14U)
/*! AUDPLLANA_PD - Audio PLL Analog Function Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_AUDPLLANA_PD(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_AUDPLLANA_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_AUDPLLANA_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_AUDPLLLDO_PD_MASK   (0x8000U)
#define SLEEPCON0_RUNCFG_CLR_AUDPLLLDO_PD_SHIFT  (15U)
/*! AUDPLLLDO_PD - Audio PLL Internal Regulator Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_AUDPLLLDO_PD(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_AUDPLLLDO_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_AUDPLLLDO_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_ADC0_PD_MASK        (0x10000U)
#define SLEEPCON0_RUNCFG_CLR_ADC0_PD_SHIFT       (16U)
/*! ADC0_PD - ADC0 Power Down Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_ADC0_PD(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_ADC0_PD_SHIFT)) & SLEEPCON0_RUNCFG_CLR_ADC0_PD_MASK)

#define SLEEPCON0_RUNCFG_CLR_FRO0_GATE_MASK      (0x20000000U)
#define SLEEPCON0_RUNCFG_CLR_FRO0_GATE_SHIFT     (29U)
/*! FRO0_GATE - FRO0 Gating Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_FRO0_GATE(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_FRO0_GATE_SHIFT)) & SLEEPCON0_RUNCFG_CLR_FRO0_GATE_MASK)

#define SLEEPCON0_RUNCFG_CLR_FRO2_GATE_MASK      (0x80000000U)
#define SLEEPCON0_RUNCFG_CLR_FRO2_GATE_SHIFT     (31U)
/*! FRO2_GATE - FRO2 Gating Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_RUNCFG_CLR_FRO2_GATE(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_RUNCFG_CLR_FRO2_GATE_SHIFT)) & SLEEPCON0_RUNCFG_CLR_FRO2_GATE_MASK)
/*! @} */

/*! @name WAKEUPEN0 - Wakeup Enable 0 */
/*! @{ */

#define SLEEPCON0_WAKEUPEN0_UTICK0_MASK          (0x2U)
#define SLEEPCON0_WAKEUPEN0_UTICK0_SHIFT         (1U)
/*! UTICK0 - UTICK0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_UTICK0(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_UTICK0_SHIFT)) & SLEEPCON0_WAKEUPEN0_UTICK0_MASK)

#define SLEEPCON0_WAKEUPEN0_CTIMER0_MASK         (0x8U)
#define SLEEPCON0_WAKEUPEN0_CTIMER0_SHIFT        (3U)
/*! CTIMER0 - CTIMER0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_CTIMER0(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CTIMER0_SHIFT)) & SLEEPCON0_WAKEUPEN0_CTIMER0_MASK)

#define SLEEPCON0_WAKEUPEN0_CTIMER1_MASK         (0x10U)
#define SLEEPCON0_WAKEUPEN0_CTIMER1_SHIFT        (4U)
/*! CTIMER1 - CTIMER1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_CTIMER1(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CTIMER1_SHIFT)) & SLEEPCON0_WAKEUPEN0_CTIMER1_MASK)

#define SLEEPCON0_WAKEUPEN0_CTIMER3_MASK         (0x40U)
#define SLEEPCON0_WAKEUPEN0_CTIMER3_SHIFT        (6U)
/*! CTIMER3 - CTIMER3 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_CTIMER3(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CTIMER3_SHIFT)) & SLEEPCON0_WAKEUPEN0_CTIMER3_MASK)

#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM0_MASK    (0x80U)
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM0_SHIFT   (7U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM0(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM0_SHIFT)) & SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM0_MASK)

#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM1_MASK    (0x100U)
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM1_SHIFT   (8U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM1(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM1_SHIFT)) & SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM1_MASK)

#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM2_MASK    (0x200U)
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM2_SHIFT   (9U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM2(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM2_SHIFT)) & SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM2_MASK)

#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM3_MASK    (0x400U)
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM3_SHIFT   (10U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM3(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM3_SHIFT)) & SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM3_MASK)

#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM4_MASK    (0x800U)
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM4_SHIFT   (11U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM4(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM4_SHIFT)) & SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM4_MASK)

#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM5_MASK    (0x1000U)
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM5_SHIFT   (12U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM5(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM5_SHIFT)) & SLEEPCON0_WAKEUPEN0_LP_FLEXCOMM5_MASK)

#define SLEEPCON0_WAKEUPEN0_LPSPI14_MASK         (0x2000U)
#define SLEEPCON0_WAKEUPEN0_LPSPI14_SHIFT        (13U)
/*! LPSPI14 - LPSPI14 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_LPSPI14(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_LPSPI14_SHIFT)) & SLEEPCON0_WAKEUPEN0_LPSPI14_MASK)

#define SLEEPCON0_WAKEUPEN0_LPI2C15_MASK         (0x4000U)
#define SLEEPCON0_WAKEUPEN0_LPI2C15_SHIFT        (14U)
/*! LPI2C15 - LPI2C15 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_LPI2C15(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_LPI2C15_SHIFT)) & SLEEPCON0_WAKEUPEN0_LPI2C15_MASK)

#define SLEEPCON0_WAKEUPEN0_ADC0_MASK            (0x8000U)
#define SLEEPCON0_WAKEUPEN0_ADC0_SHIFT           (15U)
/*! ADC0 - ADC0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_ADC0(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_ADC0_SHIFT)) & SLEEPCON0_WAKEUPEN0_ADC0_MASK)

#define SLEEPCON0_WAKEUPEN0_ACMP0_MASK           (0x20000U)
#define SLEEPCON0_WAKEUPEN0_ACMP0_SHIFT          (17U)
/*! ACMP0 - ACMP0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_ACMP0(x)             (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_ACMP0_SHIFT)) & SLEEPCON0_WAKEUPEN0_ACMP0_MASK)

#define SLEEPCON0_WAKEUPEN0_MICFIL_RD_ERR_MASK   (0x40000U)
#define SLEEPCON0_WAKEUPEN0_MICFIL_RD_ERR_SHIFT  (18U)
/*! MICFIL_RD_ERR - MICFIL Read Data Error Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_MICFIL_RD_ERR(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_MICFIL_RD_ERR_SHIFT)) & SLEEPCON0_WAKEUPEN0_MICFIL_RD_ERR_MASK)

#define SLEEPCON0_WAKEUPEN0_MICFIL_WKUP_MASK     (0x80000U)
#define SLEEPCON0_WAKEUPEN0_MICFIL_WKUP_SHIFT    (19U)
/*! MICFIL_WKUP - MICFIL Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_MICFIL_WKUP(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_MICFIL_WKUP_SHIFT)) & SLEEPCON0_WAKEUPEN0_MICFIL_WKUP_MASK)

#define SLEEPCON0_WAKEUPEN0_RTC0_ALARM_MASK      (0x4000000U)
#define SLEEPCON0_WAKEUPEN0_RTC0_ALARM_SHIFT     (26U)
/*! RTC0_ALARM - RTC0_ALARM Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_RTC0_ALARM(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_RTC0_ALARM_SHIFT)) & SLEEPCON0_WAKEUPEN0_RTC0_ALARM_MASK)

#define SLEEPCON0_WAKEUPEN0_RTC0_WKUP_MASK       (0x8000000U)
#define SLEEPCON0_WAKEUPEN0_RTC0_WKUP_SHIFT      (27U)
/*! RTC0_WKUP - RTC0_WKUP Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_RTC0_WKUP(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_RTC0_WKUP_SHIFT)) & SLEEPCON0_WAKEUPEN0_RTC0_WKUP_MASK)

#define SLEEPCON0_WAKEUPEN0_MU0_MUA_MASK         (0x20000000U)
#define SLEEPCON0_WAKEUPEN0_MU0_MUA_SHIFT        (29U)
/*! MU0_MUA - MU0_MUA Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_MU0_MUA(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_MU0_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_MU0_MUA_MASK)

#define SLEEPCON0_WAKEUPEN0_MU1_MUA_MASK         (0x40000000U)
#define SLEEPCON0_WAKEUPEN0_MU1_MUA_SHIFT        (30U)
/*! MU1_MUA - MU1_MUA Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_MU1_MUA(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_MU1_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_MU1_MUA_MASK)

#define SLEEPCON0_WAKEUPEN0_MU4_MUA_MASK         (0x80000000U)
#define SLEEPCON0_WAKEUPEN0_MU4_MUA_SHIFT        (31U)
/*! MU4_MUA - MU4_MUA Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN0_MU4_MUA(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_MU4_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_MU4_MUA_MASK)
/*! @} */

/*! @name WAKEUPEN1 - Wakeup Enable 1 */
/*! @{ */

#define SLEEPCON0_WAKEUPEN1_CTIMER2_MASK         (0x1U)
#define SLEEPCON0_WAKEUPEN1_CTIMER2_SHIFT        (0U)
/*! CTIMER2 - CTIMER2 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_CTIMER2(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CTIMER2_SHIFT)) & SLEEPCON0_WAKEUPEN1_CTIMER2_MASK)

#define SLEEPCON0_WAKEUPEN1_CTIMER4_MASK         (0x2U)
#define SLEEPCON0_WAKEUPEN1_CTIMER4_SHIFT        (1U)
/*! CTIMER4 - CTIMER4 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_CTIMER4(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CTIMER4_SHIFT)) & SLEEPCON0_WAKEUPEN1_CTIMER4_MASK)

#define SLEEPCON0_WAKEUPEN1_OSTIMER_MASK         (0x4U)
#define SLEEPCON0_WAKEUPEN1_OSTIMER_SHIFT        (2U)
/*! OSTIMER - OSTIMER Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_OSTIMER(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_OSTIMER_SHIFT)) & SLEEPCON0_WAKEUPEN1_OSTIMER_MASK)

#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM6_MASK    (0x8U)
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM6_SHIFT   (3U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM6(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM6_SHIFT)) & SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM6_MASK)

#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM7_MASK    (0x10U)
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM7_SHIFT   (4U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM7(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM7_SHIFT)) & SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM7_MASK)

#define SLEEPCON0_WAKEUPEN1_I3C0_MASK            (0x80U)
#define SLEEPCON0_WAKEUPEN1_I3C0_SHIFT           (7U)
/*! I3C0 - I3C0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_I3C0(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_I3C0_SHIFT)) & SLEEPCON0_WAKEUPEN1_I3C0_MASK)

#define SLEEPCON0_WAKEUPEN1_USB0_MASK            (0x100U)
#define SLEEPCON0_WAKEUPEN1_USB0_SHIFT           (8U)
/*! USB0 - USB0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_USB0(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_USB0_SHIFT)) & SLEEPCON0_WAKEUPEN1_USB0_MASK)

#define SLEEPCON0_WAKEUPEN1_USB1_MASK            (0x200U)
#define SLEEPCON0_WAKEUPEN1_USB1_SHIFT           (9U)
/*! USB1 - USB1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_USB1(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_USB1_SHIFT)) & SLEEPCON0_WAKEUPEN1_USB1_MASK)

#define SLEEPCON0_WAKEUPEN1_WWDT0_MASK           (0x400U)
#define SLEEPCON0_WAKEUPEN1_WWDT0_SHIFT          (10U)
/*! WWDT0 - WWDT0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_WWDT0(x)             (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_WWDT0_SHIFT)) & SLEEPCON0_WAKEUPEN1_WWDT0_MASK)

#define SLEEPCON0_WAKEUPEN1_WWDT1_MASK           (0x800U)
#define SLEEPCON0_WAKEUPEN1_WWDT1_SHIFT          (11U)
/*! WWDT1 - WWDT1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_WWDT1(x)             (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_WWDT1_SHIFT)) & SLEEPCON0_WAKEUPEN1_WWDT1_MASK)

#define SLEEPCON0_WAKEUPEN1_USBPHY0_MASK         (0x1000U)
#define SLEEPCON0_WAKEUPEN1_USBPHY0_SHIFT        (12U)
/*! USBPHY0 - USBPHY0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_USBPHY0(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_USBPHY0_SHIFT)) & SLEEPCON0_WAKEUPEN1_USBPHY0_MASK)

#define SLEEPCON0_WAKEUPEN1_PMIC_IRQN_MASK       (0x4000U)
#define SLEEPCON0_WAKEUPEN1_PMIC_IRQN_SHIFT      (14U)
/*! PMIC_IRQN - PMIC_IRQN Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_PMIC_IRQN(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_PMIC_IRQN_SHIFT)) & SLEEPCON0_WAKEUPEN1_PMIC_IRQN_MASK)

#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM8_MASK    (0x8000U)
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM8_SHIFT   (15U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM8(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM8_SHIFT)) & SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM8_MASK)

#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM9_MASK    (0x10000U)
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM9_SHIFT   (16U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM9(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM9_SHIFT)) & SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM9_MASK)

#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM10_MASK   (0x20000U)
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM10_SHIFT  (17U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM10(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM10_SHIFT)) & SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM10_MASK)

#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM11_MASK   (0x40000U)
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM11_SHIFT  (18U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM11(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM11_SHIFT)) & SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM11_MASK)

#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM12_MASK   (0x80000U)
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM12_SHIFT  (19U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM12(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM12_SHIFT)) & SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM12_MASK)

#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM13_MASK   (0x100000U)
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM13_SHIFT  (20U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM13(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM13_SHIFT)) & SLEEPCON0_WAKEUPEN1_LP_FLEXCOMM13_MASK)

#define SLEEPCON0_WAKEUPEN1_LPSPI16_MASK         (0x200000U)
#define SLEEPCON0_WAKEUPEN1_LPSPI16_SHIFT        (21U)
/*! LPSPI16 - LPSPI16 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_LPSPI16(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_LPSPI16_SHIFT)) & SLEEPCON0_WAKEUPEN1_LPSPI16_MASK)

#define SLEEPCON0_WAKEUPEN1_I3C1_MASK            (0x400000U)
#define SLEEPCON0_WAKEUPEN1_I3C1_SHIFT           (22U)
/*! I3C1 - I3C1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_I3C1(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_I3C1_SHIFT)) & SLEEPCON0_WAKEUPEN1_I3C1_MASK)

#define SLEEPCON0_WAKEUPEN1_FLEXIO_MASK          (0x800000U)
#define SLEEPCON0_WAKEUPEN1_FLEXIO_SHIFT         (23U)
/*! FLEXIO - FLEXIO Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_FLEXIO(x)            (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_FLEXIO_SHIFT)) & SLEEPCON0_WAKEUPEN1_FLEXIO_MASK)

#define SLEEPCON0_WAKEUPEN1_EDMA0_CH0_MASK       (0x8000000U)
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH0_SHIFT      (27U)
/*! EDMA0_CH0 - eDMA0 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_EDMA0_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN1_EDMA0_CH0_MASK)

#define SLEEPCON0_WAKEUPEN1_EDMA0_CH1_MASK       (0x10000000U)
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH1_SHIFT      (28U)
/*! EDMA0_CH1 - eDMA0 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_EDMA0_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN1_EDMA0_CH1_MASK)

#define SLEEPCON0_WAKEUPEN1_EDMA0_CH2_MASK       (0x20000000U)
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH2_SHIFT      (29U)
/*! EDMA0_CH2 - eDMA0 Channel 2 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH2(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_EDMA0_CH2_SHIFT)) & SLEEPCON0_WAKEUPEN1_EDMA0_CH2_MASK)

#define SLEEPCON0_WAKEUPEN1_EDMA0_CH3_MASK       (0x40000000U)
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH3_SHIFT      (30U)
/*! EDMA0_CH3 - eDMA0 Channel 3 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH3(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_EDMA0_CH3_SHIFT)) & SLEEPCON0_WAKEUPEN1_EDMA0_CH3_MASK)

#define SLEEPCON0_WAKEUPEN1_EDMA0_CH4_MASK       (0x80000000U)
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH4_SHIFT      (31U)
/*! EDMA0_CH4 - eDMA0 Channel 4 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN1_EDMA0_CH4(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_EDMA0_CH4_SHIFT)) & SLEEPCON0_WAKEUPEN1_EDMA0_CH4_MASK)
/*! @} */

/*! @name WAKEUPEN2 - Wakeup Enable 2 */
/*! @{ */

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH5_MASK       (0x1U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH5_SHIFT      (0U)
/*! EDMA0_CH5 - eDMA0 Channel 5 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH5(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH5_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH5_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH6_MASK       (0x2U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH6_SHIFT      (1U)
/*! EDMA0_CH6 - eDMA0 Channel 6 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH6(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH6_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH6_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH7_MASK       (0x4U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH7_SHIFT      (2U)
/*! EDMA0_CH7 - eDMA0 Channel 7 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH7(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH7_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH7_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH8_MASK       (0x8U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH8_SHIFT      (3U)
/*! EDMA0_CH8 - eDMA0 Channel 8 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH8(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH8_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH8_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH9_MASK       (0x10U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH9_SHIFT      (4U)
/*! EDMA0_CH9 - eDMA0 Channel 9 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH9(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH9_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH9_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH10_MASK      (0x20U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH10_SHIFT     (5U)
/*! EDMA0_CH10 - eDMA0 Channel 10 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH10(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH10_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH10_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH11_MASK      (0x40U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH11_SHIFT     (6U)
/*! EDMA0_CH11 - eDMA0 Channel 11 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH11(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH11_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH11_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH12_MASK      (0x80U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH12_SHIFT     (7U)
/*! EDMA0_CH12 - eDMA0 Channel 12 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH12(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH12_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH12_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH13_MASK      (0x100U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH13_SHIFT     (8U)
/*! EDMA0_CH13 - eDMA0 Channel 13 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH13(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH13_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH13_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH14_MASK      (0x200U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH14_SHIFT     (9U)
/*! EDMA0_CH14 - eDMA0 Channel 14 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH14(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH14_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH14_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA0_CH15_MASK      (0x400U)
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH15_SHIFT     (10U)
/*! EDMA0_CH15 - eDMA0 Channel 15 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA0_CH15(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA0_CH15_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA0_CH15_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH0_MASK       (0x800U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH0_SHIFT      (11U)
/*! EDMA1_CH0 - eDMA1 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH1_MASK       (0x1000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH1_SHIFT      (12U)
/*! EDMA1_CH1 - eDMA1 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH2_MASK       (0x2000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH2_SHIFT      (13U)
/*! EDMA1_CH2 - eDMA1 Channel 2 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH2(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH2_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH2_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH3_MASK       (0x4000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH3_SHIFT      (14U)
/*! EDMA1_CH3 - eDMA1 Channel 3 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH3(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH3_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH3_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH4_MASK       (0x8000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH4_SHIFT      (15U)
/*! EDMA1_CH4 - eDMA1 Channel 4 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH4(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH4_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH4_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH5_MASK       (0x10000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH5_SHIFT      (16U)
/*! EDMA1_CH5 - eDMA1 Channel 5 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH5(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH5_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH5_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH6_MASK       (0x20000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH6_SHIFT      (17U)
/*! EDMA1_CH6 - eDMA1 Channel 6 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH6(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH6_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH6_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH7_MASK       (0x40000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH7_SHIFT      (18U)
/*! EDMA1_CH7 - eDMA1 Channel 7 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH7(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH7_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH7_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH8_MASK       (0x80000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH8_SHIFT      (19U)
/*! EDMA1_CH8 - eDMA1 Channel 8 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH8(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH8_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH8_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH9_MASK       (0x100000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH9_SHIFT      (20U)
/*! EDMA1_CH9 - eDMA1 Channel 9 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH9(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH9_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH9_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH10_MASK      (0x200000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH10_SHIFT     (21U)
/*! EDMA1_CH10 - eDMA1 Channel 10 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH10(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH10_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH10_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH11_MASK      (0x400000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH11_SHIFT     (22U)
/*! EDMA1_CH11 - eDMA1 Channel 11 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH11(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH11_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH11_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH12_MASK      (0x800000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH12_SHIFT     (23U)
/*! EDMA1_CH12 - eDMA1 Channel 12 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH12(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH12_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH12_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH13_MASK      (0x1000000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH13_SHIFT     (24U)
/*! EDMA1_CH13 - eDMA1 Channel 13 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH13(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH13_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH13_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH14_MASK      (0x2000000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH14_SHIFT     (25U)
/*! EDMA1_CH14 - eDMA1 Channel 14 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH14(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH14_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH14_MASK)

#define SLEEPCON0_WAKEUPEN2_EDMA1_CH15_MASK      (0x4000000U)
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH15_SHIFT     (26U)
/*! EDMA1_CH15 - eDMA1 Channel 15 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_EDMA1_CH15(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_EDMA1_CH15_SHIFT)) & SLEEPCON0_WAKEUPEN2_EDMA1_CH15_MASK)

#define SLEEPCON0_WAKEUPEN2_GPIO0_CH0_MASK       (0x8000000U)
#define SLEEPCON0_WAKEUPEN2_GPIO0_CH0_SHIFT      (27U)
/*! GPIO0_CH0 - GPIO0 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_GPIO0_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_GPIO0_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_GPIO0_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_GPIO0_CH1_MASK       (0x10000000U)
#define SLEEPCON0_WAKEUPEN2_GPIO0_CH1_SHIFT      (28U)
/*! GPIO0_CH1 - GPIO0 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_GPIO0_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_GPIO0_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_GPIO0_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_GPIO1_CH0_MASK       (0x20000000U)
#define SLEEPCON0_WAKEUPEN2_GPIO1_CH0_SHIFT      (29U)
/*! GPIO1_CH0 - GPIO1 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_GPIO1_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_GPIO1_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_GPIO1_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_GPIO1_CH1_MASK       (0x40000000U)
#define SLEEPCON0_WAKEUPEN2_GPIO1_CH1_SHIFT      (30U)
/*! GPIO1_CH1 - GPIO1 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_GPIO1_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_GPIO1_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_GPIO1_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_GPIO2_CH0_MASK       (0x80000000U)
#define SLEEPCON0_WAKEUPEN2_GPIO2_CH0_SHIFT      (31U)
/*! GPIO2_CH0 - GPIO2 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN2_GPIO2_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_GPIO2_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_GPIO2_CH0_MASK)
/*! @} */

/*! @name WAKEUPEN3 - Wakeup Enable 3 */
/*! @{ */

#define SLEEPCON0_WAKEUPEN3_GPIO2_CH1_MASK       (0x1U)
#define SLEEPCON0_WAKEUPEN3_GPIO2_CH1_SHIFT      (0U)
/*! GPIO2_CH1 - GPIO2 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO2_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO2_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO2_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO3_CH0_MASK       (0x2U)
#define SLEEPCON0_WAKEUPEN3_GPIO3_CH0_SHIFT      (1U)
/*! GPIO3_CH0 - GPIO3 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO3_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO3_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO3_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO3_CH1_MASK       (0x4U)
#define SLEEPCON0_WAKEUPEN3_GPIO3_CH1_SHIFT      (2U)
/*! GPIO3_CH1 - GPIO3 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO3_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO3_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO3_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO4_CH0_MASK       (0x8U)
#define SLEEPCON0_WAKEUPEN3_GPIO4_CH0_SHIFT      (3U)
/*! GPIO4_CH0 - GPIO4 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO4_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO4_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO4_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO4_CH1_MASK       (0x10U)
#define SLEEPCON0_WAKEUPEN3_GPIO4_CH1_SHIFT      (4U)
/*! GPIO4_CH1 - GPIO4 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO4_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO4_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO4_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO5_CH0_MASK       (0x20U)
#define SLEEPCON0_WAKEUPEN3_GPIO5_CH0_SHIFT      (5U)
/*! GPIO5_CH0 - GPIO5 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO5_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO5_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO5_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO5_CH1_MASK       (0x40U)
#define SLEEPCON0_WAKEUPEN3_GPIO5_CH1_SHIFT      (6U)
/*! GPIO5_CH1 - GPIO5 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO5_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO5_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO5_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO6_CH0_MASK       (0x80U)
#define SLEEPCON0_WAKEUPEN3_GPIO6_CH0_SHIFT      (7U)
/*! GPIO6_CH0 - GPIO6 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO6_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO6_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO6_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO6_CH1_MASK       (0x100U)
#define SLEEPCON0_WAKEUPEN3_GPIO6_CH1_SHIFT      (8U)
/*! GPIO6_CH1 - GPIO6 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO6_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO6_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO6_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO7_CH0_MASK       (0x200U)
#define SLEEPCON0_WAKEUPEN3_GPIO7_CH0_SHIFT      (9U)
/*! GPIO7_CH0 - GPIO7 Channel 0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO7_CH0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO7_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO7_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_GPIO7_CH1_MASK       (0x400U)
#define SLEEPCON0_WAKEUPEN3_GPIO7_CH1_SHIFT      (10U)
/*! GPIO7_CH1 - GPIO7 Channel 1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_GPIO7_CH1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_GPIO7_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_GPIO7_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_PINT0_INTR0_MASK     (0x800U)
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR0_SHIFT    (11U)
/*! PINT0_INTR0 - PINT0_INTR0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR0(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_PINT0_INTR0_SHIFT)) & SLEEPCON0_WAKEUPEN3_PINT0_INTR0_MASK)

#define SLEEPCON0_WAKEUPEN3_PINT0_INTR1_MASK     (0x1000U)
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR1_SHIFT    (12U)
/*! PINT0_INTR1 - PINT0_INTR1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR1(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_PINT0_INTR1_SHIFT)) & SLEEPCON0_WAKEUPEN3_PINT0_INTR1_MASK)

#define SLEEPCON0_WAKEUPEN3_PINT0_INTR2_MASK     (0x2000U)
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR2_SHIFT    (13U)
/*! PINT0_INTR2 - PINT0_INTR2 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR2(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_PINT0_INTR2_SHIFT)) & SLEEPCON0_WAKEUPEN3_PINT0_INTR2_MASK)

#define SLEEPCON0_WAKEUPEN3_PINT0_INTR3_MASK     (0x4000U)
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR3_SHIFT    (14U)
/*! PINT0_INTR3 - PINT0_INTR3 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR3(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_PINT0_INTR3_SHIFT)) & SLEEPCON0_WAKEUPEN3_PINT0_INTR3_MASK)

#define SLEEPCON0_WAKEUPEN3_PINT0_INTR4_MASK     (0x8000U)
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR4_SHIFT    (15U)
/*! PINT0_INTR4 - PINT0_INTR4 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR4(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_PINT0_INTR4_SHIFT)) & SLEEPCON0_WAKEUPEN3_PINT0_INTR4_MASK)

#define SLEEPCON0_WAKEUPEN3_PINT0_INTR5_MASK     (0x10000U)
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR5_SHIFT    (16U)
/*! PINT0_INTR5 - PINT0_INTR5 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR5(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_PINT0_INTR5_SHIFT)) & SLEEPCON0_WAKEUPEN3_PINT0_INTR5_MASK)

#define SLEEPCON0_WAKEUPEN3_PINT0_INTR6_MASK     (0x20000U)
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR6_SHIFT    (17U)
/*! PINT0_INTR6 - PINT0_INTR6 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR6(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_PINT0_INTR6_SHIFT)) & SLEEPCON0_WAKEUPEN3_PINT0_INTR6_MASK)

#define SLEEPCON0_WAKEUPEN3_PINT0_INTR7_MASK     (0x40000U)
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR7_SHIFT    (18U)
/*! PINT0_INTR7 - PINT0_INTR7 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_PINT0_INTR7(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_PINT0_INTR7_SHIFT)) & SLEEPCON0_WAKEUPEN3_PINT0_INTR7_MASK)

#define SLEEPCON0_WAKEUPEN3_SAI0_MASK            (0x80000U)
#define SLEEPCON0_WAKEUPEN3_SAI0_SHIFT           (19U)
/*! SAI0 - SAI0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_SAI0(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SAI0_SHIFT)) & SLEEPCON0_WAKEUPEN3_SAI0_MASK)

#define SLEEPCON0_WAKEUPEN3_SAI1_MASK            (0x100000U)
#define SLEEPCON0_WAKEUPEN3_SAI1_SHIFT           (20U)
/*! SAI1 - SAI1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_SAI1(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SAI1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SAI1_MASK)

#define SLEEPCON0_WAKEUPEN3_SAI2_MASK            (0x200000U)
#define SLEEPCON0_WAKEUPEN3_SAI2_SHIFT           (21U)
/*! SAI2 - SAI2 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN3_SAI2(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SAI2_SHIFT)) & SLEEPCON0_WAKEUPEN3_SAI2_MASK)
/*! @} */

/*! @name WAKEUPEN4 - Wakeup Enable 4 */
/*! @{ */

#define SLEEPCON0_WAKEUPEN4_ITRC_MASK            (0x10U)
#define SLEEPCON0_WAKEUPEN4_ITRC_SHIFT           (4U)
/*! ITRC - ITRC Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN4_ITRC(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_ITRC_SHIFT)) & SLEEPCON0_WAKEUPEN4_ITRC_MASK)

#define SLEEPCON0_WAKEUPEN4_PMC0_MASK            (0x400U)
#define SLEEPCON0_WAKEUPEN4_PMC0_SHIFT           (10U)
/*! PMC0 - PMC0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN4_PMC0(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_PMC0_SHIFT)) & SLEEPCON0_WAKEUPEN4_PMC0_MASK)

#define SLEEPCON0_WAKEUPEN4_FRO0_MASK            (0x4000000U)
#define SLEEPCON0_WAKEUPEN4_FRO0_SHIFT           (26U)
/*! FRO0 - FRO0 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN4_FRO0(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_FRO0_SHIFT)) & SLEEPCON0_WAKEUPEN4_FRO0_MASK)

#define SLEEPCON0_WAKEUPEN4_FRO1_MASK            (0x8000000U)
#define SLEEPCON0_WAKEUPEN4_FRO1_SHIFT           (27U)
/*! FRO1 - FRO1 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN4_FRO1(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_FRO1_SHIFT)) & SLEEPCON0_WAKEUPEN4_FRO1_MASK)

#define SLEEPCON0_WAKEUPEN4_FRO2_MASK            (0x10000000U)
#define SLEEPCON0_WAKEUPEN4_FRO2_SHIFT           (28U)
/*! FRO2 - FRO2 Wake-up Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_WAKEUPEN4_FRO2(x)              (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_FRO2_SHIFT)) & SLEEPCON0_WAKEUPEN4_FRO2_MASK)
/*! @} */

/*! @name WAKEUPEN0_SET - Wakeup Enable 0 Set */
/*! @{ */

#define SLEEPCON0_WAKEUPEN0_SET_UTICK0_MASK      (0x2U)
#define SLEEPCON0_WAKEUPEN0_SET_UTICK0_SHIFT     (1U)
/*! UTICK0 - UTICK0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_UTICK0(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_UTICK0_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_UTICK0_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_CTIMER0_MASK     (0x8U)
#define SLEEPCON0_WAKEUPEN0_SET_CTIMER0_SHIFT    (3U)
/*! CTIMER0 - CTIMER0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_CTIMER0(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_CTIMER0_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_CTIMER0_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_CTIMER1_MASK     (0x10U)
#define SLEEPCON0_WAKEUPEN0_SET_CTIMER1_SHIFT    (4U)
/*! CTIMER1 - CTIMER1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_CTIMER1(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_CTIMER1_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_CTIMER1_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_CTIMER3_MASK     (0x40U)
#define SLEEPCON0_WAKEUPEN0_SET_CTIMER3_SHIFT    (6U)
/*! CTIMER3 - CTIMER3 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_CTIMER3(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_CTIMER3_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_CTIMER3_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM0_MASK (0x80U)
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM0_SHIFT (7U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM0(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM0_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM0_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM1_MASK (0x100U)
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM1_SHIFT (8U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM1(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM1_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM1_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM2_MASK (0x200U)
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM2_SHIFT (9U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM2(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM2_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM2_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM3_MASK (0x400U)
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM3_SHIFT (10U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM3(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM3_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM3_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM4_MASK (0x800U)
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM4_SHIFT (11U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM4(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM4_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM4_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM5_MASK (0x1000U)
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM5_SHIFT (12U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM5(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM5_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_LP_FLEXCOMM5_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_LPSPI14_MASK     (0x2000U)
#define SLEEPCON0_WAKEUPEN0_SET_LPSPI14_SHIFT    (13U)
/*! LPSPI14 - LPSPI14 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_LPSPI14(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_LPSPI14_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_LPSPI14_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_LPI2C15_MASK     (0x4000U)
#define SLEEPCON0_WAKEUPEN0_SET_LPI2C15_SHIFT    (14U)
/*! LPI2C15 - LPI2C15 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_LPI2C15(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_LPI2C15_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_LPI2C15_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_ADC0_MASK        (0x8000U)
#define SLEEPCON0_WAKEUPEN0_SET_ADC0_SHIFT       (15U)
/*! ADC0 - ADC0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_ADC0_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_ADC0_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_ACMP0_MASK       (0x20000U)
#define SLEEPCON0_WAKEUPEN0_SET_ACMP0_SHIFT      (17U)
/*! ACMP0 - ACMP0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_ACMP0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_ACMP0_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_ACMP0_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_MICFIL_RD_ERR_MASK (0x40000U)
#define SLEEPCON0_WAKEUPEN0_SET_MICFIL_RD_ERR_SHIFT (18U)
/*! MICFIL_RD_ERR - MICFIL Read Data Error Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_MICFIL_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_MICFIL_RD_ERR_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_MICFIL_RD_ERR_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_MICFIL_WKUP_MASK (0x80000U)
#define SLEEPCON0_WAKEUPEN0_SET_MICFIL_WKUP_SHIFT (19U)
/*! MICFIL_WKUP - MICFIL Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_MICFIL_WKUP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_MICFIL_WKUP_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_MICFIL_WKUP_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_RTC0_ALARM_MASK  (0x4000000U)
#define SLEEPCON0_WAKEUPEN0_SET_RTC0_ALARM_SHIFT (26U)
/*! RTC0_ALARM - RTC0_ALARM Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_RTC0_ALARM(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_RTC0_ALARM_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_RTC0_ALARM_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_RTC0_WKUP_MASK   (0x8000000U)
#define SLEEPCON0_WAKEUPEN0_SET_RTC0_WKUP_SHIFT  (27U)
/*! RTC0_WKUP - RTC0_WKUP Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_RTC0_WKUP(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_RTC0_WKUP_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_RTC0_WKUP_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_MU0_MUA_MASK     (0x20000000U)
#define SLEEPCON0_WAKEUPEN0_SET_MU0_MUA_SHIFT    (29U)
/*! MU0_MUA - MU0_MUA Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_MU0_MUA(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_MU0_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_MU0_MUA_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_MU1_MUA_MASK     (0x40000000U)
#define SLEEPCON0_WAKEUPEN0_SET_MU1_MUA_SHIFT    (30U)
/*! MU1_MUA - MU1_MUA Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_MU1_MUA(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_MU1_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_MU1_MUA_MASK)

#define SLEEPCON0_WAKEUPEN0_SET_MU4_MUA_MASK     (0x80000000U)
#define SLEEPCON0_WAKEUPEN0_SET_MU4_MUA_SHIFT    (31U)
/*! MU4_MUA - MU4_MUA Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN0_SET_MU4_MUA(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_SET_MU4_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_SET_MU4_MUA_MASK)
/*! @} */

/*! @name WAKEUPEN1_SET - Wakeup Enable 1 Set */
/*! @{ */

#define SLEEPCON0_WAKEUPEN1_SET_CTIMER2_MASK     (0x1U)
#define SLEEPCON0_WAKEUPEN1_SET_CTIMER2_SHIFT    (0U)
/*! CTIMER2 - CTIMER2 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_CTIMER2(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_CTIMER2_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_CTIMER2_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_CTIMER4_MASK     (0x2U)
#define SLEEPCON0_WAKEUPEN1_SET_CTIMER4_SHIFT    (1U)
/*! CTIMER4 - CTIMER4 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_CTIMER4(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_CTIMER4_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_CTIMER4_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_OSTIMER_MASK     (0x4U)
#define SLEEPCON0_WAKEUPEN1_SET_OSTIMER_SHIFT    (2U)
/*! OSTIMER - OSTIMER Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_OSTIMER(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_OSTIMER_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_OSTIMER_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM6_MASK (0x8U)
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM6_SHIFT (3U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM6(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM6_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM6_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM7_MASK (0x10U)
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM7_SHIFT (4U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM7(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM7_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM7_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_I3C0_MASK        (0x80U)
#define SLEEPCON0_WAKEUPEN1_SET_I3C0_SHIFT       (7U)
/*! I3C0 - I3C0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_I3C0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_I3C0_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_I3C0_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_USB0_MASK        (0x100U)
#define SLEEPCON0_WAKEUPEN1_SET_USB0_SHIFT       (8U)
/*! USB0 - USB0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_USB0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_USB0_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_USB0_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_USB1_MASK        (0x200U)
#define SLEEPCON0_WAKEUPEN1_SET_USB1_SHIFT       (9U)
/*! USB1 - USB1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_USB1(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_USB1_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_USB1_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_WWDT0_MASK       (0x400U)
#define SLEEPCON0_WAKEUPEN1_SET_WWDT0_SHIFT      (10U)
/*! WWDT0 - WWDT0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_WWDT0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_WWDT0_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_WWDT0_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_WWDT1_MASK       (0x800U)
#define SLEEPCON0_WAKEUPEN1_SET_WWDT1_SHIFT      (11U)
/*! WWDT1 - WWDT1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_WWDT1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_WWDT1_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_WWDT1_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_USBPHY0_MASK     (0x1000U)
#define SLEEPCON0_WAKEUPEN1_SET_USBPHY0_SHIFT    (12U)
/*! USBPHY0 - USBPHY0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_USBPHY0(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_USBPHY0_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_USBPHY0_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_PMIC_IRQN_MASK   (0x4000U)
#define SLEEPCON0_WAKEUPEN1_SET_PMIC_IRQN_SHIFT  (14U)
/*! PMIC_IRQN - PMIC_IRQN Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_PMIC_IRQN(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_PMIC_IRQN_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_PMIC_IRQN_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM8_MASK (0x8000U)
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM8_SHIFT (15U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM8(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM8_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM8_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM9_MASK (0x10000U)
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM9_SHIFT (16U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM9(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM9_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM9_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM10_MASK (0x20000U)
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM10_SHIFT (17U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM10_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM10_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM11_MASK (0x40000U)
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM11_SHIFT (18U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM11_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM11_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM12_MASK (0x80000U)
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM12_SHIFT (19U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM12_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM12_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM13_MASK (0x100000U)
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM13_SHIFT (20U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM13_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LP_FLEXCOMM13_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_LPSPI16_MASK     (0x200000U)
#define SLEEPCON0_WAKEUPEN1_SET_LPSPI16_SHIFT    (21U)
/*! LPSPI16 - LPSPI16 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_LPSPI16(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_LPSPI16_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_LPSPI16_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_I3C1_MASK        (0x400000U)
#define SLEEPCON0_WAKEUPEN1_SET_I3C1_SHIFT       (22U)
/*! I3C1 - I3C1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_I3C1(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_I3C1_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_I3C1_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_FLEXIO_MASK      (0x800000U)
#define SLEEPCON0_WAKEUPEN1_SET_FLEXIO_SHIFT     (23U)
/*! FLEXIO - FLEXIO Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_FLEXIO(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_FLEXIO_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_FLEXIO_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH0_MASK   (0x8000000U)
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH0_SHIFT  (27U)
/*! EDMA0_CH0 - eDMA0 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH0_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH1_MASK   (0x10000000U)
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH1_SHIFT  (28U)
/*! EDMA0_CH1 - eDMA0 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH1_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH2_MASK   (0x20000000U)
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH2_SHIFT  (29U)
/*! EDMA0_CH2 - eDMA0 Channel 2 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH2(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH2_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH2_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH3_MASK   (0x40000000U)
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH3_SHIFT  (30U)
/*! EDMA0_CH3 - eDMA0 Channel 3 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH3(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH3_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH3_MASK)

#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH4_MASK   (0x80000000U)
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH4_SHIFT  (31U)
/*! EDMA0_CH4 - eDMA0 Channel 4 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH4(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH4_SHIFT)) & SLEEPCON0_WAKEUPEN1_SET_EDMA0_CH4_MASK)
/*! @} */

/*! @name WAKEUPEN2_SET - Wakeup Enable 2 Set */
/*! @{ */

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH5_MASK   (0x1U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH5_SHIFT  (0U)
/*! EDMA0_CH5 - eDMA0 Channel 5 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH5(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH5_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH5_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH6_MASK   (0x2U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH6_SHIFT  (1U)
/*! EDMA0_CH6 - eDMA0 Channel 6 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH6(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH6_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH6_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH7_MASK   (0x4U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH7_SHIFT  (2U)
/*! EDMA0_CH7 - eDMA0 Channel 7 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH7(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH7_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH7_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH8_MASK   (0x8U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH8_SHIFT  (3U)
/*! EDMA0_CH8 - eDMA0 Channel 8 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH8(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH8_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH8_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH9_MASK   (0x10U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH9_SHIFT  (4U)
/*! EDMA0_CH9 - eDMA0 Channel 9 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH9(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH9_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH9_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH10_MASK  (0x20U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH10_SHIFT (5U)
/*! EDMA0_CH10 - eDMA0 Channel 10 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH10(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH10_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH10_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH11_MASK  (0x40U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH11_SHIFT (6U)
/*! EDMA0_CH11 - eDMA0 Channel 11 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH11(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH11_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH11_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH12_MASK  (0x80U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH12_SHIFT (7U)
/*! EDMA0_CH12 - eDMA0 Channel 12 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH12(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH12_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH12_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH13_MASK  (0x100U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH13_SHIFT (8U)
/*! EDMA0_CH13 - eDMA0 Channel 13 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH13(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH13_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH13_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH14_MASK  (0x200U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH14_SHIFT (9U)
/*! EDMA0_CH14 - eDMA0 Channel 14 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH14(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH14_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH14_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH15_MASK  (0x400U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH15_SHIFT (10U)
/*! EDMA0_CH15 - eDMA0 Channel 15 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH15(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH15_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA0_CH15_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH0_MASK   (0x800U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH0_SHIFT  (11U)
/*! EDMA1_CH0 - eDMA1 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH1_MASK   (0x1000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH1_SHIFT  (12U)
/*! EDMA1_CH1 - eDMA1 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH2_MASK   (0x2000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH2_SHIFT  (13U)
/*! EDMA1_CH2 - eDMA1 Channel 2 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH2(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH2_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH2_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH3_MASK   (0x4000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH3_SHIFT  (14U)
/*! EDMA1_CH3 - eDMA1 Channel 3 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH3(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH3_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH3_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH4_MASK   (0x8000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH4_SHIFT  (15U)
/*! EDMA1_CH4 - eDMA1 Channel 4 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH4(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH4_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH4_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH5_MASK   (0x10000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH5_SHIFT  (16U)
/*! EDMA1_CH5 - eDMA1 Channel 5 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH5(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH5_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH5_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH6_MASK   (0x20000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH6_SHIFT  (17U)
/*! EDMA1_CH6 - eDMA1 Channel 6 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH6(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH6_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH6_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH7_MASK   (0x40000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH7_SHIFT  (18U)
/*! EDMA1_CH7 - eDMA1 Channel 7 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH7(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH7_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH7_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH8_MASK   (0x80000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH8_SHIFT  (19U)
/*! EDMA1_CH8 - eDMA1 Channel 8 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH8(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH8_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH8_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH9_MASK   (0x100000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH9_SHIFT  (20U)
/*! EDMA1_CH9 - eDMA1 Channel 9 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH9(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH9_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH9_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH10_MASK  (0x200000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH10_SHIFT (21U)
/*! EDMA1_CH10 - eDMA1 Channel 10 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH10(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH10_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH10_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH11_MASK  (0x400000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH11_SHIFT (22U)
/*! EDMA1_CH11 - eDMA1 Channel 11 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH11(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH11_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH11_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH12_MASK  (0x800000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH12_SHIFT (23U)
/*! EDMA1_CH12 - eDMA1 Channel 12 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH12(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH12_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH12_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH13_MASK  (0x1000000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH13_SHIFT (24U)
/*! EDMA1_CH13 - eDMA1 Channel 13 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH13(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH13_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH13_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH14_MASK  (0x2000000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH14_SHIFT (25U)
/*! EDMA1_CH14 - eDMA1 Channel 14 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH14(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH14_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH14_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH15_MASK  (0x4000000U)
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH15_SHIFT (26U)
/*! EDMA1_CH15 - eDMA1 Channel 15 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH15(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH15_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_EDMA1_CH15_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH0_MASK   (0x8000000U)
#define SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH0_SHIFT  (27U)
/*! GPIO0_CH0 - GPIO0 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH1_MASK   (0x10000000U)
#define SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH1_SHIFT  (28U)
/*! GPIO0_CH1 - GPIO0 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_GPIO0_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH0_MASK   (0x20000000U)
#define SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH0_SHIFT  (29U)
/*! GPIO1_CH0 - GPIO1 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH1_MASK   (0x40000000U)
#define SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH1_SHIFT  (30U)
/*! GPIO1_CH1 - GPIO1 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_GPIO1_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_SET_GPIO2_CH0_MASK   (0x80000000U)
#define SLEEPCON0_WAKEUPEN2_SET_GPIO2_CH0_SHIFT  (31U)
/*! GPIO2_CH0 - GPIO2 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN2_SET_GPIO2_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_SET_GPIO2_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_SET_GPIO2_CH0_MASK)
/*! @} */

/*! @name WAKEUPEN3_SET - Wakeup Enable 3 Set */
/*! @{ */

#define SLEEPCON0_WAKEUPEN3_SET_GPIO2_CH1_MASK   (0x1U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO2_CH1_SHIFT  (0U)
/*! GPIO2_CH1 - GPIO2 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO2_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO2_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO2_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH0_MASK   (0x2U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH0_SHIFT  (1U)
/*! GPIO3_CH0 - GPIO3 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH1_MASK   (0x4U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH1_SHIFT  (2U)
/*! GPIO3_CH1 - GPIO3 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO3_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH0_MASK   (0x8U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH0_SHIFT  (3U)
/*! GPIO4_CH0 - GPIO4 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH1_MASK   (0x10U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH1_SHIFT  (4U)
/*! GPIO4_CH1 - GPIO4 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO4_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH0_MASK   (0x20U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH0_SHIFT  (5U)
/*! GPIO5_CH0 - GPIO5 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH1_MASK   (0x40U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH1_SHIFT  (6U)
/*! GPIO5_CH1 - GPIO5 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO5_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH0_MASK   (0x80U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH0_SHIFT  (7U)
/*! GPIO6_CH0 - GPIO6 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH1_MASK   (0x100U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH1_SHIFT  (8U)
/*! GPIO6_CH1 - GPIO6 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO6_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH0_MASK   (0x200U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH0_SHIFT  (9U)
/*! GPIO7_CH0 - GPIO7 Channel 0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH1_MASK   (0x400U)
#define SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH1_SHIFT  (10U)
/*! GPIO7_CH1 - GPIO7 Channel 1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_GPIO7_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR0_MASK (0x800U)
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR0_SHIFT (11U)
/*! PINT0_INTR0 - PINT0_INTR0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR0(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR0_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR0_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR1_MASK (0x1000U)
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR1_SHIFT (12U)
/*! PINT0_INTR1 - PINT0_INTR1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR1(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR1_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR2_MASK (0x2000U)
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR2_SHIFT (13U)
/*! PINT0_INTR2 - PINT0_INTR2 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR2(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR2_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR2_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR3_MASK (0x4000U)
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR3_SHIFT (14U)
/*! PINT0_INTR3 - PINT0_INTR3 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR3(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR3_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR3_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR4_MASK (0x8000U)
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR4_SHIFT (15U)
/*! PINT0_INTR4 - PINT0_INTR4 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR4(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR4_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR4_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR5_MASK (0x10000U)
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR5_SHIFT (16U)
/*! PINT0_INTR5 - PINT0_INTR5 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR5(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR5_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR5_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR6_MASK (0x20000U)
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR6_SHIFT (17U)
/*! PINT0_INTR6 - PINT0_INTR6 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR6(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR6_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR6_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR7_MASK (0x40000U)
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR7_SHIFT (18U)
/*! PINT0_INTR7 - PINT0_INTR7 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR7(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR7_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_PINT0_INTR7_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_SAI0_MASK        (0x80000U)
#define SLEEPCON0_WAKEUPEN3_SET_SAI0_SHIFT       (19U)
/*! SAI0 - SAI0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_SAI0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_SAI0_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_SAI0_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_SAI1_MASK        (0x100000U)
#define SLEEPCON0_WAKEUPEN3_SET_SAI1_SHIFT       (20U)
/*! SAI1 - SAI1 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_SAI1(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_SAI1_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_SAI1_MASK)

#define SLEEPCON0_WAKEUPEN3_SET_SAI2_MASK        (0x200000U)
#define SLEEPCON0_WAKEUPEN3_SET_SAI2_SHIFT       (21U)
/*! SAI2 - SAI2 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN3_SET_SAI2(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_SET_SAI2_SHIFT)) & SLEEPCON0_WAKEUPEN3_SET_SAI2_MASK)
/*! @} */

/*! @name WAKEUPEN4_SET - Wakeup Enable 4 Set */
/*! @{ */

#define SLEEPCON0_WAKEUPEN4_SET_ITRC_MASK        (0x10U)
#define SLEEPCON0_WAKEUPEN4_SET_ITRC_SHIFT       (4U)
/*! ITRC - ITRC Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN4_SET_ITRC(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_SET_ITRC_SHIFT)) & SLEEPCON0_WAKEUPEN4_SET_ITRC_MASK)

#define SLEEPCON0_WAKEUPEN4_SET_PMC0_MASK        (0x400U)
#define SLEEPCON0_WAKEUPEN4_SET_PMC0_SHIFT       (10U)
/*! PMC0 - PMC0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN4_SET_PMC0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_SET_PMC0_SHIFT)) & SLEEPCON0_WAKEUPEN4_SET_PMC0_MASK)

#define SLEEPCON0_WAKEUPEN4_SET_FRO0_MASK        (0x4000000U)
#define SLEEPCON0_WAKEUPEN4_SET_FRO0_SHIFT       (26U)
/*! FRO0 - FRO0 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN4_SET_FRO0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_SET_FRO0_SHIFT)) & SLEEPCON0_WAKEUPEN4_SET_FRO0_MASK)

#define SLEEPCON0_WAKEUPEN4_SET_FRO1_MASK        (0x8000000U)
#define SLEEPCON0_WAKEUPEN4_SET_FRO1_SHIFT       (27U)
/*! FRO1 - FRO1 Wake-up Enable
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN4_SET_FRO1(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_SET_FRO1_SHIFT)) & SLEEPCON0_WAKEUPEN4_SET_FRO1_MASK)

#define SLEEPCON0_WAKEUPEN4_SET_FRO2_MASK        (0x10000000U)
#define SLEEPCON0_WAKEUPEN4_SET_FRO2_SHIFT       (28U)
/*! FRO2 - FRO2 Wake-up Enable Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_WAKEUPEN4_SET_FRO2(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_SET_FRO2_SHIFT)) & SLEEPCON0_WAKEUPEN4_SET_FRO2_MASK)
/*! @} */

/*! @name WAKEUPEN0_CLR - Wakeup Enable 0 Clear */
/*! @{ */

#define SLEEPCON0_WAKEUPEN0_CLR_UTICK0_MASK      (0x2U)
#define SLEEPCON0_WAKEUPEN0_CLR_UTICK0_SHIFT     (1U)
/*! UTICK0 - UTICK0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_UTICK0(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_UTICK0_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_UTICK0_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER0_MASK     (0x8U)
#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER0_SHIFT    (3U)
/*! CTIMER0 - CTIMER0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER0(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_CTIMER0_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_CTIMER0_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER1_MASK     (0x10U)
#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER1_SHIFT    (4U)
/*! CTIMER1 - CTIMER1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER1(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_CTIMER1_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_CTIMER1_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER3_MASK     (0x40U)
#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER3_SHIFT    (6U)
/*! CTIMER3 - CTIMER3 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_CTIMER3(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_CTIMER3_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_CTIMER3_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM0_MASK (0x80U)
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM0_SHIFT (7U)
/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM0(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM0_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM0_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM1_MASK (0x100U)
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM1_SHIFT (8U)
/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM1(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM1_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM1_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM2_MASK (0x200U)
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM2_SHIFT (9U)
/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM2(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM2_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM2_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM3_MASK (0x400U)
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM3_SHIFT (10U)
/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM3(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM3_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM3_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM4_MASK (0x800U)
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM4_SHIFT (11U)
/*! LP_FLEXCOMM4 - LP_FLEXCOMM4 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM4(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM4_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM4_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM5_MASK (0x1000U)
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM5_SHIFT (12U)
/*! LP_FLEXCOMM5 - LP_FLEXCOMM5 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM5(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM5_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_LP_FLEXCOMM5_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_LPSPI14_MASK     (0x2000U)
#define SLEEPCON0_WAKEUPEN0_CLR_LPSPI14_SHIFT    (13U)
/*! LPSPI14 - LPSPI14 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_LPSPI14(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_LPSPI14_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_LPSPI14_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_LPI2C15_MASK     (0x4000U)
#define SLEEPCON0_WAKEUPEN0_CLR_LPI2C15_SHIFT    (14U)
/*! LPI2C15 - LPI2C15 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_LPI2C15(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_LPI2C15_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_LPI2C15_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_ADC0_MASK        (0x8000U)
#define SLEEPCON0_WAKEUPEN0_CLR_ADC0_SHIFT       (15U)
/*! ADC0 - ADC0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_ADC0_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_ADC0_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_ACMP0_MASK       (0x20000U)
#define SLEEPCON0_WAKEUPEN0_CLR_ACMP0_SHIFT      (17U)
/*! ACMP0 - ACMP0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_ACMP0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_ACMP0_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_ACMP0_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_MICFIL_RD_ERR_MASK (0x40000U)
#define SLEEPCON0_WAKEUPEN0_CLR_MICFIL_RD_ERR_SHIFT (18U)
/*! MICFIL_RD_ERR - MICFIL Read Data Error Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_MICFIL_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_MICFIL_RD_ERR_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_MICFIL_RD_ERR_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_MICFIL_WKUP_MASK (0x80000U)
#define SLEEPCON0_WAKEUPEN0_CLR_MICFIL_WKUP_SHIFT (19U)
/*! MICFIL_WKUP - MICFIL Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_MICFIL_WKUP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_MICFIL_WKUP_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_MICFIL_WKUP_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_RTC0_ALARM_MASK  (0x4000000U)
#define SLEEPCON0_WAKEUPEN0_CLR_RTC0_ALARM_SHIFT (26U)
/*! RTC0_ALARM - RTC0_ALARM Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_RTC0_ALARM(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_RTC0_ALARM_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_RTC0_ALARM_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_RTC0_WKUP_MASK   (0x8000000U)
#define SLEEPCON0_WAKEUPEN0_CLR_RTC0_WKUP_SHIFT  (27U)
/*! RTC0_WKUP - RTC0_WKUP Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_RTC0_WKUP(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_RTC0_WKUP_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_RTC0_WKUP_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_MU0_MUA_MASK     (0x20000000U)
#define SLEEPCON0_WAKEUPEN0_CLR_MU0_MUA_SHIFT    (29U)
/*! MU0_MUA - MU0_MUA Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_MU0_MUA(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_MU0_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_MU0_MUA_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_MU1_MUA_MASK     (0x40000000U)
#define SLEEPCON0_WAKEUPEN0_CLR_MU1_MUA_SHIFT    (30U)
/*! MU1_MUA - MU1_MUA Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_MU1_MUA(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_MU1_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_MU1_MUA_MASK)

#define SLEEPCON0_WAKEUPEN0_CLR_MU4_MUA_MASK     (0x80000000U)
#define SLEEPCON0_WAKEUPEN0_CLR_MU4_MUA_SHIFT    (31U)
/*! MU4_MUA - MU4 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN0_CLR_MU4_MUA(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN0_CLR_MU4_MUA_SHIFT)) & SLEEPCON0_WAKEUPEN0_CLR_MU4_MUA_MASK)
/*! @} */

/*! @name WAKEUPEN1_CLR - Wakeup Enable 1 Clear */
/*! @{ */

#define SLEEPCON0_WAKEUPEN1_CLR_CTIMER2_MASK     (0x1U)
#define SLEEPCON0_WAKEUPEN1_CLR_CTIMER2_SHIFT    (0U)
/*! CTIMER2 - CTIMER2 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_CTIMER2(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_CTIMER2_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_CTIMER2_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_CTIMER4_MASK     (0x2U)
#define SLEEPCON0_WAKEUPEN1_CLR_CTIMER4_SHIFT    (1U)
/*! CTIMER4 - CTIMER4 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_CTIMER4(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_CTIMER4_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_CTIMER4_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_OSTIMER_MASK     (0x4U)
#define SLEEPCON0_WAKEUPEN1_CLR_OSTIMER_SHIFT    (2U)
/*! OSTIMER - OSTIMER Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_OSTIMER(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_OSTIMER_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_OSTIMER_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM6_MASK (0x8U)
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM6_SHIFT (3U)
/*! LP_FLEXCOMM6 - LP_FLEXCOMM6 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM6(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM6_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM6_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM7_MASK (0x10U)
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM7_SHIFT (4U)
/*! LP_FLEXCOMM7 - LP_FLEXCOMM7 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM7(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM7_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM7_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_I3C0_MASK        (0x80U)
#define SLEEPCON0_WAKEUPEN1_CLR_I3C0_SHIFT       (7U)
/*! I3C0 - I3C0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_I3C0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_I3C0_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_I3C0_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_USB0_MASK        (0x100U)
#define SLEEPCON0_WAKEUPEN1_CLR_USB0_SHIFT       (8U)
/*! USB0 - USB0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_USB0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_USB0_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_USB0_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_USB1_MASK        (0x200U)
#define SLEEPCON0_WAKEUPEN1_CLR_USB1_SHIFT       (9U)
/*! USB1 - USB1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_USB1(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_USB1_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_USB1_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_WWDT0_MASK       (0x400U)
#define SLEEPCON0_WAKEUPEN1_CLR_WWDT0_SHIFT      (10U)
/*! WWDT0 - WWDT0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_WWDT0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_WWDT0_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_WWDT0_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_WWDT1_MASK       (0x800U)
#define SLEEPCON0_WAKEUPEN1_CLR_WWDT1_SHIFT      (11U)
/*! WWDT1 - WWDT1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_WWDT1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_WWDT1_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_WWDT1_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_USBPHY0_MASK     (0x1000U)
#define SLEEPCON0_WAKEUPEN1_CLR_USBPHY0_SHIFT    (12U)
/*! USBPHY0 - USBPHY0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_USBPHY0(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_USBPHY0_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_USBPHY0_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_PMIC_IRQN_MASK   (0x4000U)
#define SLEEPCON0_WAKEUPEN1_CLR_PMIC_IRQN_SHIFT  (14U)
/*! PMIC_IRQN - PMIC_IRQN Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_PMIC_IRQN(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_PMIC_IRQN_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_PMIC_IRQN_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM8_MASK (0x8000U)
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM8_SHIFT (15U)
/*! LP_FLEXCOMM8 - LP_FLEXCOMM8 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM8(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM8_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM8_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM9_MASK (0x10000U)
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM9_SHIFT (16U)
/*! LP_FLEXCOMM9 - LP_FLEXCOMM9 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM9(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM9_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM9_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM10_MASK (0x20000U)
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM10_SHIFT (17U)
/*! LP_FLEXCOMM10 - LP_FLEXCOMM10 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM10_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM10_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM11_MASK (0x40000U)
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM11_SHIFT (18U)
/*! LP_FLEXCOMM11 - LP_FLEXCOMM11 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM11_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM11_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM12_MASK (0x80000U)
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM12_SHIFT (19U)
/*! LP_FLEXCOMM12 - LP_FLEXCOMM12 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM12_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM12_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM13_MASK (0x100000U)
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM13_SHIFT (20U)
/*! LP_FLEXCOMM13 - LP_FLEXCOMM13 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM13_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LP_FLEXCOMM13_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_LPSPI16_MASK     (0x200000U)
#define SLEEPCON0_WAKEUPEN1_CLR_LPSPI16_SHIFT    (21U)
/*! LPSPI16 - LPSPI16 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_LPSPI16(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_LPSPI16_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_LPSPI16_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_I3C1_MASK        (0x400000U)
#define SLEEPCON0_WAKEUPEN1_CLR_I3C1_SHIFT       (22U)
/*! I3C1 - I3C1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_I3C1(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_I3C1_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_I3C1_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_FLEXIO_MASK      (0x800000U)
#define SLEEPCON0_WAKEUPEN1_CLR_FLEXIO_SHIFT     (23U)
/*! FLEXIO - FLEXIO Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_FLEXIO(x)        (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_FLEXIO_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_FLEXIO_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH0_MASK   (0x8000000U)
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH0_SHIFT  (27U)
/*! EDMA0_CH0 - eDMA0 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH0_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH1_MASK   (0x10000000U)
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH1_SHIFT  (28U)
/*! EDMA0_CH1 - eDMA0 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH1_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH2_MASK   (0x20000000U)
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH2_SHIFT  (29U)
/*! EDMA0_CH2 - eDMA0 Channel 2 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH2(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH2_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH2_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH3_MASK   (0x40000000U)
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH3_SHIFT  (30U)
/*! EDMA0_CH3 - eDMA0 Channel 3 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH3(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH3_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH3_MASK)

#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH4_MASK   (0x80000000U)
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH4_SHIFT  (31U)
/*! EDMA0_CH4 - eDMA0 Channel 4 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH4(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH4_SHIFT)) & SLEEPCON0_WAKEUPEN1_CLR_EDMA0_CH4_MASK)
/*! @} */

/*! @name WAKEUPEN2_CLR - Wakeup Enable 2 Clear */
/*! @{ */

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH5_MASK   (0x1U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH5_SHIFT  (0U)
/*! EDMA0_CH5 - eDMA0 Channel 5 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH5(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH5_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH5_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH6_MASK   (0x2U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH6_SHIFT  (1U)
/*! EDMA0_CH6 - eDMA0 Channel 6 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH6(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH6_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH6_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH7_MASK   (0x4U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH7_SHIFT  (2U)
/*! EDMA0_CH7 - eDMA0 Channel 7 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH7(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH7_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH7_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH8_MASK   (0x8U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH8_SHIFT  (3U)
/*! EDMA0_CH8 - eDMA0 Channel 8 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH8(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH8_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH8_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH9_MASK   (0x10U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH9_SHIFT  (4U)
/*! EDMA0_CH9 - eDMA0 Channel 9 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH9(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH9_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH9_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH10_MASK  (0x20U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH10_SHIFT (5U)
/*! EDMA0_CH10 - eDMA0 Channel 10 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH10(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH10_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH10_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH11_MASK  (0x40U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH11_SHIFT (6U)
/*! EDMA0_CH11 - eDMA0 Channel 11 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH11(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH11_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH11_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH12_MASK  (0x80U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH12_SHIFT (7U)
/*! EDMA0_CH12 - eDMA0 Channel 12 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH12(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH12_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH12_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH13_MASK  (0x100U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH13_SHIFT (8U)
/*! EDMA0_CH13 - eDMA0 Channel 13 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH13(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH13_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH13_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH14_MASK  (0x200U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH14_SHIFT (9U)
/*! EDMA0_CH14 - eDMA0 Channel 14 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH14(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH14_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH14_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH15_MASK  (0x400U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH15_SHIFT (10U)
/*! EDMA0_CH15 - eDMA0 Channel 15 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH15(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH15_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA0_CH15_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH0_MASK   (0x800U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH0_SHIFT  (11U)
/*! EDMA1_CH0 - eDMA1 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH1_MASK   (0x1000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH1_SHIFT  (12U)
/*! EDMA1_CH1 - eDMA1 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH2_MASK   (0x2000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH2_SHIFT  (13U)
/*! EDMA1_CH2 - eDMA1 Channel 2 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH2(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH2_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH2_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH3_MASK   (0x4000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH3_SHIFT  (14U)
/*! EDMA1_CH3 - eDMA1 Channel 3 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH3(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH3_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH3_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH4_MASK   (0x8000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH4_SHIFT  (15U)
/*! EDMA1_CH4 - eDMA1 Channel 4 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH4(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH4_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH4_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH5_MASK   (0x10000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH5_SHIFT  (16U)
/*! EDMA1_CH5 - eDMA1 Channel 5 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH5(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH5_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH5_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH6_MASK   (0x20000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH6_SHIFT  (17U)
/*! EDMA1_CH6 - eDMA1 Channel 6 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH6(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH6_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH6_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH7_MASK   (0x40000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH7_SHIFT  (18U)
/*! EDMA1_CH7 - eDMA1 Channel 7 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH7(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH7_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH7_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH8_MASK   (0x80000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH8_SHIFT  (19U)
/*! EDMA1_CH8 - eDMA1 Channel 8 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH8(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH8_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH8_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH9_MASK   (0x100000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH9_SHIFT  (20U)
/*! EDMA1_CH9 - eDMA1 Channel 9 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH9(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH9_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH9_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH10_MASK  (0x200000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH10_SHIFT (21U)
/*! EDMA1_CH10 - eDMA1 Channel 10 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH10(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH10_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH10_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH11_MASK  (0x400000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH11_SHIFT (22U)
/*! EDMA1_CH11 - eDMA1 Channel 11 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH11(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH11_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH11_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH12_MASK  (0x800000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH12_SHIFT (23U)
/*! EDMA1_CH12 - eDMA1 Channel 12 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH12(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH12_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH12_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH13_MASK  (0x1000000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH13_SHIFT (24U)
/*! EDMA1_CH13 - eDMA1 Channel 13 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH13(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH13_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH13_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH14_MASK  (0x2000000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH14_SHIFT (25U)
/*! EDMA1_CH14 - eDMA1 Channel 14 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH14(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH14_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH14_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH15_MASK  (0x4000000U)
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH15_SHIFT (26U)
/*! EDMA1_CH15 - eDMA1 Channel 15 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH15(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH15_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_EDMA1_CH15_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH0_MASK   (0x8000000U)
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH0_SHIFT  (27U)
/*! GPIO0_CH0 - GPIO0 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH1_MASK   (0x10000000U)
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH1_SHIFT  (28U)
/*! GPIO0_CH1 - GPIO0 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_GPIO0_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH0_MASK   (0x20000000U)
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH0_SHIFT  (29U)
/*! GPIO1_CH0 - GPIO1 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH0_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH1_MASK   (0x40000000U)
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH1_SHIFT  (30U)
/*! GPIO1_CH1 - GPIO1 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_GPIO1_CH1_MASK)

#define SLEEPCON0_WAKEUPEN2_CLR_GPIO2_CH0_MASK   (0x80000000U)
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO2_CH0_SHIFT  (31U)
/*! GPIO2_CH0 - GPIO2 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN2_CLR_GPIO2_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN2_CLR_GPIO2_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN2_CLR_GPIO2_CH0_MASK)
/*! @} */

/*! @name WAKEUPEN3_CLR - Wakeup Enable 3 Clear */
/*! @{ */

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO2_CH1_MASK   (0x1U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO2_CH1_SHIFT  (0U)
/*! GPIO2_CH1 - GPIO2 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO2_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO2_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO2_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH0_MASK   (0x2U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH0_SHIFT  (1U)
/*! GPIO3_CH0 - GPIO3 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH1_MASK   (0x4U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH1_SHIFT  (2U)
/*! GPIO3_CH1 - GPIO3 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO3_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH0_MASK   (0x8U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH0_SHIFT  (3U)
/*! GPIO4_CH0 - GPIO4 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH1_MASK   (0x10U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH1_SHIFT  (4U)
/*! GPIO4_CH1 - GPIO4 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO4_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH0_MASK   (0x20U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH0_SHIFT  (5U)
/*! GPIO5_CH0 - GPIO5 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH1_MASK   (0x40U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH1_SHIFT  (6U)
/*! GPIO5_CH1 - GPIO5 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO5_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH0_MASK   (0x80U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH0_SHIFT  (7U)
/*! GPIO6_CH0 - GPIO6 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH1_MASK   (0x100U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH1_SHIFT  (8U)
/*! GPIO6_CH1 - GPIO6 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO6_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH0_MASK   (0x200U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH0_SHIFT  (9U)
/*! GPIO7_CH0 - GPIO7 Channel 0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH0(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH0_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH0_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH1_MASK   (0x400U)
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH1_SHIFT  (10U)
/*! GPIO7_CH1 - GPIO7 Channel 1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH1(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH1_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_GPIO7_CH1_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR0_MASK (0x800U)
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR0_SHIFT (11U)
/*! PINT0_INTR0 - PINT0_INTR0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR0(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR0_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR0_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR1_MASK (0x1000U)
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR1_SHIFT (12U)
/*! PINT0_INTR1 - PINT0_INTR1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR1(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR1_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR1_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR2_MASK (0x2000U)
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR2_SHIFT (13U)
/*! PINT0_INTR2 - PINT0_INTR2 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR2(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR2_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR2_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR3_MASK (0x4000U)
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR3_SHIFT (14U)
/*! PINT0_INTR3 - PINT0_INTR3 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR3(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR3_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR3_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR4_MASK (0x8000U)
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR4_SHIFT (15U)
/*! PINT0_INTR4 - PINT0_INTR4 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR4(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR4_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR4_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR5_MASK (0x10000U)
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR5_SHIFT (16U)
/*! PINT0_INTR5 - PINT0_INTR5 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR5(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR5_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR5_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR6_MASK (0x20000U)
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR6_SHIFT (17U)
/*! PINT0_INTR6 - PINT0_INTR6 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR6(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR6_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR6_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR7_MASK (0x40000U)
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR7_SHIFT (18U)
/*! PINT0_INTR7 - PINT0_INTR7 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR7(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR7_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_PINT0_INTR7_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_SAI0_MASK        (0x80000U)
#define SLEEPCON0_WAKEUPEN3_CLR_SAI0_SHIFT       (19U)
/*! SAI0 - SAI0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_SAI0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_SAI0_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_SAI0_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_SAI1_MASK        (0x100000U)
#define SLEEPCON0_WAKEUPEN3_CLR_SAI1_SHIFT       (20U)
/*! SAI1 - SAI1 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_SAI1(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_SAI1_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_SAI1_MASK)

#define SLEEPCON0_WAKEUPEN3_CLR_SAI2_MASK        (0x200000U)
#define SLEEPCON0_WAKEUPEN3_CLR_SAI2_SHIFT       (21U)
/*! SAI2 - SAI2 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN3_CLR_SAI2(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN3_CLR_SAI2_SHIFT)) & SLEEPCON0_WAKEUPEN3_CLR_SAI2_MASK)
/*! @} */

/*! @name WAKEUPEN4_CLR - Wakeup Enable 4 Clear */
/*! @{ */

#define SLEEPCON0_WAKEUPEN4_CLR_ITRC_MASK        (0x10U)
#define SLEEPCON0_WAKEUPEN4_CLR_ITRC_SHIFT       (4U)
/*! ITRC - ITRC Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN4_CLR_ITRC(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_CLR_ITRC_SHIFT)) & SLEEPCON0_WAKEUPEN4_CLR_ITRC_MASK)

#define SLEEPCON0_WAKEUPEN4_CLR_PMC0_MASK        (0x400U)
#define SLEEPCON0_WAKEUPEN4_CLR_PMC0_SHIFT       (10U)
/*! PMC0 - PMC0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN4_CLR_PMC0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_CLR_PMC0_SHIFT)) & SLEEPCON0_WAKEUPEN4_CLR_PMC0_MASK)

#define SLEEPCON0_WAKEUPEN4_CLR_FRO0_MASK        (0x4000000U)
#define SLEEPCON0_WAKEUPEN4_CLR_FRO0_SHIFT       (26U)
/*! FRO0 - FRO0 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN4_CLR_FRO0(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_CLR_FRO0_SHIFT)) & SLEEPCON0_WAKEUPEN4_CLR_FRO0_MASK)

#define SLEEPCON0_WAKEUPEN4_CLR_FRO1_MASK        (0x8000000U)
#define SLEEPCON0_WAKEUPEN4_CLR_FRO1_SHIFT       (27U)
/*! FRO1 - FRO1 Wake-up Enable
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN4_CLR_FRO1(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_CLR_FRO1_SHIFT)) & SLEEPCON0_WAKEUPEN4_CLR_FRO1_MASK)

#define SLEEPCON0_WAKEUPEN4_CLR_FRO2_MASK        (0x10000000U)
#define SLEEPCON0_WAKEUPEN4_CLR_FRO2_SHIFT       (28U)
/*! FRO2 - FRO2 Wake-up Enable Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_WAKEUPEN4_CLR_FRO2(x)          (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_WAKEUPEN4_CLR_FRO2_SHIFT)) & SLEEPCON0_WAKEUPEN4_CLR_FRO2_MASK)
/*! @} */

/*! @name PWRDOWN_WAIT - Power Down Wait */
/*! @{ */

#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO0PDR_MASK  (0x1U)
#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO0PDR_SHIFT (0U)
/*! IGN_FRO0PDR - Ignore FRO0 Power Down Ready Signal
 *  0b0..Waits
 *  0b1..Ignores
 */
#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO0PDR(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PWRDOWN_WAIT_IGN_FRO0PDR_SHIFT)) & SLEEPCON0_PWRDOWN_WAIT_IGN_FRO0PDR_MASK)

#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO1PDR_MASK  (0x2U)
#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO1PDR_SHIFT (1U)
/*! IGN_FRO1PDR - Ignore FRO1 Power Down Ready Signals
 *  0b0..Waits
 *  0b1..Ignores
 */
#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO1PDR(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PWRDOWN_WAIT_IGN_FRO1PDR_SHIFT)) & SLEEPCON0_PWRDOWN_WAIT_IGN_FRO1PDR_MASK)

#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO2PDR_MASK  (0x4U)
#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO2PDR_SHIFT (2U)
/*! IGN_FRO2PDR - Ignore FRO2 Power Down Ready Signals
 *  0b0..Waits
 *  0b1..Ignores
 */
#define SLEEPCON0_PWRDOWN_WAIT_IGN_FRO2PDR(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PWRDOWN_WAIT_IGN_FRO2PDR_SHIFT)) & SLEEPCON0_PWRDOWN_WAIT_IGN_FRO2PDR_MASK)

#define SLEEPCON0_PWRDOWN_WAIT_IGN_LPOSCPDR_MASK (0x8U)
#define SLEEPCON0_PWRDOWN_WAIT_IGN_LPOSCPDR_SHIFT (3U)
/*! IGN_LPOSCPDR - Ignore LPOSC Power Down Ready Signals
 *  0b0..Waits
 *  0b1..Ignores
 */
#define SLEEPCON0_PWRDOWN_WAIT_IGN_LPOSCPDR(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PWRDOWN_WAIT_IGN_LPOSCPDR_SHIFT)) & SLEEPCON0_PWRDOWN_WAIT_IGN_LPOSCPDR_MASK)
/*! @} */

/*! @name HW_WAKE - eDMA Wakeup Enable */
/*! @{ */

#define SLEEPCON0_HW_WAKE_HWWK_SRC0_MASK         (0x1U)
#define SLEEPCON0_HW_WAKE_HWWK_SRC0_SHIFT        (0U)
/*! HWWK_SRC0 - eDMA Wakeup Source 0
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_HW_WAKE_HWWK_SRC0(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_HWWK_SRC0_SHIFT)) & SLEEPCON0_HW_WAKE_HWWK_SRC0_MASK)

#define SLEEPCON0_HW_WAKE_HWWK_SRC1_MASK         (0x2U)
#define SLEEPCON0_HW_WAKE_HWWK_SRC1_SHIFT        (1U)
/*! HWWK_SRC1 - eDMA Wakeup Source 1
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_HW_WAKE_HWWK_SRC1(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_HWWK_SRC1_SHIFT)) & SLEEPCON0_HW_WAKE_HWWK_SRC1_MASK)

#define SLEEPCON0_HW_WAKE_HWWK_SRC2_MASK         (0x4U)
#define SLEEPCON0_HW_WAKE_HWWK_SRC2_SHIFT        (2U)
/*! HWWK_SRC2 - eDMA Wakeup Source 2
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_HW_WAKE_HWWK_SRC2(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_HWWK_SRC2_SHIFT)) & SLEEPCON0_HW_WAKE_HWWK_SRC2_MASK)

#define SLEEPCON0_HW_WAKE_HWWK_SRC3_MASK         (0x8U)
#define SLEEPCON0_HW_WAKE_HWWK_SRC3_SHIFT        (3U)
/*! HWWK_SRC3 - eDMA Wakeup source 3
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_HW_WAKE_HWWK_SRC3(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_HWWK_SRC3_SHIFT)) & SLEEPCON0_HW_WAKE_HWWK_SRC3_MASK)

#define SLEEPCON0_HW_WAKE_HWWK_SRC4_MASK         (0x10U)
#define SLEEPCON0_HW_WAKE_HWWK_SRC4_SHIFT        (4U)
/*! HWWK_SRC4 - eDMA Wakeup Source 4
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_HW_WAKE_HWWK_SRC4(x)           (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_HWWK_SRC4_SHIFT)) & SLEEPCON0_HW_WAKE_HWWK_SRC4_MASK)
/*! @} */

/*! @name HW_WAKE_SET - eDMA Wakeup Set */
/*! @{ */

#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC0_SET_MASK (0x1U)
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC0_SET_SHIFT (0U)
/*! HWWK_SRC0_SET - eDMA Wakeup Source 0 Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC0_SET(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_SET_HWWK_SRC0_SET_SHIFT)) & SLEEPCON0_HW_WAKE_SET_HWWK_SRC0_SET_MASK)

#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC1_SET_MASK (0x2U)
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC1_SET_SHIFT (1U)
/*! HWWK_SRC1_SET - eDMA Wakeup Source 1 Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC1_SET(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_SET_HWWK_SRC1_SET_SHIFT)) & SLEEPCON0_HW_WAKE_SET_HWWK_SRC1_SET_MASK)

#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC2_SET_MASK (0x4U)
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC2_SET_SHIFT (2U)
/*! HWWK_SRC2_SET - eDMA Wakeup Source 2 Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC2_SET(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_SET_HWWK_SRC2_SET_SHIFT)) & SLEEPCON0_HW_WAKE_SET_HWWK_SRC2_SET_MASK)

#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC3_SET_MASK (0x8U)
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC3_SET_SHIFT (3U)
/*! HWWK_SRC3_SET - eDMA Wakeup Source 3 Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC3_SET(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_SET_HWWK_SRC3_SET_SHIFT)) & SLEEPCON0_HW_WAKE_SET_HWWK_SRC3_SET_MASK)

#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC4_SET_MASK (0x10U)
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC4_SET_SHIFT (4U)
/*! HWWK_SRC4_SET - eDMA Wakeup Source 4 Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_HW_WAKE_SET_HWWK_SRC4_SET(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_SET_HWWK_SRC4_SET_SHIFT)) & SLEEPCON0_HW_WAKE_SET_HWWK_SRC4_SET_MASK)
/*! @} */

/*! @name HW_WAKE_CLR - eDMA Wakeup Clear */
/*! @{ */

#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC0_CLR_MASK (0x1U)
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC0_CLR_SHIFT (0U)
/*! HWWK_SRC0_CLR - eDMA Wakeup Source 0 Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC0_CLR(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_CLR_HWWK_SRC0_CLR_SHIFT)) & SLEEPCON0_HW_WAKE_CLR_HWWK_SRC0_CLR_MASK)

#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC1_CLR_MASK (0x2U)
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC1_CLR_SHIFT (1U)
/*! HWWK_SRC1_CLR - eDMA Wakeup Source 1 Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC1_CLR(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_CLR_HWWK_SRC1_CLR_SHIFT)) & SLEEPCON0_HW_WAKE_CLR_HWWK_SRC1_CLR_MASK)

#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC2_CLR_MASK (0x4U)
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC2_CLR_SHIFT (2U)
/*! HWWK_SRC2_CLR - eDMA Wakeup Source 2 Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC2_CLR(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_CLR_HWWK_SRC2_CLR_SHIFT)) & SLEEPCON0_HW_WAKE_CLR_HWWK_SRC2_CLR_MASK)

#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC3_CLR_MASK (0x8U)
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC3_CLR_SHIFT (3U)
/*! HWWK_SRC3_CLR - eDMA Wakeup Source 3 Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC3_CLR(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_CLR_HWWK_SRC3_CLR_SHIFT)) & SLEEPCON0_HW_WAKE_CLR_HWWK_SRC3_CLR_MASK)

#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC4_CLR_MASK (0x10U)
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC4_CLR_SHIFT (4U)
/*! HWWK_SRC4_CLR - eDMA Wakeup Source 4 Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_HW_WAKE_CLR_HWWK_SRC4_CLR(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_HW_WAKE_CLR_HWWK_SRC4_CLR_SHIFT)) & SLEEPCON0_HW_WAKE_CLR_HWWK_SRC4_CLR_MASK)
/*! @} */

/*! @name SHARED_MASK0 - Shared Resources Mask */
/*! @{ */

#define SLEEPCON0_SHARED_MASK0_ADC0_MASK_MASK    (0x1U)
#define SLEEPCON0_SHARED_MASK0_ADC0_MASK_SHIFT   (0U)
/*! ADC0_MASK - ADC0 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_ADC0_MASK(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_ADC0_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_ADC0_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_ACMP0_MASK_MASK   (0x2U)
#define SLEEPCON0_SHARED_MASK0_ACMP0_MASK_SHIFT  (1U)
/*! ACMP0_MASK - ACMP0 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_ACMP0_MASK(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_ACMP0_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_ACMP0_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_MICFIL_MASK_MASK  (0x4U)
#define SLEEPCON0_SHARED_MASK0_MICFIL_MASK_SHIFT (2U)
/*! MICFIL_MASK - MICFIL Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_MICFIL_MASK(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_MICFIL_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_MICFIL_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_LPI2C15_MASK_MASK (0x8U)
#define SLEEPCON0_SHARED_MASK0_LPI2C15_MASK_SHIFT (3U)
/*! LPI2C15_MASK - LPI2C15 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_LPI2C15_MASK(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_LPI2C15_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_LPI2C15_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_GDET2_MASK_MASK   (0x10U)
#define SLEEPCON0_SHARED_MASK0_GDET2_MASK_SHIFT  (4U)
/*! GDET2_MASK - GDET2 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_GDET2_MASK(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_GDET2_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_GDET2_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_GDET3_MASK_MASK   (0x20U)
#define SLEEPCON0_SHARED_MASK0_GDET3_MASK_SHIFT  (5U)
/*! GDET3_MASK - GDET3 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_GDET3_MASK(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_GDET3_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_GDET3_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_RTC_MASK_MASK     (0x40U)
#define SLEEPCON0_SHARED_MASK0_RTC_MASK_SHIFT    (6U)
/*! RTC_MASK - Mask bit of RTC0 and RTC1
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_RTC_MASK(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_RTC_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_RTC_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_VGPU_MASK_MASK    (0x10000U)
#define SLEEPCON0_SHARED_MASK0_VGPU_MASK_SHIFT   (16U)
/*! VGPU_MASK - VGPU Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_VGPU_MASK(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_VGPU_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_VGPU_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_EZHV_MASK_MASK    (0x20000U)
#define SLEEPCON0_SHARED_MASK0_EZHV_MASK_SHIFT   (17U)
/*! EZHV_MASK - EZH-V Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_EZHV_MASK(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_EZHV_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_EZHV_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_XSPI2_MASK_MASK   (0x40000U)
#define SLEEPCON0_SHARED_MASK0_XSPI2_MASK_SHIFT  (18U)
/*! XSPI2_MASK - XSPI2 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_XSPI2_MASK(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_XSPI2_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_XSPI2_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_LPSPI14_MASK_MASK (0x80000U)
#define SLEEPCON0_SHARED_MASK0_LPSPI14_MASK_SHIFT (19U)
/*! LPSPI14_MASK - LPSPI14 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_LPSPI14_MASK(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_LPSPI14_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_LPSPI14_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_LPSPI16_MASK_MASK (0x100000U)
#define SLEEPCON0_SHARED_MASK0_LPSPI16_MASK_SHIFT (20U)
/*! LPSPI16_MASK - LPSPI16 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_LPSPI16_MASK(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_LPSPI16_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_LPSPI16_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_FLEXIO_MASK_MASK  (0x200000U)
#define SLEEPCON0_SHARED_MASK0_FLEXIO_MASK_SHIFT (21U)
/*! FLEXIO_MASK - FLEXIO Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_FLEXIO_MASK(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_FLEXIO_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_FLEXIO_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_NIC0_MASK_MASK    (0x400000U)
#define SLEEPCON0_SHARED_MASK0_NIC0_MASK_SHIFT   (22U)
/*! NIC0_MASK - NIC_MEDIA0 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_NIC0_MASK(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_NIC0_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_NIC0_MASK_MASK)

#define SLEEPCON0_SHARED_MASK0_NIC1_MASK_MASK    (0x800000U)
#define SLEEPCON0_SHARED_MASK0_NIC1_MASK_SHIFT   (23U)
/*! NIC1_MASK - NIC_MEDIA1 Mask
 *  0b0..Disables
 *  0b1..Enables
 */
#define SLEEPCON0_SHARED_MASK0_NIC1_MASK(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_NIC1_MASK_SHIFT)) & SLEEPCON0_SHARED_MASK0_NIC1_MASK_MASK)
/*! @} */

/*! @name SHARED_MASK0_SET - Shared Resources Mask Set */
/*! @{ */

#define SLEEPCON0_SHARED_MASK0_SET_ADC0_MASK_SET_MASK (0x1U)
#define SLEEPCON0_SHARED_MASK0_SET_ADC0_MASK_SET_SHIFT (0U)
/*! ADC0_MASK_SET - ADC0 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_ADC0_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_ADC0_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_ADC0_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_ACMP0_MASK_SET_MASK (0x2U)
#define SLEEPCON0_SHARED_MASK0_SET_ACMP0_MASK_SET_SHIFT (1U)
/*! ACMP0_MASK_SET - ACMP0 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_ACMP0_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_ACMP0_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_ACMP0_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_MICFIL_MASK_SET_MASK (0x4U)
#define SLEEPCON0_SHARED_MASK0_SET_MICFIL_MASK_SET_SHIFT (2U)
/*! MICFIL_MASK_SET - MICFIL Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_MICFIL_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_MICFIL_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_MICFIL_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_LPI2C15_MASK_SET_MASK (0x8U)
#define SLEEPCON0_SHARED_MASK0_SET_LPI2C15_MASK_SET_SHIFT (3U)
/*! LPI2C15_MASK_SET - LPI2C15 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_LPI2C15_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_LPI2C15_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_LPI2C15_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_GDET2_MASK_SET_MASK (0x10U)
#define SLEEPCON0_SHARED_MASK0_SET_GDET2_MASK_SET_SHIFT (4U)
/*! GDET2_MASK_SET - GDET2 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_GDET2_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_GDET2_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_GDET2_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_GDET3_MASK_SET_MASK (0x20U)
#define SLEEPCON0_SHARED_MASK0_SET_GDET3_MASK_SET_SHIFT (5U)
/*! GDET3_MASK_SET - GDET3 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_GDET3_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_GDET3_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_GDET3_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_RTC_MASK_SET_MASK (0x40U)
#define SLEEPCON0_SHARED_MASK0_SET_RTC_MASK_SET_SHIFT (6U)
/*! RTC_MASK_SET - RTC0 and RTC1 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_RTC_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_RTC_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_RTC_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_VGPU_MASK_SET_MASK (0x10000U)
#define SLEEPCON0_SHARED_MASK0_SET_VGPU_MASK_SET_SHIFT (16U)
/*! VGPU_MASK_SET - VGPU Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_VGPU_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_VGPU_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_VGPU_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_EZHV_MASK_SET_MASK (0x20000U)
#define SLEEPCON0_SHARED_MASK0_SET_EZHV_MASK_SET_SHIFT (17U)
/*! EZHV_MASK_SET - EZH-V Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_EZHV_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_EZHV_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_EZHV_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_XSPI2_MASK_SET_MASK (0x40000U)
#define SLEEPCON0_SHARED_MASK0_SET_XSPI2_MASK_SET_SHIFT (18U)
/*! XSPI2_MASK_SET - XSPI2 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_XSPI2_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_XSPI2_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_XSPI2_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_LPSPI14_MASK_SET_MASK (0x80000U)
#define SLEEPCON0_SHARED_MASK0_SET_LPSPI14_MASK_SET_SHIFT (19U)
/*! LPSPI14_MASK_SET - LPSPI14 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_LPSPI14_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_LPSPI14_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_LPSPI14_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_LPSPI16_MASK_SET_MASK (0x100000U)
#define SLEEPCON0_SHARED_MASK0_SET_LPSPI16_MASK_SET_SHIFT (20U)
/*! LPSPI16_MASK_SET - LPSPI16 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_LPSPI16_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_LPSPI16_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_LPSPI16_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_FLEXIO_MASK_SET_MASK (0x200000U)
#define SLEEPCON0_SHARED_MASK0_SET_FLEXIO_MASK_SET_SHIFT (21U)
/*! FLEXIO_MASK_SET - FLEXIO Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_FLEXIO_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_FLEXIO_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_FLEXIO_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_NIC0_MASK_SET_MASK (0x400000U)
#define SLEEPCON0_SHARED_MASK0_SET_NIC0_MASK_SET_SHIFT (22U)
/*! NIC0_MASK_SET - NIC_MEDIA0 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_NIC0_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_NIC0_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_NIC0_MASK_SET_MASK)

#define SLEEPCON0_SHARED_MASK0_SET_NIC1_MASK_SET_MASK (0x800000U)
#define SLEEPCON0_SHARED_MASK0_SET_NIC1_MASK_SET_SHIFT (23U)
/*! NIC1_MASK_SET - NIC_MEDIA1 Mask Set
 *  0b0..No effect
 *  0b1..Sets the bit
 */
#define SLEEPCON0_SHARED_MASK0_SET_NIC1_MASK_SET(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_SET_NIC1_MASK_SET_SHIFT)) & SLEEPCON0_SHARED_MASK0_SET_NIC1_MASK_SET_MASK)
/*! @} */

/*! @name SHARED_MASK0_CLR - Shared Resources Mask Clear */
/*! @{ */

#define SLEEPCON0_SHARED_MASK0_CLR_ADC0_MASK_CLR_MASK (0x1U)
#define SLEEPCON0_SHARED_MASK0_CLR_ADC0_MASK_CLR_SHIFT (0U)
/*! ADC0_MASK_CLR - ADC0 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_ADC0_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_ADC0_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_ADC0_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_ACMP0_MASK_CLR_MASK (0x2U)
#define SLEEPCON0_SHARED_MASK0_CLR_ACMP0_MASK_CLR_SHIFT (1U)
/*! ACMP0_MASK_CLR - ACMP0 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_ACMP0_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_ACMP0_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_ACMP0_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_MICFIL_MASK_CLR_MASK (0x4U)
#define SLEEPCON0_SHARED_MASK0_CLR_MICFIL_MASK_CLR_SHIFT (2U)
/*! MICFIL_MASK_CLR - MICFIL Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_MICFIL_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_MICFIL_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_MICFIL_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_LPI2C15_MASK_CLR_MASK (0x8U)
#define SLEEPCON0_SHARED_MASK0_CLR_LPI2C15_MASK_CLR_SHIFT (3U)
/*! LPI2C15_MASK_CLR - LPI2C15 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_LPI2C15_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_LPI2C15_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_LPI2C15_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_GDET2_MASK_CLR_MASK (0x10U)
#define SLEEPCON0_SHARED_MASK0_CLR_GDET2_MASK_CLR_SHIFT (4U)
/*! GDET2_MASK_CLR - GDET2 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_GDET2_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_GDET2_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_GDET2_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_GDET3_MASK_CLR_MASK (0x20U)
#define SLEEPCON0_SHARED_MASK0_CLR_GDET3_MASK_CLR_SHIFT (5U)
/*! GDET3_MASK_CLR - GDET3 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_GDET3_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_GDET3_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_GDET3_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_RTC_MASK_CLR_MASK (0x40U)
#define SLEEPCON0_SHARED_MASK0_CLR_RTC_MASK_CLR_SHIFT (6U)
/*! RTC_MASK_CLR - RTC0 and RTC1 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_RTC_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_RTC_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_RTC_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_VGPU_MASK_CLR_MASK (0x10000U)
#define SLEEPCON0_SHARED_MASK0_CLR_VGPU_MASK_CLR_SHIFT (16U)
/*! VGPU_MASK_CLR - VGPU Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_VGPU_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_VGPU_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_VGPU_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_EZHV_MASK_CLR_MASK (0x20000U)
#define SLEEPCON0_SHARED_MASK0_CLR_EZHV_MASK_CLR_SHIFT (17U)
/*! EZHV_MASK_CLR - EZH-V Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_EZHV_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_EZHV_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_EZHV_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_XSPI2_MASK_CLR_MASK (0x40000U)
#define SLEEPCON0_SHARED_MASK0_CLR_XSPI2_MASK_CLR_SHIFT (18U)
/*! XSPI2_MASK_CLR - XSPI2 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_XSPI2_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_XSPI2_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_XSPI2_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_LPSPI14_MASK_CLR_MASK (0x80000U)
#define SLEEPCON0_SHARED_MASK0_CLR_LPSPI14_MASK_CLR_SHIFT (19U)
/*! LPSPI14_MASK_CLR - LPSPI14 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_LPSPI14_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_LPSPI14_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_LPSPI14_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_LPSPI16_MASK_CLR_MASK (0x100000U)
#define SLEEPCON0_SHARED_MASK0_CLR_LPSPI16_MASK_CLR_SHIFT (20U)
/*! LPSPI16_MASK_CLR - LPSPI16 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_LPSPI16_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_LPSPI16_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_LPSPI16_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_FLEXIO_MASK_CLR_MASK (0x200000U)
#define SLEEPCON0_SHARED_MASK0_CLR_FLEXIO_MASK_CLR_SHIFT (21U)
/*! FLEXIO_MASK_CLR - FLEXIO Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_FLEXIO_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_FLEXIO_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_FLEXIO_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_NIC0_MASK_CLR_MASK (0x400000U)
#define SLEEPCON0_SHARED_MASK0_CLR_NIC0_MASK_CLR_SHIFT (22U)
/*! NIC0_MASK_CLR - NIC_MEDIA0 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_NIC0_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_NIC0_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_NIC0_MASK_CLR_MASK)

#define SLEEPCON0_SHARED_MASK0_CLR_NIC1_MASK_CLR_MASK (0x800000U)
#define SLEEPCON0_SHARED_MASK0_CLR_NIC1_MASK_CLR_SHIFT (23U)
/*! NIC1_MASK_CLR - NIC_MEDIA1 Mask Clear
 *  0b0..No effect
 *  0b1..Clears the bit
 */
#define SLEEPCON0_SHARED_MASK0_CLR_NIC1_MASK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHARED_MASK0_CLR_NIC1_MASK_CLR_SHIFT)) & SLEEPCON0_SHARED_MASK0_CLR_NIC1_MASK_CLR_MASK)
/*! @} */

/*! @name SHA_MED_CCTRL0 - Media Domain Shared Controller Low-power Control */
/*! @{ */

#define SLEEPCON0_SHA_MED_CCTRL0_VGPU_LPREQ_MASK (0x1U)
#define SLEEPCON0_SHA_MED_CCTRL0_VGPU_LPREQ_SHIFT (0U)
/*! VGPU_LPREQ - VGPU Low-Power Control
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_CCTRL0_VGPU_LPREQ(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CCTRL0_VGPU_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_CCTRL0_VGPU_LPREQ_MASK)

#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_STOP_MASK  (0x2U)
#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_STOP_SHIFT (1U)
/*! EZHV_STOP - EZH-V Stop Control
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_STOP(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CCTRL0_EZHV_STOP_SHIFT)) & SLEEPCON0_SHA_MED_CCTRL0_EZHV_STOP_MASK)

#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_HALT_MASK  (0x4U)
#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_HALT_SHIFT (2U)
/*! EZHV_HALT - EZH-V Halt Control
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_HALT(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CCTRL0_EZHV_HALT_SHIFT)) & SLEEPCON0_SHA_MED_CCTRL0_EZHV_HALT_MASK)

#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_EXIT_WAIT_MASK (0x8U)
#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_EXIT_WAIT_SHIFT (3U)
/*! EZHV_EXIT_WAIT - EZH-V Exit Wait Mode
 *  0b0..No request
 *  0b1..Sends
 */
#define SLEEPCON0_SHA_MED_CCTRL0_EZHV_EXIT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CCTRL0_EZHV_EXIT_WAIT_SHIFT)) & SLEEPCON0_SHA_MED_CCTRL0_EZHV_EXIT_WAIT_MASK)
/*! @} */

/*! @name SHA_MED_TCTRL0 - Media Domain Shared Resources Target Low-power Control */
/*! @{ */

#define SLEEPCON0_SHA_MED_TCTRL0_XSPI2_STOP_MASK (0x1U)
#define SLEEPCON0_SHA_MED_TCTRL0_XSPI2_STOP_SHIFT (0U)
/*! XSPI2_STOP - XSPI2 Stop Control
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_XSPI2_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_XSPI2_STOP_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_XSPI2_STOP_MASK)

#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_B_LPREQ_MASK (0x8U)
#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_B_LPREQ_SHIFT (3U)
/*! LPSPI14_B_LPREQ - LPSPI14 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_B_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_B_LPREQ_MASK)

#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_F_LPREQ_MASK (0x10U)
#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_F_LPREQ_SHIFT (4U)
/*! LPSPI14_F_LPREQ - LPSPI14 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_F_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_LPSPI14_F_LPREQ_MASK)

#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_B_LPREQ_MASK (0x40U)
#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_B_LPREQ_SHIFT (6U)
/*! LPSPI16_B_LPREQ - LPSPI16 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_B_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_B_LPREQ_MASK)

#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_F_LPREQ_MASK (0x80U)
#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_F_LPREQ_SHIFT (7U)
/*! LPSPI16_F_LPREQ - LPSPI16 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_F_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_LPSPI16_F_LPREQ_MASK)

#define SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_B_LPREQ_MASK (0x200U)
#define SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_B_LPREQ_SHIFT (9U)
/*! FLEXIO_B_LPREQ - FLEXIO Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_B_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_B_LPREQ_MASK)

#define SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_F_LPREQ_MASK (0x400U)
#define SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_F_LPREQ_SHIFT (10U)
/*! FLEXIO_F_LPREQ - FLEXIO Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_F_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_FLEXIO_F_LPREQ_MASK)

#define SLEEPCON0_SHA_MED_TCTRL0_NIC0_LPREQ_MASK (0x800U)
#define SLEEPCON0_SHA_MED_TCTRL0_NIC0_LPREQ_SHIFT (11U)
/*! NIC0_LPREQ - NIC_MEDIA0 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_NIC0_LPREQ(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_NIC0_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_NIC0_LPREQ_MASK)

#define SLEEPCON0_SHA_MED_TCTRL0_NIC1_LPREQ_MASK (0x1000U)
#define SLEEPCON0_SHA_MED_TCTRL0_NIC1_LPREQ_SHIFT (12U)
/*! NIC1_LPREQ - NIC_MEDIA1 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_MED_TCTRL0_NIC1_LPREQ(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_TCTRL0_NIC1_LPREQ_SHIFT)) & SLEEPCON0_SHA_MED_TCTRL0_NIC1_LPREQ_MASK)
/*! @} */

/*! @name SHA_SEN_TCTRL0 - Shared VDD1_SENSE Domain Targets Low-power Control */
/*! @{ */

#define SLEEPCON0_SHA_SEN_TCTRL0_ADC0_STOP_MASK  (0x1U)
#define SLEEPCON0_SHA_SEN_TCTRL0_ADC0_STOP_SHIFT (0U)
/*! ADC0_STOP - ADC0 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_SEN_TCTRL0_ADC0_STOP(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_SEN_TCTRL0_ADC0_STOP_SHIFT)) & SLEEPCON0_SHA_SEN_TCTRL0_ADC0_STOP_MASK)

#define SLEEPCON0_SHA_SEN_TCTRL0_ACMP0_STOP_MASK (0x4U)
#define SLEEPCON0_SHA_SEN_TCTRL0_ACMP0_STOP_SHIFT (2U)
/*! ACMP0_STOP - ACMP0 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_SEN_TCTRL0_ACMP0_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_SEN_TCTRL0_ACMP0_STOP_SHIFT)) & SLEEPCON0_SHA_SEN_TCTRL0_ACMP0_STOP_MASK)

#define SLEEPCON0_SHA_SEN_TCTRL0_MICFIL_STOP_MASK (0x8U)
#define SLEEPCON0_SHA_SEN_TCTRL0_MICFIL_STOP_SHIFT (3U)
/*! MICFIL_STOP - MICFIL Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_SEN_TCTRL0_MICFIL_STOP(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_SEN_TCTRL0_MICFIL_STOP_SHIFT)) & SLEEPCON0_SHA_SEN_TCTRL0_MICFIL_STOP_MASK)

#define SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_B_LPREQ_MASK (0x20U)
#define SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_B_LPREQ_SHIFT (5U)
/*! LPI2C15_B_LPREQ - LPI2C15 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_B_LPREQ_SHIFT)) & SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_B_LPREQ_MASK)

#define SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_F_LPREQ_MASK (0x80U)
#define SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_F_LPREQ_SHIFT (7U)
/*! LPI2C15_F_LPREQ - LPI2C15 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_F_LPREQ_SHIFT)) & SLEEPCON0_SHA_SEN_TCTRL0_LPI2C15_F_LPREQ_MASK)

#define SLEEPCON0_SHA_SEN_TCTRL0_GDET2_LPREQ_MASK (0x100U)
#define SLEEPCON0_SHA_SEN_TCTRL0_GDET2_LPREQ_SHIFT (8U)
/*! GDET2_LPREQ - GDET2 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_SEN_TCTRL0_GDET2_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_SEN_TCTRL0_GDET2_LPREQ_SHIFT)) & SLEEPCON0_SHA_SEN_TCTRL0_GDET2_LPREQ_MASK)

#define SLEEPCON0_SHA_SEN_TCTRL0_GDET3_LPREQ_MASK (0x200U)
#define SLEEPCON0_SHA_SEN_TCTRL0_GDET3_LPREQ_SHIFT (9U)
/*! GDET3_LPREQ - GDET3 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_SEN_TCTRL0_GDET3_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_SEN_TCTRL0_GDET3_LPREQ_SHIFT)) & SLEEPCON0_SHA_SEN_TCTRL0_GDET3_LPREQ_MASK)

#define SLEEPCON0_SHA_SEN_TCTRL0_RTC_STOP_MASK   (0x80000000U)
#define SLEEPCON0_SHA_SEN_TCTRL0_RTC_STOP_SHIFT  (31U)
/*! RTC_STOP - RTC0 and RTC1 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_SHA_SEN_TCTRL0_RTC_STOP(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_SEN_TCTRL0_RTC_STOP_SHIFT)) & SLEEPCON0_SHA_SEN_TCTRL0_RTC_STOP_MASK)
/*! @} */

/*! @name PRIVATE_CCTRL0 - Private Resources Controllers Low-power Control 0 */
/*! @{ */

#define SLEEPCON0_PRIVATE_CCTRL0_EDMA0_STOP_MASK (0x1U)
#define SLEEPCON0_PRIVATE_CCTRL0_EDMA0_STOP_SHIFT (0U)
/*! EDMA0_STOP - eDMA0 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_CCTRL0_EDMA0_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_CCTRL0_EDMA0_STOP_SHIFT)) & SLEEPCON0_PRIVATE_CCTRL0_EDMA0_STOP_MASK)

#define SLEEPCON0_PRIVATE_CCTRL0_EDMA1_STOP_MASK (0x2U)
#define SLEEPCON0_PRIVATE_CCTRL0_EDMA1_STOP_SHIFT (1U)
/*! EDMA1_STOP - eDMA1 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_CCTRL0_EDMA1_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_CCTRL0_EDMA1_STOP_SHIFT)) & SLEEPCON0_PRIVATE_CCTRL0_EDMA1_STOP_MASK)
/*! @} */

/*! @name PRIVATE_TCTRL0 - Private Resources Targets Low-power Control 0 */
/*! @{ */

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM0_B_LPREQ_MASK (0x1U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM0_B_LPREQ_SHIFT (0U)
/*! LP_FLEXCOMM0_B_LPREQ - LP_FLEXCOMM0 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM0_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM0_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM0_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM1_B_LPREQ_MASK (0x2U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM1_B_LPREQ_SHIFT (1U)
/*! LP_FLEXCOMM1_B_LPREQ - LP_FLEXCOMM1 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM1_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM1_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM1_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM2_B_LPREQ_MASK (0x4U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM2_B_LPREQ_SHIFT (2U)
/*! LP_FLEXCOMM2_B_LPREQ - LP_FLEXCOMM2 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM2_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM2_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM2_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM3_B_LPREQ_MASK (0x8U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM3_B_LPREQ_SHIFT (3U)
/*! LP_FLEXCOMM3_B_LPREQ - LP_FLEXCOMM3 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM3_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM3_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM3_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM4_B_LPREQ_MASK (0x10U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM4_B_LPREQ_SHIFT (4U)
/*! LP_FLEXCOMM4_B_LPREQ - LP_FLEXCOMM4 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM4_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM4_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM4_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM5_B_LPREQ_MASK (0x20U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM5_B_LPREQ_SHIFT (5U)
/*! LP_FLEXCOMM5_B_LPREQ - LP_FLEXCOMM5 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM5_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM5_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM5_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM6_B_LPREQ_MASK (0x40U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM6_B_LPREQ_SHIFT (6U)
/*! LP_FLEXCOMM6_B_LPREQ - LP_FLEXCOMM6 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM6_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM6_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM6_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM7_B_LPREQ_MASK (0x80U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM7_B_LPREQ_SHIFT (7U)
/*! LP_FLEXCOMM7_B_LPREQ - LP_FLEXCOMM7 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM7_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM7_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM7_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM8_B_LPREQ_MASK (0x100U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM8_B_LPREQ_SHIFT (8U)
/*! LP_FLEXCOMM8_B_LPREQ - LP_FLEXCOMM8 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM8_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM8_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM8_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM9_B_LPREQ_MASK (0x200U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM9_B_LPREQ_SHIFT (9U)
/*! LP_FLEXCOMM9_B_LPREQ - LP_FLEXCOMM9 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM9_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM9_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM9_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM10_B_LPREQ_MASK (0x400U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM10_B_LPREQ_SHIFT (10U)
/*! LP_FLEXCOMM10_B_LPREQ - LP_FLEXCOMM10 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM10_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM10_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM10_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM11_B_LPREQ_MASK (0x800U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM11_B_LPREQ_SHIFT (11U)
/*! LP_FLEXCOMM11_B_LPREQ - LP_FLEXCOMM11 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM11_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM11_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM11_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM12_B_LPREQ_MASK (0x1000U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM12_B_LPREQ_SHIFT (12U)
/*! LP_FLEXCOMM12_B_LPREQ - LP_FLEXCOMM12 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM12_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM12_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM12_B_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM13_B_LPREQ_MASK (0x2000U)
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM13_B_LPREQ_SHIFT (13U)
/*! LP_FLEXCOMM13_B_LPREQ - LP_FLEXCOMM13 Bus Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM13_B_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM13_B_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL0_LP_FLEXCOMM13_B_LPREQ_MASK)
/*! @} */

/*! @name PRIVATE_TCTRL1 - Private Resources Targets Low-power Control 1 */
/*! @{ */

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM0_F_LPREQ_MASK (0x1U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM0_F_LPREQ_SHIFT (0U)
/*! LP_FLEXCOMM0_F_LPREQ - LP_FLEXCOMM0 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM0_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM0_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM0_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM1_F_LPREQ_MASK (0x2U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM1_F_LPREQ_SHIFT (1U)
/*! LP_FLEXCOMM1_F_LPREQ - LP_FLEXCOMM1 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM1_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM1_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM1_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM2_F_LPREQ_MASK (0x4U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM2_F_LPREQ_SHIFT (2U)
/*! LP_FLEXCOMM2_F_LPREQ - LP_FLEXCOMM2 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM2_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM2_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM2_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM3_F_LPREQ_MASK (0x8U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM3_F_LPREQ_SHIFT (3U)
/*! LP_FLEXCOMM3_F_LPREQ - LP_FLEXCOMM3 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM3_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM3_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM3_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM4_F_LPREQ_MASK (0x10U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM4_F_LPREQ_SHIFT (4U)
/*! LP_FLEXCOMM4_F_LPREQ - LP_FLEXCOMM4 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM4_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM4_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM4_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM5_F_LPREQ_MASK (0x20U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM5_F_LPREQ_SHIFT (5U)
/*! LP_FLEXCOMM5_F_LPREQ - LP_FLEXCOMM5 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM5_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM5_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM5_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM6_F_LPREQ_MASK (0x40U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM6_F_LPREQ_SHIFT (6U)
/*! LP_FLEXCOMM6_F_LPREQ - LP_FLEXCOMM6 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM6_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM6_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM6_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM7_F_LPREQ_MASK (0x80U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM7_F_LPREQ_SHIFT (7U)
/*! LP_FLEXCOMM7_F_LPREQ - LP_FLEXCOMM7 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM7_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM7_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM7_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM8_F_LPREQ_MASK (0x100U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM8_F_LPREQ_SHIFT (8U)
/*! LP_FLEXCOMM8_F_LPREQ - LP_FLEXCOMM8 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM8_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM8_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM8_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM9_F_LPREQ_MASK (0x200U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM9_F_LPREQ_SHIFT (9U)
/*! LP_FLEXCOMM9_F_LPREQ - LP_FLEXCOMM9 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM9_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM9_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM9_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM10_F_LPREQ_MASK (0x400U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM10_F_LPREQ_SHIFT (10U)
/*! LP_FLEXCOMM10_F_LPREQ - LP_FLEXCOMM10 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM10_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM10_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM10_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM11_F_LPREQ_MASK (0x800U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM11_F_LPREQ_SHIFT (11U)
/*! LP_FLEXCOMM11_F_LPREQ - LP_FLEXCOMM11 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM11_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM11_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM11_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM12_F_LPREQ_MASK (0x1000U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM12_F_LPREQ_SHIFT (12U)
/*! LP_FLEXCOMM12_F_LPREQ - LP_FLEXCOMM12 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM12_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM12_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM12_F_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM13_F_LPREQ_MASK (0x2000U)
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM13_F_LPREQ_SHIFT (13U)
/*! LP_FLEXCOMM13_F_LPREQ - LP_FLEXCOMM13 Function Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM13_F_LPREQ(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM13_F_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL1_LP_FLEXCOMM13_F_LPREQ_MASK)
/*! @} */

/*! @name PRIVATE_TCTRL2 - Private Resources Targets Low-power Control 2 */
/*! @{ */

#define SLEEPCON0_PRIVATE_TCTRL2_GPIO0_LPREQ_MASK (0x1U)
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO0_LPREQ_SHIFT (0U)
/*! GPIO0_LPREQ - GPIO0 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO0_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GPIO0_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GPIO0_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GPIO1_LPREQ_MASK (0x2U)
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO1_LPREQ_SHIFT (1U)
/*! GPIO1_LPREQ - GPIO1 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO1_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GPIO1_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GPIO1_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GPIO2_LPREQ_MASK (0x4U)
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO2_LPREQ_SHIFT (2U)
/*! GPIO2_LPREQ - GPIO2 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO2_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GPIO2_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GPIO2_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GPIO3_LPREQ_MASK (0x8U)
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO3_LPREQ_SHIFT (3U)
/*! GPIO3_LPREQ - GPIO3 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO3_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GPIO3_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GPIO3_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GPIO4_LPREQ_MASK (0x10U)
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO4_LPREQ_SHIFT (4U)
/*! GPIO4_LPREQ - GPIO4 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO4_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GPIO4_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GPIO4_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GPIO5_LPREQ_MASK (0x20U)
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO5_LPREQ_SHIFT (5U)
/*! GPIO5_LPREQ - GPIO5 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO5_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GPIO5_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GPIO5_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GPIO6_LPREQ_MASK (0x40U)
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO6_LPREQ_SHIFT (6U)
/*! GPIO6_LPREQ - GPIO6 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO6_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GPIO6_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GPIO6_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GPIO7_LPREQ_MASK (0x80U)
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO7_LPREQ_SHIFT (7U)
/*! GPIO7_LPREQ - GPIO7 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GPIO7_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GPIO7_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GPIO7_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_SAI0_LPREQ_MASK (0x100U)
#define SLEEPCON0_PRIVATE_TCTRL2_SAI0_LPREQ_SHIFT (8U)
/*! SAI0_LPREQ - SAI0 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_SAI0_LPREQ(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_SAI0_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_SAI0_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_SAI1_LPREQ_MASK (0x200U)
#define SLEEPCON0_PRIVATE_TCTRL2_SAI1_LPREQ_SHIFT (9U)
/*! SAI1_LPREQ - SAI1 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_SAI1_LPREQ(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_SAI1_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_SAI1_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_SAI2_LPREQ_MASK (0x400U)
#define SLEEPCON0_PRIVATE_TCTRL2_SAI2_LPREQ_SHIFT (10U)
/*! SAI2_LPREQ - SAI2 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_SAI2_LPREQ(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_SAI2_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_SAI2_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_TRNG_STOP_MASK  (0x800U)
#define SLEEPCON0_PRIVATE_TCTRL2_TRNG_STOP_SHIFT (11U)
/*! TRNG_STOP - TRNG Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_TRNG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_TRNG_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_TRNG_STOP_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_XSPI0_STOP_MASK (0x1000U)
#define SLEEPCON0_PRIVATE_TCTRL2_XSPI0_STOP_SHIFT (12U)
/*! XSPI0_STOP - XSPI0 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_XSPI0_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_XSPI0_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_XSPI0_STOP_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_XSPI1_STOP_MASK (0x4000U)
#define SLEEPCON0_PRIVATE_TCTRL2_XSPI1_STOP_SHIFT (14U)
/*! XSPI1_STOP - XSPI1 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_XSPI1_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_XSPI1_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_XSPI1_STOP_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_I3C0_STOP_MASK  (0x10000U)
#define SLEEPCON0_PRIVATE_TCTRL2_I3C0_STOP_SHIFT (16U)
/*! I3C0_STOP - I3C0 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_I3C0_STOP(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_I3C0_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_I3C0_STOP_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_I3C1_STOP_MASK  (0x20000U)
#define SLEEPCON0_PRIVATE_TCTRL2_I3C1_STOP_SHIFT (17U)
/*! I3C1_STOP - I3C1 Stop
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_I3C1_STOP(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_I3C1_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_I3C1_STOP_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GDET0_LPREQ_MASK (0x40000U)
#define SLEEPCON0_PRIVATE_TCTRL2_GDET0_LPREQ_SHIFT (18U)
/*! GDET0_LPREQ - GDET0 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GDET0_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GDET0_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GDET0_LPREQ_MASK)

#define SLEEPCON0_PRIVATE_TCTRL2_GDET1_LPREQ_MASK (0x80000U)
#define SLEEPCON0_PRIVATE_TCTRL2_GDET1_LPREQ_SHIFT (19U)
/*! GDET1_LPREQ - GDET1 Low-Power Request
 *  0b0..No request
 *  0b1..Sends request
 */
#define SLEEPCON0_PRIVATE_TCTRL2_GDET1_LPREQ(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TCTRL2_GDET1_LPREQ_SHIFT)) & SLEEPCON0_PRIVATE_TCTRL2_GDET1_LPREQ_MASK)
/*! @} */

/*! @name SHA_MED_CSTAT0 - Media Domain Shared Controllers Low-power Status */
/*! @{ */

#define SLEEPCON0_SHA_MED_CSTAT0_VGPU_LPACCEPT_MASK (0x1U)
#define SLEEPCON0_SHA_MED_CSTAT0_VGPU_LPACCEPT_SHIFT (0U)
/*! VGPU_LPACCEPT - VGPU Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MED_CSTAT0_VGPU_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CSTAT0_VGPU_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MED_CSTAT0_VGPU_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MED_CSTAT0_VGPU_IDLE_MASK  (0x2U)
#define SLEEPCON0_SHA_MED_CSTAT0_VGPU_IDLE_SHIFT (1U)
/*! VGPU_IDLE - VGPU Idle Status
 *  0b0..Not in Idle status, VGPU has operation to perform.
 *  0b1..In Idle status, VGPU might accept low-power request.
 */
#define SLEEPCON0_SHA_MED_CSTAT0_VGPU_IDLE(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CSTAT0_VGPU_IDLE_SHIFT)) & SLEEPCON0_SHA_MED_CSTAT0_VGPU_IDLE_MASK)

#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_STOPPED_MASK (0x4U)
#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_STOPPED_SHIFT (2U)
/*! EZHV_STOPPED - EZH-V Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CSTAT0_EZHV_STOPPED_SHIFT)) & SLEEPCON0_SHA_MED_CSTAT0_EZHV_STOPPED_MASK)

#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_HALTED_MASK (0x8U)
#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_HALTED_SHIFT (3U)
/*! EZHV_HALTED - EZH-V Halt Status
 *  0b0..Not in Halt status
 *  0b1..In Halt status
 */
#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_HALTED(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CSTAT0_EZHV_HALTED_SHIFT)) & SLEEPCON0_SHA_MED_CSTAT0_EZHV_HALTED_MASK)

#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAITING_MASK (0x10U)
#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAITING_SHIFT (4U)
/*! EZHV_WAITING - EZH-V Waiting Status
 *  0b0..Not in waiting status
 *  0b1..In waiting status
 */
#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAITING_SHIFT)) & SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAITING_MASK)

#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAKEUP_MASK (0x20U)
#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAKEUP_SHIFT (5U)
/*! EZHV_WAKEUP - Wakeup Request from EZH-V
 *  0b0..Not needs
 *  0b1..Needs
 */
#define SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAKEUP(x)  (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAKEUP_SHIFT)) & SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAKEUP_MASK)
/*! @} */

/*! @name SHA_MEDSEN_TSTAT0 - Media and Sense Domain Shared Targets Low-power Status */
/*! @{ */

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_XSPI2_STOP_MASK (0x1U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_XSPI2_STOP_SHIFT (0U)
/*! XSPI2_STOP - XSPI2 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_XSPI2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_XSPI2_STOP_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_XSPI2_STOP_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_B_LPACCEPT_MASK (0x2U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_B_LPACCEPT_SHIFT (1U)
/*! LPSPI14_B_LPACCEPT - LPSPI14 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_B_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_B_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_F_LPACCEPT_MASK (0x4U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_F_LPACCEPT_SHIFT (2U)
/*! LPSPI14_F_LPACCEPT - LPSPI14 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_F_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI14_F_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_B_LPACCEPT_MASK (0x8U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_B_LPACCEPT_SHIFT (3U)
/*! LPSPI16_B_LPACCEPT - LPSPI16 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_B_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_B_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_F_LPACCEPT_MASK (0x10U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_F_LPACCEPT_SHIFT (4U)
/*! LPSPI16_F_LPACCEPT - LPSPI16 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_F_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_LPSPI16_F_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_B_LPACCEPT_MASK (0x20U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_B_LPACCEPT_SHIFT (5U)
/*! FLEXIO_B_LPACCEPT - FLEXIO Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_B_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_B_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_F_LPACCEPT_MASK (0x40U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_F_LPACCEPT_SHIFT (6U)
/*! FLEXIO_F_LPACCEPT - FLEXIO Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_F_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_FLEXIO_F_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC0_LPACCEPT_MASK (0x80U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC0_LPACCEPT_SHIFT (7U)
/*! NIC0_LPACCEPT - NIC_MEDIA0 Accept Low-power Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC0_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC0_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC0_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC1_LPACCEPT_MASK (0x100U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC1_LPACCEPT_SHIFT (8U)
/*! NIC1_LPACCEPT - NIC_MEDIA1 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC1_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC1_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_NIC1_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_ADC0_STOP_MASK (0x10000U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_ADC0_STOP_SHIFT (16U)
/*! ADC0_STOP - ADC0 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_ADC0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_ADC0_STOP_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_ADC0_STOP_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_ACMP0_STOP_MASK (0x20000U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_ACMP0_STOP_SHIFT (17U)
/*! ACMP0_STOP - ACMP0 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_ACMP0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_ACMP0_STOP_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_ACMP0_STOP_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_MICFIL_STOPPED_MASK (0x40000U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_MICFIL_STOPPED_SHIFT (18U)
/*! MICFIL_STOPPED - MICFIL Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_MICFIL_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_MICFIL_STOPPED_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_MICFIL_STOPPED_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_B_LPACCEPT_MASK (0x80000U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_B_LPACCEPT_SHIFT (19U)
/*! LPI2C15_B_LPACCEPT - LPI2C15 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_B_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_B_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_F_LPACCEPT_MASK (0x100000U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_F_LPACCEPT_SHIFT (20U)
/*! LPI2C15_F_LPACCEPT - LPI2C15 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_F_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_LPI2C15_F_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET2_LPACCEPT_MASK (0x200000U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET2_LPACCEPT_SHIFT (21U)
/*! GDET2_LPACCEPT - GDET2 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET2_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET2_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET2_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET3_LPACCEPT_MASK (0x400000U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET3_LPACCEPT_SHIFT (22U)
/*! GDET3_LPACCEPT - GDET3 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET3_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET3_LPACCEPT_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_GDET3_LPACCEPT_MASK)

#define SLEEPCON0_SHA_MEDSEN_TSTAT0_RTC_STOPPED_MASK (0x80000000U)
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_RTC_STOPPED_SHIFT (31U)
/*! RTC_STOPPED - RTC0 and RTC1 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_SHA_MEDSEN_TSTAT0_RTC_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_SHA_MEDSEN_TSTAT0_RTC_STOPPED_SHIFT)) & SLEEPCON0_SHA_MEDSEN_TSTAT0_RTC_STOPPED_MASK)
/*! @} */

/*! @name PRIVATE_CSTAT0 - Private Resources Controller Low-power Status */
/*! @{ */

#define SLEEPCON0_PRIVATE_CSTAT0_EDMA0_STOP_MASK (0x1U)
#define SLEEPCON0_PRIVATE_CSTAT0_EDMA0_STOP_SHIFT (0U)
/*! EDMA0_STOP - eDMA0 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_PRIVATE_CSTAT0_EDMA0_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_CSTAT0_EDMA0_STOP_SHIFT)) & SLEEPCON0_PRIVATE_CSTAT0_EDMA0_STOP_MASK)

#define SLEEPCON0_PRIVATE_CSTAT0_EDMA1_STOP_MASK (0x2U)
#define SLEEPCON0_PRIVATE_CSTAT0_EDMA1_STOP_SHIFT (1U)
/*! EDMA1_STOP - eDMA1 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_PRIVATE_CSTAT0_EDMA1_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_CSTAT0_EDMA1_STOP_SHIFT)) & SLEEPCON0_PRIVATE_CSTAT0_EDMA1_STOP_MASK)
/*! @} */

/*! @name PRIVATE_TSTAT0 - Private Resources Targets Low-power Status 0 */
/*! @{ */

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_B_LPACCEPT_MASK (0x1U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_B_LPACCEPT_SHIFT (0U)
/*! LP_FLEXCOMM0_B_LPACCEPT - LP_FLEXCOMM0 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_B_LPACCEPT_MASK (0x2U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_B_LPACCEPT_SHIFT (1U)
/*! LP_FLEXCOMM1_B_LPACCEPT - LP_FLEXCOMM1 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_B_LPACCEPT_MASK (0x4U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_B_LPACCEPT_SHIFT (2U)
/*! LP_FLEXCOMM2_B_LPACCEPT - LP_FLEXCOMM2 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_B_LPACCEPT_MASK (0x8U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_B_LPACCEPT_SHIFT (3U)
/*! LP_FLEXCOMM3_B_LPACCEPT - LP_FLEXCOMM3 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_B_LPACCEPT_MASK (0x10U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_B_LPACCEPT_SHIFT (4U)
/*! LP_FLEXCOMM4_B_LPACCEPT - LP_FLEXCOMM4 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_B_LPACCEPT_MASK (0x20U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_B_LPACCEPT_SHIFT (5U)
/*! LP_FLEXCOMM5_B_LPACCEPT - LP_FLEXCOMM5 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_B_LPACCEPT_MASK (0x40U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_B_LPACCEPT_SHIFT (6U)
/*! LP_FLEXCOMM6_B_LPACCEPT - LP_FLEXCOMM6 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_B_LPACCEPT_MASK (0x80U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_B_LPACCEPT_SHIFT (7U)
/*! LP_FLEXCOMM7_B_LPACCEPT - LP_FLEXCOMM7 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_B_LPACCEPT_MASK (0x100U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_B_LPACCEPT_SHIFT (8U)
/*! LP_FLEXCOMM8_B_LPACCEPT - LP_FLEXCOMM8 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_B_LPACCEPT_MASK (0x200U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_B_LPACCEPT_SHIFT (9U)
/*! LP_FLEXCOMM9_B_LPACCEPT - LP_FLEXCOMM9 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_B_LPACCEPT_MASK (0x400U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_B_LPACCEPT_SHIFT (10U)
/*! LP_FLEXCOMM10_B_LPACCEPT - LP_FLEXCOMM10 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_B_LPACCEPT_MASK (0x800U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_B_LPACCEPT_SHIFT (11U)
/*! LP_FLEXCOMM11_B_LPACCEPT - LP_FLEXCOMM11 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_B_LPACCEPT_MASK (0x1000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_B_LPACCEPT_SHIFT (12U)
/*! LP_FLEXCOMM12_B_LPACCEPT - LP_FLEXCOMM12 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_B_LPACCEPT_MASK (0x2000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_B_LPACCEPT_SHIFT (13U)
/*! LP_FLEXCOMM13_B_LPACCEPT - LP_FLEXCOMM13 Bus Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_B_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_B_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_B_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_F_LPACCEPT_MASK (0x10000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_F_LPACCEPT_SHIFT (16U)
/*! LP_FLEXCOMM0_F_LPACCEPT - LP_FLEXCOMM0 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM0_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_F_LPACCEPT_MASK (0x20000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_F_LPACCEPT_SHIFT (17U)
/*! LP_FLEXCOMM1_F_LPACCEPT - LP_FLEXCOMM1 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM1_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_F_LPACCEPT_MASK (0x40000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_F_LPACCEPT_SHIFT (18U)
/*! LP_FLEXCOMM2_F_LPACCEPT - LP_FLEXCOMM2 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM2_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_F_LPACCEPT_MASK (0x80000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_F_LPACCEPT_SHIFT (19U)
/*! LP_FLEXCOMM3_F_LPACCEPT - LP_FLEXCOMM3 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM3_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_F_LPACCEPT_MASK (0x100000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_F_LPACCEPT_SHIFT (20U)
/*! LP_FLEXCOMM4_F_LPACCEPT - LP_FLEXCOMM4 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM4_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_F_LPACCEPT_MASK (0x200000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_F_LPACCEPT_SHIFT (21U)
/*! LP_FLEXCOMM5_F_LPACCEPT - LP_FLEXCOMM5 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM5_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_F_LPACCEPT_MASK (0x400000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_F_LPACCEPT_SHIFT (22U)
/*! LP_FLEXCOMM6_F_LPACCEPT - LP_FLEXCOMM6 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM6_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_F_LPACCEPT_MASK (0x800000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_F_LPACCEPT_SHIFT (23U)
/*! LP_FLEXCOMM7_F_LPACCEPT - LP_FLEXCOMM7 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM7_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_F_LPACCEPT_MASK (0x1000000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_F_LPACCEPT_SHIFT (24U)
/*! LP_FLEXCOMM8_F_LPACCEPT - LP_FLEXCOMM8 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM8_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_F_LPACCEPT_MASK (0x2000000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_F_LPACCEPT_SHIFT (25U)
/*! LP_FLEXCOMM9_F_LPACCEPT - LP_FLEXCOMM9 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM9_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_F_LPACCEPT_MASK (0x4000000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_F_LPACCEPT_SHIFT (26U)
/*! LP_FLEXCOMM10_F_LPACCEPT - LP_FLEXCOMM10 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM10_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_F_LPACCEPT_MASK (0x8000000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_F_LPACCEPT_SHIFT (27U)
/*! LP_FLEXCOMM11_F_LPACCEPT - LP_FLEXCOMM11 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM11_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_F_LPACCEPT_MASK (0x10000000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_F_LPACCEPT_SHIFT (28U)
/*! LP_FLEXCOMM12_F_LPACCEPT - LP_FLEXCOMM12 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM12_F_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_F_LPACCEPT_MASK (0x20000000U)
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_F_LPACCEPT_SHIFT (29U)
/*! LP_FLEXCOMM13_F_LPACCEPT - LP_FLEXCOMM13 Function Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_F_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_F_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT0_LP_FLEXCOMM13_F_LPACCEPT_MASK)
/*! @} */

/*! @name PRIVATE_TSTAT1 - Private Resources Targets Low-power Status 1 */
/*! @{ */

#define SLEEPCON0_PRIVATE_TSTAT1_GDET0_LPACCEPT_MASK (0x1U)
#define SLEEPCON0_PRIVATE_TSTAT1_GDET0_LPACCEPT_SHIFT (0U)
/*! GDET0_LPACCEPT - GDET0 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GDET0_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GDET0_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GDET0_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GDET1_LPACCEPT_MASK (0x2U)
#define SLEEPCON0_PRIVATE_TSTAT1_GDET1_LPACCEPT_SHIFT (1U)
/*! GDET1_LPACCEPT - GDET1 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GDET1_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GDET1_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GDET1_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GPIO0_LPACCEPT_MASK (0x4U)
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO0_LPACCEPT_SHIFT (2U)
/*! GPIO0_LPACCEPT - GPIO0 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO0_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GPIO0_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GPIO0_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GPIO1_LPACCEPT_MASK (0x8U)
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO1_LPACCEPT_SHIFT (3U)
/*! GPIO1_LPACCEPT - GPIO1 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO1_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GPIO1_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GPIO1_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GPIO2_LPACCEPT_MASK (0x10U)
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO2_LPACCEPT_SHIFT (4U)
/*! GPIO2_LPACCEPT - GPIO2 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO2_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GPIO2_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GPIO2_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GPIO3_LPACCEPT_MASK (0x20U)
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO3_LPACCEPT_SHIFT (5U)
/*! GPIO3_LPACCEPT - GPIO3 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO3_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GPIO3_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GPIO3_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GPIO4_LPACCEPT_MASK (0x40U)
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO4_LPACCEPT_SHIFT (6U)
/*! GPIO4_LPACCEPT - GPIO4 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO4_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GPIO4_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GPIO4_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GPIO5_LPACCEPT_MASK (0x80U)
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO5_LPACCEPT_SHIFT (7U)
/*! GPIO5_LPACCEPT - GPIO5 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO5_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GPIO5_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GPIO5_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GPIO6_LPACCEPT_MASK (0x100U)
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO6_LPACCEPT_SHIFT (8U)
/*! GPIO6_LPACCEPT - GPIO6 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO6_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GPIO6_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GPIO6_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_GPIO7_LPACCEPT_MASK (0x200U)
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO7_LPACCEPT_SHIFT (9U)
/*! GPIO7_LPACCEPT - GPIO7 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_GPIO7_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_GPIO7_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_GPIO7_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_SAI0_LPACCEPT_MASK (0x400U)
#define SLEEPCON0_PRIVATE_TSTAT1_SAI0_LPACCEPT_SHIFT (10U)
/*! SAI0_LPACCEPT - SAI0 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_SAI0_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_SAI0_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_SAI0_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_SAI1_LPACCEPT_MASK (0x800U)
#define SLEEPCON0_PRIVATE_TSTAT1_SAI1_LPACCEPT_SHIFT (11U)
/*! SAI1_LPACCEPT - SAI1 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_SAI1_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_SAI1_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_SAI1_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_SAI2_LPACCEPT_MASK (0x1000U)
#define SLEEPCON0_PRIVATE_TSTAT1_SAI2_LPACCEPT_SHIFT (12U)
/*! SAI2_LPACCEPT - SAI2 Low-power Accept Status
 *  0b0..Not accept
 *  0b1..Accept
 */
#define SLEEPCON0_PRIVATE_TSTAT1_SAI2_LPACCEPT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_SAI2_LPACCEPT_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_SAI2_LPACCEPT_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_TRNG_STOP_MASK  (0x2000U)
#define SLEEPCON0_PRIVATE_TSTAT1_TRNG_STOP_SHIFT (13U)
/*! TRNG_STOP - TRNG Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_PRIVATE_TSTAT1_TRNG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_TRNG_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_TRNG_STOP_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_XSPI0_STOP_MASK (0x4000U)
#define SLEEPCON0_PRIVATE_TSTAT1_XSPI0_STOP_SHIFT (14U)
/*! XSPI0_STOP - XSPI0 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_PRIVATE_TSTAT1_XSPI0_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_XSPI0_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_XSPI0_STOP_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_XSPI1_STOP_MASK (0x8000U)
#define SLEEPCON0_PRIVATE_TSTAT1_XSPI1_STOP_SHIFT (15U)
/*! XSPI1_STOP - XSPI1 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_PRIVATE_TSTAT1_XSPI1_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_XSPI1_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_XSPI1_STOP_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_I3C0_STOP_MASK  (0x10000U)
#define SLEEPCON0_PRIVATE_TSTAT1_I3C0_STOP_SHIFT (16U)
/*! I3C0_STOP - I3C0 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_PRIVATE_TSTAT1_I3C0_STOP(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_I3C0_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_I3C0_STOP_MASK)

#define SLEEPCON0_PRIVATE_TSTAT1_I3C1_STOP_MASK  (0x20000U)
#define SLEEPCON0_PRIVATE_TSTAT1_I3C1_STOP_SHIFT (17U)
/*! I3C1_STOP - I3C1 Stop Status
 *  0b0..Not in Stop status
 *  0b1..In Stop status
 */
#define SLEEPCON0_PRIVATE_TSTAT1_I3C1_STOP(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_PRIVATE_TSTAT1_I3C1_STOP_SHIFT)) & SLEEPCON0_PRIVATE_TSTAT1_I3C1_STOP_MASK)
/*! @} */

/*! @name LP_HINT0 - Low-Power Hints 0 */
/*! @{ */

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_B_LPHINT_MASK (0x1U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_B_LPHINT_SHIFT (0U)
/*! LP_FLEXCOMM0_B_LPHINT - LP_FLEXCOMM0 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_B_LPHINT_MASK (0x2U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_B_LPHINT_SHIFT (1U)
/*! LP_FLEXCOMM1_B_LPHINT - LP_FLEXCOMM1 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_B_LPHINT_MASK (0x4U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_B_LPHINT_SHIFT (2U)
/*! LP_FLEXCOMM2_B_LPHINT - LP_FLEXCOMM2 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_B_LPHINT_MASK (0x8U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_B_LPHINT_SHIFT (3U)
/*! LP_FLEXCOMM3_B_LPHINT - LP_FLEXCOMM3 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_B_LPHINT_MASK (0x10U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_B_LPHINT_SHIFT (4U)
/*! LP_FLEXCOMM4_B_LPHINT - LP_FLEXCOMM4 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_B_LPHINT_MASK (0x20U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_B_LPHINT_SHIFT (5U)
/*! LP_FLEXCOMM5_B_LPHINT - LP_FLEXCOMM5 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_B_LPHINT_MASK (0x40U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_B_LPHINT_SHIFT (6U)
/*! LP_FLEXCOMM6_B_LPHINT - LP_FLEXCOMM6 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_B_LPHINT_MASK (0x80U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_B_LPHINT_SHIFT (7U)
/*! LP_FLEXCOMM7_B_LPHINT - LP_FLEXCOMM7 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_B_LPHINT_MASK (0x100U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_B_LPHINT_SHIFT (8U)
/*! LP_FLEXCOMM8_B_LPHINT - LP_FLEXCOMM8 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_B_LPHINT_MASK (0x200U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_B_LPHINT_SHIFT (9U)
/*! LP_FLEXCOMM9_B_LPHINT - LP_FLEXCOMM9 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_B_LPHINT_MASK (0x400U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_B_LPHINT_SHIFT (10U)
/*! LP_FLEXCOMM10_B_LPHINT - LP_FLEXCOMM10 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_B_LPHINT_MASK (0x800U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_B_LPHINT_SHIFT (11U)
/*! LP_FLEXCOMM11_B_LPHINT - LP_FLEXCOMM11 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_B_LPHINT_MASK (0x1000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_B_LPHINT_SHIFT (12U)
/*! LP_FLEXCOMM12_B_LPHINT - LP_FLEXCOMM12 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_B_LPHINT_MASK (0x2000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_B_LPHINT_SHIFT (13U)
/*! LP_FLEXCOMM13_B_LPHINT - LP_FLEXCOMM13 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_B_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LPSPI14_B_LPHINT_MASK (0x4000U)
#define SLEEPCON0_LP_HINT0_LPSPI14_B_LPHINT_SHIFT (14U)
/*! LPSPI14_B_LPHINT - LPSPI14 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LPSPI14_B_LPHINT(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LPSPI14_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LPSPI14_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LPSPI16_B_LPHINT_MASK (0x8000U)
#define SLEEPCON0_LP_HINT0_LPSPI16_B_LPHINT_SHIFT (15U)
/*! LPSPI16_B_LPHINT - LPSPI16 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LPSPI16_B_LPHINT(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LPSPI16_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LPSPI16_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_F_LPHINT_MASK (0x10000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_F_LPHINT_SHIFT (16U)
/*! LP_FLEXCOMM0_F_LPHINT - LP_FLEXCOMM0 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM0_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_F_LPHINT_MASK (0x20000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_F_LPHINT_SHIFT (17U)
/*! LP_FLEXCOMM1_F_LPHINT - LP_FLEXCOMM1 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM1_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_F_LPHINT_MASK (0x40000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_F_LPHINT_SHIFT (18U)
/*! LP_FLEXCOMM2_F_LPHINT - LP_FLEXCOMM2 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM2_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_F_LPHINT_MASK (0x80000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_F_LPHINT_SHIFT (19U)
/*! LP_FLEXCOMM3_F_LPHINT - LP_FLEXCOMM3 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM3_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_F_LPHINT_MASK (0x100000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_F_LPHINT_SHIFT (20U)
/*! LP_FLEXCOMM4_F_LPHINT - LP_FLEXCOMM4 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM4_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_F_LPHINT_MASK (0x200000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_F_LPHINT_SHIFT (21U)
/*! LP_FLEXCOMM5_F_LPHINT - LP_FLEXCOMM5 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM5_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_F_LPHINT_MASK (0x400000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_F_LPHINT_SHIFT (22U)
/*! LP_FLEXCOMM6_F_LPHINT - LP_FLEXCOMM6 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM6_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_F_LPHINT_MASK (0x800000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_F_LPHINT_SHIFT (23U)
/*! LP_FLEXCOMM7_F_LPHINT - LP_FLEXCOMM7 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM7_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_F_LPHINT_MASK (0x1000000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_F_LPHINT_SHIFT (24U)
/*! LP_FLEXCOMM8_F_LPHINT - LP_FLEXCOMM8 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM8_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_F_LPHINT_MASK (0x2000000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_F_LPHINT_SHIFT (25U)
/*! LP_FLEXCOMM9_F_LPHINT - LP_FLEXCOMM9 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM9_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_F_LPHINT_MASK (0x4000000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_F_LPHINT_SHIFT (26U)
/*! LP_FLEXCOMM10_F_LPHINT - LP_FLEXCOMM10 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM10_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_F_LPHINT_MASK (0x8000000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_F_LPHINT_SHIFT (27U)
/*! LP_FLEXCOMM11_F_LPHINT - LP_FLEXCOMM11 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM11_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_F_LPHINT_MASK (0x10000000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_F_LPHINT_SHIFT (28U)
/*! LP_FLEXCOMM12_F_LPHINT - LP_FLEXCOMM12 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM12_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_F_LPHINT_MASK (0x20000000U)
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_F_LPHINT_SHIFT (29U)
/*! LP_FLEXCOMM13_F_LPHINT - LP_FLEXCOMM13 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_F_LPHINT(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LP_FLEXCOMM13_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LPSPI14_F_LPHINT_MASK (0x40000000U)
#define SLEEPCON0_LP_HINT0_LPSPI14_F_LPHINT_SHIFT (30U)
/*! LPSPI14_F_LPHINT - LPSPI14 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LPSPI14_F_LPHINT(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LPSPI14_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LPSPI14_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT0_LPSPI16_F_LPHINT_MASK (0x80000000U)
#define SLEEPCON0_LP_HINT0_LPSPI16_F_LPHINT_SHIFT (31U)
/*! LPSPI16_F_LPHINT - LPSPI16 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT0_LPSPI16_F_LPHINT(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT0_LPSPI16_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT0_LPSPI16_F_LPHINT_MASK)
/*! @} */

/*! @name LP_HINT1 - Low-Power Hints 1 */
/*! @{ */

#define SLEEPCON0_LP_HINT1_GPIO0_LPHINT_MASK     (0x1U)
#define SLEEPCON0_LP_HINT1_GPIO0_LPHINT_SHIFT    (0U)
/*! GPIO0_LPHINT - GPIO0 Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_GPIO0_LPHINT(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_GPIO0_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_GPIO0_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_GPIO1_LPHINT_MASK     (0x2U)
#define SLEEPCON0_LP_HINT1_GPIO1_LPHINT_SHIFT    (1U)
/*! GPIO1_LPHINT - GPIO1 Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_GPIO1_LPHINT(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_GPIO1_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_GPIO1_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_GPIO2_LPHINT_MASK     (0x4U)
#define SLEEPCON0_LP_HINT1_GPIO2_LPHINT_SHIFT    (2U)
/*! GPIO2_LPHINT - GPIO2 Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_GPIO2_LPHINT(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_GPIO2_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_GPIO2_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_GPIO3_LPHINT_MASK     (0x8U)
#define SLEEPCON0_LP_HINT1_GPIO3_LPHINT_SHIFT    (3U)
/*! GPIO3_LPHINT - GPIO3 Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_GPIO3_LPHINT(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_GPIO3_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_GPIO3_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_GPIO4_LPHINT_MASK     (0x10U)
#define SLEEPCON0_LP_HINT1_GPIO4_LPHINT_SHIFT    (4U)
/*! GPIO4_LPHINT - GPIO4 Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_GPIO4_LPHINT(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_GPIO4_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_GPIO4_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_GPIO5_LPHINT_MASK     (0x20U)
#define SLEEPCON0_LP_HINT1_GPIO5_LPHINT_SHIFT    (5U)
/*! GPIO5_LPHINT - GPIO5 Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_GPIO5_LPHINT(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_GPIO5_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_GPIO5_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_GPIO6_LPHINT_MASK     (0x40U)
#define SLEEPCON0_LP_HINT1_GPIO6_LPHINT_SHIFT    (6U)
/*! GPIO6_LPHINT - GPIO6 Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_GPIO6_LPHINT(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_GPIO6_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_GPIO6_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_GPIO7_LPHINT_MASK     (0x80U)
#define SLEEPCON0_LP_HINT1_GPIO7_LPHINT_SHIFT    (7U)
/*! GPIO7_LPHINT - GPIO7 Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_GPIO7_LPHINT(x)       (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_GPIO7_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_GPIO7_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_SAI0_B_LPHINT_MASK    (0x100U)
#define SLEEPCON0_LP_HINT1_SAI0_B_LPHINT_SHIFT   (8U)
/*! SAI0_B_LPHINT - SAI0 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_SAI0_B_LPHINT(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_SAI0_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_SAI0_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_SAI1_B_LPHINT_MASK    (0x200U)
#define SLEEPCON0_LP_HINT1_SAI1_B_LPHINT_SHIFT   (9U)
/*! SAI1_B_LPHINT - SAI1 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_SAI1_B_LPHINT(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_SAI1_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_SAI1_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_SAI2_B_LPHINT_MASK    (0x400U)
#define SLEEPCON0_LP_HINT1_SAI2_B_LPHINT_SHIFT   (10U)
/*! SAI2_B_LPHINT - SAI2 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_SAI2_B_LPHINT(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_SAI2_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_SAI2_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_SAI0_F_LPHINT_MASK    (0x800U)
#define SLEEPCON0_LP_HINT1_SAI0_F_LPHINT_SHIFT   (11U)
/*! SAI0_F_LPHINT - SAI0 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_SAI0_F_LPHINT(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_SAI0_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_SAI0_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_SAI1_F_LPHINT_MASK    (0x1000U)
#define SLEEPCON0_LP_HINT1_SAI1_F_LPHINT_SHIFT   (12U)
/*! SAI1_F_LPHINT - SAI1 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_SAI1_F_LPHINT(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_SAI1_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_SAI1_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_SAI2_F_LPHINT_MASK    (0x2000U)
#define SLEEPCON0_LP_HINT1_SAI2_F_LPHINT_SHIFT   (13U)
/*! SAI2_F_LPHINT - SAI2 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_SAI2_F_LPHINT(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_SAI2_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_SAI2_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_FLEXIO_B_LPHINT_MASK  (0x4000U)
#define SLEEPCON0_LP_HINT1_FLEXIO_B_LPHINT_SHIFT (14U)
/*! FLEXIO_B_LPHINT - FLEXIO Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_FLEXIO_B_LPHINT(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_FLEXIO_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_FLEXIO_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_LPI2C15_B_LPHINT_MASK (0x8000U)
#define SLEEPCON0_LP_HINT1_LPI2C15_B_LPHINT_SHIFT (15U)
/*! LPI2C15_B_LPHINT - LPI2C15 Bus Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_LPI2C15_B_LPHINT(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_LPI2C15_B_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_LPI2C15_B_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_FLEXIO_F_LPHINT_MASK  (0x10000U)
#define SLEEPCON0_LP_HINT1_FLEXIO_F_LPHINT_SHIFT (16U)
/*! FLEXIO_F_LPHINT - FLEXIO Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_FLEXIO_F_LPHINT(x)    (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_FLEXIO_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_FLEXIO_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_LPI2C15_F_LPHINT_MASK (0x20000U)
#define SLEEPCON0_LP_HINT1_LPI2C15_F_LPHINT_SHIFT (17U)
/*! LPI2C15_F_LPHINT - LPI2C15 Function Clock Related Logic Status
 *  0b0..Inactive
 *  0b1..Active
 */
#define SLEEPCON0_LP_HINT1_LPI2C15_F_LPHINT(x)   (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_LPI2C15_F_LPHINT_SHIFT)) & SLEEPCON0_LP_HINT1_LPI2C15_F_LPHINT_MASK)

#define SLEEPCON0_LP_HINT1_NIC0_IDLE0_MASK       (0x40000U)
#define SLEEPCON0_LP_HINT1_NIC0_IDLE0_SHIFT      (18U)
/*! NIC0_IDLE0 - NIC_MEDIA0 Idle Status
 *  0b0..Active
 *  0b1..Idle
 */
#define SLEEPCON0_LP_HINT1_NIC0_IDLE0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_NIC0_IDLE0_SHIFT)) & SLEEPCON0_LP_HINT1_NIC0_IDLE0_MASK)

#define SLEEPCON0_LP_HINT1_NIC0_IDLE1_MASK       (0x80000U)
#define SLEEPCON0_LP_HINT1_NIC0_IDLE1_SHIFT      (19U)
/*! NIC0_IDLE1 - NIC_MEDIA0 Idle Status
 *  0b0..Active
 *  0b1..Idle
 */
#define SLEEPCON0_LP_HINT1_NIC0_IDLE1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_NIC0_IDLE1_SHIFT)) & SLEEPCON0_LP_HINT1_NIC0_IDLE1_MASK)

#define SLEEPCON0_LP_HINT1_NIC1_IDLE0_MASK       (0x100000U)
#define SLEEPCON0_LP_HINT1_NIC1_IDLE0_SHIFT      (20U)
/*! NIC1_IDLE0 - NIC_MEDIA1 Idle Status
 *  0b0..Active
 *  0b1..Idle
 */
#define SLEEPCON0_LP_HINT1_NIC1_IDLE0(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_NIC1_IDLE0_SHIFT)) & SLEEPCON0_LP_HINT1_NIC1_IDLE0_MASK)

#define SLEEPCON0_LP_HINT1_NIC1_IDLE1_MASK       (0x200000U)
#define SLEEPCON0_LP_HINT1_NIC1_IDLE1_SHIFT      (21U)
/*! NIC1_IDLE1 - NIC_MEDIA1 Idle Status
 *  0b0..Active
 *  0b1..Idle
 */
#define SLEEPCON0_LP_HINT1_NIC1_IDLE1(x)         (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_HINT1_NIC1_IDLE1_SHIFT)) & SLEEPCON0_LP_HINT1_NIC1_IDLE1_MASK)
/*! @} */

/*! @name LP_DENY0 - Low-Power Request Deny Status 0 */
/*! @{ */

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM0_LPDENY_MASK (0x1U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM0_LPDENY_SHIFT (0U)
/*! LP_FLEXCOMM0_LPDENY - LP_FLEXCOMM0 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM0_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM0_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM0_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM1_LPDENY_MASK (0x2U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM1_LPDENY_SHIFT (1U)
/*! LP_FLEXCOMM1_LPDENY - LP_FLEXCOMM1 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM1_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM1_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM1_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM2_LPDENY_MASK (0x4U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM2_LPDENY_SHIFT (2U)
/*! LP_FLEXCOMM2_LPDENY - LP_FLEXCOMM2 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM2_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM2_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM2_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM3_LPDENY_MASK (0x8U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM3_LPDENY_SHIFT (3U)
/*! LP_FLEXCOMM3_LPDENY - LP_FLEXCOMM3 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM3_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM3_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM3_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM4_LPDENY_MASK (0x10U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM4_LPDENY_SHIFT (4U)
/*! LP_FLEXCOMM4_LPDENY - LP_FLEXCOMM4 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM4_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM4_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM4_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM5_LPDENY_MASK (0x20U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM5_LPDENY_SHIFT (5U)
/*! LP_FLEXCOMM5_LPDENY - LP_FLEXCOMM5 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM5_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM5_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM5_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM6_LPDENY_MASK (0x40U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM6_LPDENY_SHIFT (6U)
/*! LP_FLEXCOMM6_LPDENY - LP_FLEXCOMM6 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM6_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM6_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM6_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM7_LPDENY_MASK (0x80U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM7_LPDENY_SHIFT (7U)
/*! LP_FLEXCOMM7_LPDENY - LP_FLEXCOMM7 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM7_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM7_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM7_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM8_LPDENY_MASK (0x100U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM8_LPDENY_SHIFT (8U)
/*! LP_FLEXCOMM8_LPDENY - LP_FLEXCOMM8 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM8_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM8_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM8_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM9_LPDENY_MASK (0x200U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM9_LPDENY_SHIFT (9U)
/*! LP_FLEXCOMM9_LPDENY - LP_FLEXCOMM9 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM9_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM9_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM9_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM10_LPDENY_MASK (0x400U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM10_LPDENY_SHIFT (10U)
/*! LP_FLEXCOMM10_LPDENY - LP_FLEXCOMM10 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM10_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM10_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM10_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM11_LPDENY_MASK (0x800U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM11_LPDENY_SHIFT (11U)
/*! LP_FLEXCOMM11_LPDENY - LP_FLEXCOMM11 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM11_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM11_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM11_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM12_LPDENY_MASK (0x1000U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM12_LPDENY_SHIFT (12U)
/*! LP_FLEXCOMM12_LPDENY - LP_FLEXCOMM12 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM12_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM12_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM12_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM13_LPDENY_MASK (0x2000U)
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM13_LPDENY_SHIFT (13U)
/*! LP_FLEXCOMM13_LPDENY - LP_FLEXCOMM13 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LP_FLEXCOMM13_LPDENY(x) (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LP_FLEXCOMM13_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LP_FLEXCOMM13_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LPSPI14_LPDENY_MASK   (0x4000U)
#define SLEEPCON0_LP_DENY0_LPSPI14_LPDENY_SHIFT  (14U)
/*! LPSPI14_LPDENY - LPSPI14 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LPSPI14_LPDENY(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LPSPI14_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LPSPI14_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LPSPI16_LPDENY_MASK   (0x8000U)
#define SLEEPCON0_LP_DENY0_LPSPI16_LPDENY_SHIFT  (15U)
/*! LPSPI16_LPDENY - LPSPI16 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LPSPI16_LPDENY(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LPSPI16_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LPSPI16_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_FLEXIO_LPDENY_MASK    (0x10000U)
#define SLEEPCON0_LP_DENY0_FLEXIO_LPDENY_SHIFT   (16U)
/*! FLEXIO_LPDENY - FLEXIO Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_FLEXIO_LPDENY(x)      (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_FLEXIO_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_FLEXIO_LPDENY_MASK)

#define SLEEPCON0_LP_DENY0_LPI2C15_LPDENY_MASK   (0x20000U)
#define SLEEPCON0_LP_DENY0_LPI2C15_LPDENY_SHIFT  (17U)
/*! LPI2C15_LPDENY - LPI2C15 Low-Power Deny Status
 *  0b0..Not deny
 *  0b1..Deny
 */
#define SLEEPCON0_LP_DENY0_LPI2C15_LPDENY(x)     (((uint32_t)(((uint32_t)(x)) << SLEEPCON0_LP_DENY0_LPI2C15_LPDENY_SHIFT)) & SLEEPCON0_LP_DENY0_LPI2C15_LPDENY_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SLEEPCON0_Register_Masks */


/* SLEEPCON0 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SLEEPCON0 base address */
  #define SLEEPCON0_BASE                           (0x50003000u)
  /** Peripheral SLEEPCON0 base address */
  #define SLEEPCON0_BASE_NS                        (0x40003000u)
  /** Peripheral SLEEPCON0 base pointer */
  #define SLEEPCON0                                ((SLEEPCON0_Type *)SLEEPCON0_BASE)
  /** Peripheral SLEEPCON0 base pointer */
  #define SLEEPCON0_NS                             ((SLEEPCON0_Type *)SLEEPCON0_BASE_NS)
  /** Array initializer of SLEEPCON0 peripheral base addresses */
  #define SLEEPCON0_BASE_ADDRS                     { SLEEPCON0_BASE }
  /** Array initializer of SLEEPCON0 peripheral base pointers */
  #define SLEEPCON0_BASE_PTRS                      { SLEEPCON0 }
  /** Array initializer of SLEEPCON0 peripheral base addresses */
  #define SLEEPCON0_BASE_ADDRS_NS                  { SLEEPCON0_BASE_NS }
  /** Array initializer of SLEEPCON0 peripheral base pointers */
  #define SLEEPCON0_BASE_PTRS_NS                   { SLEEPCON0_NS }
#else
  /** Peripheral SLEEPCON0 base address */
  #define SLEEPCON0_BASE                           (0x40003000u)
  /** Peripheral SLEEPCON0 base pointer */
  #define SLEEPCON0                                ((SLEEPCON0_Type *)SLEEPCON0_BASE)
  /** Array initializer of SLEEPCON0 peripheral base addresses */
  #define SLEEPCON0_BASE_ADDRS                     { SLEEPCON0_BASE }
  /** Array initializer of SLEEPCON0 peripheral base pointers */
  #define SLEEPCON0_BASE_PTRS                      { SLEEPCON0 }
#endif

/*!
 * @}
 */ /* end of group SLEEPCON0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSCON0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON0_Peripheral_Access_Layer SYSCON0 Peripheral Access Layer
 * @{
 */

/** SYSCON0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t SEC_CLK_CTRL;                      /**< Security Clock Control, offset: 0x0 */
  __O  uint32_t SEC_CLK_CTRL_SET;                  /**< Security Clock Control Set, offset: 0x4 */
  __O  uint32_t SEC_CLK_CTRL_CLR;                  /**< Security Clock Control Clear, offset: 0x8 */
  __IO uint32_t GDET_CTRL[2];                      /**< GDET0 Control..GDET1 Control, array offset: 0xC, array step: 0x4 */
  __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x14 */
       uint8_t RESERVED_0[4];
  __IO uint32_t CTIMERGLOBALSTARTEN;               /**< CTIMER Global Start Enable, offset: 0x1C */
       uint8_t RESERVED_1[16];
  __I  uint32_t FUSEACSTATUS;                      /**< Fuse Access Status, offset: 0x30 */
       uint8_t RESERVED_2[68];
  __IO uint32_t AHBMATPRIO;                        /**< Bus Matrix Priority, offset: 0x78 */
       uint8_t RESERVED_3[4];
  __O  uint32_t RXEVPULSEGEN;                      /**< Receive Event Pulse Generator, offset: 0x80 */
  __IO uint32_t LATCHED_CM33_TXEV;                 /**< Latched Cortex-M33 Transmit Event, offset: 0x84 */
       uint8_t RESERVED_4[8];
  __IO uint32_t SYSTEM_STICK_CALIB;                /**< System Secure Tick Calibration, offset: 0x90 */
  __IO uint32_t SYSTEM_NSTICK_CALIB;               /**< System Non-Secure Tick Calibration, offset: 0x94 */
  __I  uint32_t CPU0_STATUS;                       /**< CPU0 Status, offset: 0x98 */
       uint8_t RESERVED_5[52];
  __IO uint32_t GPIO_PSYNC;                        /**< GPIO Synchronization Stages, offset: 0xD0 */
       uint8_t RESERVED_6[64];
  __IO uint32_t AUTOCLKGATEOVERRIDE0;              /**< Automatic Clock Gate Override, offset: 0x114 */
  __IO uint32_t SRAM_CLKGATE_CTRL;                 /**< SRAM Clock Gating Control, offset: 0x118 */
       uint8_t RESERVED_7[8];
  __IO uint32_t OCOTP_MEM_CTL;                     /**< OCOTP Memory Control, offset: 0x124 */
  __IO uint32_t ELS_MEM_CTL;                       /**< ELS Memory Control, offset: 0x128 */
       uint8_t RESERVED_8[4];
  __IO uint32_t MMU0_MEM_CTRL;                     /**< MMU0 Memory Control, offset: 0x130 */
       uint8_t RESERVED_9[12];
  __IO uint32_t EDMA0_MEM_CTRL;                    /**< eDMA0 Memory Control, offset: 0x140 */
  __IO uint32_t EDMA1_MEM_CTRL;                    /**< eDMA1 Memory Control, offset: 0x144 */
       uint8_t RESERVED_10[4];
  __IO uint32_t ETF_MEM_CTRL;                      /**< ETF Memory Control, offset: 0x14C */
  __IO uint32_t MMU1_MEM_CTRL;                     /**< MMU1 Memory Control, offset: 0x150 */
  __IO uint32_t XSPI0_MEM_CTRL;                    /**< XSPI0 Memory Control, offset: 0x154 */
  __IO uint32_t XSPI1_MEM_CTRL;                    /**< XSPI1 Memory Control, offset: 0x158 */
  __IO uint32_t XSPI0_DATA_MEM_CTRL;               /**< XSPI0 Data Memory Control, offset: 0x15C */
  __IO uint32_t XSPI1_DATA_MEM_CTRL;               /**< XSPI1 Data Memory Control, offset: 0x160 */
  __IO uint32_t NPU_MEM_CTRL;                      /**< NPU Memory Control, offset: 0x164 */
  __IO uint32_t PKC0_MEM_CTRL;                     /**< PKC Memory 0 Control, offset: 0x168 */
  __IO uint32_t PKC1_MEM_CTRL;                     /**< PKC Memory 1 Control, offset: 0x16C */
       uint8_t RESERVED_11[4];
  __IO uint32_t CM33_MEM_DATA_CTRL;                /**< CPU0 Memory Data Control, offset: 0x174 */
  __IO uint32_t CM33_MEM_TAG_CTRL;                 /**< CPU0 Memory Tag Control, offset: 0x178 */
       uint8_t RESERVED_12[140];
  __IO uint32_t HIFI4_MEM_CTL;                     /**< HiFi4 Memory Control, offset: 0x208 */
       uint8_t RESERVED_13[52];
  __IO uint32_t SAI0_MCLK_CTRL;                    /**< SAI0-2 MCLK IO Direction Control, offset: 0x240 */
       uint8_t RESERVED_14[24];
  __IO uint32_t XSPI0_TAG_MEM_CTRL;                /**< XSPI0 Cache Tag Memory Control, offset: 0x25C */
  __IO uint32_t XSPI1_TAG_MEM_CTRL;                /**< XSPI1 Cache Tag Memory Control, offset: 0x260 */
       uint8_t RESERVED_15[28];
  __IO uint32_t COMP_AUTOGATE_EN;                  /**< VDD2_COMP Auto Gating Enable, offset: 0x280 */
       uint8_t RESERVED_16[12];
  __IO uint32_t COMP_DEBUG_HALTED_SEL;             /**< VDD2_COMP Debug Halted Select, offset: 0x290 */
       uint8_t RESERVED_17[108];
  __IO uint32_t DSPSTALL;                          /**< HiFi4 Stall, offset: 0x300 */
  __IO uint32_t OCDHALTONRESET;                    /**< HiFi4 OCDHaltOnReset, offset: 0x304 */
  __I  uint32_t HIFI4_GPR0;                        /**< HiFi4 General Purpose Register 0, offset: 0x308 */
       uint8_t RESERVED_18[8];
  __I  uint32_t HIFI4_GPR1;                        /**< HiFi4 General Purpose Register 1, offset: 0x314 */
  __I  uint32_t HIFI4_GPR2;                        /**< HiFi4 General Purpose Register 2, offset: 0x318 */
  __IO uint32_t DSP_VECT_REMAP;                    /**< HiFi4 DSP Vector Remap, offset: 0x31C */
       uint8_t RESERVED_19[256];
  __IO uint32_t EDMA0_EN0;                         /**< eDMA0 Request Enable 0, offset: 0x420 */
  __IO uint32_t EDMA0_EN1;                         /**< eDMA0 Request Enable 1, offset: 0x424 */
  __IO uint32_t EDMA0_EN2;                         /**< eDMA0 Request Enable 2, offset: 0x428 */
  __IO uint32_t EDMA0_EN3;                         /**< eDMA0 Request Enable 3, offset: 0x42C */
  __IO uint32_t EDMA1_EN0;                         /**< eDMA1 Request Enable 0, offset: 0x430 */
  __IO uint32_t EDMA1_EN1;                         /**< eDMA1 Request Enable 1, offset: 0x434 */
  __IO uint32_t EDMA1_EN2;                         /**< eDMA1 Request Enable 2, offset: 0x438 */
  __IO uint32_t EDMA1_EN3;                         /**< eDMA1 Request Enable 3, offset: 0x43C */
       uint8_t RESERVED_20[448];
  __IO uint32_t AXBS_CTRL;                         /**< AXBS Control, offset: 0x600 */
       uint8_t RESERVED_21[36];
  __IO uint32_t I3C_ASYNC_WAKEUP_CTRL;             /**< I3C Asynchronous Wake-up Control, offset: 0x628 */
       uint8_t RESERVED_22[36];
  __IO uint32_t GRAY_CODE_LSB;                     /**< Gray to Binary Converter - Gray Code [31:0], offset: 0x650 */
  __IO uint32_t GRAY_CODE_MSB;                     /**< Gray to Binary Converter - Gray Code [63:32], offset: 0x654 */
  __I  uint32_t BINARY_CODE_LSB;                   /**< Gray to Binary Converter - Binary Code [31:0], offset: 0x658 */
  __I  uint32_t BINARY_CODE_MSB;                   /**< Gray to Binary Converter - Binary Code [63:32], offset: 0x65C */
       uint8_t RESERVED_23[928];
  __I  uint32_t SEC_BUSY_STATE;                    /**< Secure IP Busy State, offset: 0xA00 */
       uint8_t RESERVED_24[252];
  __I  uint32_t ELS_OTP_LC_STATE;                  /**< Lifecycle State, offset: 0xB00 */
  __I  uint32_t ELS_OTP_LC_STATE_DP;               /**< Lifecycle State, offset: 0xB04 */
  __IO uint32_t ELS_TEMPORAL_STATE;                /**< ELS Temporal State, offset: 0xB08 */
  __IO uint32_t ELS_KDF_MASK;                      /**< Key Derivation Function Mask, offset: 0xB0C */
       uint8_t RESERVED_25[176];
  __I  uint32_t ELS_AS_UUID[4];                    /**< ELS AS UUID, array offset: 0xBC0, array step: 0x4 */
  __I  uint32_t ELS_AS_CFG0;                       /**< ELS AS Configuration 0, offset: 0xBD0 */
  __I  uint32_t ELS_AS_CFG1;                       /**< ELS AS Configuration 1, offset: 0xBD4 */
       uint8_t RESERVED_26[4];
  __I  uint32_t ELS_AS_CFG3;                       /**< ELS AS Configuration 3, offset: 0xBDC */
  __I  uint32_t ELS_AS_ST0;                        /**< ELS AS State 0, offset: 0xBE0 */
  __I  uint32_t ELS_AS_ST1;                        /**< ELS AS State 1, offset: 0xBE4 */
       uint8_t RESERVED_27[16];
  __I  uint32_t ELS_AS_FLAG0;                      /**< ELS AS Flag 0, offset: 0xBF8 */
  __I  uint32_t ELS_AS_FLAG1;                      /**< ELS AS Flag 1, offset: 0xBFC */
       uint8_t RESERVED_28[560];
  __IO uint32_t CLK_OVERRIDE_RAMPKC;               /**< PKC RAM Clock Override, offset: 0xE30 */
} SYSCON0_Type;

/* ----------------------------------------------------------------------------
   -- SYSCON0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON0_Register_Masks SYSCON0 Register Masks
 * @{
 */

/*! @name SEC_CLK_CTRL - Security Clock Control */
/*! @{ */

#define SYSCON0_SEC_CLK_CTRL_GDET0_REFCLK_EN_MASK (0x1U)
#define SYSCON0_SEC_CLK_CTRL_GDET0_REFCLK_EN_SHIFT (0U)
/*! GDET0_REFCLK_EN - GDET0 Reference Clock Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_SEC_CLK_CTRL_GDET0_REFCLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_GDET0_REFCLK_EN_SHIFT)) & SYSCON0_SEC_CLK_CTRL_GDET0_REFCLK_EN_MASK)

#define SYSCON0_SEC_CLK_CTRL_GDET1_REFCLK_EN_MASK (0x2U)
#define SYSCON0_SEC_CLK_CTRL_GDET1_REFCLK_EN_SHIFT (1U)
/*! GDET1_REFCLK_EN - GDET1 Reference Clock Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_SEC_CLK_CTRL_GDET1_REFCLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_GDET1_REFCLK_EN_SHIFT)) & SYSCON0_SEC_CLK_CTRL_GDET1_REFCLK_EN_MASK)

#define SYSCON0_SEC_CLK_CTRL_TRNG_REFCLK_EN_MASK (0x4U)
#define SYSCON0_SEC_CLK_CTRL_TRNG_REFCLK_EN_SHIFT (2U)
/*! TRNG_REFCLK_EN - True Random Number Generator (TRNG) Reference Clock Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_SEC_CLK_CTRL_TRNG_REFCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_TRNG_REFCLK_EN_SHIFT)) & SYSCON0_SEC_CLK_CTRL_TRNG_REFCLK_EN_MASK)

#define SYSCON0_SEC_CLK_CTRL_ELS_CLK_EN_MASK     (0x8U)
#define SYSCON0_SEC_CLK_CTRL_ELS_CLK_EN_SHIFT    (3U)
/*! ELS_CLK_EN - EdgeLock Secure Subsystem (ELS) Clock Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_SEC_CLK_CTRL_ELS_CLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_ELS_CLK_EN_SHIFT)) & SYSCON0_SEC_CLK_CTRL_ELS_CLK_EN_MASK)

#define SYSCON0_SEC_CLK_CTRL_ITRC_CLK_EN_MASK    (0x10U)
#define SYSCON0_SEC_CLK_CTRL_ITRC_CLK_EN_SHIFT   (4U)
/*! ITRC_CLK_EN - Intrusion and Tamper Response Controller (ITRC) Reference Clock Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_SEC_CLK_CTRL_ITRC_CLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_ITRC_CLK_EN_SHIFT)) & SYSCON0_SEC_CLK_CTRL_ITRC_CLK_EN_MASK)
/*! @} */

/*! @name SEC_CLK_CTRL_SET - Security Clock Control Set */
/*! @{ */

#define SYSCON0_SEC_CLK_CTRL_SET_GDET0_REFCLK_EN_SET_MASK (0x1U)
#define SYSCON0_SEC_CLK_CTRL_SET_GDET0_REFCLK_EN_SET_SHIFT (0U)
/*! GDET0_REFCLK_EN_SET - GDET0 Reference Clock Enable Set
 *  0b0..Has no effect
 *  0b1..Sets SEC_CLK_CTRL[GDET0_REFCLK_EN] to 1
 */
#define SYSCON0_SEC_CLK_CTRL_SET_GDET0_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_SET_GDET0_REFCLK_EN_SET_SHIFT)) & SYSCON0_SEC_CLK_CTRL_SET_GDET0_REFCLK_EN_SET_MASK)

#define SYSCON0_SEC_CLK_CTRL_SET_GDET1_REFCLK_EN_SET_MASK (0x2U)
#define SYSCON0_SEC_CLK_CTRL_SET_GDET1_REFCLK_EN_SET_SHIFT (1U)
/*! GDET1_REFCLK_EN_SET - GDET1 Reference Clock Enable Set
 *  0b0..Has no effect
 *  0b1..Sets SEC_CLK_CTRL[GDET1_REFCLK_EN] to 1
 */
#define SYSCON0_SEC_CLK_CTRL_SET_GDET1_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_SET_GDET1_REFCLK_EN_SET_SHIFT)) & SYSCON0_SEC_CLK_CTRL_SET_GDET1_REFCLK_EN_SET_MASK)

#define SYSCON0_SEC_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK (0x4U)
#define SYSCON0_SEC_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT (2U)
/*! TRNG_REFCLK_EN_SET - TRNG Reference Clock Enable Set
 *  0b0..Has no effect
 *  0b1..Sets SEC_CLK_CTRL[TRNG_REFCLK_EN] to 1
 */
#define SYSCON0_SEC_CLK_CTRL_SET_TRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT)) & SYSCON0_SEC_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK)

#define SYSCON0_SEC_CLK_CTRL_SET_ELS_CLK_EN_SET_MASK (0x8U)
#define SYSCON0_SEC_CLK_CTRL_SET_ELS_CLK_EN_SET_SHIFT (3U)
/*! ELS_CLK_EN_SET - ELS Clock Enable Set
 *  0b0..Has no effect
 *  0b1..Sets SEC_CLK_CTRL[ELS_CLK_EN] to 1
 */
#define SYSCON0_SEC_CLK_CTRL_SET_ELS_CLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_SET_ELS_CLK_EN_SET_SHIFT)) & SYSCON0_SEC_CLK_CTRL_SET_ELS_CLK_EN_SET_MASK)

#define SYSCON0_SEC_CLK_CTRL_SET_ITRC_CLK_EN_SET_MASK (0x10U)
#define SYSCON0_SEC_CLK_CTRL_SET_ITRC_CLK_EN_SET_SHIFT (4U)
/*! ITRC_CLK_EN_SET - ITRC Clock Enable Set
 *  0b0..Has no effect
 *  0b1..Sets SEC_CLK_CTRL[ITRC_CLK_EN] to 1
 */
#define SYSCON0_SEC_CLK_CTRL_SET_ITRC_CLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_SET_ITRC_CLK_EN_SET_SHIFT)) & SYSCON0_SEC_CLK_CTRL_SET_ITRC_CLK_EN_SET_MASK)
/*! @} */

/*! @name SEC_CLK_CTRL_CLR - Security Clock Control Clear */
/*! @{ */

#define SYSCON0_SEC_CLK_CTRL_CLR_GDET0_REFCLK_EN_CLR_MASK (0x1U)
#define SYSCON0_SEC_CLK_CTRL_CLR_GDET0_REFCLK_EN_CLR_SHIFT (0U)
/*! GDET0_REFCLK_EN_CLR - GDET0 Reference Clock Enable Clear
 *  0b0..Has no effect
 *  0b1..Clears SEC_CLK_CTRL[GDET0_REFCLK_EN] to 0
 */
#define SYSCON0_SEC_CLK_CTRL_CLR_GDET0_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_CLR_GDET0_REFCLK_EN_CLR_SHIFT)) & SYSCON0_SEC_CLK_CTRL_CLR_GDET0_REFCLK_EN_CLR_MASK)

#define SYSCON0_SEC_CLK_CTRL_CLR_GDET1_REFCLK_EN_CLR_MASK (0x2U)
#define SYSCON0_SEC_CLK_CTRL_CLR_GDET1_REFCLK_EN_CLR_SHIFT (1U)
/*! GDET1_REFCLK_EN_CLR - GDET1 Reference Clock Enable Clear
 *  0b0..Has no effect
 *  0b1..Clears SEC_CLK_CTRL[GDET1_REFCLK_EN] to 0
 */
#define SYSCON0_SEC_CLK_CTRL_CLR_GDET1_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_CLR_GDET1_REFCLK_EN_CLR_SHIFT)) & SYSCON0_SEC_CLK_CTRL_CLR_GDET1_REFCLK_EN_CLR_MASK)

#define SYSCON0_SEC_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK (0x4U)
#define SYSCON0_SEC_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT (2U)
/*! TRNG_REFCLK_EN_CLR - TRNG Reference Clock Enable Clear
 *  0b0..Has no effect
 *  0b1..Clears SEC_CLK_CTRL[TRNG_REFCLK_EN] to 0
 */
#define SYSCON0_SEC_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON0_SEC_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK)

#define SYSCON0_SEC_CLK_CTRL_CLR_ELS_CLK_EN_CLR_MASK (0x8U)
#define SYSCON0_SEC_CLK_CTRL_CLR_ELS_CLK_EN_CLR_SHIFT (3U)
/*! ELS_CLK_EN_CLR - ELS Clock Enable Clear
 *  0b0..Has no effect
 *  0b1..Clears SEC_CLK_CTRL[ELS_CLK_EN] to 0
 */
#define SYSCON0_SEC_CLK_CTRL_CLR_ELS_CLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_CLR_ELS_CLK_EN_CLR_SHIFT)) & SYSCON0_SEC_CLK_CTRL_CLR_ELS_CLK_EN_CLR_MASK)

#define SYSCON0_SEC_CLK_CTRL_CLR_ITRC_CLK_EN_CLR_MASK (0x10U)
#define SYSCON0_SEC_CLK_CTRL_CLR_ITRC_CLK_EN_CLR_SHIFT (4U)
/*! ITRC_CLK_EN_CLR - ITRC Clock Enable Clear
 *  0b0..Has no effect
 *  0b1..Clears SEC_CLK_CTRL[ITRC_CLK_EN] to 0
 */
#define SYSCON0_SEC_CLK_CTRL_CLR_ITRC_CLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_CLK_CTRL_CLR_ITRC_CLK_EN_CLR_SHIFT)) & SYSCON0_SEC_CLK_CTRL_CLR_ITRC_CLK_EN_CLR_MASK)
/*! @} */

/*! @name GDET_CTRL - GDET0 Control..GDET1 Control */
/*! @{ */

#define SYSCON0_GDET_CTRL_GDET_EVTCNT_CLR_MASK   (0x1U)
#define SYSCON0_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT  (0U)
/*! GDET_EVTCNT_CLR - GDET Event Counter Clear
 *  0b1..Clears
 *  0b0..Not clear
 */
#define SYSCON0_GDET_CTRL_GDET_EVTCNT_CLR(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT)) & SYSCON0_GDET_CTRL_GDET_EVTCNT_CLR_MASK)

#define SYSCON0_GDET_CTRL_GDET_ERR_CLR_MASK      (0x2U)
#define SYSCON0_GDET_CTRL_GDET_ERR_CLR_SHIFT     (1U)
/*! GDET_ERR_CLR - GDET Error Clear
 *  0b1..Clears
 *  0b0..Not clear
 */
#define SYSCON0_GDET_CTRL_GDET_ERR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_GDET_CTRL_GDET_ERR_CLR_SHIFT)) & SYSCON0_GDET_CTRL_GDET_ERR_CLR_MASK)

#define SYSCON0_GDET_CTRL_GDET_ISO_SW_MASK       (0xCU)
#define SYSCON0_GDET_CTRL_GDET_ISO_SW_SHIFT      (2U)
/*! GDET_ISO_SW - GDET Isolation Control
 *  0b00..Disabled
 *  0b01..Disabled
 *  0b10..Enabled
 *  0b11..Disabled
 */
#define SYSCON0_GDET_CTRL_GDET_ISO_SW(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_GDET_CTRL_GDET_ISO_SW_SHIFT)) & SYSCON0_GDET_CTRL_GDET_ISO_SW_MASK)

#define SYSCON0_GDET_CTRL_EVENT_CNT_MASK         (0xFF0000U)
#define SYSCON0_GDET_CTRL_EVENT_CNT_SHIFT        (16U)
/*! EVENT_CNT - Event Count Value */
#define SYSCON0_GDET_CTRL_EVENT_CNT(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON0_GDET_CTRL_EVENT_CNT_SHIFT)) & SYSCON0_GDET_CTRL_EVENT_CNT_MASK)

#define SYSCON0_GDET_CTRL_POS_SYNC_MASK          (0x1000000U)
#define SYSCON0_GDET_CTRL_POS_SYNC_SHIFT         (24U)
/*! POS_SYNC - Positive Glitch Detection
 *  0b0..Not detected
 *  0b1..Detected
 */
#define SYSCON0_GDET_CTRL_POS_SYNC(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_GDET_CTRL_POS_SYNC_SHIFT)) & SYSCON0_GDET_CTRL_POS_SYNC_MASK)

#define SYSCON0_GDET_CTRL_NEG_SYNC_MASK          (0x2000000U)
#define SYSCON0_GDET_CTRL_NEG_SYNC_SHIFT         (25U)
/*! NEG_SYNC - Negative Glitch Detection
 *  0b0..Not detected
 *  0b1..Detected
 */
#define SYSCON0_GDET_CTRL_NEG_SYNC(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_GDET_CTRL_NEG_SYNC_SHIFT)) & SYSCON0_GDET_CTRL_NEG_SYNC_MASK)

#define SYSCON0_GDET_CTRL_EVENT_CLR_FLAG_MASK    (0x4000000U)
#define SYSCON0_GDET_CTRL_EVENT_CLR_FLAG_SHIFT   (26U)
/*! EVENT_CLR_FLAG - Event Counter Clear
 *  0b0..Not cleared
 *  0b1..Cleared
 */
#define SYSCON0_GDET_CTRL_EVENT_CLR_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_GDET_CTRL_EVENT_CLR_FLAG_SHIFT)) & SYSCON0_GDET_CTRL_EVENT_CLR_FLAG_MASK)
/*! @} */

/* The count of SYSCON0_GDET_CTRL */
#define SYSCON0_GDET_CTRL_COUNT                  (2U)

/*! @name NMISRC - NMI Source Select */
/*! @{ */

#define SYSCON0_NMISRC_IRQCPU0_MASK              (0xFFU)
#define SYSCON0_NMISRC_IRQCPU0_SHIFT             (0U)
/*! IRQCPU0 - The IRQ number of the interrupt that acts as the NMI for CPU0, if enabled by NMIENCPU0 */
#define SYSCON0_NMISRC_IRQCPU0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON0_NMISRC_IRQCPU0_SHIFT)) & SYSCON0_NMISRC_IRQCPU0_MASK)

#define SYSCON0_NMISRC_NMIENCPU0_MASK            (0x80000000U)
#define SYSCON0_NMISRC_NMIENCPU0_SHIFT           (31U)
/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0
 *  0b1..Enables
 *  0b0..Disables
 */
#define SYSCON0_NMISRC_NMIENCPU0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON0_NMISRC_NMIENCPU0_SHIFT)) & SYSCON0_NMISRC_NMIENCPU0_MASK)
/*! @} */

/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */
/*! @{ */

#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U)
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U)
/*! CTIMER0_CLK_EN - CTIMER0 Function Clock Enable
 *  0b1..Enables
 *  0b0..Disables
 */
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON0_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK)

#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U)
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U)
/*! CTIMER1_CLK_EN - CTIMER1 Function Clock Enable
 *  0b1..Enables
 *  0b0..Disables
 */
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON0_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK)

#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U)
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U)
/*! CTIMER2_CLK_EN - CTIMER2 Function Clock Enable
 *  0b1..Enables
 *  0b0..Disables
 */
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON0_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK)

#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U)
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U)
/*! CTIMER3_CLK_EN - CTIMER3 Function Clock Enable
 *  0b1..Enables
 *  0b0..Disables
 */
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON0_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK)

#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U)
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U)
/*! CTIMER4_CLK_EN - CTIMER4 Function Clock Enable
 *  0b1..Enables
 *  0b0..Disables
 */
#define SYSCON0_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON0_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK)
/*! @} */

/*! @name FUSEACSTATUS - Fuse Access Status */
/*! @{ */

#define SYSCON0_FUSEACSTATUS_FUSE_CALIB_MASK     (0x1U)
#define SYSCON0_FUSEACSTATUS_FUSE_CALIB_SHIFT    (0U)
/*! FUSE_CALIB - Fuse Calibrate Flag
 *  0b0..Not calibrated
 *  0b1..Calibrated
 */
#define SYSCON0_FUSEACSTATUS_FUSE_CALIB(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_FUSEACSTATUS_FUSE_CALIB_SHIFT)) & SYSCON0_FUSEACSTATUS_FUSE_CALIB_MASK)

#define SYSCON0_FUSEACSTATUS_STATUS_BUSY_MASK    (0x2U)
#define SYSCON0_FUSEACSTATUS_STATUS_BUSY_SHIFT   (1U)
/*! STATUS_BUSY - OCOTP Status
 *  0b0..Not busy
 *  0b1..Busy
 */
#define SYSCON0_FUSEACSTATUS_STATUS_BUSY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_FUSEACSTATUS_STATUS_BUSY_SHIFT)) & SYSCON0_FUSEACSTATUS_STATUS_BUSY_MASK)
/*! @} */

/*! @name AHBMATPRIO - Bus Matrix Priority */
/*! @{ */

#define SYSCON0_AHBMATPRIO_MBUS_M0_MASK          (0x3U)
#define SYSCON0_AHBMATPRIO_MBUS_M0_SHIFT         (0U)
/*! MBUS_M0 - M-Bus M0 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M0_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M0_MASK)

#define SYSCON0_AHBMATPRIO_MBUS_M1_MASK          (0xCU)
#define SYSCON0_AHBMATPRIO_MBUS_M1_SHIFT         (2U)
/*! MBUS_M1 - M-Bus M1 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M1_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M1_MASK)

#define SYSCON0_AHBMATPRIO_MBUS_M2_MASK          (0x30U)
#define SYSCON0_AHBMATPRIO_MBUS_M2_SHIFT         (4U)
/*! MBUS_M2 - M-Bus M2 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M2_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M2_MASK)

#define SYSCON0_AHBMATPRIO_MBUS_M3_MASK          (0xC0U)
#define SYSCON0_AHBMATPRIO_MBUS_M3_SHIFT         (6U)
/*! MBUS_M3 - M-Bus M3 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M3_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M3_MASK)

#define SYSCON0_AHBMATPRIO_MBUS_M4_MASK          (0x300U)
#define SYSCON0_AHBMATPRIO_MBUS_M4_SHIFT         (8U)
/*! MBUS_M4 - M-Bus M4 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M4(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M4_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M4_MASK)

#define SYSCON0_AHBMATPRIO_MBUS_M5_MASK          (0xC00U)
#define SYSCON0_AHBMATPRIO_MBUS_M5_SHIFT         (10U)
/*! MBUS_M5 - M-Bus M5 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M5(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M5_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M5_MASK)

#define SYSCON0_AHBMATPRIO_MBUS_M6_MASK          (0x3000U)
#define SYSCON0_AHBMATPRIO_MBUS_M6_SHIFT         (12U)
/*! MBUS_M6 - M-Bus M6 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M6(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M6_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M6_MASK)

#define SYSCON0_AHBMATPRIO_MBUS_M7_MASK          (0xC000U)
#define SYSCON0_AHBMATPRIO_MBUS_M7_SHIFT         (14U)
/*! MBUS_M7 - M-Bus M7 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M7(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M7_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M7_MASK)

#define SYSCON0_AHBMATPRIO_MBUS_M8_MASK          (0x30000U)
#define SYSCON0_AHBMATPRIO_MBUS_M8_SHIFT         (16U)
/*! MBUS_M8 - M-Bus M8 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_MBUS_M8(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_MBUS_M8_SHIFT)) & SYSCON0_AHBMATPRIO_MBUS_M8_MASK)

#define SYSCON0_AHBMATPRIO_PBUS_M0_MASK          (0x3000000U)
#define SYSCON0_AHBMATPRIO_PBUS_M0_SHIFT         (24U)
/*! PBUS_M0 - P-Bus M0 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_PBUS_M0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_PBUS_M0_SHIFT)) & SYSCON0_AHBMATPRIO_PBUS_M0_MASK)

#define SYSCON0_AHBMATPRIO_PBUS_M1_MASK          (0xC000000U)
#define SYSCON0_AHBMATPRIO_PBUS_M1_SHIFT         (26U)
/*! PBUS_M1 - P-Bus M1 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_PBUS_M1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_PBUS_M1_SHIFT)) & SYSCON0_AHBMATPRIO_PBUS_M1_MASK)

#define SYSCON0_AHBMATPRIO_PBUS_M2_MASK          (0x30000000U)
#define SYSCON0_AHBMATPRIO_PBUS_M2_SHIFT         (28U)
/*! PBUS_M2 - P-Bus M2 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_PBUS_M2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_PBUS_M2_SHIFT)) & SYSCON0_AHBMATPRIO_PBUS_M2_MASK)

#define SYSCON0_AHBMATPRIO_PBUS_M3_MASK          (0xC0000000U)
#define SYSCON0_AHBMATPRIO_PBUS_M3_SHIFT         (30U)
/*! PBUS_M3 - P-Bus M3 Priority
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define SYSCON0_AHBMATPRIO_PBUS_M3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_AHBMATPRIO_PBUS_M3_SHIFT)) & SYSCON0_AHBMATPRIO_PBUS_M3_MASK)
/*! @} */

/*! @name RXEVPULSEGEN - Receive Event Pulse Generator */
/*! @{ */

#define SYSCON0_RXEVPULSEGEN_RXEVPULSEGEN_MASK   (0x1U)
#define SYSCON0_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT  (0U)
/*! RXEVPULSEGEN - Receive Event Pulse Generator
 *  0b0..No effect
 *  0b1..Pulse receive event high for one cycle
 */
#define SYSCON0_RXEVPULSEGEN_RXEVPULSEGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT)) & SYSCON0_RXEVPULSEGEN_RXEVPULSEGEN_MASK)
/*! @} */

/*! @name LATCHED_CM33_TXEV - Latched Cortex-M33 Transmit Event */
/*! @{ */

#define SYSCON0_LATCHED_CM33_TXEV_LATCHED_TXEV_MASK (0x1U)
#define SYSCON0_LATCHED_CM33_TXEV_LATCHED_TXEV_SHIFT (0U)
/*! LATCHED_TXEV - Cortex-M33 Transmit Event
 *  0b0..No effect
 *  0b1..Clear the event flag
 */
#define SYSCON0_LATCHED_CM33_TXEV_LATCHED_TXEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_LATCHED_CM33_TXEV_LATCHED_TXEV_SHIFT)) & SYSCON0_LATCHED_CM33_TXEV_LATCHED_TXEV_MASK)
/*! @} */

/*! @name SYSTEM_STICK_CALIB - System Secure Tick Calibration */
/*! @{ */

#define SYSCON0_SYSTEM_STICK_CALIB_TENMS_MASK    (0xFFFFFFU)
#define SYSCON0_SYSTEM_STICK_CALIB_TENMS_SHIFT   (0U)
/*! TENMS - Ten Milliseconds */
#define SYSCON0_SYSTEM_STICK_CALIB_TENMS(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_SYSTEM_STICK_CALIB_TENMS_SHIFT)) & SYSCON0_SYSTEM_STICK_CALIB_TENMS_MASK)

#define SYSCON0_SYSTEM_STICK_CALIB_SKEW_MASK     (0x1000000U)
#define SYSCON0_SYSTEM_STICK_CALIB_SKEW_SHIFT    (24U)
/*! SKEW - Skew
 *  0b0..Exact
 *  0b1..Inexact, or not given
 */
#define SYSCON0_SYSTEM_STICK_CALIB_SKEW(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_SYSTEM_STICK_CALIB_SKEW_SHIFT)) & SYSCON0_SYSTEM_STICK_CALIB_SKEW_MASK)

#define SYSCON0_SYSTEM_STICK_CALIB_NOREF_MASK    (0x2000000U)
#define SYSCON0_SYSTEM_STICK_CALIB_NOREF_SHIFT   (25U)
/*! NOREF - No Reference Clock
 *  0b0..Provides
 *  0b1..Not provide
 */
#define SYSCON0_SYSTEM_STICK_CALIB_NOREF(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_SYSTEM_STICK_CALIB_NOREF_SHIFT)) & SYSCON0_SYSTEM_STICK_CALIB_NOREF_MASK)
/*! @} */

/*! @name SYSTEM_NSTICK_CALIB - System Non-Secure Tick Calibration */
/*! @{ */

#define SYSCON0_SYSTEM_NSTICK_CALIB_TENMS_MASK   (0xFFFFFFU)
#define SYSCON0_SYSTEM_NSTICK_CALIB_TENMS_SHIFT  (0U)
/*! TENMS - Ten Milliseconds */
#define SYSCON0_SYSTEM_NSTICK_CALIB_TENMS(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_SYSTEM_NSTICK_CALIB_TENMS_SHIFT)) & SYSCON0_SYSTEM_NSTICK_CALIB_TENMS_MASK)

#define SYSCON0_SYSTEM_NSTICK_CALIB_SKEW_MASK    (0x1000000U)
#define SYSCON0_SYSTEM_NSTICK_CALIB_SKEW_SHIFT   (24U)
/*! SKEW - Skew
 *  0b0..Exact
 *  0b1..Inexact, or not given
 */
#define SYSCON0_SYSTEM_NSTICK_CALIB_SKEW(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_SYSTEM_NSTICK_CALIB_SKEW_SHIFT)) & SYSCON0_SYSTEM_NSTICK_CALIB_SKEW_MASK)

#define SYSCON0_SYSTEM_NSTICK_CALIB_NOREF_MASK   (0x2000000U)
#define SYSCON0_SYSTEM_NSTICK_CALIB_NOREF_SHIFT  (25U)
/*! NOREF - No Reference Clock
 *  0b0..Provides
 *  0b1..Not provide
 */
#define SYSCON0_SYSTEM_NSTICK_CALIB_NOREF(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_SYSTEM_NSTICK_CALIB_NOREF_SHIFT)) & SYSCON0_SYSTEM_NSTICK_CALIB_NOREF_MASK)
/*! @} */

/*! @name CPU0_STATUS - CPU0 Status */
/*! @{ */

#define SYSCON0_CPU0_STATUS_CPU0_LOCKUP_MASK     (0x1U)
#define SYSCON0_CPU0_STATUS_CPU0_LOCKUP_SHIFT    (0U)
/*! CPU0_LOCKUP - CPU0 Lockup State
 *  0b1..In lockup
 *  0b0..Not in lockup
 */
#define SYSCON0_CPU0_STATUS_CPU0_LOCKUP(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_CPU0_STATUS_CPU0_LOCKUP_SHIFT)) & SYSCON0_CPU0_STATUS_CPU0_LOCKUP_MASK)
/*! @} */

/*! @name GPIO_PSYNC - GPIO Synchronization Stages */
/*! @{ */

#define SYSCON0_GPIO_PSYNC_PSYNC_MASK            (0x1U)
#define SYSCON0_GPIO_PSYNC_PSYNC_SHIFT           (0U)
/*! PSYNC - Synchronization Stage Setting
 *  0b0..2-stage sync
 *  0b1..1-stage sync
 */
#define SYSCON0_GPIO_PSYNC_PSYNC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON0_GPIO_PSYNC_PSYNC_SHIFT)) & SYSCON0_GPIO_PSYNC_PSYNC_MASK)
/*! @} */

/*! @name AUTOCLKGATEOVERRIDE0 - Automatic Clock Gate Override */
/*! @{ */

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION0_MASK (0x1U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION0_SHIFT (0U)
/*! PARTITION0 - Partition 0
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION0_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION0_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION1_MASK (0x2U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION1_SHIFT (1U)
/*! PARTITION1 - Partition 1
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION1_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION1_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION2_MASK (0x4U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION2_SHIFT (2U)
/*! PARTITION2 - Partition 2
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION2_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION2_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION3_MASK (0x8U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION3_SHIFT (3U)
/*! PARTITION3 - Partition 3
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION3_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION3_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION4_MASK (0x10U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION4_SHIFT (4U)
/*! PARTITION4 - Partition 4
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION4_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION4_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION5_MASK (0x20U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION5_SHIFT (5U)
/*! PARTITION5 - Partition 5
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION5_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION5_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION6_MASK (0x40U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION6_SHIFT (6U)
/*! PARTITION6 - Partition 6
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION6_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION6_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION7_MASK (0x80U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION7_SHIFT (7U)
/*! PARTITION7 - Partition 7
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION7_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION7_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION8_MASK (0x100U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION8_SHIFT (8U)
/*! PARTITION8 - Partition 8
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION8_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION8_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION9_MASK (0x200U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION9_SHIFT (9U)
/*! PARTITION9 - Partition 9
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION9_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION9_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION10_MASK (0x400U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION10_SHIFT (10U)
/*! PARTITION10 - Partition 10
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION10_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION10_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION11_MASK (0x800U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION11_SHIFT (11U)
/*! PARTITION11 - Partition 11
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION11(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION11_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION11_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION12_MASK (0x1000U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION12_SHIFT (12U)
/*! PARTITION12 - Partition 12
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION12(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION12_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION12_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION13_MASK (0x2000U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION13_SHIFT (13U)
/*! PARTITION13 - Partition 13
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION13(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION13_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION13_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION14_MASK (0x4000U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION14_SHIFT (14U)
/*! PARTITION14 - Partition 14
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION14(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION14_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION14_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION15_MASK (0x8000U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION15_SHIFT (15U)
/*! PARTITION15 - Partition 15
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION15(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION15_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION15_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION16_MASK (0x10000U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION16_SHIFT (16U)
/*! PARTITION16 - Partition 16
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION16_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION16_MASK)

#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION17_MASK (0x20000U)
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION17_SHIFT (17U)
/*! PARTITION17 - Partition 17
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION17(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION17_SHIFT)) & SYSCON0_AUTOCLKGATEOVERRIDE0_PARTITION17_MASK)
/*! @} */

/*! @name SRAM_CLKGATE_CTRL - SRAM Clock Gating Control */
/*! @{ */

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION0_MASK (0x1U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION0_SHIFT (0U)
/*! PARTITION0 - Partition 0
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION0_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION0_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION1_MASK (0x2U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION1_SHIFT (1U)
/*! PARTITION1 - Partition 1
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION1(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION1_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION1_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION2_MASK (0x4U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION2_SHIFT (2U)
/*! PARTITION2 - Partition 2
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION2(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION2_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION2_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION3_MASK (0x8U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION3_SHIFT (3U)
/*! PARTITION3 - Partition 3
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION3(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION3_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION3_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION4_MASK (0x10U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION4_SHIFT (4U)
/*! PARTITION4 - Partition 4
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION4(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION4_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION4_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION5_MASK (0x20U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION5_SHIFT (5U)
/*! PARTITION5 - Partition 5
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION5(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION5_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION5_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION6_MASK (0x40U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION6_SHIFT (6U)
/*! PARTITION6 - Partition 6
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION6(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION6_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION6_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION7_MASK (0x80U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION7_SHIFT (7U)
/*! PARTITION7 - Partition 7
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION7(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION7_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION7_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION8_MASK (0x100U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION8_SHIFT (8U)
/*! PARTITION8 - Partition 8
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION8(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION8_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION8_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION9_MASK (0x200U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION9_SHIFT (9U)
/*! PARTITION9 - Partition 9
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION9(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION9_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION9_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION10_MASK (0x400U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION10_SHIFT (10U)
/*! PARTITION10 - Partition 10
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION10_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION10_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION11_MASK (0x800U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION11_SHIFT (11U)
/*! PARTITION11 - Partition 11
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION11(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION11_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION11_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION12_MASK (0x1000U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION12_SHIFT (12U)
/*! PARTITION12 - Partition 12
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION12(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION12_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION12_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION13_MASK (0x2000U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION13_SHIFT (13U)
/*! PARTITION13 - Partition 13
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION13(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION13_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION13_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION14_MASK (0x4000U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION14_SHIFT (14U)
/*! PARTITION14 - Partition 14
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION14(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION14_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION14_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION15_MASK (0x8000U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION15_SHIFT (15U)
/*! PARTITION15 - Partition 15
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION15(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION15_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION15_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION16_MASK (0x10000U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION16_SHIFT (16U)
/*! PARTITION16 - Partition 16
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION16_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION16_MASK)

#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION17_MASK (0x20000U)
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION17_SHIFT (17U)
/*! PARTITION17 - Partition 17
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON0_SRAM_CLKGATE_CTRL_PARTITION17(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_SRAM_CLKGATE_CTRL_PARTITION17_SHIFT)) & SYSCON0_SRAM_CLKGATE_CTRL_PARTITION17_MASK)
/*! @} */

/*! @name OCOTP_MEM_CTL - OCOTP Memory Control */
/*! @{ */

#define SYSCON0_OCOTP_MEM_CTL_SRAM_WLPD_MASK     (0x80U)
#define SYSCON0_OCOTP_MEM_CTL_SRAM_WLPD_SHIFT    (7U)
/*! SRAM_WLPD - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_OCOTP_MEM_CTL_SRAM_WLPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_OCOTP_MEM_CTL_SRAM_WLPD_SHIFT)) & SYSCON0_OCOTP_MEM_CTL_SRAM_WLPD_MASK)

#define SYSCON0_OCOTP_MEM_CTL_SRAM_IG_MASK       (0x100U)
#define SYSCON0_OCOTP_MEM_CTL_SRAM_IG_SHIFT      (8U)
/*! SRAM_IG - SRAM Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_OCOTP_MEM_CTL_SRAM_IG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_OCOTP_MEM_CTL_SRAM_IG_SHIFT)) & SYSCON0_OCOTP_MEM_CTL_SRAM_IG_MASK)
/*! @} */

/*! @name ELS_MEM_CTL - ELS Memory Control */
/*! @{ */

#define SYSCON0_ELS_MEM_CTL_MEM_WLPD_MASK        (0x80U)
#define SYSCON0_ELS_MEM_CTL_MEM_WLPD_SHIFT       (7U)
/*! MEM_WLPD - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_ELS_MEM_CTL_MEM_WLPD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_MEM_CTL_MEM_WLPD_SHIFT)) & SYSCON0_ELS_MEM_CTL_MEM_WLPD_MASK)

#define SYSCON0_ELS_MEM_CTL_MEM_IG_MASK          (0x100U)
#define SYSCON0_ELS_MEM_CTL_MEM_IG_SHIFT         (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_ELS_MEM_CTL_MEM_IG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_MEM_CTL_MEM_IG_SHIFT)) & SYSCON0_ELS_MEM_CTL_MEM_IG_MASK)
/*! @} */

/*! @name MMU0_MEM_CTRL - MMU0 Memory Control */
/*! @{ */

#define SYSCON0_MMU0_MEM_CTRL_MEM_STDBY_MASK     (0x80U)
#define SYSCON0_MMU0_MEM_CTRL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_MMU0_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_MMU0_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_MMU0_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_MMU0_MEM_CTRL_MEM_IG_MASK        (0x100U)
#define SYSCON0_MMU0_MEM_CTRL_MEM_IG_SHIFT       (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_MMU0_MEM_CTRL_MEM_IG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_MMU0_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON0_MMU0_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name EDMA0_MEM_CTRL - eDMA0 Memory Control */
/*! @{ */

#define SYSCON0_EDMA0_MEM_CTRL_PWR_STDBY_MASK    (0x80U)
#define SYSCON0_EDMA0_MEM_CTRL_PWR_STDBY_SHIFT   (7U)
/*! PWR_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_EDMA0_MEM_CTRL_PWR_STDBY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_MEM_CTRL_PWR_STDBY_SHIFT)) & SYSCON0_EDMA0_MEM_CTRL_PWR_STDBY_MASK)

#define SYSCON0_EDMA0_MEM_CTRL_PWR_IG_MASK       (0x100U)
#define SYSCON0_EDMA0_MEM_CTRL_PWR_IG_SHIFT      (8U)
/*! PWR_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_EDMA0_MEM_CTRL_PWR_IG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_MEM_CTRL_PWR_IG_SHIFT)) & SYSCON0_EDMA0_MEM_CTRL_PWR_IG_MASK)
/*! @} */

/*! @name EDMA1_MEM_CTRL - eDMA1 Memory Control */
/*! @{ */

#define SYSCON0_EDMA1_MEM_CTRL_PWR_STDBY_MASK    (0x80U)
#define SYSCON0_EDMA1_MEM_CTRL_PWR_STDBY_SHIFT   (7U)
/*! PWR_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_EDMA1_MEM_CTRL_PWR_STDBY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_MEM_CTRL_PWR_STDBY_SHIFT)) & SYSCON0_EDMA1_MEM_CTRL_PWR_STDBY_MASK)

#define SYSCON0_EDMA1_MEM_CTRL_PWR_IG_MASK       (0x100U)
#define SYSCON0_EDMA1_MEM_CTRL_PWR_IG_SHIFT      (8U)
/*! PWR_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_EDMA1_MEM_CTRL_PWR_IG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_MEM_CTRL_PWR_IG_SHIFT)) & SYSCON0_EDMA1_MEM_CTRL_PWR_IG_MASK)
/*! @} */

/*! @name ETF_MEM_CTRL - ETF Memory Control */
/*! @{ */

#define SYSCON0_ETF_MEM_CTRL_MEM_STDBY_MASK      (0x80U)
#define SYSCON0_ETF_MEM_CTRL_MEM_STDBY_SHIFT     (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_ETF_MEM_CTRL_MEM_STDBY(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_ETF_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_ETF_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_ETF_MEM_CTRL_MEM_IG_MASK         (0x100U)
#define SYSCON0_ETF_MEM_CTRL_MEM_IG_SHIFT        (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_ETF_MEM_CTRL_MEM_IG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON0_ETF_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON0_ETF_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name MMU1_MEM_CTRL - MMU1 Memory Control */
/*! @{ */

#define SYSCON0_MMU1_MEM_CTRL_MEM_STDBY_MASK     (0x80U)
#define SYSCON0_MMU1_MEM_CTRL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_MMU1_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_MMU1_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_MMU1_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_MMU1_MEM_CTRL_MEM_IG_MASK        (0x100U)
#define SYSCON0_MMU1_MEM_CTRL_MEM_IG_SHIFT       (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_MMU1_MEM_CTRL_MEM_IG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_MMU1_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON0_MMU1_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name XSPI0_MEM_CTRL - XSPI0 Memory Control */
/*! @{ */

#define SYSCON0_XSPI0_MEM_CTRL_MEM_STDBY_MASK    (0x80U)
#define SYSCON0_XSPI0_MEM_CTRL_MEM_STDBY_SHIFT   (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI0_MEM_CTRL_MEM_STDBY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI0_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_XSPI0_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_XSPI0_MEM_CTRL_MEM_WIG_MASK      (0x100U)
#define SYSCON0_XSPI0_MEM_CTRL_MEM_WIG_SHIFT     (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI0_MEM_CTRL_MEM_WIG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI0_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON0_XSPI0_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON0_XSPI0_MEM_CTRL_MEM_RIG_MASK      (0x200U)
#define SYSCON0_XSPI0_MEM_CTRL_MEM_RIG_SHIFT     (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI0_MEM_CTRL_MEM_RIG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI0_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON0_XSPI0_MEM_CTRL_MEM_RIG_MASK)
/*! @} */

/*! @name XSPI1_MEM_CTRL - XSPI1 Memory Control */
/*! @{ */

#define SYSCON0_XSPI1_MEM_CTRL_MEM_STDBY_MASK    (0x80U)
#define SYSCON0_XSPI1_MEM_CTRL_MEM_STDBY_SHIFT   (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI1_MEM_CTRL_MEM_STDBY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI1_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_XSPI1_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_XSPI1_MEM_CTRL_MEM_WIG_MASK      (0x100U)
#define SYSCON0_XSPI1_MEM_CTRL_MEM_WIG_SHIFT     (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI1_MEM_CTRL_MEM_WIG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI1_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON0_XSPI1_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON0_XSPI1_MEM_CTRL_MEM_RIG_MASK      (0x200U)
#define SYSCON0_XSPI1_MEM_CTRL_MEM_RIG_SHIFT     (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI1_MEM_CTRL_MEM_RIG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI1_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON0_XSPI1_MEM_CTRL_MEM_RIG_MASK)
/*! @} */

/*! @name XSPI0_DATA_MEM_CTRL - XSPI0 Data Memory Control */
/*! @{ */

#define SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_STDBY_MASK (0x80U)
#define SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_STDBY_SHIFT (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_IG_MASK  (0x100U)
#define SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_IG_SHIFT (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_IG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON0_XSPI0_DATA_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name XSPI1_DATA_MEM_CTRL - XSPI1 Data Memory Control */
/*! @{ */

#define SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_STDBY_MASK (0x80U)
#define SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_STDBY_SHIFT (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_IG_MASK  (0x100U)
#define SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_IG_SHIFT (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_IG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON0_XSPI1_DATA_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name NPU_MEM_CTRL - NPU Memory Control */
/*! @{ */

#define SYSCON0_NPU_MEM_CTRL_PWR_STDBY_MASK      (0x80U)
#define SYSCON0_NPU_MEM_CTRL_PWR_STDBY_SHIFT     (7U)
/*! PWR_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_NPU_MEM_CTRL_PWR_STDBY(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_NPU_MEM_CTRL_PWR_STDBY_SHIFT)) & SYSCON0_NPU_MEM_CTRL_PWR_STDBY_MASK)

#define SYSCON0_NPU_MEM_CTRL_PWR_IG_MASK         (0x100U)
#define SYSCON0_NPU_MEM_CTRL_PWR_IG_SHIFT        (8U)
/*! PWR_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_NPU_MEM_CTRL_PWR_IG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON0_NPU_MEM_CTRL_PWR_IG_SHIFT)) & SYSCON0_NPU_MEM_CTRL_PWR_IG_MASK)
/*! @} */

/*! @name PKC0_MEM_CTRL - PKC Memory 0 Control */
/*! @{ */

#define SYSCON0_PKC0_MEM_CTRL_PWR_STDBY_MASK     (0x80U)
#define SYSCON0_PKC0_MEM_CTRL_PWR_STDBY_SHIFT    (7U)
/*! PWR_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_PKC0_MEM_CTRL_PWR_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_PKC0_MEM_CTRL_PWR_STDBY_SHIFT)) & SYSCON0_PKC0_MEM_CTRL_PWR_STDBY_MASK)

#define SYSCON0_PKC0_MEM_CTRL_PWR_IG_MASK        (0x100U)
#define SYSCON0_PKC0_MEM_CTRL_PWR_IG_SHIFT       (8U)
/*! PWR_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_PKC0_MEM_CTRL_PWR_IG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_PKC0_MEM_CTRL_PWR_IG_SHIFT)) & SYSCON0_PKC0_MEM_CTRL_PWR_IG_MASK)
/*! @} */

/*! @name PKC1_MEM_CTRL - PKC Memory 1 Control */
/*! @{ */

#define SYSCON0_PKC1_MEM_CTRL_PWR_STDBY_MASK     (0x80U)
#define SYSCON0_PKC1_MEM_CTRL_PWR_STDBY_SHIFT    (7U)
/*! PWR_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_PKC1_MEM_CTRL_PWR_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_PKC1_MEM_CTRL_PWR_STDBY_SHIFT)) & SYSCON0_PKC1_MEM_CTRL_PWR_STDBY_MASK)

#define SYSCON0_PKC1_MEM_CTRL_PWR_IG_MASK        (0x100U)
#define SYSCON0_PKC1_MEM_CTRL_PWR_IG_SHIFT       (8U)
/*! PWR_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_PKC1_MEM_CTRL_PWR_IG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_PKC1_MEM_CTRL_PWR_IG_SHIFT)) & SYSCON0_PKC1_MEM_CTRL_PWR_IG_MASK)
/*! @} */

/*! @name CM33_MEM_DATA_CTRL - CPU0 Memory Data Control */
/*! @{ */

#define SYSCON0_CM33_MEM_DATA_CTRL_PWR_STDBY_MASK (0x80U)
#define SYSCON0_CM33_MEM_DATA_CTRL_PWR_STDBY_SHIFT (7U)
/*! PWR_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_CM33_MEM_DATA_CTRL_PWR_STDBY(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_CM33_MEM_DATA_CTRL_PWR_STDBY_SHIFT)) & SYSCON0_CM33_MEM_DATA_CTRL_PWR_STDBY_MASK)

#define SYSCON0_CM33_MEM_DATA_CTRL_PWR_IG_MASK   (0x100U)
#define SYSCON0_CM33_MEM_DATA_CTRL_PWR_IG_SHIFT  (8U)
/*! PWR_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_CM33_MEM_DATA_CTRL_PWR_IG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_CM33_MEM_DATA_CTRL_PWR_IG_SHIFT)) & SYSCON0_CM33_MEM_DATA_CTRL_PWR_IG_MASK)
/*! @} */

/*! @name CM33_MEM_TAG_CTRL - CPU0 Memory Tag Control */
/*! @{ */

#define SYSCON0_CM33_MEM_TAG_CTRL_PWR_STDBY_MASK (0x80U)
#define SYSCON0_CM33_MEM_TAG_CTRL_PWR_STDBY_SHIFT (7U)
/*! PWR_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_CM33_MEM_TAG_CTRL_PWR_STDBY(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON0_CM33_MEM_TAG_CTRL_PWR_STDBY_SHIFT)) & SYSCON0_CM33_MEM_TAG_CTRL_PWR_STDBY_MASK)

#define SYSCON0_CM33_MEM_TAG_CTRL_PWR_IG_MASK    (0x100U)
#define SYSCON0_CM33_MEM_TAG_CTRL_PWR_IG_SHIFT   (8U)
/*! PWR_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_CM33_MEM_TAG_CTRL_PWR_IG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_CM33_MEM_TAG_CTRL_PWR_IG_SHIFT)) & SYSCON0_CM33_MEM_TAG_CTRL_PWR_IG_MASK)
/*! @} */

/*! @name HIFI4_MEM_CTL - HiFi4 Memory Control */
/*! @{ */

#define SYSCON0_HIFI4_MEM_CTL_MEM_STDBY_MASK     (0x80U)
#define SYSCON0_HIFI4_MEM_CTL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_HIFI4_MEM_CTL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_HIFI4_MEM_CTL_MEM_STDBY_SHIFT)) & SYSCON0_HIFI4_MEM_CTL_MEM_STDBY_MASK)

#define SYSCON0_HIFI4_MEM_CTL_MEM_IG_MASK        (0x100U)
#define SYSCON0_HIFI4_MEM_CTL_MEM_IG_SHIFT       (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_HIFI4_MEM_CTL_MEM_IG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_HIFI4_MEM_CTL_MEM_IG_SHIFT)) & SYSCON0_HIFI4_MEM_CTL_MEM_IG_MASK)
/*! @} */

/*! @name SAI0_MCLK_CTRL - SAI0-2 MCLK IO Direction Control */
/*! @{ */

#define SYSCON0_SAI0_MCLK_CTRL_SAIMCLKDIR_MASK   (0x1U)
#define SYSCON0_SAI0_MCLK_CTRL_SAIMCLKDIR_SHIFT  (0U)
/*! SAIMCLKDIR - SAI0-2 MCLK Direction Control
 *  0b1..Output
 *  0b0..Input
 */
#define SYSCON0_SAI0_MCLK_CTRL_SAIMCLKDIR(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_SAI0_MCLK_CTRL_SAIMCLKDIR_SHIFT)) & SYSCON0_SAI0_MCLK_CTRL_SAIMCLKDIR_MASK)
/*! @} */

/*! @name XSPI0_TAG_MEM_CTRL - XSPI0 Cache Tag Memory Control */
/*! @{ */

#define SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_STDBY_MASK (0x80U)
#define SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_STDBY_SHIFT (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_STDBY(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_IG_MASK   (0x100U)
#define SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_IG_SHIFT  (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_IG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON0_XSPI0_TAG_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name XSPI1_TAG_MEM_CTRL - XSPI1 Cache Tag Memory Control */
/*! @{ */

#define SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_STDBY_MASK (0x80U)
#define SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_STDBY_SHIFT (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_STDBY(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_IG_MASK   (0x100U)
#define SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_IG_SHIFT  (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_IG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON0_XSPI1_TAG_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name COMP_AUTOGATE_EN - VDD2_COMP Auto Gating Enable */
/*! @{ */

#define SYSCON0_COMP_AUTOGATE_EN_MBUS_EN_MASK    (0x1U)
#define SYSCON0_COMP_AUTOGATE_EN_MBUS_EN_SHIFT   (0U)
/*! MBUS_EN - Automatic Clock Gating Enable for M-bus
 *  0b1..Enables clock gating
 *  0b0..Disables clock gating (continuous clock)
 */
#define SYSCON0_COMP_AUTOGATE_EN_MBUS_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_COMP_AUTOGATE_EN_MBUS_EN_SHIFT)) & SYSCON0_COMP_AUTOGATE_EN_MBUS_EN_MASK)

#define SYSCON0_COMP_AUTOGATE_EN_PBUS_EN_MASK    (0x2U)
#define SYSCON0_COMP_AUTOGATE_EN_PBUS_EN_SHIFT   (1U)
/*! PBUS_EN - Automatic Clock Gating Enable for P-bus
 *  0b1..Enables clock gating
 *  0b0..Disables clock gating (continuous clock)
 */
#define SYSCON0_COMP_AUTOGATE_EN_PBUS_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_COMP_AUTOGATE_EN_PBUS_EN_SHIFT)) & SYSCON0_COMP_AUTOGATE_EN_PBUS_EN_MASK)

#define SYSCON0_COMP_AUTOGATE_EN_BRIDGE_EN_MASK  (0x4U)
#define SYSCON0_COMP_AUTOGATE_EN_BRIDGE_EN_SHIFT (2U)
/*! BRIDGE_EN - Automatic Clock Gating Enable for AHB2APB bridge, AIPS and AXBS
 *  0b1..Enables clock gating
 *  0b0..Disables clock gating (continuous clock)
 */
#define SYSCON0_COMP_AUTOGATE_EN_BRIDGE_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON0_COMP_AUTOGATE_EN_BRIDGE_EN_SHIFT)) & SYSCON0_COMP_AUTOGATE_EN_BRIDGE_EN_MASK)
/*! @} */

/*! @name COMP_DEBUG_HALTED_SEL - VDD2_COMP Debug Halted Select */
/*! @{ */

#define SYSCON0_COMP_DEBUG_HALTED_SEL_WWDT1_SEL_MASK (0x1U)
#define SYSCON0_COMP_DEBUG_HALTED_SEL_WWDT1_SEL_SHIFT (0U)
/*! WWDT1_SEL - WWDT1 Select
 *  0b0..XOCD mode from HiFi4 will be used for WWDT1
 *  0b1..HALTED from CPU0 will be used for WWDT1
 */
#define SYSCON0_COMP_DEBUG_HALTED_SEL_WWDT1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_COMP_DEBUG_HALTED_SEL_WWDT1_SEL_SHIFT)) & SYSCON0_COMP_DEBUG_HALTED_SEL_WWDT1_SEL_MASK)

#define SYSCON0_COMP_DEBUG_HALTED_SEL_CDOG2_SEL_MASK (0x2U)
#define SYSCON0_COMP_DEBUG_HALTED_SEL_CDOG2_SEL_SHIFT (1U)
/*! CDOG2_SEL - CDOG2 Select
 *  0b0..XOCD mode from HiFi4 will be used for CDOG2
 *  0b1..HALTED from CPU0 will be used for CDOG2
 */
#define SYSCON0_COMP_DEBUG_HALTED_SEL_CDOG2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_COMP_DEBUG_HALTED_SEL_CDOG2_SEL_SHIFT)) & SYSCON0_COMP_DEBUG_HALTED_SEL_CDOG2_SEL_MASK)
/*! @} */

/*! @name DSPSTALL - HiFi4 Stall */
/*! @{ */

#define SYSCON0_DSPSTALL_DSPSTALL_MASK           (0x1U)
#define SYSCON0_DSPSTALL_DSPSTALL_SHIFT          (0U)
/*! DSPSTALL - Run and Stall Control
 *  0b0..Run (normal mode)
 *  0b1..Stall mode
 */
#define SYSCON0_DSPSTALL_DSPSTALL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON0_DSPSTALL_DSPSTALL_SHIFT)) & SYSCON0_DSPSTALL_DSPSTALL_MASK)
/*! @} */

/*! @name OCDHALTONRESET - HiFi4 OCDHaltOnReset */
/*! @{ */

#define SYSCON0_OCDHALTONRESET_OCDHALTONRESET_MASK (0x1U)
#define SYSCON0_OCDHALTONRESET_OCDHALTONRESET_SHIFT (0U)
/*! OCDHALTONRESET - OCDHaltOnReset
 *  0b0..Allow normal operation when HiFi4 exits reset (starts fetching and executing instructions from memory)
 *  0b1..Force HiFi4 to enter OCD Halt mode when HiFi4 exits reset
 */
#define SYSCON0_OCDHALTONRESET_OCDHALTONRESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_OCDHALTONRESET_OCDHALTONRESET_SHIFT)) & SYSCON0_OCDHALTONRESET_OCDHALTONRESET_MASK)
/*! @} */

/*! @name HIFI4_GPR0 - HiFi4 General Purpose Register 0 */
/*! @{ */

#define SYSCON0_HIFI4_GPR0_PFAULTINFOVLD_MASK    (0x1U)
#define SYSCON0_HIFI4_GPR0_PFAULTINFOVLD_SHIFT   (0U)
/*! PFAULTINFOVLD - PFaultInfoValid
 *  0b1..Asserted
 *  0b0..Not asserted
 */
#define SYSCON0_HIFI4_GPR0_PFAULTINFOVLD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_HIFI4_GPR0_PFAULTINFOVLD_SHIFT)) & SYSCON0_HIFI4_GPR0_PFAULTINFOVLD_MASK)

#define SYSCON0_HIFI4_GPR0_PFATALERR_MASK        (0x2U)
#define SYSCON0_HIFI4_GPR0_PFATALERR_SHIFT       (1U)
/*! PFATALERR - PFatalError
 *  0b1..Error occurs
 *  0b0..No error occurs
 */
#define SYSCON0_HIFI4_GPR0_PFATALERR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_HIFI4_GPR0_PFATALERR_SHIFT)) & SYSCON0_HIFI4_GPR0_PFATALERR_MASK)

#define SYSCON0_HIFI4_GPR0_EXCEPTIONERR_MASK     (0x4U)
#define SYSCON0_HIFI4_GPR0_EXCEPTIONERR_SHIFT    (2U)
/*! EXCEPTIONERR - DoubleExceptionError
 *  0b1..Error occurs
 *  0b0..No error occurs
 */
#define SYSCON0_HIFI4_GPR0_EXCEPTIONERR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_HIFI4_GPR0_EXCEPTIONERR_SHIFT)) & SYSCON0_HIFI4_GPR0_EXCEPTIONERR_MASK)
/*! @} */

/*! @name HIFI4_GPR1 - HiFi4 General Purpose Register 1 */
/*! @{ */

#define SYSCON0_HIFI4_GPR1_PFAULTINFO_MASK       (0xFFFFFFFFU)
#define SYSCON0_HIFI4_GPR1_PFAULTINFO_SHIFT      (0U)
/*! PFAULTINFO - PFaultInfo */
#define SYSCON0_HIFI4_GPR1_PFAULTINFO(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_HIFI4_GPR1_PFAULTINFO_SHIFT)) & SYSCON0_HIFI4_GPR1_PFAULTINFO_MASK)
/*! @} */

/*! @name HIFI4_GPR2 - HiFi4 General Purpose Register 2 */
/*! @{ */

#define SYSCON0_HIFI4_GPR2_TIE_EXPSTATE_MASK     (0xFFFFFFFFU)
#define SYSCON0_HIFI4_GPR2_TIE_EXPSTATE_SHIFT    (0U)
/*! TIE_EXPSTATE - GPIO32 Option TIE Output State */
#define SYSCON0_HIFI4_GPR2_TIE_EXPSTATE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_HIFI4_GPR2_TIE_EXPSTATE_SHIFT)) & SYSCON0_HIFI4_GPR2_TIE_EXPSTATE_MASK)
/*! @} */

/*! @name DSP_VECT_REMAP - HiFi4 DSP Vector Remap */
/*! @{ */

#define SYSCON0_DSP_VECT_REMAP_DSP_VECT_REMAP_MASK (0x1FFFU)
#define SYSCON0_DSP_VECT_REMAP_DSP_VECT_REMAP_SHIFT (0U)
/*! DSP_VECT_REMAP - DSP Vector Remap */
#define SYSCON0_DSP_VECT_REMAP_DSP_VECT_REMAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_DSP_VECT_REMAP_DSP_VECT_REMAP_SHIFT)) & SYSCON0_DSP_VECT_REMAP_DSP_VECT_REMAP_MASK)

#define SYSCON0_DSP_VECT_REMAP_STATVECSELECT_MASK (0x2000U)
#define SYSCON0_DSP_VECT_REMAP_STATVECSELECT_SHIFT (13U)
/*! STATVECSELECT - HiFi4 Remap Function Enable
 *  0b0..Remap function disabled
 *  0b1..Remap function enabled
 */
#define SYSCON0_DSP_VECT_REMAP_STATVECSELECT(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_DSP_VECT_REMAP_STATVECSELECT_SHIFT)) & SYSCON0_DSP_VECT_REMAP_STATVECSELECT_MASK)
/*! @} */

/*! @name EDMA0_EN0 - eDMA0 Request Enable 0 */
/*! @{ */

#define SYSCON0_EDMA0_EN0_MICFIL_EN_MASK         (0x2U)
#define SYSCON0_EDMA0_EN0_MICFIL_EN_SHIFT        (1U)
/*! MICFIL_EN - MICFIL Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_MICFIL_EN(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_MICFIL_EN_SHIFT)) & SYSCON0_EDMA0_EN0_MICFIL_EN_MASK)

#define SYSCON0_EDMA0_EN0_XSPI0_RX_EN_MASK       (0x4U)
#define SYSCON0_EDMA0_EN0_XSPI0_RX_EN_SHIFT      (2U)
/*! XSPI0_RX_EN - XSPI0 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_XSPI0_RX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_XSPI0_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN0_XSPI0_RX_EN_MASK)

#define SYSCON0_EDMA0_EN0_XSPI0_TX_EN_MASK       (0x8U)
#define SYSCON0_EDMA0_EN0_XSPI0_TX_EN_SHIFT      (3U)
/*! XSPI0_TX_EN - XSPI0 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_XSPI0_TX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_XSPI0_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN0_XSPI0_TX_EN_MASK)

#define SYSCON0_EDMA0_EN0_XSPI1_RX_EN_MASK       (0x10U)
#define SYSCON0_EDMA0_EN0_XSPI1_RX_EN_SHIFT      (4U)
/*! XSPI1_RX_EN - XSPI1 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_XSPI1_RX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_XSPI1_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN0_XSPI1_RX_EN_MASK)

#define SYSCON0_EDMA0_EN0_XSPI1_TX_EN_MASK       (0x20U)
#define SYSCON0_EDMA0_EN0_XSPI1_TX_EN_SHIFT      (5U)
/*! XSPI1_TX_EN - XSPI1 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_XSPI1_TX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_XSPI1_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN0_XSPI1_TX_EN_MASK)

#define SYSCON0_EDMA0_EN0_XSPI2_RX_EN_MASK       (0x40U)
#define SYSCON0_EDMA0_EN0_XSPI2_RX_EN_SHIFT      (6U)
/*! XSPI2_RX_EN - XSPI2 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_XSPI2_RX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_XSPI2_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN0_XSPI2_RX_EN_MASK)

#define SYSCON0_EDMA0_EN0_XSPI2_TX_EN_MASK       (0x80U)
#define SYSCON0_EDMA0_EN0_XSPI2_TX_EN_SHIFT      (7U)
/*! XSPI2_TX_EN - XSPI2 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_XSPI2_TX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN0_XSPI2_TX_EN_MASK)

#define SYSCON0_EDMA0_EN0_PINT0_IRQ0_EN_MASK     (0x100U)
#define SYSCON0_EDMA0_EN0_PINT0_IRQ0_EN_SHIFT    (8U)
/*! PINT0_IRQ0_EN - PINT0 Interrupt 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_PINT0_IRQ0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_PINT0_IRQ0_EN_SHIFT)) & SYSCON0_EDMA0_EN0_PINT0_IRQ0_EN_MASK)

#define SYSCON0_EDMA0_EN0_PINT0_IRQ1_EN_MASK     (0x200U)
#define SYSCON0_EDMA0_EN0_PINT0_IRQ1_EN_SHIFT    (9U)
/*! PINT0_IRQ1_EN - PINT0 Interrupt 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_PINT0_IRQ1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_PINT0_IRQ1_EN_SHIFT)) & SYSCON0_EDMA0_EN0_PINT0_IRQ1_EN_MASK)

#define SYSCON0_EDMA0_EN0_PINT0_IRQ2_EN_MASK     (0x400U)
#define SYSCON0_EDMA0_EN0_PINT0_IRQ2_EN_SHIFT    (10U)
/*! PINT0_IRQ2_EN - PINT0 Interrupt 2 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_PINT0_IRQ2_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_PINT0_IRQ2_EN_SHIFT)) & SYSCON0_EDMA0_EN0_PINT0_IRQ2_EN_MASK)

#define SYSCON0_EDMA0_EN0_PINT0_IRQ3_EN_MASK     (0x800U)
#define SYSCON0_EDMA0_EN0_PINT0_IRQ3_EN_SHIFT    (11U)
/*! PINT0_IRQ3_EN - PINT0 Interrupt 3 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_PINT0_IRQ3_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_PINT0_IRQ3_EN_SHIFT)) & SYSCON0_EDMA0_EN0_PINT0_IRQ3_EN_MASK)

#define SYSCON0_EDMA0_EN0_PINT0_IRQ4_EN_MASK     (0x1000U)
#define SYSCON0_EDMA0_EN0_PINT0_IRQ4_EN_SHIFT    (12U)
/*! PINT0_IRQ4_EN - PINT0 Interrupt 4 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_PINT0_IRQ4_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_PINT0_IRQ4_EN_SHIFT)) & SYSCON0_EDMA0_EN0_PINT0_IRQ4_EN_MASK)

#define SYSCON0_EDMA0_EN0_PINT0_IRQ5_EN_MASK     (0x2000U)
#define SYSCON0_EDMA0_EN0_PINT0_IRQ5_EN_SHIFT    (13U)
/*! PINT0_IRQ5_EN - PINT0 Interrupt 5 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_PINT0_IRQ5_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_PINT0_IRQ5_EN_SHIFT)) & SYSCON0_EDMA0_EN0_PINT0_IRQ5_EN_MASK)

#define SYSCON0_EDMA0_EN0_PINT0_IRQ6_EN_MASK     (0x4000U)
#define SYSCON0_EDMA0_EN0_PINT0_IRQ6_EN_SHIFT    (14U)
/*! PINT0_IRQ6_EN - PINT0 Interrupt 6 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_PINT0_IRQ6_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_PINT0_IRQ6_EN_SHIFT)) & SYSCON0_EDMA0_EN0_PINT0_IRQ6_EN_MASK)

#define SYSCON0_EDMA0_EN0_PINT0_IRQ7_EN_MASK     (0x8000U)
#define SYSCON0_EDMA0_EN0_PINT0_IRQ7_EN_SHIFT    (15U)
/*! PINT0_IRQ7_EN - PINT0 Interrupt 7 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_PINT0_IRQ7_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_PINT0_IRQ7_EN_SHIFT)) & SYSCON0_EDMA0_EN0_PINT0_IRQ7_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER0_M0_EN_MASK     (0x10000U)
#define SYSCON0_EDMA0_EN0_CTIMER0_M0_EN_SHIFT    (16U)
/*! CTIMER0_M0_EN - CTIMER0 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER0_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER0_M0_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER0_M0_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER0_M1_EN_MASK     (0x20000U)
#define SYSCON0_EDMA0_EN0_CTIMER0_M1_EN_SHIFT    (17U)
/*! CTIMER0_M1_EN - CTIMER0 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER0_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER0_M1_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER0_M1_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER1_M0_EN_MASK     (0x40000U)
#define SYSCON0_EDMA0_EN0_CTIMER1_M0_EN_SHIFT    (18U)
/*! CTIMER1_M0_EN - CTIMER1 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER1_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER1_M0_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER1_M0_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER1_M1_EN_MASK     (0x80000U)
#define SYSCON0_EDMA0_EN0_CTIMER1_M1_EN_SHIFT    (19U)
/*! CTIMER1_M1_EN - CTIMER1 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER1_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER1_M1_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER1_M1_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER2_M0_EN_MASK     (0x100000U)
#define SYSCON0_EDMA0_EN0_CTIMER2_M0_EN_SHIFT    (20U)
/*! CTIMER2_M0_EN - CTIMER2 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER2_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER2_M0_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER2_M0_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER2_M1_EN_MASK     (0x200000U)
#define SYSCON0_EDMA0_EN0_CTIMER2_M1_EN_SHIFT    (21U)
/*! CTIMER2_M1_EN - CTIMER2 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER2_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER2_M1_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER2_M1_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER3_M0_EN_MASK     (0x400000U)
#define SYSCON0_EDMA0_EN0_CTIMER3_M0_EN_SHIFT    (22U)
/*! CTIMER3_M0_EN - CTIMER3 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER3_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER3_M0_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER3_M0_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER3_M1_EN_MASK     (0x800000U)
#define SYSCON0_EDMA0_EN0_CTIMER3_M1_EN_SHIFT    (23U)
/*! CTIMER3_M1_EN - CTIMER3 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER3_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER3_M1_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER3_M1_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER4_M0_EN_MASK     (0x1000000U)
#define SYSCON0_EDMA0_EN0_CTIMER4_M0_EN_SHIFT    (24U)
/*! CTIMER4_M0_EN - CTIMER4 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER4_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER4_M0_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER4_M0_EN_MASK)

#define SYSCON0_EDMA0_EN0_CTIMER4_M1_EN_MASK     (0x2000000U)
#define SYSCON0_EDMA0_EN0_CTIMER4_M1_EN_SHIFT    (25U)
/*! CTIMER4_M1_EN - CTIMER4 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_CTIMER4_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_CTIMER4_M1_EN_SHIFT)) & SYSCON0_EDMA0_EN0_CTIMER4_M1_EN_MASK)

#define SYSCON0_EDMA0_EN0_SCT0_DMAA_EN_MASK      (0x4000000U)
#define SYSCON0_EDMA0_EN0_SCT0_DMAA_EN_SHIFT     (26U)
/*! SCT0_DMAA_EN - SCT0 DMA A Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_SCT0_DMAA_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_SCT0_DMAA_EN_SHIFT)) & SYSCON0_EDMA0_EN0_SCT0_DMAA_EN_MASK)

#define SYSCON0_EDMA0_EN0_SCT0_DMAB_EN_MASK      (0x8000000U)
#define SYSCON0_EDMA0_EN0_SCT0_DMAB_EN_SHIFT     (27U)
/*! SCT0_DMAB_EN - SCT0 DMA B Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_SCT0_DMAB_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_SCT0_DMAB_EN_SHIFT)) & SYSCON0_EDMA0_EN0_SCT0_DMAB_EN_MASK)

#define SYSCON0_EDMA0_EN0_ADC0_FIFO0_EN_MASK     (0x10000000U)
#define SYSCON0_EDMA0_EN0_ADC0_FIFO0_EN_SHIFT    (28U)
/*! ADC0_FIFO0_EN - ADC0 FIFO0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_ADC0_FIFO0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_ADC0_FIFO0_EN_SHIFT)) & SYSCON0_EDMA0_EN0_ADC0_FIFO0_EN_MASK)

#define SYSCON0_EDMA0_EN0_ADC0_FIFO1_EN_MASK     (0x20000000U)
#define SYSCON0_EDMA0_EN0_ADC0_FIFO1_EN_SHIFT    (29U)
/*! ADC0_FIFO1_EN - ADC0 FIFO1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_ADC0_FIFO1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_ADC0_FIFO1_EN_SHIFT)) & SYSCON0_EDMA0_EN0_ADC0_FIFO1_EN_MASK)

#define SYSCON0_EDMA0_EN0_SDADC_FIFO0_EN_MASK    (0x40000000U)
#define SYSCON0_EDMA0_EN0_SDADC_FIFO0_EN_SHIFT   (30U)
/*! SDADC_FIFO0_EN - SDADC FIFO0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_SDADC_FIFO0_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_SDADC_FIFO0_EN_SHIFT)) & SYSCON0_EDMA0_EN0_SDADC_FIFO0_EN_MASK)

#define SYSCON0_EDMA0_EN0_SDADC_FIFO1_EN_MASK    (0x80000000U)
#define SYSCON0_EDMA0_EN0_SDADC_FIFO1_EN_SHIFT   (31U)
/*! SDADC_FIFO1_EN - SDADC FIFO1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN0_SDADC_FIFO1_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN0_SDADC_FIFO1_EN_SHIFT)) & SYSCON0_EDMA0_EN0_SDADC_FIFO1_EN_MASK)
/*! @} */

/*! @name EDMA0_EN1 - eDMA0 Request Enable 1 */
/*! @{ */

#define SYSCON0_EDMA0_EN1_SDADC_FIFO2_EN_MASK    (0x1U)
#define SYSCON0_EDMA0_EN1_SDADC_FIFO2_EN_SHIFT   (0U)
/*! SDADC_FIFO2_EN - SDADC FIFO2 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_SDADC_FIFO2_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_SDADC_FIFO2_EN_SHIFT)) & SYSCON0_EDMA0_EN1_SDADC_FIFO2_EN_MASK)

#define SYSCON0_EDMA0_EN1_SDADC_FIFO3_EN_MASK    (0x2U)
#define SYSCON0_EDMA0_EN1_SDADC_FIFO3_EN_SHIFT   (1U)
/*! SDADC_FIFO3_EN - SDADC FIFO3 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_SDADC_FIFO3_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_SDADC_FIFO3_EN_SHIFT)) & SYSCON0_EDMA0_EN1_SDADC_FIFO3_EN_MASK)

#define SYSCON0_EDMA0_EN1_ACMP_EN_MASK           (0x4U)
#define SYSCON0_EDMA0_EN1_ACMP_EN_SHIFT          (2U)
/*! ACMP_EN - ACMP0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_ACMP_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_ACMP_EN_SHIFT)) & SYSCON0_EDMA0_EN1_ACMP_EN_MASK)

#define SYSCON0_EDMA0_EN1_ITRC_TAMPER0_EN_MASK   (0x8U)
#define SYSCON0_EDMA0_EN1_ITRC_TAMPER0_EN_SHIFT  (3U)
/*! ITRC_TAMPER0_EN - ITRC Tamper 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_ITRC_TAMPER0_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_ITRC_TAMPER0_EN_SHIFT)) & SYSCON0_EDMA0_EN1_ITRC_TAMPER0_EN_MASK)

#define SYSCON0_EDMA0_EN1_ITRC_TAMPER1_EN_MASK   (0x10U)
#define SYSCON0_EDMA0_EN1_ITRC_TAMPER1_EN_SHIFT  (4U)
/*! ITRC_TAMPER1_EN - ITRC Tamper 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_ITRC_TAMPER1_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_ITRC_TAMPER1_EN_SHIFT)) & SYSCON0_EDMA0_EN1_ITRC_TAMPER1_EN_MASK)

#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER0_EN_MASK (0x20U)
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER0_EN_SHIFT (5U)
/*! FLEXIO_SHFT_TIMER0_EN - FLEXIO Shift Timer 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER0_EN_SHIFT)) & SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER0_EN_MASK)

#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER1_EN_MASK (0x40U)
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER1_EN_SHIFT (6U)
/*! FLEXIO_SHFT_TIMER1_EN - FLEXIO Shift Timer 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER1_EN_SHIFT)) & SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER1_EN_MASK)

#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER2_EN_MASK (0x80U)
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER2_EN_SHIFT (7U)
/*! FLEXIO_SHFT_TIMER2_EN - FLEXIO Shift Timer 2 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER2_EN_SHIFT)) & SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER2_EN_MASK)

#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER3_EN_MASK (0x100U)
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER3_EN_SHIFT (8U)
/*! FLEXIO_SHFT_TIMER3_EN - FLEXIO Shift Timer 3 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER3_EN_SHIFT)) & SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER3_EN_MASK)

#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER4_EN_MASK (0x200U)
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER4_EN_SHIFT (9U)
/*! FLEXIO_SHFT_TIMER4_EN - FLEXIO Shift Timer 4 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER4_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER4_EN_SHIFT)) & SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER4_EN_MASK)

#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER5_EN_MASK (0x400U)
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER5_EN_SHIFT (10U)
/*! FLEXIO_SHFT_TIMER5_EN - FLEXIO Shift Timer 5 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER5_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER5_EN_SHIFT)) & SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER5_EN_MASK)

#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER6_EN_MASK (0x800U)
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER6_EN_SHIFT (11U)
/*! FLEXIO_SHFT_TIMER6_EN - FLEXIO Shift Timer 6 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER6_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER6_EN_SHIFT)) & SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER6_EN_MASK)

#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER7_EN_MASK (0x1000U)
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER7_EN_SHIFT (12U)
/*! FLEXIO_SHFT_TIMER7_EN - FLEXIO Shift Timer 7 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER7_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER7_EN_SHIFT)) & SYSCON0_EDMA0_EN1_FLEXIO_SHFT_TIMER7_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_RX_EN_MASK (0x2000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_RX_EN_SHIFT (13U)
/*! LP_FLEXCOMM0_RX_EN - LP_FLEXCOMM0 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_TX_EN_MASK (0x4000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_TX_EN_SHIFT (14U)
/*! LP_FLEXCOMM0_TX_EN - LP_FLEXCOMM0 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM0_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_RX_EN_MASK (0x8000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_RX_EN_SHIFT (15U)
/*! LP_FLEXCOMM1_RX_EN - LP_FLEXCOMM1 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_TX_EN_MASK (0x10000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_TX_EN_SHIFT (16U)
/*! LP_FLEXCOMM1_TX_EN - LP_FLEXCOMM1 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM1_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_RX_EN_MASK (0x20000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_RX_EN_SHIFT (17U)
/*! LP_FLEXCOMM2_RX_EN - LP_FLEXCOMM2 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_TX_EN_MASK (0x40000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_TX_EN_SHIFT (18U)
/*! LP_FLEXCOMM2_TX_EN - LP_FLEXCOMM2 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM2_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_RX_EN_MASK (0x80000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_RX_EN_SHIFT (19U)
/*! LP_FLEXCOMM3_RX_EN - LP_FLEXCOMM3 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_TX_EN_MASK (0x100000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_TX_EN_SHIFT (20U)
/*! LP_FLEXCOMM3_TX_EN - LP_FLEXCOMM3 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM3_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_RX_EN_MASK (0x200000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_RX_EN_SHIFT (21U)
/*! LP_FLEXCOMM4_RX_EN - LP_FLEXCOMM4 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_TX_EN_MASK (0x400000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_TX_EN_SHIFT (22U)
/*! LP_FLEXCOMM4_TX_EN - LP_FLEXCOMM4 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM4_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_RX_EN_MASK (0x800000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_RX_EN_SHIFT (23U)
/*! LP_FLEXCOMM5_RX_EN - LP_FLEXCOMM5 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_TX_EN_MASK (0x1000000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_TX_EN_SHIFT (24U)
/*! LP_FLEXCOMM5_TX_EN - LP_FLEXCOMM5 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM5_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_RX_EN_MASK (0x2000000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_RX_EN_SHIFT (25U)
/*! LP_FLEXCOMM6_RX_EN - LP_FLEXCOMM6 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_TX_EN_MASK (0x4000000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_TX_EN_SHIFT (26U)
/*! LP_FLEXCOMM6_TX_EN - LP_FLEXCOMM6 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM6_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_RX_EN_MASK (0x8000000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_RX_EN_SHIFT (27U)
/*! LP_FLEXCOMM7_RX_EN - LP_FLEXCOMM7 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_TX_EN_MASK (0x10000000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_TX_EN_SHIFT (28U)
/*! LP_FLEXCOMM7_TX_EN - LP_FLEXCOMM7 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM7_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_RX_EN_MASK (0x20000000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_RX_EN_SHIFT (29U)
/*! LP_FLEXCOMM8_RX_EN - LP_FLEXCOMM8 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_RX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_TX_EN_MASK (0x40000000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_TX_EN_SHIFT (30U)
/*! LP_FLEXCOMM8_TX_EN - LP_FLEXCOMM8 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM8_TX_EN_MASK)

#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM9_RX_EN_MASK (0x80000000U)
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM9_RX_EN_SHIFT (31U)
/*! LP_FLEXCOMM9_RX_EN - LP_FLEXCOMM9 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN1_LP_FLEXCOMM9_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN1_LP_FLEXCOMM9_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN1_LP_FLEXCOMM9_RX_EN_MASK)
/*! @} */

/*! @name EDMA0_EN2 - eDMA0 Request Enable 2 */
/*! @{ */

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM9_TX_EN_MASK (0x1U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM9_TX_EN_SHIFT (0U)
/*! LP_FLEXCOMM9_TX_EN - LP_FLEXCOMM9 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM9_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM9_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM9_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_RX_EN_MASK (0x2U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_RX_EN_SHIFT (1U)
/*! LP_FLEXCOMM10_RX_EN - LP_FLEXCOMM10 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_TX_EN_MASK (0x4U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_TX_EN_SHIFT (2U)
/*! LP_FLEXCOMM10_TX_EN - LP_FLEXCOMM10 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM10_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_RX_EN_MASK (0x8U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_RX_EN_SHIFT (3U)
/*! LP_FLEXCOMM11_RX_EN - LP_FLEXCOMM11 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_TX_EN_MASK (0x10U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_TX_EN_SHIFT (4U)
/*! LP_FLEXCOMM11_TX_EN - LP_FLEXCOMM11 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM11_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_RX_EN_MASK (0x20U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_RX_EN_SHIFT (5U)
/*! LP_FLEXCOMM12_RX_EN - LP_FLEXCOMM12 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_TX_EN_MASK (0x40U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_TX_EN_SHIFT (6U)
/*! LP_FLEXCOMM12_TX_EN - LP_FLEXCOMM12 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM12_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_RX_EN_MASK (0x80U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_RX_EN_SHIFT (7U)
/*! LP_FLEXCOMM13_RX_EN - LP_FLEXCOMM13 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_TX_EN_MASK (0x100U)
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_TX_EN_SHIFT (8U)
/*! LP_FLEXCOMM13_TX_EN - LP_FLEXCOMM13 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LP_FLEXCOMM13_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LPSPI14_RX_EN_MASK     (0x200U)
#define SYSCON0_EDMA0_EN2_LPSPI14_RX_EN_SHIFT    (9U)
/*! LPSPI14_RX_EN - LPSPI14 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LPSPI14_RX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LPSPI14_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LPSPI14_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LPSPI14_TX_EN_MASK     (0x400U)
#define SYSCON0_EDMA0_EN2_LPSPI14_TX_EN_SHIFT    (10U)
/*! LPSPI14_TX_EN - LPSPI14 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LPSPI14_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LPSPI14_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LPSPI14_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LPSPI16_RX_EN_MASK     (0x800U)
#define SYSCON0_EDMA0_EN2_LPSPI16_RX_EN_SHIFT    (11U)
/*! LPSPI16_RX_EN - LPSPI16 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LPSPI16_RX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LPSPI16_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LPSPI16_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_LPSPI16_TX_EN_MASK     (0x1000U)
#define SYSCON0_EDMA0_EN2_LPSPI16_TX_EN_SHIFT    (12U)
/*! LPSPI16_TX_EN - LPSPI16 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_LPSPI16_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_LPSPI16_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_LPSPI16_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_I3C0_RX_EN_MASK        (0x2000U)
#define SYSCON0_EDMA0_EN2_I3C0_RX_EN_SHIFT       (13U)
/*! I3C0_RX_EN - I3C0 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_I3C0_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_I3C0_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_I3C0_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_I3C0_TX_EN_MASK        (0x4000U)
#define SYSCON0_EDMA0_EN2_I3C0_TX_EN_SHIFT       (14U)
/*! I3C0_TX_EN - I3C0 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_I3C0_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_I3C0_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_I3C0_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_I3C1_RX_EN_MASK        (0x8000U)
#define SYSCON0_EDMA0_EN2_I3C1_RX_EN_SHIFT       (15U)
/*! I3C1_RX_EN - I3C1 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_I3C1_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_I3C1_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_I3C1_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_I3C1_TX_EN_MASK        (0x10000U)
#define SYSCON0_EDMA0_EN2_I3C1_TX_EN_SHIFT       (16U)
/*! I3C1_TX_EN - I3C1 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_I3C1_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_I3C1_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_I3C1_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_SAI0_RX_EN_MASK        (0x20000U)
#define SYSCON0_EDMA0_EN2_SAI0_RX_EN_SHIFT       (17U)
/*! SAI0_RX_EN - SAI0 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_SAI0_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_SAI0_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_SAI0_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_SAI0_TX_EN_MASK        (0x40000U)
#define SYSCON0_EDMA0_EN2_SAI0_TX_EN_SHIFT       (18U)
/*! SAI0_TX_EN - SAI0 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_SAI0_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_SAI0_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_SAI0_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_SAI1_RX_EN_MASK        (0x80000U)
#define SYSCON0_EDMA0_EN2_SAI1_RX_EN_SHIFT       (19U)
/*! SAI1_RX_EN - SAI1 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_SAI1_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_SAI1_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_SAI1_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_SAI1_TX_EN_MASK        (0x100000U)
#define SYSCON0_EDMA0_EN2_SAI1_TX_EN_SHIFT       (20U)
/*! SAI1_TX_EN - SAI1 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_SAI1_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_SAI1_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_SAI1_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_SAI2_RX_EN_MASK        (0x200000U)
#define SYSCON0_EDMA0_EN2_SAI2_RX_EN_SHIFT       (21U)
/*! SAI2_RX_EN - SAI2 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_SAI2_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_SAI2_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_SAI2_RX_EN_MASK)

#define SYSCON0_EDMA0_EN2_SAI2_TX_EN_MASK        (0x400000U)
#define SYSCON0_EDMA0_EN2_SAI2_TX_EN_SHIFT       (22U)
/*! SAI2_TX_EN - SAI2 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_SAI2_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_SAI2_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN2_SAI2_TX_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO0_DMA0_EN_MASK     (0x800000U)
#define SYSCON0_EDMA0_EN2_GPIO0_DMA0_EN_SHIFT    (23U)
/*! GPIO0_DMA0_EN - GPIO0 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO0_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO0_DMA0_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO0_DMA0_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO0_DMA1_EN_MASK     (0x1000000U)
#define SYSCON0_EDMA0_EN2_GPIO0_DMA1_EN_SHIFT    (24U)
/*! GPIO0_DMA1_EN - GPIO0 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO0_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO0_DMA1_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO0_DMA1_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO1_DMA0_EN_MASK     (0x2000000U)
#define SYSCON0_EDMA0_EN2_GPIO1_DMA0_EN_SHIFT    (25U)
/*! GPIO1_DMA0_EN - GPIO1 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO1_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO1_DMA0_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO1_DMA0_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO1_DMA1_EN_MASK     (0x4000000U)
#define SYSCON0_EDMA0_EN2_GPIO1_DMA1_EN_SHIFT    (26U)
/*! GPIO1_DMA1_EN - GPIO1 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO1_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO1_DMA1_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO1_DMA1_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO2_DMA0_EN_MASK     (0x8000000U)
#define SYSCON0_EDMA0_EN2_GPIO2_DMA0_EN_SHIFT    (27U)
/*! GPIO2_DMA0_EN - GPIO2 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO2_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO2_DMA0_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO2_DMA0_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO2_DMA1_EN_MASK     (0x10000000U)
#define SYSCON0_EDMA0_EN2_GPIO2_DMA1_EN_SHIFT    (28U)
/*! GPIO2_DMA1_EN - GPIO2 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO2_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO2_DMA1_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO3_DMA0_EN_MASK     (0x20000000U)
#define SYSCON0_EDMA0_EN2_GPIO3_DMA0_EN_SHIFT    (29U)
/*! GPIO3_DMA0_EN - GPIO3 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO3_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO3_DMA0_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO3_DMA0_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO3_DMA1_EN_MASK     (0x40000000U)
#define SYSCON0_EDMA0_EN2_GPIO3_DMA1_EN_SHIFT    (30U)
/*! GPIO3_DMA1_EN - GPIO3 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO3_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO3_DMA1_EN_MASK)

#define SYSCON0_EDMA0_EN2_GPIO4_DMA0_EN_MASK     (0x80000000U)
#define SYSCON0_EDMA0_EN2_GPIO4_DMA0_EN_SHIFT    (31U)
/*! GPIO4_DMA0_EN - GPIO4 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN2_GPIO4_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN2_GPIO4_DMA0_EN_SHIFT)) & SYSCON0_EDMA0_EN2_GPIO4_DMA0_EN_MASK)
/*! @} */

/*! @name EDMA0_EN3 - eDMA0 Request Enable 3 */
/*! @{ */

#define SYSCON0_EDMA0_EN3_GPIO4_DMA1_EN_MASK     (0x1U)
#define SYSCON0_EDMA0_EN3_GPIO4_DMA1_EN_SHIFT    (0U)
/*! GPIO4_DMA1_EN - GPIO4 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_GPIO4_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_GPIO4_DMA1_EN_SHIFT)) & SYSCON0_EDMA0_EN3_GPIO4_DMA1_EN_MASK)

#define SYSCON0_EDMA0_EN3_GPIO5_DMA0_EN_MASK     (0x2U)
#define SYSCON0_EDMA0_EN3_GPIO5_DMA0_EN_SHIFT    (1U)
/*! GPIO5_DMA0_EN - GPIO5 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_GPIO5_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_GPIO5_DMA0_EN_SHIFT)) & SYSCON0_EDMA0_EN3_GPIO5_DMA0_EN_MASK)

#define SYSCON0_EDMA0_EN3_GPIO5_DMA1_EN_MASK     (0x4U)
#define SYSCON0_EDMA0_EN3_GPIO5_DMA1_EN_SHIFT    (2U)
/*! GPIO5_DMA1_EN - GPIO5 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_GPIO5_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_GPIO5_DMA1_EN_SHIFT)) & SYSCON0_EDMA0_EN3_GPIO5_DMA1_EN_MASK)

#define SYSCON0_EDMA0_EN3_GPIO6_DMA0_EN_MASK     (0x8U)
#define SYSCON0_EDMA0_EN3_GPIO6_DMA0_EN_SHIFT    (3U)
/*! GPIO6_DMA0_EN - GPIO6 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_GPIO6_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_GPIO6_DMA0_EN_SHIFT)) & SYSCON0_EDMA0_EN3_GPIO6_DMA0_EN_MASK)

#define SYSCON0_EDMA0_EN3_GPIO6_DMA1_EN_MASK     (0x10U)
#define SYSCON0_EDMA0_EN3_GPIO6_DMA1_EN_SHIFT    (4U)
/*! GPIO6_DMA1_EN - GPIO6 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_GPIO6_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_GPIO6_DMA1_EN_SHIFT)) & SYSCON0_EDMA0_EN3_GPIO6_DMA1_EN_MASK)

#define SYSCON0_EDMA0_EN3_GPIO7_DMA0_EN_MASK     (0x20U)
#define SYSCON0_EDMA0_EN3_GPIO7_DMA0_EN_SHIFT    (5U)
/*! GPIO7_DMA0_EN - GPIO7 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_GPIO7_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_GPIO7_DMA0_EN_SHIFT)) & SYSCON0_EDMA0_EN3_GPIO7_DMA0_EN_MASK)

#define SYSCON0_EDMA0_EN3_GPIO7_DMA1_EN_MASK     (0x40U)
#define SYSCON0_EDMA0_EN3_GPIO7_DMA1_EN_SHIFT    (6U)
/*! GPIO7_DMA1_EN - GPIO7 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_GPIO7_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_GPIO7_DMA1_EN_SHIFT)) & SYSCON0_EDMA0_EN3_GPIO7_DMA1_EN_MASK)

#define SYSCON0_EDMA0_EN3_LPI2C15_RX_EN_MASK     (0x80U)
#define SYSCON0_EDMA0_EN3_LPI2C15_RX_EN_SHIFT    (7U)
/*! LPI2C15_RX_EN - LPI2C15 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_LPI2C15_RX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_LPI2C15_RX_EN_SHIFT)) & SYSCON0_EDMA0_EN3_LPI2C15_RX_EN_MASK)

#define SYSCON0_EDMA0_EN3_LPI2C15_TX_EN_MASK     (0x100U)
#define SYSCON0_EDMA0_EN3_LPI2C15_TX_EN_SHIFT    (8U)
/*! LPI2C15_TX_EN - LPI2C15 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA0_EN3_LPI2C15_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA0_EN3_LPI2C15_TX_EN_SHIFT)) & SYSCON0_EDMA0_EN3_LPI2C15_TX_EN_MASK)
/*! @} */

/*! @name EDMA1_EN0 - eDMA1 Request Enable 0 */
/*! @{ */

#define SYSCON0_EDMA1_EN0_MICFIL_EN_MASK         (0x2U)
#define SYSCON0_EDMA1_EN0_MICFIL_EN_SHIFT        (1U)
/*! MICFIL_EN - MICFIL Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_MICFIL_EN(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_MICFIL_EN_SHIFT)) & SYSCON0_EDMA1_EN0_MICFIL_EN_MASK)

#define SYSCON0_EDMA1_EN0_XSPI0_RX_EN_MASK       (0x4U)
#define SYSCON0_EDMA1_EN0_XSPI0_RX_EN_SHIFT      (2U)
/*! XSPI0_RX_EN - XSPI0 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_XSPI0_RX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI0_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI0_RX_EN_MASK)

#define SYSCON0_EDMA1_EN0_XSPI0_TX_EN_MASK       (0x8U)
#define SYSCON0_EDMA1_EN0_XSPI0_TX_EN_SHIFT      (3U)
/*! XSPI0_TX_EN - XSPI0 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_XSPI0_TX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI0_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI0_TX_EN_MASK)

#define SYSCON0_EDMA1_EN0_XSPI1_RX_EN_MASK       (0x10U)
#define SYSCON0_EDMA1_EN0_XSPI1_RX_EN_SHIFT      (4U)
/*! XSPI1_RX_EN - XSPI1 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_XSPI1_RX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI1_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI1_RX_EN_MASK)

#define SYSCON0_EDMA1_EN0_XSPI1_TX_EN_MASK       (0x20U)
#define SYSCON0_EDMA1_EN0_XSPI1_TX_EN_SHIFT      (5U)
/*! XSPI1_TX_EN - XSPI1 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_XSPI1_TX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI1_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI1_TX_EN_MASK)

#define SYSCON0_EDMA1_EN0_XSPI2_RX_EN_MASK       (0x40U)
#define SYSCON0_EDMA1_EN0_XSPI2_RX_EN_SHIFT      (6U)
/*! XSPI2_RX_EN - XSPI2 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_XSPI2_RX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_RX_EN_MASK)

#define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK       (0x80U)
#define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT      (7U)
/*! XSPI2_TX_EN - XSPI2 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_XSPI2_TX_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK)

#define SYSCON0_EDMA1_EN0_PINT0_IRQ0_EN_MASK     (0x100U)
#define SYSCON0_EDMA1_EN0_PINT0_IRQ0_EN_SHIFT    (8U)
/*! PINT0_IRQ0_EN - PINT0 Interrupt 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_PINT0_IRQ0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_PINT0_IRQ0_EN_SHIFT)) & SYSCON0_EDMA1_EN0_PINT0_IRQ0_EN_MASK)

#define SYSCON0_EDMA1_EN0_PINT0_IRQ1_EN_MASK     (0x200U)
#define SYSCON0_EDMA1_EN0_PINT0_IRQ1_EN_SHIFT    (9U)
/*! PINT0_IRQ1_EN - PINT0 Interrupt 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_PINT0_IRQ1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_PINT0_IRQ1_EN_SHIFT)) & SYSCON0_EDMA1_EN0_PINT0_IRQ1_EN_MASK)

#define SYSCON0_EDMA1_EN0_PINT0_IRQ2_EN_MASK     (0x400U)
#define SYSCON0_EDMA1_EN0_PINT0_IRQ2_EN_SHIFT    (10U)
/*! PINT0_IRQ2_EN - PINT0 Interrupt 2 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_PINT0_IRQ2_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_PINT0_IRQ2_EN_SHIFT)) & SYSCON0_EDMA1_EN0_PINT0_IRQ2_EN_MASK)

#define SYSCON0_EDMA1_EN0_PINT0_IRQ3_EN_MASK     (0x800U)
#define SYSCON0_EDMA1_EN0_PINT0_IRQ3_EN_SHIFT    (11U)
/*! PINT0_IRQ3_EN - PINT0 Interrupt 3 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_PINT0_IRQ3_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_PINT0_IRQ3_EN_SHIFT)) & SYSCON0_EDMA1_EN0_PINT0_IRQ3_EN_MASK)

#define SYSCON0_EDMA1_EN0_PINT0_IRQ4_EN_MASK     (0x1000U)
#define SYSCON0_EDMA1_EN0_PINT0_IRQ4_EN_SHIFT    (12U)
/*! PINT0_IRQ4_EN - PINT0 Interrupt 4 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_PINT0_IRQ4_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_PINT0_IRQ4_EN_SHIFT)) & SYSCON0_EDMA1_EN0_PINT0_IRQ4_EN_MASK)

#define SYSCON0_EDMA1_EN0_PINT0_IRQ5_EN_MASK     (0x2000U)
#define SYSCON0_EDMA1_EN0_PINT0_IRQ5_EN_SHIFT    (13U)
/*! PINT0_IRQ5_EN - PINT0 Interrupt 5 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_PINT0_IRQ5_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_PINT0_IRQ5_EN_SHIFT)) & SYSCON0_EDMA1_EN0_PINT0_IRQ5_EN_MASK)

#define SYSCON0_EDMA1_EN0_PINT0_IRQ6_EN_MASK     (0x4000U)
#define SYSCON0_EDMA1_EN0_PINT0_IRQ6_EN_SHIFT    (14U)
/*! PINT0_IRQ6_EN - PINT0 Interrupt 6 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_PINT0_IRQ6_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_PINT0_IRQ6_EN_SHIFT)) & SYSCON0_EDMA1_EN0_PINT0_IRQ6_EN_MASK)

#define SYSCON0_EDMA1_EN0_PINT0_IRQ7_EN_MASK     (0x8000U)
#define SYSCON0_EDMA1_EN0_PINT0_IRQ7_EN_SHIFT    (15U)
/*! PINT0_IRQ7_EN - PINT0 Interrupt 7 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_PINT0_IRQ7_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_PINT0_IRQ7_EN_SHIFT)) & SYSCON0_EDMA1_EN0_PINT0_IRQ7_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER0_M0_EN_MASK     (0x10000U)
#define SYSCON0_EDMA1_EN0_CTIMER0_M0_EN_SHIFT    (16U)
/*! CTIMER0_M0_EN - CTIMER0 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER0_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER0_M0_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER0_M0_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER0_M1_EN_MASK     (0x20000U)
#define SYSCON0_EDMA1_EN0_CTIMER0_M1_EN_SHIFT    (17U)
/*! CTIMER0_M1_EN - CTIMER0 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER0_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER0_M1_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER0_M1_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER1_M0_EN_MASK     (0x40000U)
#define SYSCON0_EDMA1_EN0_CTIMER1_M0_EN_SHIFT    (18U)
/*! CTIMER1_M0_EN - CTIMER1 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER1_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER1_M0_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER1_M0_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER1_M1_EN_MASK     (0x80000U)
#define SYSCON0_EDMA1_EN0_CTIMER1_M1_EN_SHIFT    (19U)
/*! CTIMER1_M1_EN - CTIMER1 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER1_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER1_M1_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER1_M1_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER2_M0_EN_MASK     (0x100000U)
#define SYSCON0_EDMA1_EN0_CTIMER2_M0_EN_SHIFT    (20U)
/*! CTIMER2_M0_EN - CTIMER2 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER2_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER2_M0_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER2_M0_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER2_M1_EN_MASK     (0x200000U)
#define SYSCON0_EDMA1_EN0_CTIMER2_M1_EN_SHIFT    (21U)
/*! CTIMER2_M1_EN - CTIMER2 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER2_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER2_M1_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER2_M1_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER3_M0_EN_MASK     (0x400000U)
#define SYSCON0_EDMA1_EN0_CTIMER3_M0_EN_SHIFT    (22U)
/*! CTIMER3_M0_EN - CTIMER3 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER3_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER3_M0_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER3_M0_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER3_M1_EN_MASK     (0x800000U)
#define SYSCON0_EDMA1_EN0_CTIMER3_M1_EN_SHIFT    (23U)
/*! CTIMER3_M1_EN - CTIMER3 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER3_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER3_M1_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER3_M1_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER4_M0_EN_MASK     (0x1000000U)
#define SYSCON0_EDMA1_EN0_CTIMER4_M0_EN_SHIFT    (24U)
/*! CTIMER4_M0_EN - CTIMER4 M0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER4_M0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER4_M0_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER4_M0_EN_MASK)

#define SYSCON0_EDMA1_EN0_CTIMER4_M1_EN_MASK     (0x2000000U)
#define SYSCON0_EDMA1_EN0_CTIMER4_M1_EN_SHIFT    (25U)
/*! CTIMER4_M1_EN - CTIMER4 M1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_CTIMER4_M1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_CTIMER4_M1_EN_SHIFT)) & SYSCON0_EDMA1_EN0_CTIMER4_M1_EN_MASK)

#define SYSCON0_EDMA1_EN0_SCT0_DMAA_EN_MASK      (0x4000000U)
#define SYSCON0_EDMA1_EN0_SCT0_DMAA_EN_SHIFT     (26U)
/*! SCT0_DMAA_EN - SCT0 DMA A Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_SCT0_DMAA_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_SCT0_DMAA_EN_SHIFT)) & SYSCON0_EDMA1_EN0_SCT0_DMAA_EN_MASK)

#define SYSCON0_EDMA1_EN0_SCT0_DMAB_EN_MASK      (0x8000000U)
#define SYSCON0_EDMA1_EN0_SCT0_DMAB_EN_SHIFT     (27U)
/*! SCT0_DMAB_EN - SCT0 DMA B Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_SCT0_DMAB_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_SCT0_DMAB_EN_SHIFT)) & SYSCON0_EDMA1_EN0_SCT0_DMAB_EN_MASK)

#define SYSCON0_EDMA1_EN0_ADC0_FIFO0_EN_MASK     (0x10000000U)
#define SYSCON0_EDMA1_EN0_ADC0_FIFO0_EN_SHIFT    (28U)
/*! ADC0_FIFO0_EN - ADC0 FIFO0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_ADC0_FIFO0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_ADC0_FIFO0_EN_SHIFT)) & SYSCON0_EDMA1_EN0_ADC0_FIFO0_EN_MASK)

#define SYSCON0_EDMA1_EN0_ADC0_FIFO1_EN_MASK     (0x20000000U)
#define SYSCON0_EDMA1_EN0_ADC0_FIFO1_EN_SHIFT    (29U)
/*! ADC0_FIFO1_EN - ADC0 FIFO1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_ADC0_FIFO1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_ADC0_FIFO1_EN_SHIFT)) & SYSCON0_EDMA1_EN0_ADC0_FIFO1_EN_MASK)

#define SYSCON0_EDMA1_EN0_SDADC_FIFO0_EN_MASK    (0x40000000U)
#define SYSCON0_EDMA1_EN0_SDADC_FIFO0_EN_SHIFT   (30U)
/*! SDADC_FIFO0_EN - SDADC FIFO0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_SDADC_FIFO0_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_SDADC_FIFO0_EN_SHIFT)) & SYSCON0_EDMA1_EN0_SDADC_FIFO0_EN_MASK)

#define SYSCON0_EDMA1_EN0_SDADC_FIFO1_EN_MASK    (0x80000000U)
#define SYSCON0_EDMA1_EN0_SDADC_FIFO1_EN_SHIFT   (31U)
/*! SDADC_FIFO1_EN - SDADC FIFO1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN0_SDADC_FIFO1_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_SDADC_FIFO1_EN_SHIFT)) & SYSCON0_EDMA1_EN0_SDADC_FIFO1_EN_MASK)
/*! @} */

/*! @name EDMA1_EN1 - eDMA1 Request Enable 1 */
/*! @{ */

#define SYSCON0_EDMA1_EN1_SDADC_FIFO2_EN_MASK    (0x1U)
#define SYSCON0_EDMA1_EN1_SDADC_FIFO2_EN_SHIFT   (0U)
/*! SDADC_FIFO2_EN - SDADC FIFO2 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_SDADC_FIFO2_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_SDADC_FIFO2_EN_SHIFT)) & SYSCON0_EDMA1_EN1_SDADC_FIFO2_EN_MASK)

#define SYSCON0_EDMA1_EN1_SDADC_FIFO3_EN_MASK    (0x2U)
#define SYSCON0_EDMA1_EN1_SDADC_FIFO3_EN_SHIFT   (1U)
/*! SDADC_FIFO3_EN - SDADC FIFO3 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_SDADC_FIFO3_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_SDADC_FIFO3_EN_SHIFT)) & SYSCON0_EDMA1_EN1_SDADC_FIFO3_EN_MASK)

#define SYSCON0_EDMA1_EN1_ACMP_EN_MASK           (0x4U)
#define SYSCON0_EDMA1_EN1_ACMP_EN_SHIFT          (2U)
/*! ACMP_EN - ACMP0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_ACMP_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_ACMP_EN_SHIFT)) & SYSCON0_EDMA1_EN1_ACMP_EN_MASK)

#define SYSCON0_EDMA1_EN1_ITRC_TAMPER0_EN_MASK   (0x8U)
#define SYSCON0_EDMA1_EN1_ITRC_TAMPER0_EN_SHIFT  (3U)
/*! ITRC_TAMPER0_EN - ITRC Tamper 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_ITRC_TAMPER0_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_ITRC_TAMPER0_EN_SHIFT)) & SYSCON0_EDMA1_EN1_ITRC_TAMPER0_EN_MASK)

#define SYSCON0_EDMA1_EN1_ITRC_TAMPER1_EN_MASK   (0x10U)
#define SYSCON0_EDMA1_EN1_ITRC_TAMPER1_EN_SHIFT  (4U)
/*! ITRC_TAMPER1_EN - ITRC Tamper 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_ITRC_TAMPER1_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_ITRC_TAMPER1_EN_SHIFT)) & SYSCON0_EDMA1_EN1_ITRC_TAMPER1_EN_MASK)

#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER0_EN_MASK (0x20U)
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER0_EN_SHIFT (5U)
/*! FLEXIO_SHFT_TIMER0_EN - FLEXIO Shift Timer 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER0_EN_SHIFT)) & SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER0_EN_MASK)

#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER1_EN_MASK (0x40U)
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER1_EN_SHIFT (6U)
/*! FLEXIO_SHFT_TIMER1_EN - FLEXIO Shift Timer 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER1_EN_SHIFT)) & SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER1_EN_MASK)

#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER2_EN_MASK (0x80U)
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER2_EN_SHIFT (7U)
/*! FLEXIO_SHFT_TIMER2_EN - FLEXIO Shift Timer 2 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER2_EN_SHIFT)) & SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER2_EN_MASK)

#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER3_EN_MASK (0x100U)
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER3_EN_SHIFT (8U)
/*! FLEXIO_SHFT_TIMER3_EN - FLEXIO Shift Timer 3 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER3_EN_SHIFT)) & SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER3_EN_MASK)

#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER4_EN_MASK (0x200U)
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER4_EN_SHIFT (9U)
/*! FLEXIO_SHFT_TIMER4_EN - FLEXIO Shift Timer 4 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER4_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER4_EN_SHIFT)) & SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER4_EN_MASK)

#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER5_EN_MASK (0x400U)
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER5_EN_SHIFT (10U)
/*! FLEXIO_SHFT_TIMER5_EN - FLEXIO Shift Timer 5 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER5_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER5_EN_SHIFT)) & SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER5_EN_MASK)

#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER6_EN_MASK (0x800U)
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER6_EN_SHIFT (11U)
/*! FLEXIO_SHFT_TIMER6_EN - FLEXIO Shift Timer 6 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER6_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER6_EN_SHIFT)) & SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER6_EN_MASK)

#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER7_EN_MASK (0x1000U)
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER7_EN_SHIFT (12U)
/*! FLEXIO_SHFT_TIMER7_EN - FLEXIO Shift Timer 7 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER7_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER7_EN_SHIFT)) & SYSCON0_EDMA1_EN1_FLEXIO_SHFT_TIMER7_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_RX_EN_MASK (0x2000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_RX_EN_SHIFT (13U)
/*! LP_FLEXCOMM0_RX_EN - LP_FLEXCOMM0 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_TX_EN_MASK (0x4000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_TX_EN_SHIFT (14U)
/*! LP_FLEXCOMM0_TX_EN - LP_FLEXCOMM0 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM0_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_RX_EN_MASK (0x8000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_RX_EN_SHIFT (15U)
/*! LP_FLEXCOMM1_RX_EN - LP_FLEXCOMM1 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_TX_EN_MASK (0x10000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_TX_EN_SHIFT (16U)
/*! LP_FLEXCOMM1_TX_EN - LP_FLEXCOMM1 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM1_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_RX_EN_MASK (0x20000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_RX_EN_SHIFT (17U)
/*! LP_FLEXCOMM2_RX_EN - LP_FLEXCOMM2 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_TX_EN_MASK (0x40000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_TX_EN_SHIFT (18U)
/*! LP_FLEXCOMM2_TX_EN - LP_FLEXCOMM2 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM2_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_RX_EN_MASK (0x80000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_RX_EN_SHIFT (19U)
/*! LP_FLEXCOMM3_RX_EN - LP_FLEXCOMM3 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_TX_EN_MASK (0x100000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_TX_EN_SHIFT (20U)
/*! LP_FLEXCOMM3_TX_EN - LP_FLEXCOMM3 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM3_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_RX_EN_MASK (0x200000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_RX_EN_SHIFT (21U)
/*! LP_FLEXCOMM4_RX_EN - LP_FLEXCOMM4 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_TX_EN_MASK (0x400000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_TX_EN_SHIFT (22U)
/*! LP_FLEXCOMM4_TX_EN - LP_FLEXCOMM4 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM4_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_RX_EN_MASK (0x800000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_RX_EN_SHIFT (23U)
/*! LP_FLEXCOMM5_RX_EN - LP_FLEXCOMM5 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_TX_EN_MASK (0x1000000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_TX_EN_SHIFT (24U)
/*! LP_FLEXCOMM5_TX_EN - LP_FLEXCOMM5 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM5_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_RX_EN_MASK (0x2000000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_RX_EN_SHIFT (25U)
/*! LP_FLEXCOMM6_RX_EN - LP_FLEXCOMM6 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_TX_EN_MASK (0x4000000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_TX_EN_SHIFT (26U)
/*! LP_FLEXCOMM6_TX_EN - LP_FLEXCOMM6 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM6_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_RX_EN_MASK (0x8000000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_RX_EN_SHIFT (27U)
/*! LP_FLEXCOMM7_RX_EN - LP_FLEXCOMM7 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_TX_EN_MASK (0x10000000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_TX_EN_SHIFT (28U)
/*! LP_FLEXCOMM7_TX_EN - LP_FLEXCOMM7 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM7_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_RX_EN_MASK (0x20000000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_RX_EN_SHIFT (29U)
/*! LP_FLEXCOMM8_RX_EN - LP_FLEXCOMM8 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_RX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_TX_EN_MASK (0x40000000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_TX_EN_SHIFT (30U)
/*! LP_FLEXCOMM8_TX_EN - LP_FLEXCOMM8 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM8_TX_EN_MASK)

#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM9_RX_EN_MASK (0x80000000U)
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM9_RX_EN_SHIFT (31U)
/*! LP_FLEXCOMM9_RX_EN - LP_FLEXCOMM9 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN1_LP_FLEXCOMM9_RX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN1_LP_FLEXCOMM9_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN1_LP_FLEXCOMM9_RX_EN_MASK)
/*! @} */

/*! @name EDMA1_EN2 - eDMA1 Request Enable 2 */
/*! @{ */

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM9_TX_EN_MASK (0x1U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM9_TX_EN_SHIFT (0U)
/*! LP_FLEXCOMM9_TX_EN - LP_FLEXCOMM9 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM9_TX_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM9_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM9_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_RX_EN_MASK (0x2U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_RX_EN_SHIFT (1U)
/*! LP_FLEXCOMM10_RX_EN - LP_FLEXCOMM10 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_TX_EN_MASK (0x4U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_TX_EN_SHIFT (2U)
/*! LP_FLEXCOMM10_TX_EN - LP_FLEXCOMM10 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM10_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_RX_EN_MASK (0x8U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_RX_EN_SHIFT (3U)
/*! LP_FLEXCOMM11_RX_EN - LP_FLEXCOMM11 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_TX_EN_MASK (0x10U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_TX_EN_SHIFT (4U)
/*! LP_FLEXCOMM11_TX_EN - LP_FLEXCOMM11 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM11_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_RX_EN_MASK (0x20U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_RX_EN_SHIFT (5U)
/*! LP_FLEXCOMM12_RX_EN - LP_FLEXCOMM12 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_TX_EN_MASK (0x40U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_TX_EN_SHIFT (6U)
/*! LP_FLEXCOMM12_TX_EN - LP_FLEXCOMM12 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM12_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_RX_EN_MASK (0x80U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_RX_EN_SHIFT (7U)
/*! LP_FLEXCOMM13_RX_EN - LP_FLEXCOMM13 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_TX_EN_MASK (0x100U)
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_TX_EN_SHIFT (8U)
/*! LP_FLEXCOMM13_TX_EN - LP_FLEXCOMM13 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LP_FLEXCOMM13_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LPSPI14_RX_EN_MASK     (0x200U)
#define SYSCON0_EDMA1_EN2_LPSPI14_RX_EN_SHIFT    (9U)
/*! LPSPI14_RX_EN - LPSPI14 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LPSPI14_RX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LPSPI14_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LPSPI14_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LPSPI14_TX_EN_MASK     (0x400U)
#define SYSCON0_EDMA1_EN2_LPSPI14_TX_EN_SHIFT    (10U)
/*! LPSPI14_TX_EN - LPSPI14 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LPSPI14_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LPSPI14_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LPSPI14_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LPSPI16_RX_EN_MASK     (0x800U)
#define SYSCON0_EDMA1_EN2_LPSPI16_RX_EN_SHIFT    (11U)
/*! LPSPI16_RX_EN - LPSPI16 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LPSPI16_RX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LPSPI16_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LPSPI16_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_LPSPI16_TX_EN_MASK     (0x1000U)
#define SYSCON0_EDMA1_EN2_LPSPI16_TX_EN_SHIFT    (12U)
/*! LPSPI16_TX_EN - LPSPI16 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_LPSPI16_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_LPSPI16_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_LPSPI16_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_I3C0_RX_EN_MASK        (0x2000U)
#define SYSCON0_EDMA1_EN2_I3C0_RX_EN_SHIFT       (13U)
/*! I3C0_RX_EN - I3C0 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_I3C0_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_I3C0_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_I3C0_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_I3C0_TX_EN_MASK        (0x4000U)
#define SYSCON0_EDMA1_EN2_I3C0_TX_EN_SHIFT       (14U)
/*! I3C0_TX_EN - I3C0 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_I3C0_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_I3C0_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_I3C0_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_I3C1_RX_EN_MASK        (0x8000U)
#define SYSCON0_EDMA1_EN2_I3C1_RX_EN_SHIFT       (15U)
/*! I3C1_RX_EN - I3C1 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_I3C1_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_I3C1_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_I3C1_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_I3C1_TX_EN_MASK        (0x10000U)
#define SYSCON0_EDMA1_EN2_I3C1_TX_EN_SHIFT       (16U)
/*! I3C1_TX_EN - I3C1 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_I3C1_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_I3C1_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_I3C1_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_SAI0_RX_EN_MASK        (0x20000U)
#define SYSCON0_EDMA1_EN2_SAI0_RX_EN_SHIFT       (17U)
/*! SAI0_RX_EN - SAI0 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_SAI0_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_SAI0_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_SAI0_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_SAI0_TX_EN_MASK        (0x40000U)
#define SYSCON0_EDMA1_EN2_SAI0_TX_EN_SHIFT       (18U)
/*! SAI0_TX_EN - SAI0 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_SAI0_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_SAI0_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_SAI0_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_SAI1_RX_EN_MASK        (0x80000U)
#define SYSCON0_EDMA1_EN2_SAI1_RX_EN_SHIFT       (19U)
/*! SAI1_RX_EN - SAI1 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_SAI1_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_SAI1_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_SAI1_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_SAI1_TX_EN_MASK        (0x100000U)
#define SYSCON0_EDMA1_EN2_SAI1_TX_EN_SHIFT       (20U)
/*! SAI1_TX_EN - SAI1 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_SAI1_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_SAI1_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_SAI1_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_SAI2_RX_EN_MASK        (0x200000U)
#define SYSCON0_EDMA1_EN2_SAI2_RX_EN_SHIFT       (21U)
/*! SAI2_RX_EN - SAI2 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_SAI2_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_SAI2_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_SAI2_RX_EN_MASK)

#define SYSCON0_EDMA1_EN2_SAI2_TX_EN_MASK        (0x400000U)
#define SYSCON0_EDMA1_EN2_SAI2_TX_EN_SHIFT       (22U)
/*! SAI2_TX_EN - SAI2 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_SAI2_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_SAI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN2_SAI2_TX_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO0_DMA0_EN_MASK     (0x800000U)
#define SYSCON0_EDMA1_EN2_GPIO0_DMA0_EN_SHIFT    (23U)
/*! GPIO0_DMA0_EN - GPIO0 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO0_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO0_DMA0_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO0_DMA0_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO0_DMA1_EN_MASK     (0x1000000U)
#define SYSCON0_EDMA1_EN2_GPIO0_DMA1_EN_SHIFT    (24U)
/*! GPIO0_DMA1_EN - GPIO0 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO0_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO0_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO0_DMA1_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO1_DMA0_EN_MASK     (0x2000000U)
#define SYSCON0_EDMA1_EN2_GPIO1_DMA0_EN_SHIFT    (25U)
/*! GPIO1_DMA0_EN - GPIO1 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO1_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO1_DMA0_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO1_DMA0_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO1_DMA1_EN_MASK     (0x4000000U)
#define SYSCON0_EDMA1_EN2_GPIO1_DMA1_EN_SHIFT    (26U)
/*! GPIO1_DMA1_EN - GPIO1 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO1_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO1_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO1_DMA1_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO2_DMA0_EN_MASK     (0x8000000U)
#define SYSCON0_EDMA1_EN2_GPIO2_DMA0_EN_SHIFT    (27U)
/*! GPIO2_DMA0_EN - GPIO2 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO2_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA0_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA0_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK     (0x10000000U)
#define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT    (28U)
/*! GPIO2_DMA1_EN - GPIO2 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO3_DMA0_EN_MASK     (0x20000000U)
#define SYSCON0_EDMA1_EN2_GPIO3_DMA0_EN_SHIFT    (29U)
/*! GPIO3_DMA0_EN - GPIO3 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO3_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA0_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA0_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK     (0x40000000U)
#define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT    (30U)
/*! GPIO3_DMA1_EN - GPIO3 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK)

#define SYSCON0_EDMA1_EN2_GPIO4_DMA0_EN_MASK     (0x80000000U)
#define SYSCON0_EDMA1_EN2_GPIO4_DMA0_EN_SHIFT    (31U)
/*! GPIO4_DMA0_EN - GPIO4 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN2_GPIO4_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO4_DMA0_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO4_DMA0_EN_MASK)
/*! @} */

/*! @name EDMA1_EN3 - eDMA1 Request Enable 3 */
/*! @{ */

#define SYSCON0_EDMA1_EN3_GPIO4_DMA1_EN_MASK     (0x1U)
#define SYSCON0_EDMA1_EN3_GPIO4_DMA1_EN_SHIFT    (0U)
/*! GPIO4_DMA1_EN - GPIO4 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_GPIO4_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_GPIO4_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN3_GPIO4_DMA1_EN_MASK)

#define SYSCON0_EDMA1_EN3_GPIO5_DMA0_EN_MASK     (0x2U)
#define SYSCON0_EDMA1_EN3_GPIO5_DMA0_EN_SHIFT    (1U)
/*! GPIO5_DMA0_EN - GPIO5 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_GPIO5_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_GPIO5_DMA0_EN_SHIFT)) & SYSCON0_EDMA1_EN3_GPIO5_DMA0_EN_MASK)

#define SYSCON0_EDMA1_EN3_GPIO5_DMA1_EN_MASK     (0x4U)
#define SYSCON0_EDMA1_EN3_GPIO5_DMA1_EN_SHIFT    (2U)
/*! GPIO5_DMA1_EN - GPIO5 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_GPIO5_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_GPIO5_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN3_GPIO5_DMA1_EN_MASK)

#define SYSCON0_EDMA1_EN3_GPIO6_DMA0_EN_MASK     (0x8U)
#define SYSCON0_EDMA1_EN3_GPIO6_DMA0_EN_SHIFT    (3U)
/*! GPIO6_DMA0_EN - GPIO6 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_GPIO6_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_GPIO6_DMA0_EN_SHIFT)) & SYSCON0_EDMA1_EN3_GPIO6_DMA0_EN_MASK)

#define SYSCON0_EDMA1_EN3_GPIO6_DMA1_EN_MASK     (0x10U)
#define SYSCON0_EDMA1_EN3_GPIO6_DMA1_EN_SHIFT    (4U)
/*! GPIO6_DMA1_EN - GPIO6 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_GPIO6_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_GPIO6_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN3_GPIO6_DMA1_EN_MASK)

#define SYSCON0_EDMA1_EN3_GPIO7_DMA0_EN_MASK     (0x20U)
#define SYSCON0_EDMA1_EN3_GPIO7_DMA0_EN_SHIFT    (5U)
/*! GPIO7_DMA0_EN - GPIO7 eDMA Request 0 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_GPIO7_DMA0_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_GPIO7_DMA0_EN_SHIFT)) & SYSCON0_EDMA1_EN3_GPIO7_DMA0_EN_MASK)

#define SYSCON0_EDMA1_EN3_GPIO7_DMA1_EN_MASK     (0x40U)
#define SYSCON0_EDMA1_EN3_GPIO7_DMA1_EN_SHIFT    (6U)
/*! GPIO7_DMA1_EN - GPIO7 eDMA Request 1 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_GPIO7_DMA1_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_GPIO7_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN3_GPIO7_DMA1_EN_MASK)

#define SYSCON0_EDMA1_EN3_LPI2C15_RX_EN_MASK     (0x80U)
#define SYSCON0_EDMA1_EN3_LPI2C15_RX_EN_SHIFT    (7U)
/*! LPI2C15_RX_EN - LPI2C15 RX FIFO Drain Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_LPI2C15_RX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_LPI2C15_RX_EN_SHIFT)) & SYSCON0_EDMA1_EN3_LPI2C15_RX_EN_MASK)

#define SYSCON0_EDMA1_EN3_LPI2C15_TX_EN_MASK     (0x100U)
#define SYSCON0_EDMA1_EN3_LPI2C15_TX_EN_SHIFT    (8U)
/*! LPI2C15_TX_EN - LPI2C15 TX FIFO Fill Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON0_EDMA1_EN3_LPI2C15_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN3_LPI2C15_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN3_LPI2C15_TX_EN_MASK)
/*! @} */

/*! @name AXBS_CTRL - AXBS Control */
/*! @{ */

#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M0_MASK (0x1U)
#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M0_SHIFT (0U)
/*! AXBS_XSPI0_PRIORITY_M0 - AXBS for XSPI0 M0 Priority
 *  0b0..Low
 *  0b1..High
 */
#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M0_SHIFT)) & SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M0_MASK)

#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M1_MASK (0x2U)
#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M1_SHIFT (1U)
/*! AXBS_XSPI0_PRIORITY_M1 - AXBS for XSPI0 M1 Priority
 *  0b0..Low
 *  0b1..High
 */
#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M1_SHIFT)) & SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M1_MASK)

#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M2_MASK (0x4U)
#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M2_SHIFT (2U)
/*! AXBS_XSPI0_PRIORITY_M2 - AXBS for XSPI0 M2 Priority
 *  0b0..Low
 *  0b1..High
 */
#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M2_SHIFT)) & SYSCON0_AXBS_CTRL_AXBS_XSPI0_PRIORITY_M2_MASK)

#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_FORCE_RR_MASK (0x8000U)
#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_FORCE_RR_SHIFT (15U)
/*! AXBS_XSPI0_FORCE_RR - AXBS for XSPI0 Force Round-Robin
 *  0b0..Fixed priority arbitration
 *  0b1..Round-robin arbitration
 */
#define SYSCON0_AXBS_CTRL_AXBS_XSPI0_FORCE_RR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AXBS_CTRL_AXBS_XSPI0_FORCE_RR_SHIFT)) & SYSCON0_AXBS_CTRL_AXBS_XSPI0_FORCE_RR_MASK)

#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M0_MASK (0x10000U)
#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M0_SHIFT (16U)
/*! AXBS_XSPI1_PRIORITY_M0 - AXBS for XSPI1 M0 Priority
 *  0b0..Low
 *  0b1..High
 */
#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M0_SHIFT)) & SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M0_MASK)

#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M1_MASK (0x20000U)
#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M1_SHIFT (17U)
/*! AXBS_XSPI1_PRIORITY_M1 - AXBS for XSPI1 M1 Priority
 *  0b0..Low
 *  0b1..High
 */
#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M1_SHIFT)) & SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M1_MASK)

#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M2_MASK (0x40000U)
#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M2_SHIFT (18U)
/*! AXBS_XSPI1_PRIORITY_M2 - AXBS for XSPI1 M2 Priority
 *  0b0..Low
 *  0b1..High
 */
#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M2_SHIFT)) & SYSCON0_AXBS_CTRL_AXBS_XSPI1_PRIORITY_M2_MASK)

#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_FORCE_RR_MASK (0x80000000U)
#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_FORCE_RR_SHIFT (31U)
/*! AXBS_XSPI1_FORCE_RR - AXBS for XSPI1 Force Round-Robin
 *  0b0..Fixed priority arbitration
 *  0b1..Round-robin arbitration
 */
#define SYSCON0_AXBS_CTRL_AXBS_XSPI1_FORCE_RR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_AXBS_CTRL_AXBS_XSPI1_FORCE_RR_SHIFT)) & SYSCON0_AXBS_CTRL_AXBS_XSPI1_FORCE_RR_MASK)
/*! @} */

/*! @name I3C_ASYNC_WAKEUP_CTRL - I3C Asynchronous Wake-up Control */
/*! @{ */

#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN0_MASK (0x1U)
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN0_SHIFT (0U)
/*! IRQ_EN0 - I3C0 Controller Mode Asynchronous Wake-up Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN0_SHIFT)) & SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN0_MASK)

#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR0_MASK (0x2U)
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR0_SHIFT (1U)
/*! IRQ_CLR0 - I3C0 Asynchronous Wake-up Interrupt Clear
 *  0b0..Interrupt not cleared
 *  0b1..Interrupt cleared
 */
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR0_SHIFT)) & SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR0_MASK)

#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS0_MASK (0x80U)
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS0_SHIFT (7U)
/*! IRQ_STATUS0 - I3C0 Asynchronous Wake-up Interrupt Status
 *  0b0..Interrupt not asserted
 *  0b1..Interrupt asserted
 */
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS0_SHIFT)) & SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS0_MASK)

#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN1_MASK (0x100U)
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN1_SHIFT (8U)
/*! IRQ_EN1 - I3C1 Controller Mode Asynchronous Wake-up Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN1_SHIFT)) & SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_EN1_MASK)

#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR1_MASK (0x200U)
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR1_SHIFT (9U)
/*! IRQ_CLR1 - I3C1 Asynchronous Wake-up Interrupt Clear
 *  0b0..Interrupt not cleared
 *  0b1..Interrupt cleared
 */
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR1_SHIFT)) & SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_CLR1_MASK)

#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS1_MASK (0x8000U)
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS1_SHIFT (15U)
/*! IRQ_STATUS1 - I3C1 Asynchronous Wake-up Interrupt Status
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS1_SHIFT)) & SYSCON0_I3C_ASYNC_WAKEUP_CTRL_IRQ_STATUS1_MASK)
/*! @} */

/*! @name GRAY_CODE_LSB - Gray to Binary Converter - Gray Code [31:0] */
/*! @{ */

#define SYSCON0_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK (0xFFFFFFFFU)
#define SYSCON0_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT (0U)
/*! CODE_GRAY_31_0 - Gray Code [31:0] */
#define SYSCON0_GRAY_CODE_LSB_CODE_GRAY_31_0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT)) & SYSCON0_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK)
/*! @} */

/*! @name GRAY_CODE_MSB - Gray to Binary Converter - Gray Code [63:32] */
/*! @{ */

#define SYSCON0_GRAY_CODE_MSB_CODE_GRAY_63_32_MASK (0xFFFFFFFFU)
#define SYSCON0_GRAY_CODE_MSB_CODE_GRAY_63_32_SHIFT (0U)
/*! CODE_GRAY_63_32 - Gray Code [63:32] */
#define SYSCON0_GRAY_CODE_MSB_CODE_GRAY_63_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_GRAY_CODE_MSB_CODE_GRAY_63_32_SHIFT)) & SYSCON0_GRAY_CODE_MSB_CODE_GRAY_63_32_MASK)
/*! @} */

/*! @name BINARY_CODE_LSB - Gray to Binary Converter - Binary Code [31:0] */
/*! @{ */

#define SYSCON0_BINARY_CODE_LSB_CODE_BIN_31_0_MASK (0xFFFFFFFFU)
#define SYSCON0_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT (0U)
/*! CODE_BIN_31_0 - Binary Code [31:0] */
#define SYSCON0_BINARY_CODE_LSB_CODE_BIN_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT)) & SYSCON0_BINARY_CODE_LSB_CODE_BIN_31_0_MASK)
/*! @} */

/*! @name BINARY_CODE_MSB - Gray to Binary Converter - Binary Code [63:32] */
/*! @{ */

#define SYSCON0_BINARY_CODE_MSB_CODE_BIN_63_32_MASK (0xFFFFFFFFU)
#define SYSCON0_BINARY_CODE_MSB_CODE_BIN_63_32_SHIFT (0U)
/*! CODE_BIN_63_32 - Binary Code [63:32] */
#define SYSCON0_BINARY_CODE_MSB_CODE_BIN_63_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_BINARY_CODE_MSB_CODE_BIN_63_32_SHIFT)) & SYSCON0_BINARY_CODE_MSB_CODE_BIN_63_32_MASK)
/*! @} */

/*! @name SEC_BUSY_STATE - Secure IP Busy State */
/*! @{ */

#define SYSCON0_SEC_BUSY_STATE_SAFO_BUSY_MASK    (0x1U)
#define SYSCON0_SEC_BUSY_STATE_SAFO_BUSY_SHIFT   (0U)
/*! SAFO_BUSY - SAFO-SGI Busy State
 *  0b1..Busy
 *  0b0..Not busy
 */
#define SYSCON0_SEC_BUSY_STATE_SAFO_BUSY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_BUSY_STATE_SAFO_BUSY_SHIFT)) & SYSCON0_SEC_BUSY_STATE_SAFO_BUSY_MASK)

#define SYSCON0_SEC_BUSY_STATE_ELS_BUSY_MASK     (0x2U)
#define SYSCON0_SEC_BUSY_STATE_ELS_BUSY_SHIFT    (1U)
/*! ELS_BUSY - ELS Busy State
 *  0b1..Busy
 *  0b0..Not busy
 */
#define SYSCON0_SEC_BUSY_STATE_ELS_BUSY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_SEC_BUSY_STATE_ELS_BUSY_SHIFT)) & SYSCON0_SEC_BUSY_STATE_ELS_BUSY_MASK)
/*! @} */

/*! @name ELS_OTP_LC_STATE - Lifecycle State */
/*! @{ */

#define SYSCON0_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU)
#define SYSCON0_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U)
/*! OTP_LC_STATE - OTP Lifecycle State */
#define SYSCON0_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON0_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK)
/*! @} */

/*! @name ELS_OTP_LC_STATE_DP - Lifecycle State */
/*! @{ */

#define SYSCON0_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU)
#define SYSCON0_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U)
/*! OTP_LC_STATE_DP - OTP Lifecycle State */
#define SYSCON0_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON0_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK)
/*! @} */

/*! @name ELS_TEMPORAL_STATE - ELS Temporal State */
/*! @{ */

#define SYSCON0_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU)
#define SYSCON0_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U)
/*! TEMPORAL_STATE - Temporal State */
#define SYSCON0_ELS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON0_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK)
/*! @} */

/*! @name ELS_KDF_MASK - Key Derivation Function Mask */
/*! @{ */

#define SYSCON0_ELS_KDF_MASK_KDF_MASK_MASK       (0xFFFFFFFFU)
#define SYSCON0_ELS_KDF_MASK_KDF_MASK_SHIFT      (0U)
/*! KDF_MASK - Key Derivation Function Mask */
#define SYSCON0_ELS_KDF_MASK_KDF_MASK(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON0_ELS_KDF_MASK_KDF_MASK_MASK)
/*! @} */

/*! @name ELS_AS_UUID - ELS AS UUID */
/*! @{ */

#define SYSCON0_ELS_AS_UUID_UUIDN_MASK           (0xFFFFFFFFU)
#define SYSCON0_ELS_AS_UUID_UUIDN_SHIFT          (0U)
/*! UUIDN - UUIDn 32-Bit Data Register */
#define SYSCON0_ELS_AS_UUID_UUIDN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_UUID_UUIDN_SHIFT)) & SYSCON0_ELS_AS_UUID_UUIDN_MASK)
/*! @} */

/* The count of SYSCON0_ELS_AS_UUID */
#define SYSCON0_ELS_AS_UUID_COUNT                (4U)

/*! @name ELS_AS_CFG0 - ELS AS Configuration 0 */
/*! @{ */

#define SYSCON0_ELS_AS_CFG0_CFG_LC_STATE_MASK    (0xFFU)
#define SYSCON0_ELS_AS_CFG0_CFG_LC_STATE_SHIFT   (0U)
/*! CFG_LC_STATE - Lifecycle State Configuration */
#define SYSCON0_ELS_AS_CFG0_CFG_LC_STATE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_LC_STATE_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD1_ENABLED_MASK (0x100U)
#define SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD1_ENABLED_SHIFT (8U)
/*! CFG_HVD_VDD1_ENABLED - HVD for VDD1 Power Rail
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD1_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD1_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD1_ENABLED_MASK (0x200U)
#define SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD1_ENABLED_SHIFT (9U)
/*! CFG_LVD_VDD1_ENABLED - LVD for VDD1 Power Rail
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD1_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD1_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD2_ENABLED_MASK (0x400U)
#define SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD2_ENABLED_SHIFT (10U)
/*! CFG_HVD_VDD2_ENABLED - HVD for VDD2 Power Rail
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD2_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD2_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_HVD_VDD2_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD2_ENABLED_MASK (0x800U)
#define SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD2_ENABLED_SHIFT (11U)
/*! CFG_LVD_VDD2_ENABLED - LVD for VDD2 Power Rail
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD2_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD2_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_LVD_VDD2_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_VDD2_HGDET0_ENABLED_MASK (0x1000U)
#define SYSCON0_ELS_AS_CFG0_CFG_VDD2_HGDET0_ENABLED_SHIFT (12U)
/*! CFG_VDD2_HGDET0_ENABLED - VDD2 High-Range GDET0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_VDD2_HGDET0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_VDD2_HGDET0_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_VDD2_HGDET0_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_VDD2_LGDET1_ENABLED_MASK (0x2000U)
#define SYSCON0_ELS_AS_CFG0_CFG_VDD2_LGDET1_ENABLED_SHIFT (13U)
/*! CFG_VDD2_LGDET1_ENABLED - VDD2 Low-Range GDET1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_VDD2_LGDET1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_VDD2_LGDET1_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_VDD2_LGDET1_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_VDD1_LGDET2_ENABLED_MASK (0x4000U)
#define SYSCON0_ELS_AS_CFG0_CFG_VDD1_LGDET2_ENABLED_SHIFT (14U)
/*! CFG_VDD1_LGDET2_ENABLED - VDD1 Low-Range GDET2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_VDD1_LGDET2_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_VDD1_LGDET2_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_VDD1_LGDET2_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_VDD1_HGDET3_ENABLED_MASK (0x8000U)
#define SYSCON0_ELS_AS_CFG0_CFG_VDD1_HGDET3_ENABLED_SHIFT (15U)
/*! CFG_VDD1_HGDET3_ENABLED - VDD1 High-Range GDET3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_VDD1_HGDET3_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_VDD1_HGDET3_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_VDD1_HGDET3_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_WWDT0_ENABLED_MASK (0x10000U)
#define SYSCON0_ELS_AS_CFG0_CFG_WWDT0_ENABLED_SHIFT (16U)
/*! CFG_WWDT0_ENABLED - WWDT0 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_WWDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_WWDT0_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_WWDT0_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_WWDT1_ENABLED_MASK (0x20000U)
#define SYSCON0_ELS_AS_CFG0_CFG_WWDT1_ENABLED_SHIFT (17U)
/*! CFG_WWDT1_ENABLED - WWDT1 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_WWDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_WWDT1_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_WWDT1_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_WWDT2_ENABLED_MASK (0x40000U)
#define SYSCON0_ELS_AS_CFG0_CFG_WWDT2_ENABLED_SHIFT (18U)
/*! CFG_WWDT2_ENABLED - WWDT2 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_WWDT2_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_WWDT2_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_WWDT2_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_WWDT3_ENABLED_MASK (0x80000U)
#define SYSCON0_ELS_AS_CFG0_CFG_WWDT3_ENABLED_SHIFT (19U)
/*! CFG_WWDT3_ENABLED - WWDT3 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_WWDT3_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_WWDT3_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_WWDT3_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_CDOG0_ENABLED_MASK (0x100000U)
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG0_ENABLED_SHIFT (20U)
/*! CFG_CDOG0_ENABLED - CDOG0 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_CDOG0_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_CDOG0_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_CDOG1_ENABLED_MASK (0x200000U)
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG1_ENABLED_SHIFT (21U)
/*! CFG_CDOG1_ENABLED - CDOG1 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_CDOG1_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_CDOG1_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_CDOG2_ENABLED_MASK (0x400000U)
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG2_ENABLED_SHIFT (22U)
/*! CFG_CDOG2_ENABLED - CDOG2 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG2_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_CDOG2_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_CDOG2_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_CDOG3_ENABLED_MASK (0x800000U)
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG3_ENABLED_SHIFT (23U)
/*! CFG_CDOG3_ENABLED - CDOG3 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG3_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_CDOG3_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_CDOG3_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_CDOG4_ENABLED_MASK (0x1000000U)
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG4_ENABLED_SHIFT (24U)
/*! CFG_CDOG4_ENABLED - CDOG4 Configuration
 *  0b0..Not activated
 *  0b1..Activated
 */
#define SYSCON0_ELS_AS_CFG0_CFG_CDOG4_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_CDOG4_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_CDOG4_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD1_ENABLED_MASK (0x2000000U)
#define SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD1_ENABLED_SHIFT (25U)
/*! CFG_AGLITCH_VDD1_ENABLED - Analog Glitch Detector for VDD1 Power Rail
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD1_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD1_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD2_ENABLED_MASK (0x4000000U)
#define SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD2_ENABLED_SHIFT (26U)
/*! CFG_AGLITCH_VDD2_ENABLED - Analog Glitch Detector for VDD2 Power Rail
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD2_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD2_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_AGLITCH_VDD2_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK (0x8000000U)
#define SYSCON0_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT (27U)
/*! CFG_CLKTAMPER_DET_ENABLED - Clock Tamper Detector in OSC32KNP for 32 kHz RTC XTAL Clock
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_ENROLL_MASK (0x10000000U)
#define SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_ENROLL_SHIFT (28U)
/*! CFG_PUF_DISABLE_ENROLL - PUF Disable Enroll */
#define SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_ENROLL_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_ENROLL_MASK)

#define SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_WRAP_MASK (0x20000000U)
#define SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_WRAP_SHIFT (29U)
/*! CFG_PUF_DISABLE_WRAP - PUF Disable Wrap */
#define SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_WRAP_SHIFT)) & SYSCON0_ELS_AS_CFG0_CFG_PUF_DISABLE_WRAP_MASK)
/*! @} */

/*! @name ELS_AS_CFG1 - ELS AS Configuration 1 */
/*! @{ */

#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_STRICT_MODE_MASK (0x1U)
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_STRICT_MODE_SHIFT (0U)
/*! CFG_CSEC_DIS_STRICT_MODE - Disable Strict Mode in VDD2_COMP Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_STRICT_MODE_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_STRICT_MODE_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_VIOL_ABORT_MASK (0x2U)
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_VIOL_ABORT_SHIFT (1U)
/*! CFG_CSEC_DIS_VIOL_ABORT - Disable Violation Abort in VDD2_COMP Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CSEC_DIS_VIOL_ABORT_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_NS_PRIV_CHK_MASK (0x4U)
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_NS_PRIV_CHK_SHIFT (2U)
/*! CFG_CSEC_ENA_NS_PRIV_CHK - Enable Non-Secure Privacy Check in VDD2_COMP Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_NS_PRIV_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_S_PRIV_CHK_MASK (0x8U)
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_S_PRIV_CHK_SHIFT (3U)
/*! CFG_CSEC_ENA_S_PRIV_CHK - Enable Secure Privacy Check in VDD2_COMP Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_S_PRIV_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_SEC_CHK_MASK (0x10U)
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_SEC_CHK_SHIFT (4U)
/*! CFG_CSEC_ENA_SEC_CHK - Enable Security Check in VDD2_COMP Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_SEC_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CSEC_ENA_SEC_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_IDAU_ALLNS_MASK (0x20U)
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_IDAU_ALLNS_SHIFT (5U)
/*! CFG_CSEC_IDAU_ALLNS - IDAU All Non-Secure in VDD2_COMP Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_CSEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CSEC_IDAU_ALLNS_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CSEC_IDAU_ALLNS_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_MPU_MASK (0x40U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_MPU_SHIFT (6U)
/*! CFG_CPU0_LOCK_NS_MPU - CPU0 Lock Non-Secure MPU */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_MPU_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_MPU_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_VTOR_MASK (0x80U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_VTOR_SHIFT (7U)
/*! CFG_CPU0_LOCK_NS_VTOR - CPU0 Lock Non-Secure VTOR */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_VTOR_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_NS_VTOR_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_MPU_MASK (0x100U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_MPU_SHIFT (8U)
/*! CFG_CPU0_LOCK_S_MPU - CPU0 Lock Secure MPU */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_MPU_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_MPU_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_VTAIRCR_MASK (0x200U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_VTAIRCR_SHIFT (9U)
/*! CFG_CPU0_LOCK_S_VTAIRCR - CPU0 Lock Secure VTAIRCR */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_VTAIRCR_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_S_VTAIRCR_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_SAU_MASK (0x400U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_SAU_SHIFT (10U)
/*! CFG_CPU0_LOCK_SAU - CPU0 Lock SAU */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_SAU_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU0_LOCK_SAU_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_STRICT_MODE_MASK (0x800U)
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_STRICT_MODE_SHIFT (11U)
/*! CFG_SSEC_DIS_STRICT_MODE - Disable Strict Mode in VDD1_SENSE Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_STRICT_MODE_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_STRICT_MODE_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_VIOL_ABORT_MASK (0x1000U)
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_VIOL_ABORT_SHIFT (12U)
/*! CFG_SSEC_DIS_VIOL_ABORT - Disable Violation Abort in VDD1_SENSE Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_SSEC_DIS_VIOL_ABORT_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_NS_PRIV_CHK_MASK (0x2000U)
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_NS_PRIV_CHK_SHIFT (13U)
/*! CFG_SSEC_ENA_NS_PRIV_CHK - Enable Non-Secure Privacy Check in VDD1_SENSE Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_NS_PRIV_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_S_PRIV_CHK_MASK (0x4000U)
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_S_PRIV_CHK_SHIFT (14U)
/*! CFG_SSEC_ENA_S_PRIV_CHK - Enable Secure Privacy Check in VDD1_SENSE Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_S_PRIV_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_SEC_CHK_MASK (0x8000U)
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_SEC_CHK_SHIFT (15U)
/*! CFG_SSEC_ENA_SEC_CHK - Enable Security Check in VDD1_SENSE Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_SEC_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_SSEC_ENA_SEC_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_IDAU_ALLNS_MASK (0x10000U)
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_IDAU_ALLNS_SHIFT (16U)
/*! CFG_SSEC_IDAU_ALLNS - IDAU All Non-Secure in VDD1_SENSE Domain */
#define SYSCON0_ELS_AS_CFG1_CFG_SSEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_SSEC_IDAU_ALLNS_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_SSEC_IDAU_ALLNS_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_MPU_MASK (0x20000U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_MPU_SHIFT (17U)
/*! CFG_CPU1_LOCK_NS_MPU - CPU1 Lock Non-Secure MPU */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_MPU_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_MPU_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_VTOR_MASK (0x40000U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_VTOR_SHIFT (18U)
/*! CFG_CPU1_LOCK_NS_VTOR - CPU1 Lock Non-Secure VTOR */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_VTOR_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_NS_VTOR_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_MPU_MASK (0x80000U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_MPU_SHIFT (19U)
/*! CFG_CPU1_LOCK_S_MPU - CPU1 Lock Secure MPU */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_MPU_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_MPU_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_VTAIRCR_MASK (0x100000U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_VTAIRCR_SHIFT (20U)
/*! CFG_CPU1_LOCK_S_VTAIRCR - CPU1 Lock Secure VTAIRCR */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_VTAIRCR_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_S_VTAIRCR_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_SAU_MASK (0x200000U)
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_SAU_SHIFT (21U)
/*! CFG_CPU1_LOCK_SAU - CPU1 Lock SAU */
#define SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_SAU_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_CPU1_LOCK_SAU_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_STRICT_MODE_MASK (0x400000U)
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_STRICT_MODE_SHIFT (22U)
/*! CFG_MSEC_DIS_STRICT_MODE - Disable Strict Mode in VDD2_MEDIA */
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_STRICT_MODE_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_STRICT_MODE_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_VIOL_ABORT_MASK (0x800000U)
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_VIOL_ABORT_SHIFT (23U)
/*! CFG_MSEC_DIS_VIOL_ABORT - Disable Violation Abort in VDD2_MEDIA */
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_MSEC_DIS_VIOL_ABORT_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_NS_PRIV_CHK_MASK (0x1000000U)
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_NS_PRIV_CHK_SHIFT (24U)
/*! CFG_MSEC_ENA_NS_PRIV_CHK - Enable Non-Secure Privacy Check in VDD2_MEDIA */
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_NS_PRIV_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_S_PRIV_CHK_MASK (0x2000000U)
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_S_PRIV_CHK_SHIFT (25U)
/*! CFG_MSEC_ENA_S_PRIV_CHK - Enable Secure Privacy Check in VDD2_MEDIA */
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_S_PRIV_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_SEC_CHK_MASK (0x4000000U)
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_SEC_CHK_SHIFT (26U)
/*! CFG_MSEC_ENA_SEC_CHK - Enable Security Check in VDD2_MEDIA */
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_SEC_CHK_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_MSEC_ENA_SEC_CHK_MASK)

#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_IDAU_ALLNS_MASK (0x8000000U)
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_IDAU_ALLNS_SHIFT (27U)
/*! CFG_MSEC_IDAU_ALLNS - IDAU All Non-Secure in VDD2_MEDIA */
#define SYSCON0_ELS_AS_CFG1_CFG_MSEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG1_CFG_MSEC_IDAU_ALLNS_SHIFT)) & SYSCON0_ELS_AS_CFG1_CFG_MSEC_IDAU_ALLNS_MASK)
/*! @} */

/*! @name ELS_AS_CFG3 - ELS AS Configuration 3 */
/*! @{ */

#define SYSCON0_ELS_AS_CFG3_METAL_VERSION_MASK   (0xF0000U)
#define SYSCON0_ELS_AS_CFG3_METAL_VERSION_SHIFT  (16U)
/*! METAL_VERSION - Metal version */
#define SYSCON0_ELS_AS_CFG3_METAL_VERSION(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG3_METAL_VERSION_SHIFT)) & SYSCON0_ELS_AS_CFG3_METAL_VERSION_MASK)

#define SYSCON0_ELS_AS_CFG3_ROM_MINOR_VER_MASK   (0xF00000U)
#define SYSCON0_ELS_AS_CFG3_ROM_MINOR_VER_SHIFT  (20U)
/*! ROM_MINOR_VER - ROM minor version */
#define SYSCON0_ELS_AS_CFG3_ROM_MINOR_VER(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG3_ROM_MINOR_VER_SHIFT)) & SYSCON0_ELS_AS_CFG3_ROM_MINOR_VER_MASK)

#define SYSCON0_ELS_AS_CFG3_ROM_PATCH_MFG_VERSION_MASK (0xF000000U)
#define SYSCON0_ELS_AS_CFG3_ROM_PATCH_MFG_VERSION_SHIFT (24U)
/*! ROM_PATCH_MFG_VERSION - ROM major version */
#define SYSCON0_ELS_AS_CFG3_ROM_PATCH_MFG_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG3_ROM_PATCH_MFG_VERSION_SHIFT)) & SYSCON0_ELS_AS_CFG3_ROM_PATCH_MFG_VERSION_MASK)

#define SYSCON0_ELS_AS_CFG3_PATCH_OTA_VERSION_HEXCODE_MASK (0xF0000000U)
#define SYSCON0_ELS_AS_CFG3_PATCH_OTA_VERSION_HEXCODE_SHIFT (28U)
/*! PATCH_OTA_VERSION_HEXCODE - Patch version */
#define SYSCON0_ELS_AS_CFG3_PATCH_OTA_VERSION_HEXCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_CFG3_PATCH_OTA_VERSION_HEXCODE_SHIFT)) & SYSCON0_ELS_AS_CFG3_PATCH_OTA_VERSION_HEXCODE_MASK)
/*! @} */

/*! @name ELS_AS_ST0 - ELS AS State 0 */
/*! @{ */

#define SYSCON0_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU)
#define SYSCON0_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U)
/*! ST_TEMPORAL_STATE - Temporal State */
#define SYSCON0_ELS_AS_ST0_ST_TEMPORAL_STATE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CPU0_DBGEN_MASK    (0x10U)
#define SYSCON0_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT   (4U)
/*! ST_CPU0_DBGEN - CPU0 Debug State */
#define SYSCON0_ELS_AS_ST0_ST_CPU0_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CPU0_DBGEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CPU0_NIDEN_MASK    (0x20U)
#define SYSCON0_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT   (5U)
/*! ST_CPU0_NIDEN - CPU0 Non-Invasive Debug State */
#define SYSCON0_ELS_AS_ST0_ST_CPU0_NIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CPU0_NIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK   (0x40U)
#define SYSCON0_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT  (6U)
/*! ST_CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug State */
#define SYSCON0_ELS_AS_ST0_ST_CPU0_SPIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK  (0x80U)
#define SYSCON0_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT (7U)
/*! ST_CPU0_SPNIDEN - CPU0 Secure Privileged Non-Invasive Debug State */
#define SYSCON0_ELS_AS_ST0_ST_CPU0_SPNIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CPU1_DBGEN_MASK    (0x100U)
#define SYSCON0_ELS_AS_ST0_ST_CPU1_DBGEN_SHIFT   (8U)
/*! ST_CPU1_DBGEN - CPU1 Debug State */
#define SYSCON0_ELS_AS_ST0_ST_CPU1_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CPU1_DBGEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CPU1_DBGEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CPU1_NIDEN_MASK    (0x200U)
#define SYSCON0_ELS_AS_ST0_ST_CPU1_NIDEN_SHIFT   (9U)
/*! ST_CPU1_NIDEN - CPU1 Non-Invasive Debug State */
#define SYSCON0_ELS_AS_ST0_ST_CPU1_NIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CPU1_NIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CPU1_NIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CPU1_SPIDEN_MASK   (0x400U)
#define SYSCON0_ELS_AS_ST0_ST_CPU1_SPIDEN_SHIFT  (10U)
/*! ST_CPU1_SPIDEN - CPU1 Secure Privileged Invasive Debug State */
#define SYSCON0_ELS_AS_ST0_ST_CPU1_SPIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CPU1_SPIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CPU1_SPIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CPU1_SPNIDEN_MASK  (0x800U)
#define SYSCON0_ELS_AS_ST0_ST_CPU1_SPNIDEN_SHIFT (11U)
/*! ST_CPU1_SPNIDEN - CPU1 Secure Privileged Non-Invasive Debug State */
#define SYSCON0_ELS_AS_ST0_ST_CPU1_SPNIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CPU1_SPNIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CPU1_SPNIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_HIFI4_DBGEN_MASK   (0x1000U)
#define SYSCON0_ELS_AS_ST0_ST_HIFI4_DBGEN_SHIFT  (12U)
/*! ST_HIFI4_DBGEN - HiFi4 Invasive Debug Access
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_HIFI4_DBGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_HIFI4_DBGEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_HIFI4_DBGEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_HIFI4_NIDEN_MASK   (0x2000U)
#define SYSCON0_ELS_AS_ST0_ST_HIFI4_NIDEN_SHIFT  (13U)
/*! ST_HIFI4_NIDEN - HiFi4 Non-Invasive Debug Access
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_HIFI4_NIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_HIFI4_NIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_HIFI4_NIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_HIFI1_DBGEN_MASK   (0x4000U)
#define SYSCON0_ELS_AS_ST0_ST_HIFI1_DBGEN_SHIFT  (14U)
/*! ST_HIFI1_DBGEN - HiFi1 Invasive Debug Access
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_HIFI1_DBGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_HIFI1_DBGEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_HIFI1_DBGEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_HIFI1_NIDEN_MASK   (0x8000U)
#define SYSCON0_ELS_AS_ST0_ST_HIFI1_NIDEN_SHIFT  (15U)
/*! ST_HIFI1_NIDEN - HiFi1 Non-Invasive Debug Access
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_HIFI1_NIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_HIFI1_NIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_HIFI1_NIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_AHBAP_DBGEN_MASK   (0x10000U)
#define SYSCON0_ELS_AS_ST0_ST_AHBAP_DBGEN_SHIFT  (16U)
/*! ST_AHBAP_DBGEN - Non-Secure Memory Space Access through AHB-AP
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_AHBAP_DBGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_AHBAP_DBGEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_AHBAP_DBGEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_AHBAP_SPIDEN_MASK  (0x20000U)
#define SYSCON0_ELS_AS_ST0_ST_AHBAP_SPIDEN_SHIFT (17U)
/*! ST_AHBAP_SPIDEN - Secure Memory Space Access through AHB-AP
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_AHBAP_SPIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_AHBAP_SPIDEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_AHBAP_SPIDEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_EZHV_DBGEN_MASK    (0x40000U)
#define SYSCON0_ELS_AS_ST0_ST_EZHV_DBGEN_SHIFT   (18U)
/*! ST_EZHV_DBGEN - EZH-V Invasive Debug Access
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_EZHV_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_EZHV_DBGEN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_EZHV_DBGEN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_CORESIGHT_EN_MASK  (0x80000U)
#define SYSCON0_ELS_AS_ST0_ST_CORESIGHT_EN_SHIFT (19U)
/*! ST_CORESIGHT_EN - CoreSight Debug Components Access
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_CORESIGHT_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_CORESIGHT_EN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_CORESIGHT_EN_MASK)

#define SYSCON0_ELS_AS_ST0_ST_TEST_ACCES_EN_MASK (0x100000U)
#define SYSCON0_ELS_AS_ST0_ST_TEST_ACCES_EN_SHIFT (20U)
/*! ST_TEST_ACCES_EN - Test Port Access
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON0_ELS_AS_ST0_ST_TEST_ACCES_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST0_ST_TEST_ACCES_EN_SHIFT)) & SYSCON0_ELS_AS_ST0_ST_TEST_ACCES_EN_MASK)
/*! @} */

/*! @name ELS_AS_ST1 - ELS AS State 1 */
/*! @{ */

#define SYSCON0_ELS_AS_ST1_ST_PUF_SCORE_MASK     (0xFU)
#define SYSCON0_ELS_AS_ST1_ST_PUF_SCORE_SHIFT    (0U)
/*! ST_PUF_SCORE - PUF Score State */
#define SYSCON0_ELS_AS_ST1_ST_PUF_SCORE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST1_ST_PUF_SCORE_SHIFT)) & SYSCON0_ELS_AS_ST1_ST_PUF_SCORE_MASK)

#define SYSCON0_ELS_AS_ST1_ST_PUF_ZEROIZED_MASK  (0x10U)
#define SYSCON0_ELS_AS_ST1_ST_PUF_ZEROIZED_SHIFT (4U)
/*! ST_PUF_ZEROIZED - PUF Zeroization State */
#define SYSCON0_ELS_AS_ST1_ST_PUF_ZEROIZED(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST1_ST_PUF_ZEROIZED_SHIFT)) & SYSCON0_ELS_AS_ST1_ST_PUF_ZEROIZED_MASK)

#define SYSCON0_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U)
#define SYSCON0_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U)
/*! ST_MAIN_CLK_IS_EXT - Main Clock Source External */
#define SYSCON0_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON0_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK)

#define SYSCON0_ELS_AS_ST1_ST_BOOT_MODE_MASK     (0xC00U)
#define SYSCON0_ELS_AS_ST1_ST_BOOT_MODE_SHIFT    (10U)
/*! ST_BOOT_MODE - Boot Mode Setting */
#define SYSCON0_ELS_AS_ST1_ST_BOOT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON0_ELS_AS_ST1_ST_BOOT_MODE_MASK)
/*! @} */

/*! @name ELS_AS_FLAG0 - ELS AS Flag 0 */
/*! @{ */

#define SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U)
/*! FLAG_AP_ENABLE_CPU0 - CPU0 AP0 Enable
 *  0b0..No such event
 *  0b1..DAP enables AP0 for CPU0 (Cortex-M33) debug access
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_MASK (0x2U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_SHIFT (1U)
/*! FLAG_AP_ENABLE_CPU1 - CPU1 AP1 Enable
 *  0b0..No such event
 *  0b1..DAP enables AP1 for CPU1 (Cortex-M33) debug access
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_AHBAP_ENABLE_MASK (0x4U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_AHBAP_ENABLE_SHIFT (2U)
/*! FLAG_AHBAP_ENABLE - AHB-AP Enable
 *  0b0..No such event
 *  0b1..DAP enables AHB-AP for memory access through SWD interface
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_AHBAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_AHBAP_ENABLE_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_AHBAP_ENABLE_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_APBAP_ENABLE_MASK (0x8U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_APBAP_ENABLE_SHIFT (3U)
/*! FLAG_APBAP_ENABLE - APB-AP Enable
 *  0b0..No such event
 *  0b1..DAP enables APB-AP for debug access of HiFi4, HiFi1 or EZH-V
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_APBAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_APBAP_ENABLE_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_APBAP_ENABLE_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD1_OCCURED_MASK (0x10U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD1_OCCURED_SHIFT (4U)
/*! FLAG_LVD_VDD1_OCCURED - VDD1 LVD Event
 *  0b0..No such event
 *  0b1..LVD from VDD1 power rail is triggered
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD1_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD1_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD1_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD1_OCCURED_MASK (0x20U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD1_OCCURED_SHIFT (5U)
/*! FLAG_HVD_VDD1_OCCURED - VDD1 HVD Event
 *  0b0..No such event
 *  0b1..HVD from VDD1 power rail is triggered
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD1_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD1_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD1_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD2_OCCURED_MASK (0x40U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD2_OCCURED_SHIFT (6U)
/*! FLAG_LVD_VDD2_OCCURED - VDD2 LVD Event
 *  0b0..No such event
 *  0b1..LVD from VDD2 power rail is triggered
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD2_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD2_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_LVD_VDD2_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD2_OCCURED_MASK (0x80U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD2_OCCURED_SHIFT (7U)
/*! FLAG_HVD_VDD2_OCCURED - VDD2 HVD Event
 *  0b0..No such event
 *  0b1..HVD from VDD2 power rail is triggered
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD2_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD2_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_HVD_VDD2_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_PUF_ERROR_MASK (0x1000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_PUF_ERROR_SHIFT (12U)
/*! FLAG_PUF_ERROR - PUF Error
 *  0b0..No such event
 *  0b1..Error is flagged from PUF block
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_PUF_ERROR(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_PUF_ERROR_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_PUF_ERROR_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD1_DETECTED_MASK (0x2000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD1_DETECTED_SHIFT (13U)
/*! FLAG_GDET_GLITCH_VDD1_DETECTED - VDD1 GDET Glitch Detected
 *  0b0..No such event
 *  0b1..GDET error is flagged
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD1_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD1_DETECTED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD1_DETECTED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD2_DETECTED_MASK (0x4000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD2_DETECTED_SHIFT (14U)
/*! FLAG_GDET_GLITCH_VDD2_DETECTED - VDD2 GDET Glitch Detected
 *  0b0..No such event
 *  0b1..GDET error is flagged
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD2_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD2_DETECTED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_GDET_GLITCH_VDD2_DETECTED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD1_DETECTED_MASK (0x8000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD1_DETECTED_SHIFT (15U)
/*! FLAG_ANA_GLITCH_VDD1_DETECTED - VDD1 Analog Glitch Detected
 *  0b0..No such event
 *  0b1..Analog GDET error is flagged
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD1_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD1_DETECTED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD1_DETECTED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD2_DETECTED_MASK (0x10000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD2_DETECTED_SHIFT (16U)
/*! FLAG_ANA_GLITCH_VDD2_DETECTED - VDD2 Analog Glitch Detected
 *  0b0..No such event
 *  0b1..Analog GDET error is flagged
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD2_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD2_DETECTED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_ANA_GLITCH_VDD2_DETECTED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_CSEC_VIOL_IRQ_OCURRED_MASK (0x20000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_CSEC_VIOL_IRQ_OCURRED_SHIFT (17U)
/*! FLAG_CSEC_VIOL_IRQ_OCURRED - Security Violation Interrupt in VDD2_COMP Domain
 *  0b0..No such event
 *  0b1..Security violation is indicated from AHBSC0
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_CSEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_CSEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_CSEC_VIOL_IRQ_OCURRED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_SSEC_VIOL_IRQ_OCURRED_MASK (0x40000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_SSEC_VIOL_IRQ_OCURRED_SHIFT (18U)
/*! FLAG_SSEC_VIOL_IRQ_OCURRED - Security Violation Interrupt in VDD1_SENSE Domain
 *  0b0..No such event
 *  0b1..Security violation is indicated from AHBSC3
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_SSEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_SSEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_SSEC_VIOL_IRQ_OCURRED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_MSEC_VIOL_IRQ_OCURRED_MASK (0x80000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_MSEC_VIOL_IRQ_OCURRED_SHIFT (19U)
/*! FLAG_MSEC_VIOL_IRQ_OCURRED - Security Violation Interrupt in VDD2_MEDIA
 *  0b0..No such event
 *  0b1..Security violation is indicated from AHBSC4
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_MSEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_MSEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_MSEC_VIOL_IRQ_OCURRED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x100000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (20U)
/*! FLAG_CPU0_NS_C_ACC_OCCURED - CPU0 Non-Secure Code Access
 *  0b0..No such event
 *  0b1..CPU0 (Cortex-M33) makes non-secure code transactions
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x200000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (21U)
/*! FLAG_CPU0_NS_D_ACC_OCCURED - CPU0 Non-Secure Data Access
 *  0b0..No such event
 *  0b1..CPU0 (Cortex-M33) makes non-secure data transactions
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_C_ACC_OCCURED_MASK (0x400000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_C_ACC_OCCURED_SHIFT (22U)
/*! FLAG_CPU1_NS_C_ACC_OCCURED - CPU1 Non-Secure Code Access
 *  0b0..No such event
 *  0b1..CPU1 (Cortex-M33) makes non-secure code transactions
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_C_ACC_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_C_ACC_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_D_ACC_OCCURED_MASK (0x800000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_D_ACC_OCCURED_SHIFT (23U)
/*! FLAG_CPU1_NS_D_ACC_OCCURED - CPU1 Non-Secure Data Access
 *  0b0..No such event
 *  0b1..CPU1 (Cortex-M33) makes non-secure data transactions
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_D_ACC_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_CPU1_NS_D_ACC_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_OTPC_EFUSE_O_ATTACK_DETECT_MASK (0x1000000U)
#define SYSCON0_ELS_AS_FLAG0_OTPC_EFUSE_O_ATTACK_DETECT_SHIFT (24U)
/*! OTPC_EFUSE_O_ATTACK_DETECT - OTPC E-Fuse Output Attack Detect */
#define SYSCON0_ELS_AS_FLAG0_OTPC_EFUSE_O_ATTACK_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_OTPC_EFUSE_O_ATTACK_DETECT_SHIFT)) & SYSCON0_ELS_AS_FLAG0_OTPC_EFUSE_O_ATTACK_DETECT_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK (0x2000000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT (25U)
/*! FLAG_CLKTAMPER_DET_IRQ_OCCURED - Clock Tamper Flag
 *  0b0..No detected
 *  0b1..Detected
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK (0x4000000U)
#define SYSCON0_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT (26U)
/*! FLAG_TEMPTAMPER_DET_IRQ_OCCURED - Temperature Tamper Flag
 *  0b0..No detected
 *  0b1..Detected
 */
#define SYSCON0_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK)
/*! @} */

/*! @name ELS_AS_FLAG1 - ELS AS Flag 1 */
/*! @{ */

#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_RESET_OCCURED_MASK (0x1U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_RESET_OCCURED_SHIFT (0U)
/*! FLAG_WWDT0_RESET_OCCURED - WWDT0 Reset
 *  0b0..No such event
 *  0b1..WWDT0 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_RESET_OCCURED_MASK (0x2U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_RESET_OCCURED_SHIFT (1U)
/*! FLAG_WWDT1_RESET_OCCURED - WWDT1 Reset
 *  0b0..No such event
 *  0b1..WWDT1 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_RESET_OCCURED_MASK (0x4U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_RESET_OCCURED_SHIFT (2U)
/*! FLAG_WWDT2_RESET_OCCURED - WWDT2 Reset
 *  0b0..No such event
 *  0b1..WWDT2 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_RESET_OCCURED_MASK (0x8U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_RESET_OCCURED_SHIFT (3U)
/*! FLAG_WWDT3_RESET_OCCURED - WWDT3 Reset
 *  0b0..No such event
 *  0b1..WWDT3 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_RESET_OCCURED_MASK (0x10U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_RESET_OCCURED_SHIFT (4U)
/*! FLAG_CDOG0_RESET_OCCURED - CDOG0 Reset
 *  0b0..No such event
 *  0b1..CDOG0 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_RESET_OCCURED_MASK (0x20U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_RESET_OCCURED_SHIFT (5U)
/*! FLAG_CDOG1_RESET_OCCURED - CDOG1 Reset
 *  0b0..No such event
 *  0b1..CDOG1 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_RESET_OCCURED_MASK (0x40U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_RESET_OCCURED_SHIFT (6U)
/*! FLAG_CDOG2_RESET_OCCURED - CDOG2 Reset
 *  0b0..No such event
 *  0b1..CDOG2 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_RESET_OCCURED_MASK (0x80U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_RESET_OCCURED_SHIFT (7U)
/*! FLAG_CDOG3_RESET_OCCURED - CDOG3 Reset
 *  0b0..No such event
 *  0b1..CDOG3 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_RESET_OCCURED_MASK (0x100U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_RESET_OCCURED_SHIFT (8U)
/*! FLAG_CDOG4_RESET_OCCURED - CDOG4 Reset
 *  0b0..No such event
 *  0b1..CDOG4 reset is enabled and reset event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_RESET_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_RESET_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_IRQ_OCCURED_MASK (0x200U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_IRQ_OCCURED_SHIFT (9U)
/*! FLAG_WWDT0_IRQ_OCCURED - WWDT0 Interrupt
 *  0b0..No such event
 *  0b1..WWDT0 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_WWDT0_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_IRQ_OCCURED_MASK (0x400U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_IRQ_OCCURED_SHIFT (10U)
/*! FLAG_WWDT1_IRQ_OCCURED - WWDT1 Interrupt
 *  0b0..No such event
 *  0b1..WWDT1 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_WWDT1_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_IRQ_OCCURED_MASK (0x800U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_IRQ_OCCURED_SHIFT (11U)
/*! FLAG_WWDT2_IRQ_OCCURED - WWDT2 Interrupt
 *  0b0..No such event
 *  0b1..WWDT2 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_WWDT2_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_IRQ_OCCURED_MASK (0x1000U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_IRQ_OCCURED_SHIFT (12U)
/*! FLAG_WWDT3_IRQ_OCCURED - WWDT3 Interrupt
 *  0b0..No such event
 *  0b1..WWDT3 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_WWDT3_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_IRQ_OCCURED_MASK (0x2000U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_IRQ_OCCURED_SHIFT (13U)
/*! FLAG_CDOG0_IRQ_OCCURED - CDOG0 Interrupt
 *  0b0..No such event
 *  0b1..CDOG0 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG0_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_IRQ_OCCURED_MASK (0x4000U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_IRQ_OCCURED_SHIFT (14U)
/*! FLAG_CDOG1_IRQ_OCCURED - CDOG1 Interrupt
 *  0b0..No such event
 *  0b1..CDOG1 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG1_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_IRQ_OCCURED_MASK (0x8000U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_IRQ_OCCURED_SHIFT (15U)
/*! FLAG_CDOG2_IRQ_OCCURED - CDOG2 Interrupt
 *  0b0..No such event
 *  0b1..CDOG2 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG2_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_IRQ_OCCURED_MASK (0x10000U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_IRQ_OCCURED_SHIFT (16U)
/*! FLAG_CDOG3_IRQ_OCCURED - CDOG3 Interrupt
 *  0b0..No such event
 *  0b1..CDOG3 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG3_IRQ_OCCURED_MASK)

#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_IRQ_OCCURED_MASK (0x20000U)
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_IRQ_OCCURED_SHIFT (17U)
/*! FLAG_CDOG4_IRQ_OCCURED - CDOG4 Interrupt
 *  0b0..No such event
 *  0b1..CDOG4 interrupt is enabled and interrupt event is triggered
 */
#define SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_IRQ_OCCURED_SHIFT)) & SYSCON0_ELS_AS_FLAG1_FLAG_CDOG4_IRQ_OCCURED_MASK)
/*! @} */

/*! @name CLK_OVERRIDE_RAMPKC - PKC RAM Clock Override */
/*! @{ */

#define SYSCON0_CLK_OVERRIDE_RAMPKC_CLK_OVERRIDE_RAMPKC_MASK (0x1U)
#define SYSCON0_CLK_OVERRIDE_RAMPKC_CLK_OVERRIDE_RAMPKC_SHIFT (0U)
/*! CLK_OVERRIDE_RAMPKC - PKC_RAM_CTRL Clock Override
 *  0b0..Clock gating is not overridden
 *  0b1..Clock gating is overridden (automatic clock gating is disabled)
 */
#define SYSCON0_CLK_OVERRIDE_RAMPKC_CLK_OVERRIDE_RAMPKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_CLK_OVERRIDE_RAMPKC_CLK_OVERRIDE_RAMPKC_SHIFT)) & SYSCON0_CLK_OVERRIDE_RAMPKC_CLK_OVERRIDE_RAMPKC_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SYSCON0_Register_Masks */


/* SYSCON0 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SYSCON0 base address */
  #define SYSCON0_BASE                             (0x50002000u)
  /** Peripheral SYSCON0 base address */
  #define SYSCON0_BASE_NS                          (0x40002000u)
  /** Peripheral SYSCON0 base pointer */
  #define SYSCON0                                  ((SYSCON0_Type *)SYSCON0_BASE)
  /** Peripheral SYSCON0 base pointer */
  #define SYSCON0_NS                               ((SYSCON0_Type *)SYSCON0_BASE_NS)
  /** Array initializer of SYSCON0 peripheral base addresses */
  #define SYSCON0_BASE_ADDRS                       { SYSCON0_BASE }
  /** Array initializer of SYSCON0 peripheral base pointers */
  #define SYSCON0_BASE_PTRS                        { SYSCON0 }
  /** Array initializer of SYSCON0 peripheral base addresses */
  #define SYSCON0_BASE_ADDRS_NS                    { SYSCON0_BASE_NS }
  /** Array initializer of SYSCON0 peripheral base pointers */
  #define SYSCON0_BASE_PTRS_NS                     { SYSCON0_NS }
#else
  /** Peripheral SYSCON0 base address */
  #define SYSCON0_BASE                             (0x40002000u)
  /** Peripheral SYSCON0 base pointer */
  #define SYSCON0                                  ((SYSCON0_Type *)SYSCON0_BASE)
  /** Array initializer of SYSCON0 peripheral base addresses */
  #define SYSCON0_BASE_ADDRS                       { SYSCON0_BASE }
  /** Array initializer of SYSCON0 peripheral base pointers */
  #define SYSCON0_BASE_PTRS                        { SYSCON0 }
#endif

/*!
 * @}
 */ /* end of group SYSCON0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSCON2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON2_Peripheral_Access_Layer SYSCON2 Peripheral Access Layer
 * @{
 */

/** SYSCON2 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4064];
  __IO uint32_t GPR[2];                            /**< General Purpose Register 0..General Purpose Register 1, array offset: 0xFE0, array step: 0x4 */
} SYSCON2_Type;

/* ----------------------------------------------------------------------------
   -- SYSCON2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON2_Register_Masks SYSCON2 Register Masks
 * @{
 */

/*! @name GPR - General Purpose Register 0..General Purpose Register 1 */
/*! @{ */

#define SYSCON2_GPR_GPR_MASK                     (0xFFFFFFFFU)
#define SYSCON2_GPR_GPR_SHIFT                    (0U)
/*! GPR - General Purpose Register Bits */
#define SYSCON2_GPR_GPR(x)                       (((uint32_t)(((uint32_t)(x)) << SYSCON2_GPR_GPR_SHIFT)) & SYSCON2_GPR_GPR_MASK)
/*! @} */

/* The count of SYSCON2_GPR */
#define SYSCON2_GPR_COUNT                        (2U)


/*!
 * @}
 */ /* end of group SYSCON2_Register_Masks */


/* SYSCON2 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SYSCON2 base address */
  #define SYSCON2_BASE                             (0x50066000u)
  /** Peripheral SYSCON2 base address */
  #define SYSCON2_BASE_NS                          (0x40066000u)
  /** Peripheral SYSCON2 base pointer */
  #define SYSCON2                                  ((SYSCON2_Type *)SYSCON2_BASE)
  /** Peripheral SYSCON2 base pointer */
  #define SYSCON2_NS                               ((SYSCON2_Type *)SYSCON2_BASE_NS)
  /** Array initializer of SYSCON2 peripheral base addresses */
  #define SYSCON2_BASE_ADDRS                       { SYSCON2_BASE }
  /** Array initializer of SYSCON2 peripheral base pointers */
  #define SYSCON2_BASE_PTRS                        { SYSCON2 }
  /** Array initializer of SYSCON2 peripheral base addresses */
  #define SYSCON2_BASE_ADDRS_NS                    { SYSCON2_BASE_NS }
  /** Array initializer of SYSCON2 peripheral base pointers */
  #define SYSCON2_BASE_PTRS_NS                     { SYSCON2_NS }
#else
  /** Peripheral SYSCON2 base address */
  #define SYSCON2_BASE                             (0x40066000u)
  /** Peripheral SYSCON2 base pointer */
  #define SYSCON2                                  ((SYSCON2_Type *)SYSCON2_BASE)
  /** Array initializer of SYSCON2 peripheral base addresses */
  #define SYSCON2_BASE_ADDRS                       { SYSCON2_BASE }
  /** Array initializer of SYSCON2 peripheral base pointers */
  #define SYSCON2_BASE_PTRS                        { SYSCON2 }
#endif

/*!
 * @}
 */ /* end of group SYSCON2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSCON3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON3_Peripheral_Access_Layer SYSCON3 Peripheral Access Layer
 * @{
 */

/** SYSCON3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t SEC_CLK_CTRL;                      /**< Security Clock Control, offset: 0x0 */
  __O  uint32_t SEC_CLK_CTRL_SET;                  /**< Security Clock Control Set, offset: 0x4 */
  __O  uint32_t SEC_CLK_CTRL_CLR;                  /**< Security Clock Control Clear, offset: 0x8 */
  __IO uint32_t GDET_CTRL[2];                      /**< GDET2 Control..GDET3 Control, array offset: 0xC, array step: 0x4 */
       uint8_t RESERVED_0[108];
  __O  uint32_t RXEVPULSEGEN;                      /**< Receive Event Pulse Generator, offset: 0x80 */
       uint8_t RESERVED_1[8];
  __IO uint32_t CPU_STATUS;                        /**< CPU Status, offset: 0x8C */
       uint8_t RESERVED_2[8];
  __IO uint32_t CPU1_SVTOR;                        /**< CPU1 Secure Vector Table Offset, offset: 0x98 */
  __IO uint32_t CPU1_NSVTOR;                       /**< CPU1 Non-Secure Vector Table Offset, offset: 0x9C */
       uint8_t RESERVED_3[36];
  __I  uint32_t SILICONREV_ID;                     /**< Silicon Revision ID, offset: 0xC4 */
       uint8_t RESERVED_4[76];
  __IO uint32_t AUTOCLKGATEOVERRIDE0;              /**< Automatic Clock Gate Override, offset: 0x114 */
  __IO uint32_t SRAM_CLKGATE_CTRL;                 /**< SRAM Clock Gating Control, offset: 0x118 */
       uint8_t RESERVED_5[356];
  __IO uint32_t SENSE_AUTOGATE_EN;                 /**< VDD1_SENSE Auto Gating Enable, offset: 0x280 */
       uint8_t RESERVED_6[656];
  __IO uint32_t TEMPDETECT_CTRL[2];                /**< TEMPDETECT0 Control..TEMPDETECT1 Control, array offset: 0x514, array step: 0x4 */
  __I  uint32_t TEMPDETECT_FLAGS;                  /**< TEMPDETECT Interrupts Output, offset: 0x51C */
       uint8_t RESERVED_7[736];
  __IO uint32_t SWD_ACCESS_CPU[2];                 /**< CPU0 Software Debug Access..CPU1 Software Debug Access, array offset: 0x800, array step: 0x4 */
  __IO uint32_t SWD_ACCESS_APBAP;                  /**< APB-AP Software Debug Access, offset: 0x808 */
  __IO uint32_t SWD_ACCESS_AHBAP;                  /**< AHB-AP Software Debug Access, offset: 0x80C */
  __IO uint32_t TAP_ACCESS_EN;                     /**< JTAG Test Access Port Enable for Chip-TAP, offset: 0x810 */
  __IO uint32_t DEBUG_FEATURES;                    /**< Cortex Debug Features Control, offset: 0x814 */
  __IO uint32_t DEBUG_FEATURES_DP;                 /**< Cortex Debug Features Control, offset: 0x818 */
  __IO uint32_t DEBUG_AUTH_BEACON;                 /**< Debug Authentication Beacon, offset: 0x81C */
       uint8_t RESERVED_8[832];
  __IO uint32_t GRAY_CODE_LSB;                     /**< Gray to Binary Converter - Gray Code [31:0], offset: 0xB60 */
  __IO uint32_t GRAY_CODE_MSB;                     /**< Gray to Binary Converter - Gray Code [63:32], offset: 0xB64 */
  __I  uint32_t BINARY_CODE_LSB;                   /**< Gray to Binary Converter - Binary Code [31:0], offset: 0xB68 */
  __I  uint32_t BINARY_CODE_MSB;                   /**< Gray to Binary Converter - Binary Code [63:32], offset: 0xB6C */
} SYSCON3_Type;

/* ----------------------------------------------------------------------------
   -- SYSCON3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON3_Register_Masks SYSCON3 Register Masks
 * @{
 */

/*! @name SEC_CLK_CTRL - Security Clock Control */
/*! @{ */

#define SYSCON3_SEC_CLK_CTRL_GDET2_REFCLK_EN_MASK (0x1U)
#define SYSCON3_SEC_CLK_CTRL_GDET2_REFCLK_EN_SHIFT (0U)
/*! GDET2_REFCLK_EN - GDET2 Reference Clock Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON3_SEC_CLK_CTRL_GDET2_REFCLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_SEC_CLK_CTRL_GDET2_REFCLK_EN_SHIFT)) & SYSCON3_SEC_CLK_CTRL_GDET2_REFCLK_EN_MASK)

#define SYSCON3_SEC_CLK_CTRL_GDET3_REFCLK_EN_MASK (0x2U)
#define SYSCON3_SEC_CLK_CTRL_GDET3_REFCLK_EN_SHIFT (1U)
/*! GDET3_REFCLK_EN - GDET3 Reference Clock Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON3_SEC_CLK_CTRL_GDET3_REFCLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_SEC_CLK_CTRL_GDET3_REFCLK_EN_SHIFT)) & SYSCON3_SEC_CLK_CTRL_GDET3_REFCLK_EN_MASK)
/*! @} */

/*! @name SEC_CLK_CTRL_SET - Security Clock Control Set */
/*! @{ */

#define SYSCON3_SEC_CLK_CTRL_SET_GDET2_REFCLK_EN_SET_MASK (0x1U)
#define SYSCON3_SEC_CLK_CTRL_SET_GDET2_REFCLK_EN_SET_SHIFT (0U)
/*! GDET2_REFCLK_EN_SET - GDET2 Reference Clock Enable Set
 *  0b0..Has no effect
 *  0b1..Sets SEC_CLK_CTRL[GDET2_REFCLK_EN] to 1
 */
#define SYSCON3_SEC_CLK_CTRL_SET_GDET2_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SEC_CLK_CTRL_SET_GDET2_REFCLK_EN_SET_SHIFT)) & SYSCON3_SEC_CLK_CTRL_SET_GDET2_REFCLK_EN_SET_MASK)

#define SYSCON3_SEC_CLK_CTRL_SET_GDET3_REFCLK_EN_SET_MASK (0x2U)
#define SYSCON3_SEC_CLK_CTRL_SET_GDET3_REFCLK_EN_SET_SHIFT (1U)
/*! GDET3_REFCLK_EN_SET - GDET3 Reference Clock Enable Set
 *  0b0..Has no effect
 *  0b1..Sets SEC_CLK_CTRL[GDET3_REFCLK_EN] to 1
 */
#define SYSCON3_SEC_CLK_CTRL_SET_GDET3_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SEC_CLK_CTRL_SET_GDET3_REFCLK_EN_SET_SHIFT)) & SYSCON3_SEC_CLK_CTRL_SET_GDET3_REFCLK_EN_SET_MASK)
/*! @} */

/*! @name SEC_CLK_CTRL_CLR - Security Clock Control Clear */
/*! @{ */

#define SYSCON3_SEC_CLK_CTRL_CLR_GDET2_REFCLK_EN_CLR_MASK (0x1U)
#define SYSCON3_SEC_CLK_CTRL_CLR_GDET2_REFCLK_EN_CLR_SHIFT (0U)
/*! GDET2_REFCLK_EN_CLR - GDET2 Reference Clock Enable Clear
 *  0b0..Has no effect
 *  0b1..Clears SEC_CLK_CTRL[GDET2_REFCLK_EN] to 0
 */
#define SYSCON3_SEC_CLK_CTRL_CLR_GDET2_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SEC_CLK_CTRL_CLR_GDET2_REFCLK_EN_CLR_SHIFT)) & SYSCON3_SEC_CLK_CTRL_CLR_GDET2_REFCLK_EN_CLR_MASK)

#define SYSCON3_SEC_CLK_CTRL_CLR_GDET3_REFCLK_EN_CLR_MASK (0x2U)
#define SYSCON3_SEC_CLK_CTRL_CLR_GDET3_REFCLK_EN_CLR_SHIFT (1U)
/*! GDET3_REFCLK_EN_CLR - GDET3 Reference Clock Enable Clear
 *  0b0..Has no effect
 *  0b1..Clears SEC_CLK_CTRL[GDET3_REFCLK_EN] to 0
 */
#define SYSCON3_SEC_CLK_CTRL_CLR_GDET3_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SEC_CLK_CTRL_CLR_GDET3_REFCLK_EN_CLR_SHIFT)) & SYSCON3_SEC_CLK_CTRL_CLR_GDET3_REFCLK_EN_CLR_MASK)
/*! @} */

/*! @name GDET_CTRL - GDET2 Control..GDET3 Control */
/*! @{ */

#define SYSCON3_GDET_CTRL_GDET_EVTCNT_CLR_MASK   (0x1U)
#define SYSCON3_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT  (0U)
/*! GDET_EVTCNT_CLR - GDET Event Counter Clear
 *  0b1..Clears
 *  0b0..Not clear
 */
#define SYSCON3_GDET_CTRL_GDET_EVTCNT_CLR(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT)) & SYSCON3_GDET_CTRL_GDET_EVTCNT_CLR_MASK)

#define SYSCON3_GDET_CTRL_GDET_ERR_CLR_MASK      (0x2U)
#define SYSCON3_GDET_CTRL_GDET_ERR_CLR_SHIFT     (1U)
/*! GDET_ERR_CLR - GDET Error Clear
 *  0b1..Clears
 *  0b0..Not clear
 */
#define SYSCON3_GDET_CTRL_GDET_ERR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON3_GDET_CTRL_GDET_ERR_CLR_SHIFT)) & SYSCON3_GDET_CTRL_GDET_ERR_CLR_MASK)

#define SYSCON3_GDET_CTRL_GDET_ISO_SW_MASK       (0xCU)
#define SYSCON3_GDET_CTRL_GDET_ISO_SW_SHIFT      (2U)
/*! GDET_ISO_SW - GDET Isolation Control
 *  0b00..Disabled
 *  0b01..Disabled
 *  0b10..Enabled
 *  0b11..Disabled
 */
#define SYSCON3_GDET_CTRL_GDET_ISO_SW(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON3_GDET_CTRL_GDET_ISO_SW_SHIFT)) & SYSCON3_GDET_CTRL_GDET_ISO_SW_MASK)

#define SYSCON3_GDET_CTRL_EVENT_CNT_MASK         (0xFF0000U)
#define SYSCON3_GDET_CTRL_EVENT_CNT_SHIFT        (16U)
/*! EVENT_CNT - Event Count Value */
#define SYSCON3_GDET_CTRL_EVENT_CNT(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON3_GDET_CTRL_EVENT_CNT_SHIFT)) & SYSCON3_GDET_CTRL_EVENT_CNT_MASK)

#define SYSCON3_GDET_CTRL_POS_SYNC_MASK          (0x1000000U)
#define SYSCON3_GDET_CTRL_POS_SYNC_SHIFT         (24U)
/*! POS_SYNC - Positive Glitch Detection
 *  0b0..Not detected
 *  0b1..Detected
 */
#define SYSCON3_GDET_CTRL_POS_SYNC(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON3_GDET_CTRL_POS_SYNC_SHIFT)) & SYSCON3_GDET_CTRL_POS_SYNC_MASK)

#define SYSCON3_GDET_CTRL_NEG_SYNC_MASK          (0x2000000U)
#define SYSCON3_GDET_CTRL_NEG_SYNC_SHIFT         (25U)
/*! NEG_SYNC - Negative Glitch Detection
 *  0b0..Not detected
 *  0b1..Detected
 */
#define SYSCON3_GDET_CTRL_NEG_SYNC(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON3_GDET_CTRL_NEG_SYNC_SHIFT)) & SYSCON3_GDET_CTRL_NEG_SYNC_MASK)

#define SYSCON3_GDET_CTRL_EVENT_CLR_FLAG_MASK    (0x4000000U)
#define SYSCON3_GDET_CTRL_EVENT_CLR_FLAG_SHIFT   (26U)
/*! EVENT_CLR_FLAG - Event Counter Clear
 *  0b0..Not cleared
 *  0b1..Cleared
 */
#define SYSCON3_GDET_CTRL_EVENT_CLR_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON3_GDET_CTRL_EVENT_CLR_FLAG_SHIFT)) & SYSCON3_GDET_CTRL_EVENT_CLR_FLAG_MASK)
/*! @} */

/* The count of SYSCON3_GDET_CTRL */
#define SYSCON3_GDET_CTRL_COUNT                  (2U)

/*! @name RXEVPULSEGEN - Receive Event Pulse Generator */
/*! @{ */

#define SYSCON3_RXEVPULSEGEN_RXEVPULSEGEN_MASK   (0x1U)
#define SYSCON3_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT  (0U)
/*! RXEVPULSEGEN - Receive Event Pulse Generator
 *  0b0..No effect
 *  0b1..Pulse receive event high for one cycle
 */
#define SYSCON3_RXEVPULSEGEN_RXEVPULSEGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT)) & SYSCON3_RXEVPULSEGEN_RXEVPULSEGEN_MASK)
/*! @} */

/*! @name CPU_STATUS - CPU Status */
/*! @{ */

#define SYSCON3_CPU_STATUS_CPU_WAIT_MASK         (0x1U)
#define SYSCON3_CPU_STATUS_CPU_WAIT_SHIFT        (0U)
/*! CPU_WAIT - CPU1 Stall
 *  0b1..Stall
 *  0b0..No stall
 */
#define SYSCON3_CPU_STATUS_CPU_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON3_CPU_STATUS_CPU_WAIT_SHIFT)) & SYSCON3_CPU_STATUS_CPU_WAIT_MASK)

#define SYSCON3_CPU_STATUS_CPU_LOCKUP_MASK       (0x2U)
#define SYSCON3_CPU_STATUS_CPU_LOCKUP_SHIFT      (1U)
/*! CPU_LOCKUP - CPU1 Lockup State
 *  0b1..In lockup
 *  0b0..Not in lockup
 */
#define SYSCON3_CPU_STATUS_CPU_LOCKUP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON3_CPU_STATUS_CPU_LOCKUP_SHIFT)) & SYSCON3_CPU_STATUS_CPU_LOCKUP_MASK)
/*! @} */

/*! @name CPU1_SVTOR - CPU1 Secure Vector Table Offset */
/*! @{ */

#define SYSCON3_CPU1_SVTOR_CPU1_SVTOR_MASK       (0x1FFFFFFU)
#define SYSCON3_CPU1_SVTOR_CPU1_SVTOR_SHIFT      (0U)
/*! CPU1_SVTOR - Secure Vector Table Offset */
#define SYSCON3_CPU1_SVTOR_CPU1_SVTOR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON3_CPU1_SVTOR_CPU1_SVTOR_SHIFT)) & SYSCON3_CPU1_SVTOR_CPU1_SVTOR_MASK)
/*! @} */

/*! @name CPU1_NSVTOR - CPU1 Non-Secure Vector Table Offset */
/*! @{ */

#define SYSCON3_CPU1_NSVTOR_CPU1_NSVTOR_MASK     (0x1FFFFFFU)
#define SYSCON3_CPU1_NSVTOR_CPU1_NSVTOR_SHIFT    (0U)
/*! CPU1_NSVTOR - Non-Secure Vector Table Offset */
#define SYSCON3_CPU1_NSVTOR_CPU1_NSVTOR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON3_CPU1_NSVTOR_CPU1_NSVTOR_SHIFT)) & SYSCON3_CPU1_NSVTOR_CPU1_NSVTOR_MASK)
/*! @} */

/*! @name SILICONREV_ID - Silicon Revision ID */
/*! @{ */

#define SYSCON3_SILICONREV_ID_MINOR_MASK         (0xFU)
#define SYSCON3_SILICONREV_ID_MINOR_SHIFT        (0U)
/*! MINOR - Silicon Revision Minor Tag */
#define SYSCON3_SILICONREV_ID_MINOR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON3_SILICONREV_ID_MINOR_SHIFT)) & SYSCON3_SILICONREV_ID_MINOR_MASK)

#define SYSCON3_SILICONREV_ID_MAJOR_MASK         (0xF0000U)
#define SYSCON3_SILICONREV_ID_MAJOR_SHIFT        (16U)
/*! MAJOR - Silicon Revision Major Tag */
#define SYSCON3_SILICONREV_ID_MAJOR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON3_SILICONREV_ID_MAJOR_SHIFT)) & SYSCON3_SILICONREV_ID_MAJOR_MASK)
/*! @} */

/*! @name AUTOCLKGATEOVERRIDE0 - Automatic Clock Gate Override */
/*! @{ */

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION18_MASK (0x1U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION18_SHIFT (0U)
/*! PARTITION18 - Partition 18
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION18(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION18_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION18_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION19_MASK (0x2U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION19_SHIFT (1U)
/*! PARTITION19 - Partition 19
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION19(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION19_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION19_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION20_MASK (0x4U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION20_SHIFT (2U)
/*! PARTITION20 - Partition 20
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION20(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION20_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION20_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION21_MASK (0x8U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION21_SHIFT (3U)
/*! PARTITION21 - Partition 21
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION21(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION21_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION21_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION22_MASK (0x10U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION22_SHIFT (4U)
/*! PARTITION22 - Partition 22
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION22(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION22_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION22_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION23_MASK (0x20U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION23_SHIFT (5U)
/*! PARTITION23 - Partition 23
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION23(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION23_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION23_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION24_MASK (0x40U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION24_SHIFT (6U)
/*! PARTITION24 - Partition 24
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION24(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION24_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION24_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION25_MASK (0x80U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION25_SHIFT (7U)
/*! PARTITION25 - Partition 25
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION25(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION25_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION25_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION26_MASK (0x100U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION26_SHIFT (8U)
/*! PARTITION26 - Partition 26
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION26(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION26_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION26_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION27_MASK (0x200U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION27_SHIFT (9U)
/*! PARTITION27 - Partition 27
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION27(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION27_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION27_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION28_MASK (0x400U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION28_SHIFT (10U)
/*! PARTITION28 - Partition 28
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION28(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION28_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION28_MASK)

#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION29_MASK (0x800U)
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION29_SHIFT (11U)
/*! PARTITION29 - Partition 29
 *  0b0..Enables clock gating
 *  0b1..Continuous clocking
 */
#define SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION29(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION29_SHIFT)) & SYSCON3_AUTOCLKGATEOVERRIDE0_PARTITION29_MASK)
/*! @} */

/*! @name SRAM_CLKGATE_CTRL - SRAM Clock Gating Control */
/*! @{ */

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION18_MASK (0x1U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION18_SHIFT (0U)
/*! PARTITION18 - Partition 18
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION18(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION18_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION18_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION19_MASK (0x2U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION19_SHIFT (1U)
/*! PARTITION19 - Partition 19
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION19(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION19_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION19_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION20_MASK (0x4U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION20_SHIFT (2U)
/*! PARTITION20 - Partition 20
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION20(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION20_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION20_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION21_MASK (0x8U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION21_SHIFT (3U)
/*! PARTITION21 - Partition 21
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION21(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION21_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION21_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION22_MASK (0x10U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION22_SHIFT (4U)
/*! PARTITION22 - Partition 22
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION22(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION22_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION22_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION23_MASK (0x20U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION23_SHIFT (5U)
/*! PARTITION23 - Partition 23
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION23(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION23_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION23_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION24_MASK (0x40U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION24_SHIFT (6U)
/*! PARTITION24 - Partition 24
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION24(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION24_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION24_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION25_MASK (0x80U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION25_SHIFT (7U)
/*! PARTITION25 - Partition 25
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION25(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION25_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION25_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION26_MASK (0x100U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION26_SHIFT (8U)
/*! PARTITION26 - Partition 26
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION26(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION26_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION26_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION27_MASK (0x200U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION27_SHIFT (9U)
/*! PARTITION27 - Partition 27
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION27(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION27_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION27_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION28_MASK (0x400U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION28_SHIFT (10U)
/*! PARTITION28 - Partition 28
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION28(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION28_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION28_MASK)

#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION29_MASK (0x800U)
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION29_SHIFT (11U)
/*! PARTITION29 - Partition 29
 *  0b0..Bus clock input gated
 *  0b1..No effects
 */
#define SYSCON3_SRAM_CLKGATE_CTRL_PARTITION29(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_SRAM_CLKGATE_CTRL_PARTITION29_SHIFT)) & SYSCON3_SRAM_CLKGATE_CTRL_PARTITION29_MASK)
/*! @} */

/*! @name SENSE_AUTOGATE_EN - VDD1_SENSE Auto Gating Enable */
/*! @{ */

#define SYSCON3_SENSE_AUTOGATE_EN_MATRIX_EN_MASK (0x1U)
#define SYSCON3_SENSE_AUTOGATE_EN_MATRIX_EN_SHIFT (0U)
/*! MATRIX_EN - Automatic Clock Gating Enable for S-Bus
 *  0b1..Enables clock gating
 *  0b0..Disables clock gating (continuous clock)
 */
#define SYSCON3_SENSE_AUTOGATE_EN_MATRIX_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON3_SENSE_AUTOGATE_EN_MATRIX_EN_SHIFT)) & SYSCON3_SENSE_AUTOGATE_EN_MATRIX_EN_MASK)

#define SYSCON3_SENSE_AUTOGATE_EN_BRIDGE_EN_MASK (0x2U)
#define SYSCON3_SENSE_AUTOGATE_EN_BRIDGE_EN_SHIFT (1U)
/*! BRIDGE_EN - Automatic Clock Gating Enable for AHB to APB Bridge, AIPS and AXBS
 *  0b1..Enables clock gating
 *  0b0..Disables clock gating (continuous clock)
 */
#define SYSCON3_SENSE_AUTOGATE_EN_BRIDGE_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON3_SENSE_AUTOGATE_EN_BRIDGE_EN_SHIFT)) & SYSCON3_SENSE_AUTOGATE_EN_BRIDGE_EN_MASK)
/*! @} */

/*! @name TEMPDETECT_CTRL - TEMPDETECT0 Control..TEMPDETECT1 Control */
/*! @{ */

#define SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK      (0x1U)
#define SYSCON3_TEMPDETECT_CTRL_ENABLE_SHIFT     (0U)
/*! ENABLE - TEMPDETECT1 Enable
 *  0b1..Enables
 *  0b0..Disables
 */
#define SYSCON3_TEMPDETECT_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_CTRL_ENABLE_SHIFT)) & SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK)

#define SYSCON3_TEMPDETECT_CTRL_TEMPSEL_MASK     (0xFF0U)
#define SYSCON3_TEMPDETECT_CTRL_TEMPSEL_SHIFT    (4U)
/*! TEMPSEL - TEMPDETECT1 Temperature Select
 *  0b00000000-0b11111111..See .
 */
#define SYSCON3_TEMPDETECT_CTRL_TEMPSEL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_CTRL_TEMPSEL_SHIFT)) & SYSCON3_TEMPDETECT_CTRL_TEMPSEL_MASK)

#define SYSCON3_TEMPDETECT_CTRL_TEMP0_HIGH_DETECT_MASK (0x2000U)
#define SYSCON3_TEMPDETECT_CTRL_TEMP0_HIGH_DETECT_SHIFT (13U)
/*! TEMP0_HIGH_DETECT - TEMPDETECT1 High Or Low Detection
 *  0b1..Above
 *  0b0..Below
 */
#define SYSCON3_TEMPDETECT_CTRL_TEMP0_HIGH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_CTRL_TEMP0_HIGH_DETECT_SHIFT)) & SYSCON3_TEMPDETECT_CTRL_TEMP0_HIGH_DETECT_MASK)

#define SYSCON3_TEMPDETECT_CTRL_INTERRUPT_CLEAR_MASK (0x80000000U)
#define SYSCON3_TEMPDETECT_CTRL_INTERRUPT_CLEAR_SHIFT (31U)
/*! INTERRUPT_CLEAR - TEMPDETECT1 Interrupt Clear
 *  0b1..Clears
 *  0b0..Not clear
 */
#define SYSCON3_TEMPDETECT_CTRL_INTERRUPT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_CTRL_INTERRUPT_CLEAR_SHIFT)) & SYSCON3_TEMPDETECT_CTRL_INTERRUPT_CLEAR_MASK)
/*! @} */

/* The count of SYSCON3_TEMPDETECT_CTRL */
#define SYSCON3_TEMPDETECT_CTRL_COUNT            (2U)

/*! @name TEMPDETECT_FLAGS - TEMPDETECT Interrupts Output */
/*! @{ */

#define SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT0_MASK (0x1U)
#define SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT0_SHIFT (0U)
/*! TEMPDETECT0 - TEMPDETECT0 Interrupt
 *  0b1..Interrupt
 *  0b0..No Interrupt
 */
#define SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT0_SHIFT)) & SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT0_MASK)

#define SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT1_MASK (0x2U)
#define SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT1_SHIFT (1U)
/*! TEMPDETECT1 - TEMPDETECT1 Interrupt
 *  0b1..Interrupt
 *  0b0..No Interrupt
 */
#define SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT1(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT1_SHIFT)) & SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT1_MASK)
/*! @} */

/*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access..CPU1 Software Debug Access */
/*! @{ */

#define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK     (0xFFFFFFFFU)
#define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT    (0U)
/*! SEC_CODE - CPU SWD-AP: 12345678h
 *  0b00010010001101000101011001111000..Value to write to enable CPU SWD access. Reading back register will be read as Ah
 *  0b00000000000000000000000000000000..CPU DAP is not allowed. Reading back register will be read as 5h
 */
#define SYSCON3_SWD_ACCESS_CPU_SEC_CODE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
/*! @} */

/* The count of SYSCON3_SWD_ACCESS_CPU */
#define SYSCON3_SWD_ACCESS_CPU_COUNT             (2U)

/*! @name SWD_ACCESS_APBAP - APB-AP Software Debug Access */
/*! @{ */

#define SYSCON3_SWD_ACCESS_APBAP_SEC_CODE_MASK   (0xFFFFFFFFU)
#define SYSCON3_SWD_ACCESS_APBAP_SEC_CODE_SHIFT  (0U)
/*! SEC_CODE - APB SWD-AP: 12345678h
 *  0b00010010001101000101011001111000..Value to write to enable APB SWD access. Reading back register will be read as Ah
 *  0b00000000000000000000000000000000..APB DAP is not allowed. Reading back register will be read as 5h
 */
#define SYSCON3_SWD_ACCESS_APBAP_SEC_CODE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_APBAP_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_APBAP_SEC_CODE_MASK)
/*! @} */

/*! @name SWD_ACCESS_AHBAP - AHB-AP Software Debug Access */
/*! @{ */

#define SYSCON3_SWD_ACCESS_AHBAP_SEC_CODE_MASK   (0xFFFFFFFFU)
#define SYSCON3_SWD_ACCESS_AHBAP_SEC_CODE_SHIFT  (0U)
/*! SEC_CODE - AHB SWD-AP: 12345678h
 *  0b00010010001101000101011001111000..Value to write to enable AHB SWD access. Reading back register will be read as Ah
 *  0b00000000000000000000000000000000..AHB DAP is not allowed. Reading back register will be read as 5h
 */
#define SYSCON3_SWD_ACCESS_AHBAP_SEC_CODE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_AHBAP_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_AHBAP_SEC_CODE_MASK)
/*! @} */

/*! @name TAP_ACCESS_EN - JTAG Test Access Port Enable for Chip-TAP */
/*! @{ */

#define SYSCON3_TAP_ACCESS_EN_SEC_CODE_MASK      (0xFFFFFFFFU)
#define SYSCON3_TAP_ACCESS_EN_SEC_CODE_SHIFT     (0U)
/*! SEC_CODE - JTAG Test Access Port Enable: 12345678h
 *  0b00010010001101000101011001111000..Value to write to enable JTAG TAP. Reading back register will be read as Ah
 *  0b00000000000000000000000000000000..JTAG TAP is not allowed. Reading back register will be read as 5h
 */
#define SYSCON3_TAP_ACCESS_EN_SEC_CODE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON3_TAP_ACCESS_EN_SEC_CODE_SHIFT)) & SYSCON3_TAP_ACCESS_EN_SEC_CODE_MASK)
/*! @} */

/*! @name DEBUG_FEATURES - Cortex Debug Features Control */
/*! @{ */

#define SYSCON3_DEBUG_FEATURES_CPU0_NIDEN_MASK   (0x3U)
#define SYSCON3_DEBUG_FEATURES_CPU0_NIDEN_SHIFT  (0U)
/*! CPU0_NIDEN - CPU0 Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CPU0_NIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CPU0_NIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_CPU0_DBGEN_MASK   (0xCU)
#define SYSCON3_DEBUG_FEATURES_CPU0_DBGEN_SHIFT  (2U)
/*! CPU0_DBGEN - CPU0 Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CPU0_DBGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CPU0_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0x30U)
#define SYSCON3_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (4U)
/*! CPU0_SPNIDEN - CPU0 Secure Privileged Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CPU0_SPNIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CPU0_SPNIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_CPU0_SPIDEN_MASK  (0xC0U)
#define SYSCON3_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (6U)
/*! CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CPU0_SPIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CPU0_SPIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_CPU1_NIDEN_MASK   (0x300U)
#define SYSCON3_DEBUG_FEATURES_CPU1_NIDEN_SHIFT  (8U)
/*! CPU1_NIDEN - CPU1 Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CPU1_NIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CPU1_NIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_CPU1_DBGEN_MASK   (0xC00U)
#define SYSCON3_DEBUG_FEATURES_CPU1_DBGEN_SHIFT  (10U)
/*! CPU1_DBGEN - CPU1 Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CPU1_DBGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CPU1_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_CPU1_SPNIDEN_MASK (0x3000U)
#define SYSCON3_DEBUG_FEATURES_CPU1_SPNIDEN_SHIFT (12U)
/*! CPU1_SPNIDEN - CPU1 Secure Privileged Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CPU1_SPNIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CPU1_SPNIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CPU1_SPNIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_CPU1_SPIDEN_MASK  (0xC000U)
#define SYSCON3_DEBUG_FEATURES_CPU1_SPIDEN_SHIFT (14U)
/*! CPU1_SPIDEN - CPU1 Secure Privileged Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CPU1_SPIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CPU1_SPIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CPU1_SPIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_HIFI4_NIDEN_MASK  (0x30000U)
#define SYSCON3_DEBUG_FEATURES_HIFI4_NIDEN_SHIFT (16U)
/*! HIFI4_NIDEN - HiFi4 Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_HIFI4_NIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_HIFI4_NIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_HIFI4_NIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_HIFI4_DBGEN_MASK  (0xC0000U)
#define SYSCON3_DEBUG_FEATURES_HIFI4_DBGEN_SHIFT (18U)
/*! HIFI4_DBGEN - HiFi4 Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_HIFI4_DBGEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_HIFI4_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_HIFI4_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_HIFI1_NIDEN_MASK  (0x300000U)
#define SYSCON3_DEBUG_FEATURES_HIFI1_NIDEN_SHIFT (20U)
/*! HIFI1_NIDEN - HiFi1 Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_HIFI1_NIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_HIFI1_NIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_HIFI1_NIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_HIFI1_DBGEN_MASK  (0xC00000U)
#define SYSCON3_DEBUG_FEATURES_HIFI1_DBGEN_SHIFT (22U)
/*! HIFI1_DBGEN - HiFi1 Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_HIFI1_DBGEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_HIFI1_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_HIFI1_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_AHBAP_DBGEN_MASK  (0x3000000U)
#define SYSCON3_DEBUG_FEATURES_AHBAP_DBGEN_SHIFT (24U)
/*! AHBAP_DBGEN - AHB-AP Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_AHBAP_DBGEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_AHBAP_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_AHBAP_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_AHBAP_SPIDEN_MASK (0xC000000U)
#define SYSCON3_DEBUG_FEATURES_AHBAP_SPIDEN_SHIFT (26U)
/*! AHBAP_SPIDEN - AHB-AP Secure Privileged Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_AHBAP_SPIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_AHBAP_SPIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_AHBAP_SPIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_EZHV_DBGEN_MASK   (0x30000000U)
#define SYSCON3_DEBUG_FEATURES_EZHV_DBGEN_SHIFT  (28U)
/*! EZHV_DBGEN - EZH-V Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_EZHV_DBGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_EZHV_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_EZHV_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_CORESIGHT_EN_MASK (0xC0000000U)
#define SYSCON3_DEBUG_FEATURES_CORESIGHT_EN_SHIFT (30U)
/*! CORESIGHT_EN - CoreSight Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_CORESIGHT_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_CORESIGHT_EN_SHIFT)) & SYSCON3_DEBUG_FEATURES_CORESIGHT_EN_MASK)
/*! @} */

/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control */
/*! @{ */

#define SYSCON3_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0x3U)
#define SYSCON3_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (0U)
/*! CPU0_NIDEN - CPU0 Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CPU0_NIDEN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0xCU)
#define SYSCON3_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (2U)
/*! CPU0_DBGEN - CPU0 Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CPU0_DBGEN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0x30U)
#define SYSCON3_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (4U)
/*! CPU0_SPNIDEN - CPU0 Secure Privileged Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0xC0U)
#define SYSCON3_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (6U)
/*! CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0x300U)
#define SYSCON3_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (8U)
/*! CPU1_NIDEN - CPU1 Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CPU1_NIDEN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0xC00U)
#define SYSCON3_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (10U)
/*! CPU1_DBGEN - CPU1 Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CPU1_DBGEN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_CPU1_SPNIDEN_MASK (0x3000U)
#define SYSCON3_DEBUG_FEATURES_DP_CPU1_SPNIDEN_SHIFT (12U)
/*! CPU1_SPNIDEN - CPU1 Secure Privileged Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CPU1_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CPU1_SPNIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CPU1_SPNIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_CPU1_SPIDEN_MASK (0xC000U)
#define SYSCON3_DEBUG_FEATURES_DP_CPU1_SPIDEN_SHIFT (14U)
/*! CPU1_SPIDEN - CPU1 Secure Privileged Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CPU1_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CPU1_SPIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CPU1_SPIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_HIFI4_NIDEN_MASK (0x30000U)
#define SYSCON3_DEBUG_FEATURES_DP_HIFI4_NIDEN_SHIFT (16U)
/*! HIFI4_NIDEN - HiFi4 Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_HIFI4_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_HIFI4_NIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_HIFI4_NIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_HIFI4_DBGEN_MASK (0xC0000U)
#define SYSCON3_DEBUG_FEATURES_DP_HIFI4_DBGEN_SHIFT (18U)
/*! HIFI4_DBGEN - HiFi4 Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_HIFI4_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_HIFI4_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_HIFI4_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_HIFI1_NIDEN_MASK (0x300000U)
#define SYSCON3_DEBUG_FEATURES_DP_HIFI1_NIDEN_SHIFT (20U)
/*! HIFI1_NIDEN - HiFi1 Non-Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_HIFI1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_HIFI1_NIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_HIFI1_NIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_HIFI1_DBGEN_MASK (0xC00000U)
#define SYSCON3_DEBUG_FEATURES_DP_HIFI1_DBGEN_SHIFT (22U)
/*! HIFI1_DBGEN - HiFi1 Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_HIFI1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_HIFI1_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_HIFI1_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_AHBAP_DBGEN_MASK (0x3000000U)
#define SYSCON3_DEBUG_FEATURES_DP_AHBAP_DBGEN_SHIFT (24U)
/*! AHBAP_DBGEN - AHB-AP Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_AHBAP_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_AHBAP_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_AHBAP_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_AHBAP_SPIDEN_MASK (0xC000000U)
#define SYSCON3_DEBUG_FEATURES_DP_AHBAP_SPIDEN_SHIFT (26U)
/*! AHBAP_SPIDEN - AHB-AP Secure Privileged Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_AHBAP_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_AHBAP_SPIDEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_AHBAP_SPIDEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_EZHV_DBGEN_MASK (0x30000000U)
#define SYSCON3_DEBUG_FEATURES_DP_EZHV_DBGEN_SHIFT (28U)
/*! EZHV_DBGEN - EZH-V Invasive Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_EZHV_DBGEN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_EZHV_DBGEN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_EZHV_DBGEN_MASK)

#define SYSCON3_DEBUG_FEATURES_DP_CORESIGHT_EN_MASK (0xC0000000U)
#define SYSCON3_DEBUG_FEATURES_DP_CORESIGHT_EN_SHIFT (30U)
/*! CORESIGHT_EN - CoreSight Debug Control
 *  0b01..Disables
 *  0b10..Enables
 */
#define SYSCON3_DEBUG_FEATURES_DP_CORESIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_FEATURES_DP_CORESIGHT_EN_SHIFT)) & SYSCON3_DEBUG_FEATURES_DP_CORESIGHT_EN_MASK)
/*! @} */

/*! @name DEBUG_AUTH_BEACON - Debug Authentication Beacon */
/*! @{ */

#define SYSCON3_DEBUG_AUTH_BEACON_BEACON_MASK    (0xFFFFFFFFU)
#define SYSCON3_DEBUG_AUTH_BEACON_BEACON_SHIFT   (0U)
/*! BEACON - Beacon */
#define SYSCON3_DEBUG_AUTH_BEACON_BEACON(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON3_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON3_DEBUG_AUTH_BEACON_BEACON_MASK)
/*! @} */

/*! @name GRAY_CODE_LSB - Gray to Binary Converter - Gray Code [31:0] */
/*! @{ */

#define SYSCON3_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK (0xFFFFFFFFU)
#define SYSCON3_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT (0U)
/*! CODE_GRAY_31_0 - Gray Code [31:0] */
#define SYSCON3_GRAY_CODE_LSB_CODE_GRAY_31_0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON3_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT)) & SYSCON3_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK)
/*! @} */

/*! @name GRAY_CODE_MSB - Gray to Binary Converter - Gray Code [63:32] */
/*! @{ */

#define SYSCON3_GRAY_CODE_MSB_CODE_GRAY_63_32_MASK (0xFFFFFFFFU)
#define SYSCON3_GRAY_CODE_MSB_CODE_GRAY_63_32_SHIFT (0U)
/*! CODE_GRAY_63_32 - Gray Code [63:32] */
#define SYSCON3_GRAY_CODE_MSB_CODE_GRAY_63_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_GRAY_CODE_MSB_CODE_GRAY_63_32_SHIFT)) & SYSCON3_GRAY_CODE_MSB_CODE_GRAY_63_32_MASK)
/*! @} */

/*! @name BINARY_CODE_LSB - Gray to Binary Converter - Binary Code [31:0] */
/*! @{ */

#define SYSCON3_BINARY_CODE_LSB_CODE_BIN_31_0_MASK (0xFFFFFFFFU)
#define SYSCON3_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT (0U)
/*! CODE_BIN_31_0 - Binary Code [31:0] */
#define SYSCON3_BINARY_CODE_LSB_CODE_BIN_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT)) & SYSCON3_BINARY_CODE_LSB_CODE_BIN_31_0_MASK)
/*! @} */

/*! @name BINARY_CODE_MSB - Gray to Binary Converter - Binary Code [63:32] */
/*! @{ */

#define SYSCON3_BINARY_CODE_MSB_CODE_BIN_63_32_MASK (0xFFFFFFFFU)
#define SYSCON3_BINARY_CODE_MSB_CODE_BIN_63_32_SHIFT (0U)
/*! CODE_BIN_63_32 - Binary Code [63:32] */
#define SYSCON3_BINARY_CODE_MSB_CODE_BIN_63_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_BINARY_CODE_MSB_CODE_BIN_63_32_SHIFT)) & SYSCON3_BINARY_CODE_MSB_CODE_BIN_63_32_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SYSCON3_Register_Masks */


/* SYSCON3 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SYSCON3 base address */
  #define SYSCON3_BASE                             (0x50062000u)
  /** Peripheral SYSCON3 base address */
  #define SYSCON3_BASE_NS                          (0x40062000u)
  /** Peripheral SYSCON3 base pointer */
  #define SYSCON3                                  ((SYSCON3_Type *)SYSCON3_BASE)
  /** Peripheral SYSCON3 base pointer */
  #define SYSCON3_NS                               ((SYSCON3_Type *)SYSCON3_BASE_NS)
  /** Array initializer of SYSCON3 peripheral base addresses */
  #define SYSCON3_BASE_ADDRS                       { SYSCON3_BASE }
  /** Array initializer of SYSCON3 peripheral base pointers */
  #define SYSCON3_BASE_PTRS                        { SYSCON3 }
  /** Array initializer of SYSCON3 peripheral base addresses */
  #define SYSCON3_BASE_ADDRS_NS                    { SYSCON3_BASE_NS }
  /** Array initializer of SYSCON3 peripheral base pointers */
  #define SYSCON3_BASE_PTRS_NS                     { SYSCON3_NS }
#else
  /** Peripheral SYSCON3 base address */
  #define SYSCON3_BASE                             (0x40062000u)
  /** Peripheral SYSCON3 base pointer */
  #define SYSCON3                                  ((SYSCON3_Type *)SYSCON3_BASE)
  /** Array initializer of SYSCON3 peripheral base addresses */
  #define SYSCON3_BASE_ADDRS                       { SYSCON3_BASE }
  /** Array initializer of SYSCON3 peripheral base pointers */
  #define SYSCON3_BASE_PTRS                        { SYSCON3 }
#endif

/*!
 * @}
 */ /* end of group SYSCON3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSCON4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON4_Peripheral_Access_Layer SYSCON4 Peripheral Access Layer
 * @{
 */

/** SYSCON4 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[40];
  __IO uint32_t MMU2_MEM_CTRL;                     /**< MMU2 Memory Control, offset: 0x28 */
  __IO uint32_t XSPI2_MEM_CTRL;                    /**< XSPI2 Memory Control, offset: 0x2C */
  __IO uint32_t EZHV_MEM_CTRL;                     /**< EZH-V Memory Control, offset: 0x30 */
  __IO uint32_t LCDIF_MEM_CTRL;                    /**< LCDIF Memory Control, offset: 0x34 */
       uint8_t RESERVED_1[4];
  __IO uint32_t JPEGDEC_MEM_CTRL;                  /**< JPEGDEC Memory Control, offset: 0x3C */
  __IO uint32_t PNGDEC_MEM_CTRL;                   /**< PNGDEC Memory Control, offset: 0x40 */
       uint8_t RESERVED_2[4];
  __IO uint32_t MIPI_MEM_CTRL;                     /**< MIPI Memory Control, offset: 0x48 */
  __IO uint32_t VGPU_MEM_CTRL;                     /**< VGPU Memory Control, offset: 0x4C */
       uint8_t RESERVED_3[128];
  __IO uint32_t EZHV_RSTBASE;                      /**< EZH-V Reset Base, offset: 0xD0 */
  __IO uint32_t EZHV_RSTMTVEC;                     /**< EZH-V MTVEC Reset Value, offset: 0xD4 */
  __IO uint32_t EZHV_RSTSTVEC;                     /**< EZH-V STVEC Reset Value, offset: 0xD8 */
  __IO uint32_t EZHV_VOFFSET_T;                    /**< EZH-V Interrupt Vector Offset, offset: 0xDC */
  __IO uint32_t EZHV2ARM_INT_EN;                   /**< EZH-V To Arm Interrupt Enable, offset: 0xE0 */
  __IO uint32_t EZHV2ARM_INT_CHAN;                 /**< EZH-V Interrupt Channel, offset: 0xE4 */
  __IO uint32_t ARM2EZHV_INT_CTRL;                 /**< Arm To EZH-V Interrupt Control, offset: 0xE8 */
       uint8_t RESERVED_4[68];
  __IO uint32_t MIPI_DSI_CTRL;                     /**< MIPI_DSI Control, offset: 0x130 */
       uint8_t RESERVED_5[332];
  __IO uint32_t MEDIA_AUTOGATE_EN;                 /**< VDD2_MEDIA Auto Gating Enable, offset: 0x280 */
       uint8_t RESERVED_6[652];
  __IO uint32_t USB0_MEM_CTRL;                     /**< USB0 Memory Control, offset: 0x510 */
  __IO uint32_t USB1_MEM_CTRL;                     /**< USB1 Memory Control, offset: 0x514 */
  __IO uint32_t USDHC0_MEM_CTRL;                   /**< uSDHC0 Memory Control, offset: 0x518 */
  __IO uint32_t USDHC1_MEM_CTRL;                   /**< uSDHC1 Memory Control, offset: 0x51C */
       uint8_t RESERVED_7[260];
  __IO uint32_t GPIO_BANK4_CFG;                    /**< PIO4 Configuration, offset: 0x624 */
  __IO uint32_t GPIO_BANK5_CFG;                    /**< PIO5 Configuration, offset: 0x628 */
  __IO uint32_t GPIO_BANK6_CFG;                    /**< PIO6 Configuration, offset: 0x62C */
       uint8_t RESERVED_8[32];
  __IO uint32_t USBPHY0_CLK_ACTIVE;                /**< USBPHY0 CLK Active, offset: 0x650 */
} SYSCON4_Type;

/* ----------------------------------------------------------------------------
   -- SYSCON4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON4_Register_Masks SYSCON4 Register Masks
 * @{
 */

/*! @name MMU2_MEM_CTRL - MMU2 Memory Control */
/*! @{ */

#define SYSCON4_MMU2_MEM_CTRL_MEM_STDBY_MASK     (0x80U)
#define SYSCON4_MMU2_MEM_CTRL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_MMU2_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_MMU2_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_MMU2_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_MMU2_MEM_CTRL_MEM_IG_MASK        (0x100U)
#define SYSCON4_MMU2_MEM_CTRL_MEM_IG_SHIFT       (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_MMU2_MEM_CTRL_MEM_IG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON4_MMU2_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON4_MMU2_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name XSPI2_MEM_CTRL - XSPI2 Memory Control */
/*! @{ */

#define SYSCON4_XSPI2_MEM_CTRL_MEM_STDBY_MASK    (0x80U)
#define SYSCON4_XSPI2_MEM_CTRL_MEM_STDBY_SHIFT   (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_XSPI2_MEM_CTRL_MEM_STDBY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON4_XSPI2_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_XSPI2_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_XSPI2_MEM_CTRL_MEM_WIG_MASK      (0x100U)
#define SYSCON4_XSPI2_MEM_CTRL_MEM_WIG_SHIFT     (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_XSPI2_MEM_CTRL_MEM_WIG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON4_XSPI2_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_XSPI2_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_XSPI2_MEM_CTRL_MEM_RIG_MASK      (0x200U)
#define SYSCON4_XSPI2_MEM_CTRL_MEM_RIG_SHIFT     (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_XSPI2_MEM_CTRL_MEM_RIG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON4_XSPI2_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_XSPI2_MEM_CTRL_MEM_RIG_MASK)
/*! @} */

/*! @name EZHV_MEM_CTRL - EZH-V Memory Control */
/*! @{ */

#define SYSCON4_EZHV_MEM_CTRL_MEM_STDBY_MASK     (0x80U)
#define SYSCON4_EZHV_MEM_CTRL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_EZHV_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_EZHV_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_EZHV_MEM_CTRL_MEM_IG_MASK        (0x100U)
#define SYSCON4_EZHV_MEM_CTRL_MEM_IG_SHIFT       (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_EZHV_MEM_CTRL_MEM_IG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON4_EZHV_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name LCDIF_MEM_CTRL - LCDIF Memory Control */
/*! @{ */

#define SYSCON4_LCDIF_MEM_CTRL_MEM_STDBY_MASK    (0x80U)
#define SYSCON4_LCDIF_MEM_CTRL_MEM_STDBY_SHIFT   (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_LCDIF_MEM_CTRL_MEM_STDBY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON4_LCDIF_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_LCDIF_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_LCDIF_MEM_CTRL_MEM_IG_MASK       (0x100U)
#define SYSCON4_LCDIF_MEM_CTRL_MEM_IG_SHIFT      (8U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_LCDIF_MEM_CTRL_MEM_IG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_LCDIF_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON4_LCDIF_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name JPEGDEC_MEM_CTRL - JPEGDEC Memory Control */
/*! @{ */

#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_STDBY_MASK  (0x80U)
#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_STDBY_SHIFT (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_STDBY(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON4_JPEGDEC_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_JPEGDEC_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_WIG_MASK    (0x100U)
#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_WIG_SHIFT   (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_WIG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON4_JPEGDEC_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_JPEGDEC_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_RIG_MASK    (0x200U)
#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_RIG_SHIFT   (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_RIG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON4_JPEGDEC_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_JPEGDEC_MEM_CTRL_MEM_RIG_MASK)

#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_IG_MASK     (0x400U)
#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_IG_SHIFT    (10U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_JPEGDEC_MEM_CTRL_MEM_IG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_JPEGDEC_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON4_JPEGDEC_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name PNGDEC_MEM_CTRL - PNGDEC Memory Control */
/*! @{ */

#define SYSCON4_PNGDEC_MEM_CTRL_MEM_STDBY_MASK   (0x80U)
#define SYSCON4_PNGDEC_MEM_CTRL_MEM_STDBY_SHIFT  (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_PNGDEC_MEM_CTRL_MEM_STDBY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON4_PNGDEC_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_PNGDEC_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_PNGDEC_MEM_CTRL_MEM_WIG_MASK     (0x100U)
#define SYSCON4_PNGDEC_MEM_CTRL_MEM_WIG_SHIFT    (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_PNGDEC_MEM_CTRL_MEM_WIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_PNGDEC_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_PNGDEC_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_PNGDEC_MEM_CTRL_MEM_RIG_MASK     (0x200U)
#define SYSCON4_PNGDEC_MEM_CTRL_MEM_RIG_SHIFT    (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_PNGDEC_MEM_CTRL_MEM_RIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_PNGDEC_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_PNGDEC_MEM_CTRL_MEM_RIG_MASK)

#define SYSCON4_PNGDEC_MEM_CTRL_MEM_IG_MASK      (0x400U)
#define SYSCON4_PNGDEC_MEM_CTRL_MEM_IG_SHIFT     (10U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_PNGDEC_MEM_CTRL_MEM_IG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON4_PNGDEC_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON4_PNGDEC_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name MIPI_MEM_CTRL - MIPI Memory Control */
/*! @{ */

#define SYSCON4_MIPI_MEM_CTRL_MEM_STDBY_MASK     (0x80U)
#define SYSCON4_MIPI_MEM_CTRL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_MIPI_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_MIPI_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_MIPI_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_MIPI_MEM_CTRL_MEM_WIG_MASK       (0x100U)
#define SYSCON4_MIPI_MEM_CTRL_MEM_WIG_SHIFT      (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_MIPI_MEM_CTRL_MEM_WIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_MIPI_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_MIPI_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_MIPI_MEM_CTRL_MEM_RIG_MASK       (0x200U)
#define SYSCON4_MIPI_MEM_CTRL_MEM_RIG_SHIFT      (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_MIPI_MEM_CTRL_MEM_RIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_MIPI_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_MIPI_MEM_CTRL_MEM_RIG_MASK)
/*! @} */

/*! @name VGPU_MEM_CTRL - VGPU Memory Control */
/*! @{ */

#define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK     (0x80U)
#define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_VGPU_MEM_CTRL_MEM_WIG_MASK       (0x100U)
#define SYSCON4_VGPU_MEM_CTRL_MEM_WIG_SHIFT      (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_VGPU_MEM_CTRL_MEM_WIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_VGPU_MEM_CTRL_MEM_RIG_MASK       (0x200U)
#define SYSCON4_VGPU_MEM_CTRL_MEM_RIG_SHIFT      (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_VGPU_MEM_CTRL_MEM_RIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_RIG_MASK)

#define SYSCON4_VGPU_MEM_CTRL_MEM_IG_MASK        (0x400U)
#define SYSCON4_VGPU_MEM_CTRL_MEM_IG_SHIFT       (10U)
/*! MEM_IG - Memory Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_VGPU_MEM_CTRL_MEM_IG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_IG_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_IG_MASK)
/*! @} */

/*! @name EZHV_RSTBASE - EZH-V Reset Base */
/*! @{ */

#define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK   (0x3FFFFFFFU)
#define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT  (0U)
/*! EZHV_RSTBASE - Reset Exception Handler Base Address */
#define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
/*! @} */

/*! @name EZHV_RSTMTVEC - EZH-V MTVEC Reset Value */
/*! @{ */

#define SYSCON4_EZHV_RSTMTVEC_EZHV_RSTMTVEC_MASK (0xFFFFFFFFU)
#define SYSCON4_EZHV_RSTMTVEC_EZHV_RSTMTVEC_SHIFT (0U)
/*! EZHV_RSTMTVEC - Reset Value of CSRs MTVEC */
#define SYSCON4_EZHV_RSTMTVEC_EZHV_RSTMTVEC(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV_RSTMTVEC_EZHV_RSTMTVEC_SHIFT)) & SYSCON4_EZHV_RSTMTVEC_EZHV_RSTMTVEC_MASK)
/*! @} */

/*! @name EZHV_RSTSTVEC - EZH-V STVEC Reset Value */
/*! @{ */

#define SYSCON4_EZHV_RSTSTVEC_EZHV_RSTSTVEC_MASK (0xFFFFFFFFU)
#define SYSCON4_EZHV_RSTSTVEC_EZHV_RSTSTVEC_SHIFT (0U)
/*! EZHV_RSTSTVEC - Reset Value of CSRs STVEC */
#define SYSCON4_EZHV_RSTSTVEC_EZHV_RSTSTVEC(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV_RSTSTVEC_EZHV_RSTSTVEC_SHIFT)) & SYSCON4_EZHV_RSTSTVEC_EZHV_RSTSTVEC_MASK)
/*! @} */

/*! @name EZHV_VOFFSET_T - EZH-V Interrupt Vector Offset */
/*! @{ */

#define SYSCON4_EZHV_VOFFSET_T_EZHV_VOFFSET_T_MASK (0x3FFFU)
#define SYSCON4_EZHV_VOFFSET_T_EZHV_VOFFSET_T_SHIFT (0U)
/*! EZHV_VOFFSET_T - Interrupt Vector Offset for Vectored Interrupts */
#define SYSCON4_EZHV_VOFFSET_T_EZHV_VOFFSET_T(x) (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV_VOFFSET_T_EZHV_VOFFSET_T_SHIFT)) & SYSCON4_EZHV_VOFFSET_T_EZHV_VOFFSET_T_MASK)
/*! @} */

/*! @name EZHV2ARM_INT_EN - EZH-V To Arm Interrupt Enable */
/*! @{ */

#define SYSCON4_EZHV2ARM_INT_EN_INT_EN_MASK      (0xFFFFU)
#define SYSCON4_EZHV2ARM_INT_EN_INT_EN_SHIFT     (0U)
/*! INT_EN - Interrupt Enable */
#define SYSCON4_EZHV2ARM_INT_EN_INT_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV2ARM_INT_EN_INT_EN_SHIFT)) & SYSCON4_EZHV2ARM_INT_EN_INT_EN_MASK)

#define SYSCON4_EZHV2ARM_INT_EN_CPU0_RXEV_EN_MASK (0x10000U)
#define SYSCON4_EZHV2ARM_INT_EN_CPU0_RXEV_EN_SHIFT (16U)
/*! CPU0_RXEV_EN - CPU0 RXEV Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON4_EZHV2ARM_INT_EN_CPU0_RXEV_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV2ARM_INT_EN_CPU0_RXEV_EN_SHIFT)) & SYSCON4_EZHV2ARM_INT_EN_CPU0_RXEV_EN_MASK)

#define SYSCON4_EZHV2ARM_INT_EN_CPU1_RXEV_EN_MASK (0x20000U)
#define SYSCON4_EZHV2ARM_INT_EN_CPU1_RXEV_EN_SHIFT (17U)
/*! CPU1_RXEV_EN - CPU1 RXEV Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON4_EZHV2ARM_INT_EN_CPU1_RXEV_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV2ARM_INT_EN_CPU1_RXEV_EN_SHIFT)) & SYSCON4_EZHV2ARM_INT_EN_CPU1_RXEV_EN_MASK)
/*! @} */

/*! @name EZHV2ARM_INT_CHAN - EZH-V Interrupt Channel */
/*! @{ */

#define SYSCON4_EZHV2ARM_INT_CHAN_INT_CHAN_MASK  (0xFFFFU)
#define SYSCON4_EZHV2ARM_INT_CHAN_INT_CHAN_SHIFT (0U)
/*! INT_CHAN - EZH-V Interrupt Outputs */
#define SYSCON4_EZHV2ARM_INT_CHAN_INT_CHAN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON4_EZHV2ARM_INT_CHAN_INT_CHAN_SHIFT)) & SYSCON4_EZHV2ARM_INT_CHAN_INT_CHAN_MASK)
/*! @} */

/*! @name ARM2EZHV_INT_CTRL - Arm To EZH-V Interrupt Control */
/*! @{ */

#define SYSCON4_ARM2EZHV_INT_CTRL_MEIP_MASK      (0x1U)
#define SYSCON4_ARM2EZHV_INT_CTRL_MEIP_SHIFT     (0U)
/*! MEIP - Machine External Input Interrupt Request
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON4_ARM2EZHV_INT_CTRL_MEIP(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON4_ARM2EZHV_INT_CTRL_MEIP_SHIFT)) & SYSCON4_ARM2EZHV_INT_CTRL_MEIP_MASK)

#define SYSCON4_ARM2EZHV_INT_CTRL_SEIP_MASK      (0x2U)
#define SYSCON4_ARM2EZHV_INT_CTRL_SEIP_SHIFT     (1U)
/*! SEIP - Supervisor External Input Interrupt Request
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON4_ARM2EZHV_INT_CTRL_SEIP(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON4_ARM2EZHV_INT_CTRL_SEIP_SHIFT)) & SYSCON4_ARM2EZHV_INT_CTRL_SEIP_MASK)

#define SYSCON4_ARM2EZHV_INT_CTRL_MSIP_MASK      (0x4U)
#define SYSCON4_ARM2EZHV_INT_CTRL_MSIP_SHIFT     (2U)
/*! MSIP - Machine Software Input Interrupt Request
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON4_ARM2EZHV_INT_CTRL_MSIP(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON4_ARM2EZHV_INT_CTRL_MSIP_SHIFT)) & SYSCON4_ARM2EZHV_INT_CTRL_MSIP_MASK)

#define SYSCON4_ARM2EZHV_INT_CTRL_MTIP_MASK      (0x8U)
#define SYSCON4_ARM2EZHV_INT_CTRL_MTIP_SHIFT     (3U)
/*! MTIP - Machine Timer Input Interrupt Request
 *  0b0..Disables
 *  0b1..Enables
 */
#define SYSCON4_ARM2EZHV_INT_CTRL_MTIP(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON4_ARM2EZHV_INT_CTRL_MTIP_SHIFT)) & SYSCON4_ARM2EZHV_INT_CTRL_MTIP_MASK)
/*! @} */

/*! @name MIPI_DSI_CTRL - MIPI_DSI Control */
/*! @{ */

#define SYSCON4_MIPI_DSI_CTRL_DSI_SD_MASK        (0x1U)
#define SYSCON4_MIPI_DSI_CTRL_DSI_SD_SHIFT       (0U)
/*! DSI_SD - DSI Shutdown Control
 *  0b0..Do not send
 *  0b1..Send
 */
#define SYSCON4_MIPI_DSI_CTRL_DSI_SD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON4_MIPI_DSI_CTRL_DSI_SD_SHIFT)) & SYSCON4_MIPI_DSI_CTRL_DSI_SD_MASK)

#define SYSCON4_MIPI_DSI_CTRL_DSI_CM_MASK        (0x2U)
#define SYSCON4_MIPI_DSI_CTRL_DSI_CM_SHIFT       (1U)
/*! DSI_CM - DSI Color Mode Control
 *  0b0..Normal (full color) mode
 *  0b1..Low color mode (8-bit)
 */
#define SYSCON4_MIPI_DSI_CTRL_DSI_CM(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON4_MIPI_DSI_CTRL_DSI_CM_SHIFT)) & SYSCON4_MIPI_DSI_CTRL_DSI_CM_MASK)

#define SYSCON4_MIPI_DSI_CTRL_DSI_TX_ACTIVE_MASK (0x4U)
#define SYSCON4_MIPI_DSI_CTRL_DSI_TX_ACTIVE_SHIFT (2U)
/*! DSI_TX_ACTIVE - DSI Transmit Active */
#define SYSCON4_MIPI_DSI_CTRL_DSI_TX_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON4_MIPI_DSI_CTRL_DSI_TX_ACTIVE_SHIFT)) & SYSCON4_MIPI_DSI_CTRL_DSI_TX_ACTIVE_MASK)
/*! @} */

/*! @name MEDIA_AUTOGATE_EN - VDD2_MEDIA Auto Gating Enable */
/*! @{ */

#define SYSCON4_MEDIA_AUTOGATE_EN_MATRIX_EN_MASK (0x1U)
#define SYSCON4_MEDIA_AUTOGATE_EN_MATRIX_EN_SHIFT (0U)
/*! MATRIX_EN - VDD2_MEDIA Automatic Clock Gating Enable
 *  0b1..Enables clock gating
 *  0b0..Disables clock gating (continuous clock)
 */
#define SYSCON4_MEDIA_AUTOGATE_EN_MATRIX_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON4_MEDIA_AUTOGATE_EN_MATRIX_EN_SHIFT)) & SYSCON4_MEDIA_AUTOGATE_EN_MATRIX_EN_MASK)
/*! @} */

/*! @name USB0_MEM_CTRL - USB0 Memory Control */
/*! @{ */

#define SYSCON4_USB0_MEM_CTRL_MEM_STDBY_MASK     (0x80U)
#define SYSCON4_USB0_MEM_CTRL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USB0_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_USB0_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_USB0_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_USB0_MEM_CTRL_MEM_WIG_MASK       (0x100U)
#define SYSCON4_USB0_MEM_CTRL_MEM_WIG_SHIFT      (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USB0_MEM_CTRL_MEM_WIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_USB0_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_USB0_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_USB0_MEM_CTRL_MEM_RIG_MASK       (0x200U)
#define SYSCON4_USB0_MEM_CTRL_MEM_RIG_SHIFT      (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USB0_MEM_CTRL_MEM_RIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_USB0_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_USB0_MEM_CTRL_MEM_RIG_MASK)
/*! @} */

/*! @name USB1_MEM_CTRL - USB1 Memory Control */
/*! @{ */

#define SYSCON4_USB1_MEM_CTRL_MEM_STDBY_MASK     (0x80U)
#define SYSCON4_USB1_MEM_CTRL_MEM_STDBY_SHIFT    (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USB1_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_USB1_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_USB1_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_USB1_MEM_CTRL_MEM_WIG_MASK       (0x100U)
#define SYSCON4_USB1_MEM_CTRL_MEM_WIG_SHIFT      (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USB1_MEM_CTRL_MEM_WIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_USB1_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_USB1_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_USB1_MEM_CTRL_MEM_RIG_MASK       (0x200U)
#define SYSCON4_USB1_MEM_CTRL_MEM_RIG_SHIFT      (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USB1_MEM_CTRL_MEM_RIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON4_USB1_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_USB1_MEM_CTRL_MEM_RIG_MASK)
/*! @} */

/*! @name USDHC0_MEM_CTRL - uSDHC0 Memory Control */
/*! @{ */

#define SYSCON4_USDHC0_MEM_CTRL_MEM_STDBY_MASK   (0x80U)
#define SYSCON4_USDHC0_MEM_CTRL_MEM_STDBY_SHIFT  (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USDHC0_MEM_CTRL_MEM_STDBY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON4_USDHC0_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_USDHC0_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_USDHC0_MEM_CTRL_MEM_WIG_MASK     (0x100U)
#define SYSCON4_USDHC0_MEM_CTRL_MEM_WIG_SHIFT    (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USDHC0_MEM_CTRL_MEM_WIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_USDHC0_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_USDHC0_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_USDHC0_MEM_CTRL_MEM_RIG_MASK     (0x200U)
#define SYSCON4_USDHC0_MEM_CTRL_MEM_RIG_SHIFT    (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USDHC0_MEM_CTRL_MEM_RIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_USDHC0_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_USDHC0_MEM_CTRL_MEM_RIG_MASK)
/*! @} */

/*! @name USDHC1_MEM_CTRL - uSDHC1 Memory Control */
/*! @{ */

#define SYSCON4_USDHC1_MEM_CTRL_MEM_STDBY_MASK   (0x80U)
#define SYSCON4_USDHC1_MEM_CTRL_MEM_STDBY_SHIFT  (7U)
/*! MEM_STDBY - Memory Standby Mode
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USDHC1_MEM_CTRL_MEM_STDBY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON4_USDHC1_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_USDHC1_MEM_CTRL_MEM_STDBY_MASK)

#define SYSCON4_USDHC1_MEM_CTRL_MEM_WIG_MASK     (0x100U)
#define SYSCON4_USDHC1_MEM_CTRL_MEM_WIG_SHIFT    (8U)
/*! MEM_WIG - Memory Write Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USDHC1_MEM_CTRL_MEM_WIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_USDHC1_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCON4_USDHC1_MEM_CTRL_MEM_WIG_MASK)

#define SYSCON4_USDHC1_MEM_CTRL_MEM_RIG_MASK     (0x200U)
#define SYSCON4_USDHC1_MEM_CTRL_MEM_RIG_SHIFT    (9U)
/*! MEM_RIG - Memory Read Input Gating
 *  0b0..Inactive
 *  0b1..Active
 */
#define SYSCON4_USDHC1_MEM_CTRL_MEM_RIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON4_USDHC1_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCON4_USDHC1_MEM_CTRL_MEM_RIG_MASK)
/*! @} */

/*! @name GPIO_BANK4_CFG - PIO4 Configuration */
/*! @{ */

#define SYSCON4_GPIO_BANK4_CFG_BANK4_CFG_MASK    (0x80000000U)
#define SYSCON4_GPIO_BANK4_CFG_BANK4_CFG_SHIFT   (31U)
/*! BANK4_CFG - Transmit Driver Size Configuration
 *  0b0..1.8 V
 *  0b1..1.2 V
 */
#define SYSCON4_GPIO_BANK4_CFG_BANK4_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON4_GPIO_BANK4_CFG_BANK4_CFG_SHIFT)) & SYSCON4_GPIO_BANK4_CFG_BANK4_CFG_MASK)
/*! @} */

/*! @name GPIO_BANK5_CFG - PIO5 Configuration */
/*! @{ */

#define SYSCON4_GPIO_BANK5_CFG_BANK5_CFG_MASK    (0x80000000U)
#define SYSCON4_GPIO_BANK5_CFG_BANK5_CFG_SHIFT   (31U)
/*! BANK5_CFG - Transmit Driver Size Configuration
 *  0b0..1.8 V
 *  0b1..1.2 V
 */
#define SYSCON4_GPIO_BANK5_CFG_BANK5_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON4_GPIO_BANK5_CFG_BANK5_CFG_SHIFT)) & SYSCON4_GPIO_BANK5_CFG_BANK5_CFG_MASK)
/*! @} */

/*! @name GPIO_BANK6_CFG - PIO6 Configuration */
/*! @{ */

#define SYSCON4_GPIO_BANK6_CFG_BANK6_CFG_MASK    (0x80000000U)
#define SYSCON4_GPIO_BANK6_CFG_BANK6_CFG_SHIFT   (31U)
/*! BANK6_CFG - Transmit Driver Size Configuration
 *  0b0..1.8 V
 *  0b1..1.2 V
 */
#define SYSCON4_GPIO_BANK6_CFG_BANK6_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON4_GPIO_BANK6_CFG_BANK6_CFG_SHIFT)) & SYSCON4_GPIO_BANK6_CFG_BANK6_CFG_MASK)
/*! @} */

/*! @name USBPHY0_CLK_ACTIVE - USBPHY0 CLK Active */
/*! @{ */

#define SYSCON4_USBPHY0_CLK_ACTIVE_IPG_CLK_ACTIVE_MASK (0x1U)
#define SYSCON4_USBPHY0_CLK_ACTIVE_IPG_CLK_ACTIVE_SHIFT (0U)
/*! IPG_CLK_ACTIVE - IPG_CLK Active
 *  0b1..IPG_CLK is active
 *  0b0..IPG_CLK is inactive
 */
#define SYSCON4_USBPHY0_CLK_ACTIVE_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON4_USBPHY0_CLK_ACTIVE_IPG_CLK_ACTIVE_SHIFT)) & SYSCON4_USBPHY0_CLK_ACTIVE_IPG_CLK_ACTIVE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SYSCON4_Register_Masks */


/* SYSCON4 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SYSCON4 base address */
  #define SYSCON4_BASE                             (0x500A2000u)
  /** Peripheral SYSCON4 base address */
  #define SYSCON4_BASE_NS                          (0x400A2000u)
  /** Peripheral SYSCON4 base pointer */
  #define SYSCON4                                  ((SYSCON4_Type *)SYSCON4_BASE)
  /** Peripheral SYSCON4 base pointer */
  #define SYSCON4_NS                               ((SYSCON4_Type *)SYSCON4_BASE_NS)
  /** Array initializer of SYSCON4 peripheral base addresses */
  #define SYSCON4_BASE_ADDRS                       { SYSCON4_BASE }
  /** Array initializer of SYSCON4 peripheral base pointers */
  #define SYSCON4_BASE_PTRS                        { SYSCON4 }
  /** Array initializer of SYSCON4 peripheral base addresses */
  #define SYSCON4_BASE_ADDRS_NS                    { SYSCON4_BASE_NS }
  /** Array initializer of SYSCON4 peripheral base pointers */
  #define SYSCON4_BASE_PTRS_NS                     { SYSCON4_NS }
#else
  /** Peripheral SYSCON4 base address */
  #define SYSCON4_BASE                             (0x400A2000u)
  /** Peripheral SYSCON4 base pointer */
  #define SYSCON4                                  ((SYSCON4_Type *)SYSCON4_BASE)
  /** Array initializer of SYSCON4 peripheral base addresses */
  #define SYSCON4_BASE_ADDRS                       { SYSCON4_BASE }
  /** Array initializer of SYSCON4 peripheral base pointers */
  #define SYSCON4_BASE_PTRS                        { SYSCON4 }
#endif

/*!
 * @}
 */ /* end of group SYSCON4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSPM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer
 * @{
 */

/** SYSPM - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x30 */
    __IO uint32_t PMCR;                              /**< Performance Monitor Control, array offset: 0x0, array step: 0x30 */
         uint8_t RESERVED_0[12];
    __I  uint8_t PMICTR_HI;                          /**< Performance Monitor Instruction Counter, array offset: 0x10, array step: 0x30, available only on: CMX_PERFMON0, CMX_PERFMON1 (missing on CMX_PERFMON2, CMX_PERFMON3) */
         uint8_t RESERVED_1[3];
    __I  uint32_t PMICTR_LO;                         /**< Performance Monitor Instruction Counter, array offset: 0x14, array step: 0x30, available only on: CMX_PERFMON0, CMX_PERFMON1 (missing on CMX_PERFMON2, CMX_PERFMON3) */
    struct {                                         /* offset: 0x18, array step: index*0x30, index2*0x8 */
      __I  uint8_t HI;                                 /**< Performance Monitor Event Counter, array offset: 0x18, array step: index*0x30, index2*0x8 */
           uint8_t RESERVED_0[3];
      __I  uint32_t LO;                                /**< Performance Monitor Event Counter, array offset: 0x1C, array step: index*0x30, index2*0x8 */
    } PMECTR[3];
  } PMCR[1];
} SYSPM_Type;

/* ----------------------------------------------------------------------------
   -- SYSPM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSPM_Register_Masks SYSPM Register Masks
 * @{
 */

/*! @name PMCR - Performance Monitor Control */
/*! @{ */

#define SYSPM_PMCR_MENB_MASK                     (0x1U)
#define SYSPM_PMCR_MENB_SHIFT                    (0U)
/*! MENB - Module Is Enabled
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSPM_PMCR_MENB(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK)

#define SYSPM_PMCR_SSC_MASK                      (0xEU)
#define SYSPM_PMCR_SSC_SHIFT                     (1U)
/*! SSC - Start and Stop Control
 *  0b000..Idle or no-op
 *  0b001..Local stop
 *  0b010, 0b011..Local start
 *  0b100..
 *  0b101..
 *  0b110, 0b111..
 */
#define SYSPM_PMCR_SSC(x)                        (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK)

#define SYSPM_PMCR_CMODE_MASK                    (0x30U)
#define SYSPM_PMCR_CMODE_SHIFT                   (4U)
/*! CMODE - Count Mode
 *  0b00..Counted in both User and Privileged modes
 *  0b01..
 *  0b10..
 *  0b11..
 */
#define SYSPM_PMCR_CMODE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK)

#define SYSPM_PMCR_DCIFSH_MASK                   (0x40U)
#define SYSPM_PMCR_DCIFSH_SHIFT                  (6U)
/*! DCIFSH - Disable Counters if Stopped or Halted
 *  0b0..Continue
 *  0b1..Stop
 */
#define SYSPM_PMCR_DCIFSH(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_DCIFSH_SHIFT)) & SYSPM_PMCR_DCIFSH_MASK)

#define SYSPM_PMCR_RICTR_MASK                    (0x80U)
#define SYSPM_PMCR_RICTR_SHIFT                   (7U)
/*! RICTR - Reset Instruction Counter
 *  0b0..Do not reset
 *  0b1..Clear
 */
#define SYSPM_PMCR_RICTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RICTR_SHIFT)) & SYSPM_PMCR_RICTR_MASK)

#define SYSPM_PMCR_RECTR1_MASK                   (0x100U)
#define SYSPM_PMCR_RECTR1_SHIFT                  (8U)
/*! RECTR1 - Reset Event Counter 1
 *  0b0..Run normally
 *  0b1..Reset
 */
#define SYSPM_PMCR_RECTR1(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK)

#define SYSPM_PMCR_RECTR2_MASK                   (0x200U)
#define SYSPM_PMCR_RECTR2_SHIFT                  (9U)
/*! RECTR2 - Reset Event Counter 2
 *  0b0..Run normally
 *  0b1..Reset
 */
#define SYSPM_PMCR_RECTR2(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK)

#define SYSPM_PMCR_RECTR3_MASK                   (0x400U)
#define SYSPM_PMCR_RECTR3_SHIFT                  (10U)
/*! RECTR3 - Reset Event Counter 3
 *  0b0..Run normally
 *  0b1..Reset
 */
#define SYSPM_PMCR_RECTR3(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK)

#define SYSPM_PMCR_SELEVT1_MASK                  (0x3F800U)
#define SYSPM_PMCR_SELEVT1_SHIFT                 (11U)
/*! SELEVT1 - Select Event 1 */
#define SYSPM_PMCR_SELEVT1(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK)

#define SYSPM_PMCR_SELEVT2_MASK                  (0x1FC0000U)
#define SYSPM_PMCR_SELEVT2_SHIFT                 (18U)
/*! SELEVT2 - Select Event 2 */
#define SYSPM_PMCR_SELEVT2(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK)

#define SYSPM_PMCR_SELEVT3_MASK                  (0xFE000000U)
#define SYSPM_PMCR_SELEVT3_SHIFT                 (25U)
/*! SELEVT3 - Select Event 3 */
#define SYSPM_PMCR_SELEVT3(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK)
/*! @} */

/* The count of SYSPM_PMCR */
#define SYSPM_PMCR_COUNT                         (1U)

/*! @name PMICTR_HI - Performance Monitor Instruction Counter */
/*! @{ */

#define SYSPM_PMICTR_HI_ICTR_MASK                (0xFFU)
#define SYSPM_PMICTR_HI_ICTR_SHIFT               (0U)
/*! ICTR - Instruction Counter */
#define SYSPM_PMICTR_HI_ICTR(x)                  (((uint8_t)(((uint8_t)(x)) << SYSPM_PMICTR_HI_ICTR_SHIFT)) & SYSPM_PMICTR_HI_ICTR_MASK)
/*! @} */

/* The count of SYSPM_PMICTR_HI */
#define SYSPM_PMICTR_HI_COUNT                    (1U)

/*! @name PMICTR_LO - Performance Monitor Instruction Counter */
/*! @{ */

#define SYSPM_PMICTR_LO_ICTR_MASK                (0xFFFFFFFFU)
#define SYSPM_PMICTR_LO_ICTR_SHIFT               (0U)
/*! ICTR - Instruction Counter */
#define SYSPM_PMICTR_LO_ICTR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSPM_PMICTR_LO_ICTR_SHIFT)) & SYSPM_PMICTR_LO_ICTR_MASK)
/*! @} */

/* The count of SYSPM_PMICTR_LO */
#define SYSPM_PMICTR_LO_COUNT                    (1U)

/*! @name HI - Performance Monitor Event Counter */
/*! @{ */

#define SYSPM_HI_ECTR_MASK                       (0xFFU)
#define SYSPM_HI_ECTR_SHIFT                      (0U)
/*! ECTR - Event Counter */
#define SYSPM_HI_ECTR(x)                         (((uint8_t)(((uint8_t)(x)) << SYSPM_HI_ECTR_SHIFT)) & SYSPM_HI_ECTR_MASK)
/*! @} */

/* The count of SYSPM_HI */
#define SYSPM_HI_COUNT                           (1U)

/* The count of SYSPM_HI */
#define SYSPM_HI_COUNT2                          (3U)

/*! @name LO - Performance Monitor Event Counter */
/*! @{ */

#define SYSPM_LO_ECTR_MASK                       (0xFFFFFFFFU)
#define SYSPM_LO_ECTR_SHIFT                      (0U)
/*! ECTR - Event Counter */
#define SYSPM_LO_ECTR(x)                         (((uint32_t)(((uint32_t)(x)) << SYSPM_LO_ECTR_SHIFT)) & SYSPM_LO_ECTR_MASK)
/*! @} */

/* The count of SYSPM_LO */
#define SYSPM_LO_COUNT                           (1U)

/* The count of SYSPM_LO */
#define SYSPM_LO_COUNT2                          (3U)


/*!
 * @}
 */ /* end of group SYSPM_Register_Masks */


/* SYSPM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CMX_PERFMON0 base address */
  #define CMX_PERFMON0_BASE                        (0x5018C000u)
  /** Peripheral CMX_PERFMON0 base address */
  #define CMX_PERFMON0_BASE_NS                     (0x4018C000u)
  /** Peripheral CMX_PERFMON0 base pointer */
  #define CMX_PERFMON0                             ((SYSPM_Type *)CMX_PERFMON0_BASE)
  /** Peripheral CMX_PERFMON0 base pointer */
  #define CMX_PERFMON0_NS                          ((SYSPM_Type *)CMX_PERFMON0_BASE_NS)
  /** Peripheral CMX_PERFMON1 base address */
  #define CMX_PERFMON1_BASE                        (0x5018D000u)
  /** Peripheral CMX_PERFMON1 base address */
  #define CMX_PERFMON1_BASE_NS                     (0x4018D000u)
  /** Peripheral CMX_PERFMON1 base pointer */
  #define CMX_PERFMON1                             ((SYSPM_Type *)CMX_PERFMON1_BASE)
  /** Peripheral CMX_PERFMON1 base pointer */
  #define CMX_PERFMON1_NS                          ((SYSPM_Type *)CMX_PERFMON1_BASE_NS)
  /** Peripheral CMX_PERFMON2 base address */
  #define CMX_PERFMON2_BASE                        (0x5018E000u)
  /** Peripheral CMX_PERFMON2 base address */
  #define CMX_PERFMON2_BASE_NS                     (0x4018E000u)
  /** Peripheral CMX_PERFMON2 base pointer */
  #define CMX_PERFMON2                             ((SYSPM_Type *)CMX_PERFMON2_BASE)
  /** Peripheral CMX_PERFMON2 base pointer */
  #define CMX_PERFMON2_NS                          ((SYSPM_Type *)CMX_PERFMON2_BASE_NS)
  /** Peripheral CMX_PERFMON3 base address */
  #define CMX_PERFMON3_BASE                        (0x5018F000u)
  /** Peripheral CMX_PERFMON3 base address */
  #define CMX_PERFMON3_BASE_NS                     (0x4018F000u)
  /** Peripheral CMX_PERFMON3 base pointer */
  #define CMX_PERFMON3                             ((SYSPM_Type *)CMX_PERFMON3_BASE)
  /** Peripheral CMX_PERFMON3 base pointer */
  #define CMX_PERFMON3_NS                          ((SYSPM_Type *)CMX_PERFMON3_BASE_NS)
  /** Array initializer of SYSPM peripheral base addresses */
  #define SYSPM_BASE_ADDRS                         { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE, CMX_PERFMON2_BASE, CMX_PERFMON3_BASE }
  /** Array initializer of SYSPM peripheral base pointers */
  #define SYSPM_BASE_PTRS                          { CMX_PERFMON0, CMX_PERFMON1, CMX_PERFMON2, CMX_PERFMON3 }
  /** Array initializer of SYSPM peripheral base addresses */
  #define SYSPM_BASE_ADDRS_NS                      { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS, CMX_PERFMON2_BASE_NS, CMX_PERFMON3_BASE_NS }
  /** Array initializer of SYSPM peripheral base pointers */
  #define SYSPM_BASE_PTRS_NS                       { CMX_PERFMON0_NS, CMX_PERFMON1_NS, CMX_PERFMON2_NS, CMX_PERFMON3_NS }
#else
  /** Peripheral CMX_PERFMON0 base address */
  #define CMX_PERFMON0_BASE                        (0x4018C000u)
  /** Peripheral CMX_PERFMON0 base pointer */
  #define CMX_PERFMON0                             ((SYSPM_Type *)CMX_PERFMON0_BASE)
  /** Peripheral CMX_PERFMON1 base address */
  #define CMX_PERFMON1_BASE                        (0x4018D000u)
  /** Peripheral CMX_PERFMON1 base pointer */
  #define CMX_PERFMON1                             ((SYSPM_Type *)CMX_PERFMON1_BASE)
  /** Peripheral CMX_PERFMON2 base address */
  #define CMX_PERFMON2_BASE                        (0x4018E000u)
  /** Peripheral CMX_PERFMON2 base pointer */
  #define CMX_PERFMON2                             ((SYSPM_Type *)CMX_PERFMON2_BASE)
  /** Peripheral CMX_PERFMON3 base address */
  #define CMX_PERFMON3_BASE                        (0x4018F000u)
  /** Peripheral CMX_PERFMON3 base pointer */
  #define CMX_PERFMON3                             ((SYSPM_Type *)CMX_PERFMON3_BASE)
  /** Array initializer of SYSPM peripheral base addresses */
  #define SYSPM_BASE_ADDRS                         { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE, CMX_PERFMON2_BASE, CMX_PERFMON3_BASE }
  /** Array initializer of SYSPM peripheral base pointers */
  #define SYSPM_BASE_PTRS                          { CMX_PERFMON0, CMX_PERFMON1, CMX_PERFMON2, CMX_PERFMON3 }
#endif

/*!
 * @}
 */ /* end of group SYSPM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TRNG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
 * @{
 */

/** TRNG - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCTL;                              /**< Miscellaneous Control Register, offset: 0x0 */
  __IO uint32_t SCMISC;                            /**< Statistical Check Miscellaneous Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t SDCTL;                             /**< Seed Control Register, offset: 0x10 */
       uint8_t RESERVED_1[4];
  union {                                          /* offset: 0x18 */
    __IO uint32_t FRQMIN;                            /**< Frequency Count Minimum Limit Register, offset: 0x18 */
    __I  uint32_t OSC2_FRQCNT;                       /**< Oscillator-2 Frequency Count Register, offset: 0x18 */
  };
  union {                                          /* offset: 0x1C */
    __I  uint32_t FRQCNT;                            /**< Frequency Count Register, offset: 0x1C */
    __IO uint32_t FRQMAX;                            /**< Frequency Count Maximum Limit Register, offset: 0x1C */
  };
  union {                                          /* offset: 0x20 */
    __I  uint32_t SCMC;                              /**< Statistical Check Monobit Count Register, offset: 0x20 */
    __IO uint32_t SCML;                              /**< Statistical Check Monobit Limit Register, offset: 0x20 */
  };
  union {                                          /* offset: 0x24 */
    __I  uint32_t SCR1C;                             /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
    __IO uint32_t SCR1L;                             /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
  };
  union {                                          /* offset: 0x28 */
    __I  uint32_t SCR2C;                             /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
    __IO uint32_t SCR2L;                             /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
  };
  union {                                          /* offset: 0x2C */
    __I  uint32_t SCR3C;                             /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
    __IO uint32_t SCR3L;                             /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
  };
       uint8_t RESERVED_2[12];
  __I  uint32_t STATUS;                            /**< Status Register, offset: 0x3C */
  __I  uint32_t ENT[8];                            /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_3[64];
  __IO uint32_t SEC_CFG;                           /**< Security Configuration Register, offset: 0xA0 */
  __IO uint32_t INT_CTRL;                          /**< Interrupt Control Register, offset: 0xA4 */
  __IO uint32_t INT_MASK;                          /**< Mask Register, offset: 0xA8 */
  __I  uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0xAC */
       uint8_t RESERVED_4[60];
  __IO uint32_t OSC2_CTL;                          /**< TRNG Oscillator 2 Control Register, offset: 0xEC */
  __I  uint32_t VID1;                              /**< Version ID Register (MS), offset: 0xF0 */
  __I  uint32_t VID2;                              /**< Version ID Register (LS), offset: 0xF4 */
} TRNG_Type;

/* ----------------------------------------------------------------------------
   -- TRNG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRNG_Register_Masks TRNG Register Masks
 * @{
 */

/*! @name MCTL - Miscellaneous Control Register */
/*! @{ */

#define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
#define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
/*! OSC_DIV - Oscillator1 Divide
 *  0b00..use ring oscillator with no divide
 *  0b01..use ring oscillator divided-by-2
 *  0b10..use ring oscillator divided-by-4
 *  0b11..use ring oscillator divided-by-8
 */
#define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)

#define TRNG_MCTL_RST_DEF_MASK                   (0x40U)
#define TRNG_MCTL_RST_DEF_SHIFT                  (6U)
/*! RST_DEF - Reset Defaults
 *  0b0..No impact.
 *  0b1..Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state.
 */
#define TRNG_MCTL_RST_DEF(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)

#define TRNG_MCTL_FCT_FAIL_MASK                  (0x100U)
#define TRNG_MCTL_FCT_FAIL_SHIFT                 (8U)
/*! FCT_FAIL - Frequency Count Fail */
#define TRNG_MCTL_FCT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)

#define TRNG_MCTL_FCT_VAL_MASK                   (0x200U)
#define TRNG_MCTL_FCT_VAL_SHIFT                  (9U)
/*! FCT_VAL - Frequency Count Valid
 *  0b0..Frequency Count is not valid
 *  0b1..Frequency Count is valid
 */
#define TRNG_MCTL_FCT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)

#define TRNG_MCTL_ENT_VAL_MASK                   (0x400U)
#define TRNG_MCTL_ENT_VAL_SHIFT                  (10U)
/*! ENT_VAL - Entropy Valid
 *  0b0..Entropy is not valid
 *  0b1..Entropy is valid
 */
#define TRNG_MCTL_ENT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)

#define TRNG_MCTL_ERR_MASK                       (0x1000U)
#define TRNG_MCTL_ERR_SHIFT                      (12U)
/*! ERR - Error Status
 *  0b0..No error
 *  0b1..Error detected
 */
#define TRNG_MCTL_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)

#define TRNG_MCTL_TSTOP_OK_MASK                  (0x2000U)
#define TRNG_MCTL_TSTOP_OK_SHIFT                 (13U)
/*! TSTOP_OK - TRNG is ok to stop
 *  0b0..TRNG is generating entropy and is not ok to stop
 *  0b1..TRNG is not generating entropy and is ok to stop
 */
#define TRNG_MCTL_TSTOP_OK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)

#define TRNG_MCTL_LRUN_CONT_MASK                 (0x4000U)
#define TRNG_MCTL_LRUN_CONT_SHIFT                (14U)
/*! LRUN_CONT - Long run count continues between entropy generations
 *  0b0..The internal test's long run count is restarted for each entropy re-generation.
 *  0b1..The count value (of TRNG's internal long_run test), at the start of an entropy generation will continue
 *       where it left off at the end of the previous entropy generation.
 */
#define TRNG_MCTL_LRUN_CONT(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)

#define TRNG_MCTL_OSC2_FAIL_MASK                 (0x8000U)
#define TRNG_MCTL_OSC2_FAIL_SHIFT                (15U)
/*! OSC2_FAIL - Oscillator 2 Failure
 *  0b0..Oscillator 2 is running.
 *  0b1..Oscillator 2 has failed (see OSC2_CTL[OSC_FAILSAFE_LMT]).
 */
#define TRNG_MCTL_OSC2_FAIL(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC2_FAIL_SHIFT)) & TRNG_MCTL_OSC2_FAIL_MASK)

#define TRNG_MCTL_PRGM_MASK                      (0x10000U)
#define TRNG_MCTL_PRGM_SHIFT                     (16U)
/*! PRGM - Program Mode
 *  0b0..TRNG is in Run Mode
 *  0b1..TRNG is in Program Mode
 */
#define TRNG_MCTL_PRGM(x)                        (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
/*! @} */

/*! @name SCMISC - Statistical Check Miscellaneous Register */
/*! @{ */

#define TRNG_SCMISC_LRUN_MAX_MASK                (0xFFU)
#define TRNG_SCMISC_LRUN_MAX_SHIFT               (0U)
#define TRNG_SCMISC_LRUN_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)

#define TRNG_SCMISC_RTY_CT_MASK                  (0xF0000U)
#define TRNG_SCMISC_RTY_CT_SHIFT                 (16U)
#define TRNG_SCMISC_RTY_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
/*! @} */

/*! @name SDCTL - Seed Control Register */
/*! @{ */

#define TRNG_SDCTL_SAMP_SIZE_MASK                (0xFFFFU)
#define TRNG_SDCTL_SAMP_SIZE_SHIFT               (0U)
#define TRNG_SDCTL_SAMP_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)

#define TRNG_SDCTL_ENT_DLY_MASK                  (0xFFFF0000U)
#define TRNG_SDCTL_ENT_DLY_SHIFT                 (16U)
#define TRNG_SDCTL_ENT_DLY(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
/*! @} */

/*! @name FRQMIN - Frequency Count Minimum Limit Register */
/*! @{ */

#define TRNG_FRQMIN_FRQ_MIN_MASK                 (0x3FFFFFU)
#define TRNG_FRQMIN_FRQ_MIN_SHIFT                (0U)
#define TRNG_FRQMIN_FRQ_MIN(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
/*! @} */

/*! @name OSC2_FRQCNT - Oscillator-2 Frequency Count Register */
/*! @{ */

#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK        (0x3FFFFFU)
#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT       (0U)
#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT(x)          (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT)) & TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK)
/*! @} */

/*! @name FRQCNT - Frequency Count Register */
/*! @{ */

#define TRNG_FRQCNT_FRQ_CT_MASK                  (0x3FFFFFU)
#define TRNG_FRQCNT_FRQ_CT_SHIFT                 (0U)
#define TRNG_FRQCNT_FRQ_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
/*! @} */

/*! @name FRQMAX - Frequency Count Maximum Limit Register */
/*! @{ */

#define TRNG_FRQMAX_FRQ_MAX_MASK                 (0x3FFFFFU)
#define TRNG_FRQMAX_FRQ_MAX_SHIFT                (0U)
#define TRNG_FRQMAX_FRQ_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
/*! @} */

/*! @name SCMC - Statistical Check Monobit Count Register */
/*! @{ */

#define TRNG_SCMC_MONO_CT_MASK                   (0xFFFFU)
#define TRNG_SCMC_MONO_CT_SHIFT                  (0U)
#define TRNG_SCMC_MONO_CT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
/*! @} */

/*! @name SCML - Statistical Check Monobit Limit Register */
/*! @{ */

#define TRNG_SCML_MONO_MAX_MASK                  (0xFFFFU)
#define TRNG_SCML_MONO_MAX_SHIFT                 (0U)
#define TRNG_SCML_MONO_MAX(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)

#define TRNG_SCML_MONO_RNG_MASK                  (0xFFFF0000U)
#define TRNG_SCML_MONO_RNG_SHIFT                 (16U)
#define TRNG_SCML_MONO_RNG(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
/*! @} */

/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
/*! @{ */

#define TRNG_SCR1C_R1_0_CT_MASK                  (0x7FFFU)
#define TRNG_SCR1C_R1_0_CT_SHIFT                 (0U)
/*! R1_0_CT - Runs of Zero, Length 1 Count */
#define TRNG_SCR1C_R1_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)

#define TRNG_SCR1C_R1_1_CT_MASK                  (0x7FFF0000U)
#define TRNG_SCR1C_R1_1_CT_SHIFT                 (16U)
/*! R1_1_CT - Runs of One, Length 1 Count */
#define TRNG_SCR1C_R1_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
/*! @} */

/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
/*! @{ */

#define TRNG_SCR1L_RUN1_MAX_MASK                 (0x7FFFU)
#define TRNG_SCR1L_RUN1_MAX_SHIFT                (0U)
/*! RUN1_MAX - Run Length 1 Maximum Limit */
#define TRNG_SCR1L_RUN1_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)

#define TRNG_SCR1L_RUN1_RNG_MASK                 (0x7FFF0000U)
#define TRNG_SCR1L_RUN1_RNG_SHIFT                (16U)
/*! RUN1_RNG - Run Length 1 Range */
#define TRNG_SCR1L_RUN1_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
/*! @} */

/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
/*! @{ */

#define TRNG_SCR2C_R2_0_CT_MASK                  (0x3FFFU)
#define TRNG_SCR2C_R2_0_CT_SHIFT                 (0U)
#define TRNG_SCR2C_R2_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)

#define TRNG_SCR2C_R2_1_CT_MASK                  (0x3FFF0000U)
#define TRNG_SCR2C_R2_1_CT_SHIFT                 (16U)
#define TRNG_SCR2C_R2_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
/*! @} */

/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
/*! @{ */

#define TRNG_SCR2L_RUN2_MAX_MASK                 (0x3FFFU)
#define TRNG_SCR2L_RUN2_MAX_SHIFT                (0U)
#define TRNG_SCR2L_RUN2_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)

#define TRNG_SCR2L_RUN2_RNG_MASK                 (0x3FFF0000U)
#define TRNG_SCR2L_RUN2_RNG_SHIFT                (16U)
#define TRNG_SCR2L_RUN2_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
/*! @} */

/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
/*! @{ */

#define TRNG_SCR3C_R3_0_CT_MASK                  (0x1FFFU)
#define TRNG_SCR3C_R3_0_CT_SHIFT                 (0U)
#define TRNG_SCR3C_R3_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)

#define TRNG_SCR3C_R3_1_CT_MASK                  (0x1FFF0000U)
#define TRNG_SCR3C_R3_1_CT_SHIFT                 (16U)
#define TRNG_SCR3C_R3_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
/*! @} */

/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
/*! @{ */

#define TRNG_SCR3L_RUN3_MAX_MASK                 (0x1FFFU)
#define TRNG_SCR3L_RUN3_MAX_SHIFT                (0U)
#define TRNG_SCR3L_RUN3_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)

#define TRNG_SCR3L_RUN3_RNG_MASK                 (0x1FFF0000U)
#define TRNG_SCR3L_RUN3_RNG_SHIFT                (16U)
#define TRNG_SCR3L_RUN3_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
/*! @} */

/*! @name STATUS - Status Register */
/*! @{ */

#define TRNG_STATUS_TF1BR0_MASK                  (0x1U)
#define TRNG_STATUS_TF1BR0_SHIFT                 (0U)
/*! TF1BR0
 *  0b0..The 1-Bit Run, Sampling 0s Test has passed
 *  0b1..The 1-Bit Run, Sampling 0s Test has failed
 */
#define TRNG_STATUS_TF1BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)

#define TRNG_STATUS_TF1BR1_MASK                  (0x2U)
#define TRNG_STATUS_TF1BR1_SHIFT                 (1U)
/*! TF1BR1
 *  0b0..The 1-Bit Run, Sampling 1s Test has passed
 *  0b1..The 1-Bit Run, Sampling 1s Test has failed
 */
#define TRNG_STATUS_TF1BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)

#define TRNG_STATUS_TF2BR0_MASK                  (0x4U)
#define TRNG_STATUS_TF2BR0_SHIFT                 (2U)
/*! TF2BR0
 *  0b0..The 2-Bit Run, Sampling 0s Test has passed
 *  0b1..The 2-Bit Run, Sampling 0s Test has failed
 */
#define TRNG_STATUS_TF2BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)

#define TRNG_STATUS_TF2BR1_MASK                  (0x8U)
#define TRNG_STATUS_TF2BR1_SHIFT                 (3U)
/*! TF2BR1
 *  0b0..The 2-Bit Run, Sampling 1s Test has passed
 *  0b1..The 2-Bit Run, Sampling 1s Test has failed
 */
#define TRNG_STATUS_TF2BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)

#define TRNG_STATUS_TF3BR0_MASK                  (0x10U)
#define TRNG_STATUS_TF3BR0_SHIFT                 (4U)
/*! TF3BR0
 *  0b0..The 3-Bit Run, Sampling 0s Test has passed
 *  0b1..The 3-Bit Run, Sampling 0s Test has failed
 */
#define TRNG_STATUS_TF3BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)

#define TRNG_STATUS_TF3BR1_MASK                  (0x20U)
#define TRNG_STATUS_TF3BR1_SHIFT                 (5U)
/*! TF3BR1 - Test Fail
 *  0b0..The 3-Bit Run, Sampling 1s Test has passed
 *  0b1..The 3-Bit Run, Sampling 1s Test has failed
 */
#define TRNG_STATUS_TF3BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)

#define TRNG_STATUS_TFLR_MASK                    (0x2000U)
#define TRNG_STATUS_TFLR_SHIFT                   (13U)
/*! TFLR - Test Fail, Long Run.
 *  0b0..The Long Run Test has passed
 *  0b1..The Long Run Test has failed
 */
#define TRNG_STATUS_TFLR(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)

#define TRNG_STATUS_TFMB_MASK                    (0x8000U)
#define TRNG_STATUS_TFMB_SHIFT                   (15U)
/*! TFMB
 *  0b0..The Mono Bit Test has passed
 *  0b1..The Mono Bit Test has failed
 */
#define TRNG_STATUS_TFMB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)

#define TRNG_STATUS_RETRY_CT_MASK                (0xF0000U)
#define TRNG_STATUS_RETRY_CT_SHIFT               (16U)
#define TRNG_STATUS_RETRY_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
/*! @} */

/*! @name ENT - Entropy Read Register */
/*! @{ */

#define TRNG_ENT_ENT_MASK                        (0xFFFFFFFFU)
#define TRNG_ENT_ENT_SHIFT                       (0U)
#define TRNG_ENT_ENT(x)                          (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
/*! @} */

/* The count of TRNG_ENT */
#define TRNG_ENT_COUNT                           (8U)

/*! @name SEC_CFG - Security Configuration Register */
/*! @{ */

#define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
#define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
/*! NO_PRGM
 *  0b0..TRNG configuration registers can be modified.
 *  0b1..TRNG configuration registers cannot be modified.
 */
#define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
/*! @} */

/*! @name INT_CTRL - Interrupt Control Register */
/*! @{ */

#define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
#define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
/*! HW_ERR
 *  0b0..Clears the INT_STATUS[HW_ERR] bit. Will automatically set after writing.
 *  0b1..Enables the INT_STATUS[HW_ERR] bit to be set, thereby enabling interrupt generation for the HW_ERR condition.
 */
#define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)

#define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
#define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
/*! ENT_VAL
 *  0b0..Clears the INT_STATUS[ENT_VAL] bit. Will automatically set after writing.
 *  0b1..Enables the INT_STATUS[ENT_VAL] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition.
 */
#define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)

#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
/*! FRQ_CT_FAIL
 *  0b0..Clears the INT_STATUS[FRQ_CT_FAIL] bit. Will automatically set after writing.
 *  0b1..Enables the INT_STATUS[FRQ_CT_FAIL] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition.
 */
#define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
/*! @} */

/*! @name INT_MASK - Mask Register */
/*! @{ */

#define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
#define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
/*! HW_ERR
 *  0b0..HW_ERR interrupt is disabled.
 *  0b1..HW_ERR interrupt is enabled.
 */
#define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)

#define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
#define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
/*! ENT_VAL
 *  0b0..ENT_VAL interrupt is disabled.
 *  0b1..ENT_VAL interrupt is enabled.
 */
#define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)

#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
/*! FRQ_CT_FAIL
 *  0b0..FRQ_CT_FAIL interrupt is disabled.
 *  0b1..FRQ_CT_FAIL interrupt is enabled.
 */
#define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
/*! @} */

/*! @name INT_STATUS - Interrupt Status Register */
/*! @{ */

#define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
#define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
/*! HW_ERR
 *  0b0..No error.
 *  0b1..Error detected.
 */
#define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)

#define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
#define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
/*! ENT_VAL
 *  0b0..Busy generating entropy. Any value read from the Entropy registers is invalid.
 *  0b1..Values read from the Entropy registers are valid.
 */
#define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)

#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
/*! FRQ_CT_FAIL
 *  0b0..No hardware nor self test frequency errors.
 *  0b1..The frequency counter has detected a failure.
 */
#define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
/*! @} */

/*! @name OSC2_CTL - TRNG Oscillator 2 Control Register */
/*! @{ */

#define TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK          (0x3U)
#define TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT         (0U)
/*! TRNG_ENT_CTL - TRNG entropy generation control.
 *  0b00..Single oscillator mode, using OSC1 (default)
 *  0b01..Dual oscillator mode
 *  0b10..Single oscillator mode, using OSC2
 *  0b11..Unused, (bit field cannot be written to this value)
 */
#define TRNG_OSC2_CTL_TRNG_ENT_CTL(x)            (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT)) & TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK)

#define TRNG_OSC2_CTL_OSC2_DIV_MASK              (0xCU)
#define TRNG_OSC2_CTL_OSC2_DIV_SHIFT             (2U)
/*! OSC2_DIV - Oscillator 2 Divide.
 *  0b00..Use ring oscillator 2 with no divide
 *  0b01..Use ring oscillator 2 divided-by-2
 *  0b10..Use ring oscillator 2 divided-by-4
 *  0b11..Use ring oscillator 2 divided-by-8
 */
#define TRNG_OSC2_CTL_OSC2_DIV(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_DIV_SHIFT)) & TRNG_OSC2_CTL_OSC2_DIV_MASK)

#define TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK          (0x200U)
#define TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT         (9U)
/*! OSC2_FCT_VAL - TRNG Oscillator 2 Frequency Count Valid
 *  0b0..Frequency count is invalid.
 *  0b1..If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT.
 */
#define TRNG_OSC2_CTL_OSC2_FCT_VAL(x)            (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT)) & TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK)

#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK      (0x3000U)
#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT     (12U)
/*! OSC_FAILSAFE_LMT - Oscillator fail safe limit.
 *  0b00..The limit N is 4096 (2^12) system clocks.
 *  0b01..The limit N is 65536 (2^16) system clocks. (default)
 *  0b10..N is 2^20 system clocks.
 *  0b11..N is 2^22 system clocks (full range of the counter being used).
 */
#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT(x)        (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK)

#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK     (0x4000U)
#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT    (14U)
/*! OSC_FAILSAFE_TEST - Oscillator fail safe test.
 *  0b0..No impact.
 *  0b1..Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b).
 */
#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST(x)       (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK)
/*! @} */

/*! @name VID1 - Version ID Register (MS) */
/*! @{ */

#define TRNG_VID1_MIN_REV_MASK                   (0xFFU)
#define TRNG_VID1_MIN_REV_SHIFT                  (0U)
/*! MIN_REV
 *  0b00001011..Minor revision number for TRNG.
 */
#define TRNG_VID1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)

#define TRNG_VID1_MAJ_REV_MASK                   (0xFF00U)
#define TRNG_VID1_MAJ_REV_SHIFT                  (8U)
/*! MAJ_REV
 *  0b00010100..Major revision number for TRNG.
 */
#define TRNG_VID1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)

#define TRNG_VID1_IP_ID_MASK                     (0xFFFF0000U)
#define TRNG_VID1_IP_ID_SHIFT                    (16U)
/*! IP_ID
 *  0b0000000000110000..ID for TRNG.
 */
#define TRNG_VID1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
/*! @} */

/*! @name VID2 - Version ID Register (LS) */
/*! @{ */

#define TRNG_VID2_CONFIG_OPT_MASK                (0xFFU)
#define TRNG_VID2_CONFIG_OPT_SHIFT               (0U)
/*! CONFIG_OPT
 *  0b00000000..TRNG_CONFIG_OPT for TRNG.
 */
#define TRNG_VID2_CONFIG_OPT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)

#define TRNG_VID2_ECO_REV_MASK                   (0xFF00U)
#define TRNG_VID2_ECO_REV_SHIFT                  (8U)
/*! ECO_REV
 *  0b00000000..TRNG_ECO_REV for TRNG.
 */
#define TRNG_VID2_ECO_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)

#define TRNG_VID2_INTG_OPT_MASK                  (0xFF0000U)
#define TRNG_VID2_INTG_OPT_SHIFT                 (16U)
/*! INTG_OPT
 *  0b00001010..INTG_OPT for TRNG.
 */
#define TRNG_VID2_INTG_OPT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)

#define TRNG_VID2_ERA_MASK                       (0xFF000000U)
#define TRNG_VID2_ERA_SHIFT                      (24U)
/*! ERA
 *  0b00001011..ERA of the TRNG.
 */
#define TRNG_VID2_ERA(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group TRNG_Register_Masks */


/* TRNG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral TRNG base address */
  #define TRNG_BASE                                (0x50187000u)
  /** Peripheral TRNG base address */
  #define TRNG_BASE_NS                             (0x40187000u)
  /** Peripheral TRNG base pointer */
  #define TRNG                                     ((TRNG_Type *)TRNG_BASE)
  /** Peripheral TRNG base pointer */
  #define TRNG_NS                                  ((TRNG_Type *)TRNG_BASE_NS)
  /** Array initializer of TRNG peripheral base addresses */
  #define TRNG_BASE_ADDRS                          { TRNG_BASE }
  /** Array initializer of TRNG peripheral base pointers */
  #define TRNG_BASE_PTRS                           { TRNG }
  /** Array initializer of TRNG peripheral base addresses */
  #define TRNG_BASE_ADDRS_NS                       { TRNG_BASE_NS }
  /** Array initializer of TRNG peripheral base pointers */
  #define TRNG_BASE_PTRS_NS                        { TRNG_NS }
#else
  /** Peripheral TRNG base address */
  #define TRNG_BASE                                (0x40187000u)
  /** Peripheral TRNG base pointer */
  #define TRNG                                     ((TRNG_Type *)TRNG_BASE)
  /** Array initializer of TRNG peripheral base addresses */
  #define TRNG_BASE_ADDRS                          { TRNG_BASE }
  /** Array initializer of TRNG peripheral base pointers */
  #define TRNG_BASE_PTRS                           { TRNG }
#endif
/* Backward compatibility */
#define TRNG0                                    TRNG


/*!
 * @}
 */ /* end of group TRNG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
 * @{
 */

/** USB - Register Layout Typedef */
typedef struct {
  __I  uint32_t ID;                                /**< Identification, offset: 0x0 */
  __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
  __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
  __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
  __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
  __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
       uint8_t RESERVED_0[104];
  __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer 0 Load, offset: 0x80 */
  __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer 0 Controller, offset: 0x84 */
  __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer 1 Load, offset: 0x88 */
  __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer 1 Controller, offset: 0x8C */
  __IO uint32_t SBUSCFG;                           /**< System Bus Configuration, offset: 0x90 */
       uint8_t RESERVED_1[108];
  __I  uint8_t CAPLENGTH;                          /**< Capability Registers Length, offset: 0x100 */
       uint8_t RESERVED_2[1];
  __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
  __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
  __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
       uint8_t RESERVED_3[20];
  __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
       uint8_t RESERVED_4[2];
  __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
       uint8_t RESERVED_5[24];
  __IO uint32_t USBCMD;                            /**< USB Command, offset: 0x140 */
  __IO uint32_t USBSTS;                            /**< USB Status, offset: 0x144 */
  __IO uint32_t USBINTR;                           /**< Interrupt Enable, offset: 0x148 */
  __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
       uint8_t RESERVED_6[4];
  union {                                          /* offset: 0x154 */
    __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
    __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
  };
  union {                                          /* offset: 0x158 */
    __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynchronous Address, offset: 0x158 */
    __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
  };
       uint8_t RESERVED_7[4];
  __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
  __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
       uint8_t RESERVED_8[16];
  __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
  __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
  __I  uint32_t CONFIGFLAG;                        /**< Configure Flag, offset: 0x180 */
  __IO uint32_t PORTSC1;                           /**< Port Status and Control, offset: 0x184 */
       uint8_t RESERVED_9[28];
  __IO uint32_t OTGSC;                             /**< On-The-Go Status and Control, offset: 0x1A4, available only on: USB0 (missing on USB1) */
  __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
  __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
  __IO uint32_t ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
  __IO uint32_t ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
  __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
  __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
  __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control 0, offset: 0x1C0 */
  __IO uint32_t ENDPTCTRL[7];                      /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
} USB_Type;

/* ----------------------------------------------------------------------------
   -- USB Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USB_Register_Masks USB Register Masks
 * @{
 */

/*! @name ID - Identification */
/*! @{ */

#define USB_ID_ID_MASK                           (0x3FU)
#define USB_ID_ID_SHIFT                          (0U)
/*! ID - Configuration Number */
#define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)

#define USB_ID_NID_MASK                          (0x3F00U)
#define USB_ID_NID_SHIFT                         (8U)
/*! NID - Complement Version */
#define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)

#define USB_ID_REVISION_MASK                     (0xFF0000U)
#define USB_ID_REVISION_SHIFT                    (16U)
/*! REVISION - Revision Number */
#define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
/*! @} */

/*! @name HWGENERAL - Hardware General */
/*! @{ */

#define USB_HWGENERAL_PHYW_MASK                  (0x30U)
#define USB_HWGENERAL_PHYW_SHIFT                 (4U)
/*! PHYW - PHY Width
 *  0b00..8-bit wide data bus (software nonprogrammable)
 *  0b01..16-bit wide data bus (software nonprogrammable)
 *  0b10..Reset to 8-bit wide data bus (software programmable)
 *  0b11..Reset to 16-bit wide data bus (software programmable)
 */
#define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)

#define USB_HWGENERAL_PHYM_MASK                  (0x3C0U)
#define USB_HWGENERAL_PHYM_SHIFT                 (6U)
/*! PHYM - Transceiver Type
 *  0b0000..UTMI/UMTI+
 *  0b0001..ULPI DDR
 *  0b0010..ULPI
 *  0b0011..Serial only
 *  0b0100..Software programmable: reset to UTMI/UTMI+
 *  0b0101..Software programmable: reset to ULPI DDR
 *  0b0110..Software programmable: reset to ULPI
 *  0b0111..Software programmable: reset to Serial
 *  0b1000..IC-USB
 *  0b1001..Software programmable: reset to IC-USB
 *  0b1010..HSIC
 *  0b1011..Software programmable: reset to HSIC
 *  0b1100-0b1111..Reserved
 */
#define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)

#define USB_HWGENERAL_SM_MASK                    (0xC00U)
#define USB_HWGENERAL_SM_SHIFT                   (10U)
/*! SM - Serial Interface Mode Capability
 *  0b00..No serial engine; always use parallel signaling
 *  0b01..Serial engine present; always use serial signaling for FS and LS
 *  0b10..Software programmable; reset to use parallel signaling for FS and LS
 *  0b11..Software programmable; reset to use serial signaling for FS and LS
 */
#define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)

#define USB_HWGENERAL_LPM_MASK                   (0x1000U)
#define USB_HWGENERAL_LPM_SHIFT                  (12U)
/*! LPM - Link Power Management Capability
 *  0b0..Not supported
 *  0b1..Supported
 */
#define USB_HWGENERAL_LPM(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_LPM_SHIFT)) & USB_HWGENERAL_LPM_MASK)
/*! @} */

/*! @name HWHOST - Host Hardware Parameters */
/*! @{ */

#define USB_HWHOST_HC_MASK                       (0x1U)
#define USB_HWHOST_HC_SHIFT                      (0U)
/*! HC - Host Capable
 *  0b1..Supported
 *  0b0..Not supported
 */
#define USB_HWHOST_HC(x)                         (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)

#define USB_HWHOST_NPORT_MASK                    (0xEU)
#define USB_HWHOST_NPORT_SHIFT                   (1U)
/*! NPORT - Number of Ports */
#define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
/*! @} */

/*! @name HWDEVICE - Device Hardware Parameters */
/*! @{ */

#define USB_HWDEVICE_DC_MASK                     (0x1U)
#define USB_HWDEVICE_DC_SHIFT                    (0U)
/*! DC - Device Capable
 *  0b1..Supported
 *  0b0..Not supported
 */
#define USB_HWDEVICE_DC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)

#define USB_HWDEVICE_DEVEP_MASK                  (0x3EU)
#define USB_HWDEVICE_DEVEP_SHIFT                 (1U)
/*! DEVEP - Device Endpoint Number */
#define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
/*! @} */

/*! @name HWTXBUF - TX Buffer Hardware Parameters */
/*! @{ */

#define USB_HWTXBUF_TXBURST_MASK                 (0xFFU)
#define USB_HWTXBUF_TXBURST_SHIFT                (0U)
/*! TXBURST - TX Burst */
#define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)

#define USB_HWTXBUF_TXCHANADD_MASK               (0xFF0000U)
#define USB_HWTXBUF_TXCHANADD_SHIFT              (16U)
/*! TXCHANADD - TX Channel Add */
#define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
/*! @} */

/*! @name HWRXBUF - RX Buffer Hardware Parameters */
/*! @{ */

#define USB_HWRXBUF_RXBURST_MASK                 (0xFFU)
#define USB_HWRXBUF_RXBURST_SHIFT                (0U)
/*! RXBURST - RX Burst */
#define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)

#define USB_HWRXBUF_RXADD_MASK                   (0xFF00U)
#define USB_HWRXBUF_RXADD_SHIFT                  (8U)
/*! RXADD - RX Add */
#define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
/*! @} */

/*! @name GPTIMER0LD - General Purpose Timer 0 Load */
/*! @{ */

#define USB_GPTIMER0LD_GPTLD_MASK                (0xFFFFFFU)
#define USB_GPTIMER0LD_GPTLD_SHIFT               (0U)
/*! GPTLD - General Purpose Timer Load Value */
#define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
/*! @} */

/*! @name GPTIMER0CTRL - General Purpose Timer 0 Controller */
/*! @{ */

#define USB_GPTIMER0CTRL_GPTCNT_MASK             (0xFFFFFFU)
#define USB_GPTIMER0CTRL_GPTCNT_SHIFT            (0U)
/*! GPTCNT - General Purpose Timer Counter */
#define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)

#define USB_GPTIMER0CTRL_GPTMODE_MASK            (0x1000000U)
#define USB_GPTIMER0CTRL_GPTMODE_SHIFT           (24U)
/*! GPTMODE - General Purpose Timer Mode
 *  0b0..One Shot mode
 *  0b1..Repeat mode
 */
#define USB_GPTIMER0CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)

#define USB_GPTIMER0CTRL_GPTRST_MASK             (0x40000000U)
#define USB_GPTIMER0CTRL_GPTRST_SHIFT            (30U)
/*! GPTRST - General Purpose Timer Reset
 *  0b0..No action
 *  0b1..Load counter value
 */
#define USB_GPTIMER0CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)

#define USB_GPTIMER0CTRL_GPTRUN_MASK             (0x80000000U)
#define USB_GPTIMER0CTRL_GPTRUN_SHIFT            (31U)
/*! GPTRUN - General Purpose Timer Run
 *  0b0..Stopped counting
 *  0b1..Running
 */
#define USB_GPTIMER0CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
/*! @} */

/*! @name GPTIMER1LD - General Purpose Timer 1 Load */
/*! @{ */

#define USB_GPTIMER1LD_GPTLD_MASK                (0xFFFFFFU)
#define USB_GPTIMER1LD_GPTLD_SHIFT               (0U)
/*! GPTLD - General Purpose Timer Load Value */
#define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
/*! @} */

/*! @name GPTIMER1CTRL - General Purpose Timer 1 Controller */
/*! @{ */

#define USB_GPTIMER1CTRL_GPTCNT_MASK             (0xFFFFFFU)
#define USB_GPTIMER1CTRL_GPTCNT_SHIFT            (0U)
/*! GPTCNT - General Purpose Timer Counter */
#define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)

#define USB_GPTIMER1CTRL_GPTMODE_MASK            (0x1000000U)
#define USB_GPTIMER1CTRL_GPTMODE_SHIFT           (24U)
/*! GPTMODE - General Purpose Timer Mode
 *  0b0..One Shot mode
 *  0b1..Repeat mode
 */
#define USB_GPTIMER1CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)

#define USB_GPTIMER1CTRL_GPTRST_MASK             (0x40000000U)
#define USB_GPTIMER1CTRL_GPTRST_SHIFT            (30U)
/*! GPTRST - General Purpose Timer Reset
 *  0b0..No action
 *  0b1..Load counter value
 */
#define USB_GPTIMER1CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)

#define USB_GPTIMER1CTRL_GPTRUN_MASK             (0x80000000U)
#define USB_GPTIMER1CTRL_GPTRUN_SHIFT            (31U)
/*! GPTRUN - General Purpose Timer Run
 *  0b0..Stopped counting
 *  0b1..Running
 */
#define USB_GPTIMER1CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
/*! @} */

/*! @name SBUSCFG - System Bus Configuration */
/*! @{ */

#define USB_SBUSCFG_AHBBRST_MASK                 (0x7U)
#define USB_SBUSCFG_AHBBRST_SHIFT                (0U)
/*! AHBBRST - AHB Manager Interface Burst Configuration
 *  0b000..Incremental burst of unspecified length only
 *  0b001..INCR4 burst, then single transfer
 *  0b010..INCR8 burst, INCR4 burst, then single transfer
 *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
 *  0b100..Reserved, do not use
 *  0b101..INCR4 burst, then incremental burst of unspecified length
 *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
 *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
 */
#define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
/*! @} */

/*! @name CAPLENGTH - Capability Registers Length */
/*! @{ */

#define USB_CAPLENGTH_CAPLENGTH_MASK             (0xFFU)
#define USB_CAPLENGTH_CAPLENGTH_SHIFT            (0U)
/*! CAPLENGTH - Capability Length */
#define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
/*! @} */

/*! @name HCIVERSION - Host Controller Interface Version */
/*! @{ */

#define USB_HCIVERSION_HCIVERSION_MASK           (0xFFFFU)
#define USB_HCIVERSION_HCIVERSION_SHIFT          (0U)
/*! HCIVERSION - Host Controller Interface Version Number */
#define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
/*! @} */

/*! @name HCSPARAMS - Host Controller Structural Parameters */
/*! @{ */

#define USB_HCSPARAMS_N_PORTS_MASK               (0xFU)
#define USB_HCSPARAMS_N_PORTS_SHIFT              (0U)
/*! N_PORTS - Number of Ports */
#define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)

#define USB_HCSPARAMS_PPC_MASK                   (0x10U)
#define USB_HCSPARAMS_PPC_SHIFT                  (4U)
/*! PPC - Port Power Control
 *  0b0..No port power switches
 *  0b1..Port power switches exist
 */
#define USB_HCSPARAMS_PPC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)

#define USB_HCSPARAMS_N_PCC_MASK                 (0xF00U)
#define USB_HCSPARAMS_N_PCC_SHIFT                (8U)
/*! N_PCC - Number of Ports per Companion Controller */
#define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)

#define USB_HCSPARAMS_N_CC_MASK                  (0xF000U)
#define USB_HCSPARAMS_N_CC_SHIFT                 (12U)
/*! N_CC - Number of Companion Controller (N_CC)
 *  0b0000..No internal companion controller exists
 *  0b0001..Internal companion controllers exist
 */
#define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)

#define USB_HCSPARAMS_PI_MASK                    (0x10000U)
#define USB_HCSPARAMS_PI_SHIFT                   (16U)
/*! PI - Port Indicators (P_INDICATOR) */
#define USB_HCSPARAMS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)

#define USB_HCSPARAMS_N_PTT_MASK                 (0xF00000U)
#define USB_HCSPARAMS_N_PTT_SHIFT                (20U)
/*! N_PTT - Number of Ports per Transaction Translator (N_PTT) */
#define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)

#define USB_HCSPARAMS_N_TT_MASK                  (0xF000000U)
#define USB_HCSPARAMS_N_TT_SHIFT                 (24U)
/*! N_TT - Number of Transaction Translators (N_TT) */
#define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
/*! @} */

/*! @name HCCPARAMS - Host Controller Capability Parameters */
/*! @{ */

#define USB_HCCPARAMS_ADC_MASK                   (0x1U)
#define USB_HCCPARAMS_ADC_SHIFT                  (0U)
/*! ADC - Addressing Capability */
#define USB_HCCPARAMS_ADC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)

#define USB_HCCPARAMS_PFL_MASK                   (0x2U)
#define USB_HCCPARAMS_PFL_SHIFT                  (1U)
/*! PFL - Programmable Frame List Flag */
#define USB_HCCPARAMS_PFL(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)

#define USB_HCCPARAMS_ASP_MASK                   (0x4U)
#define USB_HCCPARAMS_ASP_SHIFT                  (2U)
/*! ASP - Asynchronous Schedule Park Capability */
#define USB_HCCPARAMS_ASP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)

#define USB_HCCPARAMS_IST_MASK                   (0xF0U)
#define USB_HCCPARAMS_IST_SHIFT                  (4U)
/*! IST - Isochronous Scheduling Threshold */
#define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)

#define USB_HCCPARAMS_EECP_MASK                  (0xFF00U)
#define USB_HCCPARAMS_EECP_SHIFT                 (8U)
/*! EECP - EHCI Extended Capabilities Pointer */
#define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
/*! @} */

/*! @name DCIVERSION - Device Controller Interface Version */
/*! @{ */

#define USB_DCIVERSION_DCIVERSION_MASK           (0xFFFFU)
#define USB_DCIVERSION_DCIVERSION_SHIFT          (0U)
/*! DCIVERSION - Device Controller Interface Version Number */
#define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
/*! @} */

/*! @name DCCPARAMS - Device Controller Capability Parameters */
/*! @{ */

#define USB_DCCPARAMS_DEN_MASK                   (0x1FU)
#define USB_DCCPARAMS_DEN_SHIFT                  (0U)
/*! DEN - Device Endpoint Number
 *  0b00000..Not device capable
 *  0b00001..Device capable
 */
#define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)

#define USB_DCCPARAMS_DC_MASK                    (0x80U)
#define USB_DCCPARAMS_DC_SHIFT                   (7U)
/*! DC - Device Capable
 *  0b0..Not device capable
 *  0b1..Device capable
 */
#define USB_DCCPARAMS_DC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)

#define USB_DCCPARAMS_HC_MASK                    (0x100U)
#define USB_DCCPARAMS_HC_SHIFT                   (8U)
/*! HC - Host Capable
 *  0b0..Not host capable
 *  0b1..Host capable
 */
#define USB_DCCPARAMS_HC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
/*! @} */

/*! @name USBCMD - USB Command */
/*! @{ */

#define USB_USBCMD_RS_MASK                       (0x1U)
#define USB_USBCMD_RS_SHIFT                      (0U)
/*! RS - Run/Stop
 *  0b0..Stopped executing
 *  0b1..Running
 */
#define USB_USBCMD_RS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)

#define USB_USBCMD_RST_MASK                      (0x2U)
#define USB_USBCMD_RST_SHIFT                     (1U)
/*! RST - Controller Reset */
#define USB_USBCMD_RST(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)

#define USB_USBCMD_FS_1_MASK                     (0xCU)
#define USB_USBCMD_FS_1_SHIFT                    (2U)
/*! FS_1 - Frame List Size 1 */
#define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)

#define USB_USBCMD_PSE_MASK                      (0x10U)
#define USB_USBCMD_PSE_SHIFT                     (4U)
/*! PSE - Periodic Schedule Enable
 *  0b0..Do not process the periodic schedule
 *  0b1..Process the periodic schedule
 */
#define USB_USBCMD_PSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)

#define USB_USBCMD_ASE_MASK                      (0x20U)
#define USB_USBCMD_ASE_SHIFT                     (5U)
/*! ASE - Asynchronous Schedule Enable
 *  0b0..Do not process the asynchronous schedule
 *  0b1..Access the asynchronous schedule
 */
#define USB_USBCMD_ASE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)

#define USB_USBCMD_IAA_MASK                      (0x40U)
#define USB_USBCMD_IAA_SHIFT                     (6U)
/*! IAA - Interrupt on Async Advance Doorbell */
#define USB_USBCMD_IAA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)

#define USB_USBCMD_ASP_MASK                      (0x300U)
#define USB_USBCMD_ASP_SHIFT                     (8U)
/*! ASP - Asynchronous Schedule Park Mode Count */
#define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)

#define USB_USBCMD_ASPE_MASK                     (0x800U)
#define USB_USBCMD_ASPE_SHIFT                    (11U)
/*! ASPE - Asynchronous Schedule Park Mode Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBCMD_ASPE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)

#define USB_USBCMD_SUTW_MASK                     (0x2000U)
#define USB_USBCMD_SUTW_SHIFT                    (13U)
/*! SUTW - Setup Trip Wire (Device mode only) */
#define USB_USBCMD_SUTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)

#define USB_USBCMD_ATDTW_MASK                    (0x4000U)
#define USB_USBCMD_ATDTW_SHIFT                   (14U)
/*! ATDTW - Add dTD Trip Wire (Device mode only) */
#define USB_USBCMD_ATDTW(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)

#define USB_USBCMD_FS_2_MASK                     (0x8000U)
#define USB_USBCMD_FS_2_SHIFT                    (15U)
/*! FS_2 - Frame List Size 2 (Host mode only) */
#define USB_USBCMD_FS_2(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)

#define USB_USBCMD_ITC_MASK                      (0xFF0000U)
#define USB_USBCMD_ITC_SHIFT                     (16U)
/*! ITC - Interrupt Threshold Control
 *  0b00000000..Immediate (no threshold)
 *  0b00000001..1 microframe
 *  0b00000010..2 microframes
 *  0b00000100..4 microframes
 *  0b00001000..8 microframes
 *  0b00010000..16 microframes
 *  0b00100000..32 microframes
 *  0b01000000..64 microframes
 */
#define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
/*! @} */

/*! @name USBSTS - USB Status */
/*! @{ */

#define USB_USBSTS_UI_MASK                       (0x1U)
#define USB_USBSTS_UI_SHIFT                      (0U)
/*! UI - USB Interrupt (USBINT) Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_UI(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)

#define USB_USBSTS_UEI_MASK                      (0x2U)
#define USB_USBSTS_UEI_SHIFT                     (1U)
/*! UEI - USB Error Interrupt (USBERRINT) Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_UEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)

#define USB_USBSTS_PCI_MASK                      (0x4U)
#define USB_USBSTS_PCI_SHIFT                     (2U)
/*! PCI - Port Change Detect Flag
 *  0b0..Port change not detected
 *  0b1..Port change detected
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_PCI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)

#define USB_USBSTS_FRI_MASK                      (0x8U)
#define USB_USBSTS_FRI_SHIFT                     (3U)
/*! FRI - Frame List Rollover Flag
 *  0b0..Frame list index did not roll over
 *  0b1..Frame list index rolled over
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_FRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)

#define USB_USBSTS_SEI_MASK                      (0x10U)
#define USB_USBSTS_SEI_SHIFT                     (4U)
/*! SEI - System Error Flag
 *  0b0..Error response did not occur
 *  0b1..Error response occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_SEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)

#define USB_USBSTS_AAI_MASK                      (0x20U)
#define USB_USBSTS_AAI_SHIFT                     (5U)
/*! AAI - Interrupt on Asynchronous Advance Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)

#define USB_USBSTS_URI_MASK                      (0x40U)
#define USB_USBSTS_URI_SHIFT                     (6U)
/*! URI - USB Reset Received
 *  0b0..USB reset not received
 *  0b1..USB reset received
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_URI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)

#define USB_USBSTS_SRI_MASK                      (0x80U)
#define USB_USBSTS_SRI_SHIFT                     (7U)
/*! SRI - SOF Received Flag
 *  0b0..SOF not received
 *  0b1..SOF received
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_SRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)

#define USB_USBSTS_SLI_MASK                      (0x100U)
#define USB_USBSTS_SLI_SHIFT                     (8U)
/*! SLI - Device Controller Suspend Flag
 *  0b0..Did not enter Suspended state
 *  0b1..Entered Suspended state
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_SLI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)

#define USB_USBSTS_ULPII_MASK                    (0x400U)
#define USB_USBSTS_ULPII_SHIFT                   (10U)
/*! ULPII - ULPI Interrupt Flag
 *  0b0..Event completion did not occur
 *  0b1..Event completion occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_ULPII(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)

#define USB_USBSTS_HCH_MASK                      (0x1000U)
#define USB_USBSTS_HCH_SHIFT                     (12U)
/*! HCH - HC Halted */
#define USB_USBSTS_HCH(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)

#define USB_USBSTS_RCL_MASK                      (0x2000U)
#define USB_USBSTS_RCL_SHIFT                     (13U)
/*! RCL - Reclamation
 *  0b0..Does not detect
 *  0b1..Detects
 */
#define USB_USBSTS_RCL(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)

#define USB_USBSTS_PS_MASK                       (0x4000U)
#define USB_USBSTS_PS_SHIFT                      (14U)
/*! PS - Periodic Schedule Status
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define USB_USBSTS_PS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)

#define USB_USBSTS_AS_MASK                       (0x8000U)
#define USB_USBSTS_AS_SHIFT                      (15U)
/*! AS - Asynchronous Schedule Status
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define USB_USBSTS_AS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)

#define USB_USBSTS_NAKI_MASK                     (0x10000U)
#define USB_USBSTS_NAKI_SHIFT                    (16U)
/*! NAKI - NAK Interrupt */
#define USB_USBSTS_NAKI(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)

#define USB_USBSTS_UAI_MASK                      (0x40000U)
#define USB_USBSTS_UAI_SHIFT                     (18U)
/*! UAI - USB Host Asynchronous Interrupt Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_UAI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UAI_SHIFT)) & USB_USBSTS_UAI_MASK)

#define USB_USBSTS_UPI_MASK                      (0x80000U)
#define USB_USBSTS_UPI_SHIFT                     (19U)
/*! UPI - USB Host Periodic Interrupt Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_UPI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UPI_SHIFT)) & USB_USBSTS_UPI_MASK)

#define USB_USBSTS_TI0_MASK                      (0x1000000U)
#define USB_USBSTS_TI0_SHIFT                     (24U)
/*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_TI0(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)

#define USB_USBSTS_TI1_MASK                      (0x2000000U)
#define USB_USBSTS_TI1_SHIFT                     (25U)
/*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_TI1(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)

#define USB_USBSTS_LPM_L1_EXITI_MASK             (0x10000000U)
#define USB_USBSTS_LPM_L1_EXITI_SHIFT            (28U)
/*! LPM_L1_EXITI - L1 Exit Interrupt Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_LPM_L1_EXITI(x)               (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_LPM_L1_EXITI_SHIFT)) & USB_USBSTS_LPM_L1_EXITI_MASK)

#define USB_USBSTS_LPM_L1_ENTRYI_MASK            (0x20000000U)
#define USB_USBSTS_LPM_L1_ENTRYI_SHIFT           (29U)
/*! LPM_L1_ENTRYI - L1 Entry Interrupt Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_LPM_L1_ENTRYI(x)              (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_LPM_L1_ENTRYI_SHIFT)) & USB_USBSTS_LPM_L1_ENTRYI_MASK)

#define USB_USBSTS_LPM_DEV_RCVDI_MASK            (0x40000000U)
#define USB_USBSTS_LPM_DEV_RCVDI_SHIFT           (30U)
/*! LPM_DEV_RCVDI - Device Received Extension Token Interrupt Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_LPM_DEV_RCVDI(x)              (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_LPM_DEV_RCVDI_SHIFT)) & USB_USBSTS_LPM_DEV_RCVDI_MASK)

#define USB_USBSTS_LPM_HST_COMPI_MASK            (0x80000000U)
#define USB_USBSTS_LPM_HST_COMPI_SHIFT           (31U)
/*! LPM_HST_COMPI - Host Completes the LPM Transaction Interrupt Flag
 *  0b0..Interrupt did not occur
 *  0b1..Interrupt occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_USBSTS_LPM_HST_COMPI(x)              (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_LPM_HST_COMPI_SHIFT)) & USB_USBSTS_LPM_HST_COMPI_MASK)
/*! @} */

/*! @name USBINTR - Interrupt Enable */
/*! @{ */

#define USB_USBINTR_UE_MASK                      (0x1U)
#define USB_USBINTR_UE_SHIFT                     (0U)
/*! UE - USB Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_UE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)

#define USB_USBINTR_UEE_MASK                     (0x2U)
#define USB_USBINTR_UEE_SHIFT                    (1U)
/*! UEE - USB Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_UEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)

#define USB_USBINTR_PCE_MASK                     (0x4U)
#define USB_USBINTR_PCE_SHIFT                    (2U)
/*! PCE - Port Change Detect Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_PCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)

#define USB_USBINTR_FRE_MASK                     (0x8U)
#define USB_USBINTR_FRE_SHIFT                    (3U)
/*! FRE - Frame List Rollover Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_FRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)

#define USB_USBINTR_SEE_MASK                     (0x10U)
#define USB_USBINTR_SEE_SHIFT                    (4U)
/*! SEE - System Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_SEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)

#define USB_USBINTR_AAE_MASK                     (0x20U)
#define USB_USBINTR_AAE_SHIFT                    (5U)
/*! AAE - Asynchronous Advance Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_AAE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)

#define USB_USBINTR_URE_MASK                     (0x40U)
#define USB_USBINTR_URE_SHIFT                    (6U)
/*! URE - USB Reset Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_URE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)

#define USB_USBINTR_SRE_MASK                     (0x80U)
#define USB_USBINTR_SRE_SHIFT                    (7U)
/*! SRE - SOF Received Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)

#define USB_USBINTR_SLE_MASK                     (0x100U)
#define USB_USBINTR_SLE_SHIFT                    (8U)
/*! SLE - Sleep Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_SLE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)

#define USB_USBINTR_NAKE_MASK                    (0x10000U)
#define USB_USBINTR_NAKE_SHIFT                   (16U)
/*! NAKE - NAK Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_NAKE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)

#define USB_USBINTR_UAIE_MASK                    (0x40000U)
#define USB_USBINTR_UAIE_SHIFT                   (18U)
/*! UAIE - USB Host Asynchronous Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_UAIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)

#define USB_USBINTR_UPIE_MASK                    (0x80000U)
#define USB_USBINTR_UPIE_SHIFT                   (19U)
/*! UPIE - USB Host Periodic Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_UPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)

#define USB_USBINTR_TIE0_MASK                    (0x1000000U)
#define USB_USBINTR_TIE0_SHIFT                   (24U)
/*! TIE0 - General Purpose Timer 0 Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_TIE0(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)

#define USB_USBINTR_TIE1_MASK                    (0x2000000U)
#define USB_USBINTR_TIE1_SHIFT                   (25U)
/*! TIE1 - General Purpose Timer 1 Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_TIE1(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)

#define USB_USBINTR_LPM_L1_EXITIE_MASK           (0x10000000U)
#define USB_USBINTR_LPM_L1_EXITIE_SHIFT          (28U)
/*! LPM_L1_EXITIE - L1 Exit Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_LPM_L1_EXITIE(x)             (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_LPM_L1_EXITIE_SHIFT)) & USB_USBINTR_LPM_L1_EXITIE_MASK)

#define USB_USBINTR_LPM_L1_ENTRYIE_MASK          (0x20000000U)
#define USB_USBINTR_LPM_L1_ENTRYIE_SHIFT         (29U)
/*! LPM_L1_ENTRYIE - L1 Entry Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_LPM_L1_ENTRYIE(x)            (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_LPM_L1_ENTRYIE_SHIFT)) & USB_USBINTR_LPM_L1_ENTRYIE_MASK)

#define USB_USBINTR_LPM_DEV_RCVDIE_MASK          (0x40000000U)
#define USB_USBINTR_LPM_DEV_RCVDIE_SHIFT         (30U)
/*! LPM_DEV_RCVDIE - Device Received Extension Token Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_LPM_DEV_RCVDIE(x)            (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_LPM_DEV_RCVDIE_SHIFT)) & USB_USBINTR_LPM_DEV_RCVDIE_MASK)

#define USB_USBINTR_LPM_HST_COMPIE_MASK          (0x80000000U)
#define USB_USBINTR_LPM_HST_COMPIE_SHIFT         (31U)
/*! LPM_HST_COMPIE - Host Completed LPM Transaction Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBINTR_LPM_HST_COMPIE(x)            (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_LPM_HST_COMPIE_SHIFT)) & USB_USBINTR_LPM_HST_COMPIE_MASK)
/*! @} */

/*! @name FRINDEX - USB Frame Index */
/*! @{ */

#define USB_FRINDEX_FRINDEX_MASK                 (0x3FFFU)
#define USB_FRINDEX_FRINDEX_SHIFT                (0U)
/*! FRINDEX - Frame Index
 *  0b00000000000000..(1024) 12
 *  0b00000000000001..(512) 11
 *  0b00000000000010..(256) 10
 *  0b00000000000011..(128) 9
 *  0b00000000000100..(64) 8
 *  0b00000000000101..(32) 7
 *  0b00000000000110..(16) 6
 *  0b00000000000111..(8) 5
 */
#define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
/*! @} */

/*! @name DEVICEADDR - Device Address */
/*! @{ */

#define USB_DEVICEADDR_USBADRA_MASK              (0x1000000U)
#define USB_DEVICEADDR_USBADRA_SHIFT             (24U)
/*! USBADRA - Device Address Advance */
#define USB_DEVICEADDR_USBADRA(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)

#define USB_DEVICEADDR_USBADR_MASK               (0xFE000000U)
#define USB_DEVICEADDR_USBADR_SHIFT              (25U)
/*! USBADR - Device Address */
#define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
/*! @} */

/*! @name PERIODICLISTBASE - Frame List Base Address */
/*! @{ */

#define USB_PERIODICLISTBASE_BASEADR_MASK        (0xFFFFF000U)
#define USB_PERIODICLISTBASE_BASEADR_SHIFT       (12U)
/*! BASEADR - Base Address (Low) */
#define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
/*! @} */

/*! @name ASYNCLISTADDR - Next Asynchronous Address */
/*! @{ */

#define USB_ASYNCLISTADDR_ASYBASE_MASK           (0xFFFFFFE0U)
#define USB_ASYNCLISTADDR_ASYBASE_SHIFT          (5U)
/*! ASYBASE - Link Pointer Low (LPL) */
#define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
/*! @} */

/*! @name ENDPTLISTADDR - Endpoint List Address */
/*! @{ */

#define USB_ENDPTLISTADDR_EPBASE_MASK            (0xFFFFF800U)
#define USB_ENDPTLISTADDR_EPBASE_SHIFT           (11U)
/*! EPBASE - Endpoint List Pointer (Low) */
#define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
/*! @} */

/*! @name BURSTSIZE - Programmable Burst Size */
/*! @{ */

#define USB_BURSTSIZE_RXPBURST_MASK              (0xFFU)
#define USB_BURSTSIZE_RXPBURST_SHIFT             (0U)
/*! RXPBURST - Programmable RX Burst Size */
#define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)

#define USB_BURSTSIZE_TXPBURST_MASK              (0xFF00U)
#define USB_BURSTSIZE_TXPBURST_SHIFT             (8U)
/*! TXPBURST - Programmable TX Burst Size */
#define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
/*! @} */

/*! @name TXFILLTUNING - TX FIFO Fill Tuning */
/*! @{ */

#define USB_TXFILLTUNING_TXSCHOH_MASK            (0x7FU)
#define USB_TXFILLTUNING_TXSCHOH_SHIFT           (0U)
/*! TXSCHOH - Scheduler Overhead */
#define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)

#define USB_TXFILLTUNING_TXSCHHEALTH_MASK        (0x1F00U)
#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       (8U)
/*! TXSCHHEALTH - Scheduler Health Counter */
#define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)

#define USB_TXFILLTUNING_TXFIFOTHRES_MASK        (0x3F0000U)
#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       (16U)
/*! TXFIFOTHRES - FIFO Burst Threshold */
#define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
/*! @} */

/*! @name ENDPTNAK - Endpoint NAK */
/*! @{ */

#define USB_ENDPTNAK_EPRN_MASK                   (0xFFU)
#define USB_ENDPTNAK_EPRN_SHIFT                  (0U)
/*! EPRN - RX Endpoint NAK Flag
 *  0b00000000..No NACK
 *  0b00000001..NACK
 *  0b00000000..No effect
 *  0b00000001..Clear the flag
 */
#define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)

#define USB_ENDPTNAK_EPTN_MASK                   (0xFF0000U)
#define USB_ENDPTNAK_EPTN_SHIFT                  (16U)
/*! EPTN - TX Endpoint NAK Flag
 *  0b00000000..No NACK
 *  0b00000001..NACK
 *  0b00000000..No effect
 *  0b00000001..Clear the flag
 */
#define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
/*! @} */

/*! @name ENDPTNAKEN - Endpoint NAK Enable */
/*! @{ */

#define USB_ENDPTNAKEN_EPRNE_MASK                (0xFFU)
#define USB_ENDPTNAKEN_EPRNE_SHIFT               (0U)
/*! EPRNE - RX Endpoint NAK Enable */
#define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)

#define USB_ENDPTNAKEN_EPTNE_MASK                (0xFF0000U)
#define USB_ENDPTNAKEN_EPTNE_SHIFT               (16U)
/*! EPTNE - TX Endpoint NAK Enable */
#define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
/*! @} */

/*! @name CONFIGFLAG - Configure Flag */
/*! @{ */

#define USB_CONFIGFLAG_CF_MASK                   (0x1U)
#define USB_CONFIGFLAG_CF_SHIFT                  (0U)
/*! CF - Configure Flag
 *  0b0..Port routing to classic host controller
 *  0b1..Port routing to this host controller
 */
#define USB_CONFIGFLAG_CF(x)                     (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
/*! @} */

/*! @name PORTSC1 - Port Status and Control */
/*! @{ */

#define USB_PORTSC1_CCS_MASK                     (0x1U)
#define USB_PORTSC1_CCS_SHIFT                    (0U)
/*! CCS - Current Connect Status
 *  0b0..No device present or attached
 *  0b1..Device present and attached
 */
#define USB_PORTSC1_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)

#define USB_PORTSC1_CSC_MASK                     (0x2U)
#define USB_PORTSC1_CSC_SHIFT                    (1U)
/*! CSC - Connect Status Change Flag
 *  0b0..No change occurred
 *  0b1..Change occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_PORTSC1_CSC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)

#define USB_PORTSC1_PE_MASK                      (0x4U)
#define USB_PORTSC1_PE_SHIFT                     (2U)
/*! PE - Port Enable and Disable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_PORTSC1_PE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)

#define USB_PORTSC1_PEC_MASK                     (0x8U)
#define USB_PORTSC1_PEC_SHIFT                    (3U)
/*! PEC - Port Enable and Disable Change Flag
 *  0b0..No change occurred
 *  0b1..Change occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_PORTSC1_PEC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)

#define USB_PORTSC1_OCA_MASK                     (0x10U)
#define USB_PORTSC1_OCA_SHIFT                    (4U)
/*! OCA - Overcurrent Active
 *  0b0..No overcurrent condition exists
 *  0b1..Overcurrent condition exists
 */
#define USB_PORTSC1_OCA(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)

#define USB_PORTSC1_OCC_MASK                     (0x20U)
#define USB_PORTSC1_OCC_SHIFT                    (5U)
/*! OCC - Overcurrent Change Flag
 *  0b0..No change occurred
 *  0b1..Change occurred
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USB_PORTSC1_OCC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)

#define USB_PORTSC1_FPR_MASK                     (0x40U)
#define USB_PORTSC1_FPR_SHIFT                    (6U)
/*! FPR - Force Port Resume
 *  0b0..No resume (K-state) detected or driven on port
 *  0b1..Resume detected or driven on port
 */
#define USB_PORTSC1_FPR(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)

#define USB_PORTSC1_SUSP_MASK                    (0x80U)
#define USB_PORTSC1_SUSP_SHIFT                   (7U)
/*! SUSP - Suspend
 *  0b0..Port not in Suspended state
 *  0b1..Port in Suspended state
 */
#define USB_PORTSC1_SUSP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)

#define USB_PORTSC1_PR_MASK                      (0x100U)
#define USB_PORTSC1_PR_SHIFT                     (8U)
/*! PR - Port Reset
 *  0b0..Port not in reset
 *  0b1..Port in reset
 */
#define USB_PORTSC1_PR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)

#define USB_PORTSC1_HSP_MASK                     (0x200U)
#define USB_PORTSC1_HSP_SHIFT                    (9U)
/*! HSP - High-Speed Port
 *  0b0..Not in HS mode
 *  0b1..In HS mode
 */
#define USB_PORTSC1_HSP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)

#define USB_PORTSC1_LS_MASK                      (0xC00U)
#define USB_PORTSC1_LS_SHIFT                     (10U)
/*! LS - Line Status
 *  0b00..SE0
 *  0b10..J-state
 *  0b01..K-state
 *  0b11..Undefined
 */
#define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)

#define USB_PORTSC1_PP_MASK                      (0x1000U)
#define USB_PORTSC1_PP_SHIFT                     (12U)
/*! PP - Port Power (PP)
 *  0b0..Off
 *  0b1..On
 */
#define USB_PORTSC1_PP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)

#define USB_PORTSC1_PO_MASK                      (0x2000U)
#define USB_PORTSC1_PO_SHIFT                     (13U)
/*! PO - Port Owner */
#define USB_PORTSC1_PO(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)

#define USB_PORTSC1_PIC_MASK                     (0xC000U)
#define USB_PORTSC1_PIC_SHIFT                    (14U)
/*! PIC - Port Indicator Control
 *  0b00..Port indicators are off
 *  0b01..Amber
 *  0b10..Green
 *  0b11..Undefined
 */
#define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)

#define USB_PORTSC1_PTC_MASK                     (0xF0000U)
#define USB_PORTSC1_PTC_SHIFT                    (16U)
/*! PTC - Port Test Control
 *  0b0000..TEST_MODE_DISABLE
 *  0b0001..J_STATE
 *  0b0010..K_STATE
 *  0b0011..SE0 (host) or NAK (device)
 *  0b0100..Packet
 *  0b0101..FORCE_ENABLE_HS
 *  0b0110..FORCE_ENABLE_FS
 *  0b0111..FORCE_ENABLE_LS
 *  0b1000-0b1111..Reserved
 */
#define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)

#define USB_PORTSC1_WKCN_MASK                    (0x100000U)
#define USB_PORTSC1_WKCN_SHIFT                   (20U)
/*! WKCN - Wake on Connect Enable (WKCNNT_E)
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_PORTSC1_WKCN(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)

#define USB_PORTSC1_WKDC_MASK                    (0x200000U)
#define USB_PORTSC1_WKDC_SHIFT                   (21U)
/*! WKDC - Wake on Disconnect Enable (WKDSCNNT_E)
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_PORTSC1_WKDC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)

#define USB_PORTSC1_WKOC_MASK                    (0x400000U)
#define USB_PORTSC1_WKOC_SHIFT                   (22U)
/*! WKOC - Wake on Overcurrent Enable (WKOC) */
#define USB_PORTSC1_WKOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)

#define USB_PORTSC1_PHCD_MASK                    (0x800000U)
#define USB_PORTSC1_PHCD_SHIFT                   (23U)
/*! PHCD - PHY Low-Power Suspend - Clock Disable (PLPSCD)
 *  0b0..Enable
 *  0b1..Disable
 */
#define USB_PORTSC1_PHCD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)

#define USB_PORTSC1_PFSC_MASK                    (0x1000000U)
#define USB_PORTSC1_PFSC_SHIFT                   (24U)
/*! PFSC - Port Force Full Speed Connect
 *  0b0..Normal operation
 *  0b1..Forced to full speed
 */
#define USB_PORTSC1_PFSC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)

#define USB_PORTSC1_PTS_2_MASK                   (0x2000000U)
#define USB_PORTSC1_PTS_2_SHIFT                  (25U)
/*! PTS_2 - Parallel Transceiver Select 2 */
#define USB_PORTSC1_PTS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)

#define USB_PORTSC1_PSPD_MASK                    (0xC000000U)
#define USB_PORTSC1_PSPD_SHIFT                   (26U)
/*! PSPD - Port Speed
 *  0b00..FS
 *  0b01..LS
 *  0b10..HS
 *  0b11..Undefined
 */
#define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)

#define USB_PORTSC1_PTW_MASK                     (0x10000000U)
#define USB_PORTSC1_PTW_SHIFT                    (28U)
/*! PTW - Parallel Transceiver Width
 *  0b0..8-bit UTMI interface (60 MHz)
 *  0b1..16-bit UTMI interface (30 MHz)
 */
#define USB_PORTSC1_PTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)

#define USB_PORTSC1_STS_MASK                     (0x20000000U)
#define USB_PORTSC1_STS_SHIFT                    (29U)
/*! STS - Serial Transceiver Select
 *  0b0..Parallel interface signals
 *  0b1..Serial interface engine
 */
#define USB_PORTSC1_STS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)

#define USB_PORTSC1_PTS_1_MASK                   (0xC0000000U)
#define USB_PORTSC1_PTS_1_SHIFT                  (30U)
/*! PTS_1 - Parallel Transceiver Select 1 */
#define USB_PORTSC1_PTS_1(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
/*! @} */

/*! @name OTGSC - On-The-Go Status and Control */
/*! @{ */

#define USB_OTGSC_VD_MASK                        (0x1U)
#define USB_OTGSC_VD_SHIFT                       (0U)
/*! VD - VBUS Discharge */
#define USB_OTGSC_VD(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)

#define USB_OTGSC_VC_MASK                        (0x2U)
#define USB_OTGSC_VC_SHIFT                       (1U)
/*! VC - VBUS Charge */
#define USB_OTGSC_VC(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)

#define USB_OTGSC_HAAR_MASK                      (0x4U)
#define USB_OTGSC_HAAR_SHIFT                     (2U)
/*! HAAR - Hardware Assist Auto Reset
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_OTGSC_HAAR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_HAAR_SHIFT)) & USB_OTGSC_HAAR_MASK)

#define USB_OTGSC_OT_MASK                        (0x8U)
#define USB_OTGSC_OT_SHIFT                       (3U)
/*! OT - OTG Termination */
#define USB_OTGSC_OT(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)

#define USB_OTGSC_DP_MASK                        (0x10U)
#define USB_OTGSC_DP_SHIFT                       (4U)
/*! DP - Data Pulsing */
#define USB_OTGSC_DP(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)

#define USB_OTGSC_IDPU_MASK                      (0x20U)
#define USB_OTGSC_IDPU_SHIFT                     (5U)
/*! IDPU - ID Pullup */
#define USB_OTGSC_IDPU(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)

#define USB_OTGSC_HADP_MASK                      (0x40U)
#define USB_OTGSC_HADP_SHIFT                     (6U)
/*! HADP - Hardware Assist Data Pulse
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_OTGSC_HADP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_HADP_SHIFT)) & USB_OTGSC_HADP_MASK)

#define USB_OTGSC_HABA_MASK                      (0x80U)
#define USB_OTGSC_HABA_SHIFT                     (7U)
/*! HABA - Hardware Assist B-Disconnect to A-connect
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_OTGSC_HABA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_HABA_SHIFT)) & USB_OTGSC_HABA_MASK)

#define USB_OTGSC_ID_MASK                        (0x100U)
#define USB_OTGSC_ID_SHIFT                       (8U)
/*! ID - USB ID
 *  0b0..A device
 *  0b1..B device
 */
#define USB_OTGSC_ID(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)

#define USB_OTGSC_AVV_MASK                       (0x200U)
#define USB_OTGSC_AVV_SHIFT                      (9U)
/*! AVV - A VBUS Valid */
#define USB_OTGSC_AVV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)

#define USB_OTGSC_ASV_MASK                       (0x400U)
#define USB_OTGSC_ASV_SHIFT                      (10U)
/*! ASV - A Session Valid */
#define USB_OTGSC_ASV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)

#define USB_OTGSC_BSV_MASK                       (0x800U)
#define USB_OTGSC_BSV_SHIFT                      (11U)
/*! BSV - B Session Valid */
#define USB_OTGSC_BSV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)

#define USB_OTGSC_BSE_MASK                       (0x1000U)
#define USB_OTGSC_BSE_SHIFT                      (12U)
/*! BSE - B Session End */
#define USB_OTGSC_BSE(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)

#define USB_OTGSC_TOG_1MS_MASK                   (0x2000U)
#define USB_OTGSC_TOG_1MS_SHIFT                  (13U)
/*! TOG_1MS - 1 Millisecond Timer Toggle */
#define USB_OTGSC_TOG_1MS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)

#define USB_OTGSC_DPS_MASK                       (0x4000U)
#define USB_OTGSC_DPS_SHIFT                      (14U)
/*! DPS - Data Bus Pulsing Status */
#define USB_OTGSC_DPS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)

#define USB_OTGSC_IDIS_MASK                      (0x10000U)
#define USB_OTGSC_IDIS_SHIFT                     (16U)
/*! IDIS - USB ID Interrupt Status */
#define USB_OTGSC_IDIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)

#define USB_OTGSC_AVVIS_MASK                     (0x20000U)
#define USB_OTGSC_AVVIS_SHIFT                    (17U)
/*! AVVIS - A VBUS Valid Interrupt Status */
#define USB_OTGSC_AVVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)

#define USB_OTGSC_ASVIS_MASK                     (0x40000U)
#define USB_OTGSC_ASVIS_SHIFT                    (18U)
/*! ASVIS - A Session Valid Interrupt Status */
#define USB_OTGSC_ASVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)

#define USB_OTGSC_BSVIS_MASK                     (0x80000U)
#define USB_OTGSC_BSVIS_SHIFT                    (19U)
/*! BSVIS - B Session Valid Interrupt Status */
#define USB_OTGSC_BSVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)

#define USB_OTGSC_BSEIS_MASK                     (0x100000U)
#define USB_OTGSC_BSEIS_SHIFT                    (20U)
/*! BSEIS - B Session End Interrupt Status */
#define USB_OTGSC_BSEIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)

#define USB_OTGSC_STATUS_1MS_MASK                (0x200000U)
#define USB_OTGSC_STATUS_1MS_SHIFT               (21U)
/*! STATUS_1MS - 1 Millisecond Timer Interrupt Status */
#define USB_OTGSC_STATUS_1MS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)

#define USB_OTGSC_DPIS_MASK                      (0x400000U)
#define USB_OTGSC_DPIS_SHIFT                     (22U)
/*! DPIS - Data Pulse Interrupt Status */
#define USB_OTGSC_DPIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)

#define USB_OTGSC_IDIE_MASK                      (0x1000000U)
#define USB_OTGSC_IDIE_SHIFT                     (24U)
/*! IDIE - USB ID Interrupt Enable */
#define USB_OTGSC_IDIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)

#define USB_OTGSC_AVVIE_MASK                     (0x2000000U)
#define USB_OTGSC_AVVIE_SHIFT                    (25U)
/*! AVVIE - A VBUS Valid Interrupt Enable */
#define USB_OTGSC_AVVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)

#define USB_OTGSC_ASVIE_MASK                     (0x4000000U)
#define USB_OTGSC_ASVIE_SHIFT                    (26U)
/*! ASVIE - A Session Valid Interrupt Enable */
#define USB_OTGSC_ASVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)

#define USB_OTGSC_BSVIE_MASK                     (0x8000000U)
#define USB_OTGSC_BSVIE_SHIFT                    (27U)
/*! BSVIE - B Session Valid Interrupt Enable */
#define USB_OTGSC_BSVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)

#define USB_OTGSC_BSEIE_MASK                     (0x10000000U)
#define USB_OTGSC_BSEIE_SHIFT                    (28U)
/*! BSEIE - B Session End Interrupt Enable */
#define USB_OTGSC_BSEIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)

#define USB_OTGSC_EN_1MS_MASK                    (0x20000000U)
#define USB_OTGSC_EN_1MS_SHIFT                   (29U)
/*! EN_1MS - 1 Millisecond Timer Interrupt Enable */
#define USB_OTGSC_EN_1MS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)

#define USB_OTGSC_DPIE_MASK                      (0x40000000U)
#define USB_OTGSC_DPIE_SHIFT                     (30U)
/*! DPIE - Data Pulse Interrupt Enable */
#define USB_OTGSC_DPIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
/*! @} */

/*! @name USBMODE - USB Device Mode */
/*! @{ */

#define USB_USBMODE_CM_MASK                      (0x3U)
#define USB_USBMODE_CM_SHIFT                     (0U)
/*! CM - Controller Mode
 *  0b00..Idle (default for host and device combination)
 *  0b01..Reserved
 *  0b10..Device controller (default for device-only controller)
 *  0b11..Host controller (default for host-only controller)
 */
#define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)

#define USB_USBMODE_ES_MASK                      (0x4U)
#define USB_USBMODE_ES_SHIFT                     (2U)
/*! ES - Endian Select
 *  0b0..Little endian (default)
 *  0b1..Big endian
 */
#define USB_USBMODE_ES(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)

#define USB_USBMODE_SLOM_MASK                    (0x8U)
#define USB_USBMODE_SLOM_SHIFT                   (3U)
/*! SLOM - Setup Lockout Mode
 *  0b0..On (default)
 *  0b1..Off
 */
#define USB_USBMODE_SLOM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)

#define USB_USBMODE_SDIS_MASK                    (0x10U)
#define USB_USBMODE_SDIS_SHIFT                   (4U)
/*! SDIS - Stream Disable Mode
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_USBMODE_SDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
/*! @} */

/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
/*! @{ */

#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   (0xFFFFU)
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  (0U)
/*! ENDPTSETUPSTAT - Endpoint Setup Status Flag
 *  0b0000000000000000..Not received
 *  0b0000000000000001..Received
 *  0b0000000000000000..No effect
 *  0b0000000000000001..Clear the flag
 */
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
/*! @} */

/*! @name ENDPTPRIME - Endpoint Prime */
/*! @{ */

#define USB_ENDPTPRIME_PERB_MASK                 (0xFFU)
#define USB_ENDPTPRIME_PERB_SHIFT                (0U)
/*! PERB - Prime Endpoint Receive Buffer */
#define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)

#define USB_ENDPTPRIME_PETB_MASK                 (0xFF0000U)
#define USB_ENDPTPRIME_PETB_SHIFT                (16U)
/*! PETB - Prime Endpoint Transmit Buffer */
#define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
/*! @} */

/*! @name ENDPTFLUSH - Endpoint Flush */
/*! @{ */

#define USB_ENDPTFLUSH_FERB_MASK                 (0xFFU)
#define USB_ENDPTFLUSH_FERB_SHIFT                (0U)
/*! FERB - Flush Endpoint Receive Buffer */
#define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)

#define USB_ENDPTFLUSH_FETB_MASK                 (0xFF0000U)
#define USB_ENDPTFLUSH_FETB_SHIFT                (16U)
/*! FETB - Flush Endpoint Transmit Buffer */
#define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
/*! @} */

/*! @name ENDPTSTAT - Endpoint Status */
/*! @{ */

#define USB_ENDPTSTAT_ERBR_MASK                  (0xFFU)
#define USB_ENDPTSTAT_ERBR_SHIFT                 (0U)
/*! ERBR - Endpoint Receive Buffer Ready */
#define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)

#define USB_ENDPTSTAT_ETBR_MASK                  (0xFF0000U)
#define USB_ENDPTSTAT_ETBR_SHIFT                 (16U)
/*! ETBR - Endpoint Transmit Buffer Ready */
#define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
/*! @} */

/*! @name ENDPTCOMPLETE - Endpoint Complete */
/*! @{ */

#define USB_ENDPTCOMPLETE_ERCE_MASK              (0xFFU)
#define USB_ENDPTCOMPLETE_ERCE_SHIFT             (0U)
/*! ERCE - Endpoint Receive Complete Event
 *  0b00000000..Transmit incomplete
 *  0b00000001..Transmit complete
 */
#define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)

#define USB_ENDPTCOMPLETE_ETCE_MASK              (0xFF0000U)
#define USB_ENDPTCOMPLETE_ETCE_SHIFT             (16U)
/*! ETCE - Endpoint Transmit Complete Event
 *  0b00000000..Transmit incomplete
 *  0b00000001..Transmit complete
 */
#define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
/*! @} */

/*! @name ENDPTCTRL0 - Endpoint Control 0 */
/*! @{ */

#define USB_ENDPTCTRL0_RXS_MASK                  (0x1U)
#define USB_ENDPTCTRL0_RXS_SHIFT                 (0U)
/*! RXS - RX Endpoint Stall
 *  0b0..Endpoint OK
 *  0b1..Endpoint stalled
 */
#define USB_ENDPTCTRL0_RXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)

#define USB_ENDPTCTRL0_RXT_MASK                  (0xCU)
#define USB_ENDPTCTRL0_RXT_SHIFT                 (2U)
/*! RXT - RX Endpoint Type */
#define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)

#define USB_ENDPTCTRL0_RXE_MASK                  (0x80U)
#define USB_ENDPTCTRL0_RXE_SHIFT                 (7U)
/*! RXE - RX Endpoint Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_ENDPTCTRL0_RXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)

#define USB_ENDPTCTRL0_TXS_MASK                  (0x10000U)
#define USB_ENDPTCTRL0_TXS_SHIFT                 (16U)
/*! TXS - TX Endpoint Stall
 *  0b0..Endpoint OK
 *  0b1..Endpoint stalled
 */
#define USB_ENDPTCTRL0_TXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)

#define USB_ENDPTCTRL0_TXT_MASK                  (0xC0000U)
#define USB_ENDPTCTRL0_TXT_SHIFT                 (18U)
/*! TXT - TX Endpoint Type */
#define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)

#define USB_ENDPTCTRL0_TXE_MASK                  (0x800000U)
#define USB_ENDPTCTRL0_TXE_SHIFT                 (23U)
/*! TXE - TX Endpoint Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_ENDPTCTRL0_TXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
/*! @} */

/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
/*! @{ */

#define USB_ENDPTCTRL_RXS_MASK                   (0x1U)
#define USB_ENDPTCTRL_RXS_SHIFT                  (0U)
/*! RXS - RX Endpoint Stall
 *  0b0..Endpoint OK
 *  0b1..Endpoint stalled
 */
#define USB_ENDPTCTRL_RXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)

#define USB_ENDPTCTRL_RXD_MASK                   (0x2U)
#define USB_ENDPTCTRL_RXD_SHIFT                  (1U)
/*! RXD - RX Endpoint Data Sink */
#define USB_ENDPTCTRL_RXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)

#define USB_ENDPTCTRL_RXT_MASK                   (0xCU)
#define USB_ENDPTCTRL_RXT_SHIFT                  (2U)
/*! RXT - RX Endpoint Type
 *  0b00..Control
 *  0b01..Isochronous
 *  0b10..Bulk
 *  0b11..Interrupt
 */
#define USB_ENDPTCTRL_RXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)

#define USB_ENDPTCTRL_RXI_MASK                   (0x20U)
#define USB_ENDPTCTRL_RXI_SHIFT                  (5U)
/*! RXI - RX Data Toggle Inhibit
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_ENDPTCTRL_RXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)

#define USB_ENDPTCTRL_RXR_MASK                   (0x40U)
#define USB_ENDPTCTRL_RXR_SHIFT                  (6U)
/*! RXR - RX Data Toggle Reset
 *  0b0..Does not reset
 *  0b1..Resets
 */
#define USB_ENDPTCTRL_RXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)

#define USB_ENDPTCTRL_RXE_MASK                   (0x80U)
#define USB_ENDPTCTRL_RXE_SHIFT                  (7U)
/*! RXE - RX Endpoint Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_ENDPTCTRL_RXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)

#define USB_ENDPTCTRL_TXS_MASK                   (0x10000U)
#define USB_ENDPTCTRL_TXS_SHIFT                  (16U)
/*! TXS - TX Endpoint Stall
 *  0b0..Endpoint OK
 *  0b1..Endpoint stalled
 */
#define USB_ENDPTCTRL_TXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)

#define USB_ENDPTCTRL_TXD_MASK                   (0x20000U)
#define USB_ENDPTCTRL_TXD_SHIFT                  (17U)
/*! TXD - TX Endpoint Data Source */
#define USB_ENDPTCTRL_TXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)

#define USB_ENDPTCTRL_TXT_MASK                   (0xC0000U)
#define USB_ENDPTCTRL_TXT_SHIFT                  (18U)
/*! TXT - TX Endpoint Type
 *  0b00..Control
 *  0b01..Isochronous
 *  0b10..Bulk
 *  0b11..Interrupt
 */
#define USB_ENDPTCTRL_TXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)

#define USB_ENDPTCTRL_TXI_MASK                   (0x200000U)
#define USB_ENDPTCTRL_TXI_SHIFT                  (21U)
/*! TXI - TX Data Toggle Inhibit
 *  0b0..Allow
 *  0b1..Inhibit
 */
#define USB_ENDPTCTRL_TXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)

#define USB_ENDPTCTRL_TXR_MASK                   (0x400000U)
#define USB_ENDPTCTRL_TXR_SHIFT                  (22U)
/*! TXR - TX Data Toggle Reset
 *  0b0..Does not reset
 *  0b1..Resets
 */
#define USB_ENDPTCTRL_TXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)

#define USB_ENDPTCTRL_TXE_MASK                   (0x800000U)
#define USB_ENDPTCTRL_TXE_SHIFT                  (23U)
/*! TXE - TX Endpoint Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define USB_ENDPTCTRL_TXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
/*! @} */

/* The count of USB_ENDPTCTRL */
#define USB_ENDPTCTRL_COUNT                      (7U)


/*!
 * @}
 */ /* end of group USB_Register_Masks */


/* USB - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral USB0 base address */
  #define USB0_BASE                                (0x50418000u)
  /** Peripheral USB0 base address */
  #define USB0_BASE_NS                             (0x40418000u)
  /** Peripheral USB0 base pointer */
  #define USB0                                     ((USB_Type *)USB0_BASE)
  /** Peripheral USB0 base pointer */
  #define USB0_NS                                  ((USB_Type *)USB0_BASE_NS)
  /** Peripheral USB1 base address */
  #define USB1_BASE                                (0x50419000u)
  /** Peripheral USB1 base address */
  #define USB1_BASE_NS                             (0x40419000u)
  /** Peripheral USB1 base pointer */
  #define USB1                                     ((USB_Type *)USB1_BASE)
  /** Peripheral USB1 base pointer */
  #define USB1_NS                                  ((USB_Type *)USB1_BASE_NS)
  /** Array initializer of USB peripheral base addresses */
  #define USB_BASE_ADDRS                           { USB0_BASE, USB1_BASE }
  /** Array initializer of USB peripheral base pointers */
  #define USB_BASE_PTRS                            { USB0, USB1 }
  /** Array initializer of USB peripheral base addresses */
  #define USB_BASE_ADDRS_NS                        { USB0_BASE_NS, USB1_BASE_NS }
  /** Array initializer of USB peripheral base pointers */
  #define USB_BASE_PTRS_NS                         { USB0_NS, USB1_NS }
#else
  /** Peripheral USB0 base address */
  #define USB0_BASE                                (0x40418000u)
  /** Peripheral USB0 base pointer */
  #define USB0                                     ((USB_Type *)USB0_BASE)
  /** Peripheral USB1 base address */
  #define USB1_BASE                                (0x40419000u)
  /** Peripheral USB1 base pointer */
  #define USB1                                     ((USB_Type *)USB1_BASE)
  /** Array initializer of USB peripheral base addresses */
  #define USB_BASE_ADDRS                           { USB0_BASE, USB1_BASE }
  /** Array initializer of USB peripheral base pointers */
  #define USB_BASE_PTRS                            { USB0, USB1 }
#endif
/* Backward compatibility */
#define GPTIMER0CTL                              GPTIMER0CTRL
#define GPTIMER1CTL                              GPTIMER1CTRL
#define USB_SBUSCFG                              SBUSCFG
#define EPLISTADDR                               ENDPTLISTADDR
#define EPSETUPSR                                ENDPTSETUPSTAT
#define EPPRIME                                  ENDPTPRIME
#define EPFLUSH                                  ENDPTFLUSH
#define EPSR                                     ENDPTSTAT
#define EPCOMPLETE                               ENDPTCOMPLETE
#define EPCR                                     ENDPTCTRL
#define EPCR0                                    ENDPTCTRL0
#define USBHS_ID_ID_MASK                         USB_ID_ID_MASK
#define USBHS_ID_ID_SHIFT                        USB_ID_ID_SHIFT
#define USBHS_ID_ID(x)                           USB_ID_ID(x)
#define USBHS_ID_NID_MASK                        USB_ID_NID_MASK
#define USBHS_ID_NID_SHIFT                       USB_ID_NID_SHIFT
#define USBHS_ID_NID(x)                          USB_ID_NID(x)
#define USBHS_ID_REVISION_MASK                   USB_ID_REVISION_MASK
#define USBHS_ID_REVISION_SHIFT                  USB_ID_REVISION_SHIFT
#define USBHS_ID_REVISION(x)                     USB_ID_REVISION(x)
#define USBHS_HWGENERAL_PHYW_MASK                USB_HWGENERAL_PHYW_MASK
#define USBHS_HWGENERAL_PHYW_SHIFT               USB_HWGENERAL_PHYW_SHIFT
#define USBHS_HWGENERAL_PHYW(x)                  USB_HWGENERAL_PHYW(x)
#define USBHS_HWGENERAL_PHYM_MASK                USB_HWGENERAL_PHYM_MASK
#define USBHS_HWGENERAL_PHYM_SHIFT               USB_HWGENERAL_PHYM_SHIFT
#define USBHS_HWGENERAL_PHYM(x)                  USB_HWGENERAL_PHYM(x)
#define USBHS_HWGENERAL_SM_MASK                  USB_HWGENERAL_SM_MASK
#define USBHS_HWGENERAL_SM_SHIFT                 USB_HWGENERAL_SM_SHIFT
#define USBHS_HWGENERAL_SM(x)                    USB_HWGENERAL_SM(x)
#define USBHS_HWHOST_HC_MASK                     USB_HWHOST_HC_MASK
#define USBHS_HWHOST_HC_SHIFT                    USB_HWHOST_HC_SHIFT
#define USBHS_HWHOST_HC(x)                       USB_HWHOST_HC(x)
#define USBHS_HWHOST_NPORT_MASK                  USB_HWHOST_NPORT_MASK
#define USBHS_HWHOST_NPORT_SHIFT                 USB_HWHOST_NPORT_SHIFT
#define USBHS_HWHOST_NPORT(x)                    USB_HWHOST_NPORT(x)
#define USBHS_HWDEVICE_DC_MASK                   USB_HWDEVICE_DC_MASK
#define USBHS_HWDEVICE_DC_SHIFT                  USB_HWDEVICE_DC_SHIFT
#define USBHS_HWDEVICE_DC(x)                     USB_HWDEVICE_DC(x)
#define USBHS_HWDEVICE_DEVEP_MASK                USB_HWDEVICE_DEVEP_MASK
#define USBHS_HWDEVICE_DEVEP_SHIFT               USB_HWDEVICE_DEVEP_SHIFT
#define USBHS_HWDEVICE_DEVEP(x)                  USB_HWDEVICE_DEVEP(x)
#define USBHS_HWTXBUF_TXBURST_MASK               USB_HWTXBUF_TXBURST_MASK
#define USBHS_HWTXBUF_TXBURST_SHIFT              USB_HWTXBUF_TXBURST_SHIFT
#define USBHS_HWTXBUF_TXBURST(x)                 USB_HWTXBUF_TXBURST(x)
#define USBHS_HWTXBUF_TXCHANADD_MASK             USB_HWTXBUF_TXCHANADD_MASK
#define USBHS_HWTXBUF_TXCHANADD_SHIFT            USB_HWTXBUF_TXCHANADD_SHIFT
#define USBHS_HWTXBUF_TXCHANADD(x)               USB_HWTXBUF_TXCHANADD(x)
#define USBHS_HWRXBUF_RXBURST_MASK               USB_HWRXBUF_RXBURST_MASK
#define USBHS_HWRXBUF_RXBURST_SHIFT              USB_HWRXBUF_RXBURST_SHIFT
#define USBHS_HWRXBUF_RXBURST(x)                 USB_HWRXBUF_RXBURST(x)
#define USBHS_HWRXBUF_RXADD_MASK                 USB_HWRXBUF_RXADD_MASK
#define USBHS_HWRXBUF_RXADD_SHIFT                USB_HWRXBUF_RXADD_SHIFT
#define USBHS_HWRXBUF_RXADD(x)                   USB_HWRXBUF_RXADD(x)
#define USBHS_GPTIMER0LD_GPTLD_MASK              USB_GPTIMER0LD_GPTLD_MASK
#define USBHS_GPTIMER0LD_GPTLD_SHIFT             USB_GPTIMER0LD_GPTLD_SHIFT
#define USBHS_GPTIMER0LD_GPTLD(x)                USB_GPTIMER0LD_GPTLD(x)
#define USBHS_GPTIMER0CTL_GPTCNT_MASK            USB_GPTIMER0CTRL_GPTCNT_MASK
#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           USB_GPTIMER0CTRL_GPTCNT_SHIFT
#define USBHS_GPTIMER0CTL_GPTCNT(x)              USB_GPTIMER0CTRL_GPTCNT(x)
#define USBHS_GPTIMER0CTL_MODE_MASK              USB_GPTIMER0CTRL_GPTMODE_MASK
#define USBHS_GPTIMER0CTL_MODE_SHIFT             USB_GPTIMER0CTRL_GPTMODE_SHIFT
#define USBHS_GPTIMER0CTL_MODE(x)                USB_GPTIMER0CTRL_GPTMODE(x)
#define USBHS_GPTIMER0CTL_RST_MASK               USB_GPTIMER0CTRL_GPTRST_MASK
#define USBHS_GPTIMER0CTL_RST_SHIFT              USB_GPTIMER0CTRL_GPTRST_SHIFT
#define USBHS_GPTIMER0CTL_RST(x)                 USB_GPTIMER0CTRL_GPTRST(x)
#define USBHS_GPTIMER0CTL_RUN_MASK               USB_GPTIMER0CTRL_GPTRUN_MASK
#define USBHS_GPTIMER0CTL_RUN_SHIFT              USB_GPTIMER0CTRL_GPTRUN_SHIFT
#define USBHS_GPTIMER0CTL_RUN(x)                 USB_GPTIMER0CTRL_GPTRUN(x)
#define USBHS_GPTIMER1LD_GPTLD_MASK              USB_GPTIMER1LD_GPTLD_MASK
#define USBHS_GPTIMER1LD_GPTLD_SHIFT             USB_GPTIMER1LD_GPTLD_SHIFT
#define USBHS_GPTIMER1LD_GPTLD(x)                USB_GPTIMER1LD_GPTLD(x)
#define USBHS_GPTIMER1CTL_GPTCNT_MASK            USB_GPTIMER1CTRL_GPTCNT_MASK
#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           USB_GPTIMER1CTRL_GPTCNT_SHIFT
#define USBHS_GPTIMER1CTL_GPTCNT(x)              USB_GPTIMER1CTRL_GPTCNT(x)
#define USBHS_GPTIMER1CTL_MODE_MASK              USB_GPTIMER1CTRL_GPTMODE_MASK
#define USBHS_GPTIMER1CTL_MODE_SHIFT             USB_GPTIMER1CTRL_GPTMODE_SHIFT
#define USBHS_GPTIMER1CTL_MODE(x)                USB_GPTIMER1CTRL_GPTMODE(x)
#define USBHS_GPTIMER1CTL_RST_MASK               USB_GPTIMER1CTRL_GPTRST_MASK
#define USBHS_GPTIMER1CTL_RST_SHIFT              USB_GPTIMER1CTRL_GPTRST_SHIFT
#define USBHS_GPTIMER1CTL_RST(x)                 USB_GPTIMER1CTRL_GPTRST(x)
#define USBHS_GPTIMER1CTL_RUN_MASK               USB_GPTIMER1CTRL_GPTRUN_MASK
#define USBHS_GPTIMER1CTL_RUN_SHIFT              USB_GPTIMER1CTRL_GPTRUN_SHIFT
#define USBHS_GPTIMER1CTL_RUN(x)                 USB_GPTIMER1CTRL_GPTRUN(x)
#define USBHS_USB_SBUSCFG_BURSTMODE_MASK         USB_SBUSCFG_AHBBRST_MASK
#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT        USB_SBUSCFG_AHBBRST_SHIFT
#define USBHS_USB_SBUSCFG_BURSTMODE(x)           USB_SBUSCFG_AHBBRST(x)
#define USBHS_HCIVERSION_CAPLENGTH(x)            USB_HCIVERSION_CAPLENGTH(x)
#define USBHS_HCIVERSION_HCIVERSION_MASK         USB_HCIVERSION_HCIVERSION_MASK
#define USBHS_HCIVERSION_HCIVERSION_SHIFT        USB_HCIVERSION_HCIVERSION_SHIFT
#define USBHS_HCIVERSION_HCIVERSION(x)           USB_HCIVERSION_HCIVERSION(x)
#define USBHS_HCSPARAMS_N_PORTS_MASK             USB_HCSPARAMS_N_PORTS_MASK
#define USBHS_HCSPARAMS_N_PORTS_SHIFT            USB_HCSPARAMS_N_PORTS_SHIFT
#define USBHS_HCSPARAMS_N_PORTS(x)               USB_HCSPARAMS_N_PORTS(x)
#define USBHS_HCSPARAMS_PPC_MASK                 USB_HCSPARAMS_PPC_MASK
#define USBHS_HCSPARAMS_PPC_SHIFT                USB_HCSPARAMS_PPC_SHIFT
#define USBHS_HCSPARAMS_PPC(x)                   USB_HCSPARAMS_PPC(x)
#define USBHS_HCSPARAMS_N_PCC_MASK               USB_HCSPARAMS_N_PCC_MASK
#define USBHS_HCSPARAMS_N_PCC_SHIFT              USB_HCSPARAMS_N_PCC_SHIFT
#define USBHS_HCSPARAMS_N_PCC(x)                 USB_HCSPARAMS_N_PCC(x)
#define USBHS_HCSPARAMS_N_CC_MASK                USB_HCSPARAMS_N_CC_MASK
#define USBHS_HCSPARAMS_N_CC_SHIFT               USB_HCSPARAMS_N_CC_SHIFT
#define USBHS_HCSPARAMS_N_CC(x)                  USB_HCSPARAMS_N_CC(x)
#define USBHS_HCSPARAMS_PI_MASK                  USB_HCSPARAMS_PI_MASK
#define USBHS_HCSPARAMS_PI_SHIFT                 USB_HCSPARAMS_PI_SHIFT
#define USBHS_HCSPARAMS_PI(x)                    USB_HCSPARAMS_PI(x)
#define USBHS_HCSPARAMS_N_PTT_MASK               USB_HCSPARAMS_N_PTT_MASK
#define USBHS_HCSPARAMS_N_PTT_SHIFT              USB_HCSPARAMS_N_PTT_SHIFT
#define USBHS_HCSPARAMS_N_PTT(x)                 USB_HCSPARAMS_N_PTT(x)
#define USBHS_HCSPARAMS_N_TT_MASK                USB_HCSPARAMS_N_TT_MASK
#define USBHS_HCSPARAMS_N_TT_SHIFT               USB_HCSPARAMS_N_TT_SHIFT
#define USBHS_HCSPARAMS_N_TT(x)                  USB_HCSPARAMS_N_TT(x)
#define USBHS_HCCPARAMS_ADC_MASK                 USB_HCCPARAMS_ADC_MASK
#define USBHS_HCCPARAMS_ADC_SHIFT                USB_HCCPARAMS_ADC_SHIFT
#define USBHS_HCCPARAMS_ADC(x)                   USB_HCCPARAMS_ADC(x)
#define USBHS_HCCPARAMS_PFL_MASK                 USB_HCCPARAMS_PFL_MASK
#define USBHS_HCCPARAMS_PFL_SHIFT                USB_HCCPARAMS_PFL_SHIFT
#define USBHS_HCCPARAMS_PFL(x)                   USB_HCCPARAMS_PFL(x)
#define USBHS_HCCPARAMS_ASP_MASK                 USB_HCCPARAMS_ASP_MASK
#define USBHS_HCCPARAMS_ASP_SHIFT                USB_HCCPARAMS_ASP_SHIFT
#define USBHS_HCCPARAMS_ASP(x)                   USB_HCCPARAMS_ASP(x)
#define USBHS_HCCPARAMS_IST_MASK                 USB_HCCPARAMS_IST_MASK
#define USBHS_HCCPARAMS_IST_SHIFT                USB_HCCPARAMS_IST_SHIFT
#define USBHS_HCCPARAMS_IST(x)                   USB_HCCPARAMS_IST(x)
#define USBHS_HCCPARAMS_EECP_MASK                USB_HCCPARAMS_EECP_MASK
#define USBHS_HCCPARAMS_EECP_SHIFT               USB_HCCPARAMS_EECP_SHIFT
#define USBHS_HCCPARAMS_EECP(x)                  USB_HCCPARAMS_EECP(x)
#define USBHS_DCIVERSION_DCIVERSION_MASK         USB_DCIVERSION_DCIVERSION_MASK
#define USBHS_DCIVERSION_DCIVERSION_SHIFT        USB_DCIVERSION_DCIVERSION_SHIFT
#define USBHS_DCIVERSION_DCIVERSION(x)           USB_DCIVERSION_DCIVERSION(x)
#define USBHS_DCCPARAMS_DEN_MASK                 USB_DCCPARAMS_DEN_MASK
#define USBHS_DCCPARAMS_DEN_SHIFT                USB_DCCPARAMS_DEN_SHIFT
#define USBHS_DCCPARAMS_DEN(x)                   USB_DCCPARAMS_DEN(x)
#define USBHS_DCCPARAMS_DC_MASK                  USB_DCCPARAMS_DC_MASK
#define USBHS_DCCPARAMS_DC_SHIFT                 USB_DCCPARAMS_DC_SHIFT
#define USBHS_DCCPARAMS_DC(x)                    USB_DCCPARAMS_DC(x)
#define USBHS_DCCPARAMS_HC_MASK                  USB_DCCPARAMS_HC_MASK
#define USBHS_DCCPARAMS_HC_SHIFT                 USB_DCCPARAMS_HC_SHIFT
#define USBHS_DCCPARAMS_HC(x)                    USB_DCCPARAMS_HC(x)
#define USBHS_USBCMD_RS_MASK                     USB_USBCMD_RS_MASK
#define USBHS_USBCMD_RS_SHIFT                    USB_USBCMD_RS_SHIFT
#define USBHS_USBCMD_RS(x)                       USB_USBCMD_RS(x)
#define USBHS_USBCMD_RST_MASK                    USB_USBCMD_RST_MASK
#define USBHS_USBCMD_RST_SHIFT                   USB_USBCMD_RST_SHIFT
#define USBHS_USBCMD_RST(x)                      USB_USBCMD_RST(x)
#define USBHS_USBCMD_FS_MASK                     USB_USBCMD_FS_1_MASK
#define USBHS_USBCMD_FS_SHIFT                    USB_USBCMD_FS_1_SHIFT
#define USBHS_USBCMD_FS(x)                       USB_USBCMD_FS_1(x)
#define USBHS_USBCMD_PSE_MASK                    USB_USBCMD_PSE_MASK
#define USBHS_USBCMD_PSE_SHIFT                   USB_USBCMD_PSE_SHIFT
#define USBHS_USBCMD_PSE(x)                      USB_USBCMD_PSE(x)
#define USBHS_USBCMD_ASE_MASK                    USB_USBCMD_ASE_MASK
#define USBHS_USBCMD_ASE_SHIFT                   USB_USBCMD_ASE_SHIFT
#define USBHS_USBCMD_ASE(x)                      USB_USBCMD_ASE(x)
#define USBHS_USBCMD_IAA_MASK                    USB_USBCMD_IAA_MASK
#define USBHS_USBCMD_IAA_SHIFT                   USB_USBCMD_IAA_SHIFT
#define USBHS_USBCMD_IAA(x)                      USB_USBCMD_IAA(x)
#define USBHS_USBCMD_ASP_MASK                    USB_USBCMD_ASP_MASK
#define USBHS_USBCMD_ASP_SHIFT                   USB_USBCMD_ASP_SHIFT
#define USBHS_USBCMD_ASP(x)                      USB_USBCMD_ASP(x)
#define USBHS_USBCMD_ASPE_MASK                   USB_USBCMD_ASPE_MASK
#define USBHS_USBCMD_ASPE_SHIFT                  USB_USBCMD_ASPE_SHIFT
#define USBHS_USBCMD_ASPE(x)                     USB_USBCMD_ASPE(x)
#define USBHS_USBCMD_ATDTW_MASK                  USB_USBCMD_ATDTW_MASK
#define USBHS_USBCMD_ATDTW_SHIFT                 USB_USBCMD_ATDTW_SHIFT
#define USBHS_USBCMD_ATDTW(x)                    USB_USBCMD_ATDTW(x)
#define USBHS_USBCMD_SUTW_MASK                   USB_USBCMD_SUTW_MASK
#define USBHS_USBCMD_SUTW_SHIFT                  USB_USBCMD_SUTW_SHIFT
#define USBHS_USBCMD_SUTW(x)                     USB_USBCMD_SUTW(x)
#define USBHS_USBCMD_FS2_MASK                    USB_USBCMD_FS_2_MASK
#define USBHS_USBCMD_FS2_SHIFT                   USB_USBCMD_FS_2_SHIFT
#define USBHS_USBCMD_FS2(x)                      USB_USBCMD_FS_2(x)
#define USBHS_USBCMD_ITC_MASK                    USB_USBCMD_ITC_MASK
#define USBHS_USBCMD_ITC_SHIFT                   USB_USBCMD_ITC_SHIFT
#define USBHS_USBCMD_ITC(x)                      USB_USBCMD_ITC(x)
#define USBHS_USBSTS_UI_MASK                     USB_USBSTS_UI_MASK
#define USBHS_USBSTS_UI_SHIFT                    USB_USBSTS_UI_SHIFT
#define USBHS_USBSTS_UI(x)                       USB_USBSTS_UI(x)
#define USBHS_USBSTS_UEI_MASK                    USB_USBSTS_UEI_MASK
#define USBHS_USBSTS_UEI_SHIFT                   USB_USBSTS_UEI_SHIFT
#define USBHS_USBSTS_UEI(x)                      USB_USBSTS_UEI(x)
#define USBHS_USBSTS_PCI_MASK                    USB_USBSTS_PCI_MASK
#define USBHS_USBSTS_PCI_SHIFT                   USB_USBSTS_PCI_SHIFT
#define USBHS_USBSTS_PCI(x)                      USB_USBSTS_PCI(x)
#define USBHS_USBSTS_FRI_MASK                    USB_USBSTS_FRI_MASK
#define USBHS_USBSTS_FRI_SHIFT                   USB_USBSTS_FRI_SHIFT
#define USBHS_USBSTS_FRI(x)                      USB_USBSTS_FRI(x)
#define USBHS_USBSTS_SEI_MASK                    USB_USBSTS_SEI_MASK
#define USBHS_USBSTS_SEI_SHIFT                   USB_USBSTS_SEI_SHIFT
#define USBHS_USBSTS_SEI(x)                      USB_USBSTS_SEI(x)
#define USBHS_USBSTS_AAI_MASK                    USB_USBSTS_AAI_MASK
#define USBHS_USBSTS_AAI_SHIFT                   USB_USBSTS_AAI_SHIFT
#define USBHS_USBSTS_AAI(x)                      USB_USBSTS_AAI(x)
#define USBHS_USBSTS_URI_MASK                    USB_USBSTS_URI_MASK
#define USBHS_USBSTS_URI_SHIFT                   USB_USBSTS_URI_SHIFT
#define USBHS_USBSTS_URI(x)                      USB_USBSTS_URI(x)
#define USBHS_USBSTS_SRI_MASK                    USB_USBSTS_SRI_MASK
#define USBHS_USBSTS_SRI_SHIFT                   USB_USBSTS_SRI_SHIFT
#define USBHS_USBSTS_SRI(x)                      USB_USBSTS_SRI(x)
#define USBHS_USBSTS_SLI_MASK                    USB_USBSTS_SLI_MASK
#define USBHS_USBSTS_SLI_SHIFT                   USB_USBSTS_SLI_SHIFT
#define USBHS_USBSTS_SLI(x)                      USB_USBSTS_SLI(x)
#define USBHS_USBSTS_ULPII_MASK                  USB_USBSTS_ULPII_MASK
#define USBHS_USBSTS_ULPII_SHIFT                 USB_USBSTS_ULPII_SHIFT
#define USBHS_USBSTS_ULPII(x)                    USB_USBSTS_ULPII(x)
#define USBHS_USBSTS_HCH_MASK                    USB_USBSTS_HCH_MASK
#define USBHS_USBSTS_HCH_SHIFT                   USB_USBSTS_HCH_SHIFT
#define USBHS_USBSTS_HCH(x)                      USB_USBSTS_HCH(x)
#define USBHS_USBSTS_RCL_MASK                    USB_USBSTS_RCL_MASK
#define USBHS_USBSTS_RCL_SHIFT                   USB_USBSTS_RCL_SHIFT
#define USBHS_USBSTS_RCL(x)                      USB_USBSTS_RCL(x)
#define USBHS_USBSTS_PS_MASK                     USB_USBSTS_PS_MASK
#define USBHS_USBSTS_PS_SHIFT                    USB_USBSTS_PS_SHIFT
#define USBHS_USBSTS_PS(x)                       USB_USBSTS_PS(x)
#define USBHS_USBSTS_AS_MASK                     USB_USBSTS_AS_MASK
#define USBHS_USBSTS_AS_SHIFT                    USB_USBSTS_AS_SHIFT
#define USBHS_USBSTS_AS(x)                       USB_USBSTS_AS(x)
#define USBHS_USBSTS_NAKI_MASK                   USB_USBSTS_NAKI_MASK
#define USBHS_USBSTS_NAKI_SHIFT                  USB_USBSTS_NAKI_SHIFT
#define USBHS_USBSTS_NAKI(x)                     USB_USBSTS_NAKI(x)
#define USBHS_USBSTS_TI0_MASK                    USB_USBSTS_TI0_MASK
#define USBHS_USBSTS_TI0_SHIFT                   USB_USBSTS_TI0_SHIFT
#define USBHS_USBSTS_TI0(x)                      USB_USBSTS_TI0(x)
#define USBHS_USBSTS_TI1_MASK                    USB_USBSTS_TI1_MASK
#define USBHS_USBSTS_TI1_SHIFT                   USB_USBSTS_TI1_SHIFT
#define USBHS_USBSTS_TI1(x)                      USB_USBSTS_TI1(x)
#define USBHS_USBINTR_UE_MASK                    USB_USBINTR_UE_MASK
#define USBHS_USBINTR_UE_SHIFT                   USB_USBINTR_UE_SHIFT
#define USBHS_USBINTR_UE(x)                      USB_USBINTR_UE(x)
#define USBHS_USBINTR_UEE_MASK                   USB_USBINTR_UEE_MASK
#define USBHS_USBINTR_UEE_SHIFT                  USB_USBINTR_UEE_SHIFT
#define USBHS_USBINTR_UEE(x)                     USB_USBINTR_UEE(x)
#define USBHS_USBINTR_PCE_MASK                   USB_USBINTR_PCE_MASK
#define USBHS_USBINTR_PCE_SHIFT                  USB_USBINTR_PCE_SHIFT
#define USBHS_USBINTR_PCE(x)                     USB_USBINTR_PCE(x)
#define USBHS_USBINTR_FRE_MASK                   USB_USBINTR_FRE_MASK
#define USBHS_USBINTR_FRE_SHIFT                  USB_USBINTR_FRE_SHIFT
#define USBHS_USBINTR_FRE(x)                     USB_USBINTR_FRE(x)
#define USBHS_USBINTR_SEE_MASK                   USB_USBINTR_SEE_MASK
#define USBHS_USBINTR_SEE_SHIFT                  USB_USBINTR_SEE_SHIFT
#define USBHS_USBINTR_SEE(x)                     USB_USBINTR_SEE(x)
#define USBHS_USBINTR_AAE_MASK                   USB_USBINTR_AAE_MASK
#define USBHS_USBINTR_AAE_SHIFT                  USB_USBINTR_AAE_SHIFT
#define USBHS_USBINTR_AAE(x)                     USB_USBINTR_AAE(x)
#define USBHS_USBINTR_URE_MASK                   USB_USBINTR_URE_MASK
#define USBHS_USBINTR_URE_SHIFT                  USB_USBINTR_URE_SHIFT
#define USBHS_USBINTR_URE(x)                     USB_USBINTR_URE(x)
#define USBHS_USBINTR_SRE_MASK                   USB_USBINTR_SRE_MASK
#define USBHS_USBINTR_SRE_SHIFT                  USB_USBINTR_SRE_SHIFT
#define USBHS_USBINTR_SRE(x)                     USB_USBINTR_SRE(x)
#define USBHS_USBINTR_SLE_MASK                   USB_USBINTR_SLE_MASK
#define USBHS_USBINTR_SLE_SHIFT                  USB_USBINTR_SLE_SHIFT
#define USBHS_USBINTR_SLE(x)                     USB_USBINTR_SLE(x)
#define USBHS_USBINTR_ULPIE_MASK                 USB_USBINTR_ULPIE_MASK
#define USBHS_USBINTR_ULPIE_SHIFT                USB_USBINTR_ULPIE_SHIFT
#define USBHS_USBINTR_ULPIE(x)                   USB_USBINTR_ULPIE(x)
#define USBHS_USBINTR_NAKE_MASK                  USB_USBINTR_NAKE_MASK
#define USBHS_USBINTR_NAKE_SHIFT                 USB_USBINTR_NAKE_SHIFT
#define USBHS_USBINTR_NAKE(x)                    USB_USBINTR_NAKE(x)
#define USBHS_USBINTR_UAIE_MASK                  USB_USBINTR_UAIE_MASK
#define USBHS_USBINTR_UAIE_SHIFT                 USB_USBINTR_UAIE_SHIFT
#define USBHS_USBINTR_UAIE(x)                    USB_USBINTR_UAIE(x)
#define USBHS_USBINTR_UPIE_MASK                  USB_USBINTR_UPIE_MASK
#define USBHS_USBINTR_UPIE_SHIFT                 USB_USBINTR_UPIE_SHIFT
#define USBHS_USBINTR_UPIE(x)                    USB_USBINTR_UPIE(x)
#define USBHS_USBINTR_TIE0_MASK                  USB_USBINTR_TIE0_MASK
#define USBHS_USBINTR_TIE0_SHIFT                 USB_USBINTR_TIE0_SHIFT
#define USBHS_USBINTR_TIE0(x)                    USB_USBINTR_TIE0(x)
#define USBHS_USBINTR_TIE1_MASK                  USB_USBINTR_TIE1_MASK
#define USBHS_USBINTR_TIE1_SHIFT                 USB_USBINTR_TIE1_SHIFT
#define USBHS_USBINTR_TIE1(x)                    USB_USBINTR_TIE1(x)
#define USBHS_FRINDEX_FRINDEX_MASK               USB_FRINDEX_FRINDEX_MASK
#define USBHS_FRINDEX_FRINDEX_SHIFT              USB_FRINDEX_FRINDEX_SHIFT
#define USBHS_FRINDEX_FRINDEX(x)                 USB_FRINDEX_FRINDEX(x)
#define USBHS_DEVICEADDR_USBADRA_MASK            USB_DEVICEADDR_USBADRA_MASK
#define USBHS_DEVICEADDR_USBADRA_SHIFT           USB_DEVICEADDR_USBADRA_SHIFT
#define USBHS_DEVICEADDR_USBADRA(x)              USB_DEVICEADDR_USBADRA(x)
#define USBHS_DEVICEADDR_USBADR_MASK             USB_DEVICEADDR_USBADR_MASK
#define USBHS_DEVICEADDR_USBADR_SHIFT            USB_DEVICEADDR_USBADR_SHIFT
#define USBHS_DEVICEADDR_USBADR(x)               USB_DEVICEADDR_USBADR(x)
#define USBHS_PERIODICLISTBASE_PERBASE_MASK      USB_PERIODICLISTBASE_BASEADR_MASK
#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT     USB_PERIODICLISTBASE_BASEADR_SHIFT
#define USBHS_PERIODICLISTBASE_PERBASE(x)        USB_PERIODICLISTBASE_BASEADR(x)
#define USBHS_ASYNCLISTADDR_ASYBASE_MASK         USB_ASYNCLISTADDR_ASYBASE_MASK
#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        USB_ASYNCLISTADDR_ASYBASE_SHIFT
#define USBHS_ASYNCLISTADDR_ASYBASE(x)           USB_ASYNCLISTADDR_ASYBASE(x)
#define USBHS_EPLISTADDR_EPBASE_MASK             USB_ENDPTLISTADDR_EPBASE_MASK
#define USBHS_EPLISTADDR_EPBASE_SHIFT            USB_ENDPTLISTADDR_EPBASE_SHIFT
#define USBHS_EPLISTADDR_EPBASE(x)               USB_ENDPTLISTADDR_EPBASE(x)
#define USBHS_BURSTSIZE_RXPBURST_MASK            USB_BURSTSIZE_RXPBURST_MASK
#define USBHS_BURSTSIZE_RXPBURST_SHIFT           USB_BURSTSIZE_RXPBURST_SHIFT
#define USBHS_BURSTSIZE_RXPBURST(x)              USB_BURSTSIZE_RXPBURST(x)
#define USBHS_BURSTSIZE_TXPBURST_MASK            USB_BURSTSIZE_TXPBURST_MASK
#define USBHS_BURSTSIZE_TXPBURST_SHIFT           USB_BURSTSIZE_TXPBURST_SHIFT
#define USBHS_BURSTSIZE_TXPBURST(x)              USB_BURSTSIZE_TXPBURST(x)
#define USBHS_TXFILLTUNING_TXSCHOH_MASK          USB_TXFILLTUNING_TXSCHOH_MASK
#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         USB_TXFILLTUNING_TXSCHOH_SHIFT
#define USBHS_TXFILLTUNING_TXSCHOH(x)            USB_TXFILLTUNING_TXSCHOH(x)
#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      USB_TXFILLTUNING_TXSCHHEALTH_MASK
#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
#define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        USB_TXFILLTUNING_TXSCHHEALTH(x)
#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      USB_TXFILLTUNING_TXFIFOTHRES_MASK
#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
#define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        USB_TXFILLTUNING_TXFIFOTHRES(x)
#define USBHS_ENDPTNAK_EPRN_MASK                 USB_ENDPTNAK_EPRN_MASK
#define USBHS_ENDPTNAK_EPRN_SHIFT                USB_ENDPTNAK_EPRN_SHIFT
#define USBHS_ENDPTNAK_EPRN(x)                   USB_ENDPTNAK_EPRN(x)
#define USBHS_ENDPTNAK_EPTN_MASK                 USB_ENDPTNAK_EPTN_MASK
#define USBHS_ENDPTNAK_EPTN_SHIFT                USB_ENDPTNAK_EPTN_SHIFT
#define USBHS_ENDPTNAK_EPTN(x)                   USB_ENDPTNAK_EPTN(x)
#define USBHS_ENDPTNAKEN_EPRNE_MASK              USB_ENDPTNAKEN_EPRNE_MASK
#define USBHS_ENDPTNAKEN_EPRNE_SHIFT             USB_ENDPTNAKEN_EPRNE_SHIFT
#define USBHS_ENDPTNAKEN_EPRNE(x)                USB_ENDPTNAKEN_EPRNE(x)
#define USBHS_ENDPTNAKEN_EPTNE_MASK              USB_ENDPTNAKEN_EPTNE_MASK
#define USBHS_ENDPTNAKEN_EPTNE_SHIFT             USB_ENDPTNAKEN_EPTNE_SHIFT
#define USBHS_ENDPTNAKEN_EPTNE(x)                USB_ENDPTNAKEN_EPTNE(x)
#define USBHS_CONFIGFLAG_CF_MASK                 USB_CONFIGFLAG_CF_MASK
#define USBHS_CONFIGFLAG_CF_SHIFT                USB_CONFIGFLAG_CF_SHIFT
#define USBHS_CONFIGFLAG_CF(x)                   USB_CONFIGFLAG_CF(x)
#define USBHS_PORTSC1_CCS_MASK                   USB_PORTSC1_CCS_MASK
#define USBHS_PORTSC1_CCS_SHIFT                  USB_PORTSC1_CCS_SHIFT
#define USBHS_PORTSC1_CCS(x)                     USB_PORTSC1_CCS(x)
#define USBHS_PORTSC1_CSC_MASK                   USB_PORTSC1_CSC_MASK
#define USBHS_PORTSC1_CSC_SHIFT                  USB_PORTSC1_CSC_SHIFT
#define USBHS_PORTSC1_CSC(x)                     USB_PORTSC1_CSC(x)
#define USBHS_PORTSC1_PE_MASK                    USB_PORTSC1_PE_MASK
#define USBHS_PORTSC1_PE_SHIFT                   USB_PORTSC1_PE_SHIFT
#define USBHS_PORTSC1_PE(x)                      USB_PORTSC1_PE(x)
#define USBHS_PORTSC1_PEC_MASK                   USB_PORTSC1_PEC_MASK
#define USBHS_PORTSC1_PEC_SHIFT                  USB_PORTSC1_PEC_SHIFT
#define USBHS_PORTSC1_PEC(x)                     USB_PORTSC1_PEC(x)
#define USBHS_PORTSC1_OCA_MASK                   USB_PORTSC1_OCA_MASK
#define USBHS_PORTSC1_OCA_SHIFT                  USB_PORTSC1_OCA_SHIFT
#define USBHS_PORTSC1_OCA(x)                     USB_PORTSC1_OCA(x)
#define USBHS_PORTSC1_OCC_MASK                   USB_PORTSC1_OCC_MASK
#define USBHS_PORTSC1_OCC_SHIFT                  USB_PORTSC1_OCC_SHIFT
#define USBHS_PORTSC1_OCC(x)                     USB_PORTSC1_OCC(x)
#define USBHS_PORTSC1_FPR_MASK                   USB_PORTSC1_FPR_MASK
#define USBHS_PORTSC1_FPR_SHIFT                  USB_PORTSC1_FPR_SHIFT
#define USBHS_PORTSC1_FPR(x)                     USB_PORTSC1_FPR(x)
#define USBHS_PORTSC1_SUSP_MASK                  USB_PORTSC1_SUSP_MASK
#define USBHS_PORTSC1_SUSP_SHIFT                 USB_PORTSC1_SUSP_SHIFT
#define USBHS_PORTSC1_SUSP(x)                    USB_PORTSC1_SUSP(x)
#define USBHS_PORTSC1_PR_MASK                    USB_PORTSC1_PR_MASK
#define USBHS_PORTSC1_PR_SHIFT                   USB_PORTSC1_PR_SHIFT
#define USBHS_PORTSC1_PR(x)                      USB_PORTSC1_PR(x)
#define USBHS_PORTSC1_HSP_MASK                   USB_PORTSC1_HSP_MASK
#define USBHS_PORTSC1_HSP_SHIFT                  USB_PORTSC1_HSP_SHIFT
#define USBHS_PORTSC1_HSP(x)                     USB_PORTSC1_HSP(x)
#define USBHS_PORTSC1_LS_MASK                    USB_PORTSC1_LS_MASK
#define USBHS_PORTSC1_LS_SHIFT                   USB_PORTSC1_LS_SHIFT
#define USBHS_PORTSC1_LS(x)                      USB_PORTSC1_LS(x)
#define USBHS_PORTSC1_PP_MASK                    USB_PORTSC1_PP_MASK
#define USBHS_PORTSC1_PP_SHIFT                   USB_PORTSC1_PP_SHIFT
#define USBHS_PORTSC1_PP(x)                      USB_PORTSC1_PP(x)
#define USBHS_PORTSC1_PO_MASK                    USB_PORTSC1_PO_MASK
#define USBHS_PORTSC1_PO_SHIFT                   USB_PORTSC1_PO_SHIFT
#define USBHS_PORTSC1_PO(x)                      USB_PORTSC1_PO(x)
#define USBHS_PORTSC1_PIC_MASK                   USB_PORTSC1_PIC_MASK
#define USBHS_PORTSC1_PIC_SHIFT                  USB_PORTSC1_PIC_SHIFT
#define USBHS_PORTSC1_PIC(x)                     USB_PORTSC1_PIC(x)
#define USBHS_PORTSC1_PTC_MASK                   USB_PORTSC1_PTC_MASK
#define USBHS_PORTSC1_PTC_SHIFT                  USB_PORTSC1_PTC_SHIFT
#define USBHS_PORTSC1_PTC(x)                     USB_PORTSC1_PTC(x)
#define USBHS_PORTSC1_WKCN_MASK                  USB_PORTSC1_WKCN_MASK
#define USBHS_PORTSC1_WKCN_SHIFT                 USB_PORTSC1_WKCN_SHIFT
#define USBHS_PORTSC1_WKCN(x)                    USB_PORTSC1_WKCN(x)
#define USBHS_PORTSC1_WKDS_MASK                  USB_PORTSC1_WKDC_MASK
#define USBHS_PORTSC1_WKDS_SHIFT                 USB_PORTSC1_WKDC_SHIFT
#define USBHS_PORTSC1_WKDS(x)                    USB_PORTSC1_WKDC(x)
#define USBHS_PORTSC1_WKOC_MASK                  USB_PORTSC1_WKOC_MASK
#define USBHS_PORTSC1_WKOC_SHIFT                 USB_PORTSC1_WKOC_SHIFT
#define USBHS_PORTSC1_WKOC(x)                    USB_PORTSC1_WKOC(x)
#define USBHS_PORTSC1_PHCD_MASK                  USB_PORTSC1_PHCD_MASK
#define USBHS_PORTSC1_PHCD_SHIFT                 USB_PORTSC1_PHCD_SHIFT
#define USBHS_PORTSC1_PHCD(x)                    USB_PORTSC1_PHCD(x)
#define USBHS_PORTSC1_PFSC_MASK                  USB_PORTSC1_PFSC_MASK
#define USBHS_PORTSC1_PFSC_SHIFT                 USB_PORTSC1_PFSC_SHIFT
#define USBHS_PORTSC1_PFSC(x)                    USB_PORTSC1_PFSC(x)
#define USBHS_PORTSC1_PTS2_MASK                  USB_PORTSC1_PTS_2_MASK
#define USBHS_PORTSC1_PTS2_SHIFT                 USB_PORTSC1_PTS_2_SHIFT
#define USBHS_PORTSC1_PTS2(x)                    USB_PORTSC1_PTS_2(x)
#define USBHS_PORTSC1_PSPD_MASK                  USB_PORTSC1_PSPD_MASK
#define USBHS_PORTSC1_PSPD_SHIFT                 USB_PORTSC1_PSPD_SHIFT
#define USBHS_PORTSC1_PSPD(x)                    USB_PORTSC1_PSPD(x)
#define USBHS_PORTSC1_PTW_MASK                   USB_PORTSC1_PTW_MASK
#define USBHS_PORTSC1_PTW_SHIFT                  USB_PORTSC1_PTW_SHIFT
#define USBHS_PORTSC1_PTW(x)                     USB_PORTSC1_PTW(x)
#define USBHS_PORTSC1_STS_MASK                   USB_PORTSC1_STS_MASK
#define USBHS_PORTSC1_STS_SHIFT                  USB_PORTSC1_STS_SHIFT
#define USBHS_PORTSC1_STS(x)                     USB_PORTSC1_STS(x)
#define USBHS_PORTSC1_PTS_MASK                   USB_PORTSC1_PTS_1_MASK
#define USBHS_PORTSC1_PTS_SHIFT                  USB_PORTSC1_PTS_1_SHIFT
#define USBHS_PORTSC1_PTS(x)                     USB_PORTSC1_PTS_1(x)
#define USBHS_OTGSC_VD_MASK                      USB_OTGSC_VD_MASK
#define USBHS_OTGSC_VD_SHIFT                     USB_OTGSC_VD_SHIFT
#define USBHS_OTGSC_VD(x)                        USB_OTGSC_VD(x)
#define USBHS_OTGSC_VC_MASK                      USB_OTGSC_VC_MASK
#define USBHS_OTGSC_VC_SHIFT                     USB_OTGSC_VC_SHIFT
#define USBHS_OTGSC_VC(x)                        USB_OTGSC_VC(x)
#define USBHS_OTGSC_OT_MASK                      USB_OTGSC_OT_MASK
#define USBHS_OTGSC_OT_SHIFT                     USB_OTGSC_OT_SHIFT
#define USBHS_OTGSC_OT(x)                        USB_OTGSC_OT(x)
#define USBHS_OTGSC_DP_MASK                      USB_OTGSC_DP_MASK
#define USBHS_OTGSC_DP_SHIFT                     USB_OTGSC_DP_SHIFT
#define USBHS_OTGSC_DP(x)                        USB_OTGSC_DP(x)
#define USBHS_OTGSC_IDPU_MASK                    USB_OTGSC_IDPU_MASK
#define USBHS_OTGSC_IDPU_SHIFT                   USB_OTGSC_IDPU_SHIFT
#define USBHS_OTGSC_IDPU(x)                      USB_OTGSC_IDPU(x)
#define USBHS_OTGSC_ID_MASK                      USB_OTGSC_ID_MASK
#define USBHS_OTGSC_ID_SHIFT                     USB_OTGSC_ID_SHIFT
#define USBHS_OTGSC_ID(x)                        USB_OTGSC_ID(x)
#define USBHS_OTGSC_AVV_MASK                     USB_OTGSC_AVV_MASK
#define USBHS_OTGSC_AVV_SHIFT                    USB_OTGSC_AVV_SHIFT
#define USBHS_OTGSC_AVV(x)                       USB_OTGSC_AVV(x)
#define USBHS_OTGSC_ASV_MASK                     USB_OTGSC_ASV_MASK
#define USBHS_OTGSC_ASV_SHIFT                    USB_OTGSC_ASV_SHIFT
#define USBHS_OTGSC_ASV(x)                       USB_OTGSC_ASV(x)
#define USBHS_OTGSC_BSV_MASK                     USB_OTGSC_BSV_MASK
#define USBHS_OTGSC_BSV_SHIFT                    USB_OTGSC_BSV_SHIFT
#define USBHS_OTGSC_BSV(x)                       USB_OTGSC_BSV(x)
#define USBHS_OTGSC_BSE_MASK                     USB_OTGSC_BSE_MASK
#define USBHS_OTGSC_BSE_SHIFT                    USB_OTGSC_BSE_SHIFT
#define USBHS_OTGSC_BSE(x)                       USB_OTGSC_BSE(x)
#define USBHS_OTGSC_MST_MASK                     USB_OTGSC_TOG_1MS_MASK
#define USBHS_OTGSC_MST_SHIFT                    USB_OTGSC_TOG_1MS_SHIFT
#define USBHS_OTGSC_MST(x)                       USB_OTGSC_TOG_1MS(x)
#define USBHS_OTGSC_DPS_MASK                     USB_OTGSC_DPS_MASK
#define USBHS_OTGSC_DPS_SHIFT                    USB_OTGSC_DPS_SHIFT
#define USBHS_OTGSC_DPS(x)                       USB_OTGSC_DPS(x)
#define USBHS_OTGSC_IDIS_MASK                    USB_OTGSC_IDIS_MASK
#define USBHS_OTGSC_IDIS_SHIFT                   USB_OTGSC_IDIS_SHIFT
#define USBHS_OTGSC_IDIS(x)                      USB_OTGSC_IDIS(x)
#define USBHS_OTGSC_AVVIS_MASK                   USB_OTGSC_AVVIS_MASK
#define USBHS_OTGSC_AVVIS_SHIFT                  USB_OTGSC_AVVIS_SHIFT
#define USBHS_OTGSC_AVVIS(x)                     USB_OTGSC_AVVIS(x)
#define USBHS_OTGSC_ASVIS_MASK                   USB_OTGSC_ASVIS_MASK
#define USBHS_OTGSC_ASVIS_SHIFT                  USB_OTGSC_ASVIS_SHIFT
#define USBHS_OTGSC_ASVIS(x)                     USB_OTGSC_ASVIS(x)
#define USBHS_OTGSC_BSVIS_MASK                   USB_OTGSC_BSVIS_MASK
#define USBHS_OTGSC_BSVIS_SHIFT                  USB_OTGSC_BSVIS_SHIFT
#define USBHS_OTGSC_BSVIS(x)                     USB_OTGSC_BSVIS(x)
#define USBHS_OTGSC_BSEIS_MASK                   USB_OTGSC_BSEIS_MASK
#define USBHS_OTGSC_BSEIS_SHIFT                  USB_OTGSC_BSEIS_SHIFT
#define USBHS_OTGSC_BSEIS(x)                     USB_OTGSC_BSEIS(x)
#define USBHS_OTGSC_MSS_MASK                     USB_OTGSC_STATUS_1MS_MASK
#define USBHS_OTGSC_MSS_SHIFT                    USB_OTGSC_STATUS_1MS_SHIFT
#define USBHS_OTGSC_MSS(x)                       USB_OTGSC_STATUS_1MS(x)
#define USBHS_OTGSC_DPIS_MASK                    USB_OTGSC_DPIS_MASK
#define USBHS_OTGSC_DPIS_SHIFT                   USB_OTGSC_DPIS_SHIFT
#define USBHS_OTGSC_DPIS(x)                      USB_OTGSC_DPIS(x)
#define USBHS_OTGSC_IDIE_MASK                    USB_OTGSC_IDIE_MASK
#define USBHS_OTGSC_IDIE_SHIFT                   USB_OTGSC_IDIE_SHIFT
#define USBHS_OTGSC_IDIE(x)                      USB_OTGSC_IDIE(x)
#define USBHS_OTGSC_AVVIE_MASK                   USB_OTGSC_AVVIE_MASK
#define USBHS_OTGSC_AVVIE_SHIFT                  USB_OTGSC_AVVIE_SHIFT
#define USBHS_OTGSC_AVVIE(x)                     USB_OTGSC_AVVIE(x)
#define USBHS_OTGSC_ASVIE_MASK                   USB_OTGSC_ASVIE_MASK
#define USBHS_OTGSC_ASVIE_SHIFT                  USB_OTGSC_ASVIE_SHIFT
#define USBHS_OTGSC_ASVIE(x)                     USB_OTGSC_ASVIE(x)
#define USBHS_OTGSC_BSVIE_MASK                   USB_OTGSC_BSVIE_MASK
#define USBHS_OTGSC_BSVIE_SHIFT                  USB_OTGSC_BSVIE_SHIFT
#define USBHS_OTGSC_BSVIE(x)                     USB_OTGSC_BSVIE(x)
#define USBHS_OTGSC_BSEIE_MASK                   USB_OTGSC_BSEIE_MASK
#define USBHS_OTGSC_BSEIE_SHIFT                  USB_OTGSC_BSEIE_SHIFT
#define USBHS_OTGSC_BSEIE(x)                     USB_OTGSC_BSEIE(x)
#define USBHS_OTGSC_MSE_MASK                     USB_OTGSC_EN_1MS_MASK
#define USBHS_OTGSC_MSE_SHIFT                    USB_OTGSC_EN_1MS_SHIFT
#define USBHS_OTGSC_MSE(x)                       USB_OTGSC_EN_1MS(x)
#define USBHS_OTGSC_DPIE_MASK                    USB_OTGSC_DPIE_MASK
#define USBHS_OTGSC_DPIE_SHIFT                   USB_OTGSC_DPIE_SHIFT
#define USBHS_OTGSC_DPIE(x)                      USB_OTGSC_DPIE(x)
#define USBHS_USBMODE_CM_MASK                    USB_USBMODE_CM_MASK
#define USBHS_USBMODE_CM_SHIFT                   USB_USBMODE_CM_SHIFT
#define USBHS_USBMODE_CM(x)                      USB_USBMODE_CM(x)
#define USBHS_USBMODE_ES_MASK                    USB_USBMODE_ES_MASK
#define USBHS_USBMODE_ES_SHIFT                   USB_USBMODE_ES_SHIFT
#define USBHS_USBMODE_ES(x)                      USB_USBMODE_ES(x)
#define USBHS_USBMODE_SLOM_MASK                  USB_USBMODE_SLOM_MASK
#define USBHS_USBMODE_SLOM_SHIFT                 USB_USBMODE_SLOM_SHIFT
#define USBHS_USBMODE_SLOM(x)                    USB_USBMODE_SLOM(x)
#define USBHS_USBMODE_SDIS_MASK                  USB_USBMODE_SDIS_MASK
#define USBHS_USBMODE_SDIS_SHIFT                 USB_USBMODE_SDIS_SHIFT
#define USBHS_USBMODE_SDIS(x)                    USB_USBMODE_SDIS(x)
#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
#define USBHS_EPSETUPSR_EPSETUPSTAT(x)           USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
#define USBHS_EPPRIME_PERB_MASK                  USB_ENDPTPRIME_PERB_MASK
#define USBHS_EPPRIME_PERB_SHIFT                 USB_ENDPTPRIME_PERB_SHIFT
#define USBHS_EPPRIME_PERB(x)                    USB_ENDPTPRIME_PERB(x)
#define USBHS_EPPRIME_PETB_MASK                  USB_ENDPTPRIME_PETB_MASK
#define USBHS_EPPRIME_PETB_SHIFT                 USB_ENDPTPRIME_PETB_SHIFT
#define USBHS_EPPRIME_PETB(x)                    USB_ENDPTPRIME_PETB(x)
#define USBHS_EPFLUSH_FERB_MASK                  USB_ENDPTFLUSH_FERB_MASK
#define USBHS_EPFLUSH_FERB_SHIFT                 USB_ENDPTFLUSH_FERB_SHIFT
#define USBHS_EPFLUSH_FERB(x)                    USB_ENDPTFLUSH_FERB(x)
#define USBHS_EPFLUSH_FETB_MASK                  USB_ENDPTFLUSH_FETB_MASK
#define USBHS_EPFLUSH_FETB_SHIFT                 USB_ENDPTFLUSH_FETB_SHIFT
#define USBHS_EPFLUSH_FETB(x)                    USB_ENDPTFLUSH_FETB(x)
#define USBHS_EPSR_ERBR_MASK                     USB_ENDPTSTAT_ERBR_MASK
#define USBHS_EPSR_ERBR_SHIFT                    USB_ENDPTSTAT_ERBR_SHIFT
#define USBHS_EPSR_ERBR(x)                       USB_ENDPTSTAT_ERBR(x)
#define USBHS_EPSR_ETBR_MASK                     USB_ENDPTSTAT_ETBR_MASK
#define USBHS_EPSR_ETBR_SHIFT                    USB_ENDPTSTAT_ETBR_SHIFT
#define USBHS_EPSR_ETBR(x)                       USB_ENDPTSTAT_ETBR(x)
#define USBHS_EPCOMPLETE_ERCE_MASK               USB_ENDPTCOMPLETE_ERCE_MASK
#define USBHS_EPCOMPLETE_ERCE_SHIFT              USB_ENDPTCOMPLETE_ERCE_SHIFT
#define USBHS_EPCOMPLETE_ERCE(x)                 USB_ENDPTCOMPLETE_ERCE(x)
#define USBHS_EPCOMPLETE_ETCE_MASK               USB_ENDPTCOMPLETE_ETCE_MASK
#define USBHS_EPCOMPLETE_ETCE_SHIFT              USB_ENDPTCOMPLETE_ETCE_SHIFT
#define USBHS_EPCOMPLETE_ETCE(x)                 USB_ENDPTCOMPLETE_ETCE(x)
#define USBHS_EPCR0_RXS_MASK                     USB_ENDPTCTRL0_RXS_MASK
#define USBHS_EPCR0_RXS_SHIFT                    USB_ENDPTCTRL0_RXS_SHIFT
#define USBHS_EPCR0_RXS(x)                       USB_ENDPTCTRL0_RXS(x)
#define USBHS_EPCR0_RXT_MASK                     USB_ENDPTCTRL0_RXT_MASK
#define USBHS_EPCR0_RXT_SHIFT                    USB_ENDPTCTRL0_RXT_SHIFT
#define USBHS_EPCR0_RXT(x)                       USB_ENDPTCTRL0_RXT(x)
#define USBHS_EPCR0_RXE_MASK                     USB_ENDPTCTRL0_RXE_MASK
#define USBHS_EPCR0_RXE_SHIFT                    USB_ENDPTCTRL0_RXE_SHIFT
#define USBHS_EPCR0_RXE(x)                       USB_ENDPTCTRL0_RXE(x)
#define USBHS_EPCR0_TXS_MASK                     USB_ENDPTCTRL0_TXS_MASK
#define USBHS_EPCR0_TXS_SHIFT                    USB_ENDPTCTRL0_TXS_SHIFT
#define USBHS_EPCR0_TXS(x)                       USB_ENDPTCTRL0_TXS(x)
#define USBHS_EPCR0_TXT_MASK                     USB_ENDPTCTRL0_TXT_MASK
#define USBHS_EPCR0_TXT_SHIFT                    USB_ENDPTCTRL0_TXT_SHIFT
#define USBHS_EPCR0_TXT(x)                       USB_ENDPTCTRL0_TXT(x)
#define USBHS_EPCR0_TXE_MASK                     USB_ENDPTCTRL0_TXE_MASK
#define USBHS_EPCR0_TXE_SHIFT                    USB_ENDPTCTRL0_TXE_SHIFT
#define USBHS_EPCR0_TXE(x)                       USB_ENDPTCTRL0_TXE(x)
#define USBHS_EPCR_RXS_MASK                      USB_ENDPTCTRL_RXS_MASK
#define USBHS_EPCR_RXS_SHIFT                     USB_ENDPTCTRL_RXS_SHIFT
#define USBHS_EPCR_RXS(x)                        USB_ENDPTCTRL_RXS(x)
#define USBHS_EPCR_RXD_MASK                      USB_ENDPTCTRL_RXD_MASK
#define USBHS_EPCR_RXD_SHIFT                     USB_ENDPTCTRL_RXD_SHIFT
#define USBHS_EPCR_RXD(x)                        USB_ENDPTCTRL_RXD(x)
#define USBHS_EPCR_RXT_MASK                      USB_ENDPTCTRL_RXT_MASK
#define USBHS_EPCR_RXT_SHIFT                     USB_ENDPTCTRL_RXT_SHIFT
#define USBHS_EPCR_RXT(x)                        USB_ENDPTCTRL_RXT(x)
#define USBHS_EPCR_RXI_MASK                      USB_ENDPTCTRL_RXI_MASK
#define USBHS_EPCR_RXI_SHIFT                     USB_ENDPTCTRL_RXI_SHIFT
#define USBHS_EPCR_RXI(x)                        USB_ENDPTCTRL_RXI(x)
#define USBHS_EPCR_RXR_MASK                      USB_ENDPTCTRL_RXR_MASK
#define USBHS_EPCR_RXR_SHIFT                     USB_ENDPTCTRL_RXR_SHIFT
#define USBHS_EPCR_RXR(x)                        USB_ENDPTCTRL_RXR(x)
#define USBHS_EPCR_RXE_MASK                      USB_ENDPTCTRL_RXE_MASK
#define USBHS_EPCR_RXE_SHIFT                     USB_ENDPTCTRL_RXE_SHIFT
#define USBHS_EPCR_RXE(x)                        USB_ENDPTCTRL_RXE(x)
#define USBHS_EPCR_TXS_MASK                      USB_ENDPTCTRL_TXS_MASK
#define USBHS_EPCR_TXS_SHIFT                     USB_ENDPTCTRL_TXS_SHIFT
#define USBHS_EPCR_TXS(x)                        USB_ENDPTCTRL_TXS(x)
#define USBHS_EPCR_TXD_MASK                      USB_ENDPTCTRL_TXD_MASK
#define USBHS_EPCR_TXD_SHIFT                     USB_ENDPTCTRL_TXD_SHIFT
#define USBHS_EPCR_TXD(x)                        USB_ENDPTCTRL_TXD(x)
#define USBHS_EPCR_TXT_MASK                      USB_ENDPTCTRL_TXT_MASK
#define USBHS_EPCR_TXT_SHIFT                     USB_ENDPTCTRL_TXT_SHIFT
#define USBHS_EPCR_TXT(x)                        USB_ENDPTCTRL_TXT(x)
#define USBHS_EPCR_TXI_MASK                      USB_ENDPTCTRL_TXI_MASK
#define USBHS_EPCR_TXI_SHIFT                     USB_ENDPTCTRL_TXI_SHIFT
#define USBHS_EPCR_TXI(x)                        USB_ENDPTCTRL_TXI(x)
#define USBHS_EPCR_TXR_MASK                      USB_ENDPTCTRL_TXR_MASK
#define USBHS_EPCR_TXR_SHIFT                     USB_ENDPTCTRL_TXR_SHIFT
#define USBHS_EPCR_TXR(x)                        USB_ENDPTCTRL_TXR(x)
#define USBHS_EPCR_TXE_MASK                      USB_ENDPTCTRL_TXE_MASK
#define USBHS_EPCR_TXE_SHIFT                     USB_ENDPTCTRL_TXE_SHIFT
#define USBHS_EPCR_TXE(x)                        USB_ENDPTCTRL_TXE(x)
#define USBHS_EPCR_COUNT                         USB_ENDPTCTRL_COUNT
#define USBHS_Type                               USB_Type
#define USBHS_BASE_ADDRS                         USB_BASE_ADDRS
#define USBHS_IRQS                               USB_IRQS
#define USBHS_IRQHandler                         USB0_IRQHandler


/*!
 * @}
 */ /* end of group USB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBHSDCD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
 * @{
 */

/** USBHSDCD - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
  __IO uint32_t CLOCK;                             /**< Clock, offset: 0x4 */
  __I  uint32_t STATUS;                            /**< Status, offset: 0x8 */
  __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override, offset: 0xC */
  __IO uint32_t TIMER0;                            /**< TIMER0, offset: 0x10 */
  __IO uint32_t TIMER1;                            /**< TIMER1, offset: 0x14 */
  union {                                          /* offset: 0x18 */
    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11, offset: 0x18 */
    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12, offset: 0x18 */
  };
} USBHSDCD_Type;

/* ----------------------------------------------------------------------------
   -- USBHSDCD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
 * @{
 */

/*! @name CONTROL - Control */
/*! @{ */

#define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
#define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
/*! IACK - Interrupt Acknowledge
 *  0b0..Do not clear the interrupt.
 *  0b1..Clear the IF field (interrupt flag).
 */
#define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)

#define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
#define USBHSDCD_CONTROL_IF_SHIFT                (8U)
/*! IF - Interrupt Flag
 *  0b0..No interrupt is pending.
 *  0b1..An interrupt is pending.
 */
#define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)

#define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
#define USBHSDCD_CONTROL_IE_SHIFT                (16U)
/*! IE - Interrupt Enable
 *  0b0..Disable interrupts to the system.
 *  0b1..Enable interrupts to the system.
 */
#define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)

#define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
#define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
/*! BC12 - Battery Charging Revision 1.2 Compatibility
 *  0b0..Compatible with BC1.1 (default)
 *  0b1..Compatible with BC1.2
 */
#define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)

#define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
#define USBHSDCD_CONTROL_START_SHIFT             (24U)
/*! START - Start Change Detection Sequence
 *  0b0..Do not start the sequence. Writes of this value have no effect.
 *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
 */
#define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)

#define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
#define USBHSDCD_CONTROL_SR_SHIFT                (25U)
/*! SR - Software Reset
 *  0b0..Do not perform a software reset.
 *  0b1..Perform a software reset.
 */
#define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
/*! @} */

/*! @name CLOCK - Clock */
/*! @{ */

#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
 *  0b0..kHz Speed (between 4 kHz and 1023 kHz)
 *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
 */
#define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)

#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
/*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */
#define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
/*! @} */

/*! @name STATUS - Status */
/*! @{ */

#define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
#define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
/*! SEQ_RES - Charger Detection Sequence Results
 *  0b00..No results to report.
 *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
 *  0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached
 *        to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The
 *        charger type detection has completed.)
 *  0b11..Attached to a DCP.
 */
#define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)

#define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
#define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
/*! SEQ_STAT - Charger Detection Sequence Status
 *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
 *  0b01..Data pin contact detection is complete.
 *  0b10..Charging port detection is complete.
 *  0b11..Charger type detection is complete.
 */
#define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)

#define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
#define USBHSDCD_STATUS_ERR_SHIFT                (20U)
/*! ERR - Error Flag
 *  0b0..No sequence errors.
 *  0b1..Error in the detection sequence.
 */
#define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)

#define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
#define USBHSDCD_STATUS_TO_SHIFT                 (21U)
/*! TO - Timeout Flag
 *  0b0..The detection sequence is not running for over 1 s.
 *  0b1..It is over 1 s since the data pin contact was detected and debounced.
 */
#define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)

#define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
#define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
/*! ACTIVE - Active Status Indicator
 *  0b0..The sequence is not running.
 *  0b1..The sequence is running.
 */
#define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
/*! @} */

/*! @name SIGNAL_OVERRIDE - Signal Override */
/*! @{ */

#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
/*! PS - Phase Selection
 *  0b00..No overrides. Field must remain at this value during normal USB data communication to prevent unexpected
 *        conditions on USB_DP and USB_DM pins. (Default)
 *  0b01..Reserved, not for customer use.
 *  0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
 *  0b11..Reserved, not for customer use.
 */
#define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
/*! @} */

/*! @name TIMER0 - TIMER0 */
/*! @{ */

#define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
#define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
/*! TUNITCON - Unit Connection Timer Elapse (in ms) */
#define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)

#define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
/*! TSEQ_INIT - Sequence Initiation Time
 *  0b0000000000-0b1111111111..0 ms - 1023 ms
 */
#define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
/*! @} */

/*! @name TIMER1 - TIMER1 */
/*! @{ */

#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
/*! TVDPSRC_ON - Time Period Comparator Enabled
 *  0b0000000001-0b1111111111..1 ms - 1023 ms
 */
#define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)

#define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
/*! TDCD_DBNC - Time Period to Debounce D+ Signal
 *  0b0000000001-0b1111111111..1 ms - 1023 ms
 */
#define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
/*! @} */

/*! @name TIMER2_BC11 - TIMER2_BC11 */
/*! @{ */

#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
/*! CHECK_DM - Time Before Check of D- Line
 *  0b0001-0b1111..1 ms - 15 ms
 */
#define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)

#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
/*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
 *  0b0000000001-0b1111111111..1 ms - 1023 ms
 */
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
/*! @} */

/*! @name TIMER2_BC12 - TIMER2_BC12 */
/*! @{ */

#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
/*! TVDMSRC_ON - TVDMSRC_ON
 *  0b0000000000-0b0000101000..0 ms - 40 ms
 */
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)

#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
/*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
 *  0b0000000001-0b1111111111..1 ms - 1023 ms
 */
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBHSDCD_Register_Masks */


/* USBHSDCD - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral USBDCD base address */
  #define USBDCD_BASE                              (0x50414800u)
  /** Peripheral USBDCD base address */
  #define USBDCD_BASE_NS                           (0x40414800u)
  /** Peripheral USBDCD base pointer */
  #define USBDCD                                   ((USBHSDCD_Type *)USBDCD_BASE)
  /** Peripheral USBDCD base pointer */
  #define USBDCD_NS                                ((USBHSDCD_Type *)USBDCD_BASE_NS)
  /** Array initializer of USBHSDCD peripheral base addresses */
  #define USBHSDCD_BASE_ADDRS                      { USBDCD_BASE }
  /** Array initializer of USBHSDCD peripheral base pointers */
  #define USBHSDCD_BASE_PTRS                       { USBDCD }
  /** Array initializer of USBHSDCD peripheral base addresses */
  #define USBHSDCD_BASE_ADDRS_NS                   { USBDCD_BASE_NS }
  /** Array initializer of USBHSDCD peripheral base pointers */
  #define USBHSDCD_BASE_PTRS_NS                    { USBDCD_NS }
#else
  /** Peripheral USBDCD base address */
  #define USBDCD_BASE                              (0x40414800u)
  /** Peripheral USBDCD base pointer */
  #define USBDCD                                   ((USBHSDCD_Type *)USBDCD_BASE)
  /** Array initializer of USBHSDCD peripheral base addresses */
  #define USBHSDCD_BASE_ADDRS                      { USBDCD_BASE }
  /** Array initializer of USBHSDCD peripheral base pointers */
  #define USBHSDCD_BASE_PTRS                       { USBDCD }
#endif

/*!
 * @}
 */ /* end of group USBHSDCD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBNC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
 * @{
 */

/** USBNC - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL1;                             /**< USB Control 1, offset: 0x0 */
  __IO uint32_t CTRL2;                             /**< USB Control 2, offset: 0x4 */
       uint8_t RESERVED_0[152];
  __IO uint32_t LPM_CSR0;                          /**< USB LPM Control and Status 0, offset: 0xA0 */
  __IO uint32_t LPM_CSR1;                          /**< USB LPM Control and Status 1, offset: 0xA4 */
  __IO uint32_t LPM_CSR2;                          /**< USB LPM Control and Status 2, offset: 0xA8 */
       uint8_t RESERVED_1[84];
  __IO uint32_t EUSB_CTRL0;                        /**< eUSB Control 0, offset: 0x100, available only on: USBNC1 (missing on USBNC0) */
       uint8_t RESERVED_2[68];
  __IO uint32_t EUSB_RAP;                          /**< eUSB RAP Control and Status, offset: 0x148, available only on: USBNC1 (missing on USBNC0) */
} USBNC_Type;

/* ----------------------------------------------------------------------------
   -- USBNC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBNC_Register_Masks USBNC Register Masks
 * @{
 */

/*! @name CTRL1 - USB Control 1 */
/*! @{ */

#define USBNC_CTRL1_OVER_CUR_DIS_MASK            (0x80U)
#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT           (7U)
/*! OVER_CUR_DIS - Overcurrent Disable
 *  0b1..Disable
 *  0b0..Enable
 */
#define USBNC_CTRL1_OVER_CUR_DIS(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)

#define USBNC_CTRL1_OVER_CUR_POL_MASK            (0x100U)
#define USBNC_CTRL1_OVER_CUR_POL_SHIFT           (8U)
/*! OVER_CUR_POL - Overcurrent Polarity
 *  0b1..Active low
 *  0b0..Active high
 */
#define USBNC_CTRL1_OVER_CUR_POL(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)

#define USBNC_CTRL1_PWR_POL_MASK                 (0x200U)
#define USBNC_CTRL1_PWR_POL_SHIFT                (9U)
/*! PWR_POL - Power Polarity
 *  0b1..Active high
 *  0b0..Active low
 */
#define USBNC_CTRL1_PWR_POL(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)

#define USBNC_CTRL1_WIE_MASK                     (0x400U)
#define USBNC_CTRL1_WIE_SHIFT                    (10U)
/*! WIE - Wake-Up Interrupt Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_CTRL1_WIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)

#define USBNC_CTRL1_WKUP_SW_EN_MASK              (0x4000U)
#define USBNC_CTRL1_WKUP_SW_EN_SHIFT             (14U)
/*! WKUP_SW_EN - Software Wake-Up Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_CTRL1_WKUP_SW_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)

#define USBNC_CTRL1_WKUP_SW_MASK                 (0x8000U)
#define USBNC_CTRL1_WKUP_SW_SHIFT                (15U)
/*! WKUP_SW - Software Wake-Up
 *  0b1..Force wake-up
 *  0b0..Inactive
 */
#define USBNC_CTRL1_WKUP_SW(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)

#define USBNC_CTRL1_WKUP_VBUS_EN_MASK            (0x20000U)
#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT           (17U)
/*! WKUP_VBUS_EN - Wake-Up After VBUS Change Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_CTRL1_WKUP_VBUS_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)

#define USBNC_CTRL1_REMOTE_WAKEUP_EN_MASK        (0x10000000U)
#define USBNC_CTRL1_REMOTE_WAKEUP_EN_SHIFT       (28U)
/*! REMOTE_WAKEUP_EN - Remote Wake-Up Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_CTRL1_REMOTE_WAKEUP_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_REMOTE_WAKEUP_EN_SHIFT)) & USBNC_CTRL1_REMOTE_WAKEUP_EN_MASK)

#define USBNC_CTRL1_WKUP_DPDM_EN_MASK            (0x20000000U)
#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT           (29U)
/*! WKUP_DPDM_EN - Wake-Up After DP or DM Change Enable
 *  0b1..Enable (default)
 *  0b0..Disable only when VBUS is invalid
 */
#define USBNC_CTRL1_WKUP_DPDM_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)

#define USBNC_CTRL1_WIR_MASK                     (0x80000000U)
#define USBNC_CTRL1_WIR_SHIFT                    (31U)
/*! WIR - Wake-Up Interrupt Request
 *  0b1..Received
 *  0b0..Not received
 */
#define USBNC_CTRL1_WIR(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
/*! @} */

/*! @name CTRL2 - USB Control 2 */
/*! @{ */

#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK         (0x3U)
#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT        (0U)
/*! VBUS_SOURCE_SEL - VBUS Source Select
 *  0b00..vbus_valid
 *  0b01..sess_valid
 *  0b10..sess_valid
 *  0b11..sess_valid
 */
#define USBNC_CTRL2_VBUS_SOURCE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)

#define USBNC_CTRL2_UTMI_CLK_VLD_MASK            (0x80000000U)
#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT           (31U)
/*! UTMI_CLK_VLD - UTMI Clock Valid Flag
 *  0b0..Not valid
 *  0b1..Valid
 *  0b0..No effect
 *  0b1..Clear the flag
 */
#define USBNC_CTRL2_UTMI_CLK_VLD(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
/*! @} */

/*! @name LPM_CSR0 - USB LPM Control and Status 0 */
/*! @{ */

#define USBNC_LPM_CSR0_LPM_EN_MASK               (0x1U)
#define USBNC_LPM_CSR0_LPM_EN_SHIFT              (0U)
/*! LPM_EN - Link Power Management Feature Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_LPM_CSR0_LPM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR0_LPM_EN_SHIFT)) & USBNC_LPM_CSR0_LPM_EN_MASK)

#define USBNC_LPM_CSR0_LPM_ERRATA_EN_MASK        (0x2U)
#define USBNC_LPM_CSR0_LPM_ERRATA_EN_SHIFT       (1U)
/*! LPM_ERRATA_EN - Link Power Management ECN Errata Feature Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_LPM_CSR0_LPM_ERRATA_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR0_LPM_ERRATA_EN_SHIFT)) & USBNC_LPM_CSR0_LPM_ERRATA_EN_MASK)

#define USBNC_LPM_CSR0_LPM_AUTO_PHCD_MASK        (0x8U)
#define USBNC_LPM_CSR0_LPM_AUTO_PHCD_SHIFT       (3U)
/*! LPM_AUTO_PHCD - Auto Low-Power Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_LPM_CSR0_LPM_AUTO_PHCD(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR0_LPM_AUTO_PHCD_SHIFT)) & USBNC_LPM_CSR0_LPM_AUTO_PHCD_MASK)

#define USBNC_LPM_CSR0_LPM_RESUMEOK_MASK         (0x40000000U)
#define USBNC_LPM_CSR0_LPM_RESUMEOK_SHIFT        (30U)
/*! LPM_RESUMEOK - LPM Resume OK
 *  0b1..Can resume
 *  0b0..Cannot resume
 */
#define USBNC_LPM_CSR0_LPM_RESUMEOK(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR0_LPM_RESUMEOK_SHIFT)) & USBNC_LPM_CSR0_LPM_RESUMEOK_MASK)

#define USBNC_LPM_CSR0_LPM_L1_ACTIVE_MASK        (0x80000000U)
#define USBNC_LPM_CSR0_LPM_L1_ACTIVE_SHIFT       (31U)
/*! LPM_L1_ACTIVE - LPM Active
 *  0b1..Active
 *  0b0..Inactive
 */
#define USBNC_LPM_CSR0_LPM_L1_ACTIVE(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR0_LPM_L1_ACTIVE_SHIFT)) & USBNC_LPM_CSR0_LPM_L1_ACTIVE_MASK)
/*! @} */

/*! @name LPM_CSR1 - USB LPM Control and Status 1 */
/*! @{ */

#define USBNC_LPM_CSR1_LPM_DEV_BESLTHRES_MASK    (0xFU)
#define USBNC_LPM_CSR1_LPM_DEV_BESLTHRES_SHIFT   (0U)
/*! LPM_DEV_BESLTHRES - Device Required Host Initiated Resume Duration
 *  0b0000..75 us, if LPM_ERRATA_EN = 1; 50 us, if LPM_ERRATA_EN = 0
 *  0b0001..100 us, if LPM_ERRATA_EN = 1; 125 us, if LPM_ERRATA_EN = 0
 *  0b0010..150 us, if LPM_ERRATA_EN = 1; 200 us, if LPM_ERRATA_EN = 0
 *  0b0011..250 us, if LPM_ERRATA_EN = 1; 275 us, if LPM_ERRATA_EN = 0
 *  0b0100..350 us, if LPM_ERRATA_EN = 1; 350 us, if LPM_ERRATA_EN = 0
 *  0b0101..450 us, if LPM_ERRATA_EN = 1; 425 us, if LPM_ERRATA_EN = 0
 *  0b0110..950 us, if LPM_ERRATA_EN = 1; 500 us, if LPM_ERRATA_EN = 0
 *  0b0111..1950 us, if LPM_ERRATA_EN = 1; 575 us, if LPM_ERRATA_EN = 0
 *  0b1000..2950 us, if LPM_ERRATA_EN = 1; 650 us, if LPM_ERRATA_EN = 0
 *  0b1001..3950 us, if LPM_ERRATA_EN = 1; 725 us, if LPM_ERRATA_EN = 0
 *  0b1010..4950 us, if LPM_ERRATA_EN = 1; 800 us, if LPM_ERRATA_EN = 0
 *  0b1011..5950 us, if LPM_ERRATA_EN = 1; 875 us, if LPM_ERRATA_EN = 0
 *  0b1100..6950 us, if LPM_ERRATA_EN = 1; 950 us, if LPM_ERRATA_EN = 0
 *  0b1101..7950 us, if LPM_ERRATA_EN = 1; 1025 us, if LPM_ERRATA_EN = 0
 *  0b1110..8950 us, if LPM_ERRATA_EN = 1; 1100 us, if LPM_ERRATA_EN = 0
 *  0b1111..9950 us, if LPM_ERRATA_EN = 1; 1175 us, if LPM_ERRATA_EN = 0
 */
#define USBNC_LPM_CSR1_LPM_DEV_BESLTHRES(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR1_LPM_DEV_BESLTHRES_SHIFT)) & USBNC_LPM_CSR1_LPM_DEV_BESLTHRES_MASK)

#define USBNC_LPM_CSR1_LPM_DEV_RES_MASK          (0x10U)
#define USBNC_LPM_CSR1_LPM_DEV_RES_SHIFT         (4U)
/*! LPM_DEV_RES - LPM Device Response
 *  0b1..Fourth condition needed
 *  0b0..Fourth condition not needed
 */
#define USBNC_LPM_CSR1_LPM_DEV_RES(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR1_LPM_DEV_RES_SHIFT)) & USBNC_LPM_CSR1_LPM_DEV_RES_MASK)

#define USBNC_LPM_CSR1_LPM_DEV_DP_MASK           (0x20U)
#define USBNC_LPM_CSR1_LPM_DEV_DP_SHIFT          (5U)
/*! LPM_DEV_DP - LPM Device Data Pending
 *  0b1..Pending
 *  0b0..Not pending
 */
#define USBNC_LPM_CSR1_LPM_DEV_DP(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR1_LPM_DEV_DP_SHIFT)) & USBNC_LPM_CSR1_LPM_DEV_DP_MASK)

#define USBNC_LPM_CSR1_LPM_DEV_RSPSTS_MASK       (0x300000U)
#define USBNC_LPM_CSR1_LPM_DEV_RSPSTS_SHIFT      (20U)
/*! LPM_DEV_RSPSTS - LPM Device Response Status
 *  0b00..Invalid
 *  0b01..ACK
 *  0b10..NYET
 *  0b11..STALL
 */
#define USBNC_LPM_CSR1_LPM_DEV_RSPSTS(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR1_LPM_DEV_RSPSTS_SHIFT)) & USBNC_LPM_CSR1_LPM_DEV_RSPSTS_MASK)

#define USBNC_LPM_CSR1_LPM_DEV_RWKENRCVD_MASK    (0x800000U)
#define USBNC_LPM_CSR1_LPM_DEV_RWKENRCVD_SHIFT   (23U)
/*! LPM_DEV_RWKENRCVD - LPM Device Received bRemoteWake
 *  0b1..1
 *  0b0..0
 */
#define USBNC_LPM_CSR1_LPM_DEV_RWKENRCVD(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR1_LPM_DEV_RWKENRCVD_SHIFT)) & USBNC_LPM_CSR1_LPM_DEV_RWKENRCVD_MASK)

#define USBNC_LPM_CSR1_LPM_DEV_LNKSTRCVD_MASK    (0xF000000U)
#define USBNC_LPM_CSR1_LPM_DEV_LNKSTRCVD_SHIFT   (24U)
/*! LPM_DEV_LNKSTRCVD - LPM Device Received bLinkState
 *  0b0000..Reserved for future use
 *  0b0001..L1 (Sleep mode)
 *  0b0010-0b1111..Reserved for future use
 */
#define USBNC_LPM_CSR1_LPM_DEV_LNKSTRCVD(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR1_LPM_DEV_LNKSTRCVD_SHIFT)) & USBNC_LPM_CSR1_LPM_DEV_LNKSTRCVD_MASK)

#define USBNC_LPM_CSR1_LPM_DEV_BESLRCVD_MASK     (0xF0000000U)
#define USBNC_LPM_CSR1_LPM_DEV_BESLRCVD_SHIFT    (28U)
/*! LPM_DEV_BESLRCVD - LPM Device Received BESL */
#define USBNC_LPM_CSR1_LPM_DEV_BESLRCVD(x)       (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR1_LPM_DEV_BESLRCVD_SHIFT)) & USBNC_LPM_CSR1_LPM_DEV_BESLRCVD_MASK)
/*! @} */

/*! @name LPM_CSR2 - USB LPM Control and Status 2 */
/*! @{ */

#define USBNC_LPM_CSR2_LPM_HST_SEND_MASK         (0x1U)
#define USBNC_LPM_CSR2_LPM_HST_SEND_SHIFT        (0U)
/*! LPM_HST_SEND - LPM Host Send Extension Token
 *  0b0..LPM transaction did not happen or is complete
 *  0b1..LPM transaction is ongoing
 */
#define USBNC_LPM_CSR2_LPM_HST_SEND(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR2_LPM_HST_SEND_SHIFT)) & USBNC_LPM_CSR2_LPM_HST_SEND_MASK)

#define USBNC_LPM_CSR2_LPM_HST_DEVADD_MASK       (0xFEU)
#define USBNC_LPM_CSR2_LPM_HST_DEVADD_SHIFT      (1U)
/*! LPM_HST_DEVADD - LPM Host Extension Token's Device Address */
#define USBNC_LPM_CSR2_LPM_HST_DEVADD(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR2_LPM_HST_DEVADD_SHIFT)) & USBNC_LPM_CSR2_LPM_HST_DEVADD_MASK)

#define USBNC_LPM_CSR2_LPM_HST_BESL_MASK         (0xF00U)
#define USBNC_LPM_CSR2_LPM_HST_BESL_SHIFT        (8U)
/*! LPM_HST_BESL - LPM Host Extension Token's BESL or HIRD */
#define USBNC_LPM_CSR2_LPM_HST_BESL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR2_LPM_HST_BESL_SHIFT)) & USBNC_LPM_CSR2_LPM_HST_BESL_MASK)

#define USBNC_LPM_CSR2_LPM_HST_RWKEN_MASK        (0x1000U)
#define USBNC_LPM_CSR2_LPM_HST_RWKEN_SHIFT       (12U)
/*! LPM_HST_RWKEN - LPM Host Extension Token's bRemoteWake
 *  0b0..Disable
 *  0b1..Enable
 */
#define USBNC_LPM_CSR2_LPM_HST_RWKEN(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR2_LPM_HST_RWKEN_SHIFT)) & USBNC_LPM_CSR2_LPM_HST_RWKEN_MASK)

#define USBNC_LPM_CSR2_LPM_HST_STSRCVD_MASK      (0x70000000U)
#define USBNC_LPM_CSR2_LPM_HST_STSRCVD_SHIFT     (28U)
/*! LPM_HST_STSRCVD - LPM Host Response Status from the Device
 *  0b000..Invalid
 *  0b001..ACK
 *  0b010..NYET
 *  0b011..STALL
 *  0b100..Timeout
 *  0b101..ERR
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define USBNC_LPM_CSR2_LPM_HST_STSRCVD(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_LPM_CSR2_LPM_HST_STSRCVD_SHIFT)) & USBNC_LPM_CSR2_LPM_HST_STSRCVD_MASK)
/*! @} */

/*! @name EUSB_CTRL0 - eUSB Control 0 */
/*! @{ */

#define USBNC_EUSB_CTRL0_UN_TERMINATED_MODE_MASK (0x20U)
#define USBNC_EUSB_CTRL0_UN_TERMINATED_MODE_SHIFT (5U)
/*! UN_TERMINATED_MODE - HS Receiver Termination Option
 *  0b0..Enable
 *  0b1..Disable
 */
#define USBNC_EUSB_CTRL0_UN_TERMINATED_MODE(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_CTRL0_UN_TERMINATED_MODE_SHIFT)) & USBNC_EUSB_CTRL0_UN_TERMINATED_MODE_MASK)

#define USBNC_EUSB_CTRL0_PONRST_MASK             (0x40U)
#define USBNC_EUSB_CTRL0_PONRST_SHIFT            (6U)
/*! PONRST - Power-On Reset
 *  0b0..Reset
 *  0b1..Operate normally
 */
#define USBNC_EUSB_CTRL0_PONRST(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_CTRL0_PONRST_SHIFT)) & USBNC_EUSB_CTRL0_PONRST_MASK)

#define USBNC_EUSB_CTRL0_NATIVE_MODE_MASK        (0x80U)
#define USBNC_EUSB_CTRL0_NATIVE_MODE_SHIFT       (7U)
/*! NATIVE_MODE - Mode Select
 *  0b0..Repeater mode
 *  0b1..Native mode
 */
#define USBNC_EUSB_CTRL0_NATIVE_MODE(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_CTRL0_NATIVE_MODE_SHIFT)) & USBNC_EUSB_CTRL0_NATIVE_MODE_MASK)

#define USBNC_EUSB_CTRL0_EUSB_DEV_PORT_RST_MASK  (0x1000000U)
#define USBNC_EUSB_CTRL0_EUSB_DEV_PORT_RST_SHIFT (24U)
/*! EUSB_DEV_PORT_RST - Trigger Device Issue Port Reset
 *  0b0..No action
 *  0b1..Trigger device issue port reset
 */
#define USBNC_EUSB_CTRL0_EUSB_DEV_PORT_RST(x)    (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_CTRL0_EUSB_DEV_PORT_RST_SHIFT)) & USBNC_EUSB_CTRL0_EUSB_DEV_PORT_RST_MASK)
/*! @} */

/*! @name EUSB_RAP - eUSB RAP Control and Status */
/*! @{ */

#define USBNC_EUSB_RAP_CM_RAP_WRDATA_MASK        (0xFFU)
#define USBNC_EUSB_RAP_CM_RAP_WRDATA_SHIFT       (0U)
/*! CM_RAP_WRDATA - CM.RAP Write Data */
#define USBNC_EUSB_RAP_CM_RAP_WRDATA(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_WRDATA_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_WRDATA_MASK)

#define USBNC_EUSB_RAP_CM_RAP_ADDR_MASK          (0x3F00U)
#define USBNC_EUSB_RAP_CM_RAP_ADDR_SHIFT         (8U)
/*! CM_RAP_ADDR - CM.RAP Address */
#define USBNC_EUSB_RAP_CM_RAP_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_ADDR_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_ADDR_MASK)

#define USBNC_EUSB_RAP_CM_RAP_OP_MASK            (0xC000U)
#define USBNC_EUSB_RAP_CM_RAP_OP_SHIFT           (14U)
/*! CM_RAP_OP - CM.RAP Operation Code
 *  0b00..Write; data is written to the register address
 *  0b01..Read; data is read from the register address
 *  0b10..Clear; active-high, bitwise clear with the data on the register address
 *  0b11..Set; bitwise OR with the data on the register address
 */
#define USBNC_EUSB_RAP_CM_RAP_OP(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_OP_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_OP_MASK)

#define USBNC_EUSB_RAP_CM_RAP_INIT_EN_MASK       (0x10000U)
#define USBNC_EUSB_RAP_CM_RAP_INIT_EN_SHIFT      (16U)
/*! CM_RAP_INIT_EN - Enable CM.RAP Feature
 *  0b0..Disable
 *  0b1..Enable
 */
#define USBNC_EUSB_RAP_CM_RAP_INIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_INIT_EN_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_INIT_EN_MASK)

#define USBNC_EUSB_RAP_CM_RAP_START_MASK         (0x20000U)
#define USBNC_EUSB_RAP_CM_RAP_START_SHIFT        (17U)
/*! CM_RAP_START - CM.RAP Start
 *  0b0..Disable
 *  0b1..Enable
 */
#define USBNC_EUSB_RAP_CM_RAP_START(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_START_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_START_MASK)

#define USBNC_EUSB_RAP_CM_RAP_FAIL_MASK          (0x200000U)
#define USBNC_EUSB_RAP_CM_RAP_FAIL_SHIFT         (21U)
/*! CM_RAP_FAIL - CM.RAP Command Fail
 *  0b0..Not failed
 *  0b1..Failed
 */
#define USBNC_EUSB_RAP_CM_RAP_FAIL(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_FAIL_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_FAIL_MASK)

#define USBNC_EUSB_RAP_CM_RAP_DONE_MASK          (0x400000U)
#define USBNC_EUSB_RAP_CM_RAP_DONE_SHIFT         (22U)
/*! CM_RAP_DONE - CM.RAP Command Done
 *  0b0..Not complete
 *  0b1..Complete
 */
#define USBNC_EUSB_RAP_CM_RAP_DONE(x)            (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_DONE_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_DONE_MASK)

#define USBNC_EUSB_RAP_CM_RAP_INIT_READY_MASK    (0x800000U)
#define USBNC_EUSB_RAP_CM_RAP_INIT_READY_SHIFT   (23U)
/*! CM_RAP_INIT_READY - Host and Device Entering CM.RAP State
 *  0b0..Not ready
 *  0b1..Ready
 */
#define USBNC_EUSB_RAP_CM_RAP_INIT_READY(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_INIT_READY_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_INIT_READY_MASK)

#define USBNC_EUSB_RAP_CM_RAP_RDDATA_MASK        (0xFF000000U)
#define USBNC_EUSB_RAP_CM_RAP_RDDATA_SHIFT       (24U)
/*! CM_RAP_RDDATA - CM.RAP Read Data */
#define USBNC_EUSB_RAP_CM_RAP_RDDATA(x)          (((uint32_t)(((uint32_t)(x)) << USBNC_EUSB_RAP_CM_RAP_RDDATA_SHIFT)) & USBNC_EUSB_RAP_CM_RAP_RDDATA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBNC_Register_Masks */


/* USBNC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral USBNC0 base address */
  #define USBNC0_BASE                              (0x50418200u)
  /** Peripheral USBNC0 base address */
  #define USBNC0_BASE_NS                           (0x40418200u)
  /** Peripheral USBNC0 base pointer */
  #define USBNC0                                   ((USBNC_Type *)USBNC0_BASE)
  /** Peripheral USBNC0 base pointer */
  #define USBNC0_NS                                ((USBNC_Type *)USBNC0_BASE_NS)
  /** Peripheral USBNC1 base address */
  #define USBNC1_BASE                              (0x50419200u)
  /** Peripheral USBNC1 base address */
  #define USBNC1_BASE_NS                           (0x40419200u)
  /** Peripheral USBNC1 base pointer */
  #define USBNC1                                   ((USBNC_Type *)USBNC1_BASE)
  /** Peripheral USBNC1 base pointer */
  #define USBNC1_NS                                ((USBNC_Type *)USBNC1_BASE_NS)
  /** Array initializer of USBNC peripheral base addresses */
  #define USBNC_BASE_ADDRS                         { USBNC0_BASE, USBNC1_BASE }
  /** Array initializer of USBNC peripheral base pointers */
  #define USBNC_BASE_PTRS                          { USBNC0, USBNC1 }
  /** Array initializer of USBNC peripheral base addresses */
  #define USBNC_BASE_ADDRS_NS                      { USBNC0_BASE_NS, USBNC1_BASE_NS }
  /** Array initializer of USBNC peripheral base pointers */
  #define USBNC_BASE_PTRS_NS                       { USBNC0_NS, USBNC1_NS }
#else
  /** Peripheral USBNC0 base address */
  #define USBNC0_BASE                              (0x40418200u)
  /** Peripheral USBNC0 base pointer */
  #define USBNC0                                   ((USBNC_Type *)USBNC0_BASE)
  /** Peripheral USBNC1 base address */
  #define USBNC1_BASE                              (0x40419200u)
  /** Peripheral USBNC1 base pointer */
  #define USBNC1                                   ((USBNC_Type *)USBNC1_BASE)
  /** Array initializer of USBNC peripheral base addresses */
  #define USBNC_BASE_ADDRS                         { USBNC0_BASE, USBNC1_BASE }
  /** Array initializer of USBNC peripheral base pointers */
  #define USBNC_BASE_PTRS                          { USBNC0, USBNC1 }
#endif
/* Backward compatibility */
#define USB_OTGn_CTRL     CTRL1
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK      USBNC_CTRL1_OVER_CUR_DIS_MASK
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT     USBNC_CTRL1_OVER_CUR_DIS_SHIFT
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)        USBNC_CTRL1_OVER_CUR_DIS(x)
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK      USBNC_CTRL1_OVER_CUR_POL_MASK
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT     USBNC_CTRL1_OVER_CUR_POL_SHIFT
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)        USBNC_CTRL1_OVER_CUR_POL(x)
#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK           USBNC_CTRL1_PWR_POL_MASK
#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT          USBNC_CTRL1_PWR_POL_SHIFT
#define USBNC_USB_OTGn_CTRL_PWR_POL(x)             USBNC_CTRL1_PWR_POL(x)
#define USBNC_USB_OTGn_CTRL_WIE_MASK               USBNC_CTRL1_WIE_MASK
#define USBNC_USB_OTGn_CTRL_WIE_SHIFT              USBNC_CTRL1_WIE_SHIFT
#define USBNC_USB_OTGn_CTRL_WIE(x)                 USBNC_CTRL1_WIE(x)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK        USBNC_CTRL1_WKUP_SW_EN_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT       USBNC_CTRL1_WKUP_SW_EN_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)          USBNC_CTRL1_WKUP_SW_EN(x)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK           USBNC_CTRL1_WKUP_SW_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT          USBNC_CTRL1_WKUP_SW_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_SW(x)             USBNC_CTRL1_WKUP_SW(x)
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK      USBNC_CTRL1_WKUP_VBUS_EN_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT     USBNC_CTRL1_WKUP_VBUS_EN_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)        USBNC_CTRL1_WKUP_VBUS_EN(x)
#define USBNC_USB_OTGn_CTRL_REMOTE_WAKEUP_EN_MASK  USBNC_CTRL1_REMOTE_WAKEUP_EN_MASK
#define USBNC_USB_OTGn_CTRL_REMOTE_WAKEUP_EN_SHIFT USBNC_CTRL1_REMOTE_WAKEUP_EN_SHIFT
#define USBNC_USB_OTGn_CTRL_REMOTE_WAKEUP_EN(x)    USBNC_CTRL1_REMOTE_WAKEUP_EN(x)
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK      USBNC_CTRL1_WKUP_DPDM_EN_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT     USBNC_CTRL1_WKUP_DPDM_EN_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)        USBNC_CTRL1_WKUP_DPDM_EN(x)
#define USBNC_USB_OTGn_CTRL_WIR_MASK               USBNC_CTRL1_WIR_MASK
#define USBNC_USB_OTGn_CTRL_WIR_SHIFT              USBNC_CTRL1_WIR_SHIFT
#define USBNC_USB_OTGn_CTRL_WIR(x)                 USBNC_CTRL1_WIR(x)
#define USBNC_STACK_BASE_ADDRS                     { USBNC0_BASE, USBNC1_BASE }


/*!
 * @}
 */ /* end of group USBNC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBPHY Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
 * @{
 */

/** USBPHY - Register Layout Typedef */
typedef struct {
  __IO uint32_t PWD;                               /**< USBPHY Powerdown, offset: 0x0 */
  __IO uint32_t PWD_SET;                           /**< USBPHY Powerdown, offset: 0x4 */
  __IO uint32_t PWD_CLR;                           /**< USBPHY Powerdown, offset: 0x8 */
  __IO uint32_t PWD_TOG;                           /**< USBPHY Powerdown, offset: 0xC */
  __IO uint32_t TX;                                /**< USBPHY Transmitter Control, offset: 0x10 */
  __IO uint32_t TX_SET;                            /**< USBPHY Transmitter Control, offset: 0x14 */
  __IO uint32_t TX_CLR;                            /**< USBPHY Transmitter Control, offset: 0x18 */
  __IO uint32_t TX_TOG;                            /**< USBPHY Transmitter Control, offset: 0x1C */
  __IO uint32_t RX;                                /**< USBPHY Receiver Control, offset: 0x20 */
  __IO uint32_t RX_SET;                            /**< USBPHY Receiver Control, offset: 0x24 */
  __IO uint32_t RX_CLR;                            /**< USBPHY Receiver Control, offset: 0x28 */
  __IO uint32_t RX_TOG;                            /**< USBPHY Receiver Control, offset: 0x2C */
  __IO uint32_t CTRL;                              /**< USBPHY General Control, offset: 0x30 */
  __IO uint32_t CTRL_SET;                          /**< USBPHY General Control, offset: 0x34 */
  __IO uint32_t CTRL_CLR;                          /**< USBPHY General Control, offset: 0x38 */
  __IO uint32_t CTRL_TOG;                          /**< USBPHY General Control, offset: 0x3C */
  __I  uint32_t STATUS;                            /**< USBPHY Status, offset: 0x40 */
       uint8_t RESERVED_0[12];
  __IO uint32_t DEBUGr;                            /**< USBPHY Debug, offset: 0x50, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
  __IO uint32_t DEBUG_SET;                         /**< USBPHY Debug, offset: 0x54 */
  __IO uint32_t DEBUG_CLR;                         /**< USBPHY Debug, offset: 0x58 */
  __IO uint32_t DEBUG_TOG;                         /**< USBPHY Debug, offset: 0x5C */
  __I  uint32_t DEBUG0_STATUS;                     /**< UTMI Debug Status 0, offset: 0x60 */
       uint8_t RESERVED_1[12];
  __IO uint32_t DEBUG1;                            /**< UTMI Debug Status 1, offset: 0x70 */
  __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status 1, offset: 0x74 */
  __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status 1, offset: 0x78 */
  __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status 1, offset: 0x7C */
  __I  uint32_t VERSION;                           /**< USBPHY Version, offset: 0x80 */
       uint8_t RESERVED_2[28];
  __IO uint32_t PLL_SIC;                           /**< USBPHY PLL Control and Status, offset: 0xA0 */
  __IO uint32_t PLL_SIC_SET;                       /**< USBPHY PLL Control and Status, offset: 0xA4 */
  __IO uint32_t PLL_SIC_CLR;                       /**< USBPHY PLL Control and Status, offset: 0xA8 */
  __IO uint32_t PLL_SIC_TOG;                       /**< USBPHY PLL Control and Status, offset: 0xAC */
       uint8_t RESERVED_3[16];
  __IO uint32_t USB1_VBUS_DETECT;                  /**< USBPHY VBUS Detect Control, offset: 0xC0 */
  __IO uint32_t USB1_VBUS_DETECT_SET;              /**< USBPHY VBUS Detect Control, offset: 0xC4 */
  __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USBPHY VBUS Detect Control, offset: 0xC8 */
  __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USBPHY VBUS Detect Control, offset: 0xCC */
  __I  uint32_t USB1_VBUS_DET_STAT;                /**< USBPHY VBUS Detector Status, offset: 0xD0 */
       uint8_t RESERVED_4[12];
  __IO uint32_t USB1_CHRG_DETECT;                  /**< USBPHY Charger Detect Control, offset: 0xE0 */
  __IO uint32_t USB1_CHRG_DETECT_SET;              /**< USBPHY Charger Detect Control, offset: 0xE4 */
  __IO uint32_t USB1_CHRG_DETECT_CLR;              /**< USBPHY Charger Detect Control, offset: 0xE8 */
  __IO uint32_t USB1_CHRG_DETECT_TOG;              /**< USBPHY Charger Detect Control, offset: 0xEC */
  __I  uint32_t USB1_CHRG_DET_STAT;                /**< USBPHY Charger Detect Status, offset: 0xF0 */
       uint8_t RESERVED_5[12];
  __IO uint32_t ANACTRL;                           /**< USBPHY Analog Control, offset: 0x100 */
  __IO uint32_t ANACTRL_SET;                       /**< USBPHY Analog Control, offset: 0x104 */
  __IO uint32_t ANACTRL_CLR;                       /**< USBPHY Analog Control, offset: 0x108 */
  __IO uint32_t ANACTRL_TOG;                       /**< USBPHY Analog Control, offset: 0x10C */
  __IO uint32_t USB1_LOOPBACK;                     /**< USBPHY Loopback Control and Status, offset: 0x110 */
  __IO uint32_t USB1_LOOPBACK_SET;                 /**< USBPHY Loopback Control and Status, offset: 0x114 */
  __IO uint32_t USB1_LOOPBACK_CLR;                 /**< USBPHY Loopback Control and Status, offset: 0x118 */
  __IO uint32_t USB1_LOOPBACK_TOG;                 /**< USBPHY Loopback Control and Status, offset: 0x11C */
  __IO uint32_t USB1_LOOPBACK_HSFSCNT;             /**< USBPHY Loopback Packet Number Selection, offset: 0x120 */
  __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;         /**< USBPHY Loopback Packet Number Selection, offset: 0x124 */
  __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;         /**< USBPHY Loopback Packet Number Selection, offset: 0x128 */
  __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;         /**< USBPHY Loopback Packet Number Selection, offset: 0x12C */
  __IO uint32_t TRIM_OVERRIDE_EN;                  /**< USBPHY Trim Override Enable, offset: 0x130 */
  __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< USBPHY Trim Override Enable, offset: 0x134 */
  __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< USBPHY Trim Override Enable, offset: 0x138 */
  __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< USBPHY Trim Override Enable, offset: 0x13C */
} USBPHY_Type;

/* ----------------------------------------------------------------------------
   -- USBPHY Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
 * @{
 */

/*! @name PWD - USBPHY Powerdown */
/*! @{ */

#define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
#define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
/*! TXPWDFS - FS Transmitter Powerdown
 *  0b0..Provide bias to enable for normal operation
 *  0b1..Disable or power down
 */
#define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)

#define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
#define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
/*! TXPWDIBIAS - Transmitter Bias Powerdown
 *  0b0..Enable for normal operation
 *  0b1..Disable or power down
 */
#define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)

#define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
#define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
/*! TXPWDV2I - USBPHY TX V-I Converter and Current Mirror Powerdown
 *  0b0..Enable for normal operation
 *  0b1..Disable or power down
 */
#define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)

#define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
#define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
/*! RXPWDENV - Receiver Envelope Powerdown
 *  0b0..Enable for normal operation
 *  0b1..Disable or power down
 */
#define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)

#define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
#define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
/*! RXPWD1PT1 - FS Receiver Powerdown
 *  0b0..Enable for normal operation
 *  0b1..Disable or power down
 */
#define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)

#define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
#define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
/*! RXPWDDIFF - HS Receiver Powerdown
 *  0b0..Enable for normal operation
 *  0b1..Disable or power down
 */
#define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)

#define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
#define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
/*! RXPWDRX - Receiver Powerdown
 *  0b0..Enable for normal operation
 *  0b1..Disable or power down RX circuits
 */
#define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
/*! @} */

/*! @name PWD_SET - USBPHY Powerdown */
/*! @{ */

#define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
#define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
/*! TXPWDFS - FS Transmitter Powerdown */
#define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)

#define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
/*! TXPWDIBIAS - Transmitter Bias Powerdown */
#define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)

#define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
#define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
/*! TXPWDV2I - USBPHY TX V-I Converter and Current Mirror Powerdown */
#define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)

#define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
#define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
/*! RXPWDENV - Receiver Envelope Powerdown */
#define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)

#define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
/*! RXPWD1PT1 - FS Receiver Powerdown */
#define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)

#define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
/*! RXPWDDIFF - HS Receiver Powerdown */
#define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)

#define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
#define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
/*! RXPWDRX - Receiver Powerdown */
#define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
/*! @} */

/*! @name PWD_CLR - USBPHY Powerdown */
/*! @{ */

#define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
#define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
/*! TXPWDFS - FS Transmitter Powerdown */
#define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)

#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
/*! TXPWDIBIAS - Transmitter Bias Powerdown */
#define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)

#define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
/*! TXPWDV2I - USBPHY TX V-I Converter and Current Mirror Powerdown */
#define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)

#define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
#define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
/*! RXPWDENV - Receiver Envelope Powerdown */
#define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)

#define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
/*! RXPWD1PT1 - FS Receiver Powerdown */
#define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)

#define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
/*! RXPWDDIFF - HS Receiver Powerdown */
#define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)

#define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
#define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
/*! RXPWDRX - Receiver Powerdown */
#define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
/*! @} */

/*! @name PWD_TOG - USBPHY Powerdown */
/*! @{ */

#define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
#define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
/*! TXPWDFS - FS Transmitter Powerdown */
#define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)

#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
/*! TXPWDIBIAS - Transmitter Bias Powerdown */
#define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)

#define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
/*! TXPWDV2I - USBPHY TX V-I Converter and Current Mirror Powerdown */
#define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)

#define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
#define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
/*! RXPWDENV - Receiver Envelope Powerdown */
#define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)

#define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
/*! RXPWD1PT1 - FS Receiver Powerdown */
#define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)

#define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
/*! RXPWDDIFF - HS Receiver Powerdown */
#define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)

#define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
#define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
/*! RXPWDRX - Receiver Powerdown */
#define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
/*! @} */

/*! @name TX - USBPHY Transmitter Control */
/*! @{ */

#define USBPHY_TX_D_CAL_MASK                     (0xFU)
#define USBPHY_TX_D_CAL_SHIFT                    (0U)
/*! D_CAL - HS Transmit Output Current Trim
 *  0b0000..+20.30%
 *  0b0001..+17.60%
 *  0b0010..+14.80%
 *  0b0011..+12.60%
 *  0b0100..+8.79%
 *  0b0101..+6.04%
 *  0b0110..+2.75%
 *  0b0111..0%
 *  0b1000..-2.75%
 *  0b1001..-5.49%
 *  0b1010..-7.69%
 *  0b1011..-10.40%
 *  0b1100..-12.60%
 *  0b1101..-14.30%
 *  0b1110..-18.10%
 *  0b1111..-22.00%
 */
#define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)

#define USBPHY_TX_TXCAL45DN_MASK                 (0xF00U)
#define USBPHY_TX_TXCAL45DN_SHIFT                (8U)
/*! TXCAL45DN - Transmit Calculation 45 ohm DN
 *  0b0000..+19.95%
 *  0b0001..+17.35%
 *  0b0010..+14.85%
 *  0b0011..+12.46%
 *  0b0100..+9.07%
 *  0b0101..+5.87%
 *  0b0110..+2.85%
 *  0b0111..0%
 *  0b1000..-2.70%
 *  0b1001..-5.25%
 *  0b1010..-7.67%
 *  0b1011..-9.98%
 *  0b1100..-12.17%
 *  0b1101..-14.25%
 *  0b1110..-18.14%
 *  0b1111..-21.68%
 */
#define USBPHY_TX_TXCAL45DN(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)

#define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
#define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
/*! TXCAL45DP - Transmit Calculation 45 ohm DP
 *  0b0000..+19.95%
 *  0b0001..+17.35%
 *  0b0010..+14.85%
 *  0b0011..+12.46%
 *  0b0100..+9.07%
 *  0b0101..+5.87%
 *  0b0110..+2.85%
 *  0b0111..0%
 *  0b1000..-2.70%
 *  0b1001..-5.25%
 *  0b1010..-7.67%
 *  0b1011..-9.98%
 *  0b1100..-12.17%
 *  0b1101..-14.25%
 *  0b1110..-18.14%
 *  0b1111..-21.68%
 */
#define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
/*! @} */

/*! @name TX_SET - USBPHY Transmitter Control */
/*! @{ */

#define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
#define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
/*! D_CAL - HS Transmit Output Current Trim */
#define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)

#define USBPHY_TX_SET_TXCAL45DN_MASK             (0xF00U)
#define USBPHY_TX_SET_TXCAL45DN_SHIFT            (8U)
/*! TXCAL45DN - Transmit Calculation 45 ohm DN */
#define USBPHY_TX_SET_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)

#define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
#define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
/*! TXCAL45DP - Transmit Calculation 45 ohm DP */
#define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
/*! @} */

/*! @name TX_CLR - USBPHY Transmitter Control */
/*! @{ */

#define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
#define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
/*! D_CAL - HS Transmit Output Current Trim */
#define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)

#define USBPHY_TX_CLR_TXCAL45DN_MASK             (0xF00U)
#define USBPHY_TX_CLR_TXCAL45DN_SHIFT            (8U)
/*! TXCAL45DN - Transmit Calculation 45 ohm DN */
#define USBPHY_TX_CLR_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)

#define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
#define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
/*! TXCAL45DP - Transmit Calculation 45 ohm DP */
#define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
/*! @} */

/*! @name TX_TOG - USBPHY Transmitter Control */
/*! @{ */

#define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
#define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
/*! D_CAL - HS Transmit Output Current Trim */
#define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)

#define USBPHY_TX_TOG_TXCAL45DN_MASK             (0xF00U)
#define USBPHY_TX_TOG_TXCAL45DN_SHIFT            (8U)
/*! TXCAL45DN - Transmit Calculation 45 ohm DN */
#define USBPHY_TX_TOG_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)

#define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
#define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
/*! TXCAL45DP - Transmit Calculation 45 ohm DP */
#define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
/*! @} */

/*! @name RX - USBPHY Receiver Control */
/*! @{ */

#define USBPHY_RX_ENVADJ_MASK                    (0x7U)
#define USBPHY_RX_ENVADJ_SHIFT                   (0U)
/*! ENVADJ - Envelope Adjustment
 *  0b000..0.1000 V
 *  0b001..0.1125 V
 *  0b010..0.1250 V
 *  0b011..0.0875 V
 *  0b1xx..Reserved
 */
#define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)

#define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
#define USBPHY_RX_DISCONADJ_SHIFT                (4U)
/*! DISCONADJ - Disconnect Adjustment
 *  0b000..0.56875 V
 *  0b001..0.55000 V
 *  0b010..0.58125 V
 *  0b011..0.60000 V
 *  0b1xx..Reserved
 */
#define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)

#define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
#define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
/*! RXDBYPASS - Differential Receiver Bypass
 *  0b0..Operate normally
 *  0b1..Bypass
 */
#define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
/*! @} */

/*! @name RX_SET - USBPHY Receiver Control */
/*! @{ */

#define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
#define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
/*! ENVADJ - Envelope Adjustment */
#define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)

#define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
#define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
/*! DISCONADJ - Disconnect Adjustment */
#define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)

#define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
#define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
/*! RXDBYPASS - Differential Receiver Bypass */
#define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
/*! @} */

/*! @name RX_CLR - USBPHY Receiver Control */
/*! @{ */

#define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
#define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
/*! ENVADJ - Envelope Adjustment */
#define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)

#define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
#define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
/*! DISCONADJ - Disconnect Adjustment */
#define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)

#define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
#define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
/*! RXDBYPASS - Differential Receiver Bypass */
#define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
/*! @} */

/*! @name RX_TOG - USBPHY Receiver Control */
/*! @{ */

#define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
#define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
/*! ENVADJ - Envelope Adjustment */
#define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)

#define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
#define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
/*! DISCONADJ - Disconnect Adjustment */
#define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)

#define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
#define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
/*! RXDBYPASS - Differential Receiver Bypass */
#define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
/*! @} */

/*! @name CTRL - USBPHY General Control */
/*! @{ */

#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)

#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         (0x4U)
#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        (2U)
/*! ENIRQHOSTDISCON - Host Disconnect Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENIRQHOSTDISCON(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)

#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt
 *  0b0..Connected
 *  0b1..Disconnected
 */
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)

#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       (0x10U)
#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      (4U)
/*! ENDEVPLUGINDETECT - Nonstandard Resistive Plugged-In Detection Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENDEVPLUGINDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)

#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      (0x20U)
#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     (5U)
/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity
 *  0b0..Plugged in
 *  0b1..Unplugged
 */
#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)

#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         (0x100U)
#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        (8U)
/*! RESUMEIRQSTICKY - RESUME_IRQ Sticky
 *  0b0..Remains 1 during the wake-up period
 *  0b1..Remains 1 until you write 0 to it
 */
#define USBPHY_CTRL_RESUMEIRQSTICKY(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)

#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       (0x200U)
#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      (9U)
/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENIRQRESUMEDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)

#define USBPHY_CTRL_RESUME_IRQ_MASK              (0x400U)
#define USBPHY_CTRL_RESUME_IRQ_SHIFT             (10U)
/*! RESUME_IRQ - Interrupt Resume
 *  0b0..No resume interrupt
 *  0b1..Resume interrupt
 */
#define USBPHY_CTRL_RESUME_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)

#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          (0x800U)
#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         (11U)
/*! ENIRQDEVPLUGIN - Device Plug-In Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENIRQDEVPLUGIN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)

#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt
 *  0b0..Not connected
 *  0b1..Connected
 */
#define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)

#define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
/*! ENUTMILEVEL2 - UTMI Level 2 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)

#define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
/*! ENUTMILEVEL3 - UTMI Level 3 Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)

#define USBPHY_CTRL_ENIRQWAKEUP_MASK             (0x10000U)
#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            (16U)
/*! ENIRQWAKEUP - Wake-Up Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENIRQWAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)

#define USBPHY_CTRL_WAKEUP_IRQ_MASK              (0x20000U)
#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             (17U)
/*! WAKEUP_IRQ - Wake-Up Interrupt
 *  0b0..No wake-up event exists
 *  0b1..Wake-up event exists
 */
#define USBPHY_CTRL_WAKEUP_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)

#define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
#define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
/*! AUTORESUME_EN - Auto Resume Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)

#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
/*! ENAUTOCLR_CLKGATE - Clock Gating Auto Clear Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)

#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
/*! ENAUTOCLR_PHY_PWD - PHY PWD Auto Clear Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)

#define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
/*! FSDLL_RST_EN - FSDLL Reset Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)

#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
/*! HOST_FORCE_LS_SE0 - FS EOP LS Timing
 *  0b0..Do not force the next FS packet
 *  0b1..Force the next FS packet
 */
#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)

#define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
/*! UTMI_SUSPENDM - UTMI Suspend Mode
 *  0b0..Suspended
 *  0b1..Not suspended
 */
#define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)

#define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
#define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
/*! CLKGATE - Clock Gating
 *  0b0..Run clocks
 *  0b1..Gate clocks
 */
#define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)

#define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
#define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
/*! SFTRST - Software Reset
 *  0b0..Release from reset
 *  0b1..Reset
 */
#define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
/*! @} */

/*! @name CTRL_SET - USBPHY General Control */
/*! @{ */

#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)

#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     (0x4U)
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    (2U)
/*! ENIRQHOSTDISCON - Host Disconnect Interrupt Enable */
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)

#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)

#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   (0x10U)
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  (4U)
/*! ENDEVPLUGINDETECT - Nonstandard Resistive Plugged-In Detection Enable */
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)

#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  (0x20U)
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)

#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     (0x100U)
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    (8U)
/*! RESUMEIRQSTICKY - RESUME_IRQ Sticky */
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)

#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  (9U)
/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)

#define USBPHY_CTRL_SET_RESUME_IRQ_MASK          (0x400U)
#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         (10U)
/*! RESUME_IRQ - Interrupt Resume */
#define USBPHY_CTRL_SET_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)

#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      (0x800U)
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     (11U)
/*! ENIRQDEVPLUGIN - Device Plug-In Interrupt Enable */
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)

#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)

#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
/*! ENUTMILEVEL2 - UTMI Level 2 Enable */
#define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)

#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
/*! ENUTMILEVEL3 - UTMI Level 3 Enable */
#define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)

#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         (0x10000U)
#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        (16U)
/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */
#define USBPHY_CTRL_SET_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)

#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          (0x20000U)
#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         (17U)
/*! WAKEUP_IRQ - Wake-Up Interrupt */
#define USBPHY_CTRL_SET_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)

#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
/*! AUTORESUME_EN - Auto Resume Enable */
#define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)

#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
/*! ENAUTOCLR_CLKGATE - Clock Gating Auto Clear Enable */
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)

#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
/*! ENAUTOCLR_PHY_PWD - PHY PWD Auto Clear Enable */
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)

#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
/*! FSDLL_RST_EN - FSDLL Reset Enable */
#define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)

#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
/*! HOST_FORCE_LS_SE0 - FS EOP LS Timing */
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)

#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
/*! UTMI_SUSPENDM - UTMI Suspend Mode */
#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)

#define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
#define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
/*! CLKGATE - Clock Gating */
#define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)

#define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
#define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
/*! SFTRST - Software Reset */
#define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
/*! @} */

/*! @name CTRL_CLR - USBPHY General Control */
/*! @{ */

#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)

#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     (0x4U)
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    (2U)
/*! ENIRQHOSTDISCON - Host Disconnect Interrupt Enable */
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)

#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)

#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   (0x10U)
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  (4U)
/*! ENDEVPLUGINDETECT - Nonstandard Resistive Plugged-In Detection Enable */
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)

#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  (0x20U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)

#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     (0x100U)
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    (8U)
/*! RESUMEIRQSTICKY - RESUME_IRQ Sticky */
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)

#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  (9U)
/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)

#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          (0x400U)
#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         (10U)
/*! RESUME_IRQ - Interrupt Resume */
#define USBPHY_CTRL_CLR_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)

#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      (0x800U)
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     (11U)
/*! ENIRQDEVPLUGIN - Device Plug-In Interrupt Enable */
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)

#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)

#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
/*! ENUTMILEVEL2 - UTMI Level 2 Enable */
#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)

#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
/*! ENUTMILEVEL3 - UTMI Level 3 Enable */
#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)

#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         (0x10000U)
#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        (16U)
/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */
#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)

#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          (0x20000U)
#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         (17U)
/*! WAKEUP_IRQ - Wake-Up Interrupt */
#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)

#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
/*! AUTORESUME_EN - Auto Resume Enable */
#define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)

#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
/*! ENAUTOCLR_CLKGATE - Clock Gating Auto Clear Enable */
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)

#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
/*! ENAUTOCLR_PHY_PWD - PHY PWD Auto Clear Enable */
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)

#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
/*! FSDLL_RST_EN - FSDLL Reset Enable */
#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)

#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
/*! HOST_FORCE_LS_SE0 - FS EOP LS Timing */
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)

#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
/*! UTMI_SUSPENDM - UTMI Suspend Mode */
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)

#define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
#define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
/*! CLKGATE - Clock Gating */
#define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)

#define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
#define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
/*! SFTRST - Software Reset */
#define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
/*! @} */

/*! @name CTRL_TOG - USBPHY General Control */
/*! @{ */

#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)

#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     (0x4U)
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    (2U)
/*! ENIRQHOSTDISCON - Host Disconnect Interrupt Enable */
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)

#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)

#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   (0x10U)
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  (4U)
/*! ENDEVPLUGINDETECT - Nonstandard Resistive Plugged-In Detection Enable */
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)

#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  (0x20U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)

#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     (0x100U)
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    (8U)
/*! RESUMEIRQSTICKY - RESUME_IRQ Sticky */
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)

#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  (9U)
/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)

#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          (0x400U)
#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         (10U)
/*! RESUME_IRQ - Interrupt Resume */
#define USBPHY_CTRL_TOG_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)

#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      (0x800U)
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     (11U)
/*! ENIRQDEVPLUGIN - Device Plug-In Interrupt Enable */
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)

#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)

#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
/*! ENUTMILEVEL2 - UTMI Level 2 Enable */
#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)

#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
/*! ENUTMILEVEL3 - UTMI Level 3 Enable */
#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)

#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         (0x10000U)
#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        (16U)
/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */
#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)

#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          (0x20000U)
#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         (17U)
/*! WAKEUP_IRQ - Wake-Up Interrupt */
#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)

#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
/*! AUTORESUME_EN - Auto Resume Enable */
#define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)

#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
/*! ENAUTOCLR_CLKGATE - Clock Gating Auto Clear Enable */
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)

#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
/*! ENAUTOCLR_PHY_PWD - PHY PWD Auto Clear Enable */
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)

#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
/*! FSDLL_RST_EN - FSDLL Reset Enable */
#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)

#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
/*! HOST_FORCE_LS_SE0 - FS EOP LS Timing */
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)

#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
/*! UTMI_SUSPENDM - UTMI Suspend Mode */
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)

#define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
#define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
/*! CLKGATE - Clock Gating */
#define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)

#define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
#define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
/*! SFTRST - Software Reset */
#define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
/*! @} */

/*! @name STATUS - USBPHY Status */
/*! @{ */

#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
/*! HOSTDISCONDETECT_STATUS - Host Disconnect Detection Status
 *  0b0..Do not detect
 *  0b1..Detect
 */
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)

#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
/*! DEVPLUGIN_STATUS - Status Indicator for Nonstandard Resistive Plugged-In Detection
 *  0b0..No attachment detected
 *  0b1..Cable attachment detected
 */
#define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)

#define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
#define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
/*! RESUME_STATUS - Resume Status
 *  0b0..Is in J state
 *  0b1..Is not in J state
 */
#define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
/*! @} */

/*! @name DEBUG - USBPHY Debug */
/*! @{ */

#define USBPHY_DEBUG_HSTPULLDOWN_MASK            (0xCU)
#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           (2U)
/*! HSTPULLDOWN - Select DP and DN Pulldown Resistors in Host Pulldown Overdrive Mode
 *  0b01..Connect 15 kohm pulldown on DN
 *  0b10..Connect 15 kohm pulldown on DP
 *  0b11..Connect 15 kohm pulldown on DP and DN
 *  0b00..Disconnect the resistors
 */
#define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)

#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          (0x30U)
#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         (4U)
/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode
 *  0b01..Override the control of DN 15 kohm pulldown
 *  0b10..Override the control of DP 15 kohm pulldown
 *  0b11..Override the control of DP and DN 15 kohm pulldown
 *  0b00..Disable Host Pulldown Overdrive mode
 */
#define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)

#define USBPHY_DEBUG_TX2RXCOUNT_MASK             (0xF00U)
#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            (8U)
/*! TX2RXCOUNT - Set Countdown Delay Value from TX to RX Packets for Debug */
#define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)

#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           (0x1000U)
#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          (12U)
/*! ENTX2RXCOUNT - Enable Countdown from TX to RX Packets for Debug
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_DEBUG_ENTX2RXCOUNT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)

#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      (0x1F0000U)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     (16U)
/*! SQUELCHRESETCOUNT - Squelch Reset Count */
#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)

#define USBPHY_DEBUG_ENSQUELCHRESET_MASK         (0x1000000U)
#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        (24U)
/*! ENSQUELCHRESET - Enable Squelch Reset
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_DEBUG_ENSQUELCHRESET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)

#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     (0x1E000000U)
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    (25U)
/*! SQUELCHRESETLENGTH - Squelch Reset Length */
#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)

#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      (0x20000000U)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     (29U)
/*! HOST_RESUME_DEBUG - Host Resume
 *  0b0..Based on CTRL[HOST_FORCE_LS_SE0]
 *  0b1..Based on CTRL[UTMI_SUSPENDM]
 */
#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)

#define USBPHY_DEBUG_CLKGATE_MASK                (0x40000000U)
#define USBPHY_DEBUG_CLKGATE_SHIFT               (30U)
/*! CLKGATE - Clock Gating
 *  0b0..Run clocks
 *  0b1..Gate clocks
 */
#define USBPHY_DEBUG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
/*! @} */

/*! @name DEBUG_SET - USBPHY Debug */
/*! @{ */

#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        (0xCU)
#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       (2U)
/*! HSTPULLDOWN - Select DP and DN Pulldown Resistors in Host Pulldown Overdrive Mode */
#define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)

#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      (0x30U)
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     (4U)
/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)

#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         (0xF00U)
#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        (8U)
/*! TX2RXCOUNT - Set Countdown Delay Value from TX to RX Packets for Debug */
#define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)

#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       (0x1000U)
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      (12U)
/*! ENTX2RXCOUNT - Enable Countdown from TX to RX Packets for Debug */
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)

#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - Squelch Reset Count */
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)

#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     (0x1000000U)
#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    (24U)
/*! ENSQUELCHRESET - Enable Squelch Reset */
#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)

#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - Squelch Reset Length */
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)

#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  (0x20000000U)
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - Host Resume */
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)

#define USBPHY_DEBUG_SET_CLKGATE_MASK            (0x40000000U)
#define USBPHY_DEBUG_SET_CLKGATE_SHIFT           (30U)
/*! CLKGATE - Clock Gating */
#define USBPHY_DEBUG_SET_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
/*! @} */

/*! @name DEBUG_CLR - USBPHY Debug */
/*! @{ */

#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        (0xCU)
#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       (2U)
/*! HSTPULLDOWN - Select DP and DN Pulldown Resistors in Host Pulldown Overdrive Mode */
#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)

#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      (0x30U)
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     (4U)
/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)

#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         (0xF00U)
#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        (8U)
/*! TX2RXCOUNT - Set Countdown Delay Value from TX to RX Packets for Debug */
#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)

#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       (0x1000U)
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      (12U)
/*! ENTX2RXCOUNT - Enable Countdown from TX to RX Packets for Debug */
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)

#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - Squelch Reset Count */
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)

#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     (0x1000000U)
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    (24U)
/*! ENSQUELCHRESET - Enable Squelch Reset */
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)

#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - Squelch Reset Length */
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)

#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  (0x20000000U)
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - Host Resume */
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)

#define USBPHY_DEBUG_CLR_CLKGATE_MASK            (0x40000000U)
#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           (30U)
/*! CLKGATE - Clock Gating */
#define USBPHY_DEBUG_CLR_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
/*! @} */

/*! @name DEBUG_TOG - USBPHY Debug */
/*! @{ */

#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        (0xCU)
#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       (2U)
/*! HSTPULLDOWN - Select DP and DN Pulldown Resistors in Host Pulldown Overdrive Mode */
#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)

#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      (0x30U)
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     (4U)
/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)

#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         (0xF00U)
#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        (8U)
/*! TX2RXCOUNT - Set Countdown Delay Value from TX to RX Packets for Debug */
#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)

#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       (0x1000U)
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      (12U)
/*! ENTX2RXCOUNT - Enable Countdown from TX to RX Packets for Debug */
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)

#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - Squelch Reset Count */
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)

#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     (0x1000000U)
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    (24U)
/*! ENSQUELCHRESET - Enable Squelch Reset */
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)

#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - Squelch Reset Length */
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)

#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  (0x20000000U)
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - Host Resume */
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)

#define USBPHY_DEBUG_TOG_CLKGATE_MASK            (0x40000000U)
#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           (30U)
/*! CLKGATE - Clock Gating */
#define USBPHY_DEBUG_TOG_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
/*! @} */

/*! @name DEBUG0_STATUS - UTMI Debug Status 0 */
/*! @{ */

#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
/*! LOOP_BACK_FAIL_COUNT - Loopback Fail Count */
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)

#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
/*! UTMI_RXERROR_FAIL_COUNT - UTMI Receive Error Fail Count */
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)

#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  (0xFC000000U)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
/*! SQUELCH_COUNT - Squelch Count */
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
/*! @} */

/*! @name DEBUG1 - UTMI Debug Status 1 */
/*! @{ */

#define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
/*! ENTAILADJVD - HS RX Squelch Rise Time Delay Trim
 *  0b00..Squelch rising edge delay is nominal
 *  0b01..+20% delay compared to nominal
 *  0b10..-20% delay compared to nominal
 *  0b11..-40% delay compared to nominal
 */
#define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Self-Bias Off for Reference Bias Amplifiers and Comparators
 *  0b1..Current reference bias
 *  0b0..Self-bias
 */
#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Bandgap Voltage Status Comparator Powerdown
 *  0b0..Enables
 *  0b1..Disables
 */
#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT  (17U)
/*! USB2_REFBIAS_LOWPWR - Reference Bias Low Power Configuration
 *  0b0..Nominal bias current
 *  0b1..50% of nominal bias current
 */
#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT  (18U)
/*! USB2_REFBIAS_VBGADJ - Bandgap Voltage Adjustment
 *  0b000..Nominal bandgap voltage; flattest temperature coefficient
 *  0b001..≈ +10 mV compared to nominal
 *  0b010..≈ +20 mV compared to nominal
 *  0b011..≈ +30 mV compared to nominal; most-positive temperature coefficient
 *  0b100..≈ -10 mV compared to nominal
 *  0b101..≈ -20 mV compared to nominal
 *  0b110..≈ -30 mV compared to nominal
 *  0b111..≈ -40 mV compared to nominal; most-negative temperature coefficient
 */
#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK      (0x600000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT     (21U)
/*! USB2_REFBIAS_TST - Bias Current Control Adjustment
 *  0b00..≈ 10 uA reference current; nominal
 *  0b01..≈ 0.9x compared to nominal
 *  0b10..≈ 0.8x compared to nominal
 *  0b11..≈ 1.1x compared to nominal
 */
#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
/*! @} */

/*! @name DEBUG1_SET - UTMI Debug Status 1 */
/*! @{ */

#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
/*! ENTAILADJVD - HS RX Squelch Rise Time Delay Trim */
#define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Self-Bias Off for Reference Bias Amplifiers and Comparators */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Bandgap Voltage Status Comparator Powerdown */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - Reference Bias Low Power Configuration */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Bandgap Voltage Adjustment */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK  (0x600000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias Current Control Adjustment */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
/*! @} */

/*! @name DEBUG1_CLR - UTMI Debug Status 1 */
/*! @{ */

#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
/*! ENTAILADJVD - HS RX Squelch Rise Time Delay Trim */
#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Self-Bias Off for Reference Bias Amplifiers and Comparators */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Bandgap Voltage Status Comparator Powerdown */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - Reference Bias Low Power Configuration */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Bandgap Voltage Adjustment */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK  (0x600000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias Current Control Adjustment */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
/*! @} */

/*! @name DEBUG1_TOG - UTMI Debug Status 1 */
/*! @{ */

#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
/*! ENTAILADJVD - HS RX Squelch Rise Time Delay Trim */
#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Self-Bias Off for Reference Bias Amplifiers and Comparators */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Bandgap Voltage Status Comparator Powerdown */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - Reference Bias Low Power Configuration */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Bandgap Voltage Adjustment */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK  (0x600000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias Current Control Adjustment */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
/*! @} */

/*! @name VERSION - USBPHY Version */
/*! @{ */

#define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
#define USBPHY_VERSION_STEP_SHIFT                (0U)
/*! STEP - Step */
#define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)

#define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
#define USBPHY_VERSION_MINOR_SHIFT               (16U)
/*! MINOR - Minor */
#define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)

#define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
#define USBPHY_VERSION_MAJOR_SHIFT               (24U)
/*! MAJOR - Major */
#define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
/*! @} */

/*! @name PLL_SIC - USBPHY PLL Control and Status */
/*! @{ */

#define USBPHY_PLL_SIC_PLL_POSTDIV_MASK          (0x1CU)
#define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT         (2U)
/*! PLL_POSTDIV - PLL Post-Divider Output Value Configuration
 *  0b000..Disable the output of PLL post divider
 *  0b001..Divide value is 1
 *  0b010..Divide value is 2
 *  0b011..Divide value is 3
 *  0b100..Divide value is 4
 *  0b101..Divide value is 5
 *  0b110..Divide value is 6
 *  0b111..Reserved; do not use
 */
#define USBPHY_PLL_SIC_PLL_POSTDIV(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)

#define USBPHY_PLL_SIC_PLL_MISC2_CONTROL0_MASK   (0x20U)
#define USBPHY_PLL_SIC_PLL_MISC2_CONTROL0_SHIFT  (5U)
/*! PLL_MISC2_CONTROL0 - PLL_MISC2_CONTROL0
 *  0b0..Power up PLL without regard to state of "SuspendM" signal
 *  0b1..Power down PLL when in Suspend bus state
 */
#define USBPHY_PLL_SIC_PLL_MISC2_CONTROL0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_PLL_MISC2_CONTROL0_MASK)

#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK      (0x40U)
#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT     (6U)
/*! PLL_EN_USB_CLKS - PLL USB Clocks Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)

#define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
#define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
/*! PLL_POWER - PLL Power
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)

#define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
/*! PLL_ENABLE - PLL Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)

#define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
/*! PLL_BYPASS - PLL Bypass
 *  0b0..Do not bypass
 *  0b1..Bypass
 */
#define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)

#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK      (0x80000U)
#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT     (19U)
/*! REFBIAS_PWD_SEL - Reference Bias Powerdown Selection
 *  0b0..PLL_POWER
 *  0b1..REFBIAS_PWD
 */
#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)

#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK          (0x100000U)
#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT         (20U)
/*! REFBIAS_PWD - Reference Bias Powerdown
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_PLL_SIC_REFBIAS_PWD(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)

#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK       (0x200000U)
#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT      (21U)
/*! PLL_REG_ENABLE - PLL Regulator Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)

#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x1C00000U)
#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (22U)
/*! PLL_DIV_SEL - PLL Divider Selection
 *  0b000..Divide by 13
 *  0b001..Divide by 15
 *  0b010..Divide by 16
 *  0b011..Divide by 20
 *  0b100..Divide by 22
 *  0b101..Divide by 25
 *  0b110..Divide by 30
 *  0b111..Divide by 40
 */
#define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)

#define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
/*! PLL_LOCK - PLL Lock
 *  0b0..Not locked
 *  0b1..Locked
 */
#define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
/*! @} */

/*! @name PLL_SIC_SET - USBPHY PLL Control and Status */
/*! @{ */

#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK      (0x1CU)
#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT     (2U)
/*! PLL_POSTDIV - PLL Post-Divider Output Value Configuration */
#define USBPHY_PLL_SIC_SET_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK)

#define USBPHY_PLL_SIC_SET_PLL_MISC2_CONTROL0_MASK (0x20U)
#define USBPHY_PLL_SIC_SET_PLL_MISC2_CONTROL0_SHIFT (5U)
/*! PLL_MISC2_CONTROL0 - PLL_MISC2_CONTROL0 */
#define USBPHY_PLL_SIC_SET_PLL_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_MISC2_CONTROL0_MASK)

#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK  (0x40U)
#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL USB Clocks Enable */
#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)

#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
/*! PLL_POWER - PLL Power */
#define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)

#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
/*! PLL_ENABLE - PLL Enable */
#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)

#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
/*! PLL_BYPASS - PLL Bypass */
#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)

#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK  (0x80000U)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - Reference Bias Powerdown Selection */
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)

#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK      (0x100000U)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT     (20U)
/*! REFBIAS_PWD - Reference Bias Powerdown */
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)

#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT  (21U)
/*! PLL_REG_ENABLE - PLL Regulator Enable */
#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)

#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x1C00000U)
#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (22U)
/*! PLL_DIV_SEL - PLL Divider Selection */
#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)

#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
/*! PLL_LOCK - PLL Lock */
#define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
/*! @} */

/*! @name PLL_SIC_CLR - USBPHY PLL Control and Status */
/*! @{ */

#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK      (0x1CU)
#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT     (2U)
/*! PLL_POSTDIV - PLL Post-Divider Output Value Configuration */
#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_MISC2_CONTROL0_MASK (0x20U)
#define USBPHY_PLL_SIC_CLR_PLL_MISC2_CONTROL0_SHIFT (5U)
/*! PLL_MISC2_CONTROL0 - PLL_MISC2_CONTROL0 */
#define USBPHY_PLL_SIC_CLR_PLL_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_MISC2_CONTROL0_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK  (0x40U)
#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL USB Clocks Enable */
#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
/*! PLL_POWER - PLL Power */
#define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
/*! PLL_ENABLE - PLL Enable */
#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
/*! PLL_BYPASS - PLL Bypass */
#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)

#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK  (0x80000U)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - Reference Bias Powerdown Selection */
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)

#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK      (0x100000U)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT     (20U)
/*! REFBIAS_PWD - Reference Bias Powerdown */
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT  (21U)
/*! PLL_REG_ENABLE - PLL Regulator Enable */
#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x1C00000U)
#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (22U)
/*! PLL_DIV_SEL - PLL Divider Selection */
#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
/*! PLL_LOCK - PLL Lock */
#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
/*! @} */

/*! @name PLL_SIC_TOG - USBPHY PLL Control and Status */
/*! @{ */

#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK      (0x1CU)
#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT     (2U)
/*! PLL_POSTDIV - PLL Post-Divider Output Value Configuration */
#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_MISC2_CONTROL0_MASK (0x20U)
#define USBPHY_PLL_SIC_TOG_PLL_MISC2_CONTROL0_SHIFT (5U)
/*! PLL_MISC2_CONTROL0 - PLL_MISC2_CONTROL0 */
#define USBPHY_PLL_SIC_TOG_PLL_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_MISC2_CONTROL0_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK  (0x40U)
#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL USB Clocks Enable */
#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
/*! PLL_POWER - PLL Power */
#define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
/*! PLL_ENABLE - PLL Enable */
#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
/*! PLL_BYPASS - PLL Bypass */
#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)

#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK  (0x80000U)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - Reference Bias Powerdown Selection */
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)

#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK      (0x100000U)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT     (20U)
/*! REFBIAS_PWD - Reference Bias Powerdown */
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT  (21U)
/*! PLL_REG_ENABLE - PLL Regulator Enable */
#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x1C00000U)
#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (22U)
/*! PLL_DIV_SEL - PLL Divider Selection */
#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
/*! PLL_LOCK - PLL Lock */
#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
/*! @} */

/*! @name USB1_VBUS_DETECT - USBPHY VBUS Detect Control */
/*! @{ */

#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID Threshold
 *  0b000..4.0 V
 *  0b001..4.1 V
 *  0b010..4.2 V
 *  0b011..4.3 V
 *  0b100..4.4 V
 *  0b101..4.5 V
 *  0b110..4.6 V
 *  0b111..4.7 V
 */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Override Enable
 *  0b0..Results of VBUS_VALID and session valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND
 *  0b1..Override values for VBUS_VALID, AVALID, BVALID, and SESSEND
 */
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override Value for SESSEND
 *  0b0..Overridden to 0
 *  0b1..Overridden to 1
 */
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid
 *  0b0..Overridden to 0
 *  0b1..Overridden to 1
 */
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid
 *  0b0..Overridden to 0
 *  0b1..Overridden to 1
 */
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal
 *  0b0..Overridden to 0
 *  0b1..Overridden to 1
 */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - VBUS_VALID Source Selection
 *  0b0..VBUS_VALID comparator results
 *  0b1..VBUS_VALID_3V detector results
 */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection
 *  0b00..VBUS_VALID comparator results
 *  0b01..Session valid comparator results
 *  0b10..Session valid comparator result
 *  0b11..Reserved; do not use
 */
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - VBUS_VALID Comparator Selection
 *  0b0..VBUS_VALID comparator for the VBUS_VALID results
 *  0b1..Session end comparator for the VBUS_VALID results
 */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)

#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - VBUS_VALID Comparator Enable
 *  0b000..Disable the VBUS_VALID comparator
 *  0b001..Enable the SESS_VALID comparator
 *  0b010..Enable 3V detection
 */
#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)

#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - VBUS Discharge Resistor Controller
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)

#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Charger Resistor Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
/*! @} */

/*! @name USB1_VBUS_DETECT_SET - USBPHY VBUS Detect Control */
/*! @{ */

#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID Threshold */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Override Enable */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override Value for SESSEND */
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - VBUS_VALID Source Selection */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - VBUS_VALID Comparator Selection */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - VBUS_VALID Comparator Enable */
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - VBUS Discharge Resistor Controller */
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Charger Resistor Enable */
#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
/*! @} */

/*! @name USB1_VBUS_DETECT_CLR - USBPHY VBUS Detect Control */
/*! @{ */

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID Threshold */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Override Enable */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override Value for SESSEND */
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - VBUS_VALID Source Selection */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - VBUS_VALID Comparator Selection */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - VBUS_VALID Comparator Enable */
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - VBUS Discharge Resistor Controller */
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Charger Resistor Enable */
#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
/*! @} */

/*! @name USB1_VBUS_DETECT_TOG - USBPHY VBUS Detect Control */
/*! @{ */

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID Threshold */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Override Enable */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override Value for SESSEND */
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - VBUS_VALID Source Selection */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - VBUS_VALID Comparator Selection */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - VBUS_VALID Comparator Enable */
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - VBUS Discharge Resistor Controller */
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Charger Resistor Enable */
#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
/*! @} */

/*! @name USB1_VBUS_DET_STAT - USBPHY VBUS Detector Status */
/*! @{ */

#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
/*! SESSEND - Session End Indicator
 *  0b0..Above threshold
 *  0b1..Below threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)

#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
/*! BVALID - B-Device Session Valid Status
 *  0b0..Below threshold
 *  0b1..Above threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)

#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
/*! AVALID - A-Device Session Valid Status
 *  0b0..Below threshold
 *  0b1..Above threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)

#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
/*! VBUS_VALID - VBUS Voltage Status
 *  0b0..Below threshold
 *  0b1..Above threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)

#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status
 *  0b0..Below threshold
 *  0b1..Above threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
/*! @} */

/*! @name USB1_CHRG_DETECT - USBPHY Charger Detect Control */
/*! @{ */

#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK   (0x4U)
#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT  (2U)
/*! PULLUP_DP - DP Pullup Resistor Enable Override Control
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)

#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK   (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT  (23U)
/*! BGR_IBIAS - BGR Bias
 *  0b0..Local bias
 *  0b1..Bandgap bias
 */
#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK)

#define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK      (0x80000000U)
#define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT     (31U)
/*! DCDSEL - DCD Selection
 *  0b0..Fields in the USB1_CHRG_DETECT register
 *  0b1..Fields and state machines in the USBHSDCD module
 */
#define USBPHY_USB1_CHRG_DETECT_DCDSEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK)
/*! @} */

/*! @name USB1_CHRG_DETECT_SET - USBPHY Charger Detect Control */
/*! @{ */

#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */
#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)

#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U)
/*! BGR_IBIAS - BGR Bias */
#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK)

#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK  (0x80000000U)
#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U)
/*! DCDSEL - DCD Selection */
#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK)
/*! @} */

/*! @name USB1_CHRG_DETECT_CLR - USBPHY Charger Detect Control */
/*! @{ */

#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */
#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)

#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U)
/*! BGR_IBIAS - BGR Bias */
#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK)

#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK  (0x80000000U)
#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U)
/*! DCDSEL - DCD Selection */
#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK)
/*! @} */

/*! @name USB1_CHRG_DETECT_TOG - USBPHY Charger Detect Control */
/*! @{ */

#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */
#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)

#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U)
/*! BGR_IBIAS - BGR Bias */
#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK)

#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK  (0x80000000U)
#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U)
/*! DCDSEL - DCD Selection */
#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK)
/*! @} */

/*! @name USB1_CHRG_DET_STAT - USBPHY Charger Detect Status */
/*! @{ */

#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output
 *  0b0..Not detected
 *  0b1..Detected
 */
#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)

#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output
 *  0b0..SDP detected
 *  0b1..Charging port detected
 */
#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)

#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK  (0x4U)
#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U)
/*! DN_STATE - DN State
 *  0b0..< 0.8 V
 *  0b1..> 2.0 V
 */
#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK)

#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
/*! DP_STATE - DP State
 *  0b0..< 0.8 V
 *  0b1..> 2.0 V
 */
#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)

#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output
 *  0b0..CDP detected
 *  0b1..DCP detected
 */
#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
/*! @} */

/*! @name ANACTRL - USBPHY Analog Control */
/*! @{ */

#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
/*! DEV_PULLDOWN - Device Pulldown
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
/*! @} */

/*! @name ANACTRL_SET - USBPHY Analog Control */
/*! @{ */

#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
/*! DEV_PULLDOWN - Device Pulldown */
#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
/*! @} */

/*! @name ANACTRL_CLR - USBPHY Analog Control */
/*! @{ */

#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
/*! DEV_PULLDOWN - Device Pulldown */
#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
/*! @} */

/*! @name ANACTRL_TOG - USBPHY Analog Control */
/*! @{ */

#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
/*! DEV_PULLDOWN - Device Pulldown */
#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
/*! @} */

/*! @name USB1_LOOPBACK - USBPHY Loopback Control and Status */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI Test Start
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)

#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK  (0x2U)
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI Digital Test 0
 *  0b0..Pseudorandom mode
 *  0b1..Pulse mode
 */
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK  (0x4U)
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI Digital Test 1
 *  0b0..Pulse mode
 *  0b1..Pseudorandom mode
 */
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - Loopback Test HS Mode
 *  0b0..FS
 *  0b1..HS
 */
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - Loopback Test LS Mode
 *  0b0..HS or FS (defined by TSTI1_TX_HS)
 *  0b1..LS
 */
#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK     (0x20U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT    (5U)
/*! TSTI_TX_EN - Loopback Test Transmit Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK    (0x40U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
/*! TSTI_TX_HIZ - Loopback Test Transmit Hi-Z
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)

#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK  (0x80U)
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO Digital Test 0
 *  0b0..Passing
 *  0b1..Not passing
 */
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK  (0x100U)
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO Digital Test 1
 *  0b0..Not passing
 *  0b1..Passing
 */
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - Loopback Test HS-FS Mode Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)

#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK         (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT        (16U)
/*! TSTPKT - Testing Packet */
#define USBPHY_USB1_LOOPBACK_TSTPKT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_SET - USBPHY Loopback Control and Status */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI Test Start */
#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)

#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI Digital Test 0 */
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI Digital Test 1 */
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - Loopback Test HS Mode */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - Loopback Test LS Mode */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - Loopback Test Transmit Enable */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - Loopback Test Transmit Hi-Z */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)

#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO Digital Test 0 */
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO Digital Test 1 */
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - Loopback Test HS-FS Mode Enable */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK     (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT    (16U)
/*! TSTPKT - Testing Packet */
#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_CLR - USBPHY Loopback Control and Status */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI Test Start */
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI Digital Test 0 */
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI Digital Test 1 */
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - Loopback Test HS Mode */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - Loopback Test LS Mode */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - Loopback Test Transmit Enable */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - Loopback Test Transmit Hi-Z */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO Digital Test 0 */
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO Digital Test 1 */
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - Loopback Test HS-FS Mode Enable */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK     (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT    (16U)
/*! TSTPKT - Testing Packet */
#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_TOG - USBPHY Loopback Control and Status */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI Test Start */
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI Digital Test 0 */
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI Digital Test 1 */
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - Loopback Test HS Mode */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - Loopback Test LS Mode */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - Loopback Test Transmit Enable */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - Loopback Test Transmit Hi-Z */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO Digital Test 0 */
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO Digital Test 1 */
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - Loopback Test HS-FS Mode Enable */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK     (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT    (16U)
/*! TSTPKT - Testing Packet */
#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_HSFSCNT - USBPHY Loopback Packet Number Selection */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - Loopback Test HS Packet Number */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)

#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - Loopback Test FS Packet Number */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_HSFSCNT_SET - USBPHY Loopback Packet Number Selection */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - Loopback Test HS Packet Number */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)

#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - Loopback Test FS Packet Number */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_HSFSCNT_CLR - USBPHY Loopback Packet Number Selection */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - Loopback Test HS Packet Number */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)

#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - Loopback Test FS Packet Number */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_HSFSCNT_TOG - USBPHY Loopback Packet Number Selection */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - Loopback Test HS Packet Number */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)

#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - Loopback Test FS Packet Number */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
/*! @} */

/*! @name TRIM_OVERRIDE_EN - USBPHY Trim Override Enable */
/*! @{ */

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - Override Enable for HS RX Squelch Rise Time Delay Trim
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - Override Enable for the HS TX Output Current Trim
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - Override Enable for DP Series Termination Trim
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - Override Enable for DN Series Termination Trim
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override Enable for Bandgap Voltage Adjustment
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override Enable for Bias Current Control
 *  0b0..Disables
 *  0b1..Enables
 */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - Bandgap Voltage Adjustment Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - Bias Current Control Adjustment Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - HS RX Squelch Rise Time Delay Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY
 *  0b0000..Maximum current; approximately 19% above nominal
 *  0b0111..Nominal
 *  0b1111..Minimum current; approximately 19% below nominal
 */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - DN Series Termination Resistance Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */

/*! @name TRIM_OVERRIDE_EN_SET - USBPHY Trim Override Enable */
/*! @{ */

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - Override Enable for HS RX Squelch Rise Time Delay Trim */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - Override Enable for the HS TX Output Current Trim */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - Override Enable for DP Series Termination Trim */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - Override Enable for DN Series Termination Trim */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override Enable for Bandgap Voltage Adjustment */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override Enable for Bias Current Control */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - Bandgap Voltage Adjustment Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - Bias Current Control Adjustment Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - HS RX Squelch Rise Time Delay Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - DN Series Termination Resistance Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */

/*! @name TRIM_OVERRIDE_EN_CLR - USBPHY Trim Override Enable */
/*! @{ */

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - Override Enable for HS RX Squelch Rise Time Delay Trim */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - Override Enable for the HS TX Output Current Trim */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - Override Enable for DP Series Termination Trim */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - Override Enable for DN Series Termination Trim */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override Enable for Bandgap Voltage Adjustment */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override Enable for Bias Current Control */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - Bandgap Voltage Adjustment Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - Bias Current Control Adjustment Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - HS RX Squelch Rise Time Delay Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - DN Series Termination Resistance Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */

/*! @name TRIM_OVERRIDE_EN_TOG - USBPHY Trim Override Enable */
/*! @{ */

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - Override Enable for HS RX Squelch Rise Time Delay Trim */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - Override Enable for the HS TX Output Current Trim */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - Override Enable for DP Series Termination Trim */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - Override Enable for DN Series Termination Trim */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override Enable for Bandgap Voltage Adjustment */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override Enable for Bias Current Control */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - Bandgap Voltage Adjustment Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - Bias Current Control Adjustment Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - HS RX Squelch Rise Time Delay Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - DN Series Termination Resistance Trim Bits from Outside USBPHY */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBPHY_Register_Masks */


/* USBPHY - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral USBPHY base address */
  #define USBPHY_BASE                              (0x50414000u)
  /** Peripheral USBPHY base address */
  #define USBPHY_BASE_NS                           (0x40414000u)
  /** Peripheral USBPHY base pointer */
  #define USBPHY                                   ((USBPHY_Type *)USBPHY_BASE)
  /** Peripheral USBPHY base pointer */
  #define USBPHY_NS                                ((USBPHY_Type *)USBPHY_BASE_NS)
  /** Array initializer of USBPHY peripheral base addresses */
  #define USBPHY_BASE_ADDRS                        { USBPHY_BASE }
  /** Array initializer of USBPHY peripheral base pointers */
  #define USBPHY_BASE_PTRS                         { USBPHY }
  /** Array initializer of USBPHY peripheral base addresses */
  #define USBPHY_BASE_ADDRS_NS                     { USBPHY_BASE_NS }
  /** Array initializer of USBPHY peripheral base pointers */
  #define USBPHY_BASE_PTRS_NS                      { USBPHY_NS }
#else
  /** Peripheral USBPHY base address */
  #define USBPHY_BASE                              (0x40414000u)
  /** Peripheral USBPHY base pointer */
  #define USBPHY                                   ((USBPHY_Type *)USBPHY_BASE)
  /** Array initializer of USBPHY peripheral base addresses */
  #define USBPHY_BASE_ADDRS                        { USBPHY_BASE }
  /** Array initializer of USBPHY peripheral base pointers */
  #define USBPHY_BASE_PTRS                         { USBPHY }
#endif
/* Backward compatibility */
#define USBPHY_CTRL_ENDEVPLUGINDET_MASK     USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT    USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define USBPHY_CTRL_ENDEVPLUGINDET(x)       USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define USBPHY_TX_TXCAL45DM_MASK            USBPHY_TX_TXCAL45DN_MASK
#define USBPHY_TX_TXCAL45DM_SHIFT           USBPHY_TX_TXCAL45DN_SHIFT
#define USBPHY_TX_TXCAL45DM(x)              USBPHY_TX_TXCAL45DN(x)


/*!
 * @}
 */ /* end of group USBPHY_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USDHC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
 * @{
 */

/** USDHC - Register Layout Typedef */
typedef struct {
  __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
  __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
  __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
  __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
  __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
  __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
  __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
  __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
  __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
  __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
  __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
  __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
  __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
  __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
  __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
  __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
  __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
  __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
  __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
       uint8_t RESERVED_0[4];
  __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
  __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
  __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
       uint8_t RESERVED_1[4];
  __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
  __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
  __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
       uint8_t RESERVED_2[4];
  __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
  __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
       uint8_t RESERVED_3[72];
  __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
  __IO uint32_t MMC_BOOT;                          /**< eMMC Boot, offset: 0xC4 */
  __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
  __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
       uint8_t RESERVED_4[48];
  __I  uint32_t CQVER;                             /**< Command Queuing Version, offset: 0x100 */
  __IO uint32_t CQCAP;                             /**< Command Queuing Capabilities, offset: 0x104 */
  __IO uint32_t CQCFG;                             /**< Command Queuing Configuration, offset: 0x108 */
  __IO uint32_t CQCTL;                             /**< Command Queuing Control, offset: 0x10C */
  __IO uint32_t CQIS;                              /**< Command Queuing Interrupt Status, offset: 0x110 */
  __IO uint32_t CQISTE;                            /**< Command Queuing Interrupt Status Enable, offset: 0x114 */
  __IO uint32_t CQISGE;                            /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */
  __IO uint32_t CQIC;                              /**< Command Queuing Interrupt Coalescing, offset: 0x11C */
  __IO uint32_t CQTDLBA;                           /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */
  __IO uint32_t CQTDLBAU;                          /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */
  __IO uint32_t CQTDBR;                            /**< Command Queuing Task Doorbell, offset: 0x128 */
  __IO uint32_t CQTCN;                             /**< Command Queuing Task Completion Notification, offset: 0x12C */
  __I  uint32_t CQDQS;                             /**< Command Queuing Device Queue Status, offset: 0x130 */
  __I  uint32_t CQDPT;                             /**< Command Queuing Device Pending Tasks, offset: 0x134 */
  __IO uint32_t CQTCLR;                            /**< Command Queuing Task Clear, offset: 0x138 */
       uint8_t RESERVED_5[4];
  __IO uint32_t CQSSC1;                            /**< Command Queuing Send Status Configuration 1, offset: 0x140 */
  __IO uint32_t CQSSC2;                            /**< Command Queuing Send Status Configuration 2, offset: 0x144 */
  __I  uint32_t CQCRDCT;                           /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */
       uint8_t RESERVED_6[4];
  __IO uint32_t CQRMEM;                            /**< Command Queuing Response Mode Error Mask, offset: 0x150 */
  __I  uint32_t CQTERRI;                           /**< Command Queuing Task Error Information, offset: 0x154 */
  __I  uint32_t CQCRI;                             /**< Command Queuing Command Response Index, offset: 0x158 */
  __I  uint32_t CQCRA;                             /**< Command Queuing Command Response Argument, offset: 0x15C */
} USDHC_Type;

/* ----------------------------------------------------------------------------
   -- USDHC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USDHC_Register_Masks USDHC Register Masks
 * @{
 */

/*! @name DS_ADDR - DMA System Address */
/*! @{ */

#define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
#define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
/*! DS_ADDR - System address */
#define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
/*! @} */

/*! @name BLK_ATT - Block Attributes */
/*! @{ */

#define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
#define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
/*! BLKSIZE - Transfer block size
 *  0b1000000000000..4096 bytes
 *  0b0100000000000..2048 bytes
 *  0b0001000000000..512 bytes
 *  0b0000111111111..511 bytes
 *  0b0000000000100..4 bytes
 *  0b0000000000011..3 bytes
 *  0b0000000000010..2 bytes
 *  0b0000000000001..1 byte
 *  0b0000000000000..No data transfer
 */
#define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

#define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
#define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
/*! BLKCNT - Blocks count for current transfer
 *  0b1111111111111111..65535 blocks
 *  0b0000000000000010..2 blocks
 *  0b0000000000000001..1 block
 *  0b0000000000000000..Stop count
 */
#define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
/*! @} */

/*! @name CMD_ARG - Command Argument */
/*! @{ */

#define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
#define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
/*! CMDARG - Command argument */
#define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
/*! @} */

/*! @name CMD_XFR_TYP - Command Transfer Type */
/*! @{ */

#define USDHC_CMD_XFR_TYP_DMAEN_MASK             (0x1U)
#define USDHC_CMD_XFR_TYP_DMAEN_SHIFT            (0U)
/*! DMAEN - DMAEN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_DMAEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & USDHC_CMD_XFR_TYP_DMAEN_MASK)

#define USDHC_CMD_XFR_TYP_BCEN_MASK              (0x2U)
#define USDHC_CMD_XFR_TYP_BCEN_SHIFT             (1U)
/*! BCEN - BCEN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_BCEN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & USDHC_CMD_XFR_TYP_BCEN_MASK)

#define USDHC_CMD_XFR_TYP_AC12EN_MASK            (0x4U)
#define USDHC_CMD_XFR_TYP_AC12EN_SHIFT           (2U)
/*! AC12EN - AC12EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_AC12EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC12EN_MASK)

#define USDHC_CMD_XFR_TYP_DDR_EN_MASK            (0x8U)
#define USDHC_CMD_XFR_TYP_DDR_EN_SHIFT           (3U)
/*! DDR_EN - DDR_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_DDR_EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & USDHC_CMD_XFR_TYP_DDR_EN_MASK)

#define USDHC_CMD_XFR_TYP_DTDSEL_MASK            (0x10U)
#define USDHC_CMD_XFR_TYP_DTDSEL_SHIFT           (4U)
/*! DTDSEL - DTDSEL
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_DTDSEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DTDSEL_MASK)

#define USDHC_CMD_XFR_TYP_MSBSEL_MASK            (0x20U)
#define USDHC_CMD_XFR_TYP_MSBSEL_SHIFT           (5U)
/*! MSBSEL - MSBSEL
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_MSBSEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & USDHC_CMD_XFR_TYP_MSBSEL_MASK)

#define USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK        (0x40U)
#define USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT       (6U)
/*! NIBBLE_POS - NIBBLE_POS
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_NIBBLE_POS(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK)

#define USDHC_CMD_XFR_TYP_AC23EN_MASK            (0x80U)
#define USDHC_CMD_XFR_TYP_AC23EN_SHIFT           (7U)
/*! AC23EN - AC23EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_AC23EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC23EN_MASK)

#define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
/*! RSPTYP - Response type select
 *  0b00..No response
 *  0b01..Response length 136
 *  0b10..Response length 48
 *  0b11..Response length 48, check busy after response
 */
#define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

#define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
/*! CCCEN - Command CRC check enable
 *  0b1..Enables command CRC check
 *  0b0..Disables command CRC check
 */
#define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

#define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
#define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
/*! CICEN - Command index check enable
 *  0b1..Enables command index check
 *  0b0..Disable command index check
 */
#define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

#define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
/*! DPSEL - Data present select
 *  0b1..Data present
 *  0b0..No data present
 */
#define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

#define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
/*! CMDTYP - Command type
 *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
 *  0b10..Resume CMD52 for writing function select in CCCR
 *  0b01..Suspend CMD52 for writing bus suspend in CCCR
 *  0b00..Normal other commands
 */
#define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

#define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
/*! CMDINX - Command index */
#define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
/*! @} */

/*! @name CMD_RSP0 - Command Response0 */
/*! @{ */

#define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
/*! CMDRSP0 - Command response 0 */
#define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
/*! @} */

/*! @name CMD_RSP1 - Command Response1 */
/*! @{ */

#define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
/*! CMDRSP1 - Command response 1 */
#define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/*! @} */

/*! @name CMD_RSP2 - Command Response2 */
/*! @{ */

#define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
/*! CMDRSP2 - Command response 2 */
#define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/*! @} */

/*! @name CMD_RSP3 - Command Response3 */
/*! @{ */

#define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
/*! CMDRSP3 - Command response 3 */
#define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
/*! @} */

/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
/*! @{ */

#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
/*! DATCONT - Data content */
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
/*! @} */

/*! @name PRES_STATE - Present State */
/*! @{ */

#define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
#define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
/*! CIHB - Command inhibit (CMD)
 *  0b1..Cannot issue command
 *  0b0..Can issue command using only CMD line
 */
#define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

#define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
#define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
/*! CDIHB - Command Inhibit Data (DATA)
 *  0b1..Cannot issue command that uses the DATA line
 *  0b0..Can issue command that uses the DATA line
 */
#define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

#define USDHC_PRES_STATE_DLA_MASK                (0x4U)
#define USDHC_PRES_STATE_DLA_SHIFT               (2U)
/*! DLA - Data line active
 *  0b1..DATA line active
 *  0b0..DATA line inactive
 */
#define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

#define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
#define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
/*! SDSTB - SD clock stable
 *  0b1..Clock is stable.
 *  0b0..Clock is changing frequency and not stable.
 */
#define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

#define USDHC_PRES_STATE_WTA_MASK                (0x100U)
#define USDHC_PRES_STATE_WTA_SHIFT               (8U)
/*! WTA - Write transfer active
 *  0b1..Transferring data
 *  0b0..No valid data
 */
#define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

#define USDHC_PRES_STATE_RTA_MASK                (0x200U)
#define USDHC_PRES_STATE_RTA_SHIFT               (9U)
/*! RTA - Read transfer active
 *  0b1..Transferring data
 *  0b0..No valid data
 */
#define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

#define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
#define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
/*! BWEN - Buffer write enable
 *  0b1..Write enable
 *  0b0..Write disable
 */
#define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

#define USDHC_PRES_STATE_BREN_MASK               (0x800U)
#define USDHC_PRES_STATE_BREN_SHIFT              (11U)
/*! BREN - Buffer read enable
 *  0b1..Read enable
 *  0b0..Read disable
 */
#define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

#define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
#define USDHC_PRES_STATE_RTR_SHIFT               (12U)
/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode, and eMMC HS200 mode)
 *  0b1..Sampling clock needs re-tuning
 *  0b0..Fixed or well tuned sampling clock
 */
#define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

#define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
#define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
/*! TSCD - Tap select change done
 *  0b1..Delay cell select change is finished.
 *  0b0..Delay cell select change is not finished.
 */
#define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

#define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
#define USDHC_PRES_STATE_CINST_SHIFT             (16U)
/*! CINST - Card inserted
 *  0b1..Card inserted
 *  0b0..Power on reset or no card
 */
#define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

#define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
#define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
/*! CDPL - Card detect pin level
 *  0b1..Card present (CD_B = 0)
 *  0b0..No card present (CD_B = 1)
 */
#define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

#define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
#define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
/*! WPSPL - Write protect switch pin level
 *  0b1..Write enabled (WP = 0)
 *  0b0..Write protected (WP = 1)
 */
#define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

#define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
#define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
/*! CLSL - CMD line signal level */
#define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

#define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
#define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
/*! DLSL - DATA[7:0] line signal level
 *  0b10000000..Data 7 line signal level
 *  0b01000000..Data 6 line signal level
 *  0b00100000..Data 5 line signal level
 *  0b00010000..Data 4 line signal level
 *  0b00001000..Data 3 line signal level
 *  0b00000100..Data 2 line signal level
 *  0b00000010..Data 1 line signal level
 *  0b00000001..Data 0 line signal level
 */
#define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
/*! @} */

/*! @name PROT_CTRL - Protocol Control */
/*! @{ */

#define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
#define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
/*! DTW - Data transfer width
 *  0b10..8-bit mode
 *  0b01..4-bit mode
 *  0b00..1-bit mode
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

#define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
#define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
/*! D3CD - DATA3 as card detection pin
 *  0b1..DATA3 as card detection pin
 *  0b0..DATA3 does not monitor card insertion
 */
#define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

#define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
#define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
/*! EMODE - Endian mode
 *  0b00..Big endian mode
 *  0b01..Half word big endian mode
 *  0b10..Little endian mode
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

#define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
#define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
/*! DMASEL - DMA select
 *  0b00..No DMA or simple DMA is selected.
 *  0b01..ADMA1 is selected.
 *  0b10..ADMA2 is selected.
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

#define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
#define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
/*! SABGREQ - Stop at block gap request
 *  0b1..Stop
 *  0b0..Transfer
 */
#define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

#define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
#define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
/*! CREQ - Continue request
 *  0b1..Restart
 *  0b0..No effect
 */
#define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

#define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
#define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
/*! RWCTL - Read wait control
 *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
 *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
 */
#define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

#define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
#define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
/*! IABG - Interrupt at block gap
 *  0b1..Enables interrupt at block gap
 *  0b0..Disables interrupt at block gap
 */
#define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
/*! RD_DONE_NO_8CLK - Read performed number 8 clock */
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

#define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
#define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
/*! WECINT - Wakeup event enable on card interrupt
 *  0b1..Enables wakeup event enable on card interrupt
 *  0b0..Disables wakeup event enable on card interrupt
 */
#define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

#define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
#define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
/*! WECINS - Wakeup event enable on SD card insertion
 *  0b1..Enable wakeup event enable on SD card insertion
 *  0b0..Disable wakeup event enable on SD card insertion
 */
#define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

#define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
#define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
/*! WECRM - Wakeup event enable on SD card removal
 *  0b1..Enables wakeup event enable on SD card removal
 *  0b0..Disables wakeup event enable on SD card removal
 */
#define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
/*! NON_EXACT_BLK_RD - Non-exact block read
 *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
 *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
 */
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
/*! @} */

/*! @name SYS_CTRL - System Control */
/*! @{ */

#define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
#define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
/*! DVS - Divisor
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

#define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
#define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
/*! SDCLKFS - SDCLK frequency select */
#define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

#define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
#define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
/*! DTOCV - Data timeout counter value
 *  0b1111..SDCLK x 2 31, recommend to use for HS400 mode
 *  0b1110..SDCLK x 2 30, recommend to use for HS200 and SDR104 mode
 *  0b1101..SDCLK x 2 29, recommend to use for supported speed modes except HS200, HS400, SDR104 mode
 *  0b0011..SDCLK x 2 19
 *  0b0010..SDCLK x 2 18
 *  0b0001..SDCLK x 2 33
 *  0b0000..SDCLK x 2 32
 */
#define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

#define USDHC_SYS_CTRL_RST_FIFO_MASK             (0x400000U)
#define USDHC_SYS_CTRL_RST_FIFO_SHIFT            (22U)
/*! RST_FIFO - Reset the async FIFO */
#define USDHC_SYS_CTRL_RST_FIFO(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK)

#define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
/*! IPP_RST_N - Hardware reset */
#define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

#define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
#define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
/*! RSTA - Software reset for all
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

#define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
#define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
/*! RSTC - Software reset for CMD line
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

#define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
#define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
/*! RSTD - Software reset for data line
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

#define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
#define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
/*! INITA - Initialization active */
#define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

#define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
#define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
/*! RSTT - Reset tuning */
#define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
/*! @} */

/*! @name INT_STATUS - Interrupt Status */
/*! @{ */

#define USDHC_INT_STATUS_CC_MASK                 (0x1U)
#define USDHC_INT_STATUS_CC_SHIFT                (0U)
/*! CC - Command complete
 *  0b1..Command complete
 *  0b0..Command not complete
 */
#define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

#define USDHC_INT_STATUS_TC_MASK                 (0x2U)
#define USDHC_INT_STATUS_TC_SHIFT                (1U)
/*! TC - Transfer complete
 *  0b1..Transfer complete
 *  0b0..Transfer does not complete
 */
#define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

#define USDHC_INT_STATUS_BGE_MASK                (0x4U)
#define USDHC_INT_STATUS_BGE_SHIFT               (2U)
/*! BGE - Block gap event
 *  0b1..Transaction stopped at block gap
 *  0b0..No block gap event
 */
#define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

#define USDHC_INT_STATUS_DINT_MASK               (0x8U)
#define USDHC_INT_STATUS_DINT_SHIFT              (3U)
/*! DINT - DMA interrupt
 *  0b1..DMA interrupt is generated.
 *  0b0..No DMA interrupt
 */
#define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

#define USDHC_INT_STATUS_BWR_MASK                (0x10U)
#define USDHC_INT_STATUS_BWR_SHIFT               (4U)
/*! BWR - Buffer write ready
 *  0b1..Ready to write buffer
 *  0b0..Not ready to write buffer
 */
#define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

#define USDHC_INT_STATUS_BRR_MASK                (0x20U)
#define USDHC_INT_STATUS_BRR_SHIFT               (5U)
/*! BRR - Buffer read ready
 *  0b1..Ready to read buffer
 *  0b0..Not ready to read buffer
 */
#define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

#define USDHC_INT_STATUS_CINS_MASK               (0x40U)
#define USDHC_INT_STATUS_CINS_SHIFT              (6U)
/*! CINS - Card insertion
 *  0b1..Card inserted
 *  0b0..Card state unstable or removed
 */
#define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

#define USDHC_INT_STATUS_CRM_MASK                (0x80U)
#define USDHC_INT_STATUS_CRM_SHIFT               (7U)
/*! CRM - Card removal
 *  0b1..Card removed
 *  0b0..Card state unstable or inserted
 */
#define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

#define USDHC_INT_STATUS_CINT_MASK               (0x100U)
#define USDHC_INT_STATUS_CINT_SHIFT              (8U)
/*! CINT - Card interrupt
 *  0b1..Generate card interrupt
 *  0b0..No card interrupt
 */
#define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

#define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
#define USDHC_INT_STATUS_RTE_SHIFT               (12U)
/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode)
 *  0b1..Re-tuning should be performed.
 *  0b0..Re-tuning is not required.
 */
#define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

#define USDHC_INT_STATUS_TP_MASK                 (0x2000U)
#define USDHC_INT_STATUS_TP_SHIFT                (13U)
/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode) */
#define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

#define USDHC_INT_STATUS_CQI_MASK                (0x4000U)
#define USDHC_INT_STATUS_CQI_SHIFT               (14U)
/*! CQI - Command queuing interrupt */
#define USDHC_INT_STATUS_CQI(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK)

#define USDHC_INT_STATUS_ERR_INT_STATUS_MASK     (0x8000U)
#define USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT    (15U)
/*! ERR_INT_STATUS - Error Interrupt Status */
#define USDHC_INT_STATUS_ERR_INT_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & USDHC_INT_STATUS_ERR_INT_STATUS_MASK)

#define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
#define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
/*! CTOE - Command timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

#define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
#define USDHC_INT_STATUS_CCE_SHIFT               (17U)
/*! CCE - Command CRC error
 *  0b1..CRC error generated
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

#define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
#define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
/*! CEBE - Command end bit error
 *  0b1..End bit error generated
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

#define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
#define USDHC_INT_STATUS_CIE_SHIFT               (19U)
/*! CIE - Command index error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

#define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
#define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
/*! DTOE - Data timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

#define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
#define USDHC_INT_STATUS_DCE_SHIFT               (21U)
/*! DCE - Data CRC error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

#define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
#define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
/*! DEBE - Data end bit error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

#define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
#define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
/*! AC12E - Auto CMD12 error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

#define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
#define USDHC_INT_STATUS_TNE_SHIFT               (26U)
/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode) */
#define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

#define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
#define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
/*! DMAE - DMA error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
/*! @} */

/*! @name INT_STATUS_EN - Interrupt Status Enable */
/*! @{ */

#define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
#define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
/*! CCSEN - Command complete status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

#define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
#define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
/*! TCSEN - Transfer complete status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

#define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
#define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
/*! BGESEN - Block gap event status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

#define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
/*! DINTSEN - DMA interrupt status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

#define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
/*! BWRSEN - Buffer write ready status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

#define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
/*! BRRSEN - Buffer read ready status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

#define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
/*! CINSSEN - Card insertion status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

#define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
/*! CRMSEN - Card removal status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

#define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
/*! CINTSEN - Card interrupt status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

#define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
#define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
/*! RTESEN - Re-tuning event status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

#define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x2000U)
#define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (13U)
/*! TPSEN - Tuning pass status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

#define USDHC_INT_STATUS_EN_CQISEN_MASK          (0x4000U)
#define USDHC_INT_STATUS_EN_CQISEN_SHIFT         (14U)
/*! CQISEN - Command queuing status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CQISEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK)

#define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
/*! CTOESEN - Command timeout error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

#define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
#define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
/*! CCESEN - Command CRC error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

#define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
/*! CEBESEN - Command end bit error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

#define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
#define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
/*! CIESEN - Command index error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

#define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
/*! DTOESEN - Data timeout error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

#define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
#define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
/*! DCESEN - Data CRC error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

#define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
/*! DEBESEN - Data end bit error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

#define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
/*! AC12ESEN - Auto CMD12 error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

#define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
#define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
/*! TNESEN - Tuning error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

#define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
/*! DMAESEN - DMA error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
/*! @} */

/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
/*! @{ */

#define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
/*! CCIEN - Command complete interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

#define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
/*! TCIEN - Transfer complete interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
/*! BGEIEN - Block gap event interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
/*! DINTIEN - DMA interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
/*! BWRIEN - Buffer write ready interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
/*! BRRIEN - Buffer read ready interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
/*! CINSIEN - Card insertion interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
/*! CRMIEN - Card removal interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
/*! CINTIEN - Card interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
/*! RTEIEN - Re-tuning event interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x2000U)
#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (13U)
/*! TPIEN - Tuning pass interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CQIIEN_MASK          (0x4000U)
#define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT         (14U)
/*! CQIIEN - Command queuing signal enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CQIIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
/*! CTOEIEN - Command timeout error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
/*! CCEIEN - Command CRC error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
/*! CEBEIEN - Command end bit error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
/*! CIEIEN - Command index error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
/*! DTOEIEN - Data timeout error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
/*! DCEIEN - Data CRC error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
/*! DEBEIEN - Data end bit error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
/*! AC12EIEN - Auto CMD12 error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
/*! TNEIEN - Tuning error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
/*! DMAEIEN - DMA error interrupt enable
 *  0b1..Enable
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
/*! @} */

/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
/*! @{ */

#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
/*! AC12NE - Auto CMD12 not executed
 *  0b1..Not executed
 *  0b0..Executed
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
/*! AC12TOE - Auto CMD12 / 23 timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x4U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (2U)
/*! AC12CE - Auto CMD12 / 23 CRC error
 *  0b1..CRC error met in Auto CMD12/23 response
 *  0b0..No CRC error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x8U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U)
/*! AC12EBE - Auto CMD12 / 23 end bit error
 *  0b1..End bit error generated
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
/*! AC12IE - Auto CMD12 / 23 index error
 *  0b1..Error, the CMD index in response is not CMD12/23
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
/*! CNIBAC12E - Command not issued by Auto CMD12 error
 *  0b1..Not issued
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
/*! EXECUTE_TUNING - Execute tuning
 *  0b1..Start tuning procedure
 *  0b0..Tuning procedure is aborted
 */
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
/*! SMP_CLK_SEL - Sample clock select
 *  0b1..Tuned clock is used to sample data
 *  0b0..Fixed clock is used to sample data
 */
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
/*! @} */

/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
/*! @{ */

#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
/*! SDR50_SUPPORT - SDR50 support */
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
/*! SDR104_SUPPORT - SDR104 support */
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
/*! DDR50_SUPPORT - DDR50 support */
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
/*! USE_TUNING_SDR50 - Use Tuning for SDR50
 *  0b1..SDR50 supports tuning
 *  0b0..SDR50 does not support tuning
 */
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

#define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
#define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
/*! MBL - Max block length
 *  0b000..512 bytes
 *  0b001..1024 bytes
 *  0b010..2048 bytes
 *  0b011..4096 bytes
 */
#define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

#define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
/*! ADMAS - ADMA support
 *  0b1..Advanced DMA supported
 *  0b0..Advanced DMA not supported
 */
#define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

#define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
#define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
/*! HSS - High speed support
 *  0b1..High speed supported
 *  0b0..High speed not supported
 */
#define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

#define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
/*! DMAS - DMA support
 *  0b1..DMA supported
 *  0b0..DMA not supported
 */
#define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

#define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
#define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
/*! SRS - Suspend / resume support
 *  0b1..Supported
 *  0b0..Not supported
 */
#define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

#define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
#define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
/*! VS33 - Voltage support 3.3 V
 *  0b1..3.3 V supported
 *  0b0..3.3 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

#define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
#define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
/*! VS30 - Voltage support 3.0 V
 *  0b1..3.0 V supported
 *  0b0..3.0 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

#define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
#define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
/*! VS18 - Voltage support 1.8 V
 *  0b1..1.8 V supported
 *  0b0..1.8 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
/*! @} */

/*! @name WTMK_LVL - Watermark Level */
/*! @{ */

#define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
#define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
/*! RD_WML - Read watermark level */
#define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

#define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
#define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
/*! WR_WML - Write watermark level */
#define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
/*! @} */

/*! @name MIX_CTRL - Mixer Control */
/*! @{ */

#define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
#define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
/*! DMAEN - DMA enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

#define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
#define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
/*! BCEN - Block count enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

#define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
#define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
/*! AC12EN - Auto CMD12 enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

#define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
#define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
/*! DDR_EN - Dual data rate mode selection */
#define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

#define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
#define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
/*! DTDSEL - Data transfer direction select
 *  0b1..Read (Card to host)
 *  0b0..Write (Host to card)
 */
#define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

#define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
#define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
/*! MSBSEL - Multi / Single block select
 *  0b1..Multiple blocks
 *  0b0..Single block
 */
#define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

#define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
/*! NIBBLE_POS - Nibble position indication */
#define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

#define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
#define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
/*! AC23EN - Auto CMD23 enable */
#define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

#define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)
 *  0b1..Execute tuning
 *  0b0..Not tuned or tuning completed
 */
#define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
/*! SMP_CLK_SEL - Clock selection
 *  0b1..Tuned clock is used to sample data / cmd
 *  0b0..Fixed clock is used to sample data / cmd
 */
#define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)
 *  0b1..Enable auto tuning
 *  0b0..Disable auto tuning
 */
#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

#define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)
 *  0b1..Feedback clock comes from the ipp_card_clk_out
 *  0b0..Feedback clock comes from the loopback CLK
 */
#define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

#define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
#define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
/*! HS400_MODE - Enable HS400 mode */
#define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)

#define USDHC_MIX_CTRL_EN_HS400_MODE_MASK        (0x8000000U)
#define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT       (27U)
/*! EN_HS400_MODE - Enable enhance HS400 mode */
#define USDHC_MIX_CTRL_EN_HS400_MODE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK)
/*! @} */

/*! @name FORCE_EVENT - Force Event */
/*! @{ */

#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
/*! FEVTAC12NE - Force event auto command 12 not executed */
#define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
/*! FEVTAC12TOE - Force event auto command 12 time out error */
#define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
/*! FEVTAC12CE - Force event auto command 12 CRC error */
#define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
/*! FEVTAC12EBE - Force event Auto Command 12 end bit error */
#define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
/*! FEVTAC12IE - Force event Auto Command 12 index error */
#define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
/*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

#define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
/*! FEVTCTOE - Force event command time out error */
#define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

#define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
/*! FEVTCCE - Force event command CRC error */
#define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

#define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
/*! FEVTCEBE - Force event command end bit error */
#define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

#define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
/*! FEVTCIE - Force event command index error */
#define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

#define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
/*! FEVTDTOE - Force event data time out error */
#define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

#define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
/*! FEVTDCE - Force event data CRC error */
#define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

#define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
/*! FEVTDEBE - Force event data end bit error */
#define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
/*! FEVTAC12E - Force event Auto Command 12 error */
#define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

#define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
/*! FEVTTNE - Force tuning error */
#define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

#define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
/*! FEVTDMAE - Force event DMA error */
#define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

#define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
/*! FEVTCINT - Force event card interrupt */
#define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
/*! @} */

/*! @name ADMA_ERR_STATUS - ADMA Error Status */
/*! @{ */

#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
/*! ADMAES - ADMA error state (when ADMA error is occurred) */
#define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
/*! ADMALME - ADMA length mismatch error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
/*! ADMADCE - ADMA descriptor error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
/*! @} */

/*! @name ADMA_SYS_ADDR - ADMA System Address */
/*! @{ */

#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
/*! ADS_ADDR - ADMA system address */
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
/*! @} */

/*! @name DLL_CTRL - DLL (Delay Line) Control */
/*! @{ */

#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
/*! DLL_CTRL_ENABLE - DLL and delay chain */
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
/*! DLL_CTRL_RESET - DLL reset */
#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! DLL_CTRL_GATE_UPDATE - DLL gate update */
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name DLL_STATUS - DLL Status */
/*! @{ */

#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
/*! DLL_STS_SLV_LOCK - Slave delay-line lock status */
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
/*! DLL_STS_REF_LOCK - Reference DLL lock status */
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
/*! DLL_STS_SLV_SEL - Slave delay line select status */
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
/*! DLL_STS_REF_SEL - Reference delay line select taps */
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
/*! @} */

/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
/*! @{ */

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
/*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
/*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
/*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
/*! NXT_ERR - NXT error */
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
/*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
/*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
/*! TAP_SEL_PRE - TAP_SEL_PRE */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
/*! PRE_ERR - PRE error */
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
/*! @} */

/*! @name STROBE_DLL_CTRL - Strobe DLL control */
/*! @{ */

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
/*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name STROBE_DLL_STATUS - Strobe DLL status */
/*! @{ */

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
/*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
/*! @} */

/*! @name VEND_SPEC - Vendor Specific Register */
/*! @{ */

#define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
#define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
/*! VSELECT - Voltage selection
 *  0b1..Change the voltage to low voltage range , around 1.8 V
 *  0b0..Change the voltage to high voltage range, around 3.0 V
 */
#define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
/*! AC12_WR_CHKBUSY_EN - Check busy enable
 *  0b0..Do not check busy after auto CMD12 for write data packet
 *  0b1..Check busy after auto CMD12 for write data packet
 */
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
/*! FRC_SDCLK_ON - Force CLK
 *  0b0..CLK active or inactive is fully controlled by the hardware.
 *  0b1..Force CLK active
 */
#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
/*! CRC_CHK_DIS - CRC Check Disable
 *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
 *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
 */
#define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
/*! CMD_BYTE_EN - Register byte access for CMD_XFR_TYP
 *  0b0..Disable. MIX_CTRL[7:0] is read/write and CMD_XFR_TYP[7:0] is read-only.
 *  0b1..Enable. MIX_CTRL[7:0] is read-only and CMD_XFR_TYP[7:0] is read/write.
 */
#define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
/*! @} */

/*! @name MMC_BOOT - eMMC Boot */
/*! @{ */

#define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
/*! DTOCV_ACK - DTOCV_ACK
 *  0b0000..SDCLK x 2^32
 *  0b0001..SDCLK x 2^33
 *  0b0010..SDCLK x 2^18
 *  0b0011..SDCLK x 2^19
 *  0b0100..SDCLK x 2^20
 *  0b0101..SDCLK x 2^21
 *  0b0110..SDCLK x 2^22
 *  0b0111..SDCLK x 2^23
 *  0b1110..SDCLK x 2^30
 *  0b1111..SDCLK x 2^31
 */
#define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

#define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
/*! BOOT_ACK - BOOT ACK
 *  0b0..No ack
 *  0b1..Ack
 */
#define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

#define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
/*! BOOT_MODE - Boot mode
 *  0b0..Normal boot
 *  0b1..Alternative boot
 */
#define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

#define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
#define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
/*! BOOT_EN - Boot enable
 *  0b0..Fast boot disable
 *  0b1..Fast boot enable
 */
#define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
/*! AUTO_SABG_EN - Auto stop at block gap */
#define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
/*! DISABLE_TIME_OUT - Time out
 *  0b0..Enable time out
 *  0b1..Disable time out
 */
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
/*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */
#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
/*! @} */

/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
/*! @{ */

#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
/*! CARD_INT_D3_TEST - Card interrupt detection test
 *  0b0..Check the card interrupt only when DATA3 is high.
 *  0b1..Check the card interrupt by ignoring the status of DATA3.
 */
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

#define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK      (0x30U)
#define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT     (4U)
/*! TUNING_BIT_EN - Tuning bit enable
 *  0b00..Enable Tuning circuit for DATA[3:0]
 *  0b01..Enable Tuning circuit for DATA[7:0]
 *  0b10..Enable Tuning circuit for DATA[0]
 *  0b11..Invalid
 */
#define USDHC_VEND_SPEC2_TUNING_BIT_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK)

#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
/*! TUNING_CMD_EN - Tuning command enable
 *  0b0..Auto tuning circuit does not check the CMD line.
 *  0b1..Auto tuning circuit checks the CMD line.
 */
#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
/*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)

#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
/*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)

#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
 *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
 *  0b0..Disable
 */
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK         (0x8000U)
#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT        (15U)
/*! EN_32K_CLK - Select the clock source for host card detection.
 *  0b0..Use the peripheral clock (ipg_clk) for card detection.
 *  0b1..Use the low power clock (ipg_clk_lp) for card detection.
 */
#define USDHC_VEND_SPEC2_EN_32K_CLK(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK)

#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK      (0xFFFF0000U)
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT     (16U)
/*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock */
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK)
/*! @} */

/*! @name TUNING_CTRL - Tuning Control */
/*! @{ */

#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0x7FU)
#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
/*! TUNING_START_TAP - Tuning start */
#define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
/*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)

#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
/*! TUNING_COUNTER - Tuning counter */
#define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

#define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
/*! TUNING_STEP - TUNING_STEP */
#define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
/*! TUNING_WINDOW - Data window */
#define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
/*! STD_TUNING_EN - Standard tuning circuit and procedure enable */
#define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
/*! @} */

/*! @name CQVER - Command Queuing Version */
/*! @{ */

#define USDHC_CQVER_VERSION_SUFFIX_MASK          (0xFU)
#define USDHC_CQVER_VERSION_SUFFIX_SHIFT         (0U)
/*! VERSION_SUFFIX - eMMC version suffix */
#define USDHC_CQVER_VERSION_SUFFIX(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK)

#define USDHC_CQVER_MINOR_VN_MASK                (0xF0U)
#define USDHC_CQVER_MINOR_VN_SHIFT               (4U)
/*! MINOR_VN - eMMC minor version number */
#define USDHC_CQVER_MINOR_VN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK)

#define USDHC_CQVER_MAJOR_VN_MASK                (0xF00U)
#define USDHC_CQVER_MAJOR_VN_SHIFT               (8U)
/*! MAJOR_VN - eMMC major version number */
#define USDHC_CQVER_MAJOR_VN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK)
/*! @} */

/*! @name CQCAP - Command Queuing Capabilities */
/*! @{ */

#define USDHC_CQCAP_ITCFVAL_MASK                 (0x3FFU)
#define USDHC_CQCAP_ITCFVAL_SHIFT                (0U)
/*! ITCFVAL - Internal timer clock frequency value */
#define USDHC_CQCAP_ITCFVAL(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK)

#define USDHC_CQCAP_ITCFMUL_MASK                 (0xF000U)
#define USDHC_CQCAP_ITCFMUL_SHIFT                (12U)
/*! ITCFMUL - Internal timer clock frequency multiplier
 *  0b0001..0.001 MHz
 *  0b0010..0.01 MHz
 *  0b0011..0.1 MHz
 *  0b0100..1 MHz
 *  0b0101..10 MHz
 *  0b0110-0b1001..Reserved
 */
#define USDHC_CQCAP_ITCFMUL(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK)
/*! @} */

/*! @name CQCFG - Command Queuing Configuration */
/*! @{ */

#define USDHC_CQCFG_CQUE_MASK                    (0x1U)
#define USDHC_CQCFG_CQUE_SHIFT                   (0U)
/*! CQUE - Command queuing enable */
#define USDHC_CQCFG_CQUE(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK)

#define USDHC_CQCFG_TDS_MASK                     (0x100U)
#define USDHC_CQCFG_TDS_SHIFT                    (8U)
/*! TDS - Task descriptor size
 *  0b0..Task descriptor size is 64 bits
 *  0b1..Task descriptor size is 128 bits
 */
#define USDHC_CQCFG_TDS(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK)

#define USDHC_CQCFG_DCMDE_MASK                   (0x1000U)
#define USDHC_CQCFG_DCMDE_SHIFT                  (12U)
/*! DCMDE - Direct command (DCMD) enable
 *  0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor
 *  0b1..Task descriptor in slot #31 is a DCMD Task Descriptor
 */
#define USDHC_CQCFG_DCMDE(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK)
/*! @} */

/*! @name CQCTL - Command Queuing Control */
/*! @{ */

#define USDHC_CQCTL_HALT_MASK                    (0x1U)
#define USDHC_CQCTL_HALT_SHIFT                   (0U)
/*! HALT - Halt */
#define USDHC_CQCTL_HALT(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK)

#define USDHC_CQCTL_CLEAR_MASK                   (0x100U)
#define USDHC_CQCTL_CLEAR_SHIFT                  (8U)
/*! CLEAR - Clear all tasks */
#define USDHC_CQCTL_CLEAR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK)
/*! @} */

/*! @name CQIS - Command Queuing Interrupt Status */
/*! @{ */

#define USDHC_CQIS_HAC_MASK                      (0x1U)
#define USDHC_CQIS_HAC_SHIFT                     (0U)
/*! HAC - Halt complete interrupt */
#define USDHC_CQIS_HAC(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK)

#define USDHC_CQIS_TCC_MASK                      (0x2U)
#define USDHC_CQIS_TCC_SHIFT                     (1U)
/*! TCC - Task complete interrupt */
#define USDHC_CQIS_TCC(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK)

#define USDHC_CQIS_RED_MASK                      (0x4U)
#define USDHC_CQIS_RED_SHIFT                     (2U)
/*! RED - Response error detected interrupt */
#define USDHC_CQIS_RED(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK)

#define USDHC_CQIS_TCL_MASK                      (0x8U)
#define USDHC_CQIS_TCL_SHIFT                     (3U)
/*! TCL - Task cleared */
#define USDHC_CQIS_TCL(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK)
/*! @} */

/*! @name CQISTE - Command Queuing Interrupt Status Enable */
/*! @{ */

#define USDHC_CQISTE_HAC_STE_MASK                (0x1U)
#define USDHC_CQISTE_HAC_STE_SHIFT               (0U)
/*! HAC_STE - Halt complete status enable
 *  0b0..CQIS[HAC] is disabled
 *  0b1..CQIS[HAC] is set when its interrupt condition is active
 */
#define USDHC_CQISTE_HAC_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK)

#define USDHC_CQISTE_TCC_STE_MASK                (0x2U)
#define USDHC_CQISTE_TCC_STE_SHIFT               (1U)
/*! TCC_STE - Task complete status enable
 *  0b0..CQIS[TCC] is disabled
 *  0b1..CQIS[TCC] is set when its interrupt condition is active
 */
#define USDHC_CQISTE_TCC_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK)

#define USDHC_CQISTE_RED_STE_MASK                (0x4U)
#define USDHC_CQISTE_RED_STE_SHIFT               (2U)
/*! RED_STE - Response error detected status enable
 *  0b0..CQIS[RED]is disabled
 *  0b1..CQIS[RED] is set when its interrupt condition is active
 */
#define USDHC_CQISTE_RED_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK)

#define USDHC_CQISTE_TCL_STE_MASK                (0x8U)
#define USDHC_CQISTE_TCL_STE_SHIFT               (3U)
/*! TCL_STE - Task cleared status enable
 *  0b0..CQIS[TCL] is disabled
 *  0b1..CQIS[TCL] is set when its interrupt condition is active
 */
#define USDHC_CQISTE_TCL_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK)
/*! @} */

/*! @name CQISGE - Command Queuing Interrupt Signal Enable */
/*! @{ */

#define USDHC_CQISGE_HAC_SGE_MASK                (0x1U)
#define USDHC_CQISGE_HAC_SGE_SHIFT               (0U)
/*! HAC_SGE - Halt complete signal enable */
#define USDHC_CQISGE_HAC_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK)

#define USDHC_CQISGE_TCC_SGE_MASK                (0x2U)
#define USDHC_CQISGE_TCC_SGE_SHIFT               (1U)
/*! TCC_SGE - Task complete signal enable */
#define USDHC_CQISGE_TCC_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK)

#define USDHC_CQISGE_RED_SGE_MASK                (0x4U)
#define USDHC_CQISGE_RED_SGE_SHIFT               (2U)
/*! RED_SGE - Response error detected signal enable */
#define USDHC_CQISGE_RED_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK)

#define USDHC_CQISGE_TCL_SGE_MASK                (0x8U)
#define USDHC_CQISGE_TCL_SGE_SHIFT               (3U)
/*! TCL_SGE - Task cleared signal enable */
#define USDHC_CQISGE_TCL_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK)
/*! @} */

/*! @name CQIC - Command Queuing Interrupt Coalescing */
/*! @{ */

#define USDHC_CQIC_ICTOVAL_MASK                  (0x7FU)
#define USDHC_CQIC_ICTOVAL_SHIFT                 (0U)
/*! ICTOVAL - Interrupt coalescing timeout value */
#define USDHC_CQIC_ICTOVAL(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK)

#define USDHC_CQIC_ICTOVALWEN_MASK               (0x80U)
#define USDHC_CQIC_ICTOVALWEN_SHIFT              (7U)
/*! ICTOVALWEN - Interrupt coalescing timeout value write enable */
#define USDHC_CQIC_ICTOVALWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK)

#define USDHC_CQIC_ICCTH_MASK                    (0x1F00U)
#define USDHC_CQIC_ICCTH_SHIFT                   (8U)
/*! ICCTH - Interrupt coalescing counter threshold */
#define USDHC_CQIC_ICCTH(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK)

#define USDHC_CQIC_ICCTHWEN_MASK                 (0x8000U)
#define USDHC_CQIC_ICCTHWEN_SHIFT                (15U)
/*! ICCTHWEN - Interrupt coalescing counter threshold write enable */
#define USDHC_CQIC_ICCTHWEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK)

#define USDHC_CQIC_ICCTR_MASK                    (0x10000U)
#define USDHC_CQIC_ICCTR_SHIFT                   (16U)
/*! ICCTR - Counter and timer reset */
#define USDHC_CQIC_ICCTR(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK)

#define USDHC_CQIC_ICSB_MASK                     (0x100000U)
#define USDHC_CQIC_ICSB_SHIFT                    (20U)
/*! ICSB - Interrupt coalescing status
 *  0b0..No task completions have occurred since last counter reset (IC counter =0)
 *  0b1..At least one task completion has been counted (IC counter >0)
 */
#define USDHC_CQIC_ICSB(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK)

#define USDHC_CQIC_ICENDIS_MASK                  (0x80000000U)
#define USDHC_CQIC_ICENDIS_SHIFT                 (31U)
/*! ICENDIS - Interrupt coalescing enable/disable */
#define USDHC_CQIC_ICENDIS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK)
/*! @} */

/*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */
/*! @{ */

#define USDHC_CQTDLBA_TDLBA_MASK                 (0xFFFFFFFFU)
#define USDHC_CQTDLBA_TDLBA_SHIFT                (0U)
/*! TDLBA - Task descriptor list base address */
#define USDHC_CQTDLBA_TDLBA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK)
/*! @} */

/*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */
/*! @{ */

#define USDHC_CQTDLBAU_TDLBAU_MASK               (0xFFFFFFFFU)
#define USDHC_CQTDLBAU_TDLBAU_SHIFT              (0U)
/*! TDLBAU - Task descriptor list base address */
#define USDHC_CQTDLBAU_TDLBAU(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK)
/*! @} */

/*! @name CQTDBR - Command Queuing Task Doorbell */
/*! @{ */

#define USDHC_CQTDBR_TDBR_MASK                   (0xFFFFFFFFU)
#define USDHC_CQTDBR_TDBR_SHIFT                  (0U)
/*! TDBR - Task doorbell */
#define USDHC_CQTDBR_TDBR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK)
/*! @} */

/*! @name CQTCN - Command Queuing Task Completion Notification */
/*! @{ */

#define USDHC_CQTCN_TCN_MASK                     (0xFFFFFFFFU)
#define USDHC_CQTCN_TCN_SHIFT                    (0U)
/*! TCN - Task complete notification */
#define USDHC_CQTCN_TCN(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK)
/*! @} */

/*! @name CQDQS - Command Queuing Device Queue Status */
/*! @{ */

#define USDHC_CQDQS_DQS_MASK                     (0xFFFFFFFFU)
#define USDHC_CQDQS_DQS_SHIFT                    (0U)
/*! DQS - Device queue status */
#define USDHC_CQDQS_DQS(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK)
/*! @} */

/*! @name CQDPT - Command Queuing Device Pending Tasks */
/*! @{ */

#define USDHC_CQDPT_DPT_MASK                     (0xFFFFFFFFU)
#define USDHC_CQDPT_DPT_SHIFT                    (0U)
/*! DPT - Device pending tasks */
#define USDHC_CQDPT_DPT(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK)
/*! @} */

/*! @name CQTCLR - Command Queuing Task Clear */
/*! @{ */

#define USDHC_CQTCLR_TCLR_MASK                   (0xFFFFFFFFU)
#define USDHC_CQTCLR_TCLR_SHIFT                  (0U)
/*! TCLR - Task clear */
#define USDHC_CQTCLR_TCLR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK)
/*! @} */

/*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */
/*! @{ */

#define USDHC_CQSSC1_CIT_MASK                    (0xFFFFU)
#define USDHC_CQSSC1_CIT_SHIFT                   (0U)
/*! CIT - Send status command idle timer */
#define USDHC_CQSSC1_CIT(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK)

#define USDHC_CQSSC1_CBC_MASK                    (0xF0000U)
#define USDHC_CQSSC1_CBC_SHIFT                   (16U)
/*! CBC - Send status command block counter */
#define USDHC_CQSSC1_CBC(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK)
/*! @} */

/*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */
/*! @{ */

#define USDHC_CQSSC2_SSC2_MASK                   (0xFFFFU)
#define USDHC_CQSSC2_SSC2_SHIFT                  (0U)
/*! SSC2 - Send queue status RCA */
#define USDHC_CQSSC2_SSC2(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK)
/*! @} */

/*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */
/*! @{ */

#define USDHC_CQCRDCT_CRDCT_MASK                 (0xFFFFFFFFU)
#define USDHC_CQCRDCT_CRDCT_SHIFT                (0U)
/*! CRDCT - Direct command last response */
#define USDHC_CQCRDCT_CRDCT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK)
/*! @} */

/*! @name CQRMEM - Command Queuing Response Mode Error Mask */
/*! @{ */

#define USDHC_CQRMEM_RMEM_MASK                   (0xFFFFFFFFU)
#define USDHC_CQRMEM_RMEM_SHIFT                  (0U)
/*! RMEM - Response mode error mask
 *  0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored
 *  0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated
 */
#define USDHC_CQRMEM_RMEM(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK)
/*! @} */

/*! @name CQTERRI - Command Queuing Task Error Information */
/*! @{ */

#define USDHC_CQTERRI_RMECI_MASK                 (0x3FU)
#define USDHC_CQTERRI_RMECI_SHIFT                (0U)
/*! RMECI - Response mode error command index */
#define USDHC_CQTERRI_RMECI(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK)

#define USDHC_CQTERRI_RMETID_MASK                (0x1F00U)
#define USDHC_CQTERRI_RMETID_SHIFT               (8U)
/*! RMETID - Response mode error task ID */
#define USDHC_CQTERRI_RMETID(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK)

#define USDHC_CQTERRI_RMEFV_MASK                 (0x8000U)
#define USDHC_CQTERRI_RMEFV_SHIFT                (15U)
/*! RMEFV - Response mode error fields valid */
#define USDHC_CQTERRI_RMEFV(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK)

#define USDHC_CQTERRI_DTECI_MASK                 (0x3F0000U)
#define USDHC_CQTERRI_DTECI_SHIFT                (16U)
/*! DTECI - Data transfer error command index */
#define USDHC_CQTERRI_DTECI(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK)

#define USDHC_CQTERRI_DTETID_MASK                (0x1F000000U)
#define USDHC_CQTERRI_DTETID_SHIFT               (24U)
/*! DTETID - Data transfer error task ID */
#define USDHC_CQTERRI_DTETID(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK)

#define USDHC_CQTERRI_DTEFV_MASK                 (0x80000000U)
#define USDHC_CQTERRI_DTEFV_SHIFT                (31U)
/*! DTEFV - Data transfer error fields valid */
#define USDHC_CQTERRI_DTEFV(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK)
/*! @} */

/*! @name CQCRI - Command Queuing Command Response Index */
/*! @{ */

#define USDHC_CQCRI_LCMDRI_MASK                  (0x3FU)
#define USDHC_CQCRI_LCMDRI_SHIFT                 (0U)
/*! LCMDRI - Last command response index */
#define USDHC_CQCRI_LCMDRI(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK)
/*! @} */

/*! @name CQCRA - Command Queuing Command Response Argument */
/*! @{ */

#define USDHC_CQCRA_LCMDRA_MASK                  (0xFFFFFFFFU)
#define USDHC_CQCRA_LCMDRA_SHIFT                 (0U)
/*! LCMDRA - Last command response argument */
#define USDHC_CQCRA_LCMDRA(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USDHC_Register_Masks */


/* USDHC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral USDHC0 base address */
  #define USDHC0_BASE                              (0x50412000u)
  /** Peripheral USDHC0 base address */
  #define USDHC0_BASE_NS                           (0x40412000u)
  /** Peripheral USDHC0 base pointer */
  #define USDHC0                                   ((USDHC_Type *)USDHC0_BASE)
  /** Peripheral USDHC0 base pointer */
  #define USDHC0_NS                                ((USDHC_Type *)USDHC0_BASE_NS)
  /** Peripheral USDHC1 base address */
  #define USDHC1_BASE                              (0x50413000u)
  /** Peripheral USDHC1 base address */
  #define USDHC1_BASE_NS                           (0x40413000u)
  /** Peripheral USDHC1 base pointer */
  #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
  /** Peripheral USDHC1 base pointer */
  #define USDHC1_NS                                ((USDHC_Type *)USDHC1_BASE_NS)
  /** Array initializer of USDHC peripheral base addresses */
  #define USDHC_BASE_ADDRS                         { USDHC0_BASE, USDHC1_BASE }
  /** Array initializer of USDHC peripheral base pointers */
  #define USDHC_BASE_PTRS                          { USDHC0, USDHC1 }
  /** Array initializer of USDHC peripheral base addresses */
  #define USDHC_BASE_ADDRS_NS                      { USDHC0_BASE_NS, USDHC1_BASE_NS }
  /** Array initializer of USDHC peripheral base pointers */
  #define USDHC_BASE_PTRS_NS                       { USDHC0_NS, USDHC1_NS }
#else
  /** Peripheral USDHC0 base address */
  #define USDHC0_BASE                              (0x40412000u)
  /** Peripheral USDHC0 base pointer */
  #define USDHC0                                   ((USDHC_Type *)USDHC0_BASE)
  /** Peripheral USDHC1 base address */
  #define USDHC1_BASE                              (0x40413000u)
  /** Peripheral USDHC1 base pointer */
  #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
  /** Array initializer of USDHC peripheral base addresses */
  #define USDHC_BASE_ADDRS                         { USDHC0_BASE, USDHC1_BASE }
  /** Array initializer of USDHC peripheral base pointers */
  #define USDHC_BASE_PTRS                          { USDHC0, USDHC1 }
#endif

/*!
 * @}
 */ /* end of group USDHC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- UTICK Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
 * @{
 */

/** UTICK - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Control, offset: 0x0 */
  __IO uint32_t STAT;                              /**< Status, offset: 0x4 */
  __IO uint32_t CFG;                               /**< Capture Configuration, offset: 0x8 */
  __O  uint32_t CAPCLR;                            /**< Capture Clear, offset: 0xC */
  __I  uint32_t CAP[4];                            /**< Capture, array offset: 0x10, array step: 0x4 */
} UTICK_Type;

/* ----------------------------------------------------------------------------
   -- UTICK Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup UTICK_Register_Masks UTICK Register Masks
 * @{
 */

/*! @name CTRL - Control */
/*! @{ */

#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
/*! DELAYVAL - Tick Interval
 *  0b0000000000000000000000000000000..
 *  *..Clock cycles as defined in the description
 */
#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)

#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
/*! REPEAT - Repeat Delay
 *  0b0..One-time delay
 *  0b1..Delay repeats continuously
 */
#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
/*! @} */

/*! @name STAT - Status */
/*! @{ */

#define UTICK_STAT_INTR_MASK                     (0x1U)
#define UTICK_STAT_INTR_SHIFT                    (0U)
/*! INTR - Interrupt Flag
 *  0b0..Not pending
 *  0b1..Pending
 */
#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)

#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
/*! ACTIVE - Timer Active Flag
 *  0b0..Inactive (stopped)
 *  0b1..Active
 */
#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
/*! @} */

/*! @name CFG - Capture Configuration */
/*! @{ */

#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
/*! CAPEN0 - Enable Capture 0
 *  0b0..Disable
 *  0b1..Enable
 */
#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)

#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
/*! CAPEN1 - Enable Capture 1
 *  0b0..Disable
 *  0b1..Enable
 */
#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)

#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
/*! CAPEN2 - Enable Capture 2
 *  0b0..Disable
 *  0b1..Enable
 */
#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)

#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
/*! CAPEN3 - Enable Capture 3
 *  0b0..Disable
 *  0b1..Enable
 */
#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)

#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
/*! CAPPOL0 - Capture Polarity 0
 *  0b0..Positive
 *  0b1..Negative
 */
#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)

#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
/*! CAPPOL1 - Capture-Polarity 1
 *  0b0..Positive
 *  0b1..Negative
 */
#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)

#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
/*! CAPPOL2 - Capture Polarity 2
 *  0b0..Positive
 *  0b1..Negative
 */
#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)

#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
/*! CAPPOL3 - Capture Polarity 3
 *  0b0..Positive
 *  0b1..Negative
 */
#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
/*! @} */

/*! @name CAPCLR - Capture Clear */
/*! @{ */

#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
/*! CAPCLR0 - Clear Capture 0
 *  0b0..Does nothing
 *  0b1..Clears the CAP0 register value
 */
#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)

#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
/*! CAPCLR1 - Clear Capture 1
 *  0b0..Does nothing
 *  0b1..Clears the CAP1 register value
 */
#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)

#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
/*! CAPCLR2 - Clear Capture 2
 *  0b0..Does nothing
 *  0b1..Clears the CAP2 register value
 */
#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)

#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
/*! CAPCLR3 - Clear Capture 3
 *  0b0..Does nothing
 *  0b1..Clears the CAP3 register value
 */
#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
/*! @} */

/*! @name CAP - Capture */
/*! @{ */

#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
/*! CAP_VALUE - Captured Value for the Related Capture Event */
#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)

#define UTICK_CAP_VALID_MASK                     (0x80000000U)
#define UTICK_CAP_VALID_SHIFT                    (31U)
/*! VALID - Captured Value Valid Flag
 *  0b0..Valid value not captured
 *  0b1..Valid value captured
 */
#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
/*! @} */

/* The count of UTICK_CAP */
#define UTICK_CAP_COUNT                          (4U)


/*!
 * @}
 */ /* end of group UTICK_Register_Masks */


/* UTICK - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral UTICK0 base address */
  #define UTICK0_BASE                              (0x5000F000u)
  /** Peripheral UTICK0 base address */
  #define UTICK0_BASE_NS                           (0x4000F000u)
  /** Peripheral UTICK0 base pointer */
  #define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
  /** Peripheral UTICK0 base pointer */
  #define UTICK0_NS                                ((UTICK_Type *)UTICK0_BASE_NS)
  /** Array initializer of UTICK peripheral base addresses */
  #define UTICK_BASE_ADDRS                         { UTICK0_BASE }
  /** Array initializer of UTICK peripheral base pointers */
  #define UTICK_BASE_PTRS                          { UTICK0 }
  /** Array initializer of UTICK peripheral base addresses */
  #define UTICK_BASE_ADDRS_NS                      { UTICK0_BASE_NS }
  /** Array initializer of UTICK peripheral base pointers */
  #define UTICK_BASE_PTRS_NS                       { UTICK0_NS }
#else
  /** Peripheral UTICK0 base address */
  #define UTICK0_BASE                              (0x4000F000u)
  /** Peripheral UTICK0 base pointer */
  #define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
  /** Array initializer of UTICK peripheral base addresses */
  #define UTICK_BASE_ADDRS                         { UTICK0_BASE }
  /** Array initializer of UTICK peripheral base pointers */
  #define UTICK_BASE_PTRS                          { UTICK0 }
#endif
/** Interrupt vectors for the UTICK peripheral type */
#define UTICK_IRQS                               { UTICK0_IRQn }

/*!
 * @}
 */ /* end of group UTICK_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WWDT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
 * @{
 */

/** WWDT - Register Layout Typedef */
typedef struct {
  __IO uint32_t MOD;                               /**< Mode, offset: 0x0 */
  __IO uint32_t TC;                                /**< Timer Constant, offset: 0x4 */
  __O  uint32_t FEED;                              /**< Feed Sequence, offset: 0x8 */
  __I  uint32_t TV;                                /**< Timer Value, offset: 0xC */
       uint8_t RESERVED_0[4];
  __IO uint32_t WARNINT;                           /**< Warning Interrupt Compare Value, offset: 0x14 */
  __IO uint32_t WINDOW;                            /**< Window Compare Value, offset: 0x18 */
} WWDT_Type;

/* ----------------------------------------------------------------------------
   -- WWDT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WWDT_Register_Masks WWDT Register Masks
 * @{
 */

/*! @name MOD - Mode */
/*! @{ */

#define WWDT_MOD_WDEN_MASK                       (0x1U)
#define WWDT_MOD_WDEN_SHIFT                      (0U)
/*! WDEN - Watchdog Enable
 *  0b0..Timer stopped
 *  0b1..Timer running
 */
#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)

#define WWDT_MOD_WDRESET_MASK                    (0x2U)
#define WWDT_MOD_WDRESET_SHIFT                   (1U)
/*! WDRESET - Watchdog Reset Enable
 *  0b0..Interrupt
 *  0b1..Reset
 */
#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)

#define WWDT_MOD_WDTOF_MASK                      (0x4U)
#define WWDT_MOD_WDTOF_SHIFT                     (2U)
/*! WDTOF - Watchdog Timeout Flag
 *  0b0..Watchdog event has not occurred.
 *  0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1).
 */
#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)

#define WWDT_MOD_WDINT_MASK                      (0x8U)
#define WWDT_MOD_WDINT_SHIFT                     (3U)
/*! WDINT - Warning Interrupt Flag
 *  0b0..No flag
 *  0b1..Flag
 */
#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)

#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
/*! WDPROTECT - Watchdog Update Mode
 *  0b0..Flexible
 *  0b1..Threshold
 */
#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)

#define WWDT_MOD_LOCK_MASK                       (0x20U)
#define WWDT_MOD_LOCK_SHIFT                      (5U)
/*! LOCK - Lock
 *  0b0..No Lock
 *  0b1..Lock
 */
#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)

#define WWDT_MOD_DEBUG_EN_MASK                   (0x40U)
#define WWDT_MOD_DEBUG_EN_SHIFT                  (6U)
/*! DEBUG_EN - Debug Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define WWDT_MOD_DEBUG_EN(x)                     (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_DEBUG_EN_SHIFT)) & WWDT_MOD_DEBUG_EN_MASK)
/*! @} */

/*! @name TC - Timer Constant */
/*! @{ */

#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
#define WWDT_TC_COUNT_SHIFT                      (0U)
/*! COUNT - Watchdog Timeout Value */
#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
/*! @} */

/*! @name FEED - Feed Sequence */
/*! @{ */

#define WWDT_FEED_FEED_MASK                      (0xFFU)
#define WWDT_FEED_FEED_SHIFT                     (0U)
/*! FEED - Feed Value */
#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
/*! @} */

/*! @name TV - Timer Value */
/*! @{ */

#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
#define WWDT_TV_COUNT_SHIFT                      (0U)
/*! COUNT - Counter Timer Value */
#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
/*! @} */

/*! @name WARNINT - Warning Interrupt Compare Value */
/*! @{ */

#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
/*! WARNINT - Watchdog Warning Interrupt Compare Value */
#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
/*! @} */

/*! @name WINDOW - Window Compare Value */
/*! @{ */

#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
/*! WINDOW - Watchdog Window Value */
#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WWDT_Register_Masks */


/* WWDT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral WWDT0 base address */
  #define WWDT0_BASE                               (0x5000E000u)
  /** Peripheral WWDT0 base address */
  #define WWDT0_BASE_NS                            (0x4000E000u)
  /** Peripheral WWDT0 base pointer */
  #define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
  /** Peripheral WWDT0 base pointer */
  #define WWDT0_NS                                 ((WWDT_Type *)WWDT0_BASE_NS)
  /** Peripheral WWDT1 base address */
  #define WWDT1_BASE                               (0x5002E000u)
  /** Peripheral WWDT1 base address */
  #define WWDT1_BASE_NS                            (0x4002E000u)
  /** Peripheral WWDT1 base pointer */
  #define WWDT1                                    ((WWDT_Type *)WWDT1_BASE)
  /** Peripheral WWDT1 base pointer */
  #define WWDT1_NS                                 ((WWDT_Type *)WWDT1_BASE_NS)
  /** Array initializer of WWDT peripheral base addresses */
  #define WWDT_BASE_ADDRS                          { WWDT0_BASE, WWDT1_BASE }
  /** Array initializer of WWDT peripheral base pointers */
  #define WWDT_BASE_PTRS                           { WWDT0, WWDT1 }
  /** Array initializer of WWDT peripheral base addresses */
  #define WWDT_BASE_ADDRS_NS                       { WWDT0_BASE_NS, WWDT1_BASE_NS }
  /** Array initializer of WWDT peripheral base pointers */
  #define WWDT_BASE_PTRS_NS                        { WWDT0_NS, WWDT1_NS }
#else
  /** Peripheral WWDT0 base address */
  #define WWDT0_BASE                               (0x4000E000u)
  /** Peripheral WWDT0 base pointer */
  #define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
  /** Peripheral WWDT1 base address */
  #define WWDT1_BASE                               (0x4002E000u)
  /** Peripheral WWDT1 base pointer */
  #define WWDT1                                    ((WWDT_Type *)WWDT1_BASE)
  /** Array initializer of WWDT peripheral base addresses */
  #define WWDT_BASE_ADDRS                          { WWDT0_BASE, WWDT1_BASE }
  /** Array initializer of WWDT peripheral base pointers */
  #define WWDT_BASE_PTRS                           { WWDT0, WWDT1 }
#endif
/** Interrupt vectors for the WWDT peripheral type */
#define WWDT_IRQS                                { WWDT0_IRQn, WWDT1_IRQn }

/*!
 * @}
 */ /* end of group WWDT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XCACHE Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCACHE_Peripheral_Access_Layer XCACHE Peripheral Access Layer
 * @{
 */

/** XCACHE - Register Layout Typedef */
typedef struct {
  __IO uint32_t CCR;                               /**< Cache Control, offset: 0x0 */
  __IO uint32_t CLCR;                              /**< Cache Line Control, offset: 0x4 */
  __IO uint32_t CSAR;                              /**< Cache Search Address, offset: 0x8 */
  __IO uint32_t CCVR;                              /**< Cache Read/Write Value, offset: 0xC */
} XCACHE_Type;

/* ----------------------------------------------------------------------------
   -- XCACHE Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCACHE_Register_Masks XCACHE Register Masks
 * @{
 */

/*! @name CCR - Cache Control */
/*! @{ */

#define XCACHE_CCR_ENCACHE_MASK                  (0x1U)
#define XCACHE_CCR_ENCACHE_SHIFT                 (0U)
/*! ENCACHE - Cache Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define XCACHE_CCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_ENCACHE_SHIFT)) & XCACHE_CCR_ENCACHE_MASK)

#define XCACHE_CCR_FRCWT_MASK                    (0x4U)
#define XCACHE_CCR_FRCWT_SHIFT                   (2U)
/*! FRCWT - Force Write Through Mode
 *  0b0..Not force
 *  0b1..Force
 */
#define XCACHE_CCR_FRCWT(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_FRCWT_SHIFT)) & XCACHE_CCR_FRCWT_MASK)

#define XCACHE_CCR_FRCNOALLC_MASK                (0x8U)
#define XCACHE_CCR_FRCNOALLC_SHIFT               (3U)
/*! FRCNOALLC - Force No Allocation on Cache Misses
 *  0b0..Allocate on cache misses
 *  0b1..Force no allocation on cache misses
 */
#define XCACHE_CCR_FRCNOALLC(x)                  (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_FRCNOALLC_SHIFT)) & XCACHE_CCR_FRCNOALLC_MASK)

#define XCACHE_CCR_INVW0_MASK                    (0x1000000U)
#define XCACHE_CCR_INVW0_SHIFT                   (24U)
/*! INVW0 - Invalidate Way 0
 *  0b0..No operation
 *  0b1..Invalidate all lines in way 0
 */
#define XCACHE_CCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_INVW0_SHIFT)) & XCACHE_CCR_INVW0_MASK)

#define XCACHE_CCR_PUSHW0_MASK                   (0x2000000U)
#define XCACHE_CCR_PUSHW0_SHIFT                  (25U)
/*! PUSHW0 - Push Way 0
 *  0b0..No operation
 *  0b1..Pushes all modified lines in way 0
 */
#define XCACHE_CCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_PUSHW0_SHIFT)) & XCACHE_CCR_PUSHW0_MASK)

#define XCACHE_CCR_INVW1_MASK                    (0x4000000U)
#define XCACHE_CCR_INVW1_SHIFT                   (26U)
/*! INVW1 - Invalidate Way 1
 *  0b0..No operation
 *  0b1..Invalidate all lines in way 1
 */
#define XCACHE_CCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_INVW1_SHIFT)) & XCACHE_CCR_INVW1_MASK)

#define XCACHE_CCR_PUSHW1_MASK                   (0x8000000U)
#define XCACHE_CCR_PUSHW1_SHIFT                  (27U)
/*! PUSHW1 - Push Way 1
 *  0b0..No operation
 *  0b1..Push all modified lines in way 1
 */
#define XCACHE_CCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_PUSHW1_SHIFT)) & XCACHE_CCR_PUSHW1_MASK)

#define XCACHE_CCR_GO_MASK                       (0x80000000U)
#define XCACHE_CCR_GO_SHIFT                      (31U)
/*! GO - Initiate Cache Command
 *  0b0..Write: no effect; Read: no cache command active
 *  0b1..Write: initiate command; Read: cache command active
 */
#define XCACHE_CCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_GO_SHIFT)) & XCACHE_CCR_GO_MASK)
/*! @} */

/*! @name CLCR - Cache Line Control */
/*! @{ */

#define XCACHE_CLCR_LGO_MASK                     (0x1U)
#define XCACHE_CLCR_LGO_SHIFT                    (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect; Read: no line command active
 *  0b1..Write: initiate line command; Read: line command active
 */
#define XCACHE_CLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LGO_SHIFT)) & XCACHE_CLCR_LGO_MASK)

#define XCACHE_CLCR_CACHEADDR_MASK               (0x3FFCU)
#define XCACHE_CLCR_CACHEADDR_SHIFT              (2U)
/*! CACHEADDR - Cache Address */
#define XCACHE_CLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_CACHEADDR_SHIFT)) & XCACHE_CLCR_CACHEADDR_MASK)

#define XCACHE_CLCR_WSEL_MASK                    (0x4000U)
#define XCACHE_CLCR_WSEL_SHIFT                   (14U)
/*! WSEL - Way Select
 *  0b0..Way 0
 *  0b1..Way 1
 */
#define XCACHE_CLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_WSEL_SHIFT)) & XCACHE_CLCR_WSEL_MASK)

#define XCACHE_CLCR_TDSEL_MASK                   (0x10000U)
#define XCACHE_CLCR_TDSEL_SHIFT                  (16U)
/*! TDSEL - Tag or Data Select
 *  0b0..Data
 *  0b1..Tag
 */
#define XCACHE_CLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_TDSEL_SHIFT)) & XCACHE_CLCR_TDSEL_MASK)

#define XCACHE_CLCR_LCIVB_MASK                   (0x100000U)
#define XCACHE_CLCR_LCIVB_SHIFT                  (20U)
/*! LCIVB - Line Command Initial Valid */
#define XCACHE_CLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCIVB_SHIFT)) & XCACHE_CLCR_LCIVB_MASK)

#define XCACHE_CLCR_LCIMB_MASK                   (0x200000U)
#define XCACHE_CLCR_LCIMB_SHIFT                  (21U)
/*! LCIMB - Line Command Initial Modified */
#define XCACHE_CLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCIMB_SHIFT)) & XCACHE_CLCR_LCIMB_MASK)

#define XCACHE_CLCR_LCWAY_MASK                   (0x400000U)
#define XCACHE_CLCR_LCWAY_SHIFT                  (22U)
/*! LCWAY - Line Command Way */
#define XCACHE_CLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCWAY_SHIFT)) & XCACHE_CLCR_LCWAY_MASK)

#define XCACHE_CLCR_LCMD_MASK                    (0x3000000U)
#define XCACHE_CLCR_LCMD_SHIFT                   (24U)
/*! LCMD - Line Command
 *  0b00..Search and read or write
 *  0b01..Invalidate
 *  0b10..Push
 *  0b11..Clear
 */
#define XCACHE_CLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCMD_SHIFT)) & XCACHE_CLCR_LCMD_MASK)

#define XCACHE_CLCR_LADSEL_MASK                  (0x4000000U)
#define XCACHE_CLCR_LADSEL_SHIFT                 (26U)
/*! LADSEL - Line Address Select
 *  0b0..Cache address
 *  0b1..Physical address
 */
#define XCACHE_CLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LADSEL_SHIFT)) & XCACHE_CLCR_LADSEL_MASK)

#define XCACHE_CLCR_LACC_MASK                    (0x8000000U)
#define XCACHE_CLCR_LACC_SHIFT                   (27U)
/*! LACC - Line Access Type
 *  0b0..Read
 *  0b1..Write
 */
#define XCACHE_CLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LACC_SHIFT)) & XCACHE_CLCR_LACC_MASK)
/*! @} */

/*! @name CSAR - Cache Search Address */
/*! @{ */

#define XCACHE_CSAR_LGO_MASK                     (0x1U)
#define XCACHE_CSAR_LGO_SHIFT                    (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect; Read: no line command active
 *  0b1..Write: initiate line command; Read: line command active
 */
#define XCACHE_CSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << XCACHE_CSAR_LGO_SHIFT)) & XCACHE_CSAR_LGO_MASK)

#define XCACHE_CSAR_PHYADDR_MASK                 (0xFFFFFFFCU)
#define XCACHE_CSAR_PHYADDR_SHIFT                (2U)
/*! PHYADDR - Physical Address */
#define XCACHE_CSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << XCACHE_CSAR_PHYADDR_SHIFT)) & XCACHE_CSAR_PHYADDR_MASK)
/*! @} */

/*! @name CCVR - Cache Read/Write Value */
/*! @{ */

#define XCACHE_CCVR_DATA_MASK                    (0xFFFFFFFFU)
#define XCACHE_CCVR_DATA_SHIFT                   (0U)
/*! DATA - Cache Read/Write Data */
#define XCACHE_CCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CCVR_DATA_SHIFT)) & XCACHE_CCVR_DATA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group XCACHE_Register_Masks */


/* XCACHE - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XCACHE0 base address */
  #define XCACHE0_BASE                             (0x50033000u)
  /** Peripheral XCACHE0 base address */
  #define XCACHE0_BASE_NS                          (0x40033000u)
  /** Peripheral XCACHE0 base pointer */
  #define XCACHE0                                  ((XCACHE_Type *)XCACHE0_BASE)
  /** Peripheral XCACHE0 base pointer */
  #define XCACHE0_NS                               ((XCACHE_Type *)XCACHE0_BASE_NS)
  /** Peripheral XCACHE1 base address */
  #define XCACHE1_BASE                             (0x50034000u)
  /** Peripheral XCACHE1 base address */
  #define XCACHE1_BASE_NS                          (0x40034000u)
  /** Peripheral XCACHE1 base pointer */
  #define XCACHE1                                  ((XCACHE_Type *)XCACHE1_BASE)
  /** Peripheral XCACHE1 base pointer */
  #define XCACHE1_NS                               ((XCACHE_Type *)XCACHE1_BASE_NS)
  /** Array initializer of XCACHE peripheral base addresses */
  #define XCACHE_BASE_ADDRS                        { XCACHE0_BASE, XCACHE1_BASE }
  /** Array initializer of XCACHE peripheral base pointers */
  #define XCACHE_BASE_PTRS                         { XCACHE0, XCACHE1 }
  /** Array initializer of XCACHE peripheral base addresses */
  #define XCACHE_BASE_ADDRS_NS                     { XCACHE0_BASE_NS, XCACHE1_BASE_NS }
  /** Array initializer of XCACHE peripheral base pointers */
  #define XCACHE_BASE_PTRS_NS                      { XCACHE0_NS, XCACHE1_NS }
#else
  /** Peripheral XCACHE0 base address */
  #define XCACHE0_BASE                             (0x40033000u)
  /** Peripheral XCACHE0 base pointer */
  #define XCACHE0                                  ((XCACHE_Type *)XCACHE0_BASE)
  /** Peripheral XCACHE1 base address */
  #define XCACHE1_BASE                             (0x40034000u)
  /** Peripheral XCACHE1 base pointer */
  #define XCACHE1                                  ((XCACHE_Type *)XCACHE1_BASE)
  /** Array initializer of XCACHE peripheral base addresses */
  #define XCACHE_BASE_ADDRS                        { XCACHE0_BASE, XCACHE1_BASE }
  /** Array initializer of XCACHE peripheral base pointers */
  #define XCACHE_BASE_PTRS                         { XCACHE0, XCACHE1 }
#endif

/*!
 * @}
 */ /* end of group XCACHE_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XSPI_Peripheral_Access_Layer XSPI Peripheral Access Layer
 * @{
 */

/** XSPI - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< Module Configuration, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __I  uint32_t IPCR;                              /**< IP Configuration, offset: 0x8 */
  __IO uint32_t FLSHCR;                            /**< Flash Memory Configuration, offset: 0xC */
  __IO uint32_t BUFCR[4];                          /**< Buffer Configuration, array offset: 0x10, array step: 0x4 */
  __IO uint32_t BFGENCR;                           /**< Buffer Generic Configuration, offset: 0x20 */
  __IO uint32_t SOCCR;                             /**< SOC Configuration, offset: 0x24 */
       uint8_t RESERVED_1[8];
  __IO uint32_t BUFIND[3];                         /**< Buffer 0 Top Index..Buffer 2 Top Index, array offset: 0x30, array step: 0x4 */
       uint8_t RESERVED_2[20];
  __IO uint32_t AWRCR;                             /**< AHB Write Configuration, offset: 0x50 */
       uint8_t RESERVED_3[12];
  __IO uint32_t DLLCR[1];                          /**< DLL Flash Memory A Configuration, array offset: 0x60, array step: 0x4 */
       uint8_t RESERVED_4[156];
  __I  uint32_t SFAR;                              /**< Serial Flash Memory Address, offset: 0x100 */
  __IO uint32_t SFACR;                             /**< Serial Flash Memory Address Configuration, offset: 0x104 */
  __IO uint32_t SMPR;                              /**< Sampling, offset: 0x108 */
  __I  uint32_t RBSR;                              /**< RX Buffer Status, offset: 0x10C */
  __IO uint32_t RBCT;                              /**< RX Buffer Control, offset: 0x110 */
       uint8_t RESERVED_5[12];
  __I  uint32_t AWRSR;                             /**< AHB Write Status, offset: 0x120 */
       uint8_t RESERVED_6[8];
  __I  uint32_t DLLSR;                             /**< DLL Status, offset: 0x12C */
  __IO uint32_t DLCR;                              /**< Data Learning Configuration, offset: 0x130 */
  __I  uint32_t DLSR_F[1];                         /**< Data Learning Status Flash Memory, array offset: 0x134, array step: 0x4 */
       uint8_t RESERVED_7[24];
  __I  uint32_t TBSR;                              /**< TX Buffer Status, offset: 0x150 */
  __IO uint32_t TBDR;                              /**< TX Buffer Data, offset: 0x154 */
  __IO uint32_t TBCT;                              /**< TX Buffer Control, offset: 0x158 */
  __I  uint32_t SR;                                /**< Status, offset: 0x15C */
  __IO uint32_t FR;                                /**< Flag, offset: 0x160 */
  __IO uint32_t RSER;                              /**< Interrupt and DMA Request Enable, offset: 0x164 */
  __I  uint32_t SPNDST;                            /**< Sequence Suspend Status, offset: 0x168 */
  __IO uint32_t SPTRCLR;                           /**< Sequence Pointer Clear, offset: 0x16C */
       uint8_t RESERVED_8[16];
  __IO uint32_t SFAD[1][2];                        /**< Serial Flash Memory Top Address, array offset: 0x180, array step: index*0x8, index2*0x4 */
       uint8_t RESERVED_9[8];
  __IO uint32_t DLPR;                              /**< Data Learning Pattern, offset: 0x190 */
  __I  uint32_t FAIL_ADDR[1];                      /**< Flash Memory A Failing Address Status, array offset: 0x194, array step: 0x4 */
       uint8_t RESERVED_10[104];
  __I  uint32_t RBDR[64];                          /**< RX Buffer Data, array offset: 0x200, array step: 0x4 */
  __IO uint32_t LUTKEY;                            /**< LUT Key, offset: 0x300 */
  __IO uint32_t LCKCR;                             /**< LUT Lock Configuration, offset: 0x304 */
       uint8_t RESERVED_11[8];
  __IO uint32_t LUT[80];                           /**< Lookup Table, array offset: 0x310, array step: 0x4 */
       uint8_t RESERVED_12[48];
  __IO uint32_t BUF_ADDR_RANGE[4][4];              /**< AHB Buffer 0 Sub Buffer 0 Start and End Address Range..AHB Buffer 3 Sub Buffer 3 Start and End Address Range, array offset: 0x480, array step: index*0x10, index2*0x4 */
  __I  uint32_t AHB_BUF_STATUS;                    /**< AHB Buffer Status, offset: 0x4C0 */
  __IO uint32_t AHB_PERF_CTRL;                     /**< AHB Buffer Hit/Miss Performance Monitor Control, offset: 0x4C4 */
  __I  uint32_t AHB_PERF_TIME_CNT;                 /**< AHB Performance Monitor Time Counter, offset: 0x4C8 */
  __I  uint32_t AHB_PERF_BUF[4];                   /**< AHB Buffer 0 Performance Monitor..AHB Buffer 3 Performance Monitor, array offset: 0x4CC, array step: 0x4 */
  __IO uint32_t AHRDYTO;                           /**< AHB HREADY Timeout, offset: 0x4DC */
  __IO uint32_t AHB_ERR_PAYLOAD_HI;                /**< AHB Error Payload High, offset: 0x4E0 */
  __IO uint32_t AHB_ERR_PAYLOAD_LO;                /**< AHB Error Payload Low, offset: 0x4E4 */
  __I  uint32_t AHB_RD_ERR_ADDR;                   /**< AHB Read Error Address, offset: 0x4E8 */
  __I  uint32_t AHB_RD_ERR_MID;                    /**< AHB Read Error Manager ID, offset: 0x4EC */
  __I  uint32_t SPNDST_ADDR;                       /**< Suspend Transaction Address, offset: 0x4F0 */
  __IO uint32_t PPWF_TCNT;                         /**< Page Program Wait Time Counter, offset: 0x4F4 */
  __IO uint32_t PPW_RDSR;                          /**< Page Program Wait Read Status, offset: 0x4F8 */
       uint8_t RESERVED_13[36];
  struct {                                         /* offset: 0x520, array step: 0x20 */
    __IO uint32_t IPEDCTXIV[2];                      /**< IPED Context Initial Vector, array offset: 0x520, array step: index*0x20, index2*0x4, available only on: XSPI0, XSPI1 (missing on XSPI2) */
    __IO uint32_t IPEDCTXSTART;                      /**< IPED Start Address Region, array offset: 0x528, array step: 0x20, available only on: XSPI0, XSPI1 (missing on XSPI2) */
    __IO uint32_t IPEDCTXEND;                        /**< IPED End Address Region, array offset: 0x52C, array step: 0x20, available only on: XSPI0, XSPI1 (missing on XSPI2) */
    __IO uint32_t IPEDCTXAAD[2];                     /**< IPED Context Additional Authentication Data, array offset: 0x530, array step: index*0x20, index2*0x4, available only on: XSPI0, XSPI1 (missing on XSPI2) */
         uint8_t RESERVED_0[8];
  } IPEDCTXXIV[16];
  __IO uint32_t IPEDCTRL;                          /**< IPED Function Control, offset: 0x720, available only on: XSPI0, XSPI1 (missing on XSPI2) */
       uint8_t RESERVED_14[4];
  __IO uint32_t IPEDCTXCTRL[2];                    /**< IPED Context Control 0..IPED Context Control 1, array offset: 0x728, array step: 0x4, available only on: XSPI0, XSPI1 (missing on XSPI2) */
       uint8_t RESERVED_15[208];
  __IO uint32_t FRAD0_WORD0;                       /**< Flash Region Word 0 - Start Address, offset: 0x800 */
  __IO uint32_t FRAD0_WORD1;                       /**< Flash Region Word 1 - End Address, offset: 0x804 */
  __IO uint32_t FRAD0_WORD2;                       /**< Flash Region Word 2 - Privileges, offset: 0x808 */
  __IO uint32_t FRAD0_WORD3;                       /**< Flash Region Word 3 - Lock Control, offset: 0x80C */
  __I  uint32_t FRAD0_WORD4;                       /**< Flash Region Word 4 - Compare Address Status, offset: 0x810 */
  __I  uint32_t FRAD0_WORD5;                       /**< Flash Region Word 5 - Compare Status Data, offset: 0x814 */
       uint8_t RESERVED_16[8];
  __IO uint32_t FRAD1_WORD0;                       /**< Flash Region Word 0 - Start Address, offset: 0x820 */
  __IO uint32_t FRAD1_WORD1;                       /**< Flash Region Word 1 - End Address, offset: 0x824 */
  __IO uint32_t FRAD1_WORD2;                       /**< Flash Region Word 2 - Privileges, offset: 0x828 */
  __IO uint32_t FRAD1_WORD3;                       /**< Flash Region Word 3 - Lock Control, offset: 0x82C */
  __I  uint32_t FRAD1_WORD4;                       /**< Flash Region Word 4 - Compare Address Status, offset: 0x830 */
  __I  uint32_t FRAD1_WORD5;                       /**< Flash Region Word 5 - Compare Status Data, offset: 0x834 */
       uint8_t RESERVED_17[8];
  __IO uint32_t FRAD2_WORD0;                       /**< Flash Region Word 0 - Start Address, offset: 0x840 */
  __IO uint32_t FRAD2_WORD1;                       /**< Flash Region Word 1 - End Address, offset: 0x844 */
  __IO uint32_t FRAD2_WORD2;                       /**< Flash Region Word 2 - Privileges, offset: 0x848 */
  __IO uint32_t FRAD2_WORD3;                       /**< Flash Region Word 3 - Lock Control, offset: 0x84C */
  __I  uint32_t FRAD2_WORD4;                       /**< Flash Region Word 4 - Compare Address Status, offset: 0x850 */
  __I  uint32_t FRAD2_WORD5;                       /**< Flash Region Word 5 - Compare Status Data, offset: 0x854 */
       uint8_t RESERVED_18[8];
  __IO uint32_t FRAD3_WORD0;                       /**< Flash Region Word 0 - Start Address, offset: 0x860 */
  __IO uint32_t FRAD3_WORD1;                       /**< Flash Region Word 1 - End Address, offset: 0x864 */
  __IO uint32_t FRAD3_WORD2;                       /**< Flash Region Word 2 - Privileges, offset: 0x868 */
  __IO uint32_t FRAD3_WORD3;                       /**< Flash Region Word 3 - Lock Control, offset: 0x86C */
  __I  uint32_t FRAD3_WORD4;                       /**< Flash Region Word 4 - Compare Address Status, offset: 0x870 */
  __I  uint32_t FRAD3_WORD5;                       /**< Flash Region Word 5 - Compare Status Data, offset: 0x874 */
       uint8_t RESERVED_19[8];
  __IO uint32_t FRAD4_WORD0;                       /**< Flash Region Word 0 - Start Address, offset: 0x880 */
  __IO uint32_t FRAD4_WORD1;                       /**< Flash Region Word 1 - End Address, offset: 0x884 */
  __IO uint32_t FRAD4_WORD2;                       /**< Flash Region Word 2 - Privileges, offset: 0x888 */
  __IO uint32_t FRAD4_WORD3;                       /**< Flash Region Word 3 - Lock Control, offset: 0x88C */
  __I  uint32_t FRAD4_WORD4;                       /**< Flash Region Word 4 - Compare Address Status, offset: 0x890 */
  __I  uint32_t FRAD4_WORD5;                       /**< Flash Region Word 5 - Compare Status Data, offset: 0x894 */
       uint8_t RESERVED_20[8];
  __IO uint32_t FRAD5_WORD0;                       /**< Flash Region Word 0 - Start Address, offset: 0x8A0 */
  __IO uint32_t FRAD5_WORD1;                       /**< Flash Region Word 1 - End Address, offset: 0x8A4 */
  __IO uint32_t FRAD5_WORD2;                       /**< Flash Region Word 2 - Privileges, offset: 0x8A8 */
  __IO uint32_t FRAD5_WORD3;                       /**< Flash Region Word 3 - Lock Control, offset: 0x8AC */
  __I  uint32_t FRAD5_WORD4;                       /**< Flash Region Word 4 - Compare Address Status, offset: 0x8B0 */
  __I  uint32_t FRAD5_WORD5;                       /**< Flash Region Word 5 - Compare Status Data, offset: 0x8B4 */
       uint8_t RESERVED_21[8];
  __IO uint32_t FRAD6_WORD0;                       /**< Flash Region Word 0 - Start Address, offset: 0x8C0 */
  __IO uint32_t FRAD6_WORD1;                       /**< Flash Region Word 1 - End Address, offset: 0x8C4 */
  __IO uint32_t FRAD6_WORD2;                       /**< Flash Region Word 2 - Privileges, offset: 0x8C8 */
  __IO uint32_t FRAD6_WORD3;                       /**< Flash Region Word 3 - Lock Control, offset: 0x8CC */
  __I  uint32_t FRAD6_WORD4;                       /**< Flash Region Word 4 - Compare Address Status, offset: 0x8D0 */
  __I  uint32_t FRAD6_WORD5;                       /**< Flash Region Word 5 - Compare Status Data, offset: 0x8D4 */
       uint8_t RESERVED_22[8];
  __IO uint32_t FRAD7_WORD0;                       /**< Flash Region Word 0 - Start Address, offset: 0x8E0 */
  __IO uint32_t FRAD7_WORD1;                       /**< Flash Region Word 1 - End Address, offset: 0x8E4 */
  __IO uint32_t FRAD7_WORD2;                       /**< Flash Region Word 2 - Privileges, offset: 0x8E8 */
  __IO uint32_t FRAD7_WORD3;                       /**< Flash Region Word 3 - Lock Control, offset: 0x8EC */
  __I  uint32_t FRAD7_WORD4;                       /**< Flash Region Word 4 - Compare Address Status, offset: 0x8F0 */
  __I  uint32_t FRAD7_WORD5;                       /**< Flash Region Word 5 - Compare Status Data, offset: 0x8F4 */
       uint8_t RESERVED_23[4];
  __IO uint32_t SFP_ARB_TIMEOUT;                   /**< SFP Arbitration Lock Timeout Counter, offset: 0x8FC */
  __IO uint32_t TG0MDAD;                           /**< Target Group Manager Domain Access Descriptor, offset: 0x900 */
  __I  uint32_t TGSFAR;                            /**< Target Group SFAR Address, offset: 0x904 */
  __IO uint32_t TGSFARS;                           /**< Target Group SFAR Status, offset: 0x908 */
  __IO uint32_t TGIPCRS;                           /**< Target Group IP Configuration Status, offset: 0x90C */
  __IO uint32_t TG1MDAD;                           /**< Target Group Manager Domain Access Descriptor, offset: 0x910 */
       uint8_t RESERVED_24[12];
  __IO uint32_t MGC;                               /**< Manager Global Configuration, offset: 0x920 */
  __IO uint32_t MRC;                               /**< Manager Read Command, offset: 0x924 */
  __IO uint32_t MTO;                               /**< Manager Timeout, offset: 0x928 */
  __I  uint32_t FLSEQREQ;                          /**< Flash Sequence Request, offset: 0x92C */
  __I  uint32_t FSMSTAT;                           /**< FSM Status, offset: 0x930 */
  __IO uint32_t IPSERROR;                          /**< IPS Error, offset: 0x934 */
  __IO uint32_t ERRSTAT;                           /**< Error Status, offset: 0x938 */
  __IO uint32_t INT_EN;                            /**< Interrupt Enable, offset: 0x93C */
       uint8_t RESERVED_25[24];
  __IO uint32_t SFP_TG_IPCR;                       /**< IP Configuration, offset: 0x958 */
  __IO uint32_t SFP_TG_SFAR;                       /**< Serial Flash Memory Address, offset: 0x95C */
  __IO uint32_t SFP_LUT_EN[2];                     /**< LUT Access Enable, array offset: 0x960, array step: 0x4 */
       uint8_t RESERVED_26[276];
  __I  uint32_t SFP_LOCK_ERR_ADDR;                 /**< SFP Lock Error Address, offset: 0xA7C */
  struct {                                         /* offset: 0xA80, array step: 0x14 */
    __IO uint32_t SFP_TG_SUB_IPCR;                   /**< IP Configuration, array offset: 0xA80, array step: 0x14 */
    __IO uint32_t SFP_TG_SUB_SFAR;                   /**< Serial Flash Memory Address, array offset: 0xA84, array step: 0x14 */
    __I  uint32_t TGSFAR_SUB;                        /**< Target Group SFAR Address, array offset: 0xA88, array step: 0x14 */
    __IO uint32_t TGSFARS_SUB;                       /**< Target Group SFAR Status, array offset: 0xA8C, array step: 0x14 */
    __IO uint32_t TGIPCRS_SUB;                       /**< Target Group n IP Configuration Status, array offset: 0xA90, array step: 0x14 */
  } SUB_REG_MDAM_ARRAY[1];
} XSPI_Type;

/* ----------------------------------------------------------------------------
   -- XSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XSPI_Register_Masks XSPI Register Masks
 * @{
 */

/*! @name MCR - Module Configuration */
/*! @{ */

#define XSPI_MCR_SWRSTSD_MASK                    (0x1U)
#define XSPI_MCR_SWRSTSD_SHIFT                   (0U)
/*! SWRSTSD - Software Reset for Serial Flash Memory Domain
 *  0b0..Deasserts reset
 *  0b1..Resets
 */
#define XSPI_MCR_SWRSTSD(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_SWRSTSD_SHIFT)) & XSPI_MCR_SWRSTSD_MASK)

#define XSPI_MCR_SWRSTHD_MASK                    (0x2U)
#define XSPI_MCR_SWRSTHD_SHIFT                   (1U)
/*! SWRSTHD - Software Reset for AHB Domain
 *  0b0..Deasserts reset
 *  0b1..Resets
 */
#define XSPI_MCR_SWRSTHD(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_SWRSTHD_SHIFT)) & XSPI_MCR_SWRSTHD_MASK)

#define XSPI_MCR_END_CFG_MASK                    (0xCU)
#define XSPI_MCR_END_CFG_SHIFT                   (2U)
/*! END_CFG - Byte Order
 *  0b00..64-bit BE
 *  0b01..32-bit LE
 *  0b10..32-bit BE
 *  0b11..64-bit LE
 */
#define XSPI_MCR_END_CFG(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_END_CFG_SHIFT)) & XSPI_MCR_END_CFG_MASK)

#define XSPI_MCR_DQS_OUT_EN_MASK                 (0x10U)
#define XSPI_MCR_DQS_OUT_EN_SHIFT                (4U)
/*! DQS_OUT_EN - DQS Output Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_MCR_DQS_OUT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_DQS_OUT_EN_SHIFT)) & XSPI_MCR_DQS_OUT_EN_MASK)

#define XSPI_MCR_DQS_LAT_EN_MASK                 (0x20U)
#define XSPI_MCR_DQS_LAT_EN_SHIFT                (5U)
/*! DQS_LAT_EN - DQS Latency Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_MCR_DQS_LAT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_DQS_LAT_EN_SHIFT)) & XSPI_MCR_DQS_LAT_EN_MASK)

#define XSPI_MCR_DQS_EN_MASK                     (0x40U)
#define XSPI_MCR_DQS_EN_SHIFT                    (6U)
/*! DQS_EN - DQS Enable
 *  0b0..Reserved
 *  0b1..Enables
 */
#define XSPI_MCR_DQS_EN(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_DQS_EN_SHIFT)) & XSPI_MCR_DQS_EN_MASK)

#define XSPI_MCR_DDR_EN_MASK                     (0x80U)
#define XSPI_MCR_DDR_EN_SHIFT                    (7U)
/*! DDR_EN - DDR Mode Enable
 *  0b0..2x clock disabled. Only SDR instructions processed
 *  0b1..2x clock enabled. Both SDR and DDR instructions processed
 */
#define XSPI_MCR_DDR_EN(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_DDR_EN_SHIFT)) & XSPI_MCR_DDR_EN_MASK)

#define XSPI_MCR_VAR_LAT_EN_MASK                 (0x100U)
#define XSPI_MCR_VAR_LAT_EN_SHIFT                (8U)
/*! VAR_LAT_EN - Variable Latency Enable
 *  0b0..Fixed latency
 *  0b1..Additional initial latency
 */
#define XSPI_MCR_VAR_LAT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_VAR_LAT_EN_SHIFT)) & XSPI_MCR_VAR_LAT_EN_MASK)

#define XSPI_MCR_IPS_TG_RST_MASK                 (0x200U)
#define XSPI_MCR_IPS_TG_RST_SHIFT                (9U)
/*! IPS_TG_RST - Software Reset for IPS Target Group Queue
 *  0b0..No action
 *  0b1..Resets
 *  0b0..No action
 *  0b1..Reset of IPS TG queue is in progress if is having TG Grant
 */
#define XSPI_MCR_IPS_TG_RST(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_IPS_TG_RST_SHIFT)) & XSPI_MCR_IPS_TG_RST_MASK)

#define XSPI_MCR_CLR_RXF_MASK                    (0x400U)
#define XSPI_MCR_CLR_RXF_SHIFT                   (10U)
/*! CLR_RXF - Clear RX FIFO
 *  0b0..No action. Always reads 0.
 *  0b1..Clears buffer and returns pointers to 0
 */
#define XSPI_MCR_CLR_RXF(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_CLR_RXF_SHIFT)) & XSPI_MCR_CLR_RXF_MASK)

#define XSPI_MCR_CLR_TXF_MASK                    (0x800U)
#define XSPI_MCR_CLR_TXF_SHIFT                   (11U)
/*! CLR_TXF - Clear TX FIFO
 *  0b0..No action. Always reads 0.
 *  0b1..Clears buffer and returns pointers to 0
 */
#define XSPI_MCR_CLR_TXF(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_CLR_TXF_SHIFT)) & XSPI_MCR_CLR_TXF_MASK)

#define XSPI_MCR_DLPEN_MASK                      (0x1000U)
#define XSPI_MCR_DLPEN_SHIFT                     (12U)
/*! DLPEN - Data Learning Pattern Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_MCR_DLPEN(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_DLPEN_SHIFT)) & XSPI_MCR_DLPEN_MASK)

#define XSPI_MCR_MDIS_MASK                       (0x4000U)
#define XSPI_MCR_MDIS_SHIFT                      (14U)
/*! MDIS - Module Disable
 *  0b0..Enables clocks
 *  0b1..Allows external logic to disable clocks
 */
#define XSPI_MCR_MDIS(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_MDIS_SHIFT)) & XSPI_MCR_MDIS_MASK)

#define XSPI_MCR_DOZE_MASK                       (0x8000U)
#define XSPI_MCR_DOZE_SHIFT                      (15U)
/*! DOZE - Doze Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_MCR_DOZE(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_DOZE_SHIFT)) & XSPI_MCR_DOZE_MASK)

#define XSPI_MCR_ISD2FA_MASK                     (0x10000U)
#define XSPI_MCR_ISD2FA_SHIFT                    (16U)
/*! ISD2FA - Idle Signal Drive IOFA[2] Flash Memory A
 *  0b0..Logic low
 *  0b1..Logic high
 */
#define XSPI_MCR_ISD2FA(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_ISD2FA_SHIFT)) & XSPI_MCR_ISD2FA_MASK)

#define XSPI_MCR_ISD3FA_MASK                     (0x20000U)
#define XSPI_MCR_ISD3FA_SHIFT                    (17U)
/*! ISD3FA - Idle Signal Drive IOFA[3] Flash Memory A
 *  0b0..Logic low
 *  0b1..Logic high
 */
#define XSPI_MCR_ISD3FA(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_ISD3FA_SHIFT)) & XSPI_MCR_ISD3FA_MASK)

#define XSPI_MCR_X16_DB_CA_EN_MASK               (0x100000U)
#define XSPI_MCR_X16_DB_CA_EN_SHIFT              (20U)
/*! X16_DB_CA_EN - X16 Databus Enable
 *  0b0..Data only
 *  0b1..Address and command information along with data
 */
#define XSPI_MCR_X16_DB_CA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_X16_DB_CA_EN_SHIFT)) & XSPI_MCR_X16_DB_CA_EN_MASK)

#define XSPI_MCR_X16_EN_MASK                     (0x200000U)
#define XSPI_MCR_X16_EN_SHIFT                    (21U)
/*! X16_EN - X16 Mode Enable
 *  0b0..Disables (x8, x4, x2, x1 modes remain enabled)
 *  0b1..Enables
 */
#define XSPI_MCR_X16_EN(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_X16_EN_SHIFT)) & XSPI_MCR_X16_EN_MASK)

#define XSPI_MCR_DQS_FA_SEL_MASK                 (0x3000000U)
#define XSPI_MCR_DQS_FA_SEL_SHIFT                (24U)
/*! DQS_FA_SEL - DQS Clock For Sampling Read Data Flash Memory A
 *  0b00..
 *  0b01..Dummy pad loopback
 *  0b10..DQS pad loopback
 *  0b11..External DQS
 */
#define XSPI_MCR_DQS_FA_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_DQS_FA_SEL_SHIFT)) & XSPI_MCR_DQS_FA_SEL_MASK)

#define XSPI_MCR_CKN_FA_EN_MASK                  (0x4000000U)
#define XSPI_MCR_CKN_FA_EN_SHIFT                 (26U)
/*! CKN_FA_EN - CKN Pad For Flash Memory A
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_MCR_CKN_FA_EN(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_CKN_FA_EN_SHIFT)) & XSPI_MCR_CKN_FA_EN_MASK)
/*! @} */

/*! @name IPCR - IP Configuration */
/*! @{ */

#define XSPI_IPCR_IDATSZ_MASK                    (0xFFFFU)
#define XSPI_IPCR_IDATSZ_SHIFT                   (0U)
/*! IDATSZ - IP Data Transfer Size */
#define XSPI_IPCR_IDATSZ(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_IPCR_IDATSZ_SHIFT)) & XSPI_IPCR_IDATSZ_MASK)

#define XSPI_IPCR_SEQID_MASK                     (0xF000000U)
#define XSPI_IPCR_SEQID_SHIFT                    (24U)
/*! SEQID - LUT Sequence ID */
#define XSPI_IPCR_SEQID(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_IPCR_SEQID_SHIFT)) & XSPI_IPCR_SEQID_MASK)
/*! @} */

/*! @name FLSHCR - Flash Memory Configuration */
/*! @{ */

#define XSPI_FLSHCR_TCSS_MASK                    (0xFU)
#define XSPI_FLSHCR_TCSS_SHIFT                   (0U)
/*! TCSS - Serial Flash Memory CS Setup Time */
#define XSPI_FLSHCR_TCSS(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_FLSHCR_TCSS_SHIFT)) & XSPI_FLSHCR_TCSS_MASK)

#define XSPI_FLSHCR_TCSH_MASK                    (0xF00U)
#define XSPI_FLSHCR_TCSH_SHIFT                   (8U)
/*! TCSH - Serial Flash Memory CS Hold Time */
#define XSPI_FLSHCR_TCSH(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_FLSHCR_TCSH_SHIFT)) & XSPI_FLSHCR_TCSH_MASK)

#define XSPI_FLSHCR_TDH_MASK                     (0x30000U)
#define XSPI_FLSHCR_TDH_SHIFT                    (16U)
/*! TDH - Serial Flash Memory Data in Hold Time
 *  0b00..Posedge of XSPI internal reference clock
 *  0b01..2x serial flash memory half clock
 *  *..
 */
#define XSPI_FLSHCR_TDH(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_FLSHCR_TDH_SHIFT)) & XSPI_FLSHCR_TDH_MASK)
/*! @} */

/*! @name BUFCR - Buffer Configuration */
/*! @{ */

#define XSPI_BUFCR_MSTRID_MASK                   (0x1FU)
#define XSPI_BUFCR_MSTRID_SHIFT                  (0U)
/*! MSTRID - Manager ID */
#define XSPI_BUFCR_MSTRID(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_MSTRID_SHIFT)) & XSPI_BUFCR_MSTRID_MASK)

#define XSPI_BUFCR_ADATSZ_MASK                   (0x3FF00U)
#define XSPI_BUFCR_ADATSZ_SHIFT                  (8U)
/*! ADATSZ - AHB Data Transfer Size */
#define XSPI_BUFCR_ADATSZ(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_ADATSZ_SHIFT)) & XSPI_BUFCR_ADATSZ_MASK)

#define XSPI_BUFCR_SUBBUF0_DIV_MASK              (0xE00000U)
#define XSPI_BUFCR_SUBBUF0_DIV_SHIFT             (21U)
/*! SUBBUF0_DIV - Sub-Buffer Division Factor
 *  0b001..2
 *  0b010..4
 *  0b011..8
 *  0b100..16
 *  *..
 */
#define XSPI_BUFCR_SUBBUF0_DIV(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_SUBBUF0_DIV_SHIFT)) & XSPI_BUFCR_SUBBUF0_DIV_MASK)

#define XSPI_BUFCR_SUBBUF1_DIV_MASK              (0x7000000U)
#define XSPI_BUFCR_SUBBUF1_DIV_SHIFT             (24U)
/*! SUBBUF1_DIV - Sub-Buffer Division Factor
 *  0b001..2
 *  0b010..4
 *  0b011..8
 *  0b100..16
 *  *..
 */
#define XSPI_BUFCR_SUBBUF1_DIV(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_SUBBUF1_DIV_SHIFT)) & XSPI_BUFCR_SUBBUF1_DIV_MASK)

#define XSPI_BUFCR_SUBBUF2_DIV_MASK              (0x38000000U)
#define XSPI_BUFCR_SUBBUF2_DIV_SHIFT             (27U)
/*! SUBBUF2_DIV - Sub-Buffer Division Factor
 *  0b001..2
 *  0b010..4
 *  0b011..8
 *  0b100..16
 *  *..
 */
#define XSPI_BUFCR_SUBBUF2_DIV(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_SUBBUF2_DIV_SHIFT)) & XSPI_BUFCR_SUBBUF2_DIV_MASK)

#define XSPI_BUFCR_SUB_DIV_EN_MASK               (0x40000000U)
#define XSPI_BUFCR_SUB_DIV_EN_SHIFT              (30U)
/*! SUB_DIV_EN - Buffer Sub-Division Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_BUFCR_SUB_DIV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_SUB_DIV_EN_SHIFT)) & XSPI_BUFCR_SUB_DIV_EN_MASK)

#define XSPI_BUFCR_ALLMST_MASK                   (0x80000000U)
#define XSPI_BUFCR_ALLMST_SHIFT                  (31U)
/*! ALLMST - All Manager Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_BUFCR_ALLMST(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_ALLMST_SHIFT)) & XSPI_BUFCR_ALLMST_MASK)

#define XSPI_BUFCR_HP_EN_MASK                    (0x80000000U)
#define XSPI_BUFCR_HP_EN_SHIFT                   (31U)
/*! HP_EN - High Priority Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_BUFCR_HP_EN(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_HP_EN_SHIFT)) & XSPI_BUFCR_HP_EN_MASK)
/*! @} */

/* The count of XSPI_BUFCR */
#define XSPI_BUFCR_COUNT                         (4U)

/*! @name BFGENCR - Buffer Generic Configuration */
/*! @{ */

#define XSPI_BFGENCR_SEQID_RDSR_MASK             (0xFU)
#define XSPI_BFGENCR_SEQID_RDSR_SHIFT            (0U)
/*! SEQID_RDSR - Read Status Register Sequence ID in LUT */
#define XSPI_BFGENCR_SEQID_RDSR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_SEQID_RDSR_SHIFT)) & XSPI_BFGENCR_SEQID_RDSR_MASK)

#define XSPI_BFGENCR_SPLITEN_MASK                (0x100U)
#define XSPI_BFGENCR_SPLITEN_SHIFT               (8U)
/*! SPLITEN - AHB Transaction Split Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_BFGENCR_SPLITEN(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_SPLITEN_SHIFT)) & XSPI_BFGENCR_SPLITEN_MASK)

#define XSPI_BFGENCR_AHBSSIZE_MASK               (0x600U)
#define XSPI_BFGENCR_AHBSSIZE_SHIFT              (9U)
/*! AHBSSIZE - AHB Split Size
 *  0b00..8 bytes
 *  0b01..16 bytes
 *  0b10..32 bytes
 *  0b11..64 bytes
 */
#define XSPI_BFGENCR_AHBSSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_AHBSSIZE_SHIFT)) & XSPI_BFGENCR_AHBSSIZE_MASK)

#define XSPI_BFGENCR_SEQID_MASK                  (0xF000U)
#define XSPI_BFGENCR_SEQID_SHIFT                 (12U)
/*! SEQID - LUT Sequence Pointer */
#define XSPI_BFGENCR_SEQID(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_SEQID_SHIFT)) & XSPI_BFGENCR_SEQID_MASK)

#define XSPI_BFGENCR_SEQID_WR_EN_MASK            (0x20000U)
#define XSPI_BFGENCR_SEQID_WR_EN_SHIFT           (17U)
/*! SEQID_WR_EN - Enable Write Sequence ID
 *  0b0..Disables (use SEQID)
 *  0b1..Enables
 */
#define XSPI_BFGENCR_SEQID_WR_EN(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_SEQID_WR_EN_SHIFT)) & XSPI_BFGENCR_SEQID_WR_EN_MASK)

#define XSPI_BFGENCR_PPWF_CLR_MASK               (0x100000U)
#define XSPI_BFGENCR_PPWF_CLR_SHIFT              (20U)
/*! PPWF_CLR - Page Program Wait Flag Clear
 *  0b0..Cleared by software
 *  0b1..Cleared by XSPI. No software intervention required.
 */
#define XSPI_BFGENCR_PPWF_CLR(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_PPWF_CLR_SHIFT)) & XSPI_BFGENCR_PPWF_CLR_MASK)

#define XSPI_BFGENCR_WR_FLUSH_EN_MASK            (0x200000U)
#define XSPI_BFGENCR_WR_FLUSH_EN_SHIFT           (21U)
/*! WR_FLUSH_EN - Write Flush Enable
 *  0b0..Not cleared
 *  0b1..Cleared
 */
#define XSPI_BFGENCR_WR_FLUSH_EN(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_WR_FLUSH_EN_SHIFT)) & XSPI_BFGENCR_WR_FLUSH_EN_MASK)

#define XSPI_BFGENCR_ALIGN_MASK                  (0xC00000U)
#define XSPI_BFGENCR_ALIGN_SHIFT                 (22U)
/*! ALIGN - AHB Alignment
 *  0b00..No limit
 *  0b01..256 bytes
 *  0b10..512 bytes
 *  0b11..1 KB
 */
#define XSPI_BFGENCR_ALIGN(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_ALIGN_SHIFT)) & XSPI_BFGENCR_ALIGN_MASK)

#define XSPI_BFGENCR_SEQID_WR_MASK               (0xF0000000U)
#define XSPI_BFGENCR_SEQID_WR_SHIFT              (28U)
/*! SEQID_WR - Write Sequence ID */
#define XSPI_BFGENCR_SEQID_WR(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_BFGENCR_SEQID_WR_SHIFT)) & XSPI_BFGENCR_SEQID_WR_MASK)
/*! @} */

/*! @name SOCCR - SOC Configuration */
/*! @{ */

#define XSPI_SOCCR_SOCCFG_MASK                   (0xFFFFFFU)
#define XSPI_SOCCR_SOCCFG_SHIFT                  (0U)
/*! SOCCFG - SOC Configuration */
#define XSPI_SOCCR_SOCCFG(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_SOCCR_SOCCFG_SHIFT)) & XSPI_SOCCR_SOCCFG_MASK)

#define XSPI_SOCCR_MASK_ECC_MASK                 (0x2000000U)
#define XSPI_SOCCR_MASK_ECC_SHIFT                (25U)
/*! MASK_ECC - Mask ECC for False AHB Reads
 *  0b0..Unmask ECC error
 *  0b1..Mask ECC error
 */
#define XSPI_SOCCR_MASK_ECC(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_SOCCR_MASK_ECC_SHIFT)) & XSPI_SOCCR_MASK_ECC_MASK)

#define XSPI_SOCCR_OBE_MASK_EN_MASK              (0x4000000U)
#define XSPI_SOCCR_OBE_MASK_EN_SHIFT             (26U)
/*! OBE_MASK_EN - Output Buffer Enable Mask Enable
 *  0b0..Enable all OBE in output direction for x8 mode during write transaction (in a non-Dummy phase)
 *  0b1..Normal OBE handling for both read and write operation
 */
#define XSPI_SOCCR_OBE_MASK_EN(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_SOCCR_OBE_MASK_EN_SHIFT)) & XSPI_SOCCR_OBE_MASK_EN_MASK)

#define XSPI_SOCCR_HRESP_ERR_MASK_MASK           (0x8000000U)
#define XSPI_SOCCR_HRESP_ERR_MASK_SHIFT          (27U)
/*! HRESP_ERR_MASK - HRESP Error Mask
 *  0b0..Allows HRESP error generation
 *  0b1..Masks HRESP error generation
 */
#define XSPI_SOCCR_HRESP_ERR_MASK(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_SOCCR_HRESP_ERR_MASK_SHIFT)) & XSPI_SOCCR_HRESP_ERR_MASK_MASK)

#define XSPI_SOCCR_ENA_DLLABRT_MASK              (0x10000000U)
#define XSPI_SOCCR_ENA_DLLABRT_SHIFT             (28U)
/*! ENA_DLLABRT - DLL Abort Request Status Enable
 *  0b0..Masks
 *  0b1..Unmasks
 */
#define XSPI_SOCCR_ENA_DLLABRT(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_SOCCR_ENA_DLLABRT_SHIFT)) & XSPI_SOCCR_ENA_DLLABRT_MASK)
/*! @} */

/*! @name BUFIND - Buffer 0 Top Index..Buffer 2 Top Index */
/*! @{ */

#define XSPI_BUFIND_TPINDX_MASK                  (0x1FF8U)
#define XSPI_BUFIND_TPINDX_SHIFT                 (3U)
/*! TPINDX - Top Index Buffer */
#define XSPI_BUFIND_TPINDX(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_BUFIND_TPINDX_SHIFT)) & XSPI_BUFIND_TPINDX_MASK)
/*! @} */

/* The count of XSPI_BUFIND */
#define XSPI_BUFIND_COUNT                        (3U)

/*! @name AWRCR - AHB Write Configuration */
/*! @{ */

#define XSPI_AWRCR_PPW_RD_DIS_MASK               (0x4000U)
#define XSPI_AWRCR_PPW_RD_DIS_SHIFT              (14U)
/*! PPW_RD_DIS - Page Program Wait Read Disable
 *  0b0..Enables subsequent reads
 *  0b1..Disables subsequent reads
 */
#define XSPI_AWRCR_PPW_RD_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_AWRCR_PPW_RD_DIS_SHIFT)) & XSPI_AWRCR_PPW_RD_DIS_MASK)

#define XSPI_AWRCR_PPW_WR_DIS_MASK               (0x8000U)
#define XSPI_AWRCR_PPW_WR_DIS_SHIFT              (15U)
/*! PPW_WR_DIS - Page Program Wait Write Disable
 *  0b0..Enables subsequent writes
 *  0b1..Disables subsequent writes
 */
#define XSPI_AWRCR_PPW_WR_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_AWRCR_PPW_WR_DIS_SHIFT)) & XSPI_AWRCR_PPW_WR_DIS_MASK)
/*! @} */

/*! @name DLLCR - DLL Flash Memory A Configuration */
/*! @{ */

#define XSPI_DLLCR_SLV_UPD_MASK                  (0x1U)
#define XSPI_DLLCR_SLV_UPD_SHIFT                 (0U)
/*! SLV_UPD - Subordinate Update
 *  0b0..Disables any further update on the DQS subordinate delay chain.
 *  0b1..Updates
 */
#define XSPI_DLLCR_SLV_UPD(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_UPD_SHIFT)) & XSPI_DLLCR_SLV_UPD_MASK)

#define XSPI_DLLCR_SLV_DLL_BYPASS_MASK           (0x2U)
#define XSPI_DLLCR_SLV_DLL_BYPASS_SHIFT          (1U)
/*! SLV_DLL_BYPASS - Subordinate DLL Bypass
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_DLLCR_SLV_DLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_DLL_BYPASS_SHIFT)) & XSPI_DLLCR_SLV_DLL_BYPASS_MASK)

#define XSPI_DLLCR_SLV_EN_MASK                   (0x4U)
#define XSPI_DLLCR_SLV_EN_SHIFT                  (2U)
/*! SLV_EN - Subordinate Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_DLLCR_SLV_EN(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_EN_SHIFT)) & XSPI_DLLCR_SLV_EN_MASK)

#define XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK          (0x8U)
#define XSPI_DLLCR_SLAVE_AUTO_UPDT_SHIFT         (3U)
/*! SLAVE_AUTO_UPDT - Subordinate Chain Auto-Update Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_DLLCR_SLAVE_AUTO_UPDT(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLAVE_AUTO_UPDT_SHIFT)) & XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK)

#define XSPI_DLLCR_DLL_CDL8_MASK                 (0x10U)
#define XSPI_DLLCR_DLL_CDL8_SHIFT                (4U)
/*! DLL_CDL8 - DLL Course Delay Line 8 Enable
 *  0b0..DLL is implemented to support up to 2x variation
 *  0b1..DLL is implemented to support up to 3x variation (BCS -> WCS)
 */
#define XSPI_DLLCR_DLL_CDL8(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_DLL_CDL8_SHIFT)) & XSPI_DLLCR_DLL_CDL8_MASK)

#define XSPI_DLLCR_SLV_DLY_FINE_MASK             (0xE0U)
#define XSPI_DLLCR_SLV_DLY_FINE_SHIFT            (5U)
/*! SLV_DLY_FINE - Fine Adjustment Delay Elements */
#define XSPI_DLLCR_SLV_DLY_FINE(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_DLY_FINE_SHIFT)) & XSPI_DLLCR_SLV_DLY_FINE_MASK)

#define XSPI_DLLCR_SLV_DLY_COARSE_MASK           (0xF00U)
#define XSPI_DLLCR_SLV_DLY_COARSE_SHIFT          (8U)
/*! SLV_DLY_COARSE - Delay Elements in Delay Tap */
#define XSPI_DLLCR_SLV_DLY_COARSE(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_DLY_COARSE_SHIFT)) & XSPI_DLLCR_SLV_DLY_COARSE_MASK)

#define XSPI_DLLCR_SLV_DLY_OFFSET_MASK           (0x7000U)
#define XSPI_DLLCR_SLV_DLY_OFFSET_SHIFT          (12U)
/*! SLV_DLY_OFFSET - T/16 Offset Delay Elements */
#define XSPI_DLLCR_SLV_DLY_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_DLY_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_DLY_OFFSET_MASK)

#define XSPI_DLLCR_SLV_FINE_OFFSET_MASK          (0xF0000U)
#define XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT         (16U)
/*! SLV_FINE_OFFSET - Fine Offset Delay Elements */
#define XSPI_DLLCR_SLV_FINE_OFFSET(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)

#define XSPI_DLLCR_DLLRES_MASK                   (0xF00000U)
#define XSPI_DLLCR_DLLRES_SHIFT                  (20U)
/*! DLLRES - DLL Resolution */
#define XSPI_DLLCR_DLLRES(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_DLLRES_SHIFT)) & XSPI_DLLCR_DLLRES_MASK)

#define XSPI_DLLCR_DLL_REFCNTR_MASK              (0xF000000U)
#define XSPI_DLLCR_DLL_REFCNTR_SHIFT             (24U)
/*! DLL_REFCNTR - DLL Reference Counter */
#define XSPI_DLLCR_DLL_REFCNTR(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_DLL_REFCNTR_SHIFT)) & XSPI_DLLCR_DLL_REFCNTR_MASK)

#define XSPI_DLLCR_FREQEN_MASK                   (0x40000000U)
#define XSPI_DLLCR_FREQEN_SHIFT                  (30U)
/*! FREQEN - Frequency Enable
 *  0b0..Low frequency
 *  0b1..High frequency
 */
#define XSPI_DLLCR_FREQEN(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_FREQEN_SHIFT)) & XSPI_DLLCR_FREQEN_MASK)

#define XSPI_DLLCR_DLLEN_MASK                    (0x80000000U)
#define XSPI_DLLCR_DLLEN_SHIFT                   (31U)
/*! DLLEN - DLL Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_DLLCR_DLLEN(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_DLLEN_SHIFT)) & XSPI_DLLCR_DLLEN_MASK)
/*! @} */

/* The count of XSPI_DLLCR */
#define XSPI_DLLCR_COUNT                         (1U)

/*! @name SFAR - Serial Flash Memory Address */
/*! @{ */

#define XSPI_SFAR_SFADR_MASK                     (0xFFFFFFFFU)
#define XSPI_SFAR_SFADR_SHIFT                    (0U)
/*! SFADR - Serial Flash Memory Address */
#define XSPI_SFAR_SFADR(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SFAR_SFADR_SHIFT)) & XSPI_SFAR_SFADR_MASK)
/*! @} */

/*! @name SFACR - Serial Flash Memory Address Configuration */
/*! @{ */

#define XSPI_SFACR_CAS_MASK                      (0xFU)
#define XSPI_SFACR_CAS_SHIFT                     (0U)
/*! CAS - Column Address Space */
#define XSPI_SFACR_CAS(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_CAS_SHIFT)) & XSPI_SFACR_CAS_MASK)

#define XSPI_SFACR_PPWB_MASK                     (0x1F00U)
#define XSPI_SFACR_PPWB_SHIFT                    (8U)
/*! PPWB - Page Program Boundary */
#define XSPI_SFACR_PPWB(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_PPWB_SHIFT)) & XSPI_SFACR_PPWB_MASK)

#define XSPI_SFACR_WA_MASK                       (0x10000U)
#define XSPI_SFACR_WA_SHIFT                      (16U)
/*! WA - Word Addressable
 *  0b0..Byte addressable
 *  0b1..Word (2-byte) addressable mode
 */
#define XSPI_SFACR_WA(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_WA_SHIFT)) & XSPI_SFACR_WA_MASK)

#define XSPI_SFACR_BYTE_SWAP_MASK                (0x20000U)
#define XSPI_SFACR_BYTE_SWAP_SHIFT               (17U)
/*! BYTE_SWAP - Byte Swapping
 *  0b0..One word of two bytes at addresses [n, n + 1]
 *  0b1..One word of two bytes at addresses [n + 1, n]
 */
#define XSPI_SFACR_BYTE_SWAP(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_BYTE_SWAP_SHIFT)) & XSPI_SFACR_BYTE_SWAP_MASK)

#define XSPI_SFACR_RX_BP_EN_MASK                 (0x40000U)
#define XSPI_SFACR_RX_BP_EN_SHIFT                (18U)
/*! RX_BP_EN - RX Backpressure Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_SFACR_RX_BP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_RX_BP_EN_SHIFT)) & XSPI_SFACR_RX_BP_EN_MASK)

#define XSPI_SFACR_CAS_INTRLVD_MASK              (0x100000U)
#define XSPI_SFACR_CAS_INTRLVD_SHIFT             (20U)
/*! CAS_INTRLVD - CAS Interleaving
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_SFACR_CAS_INTRLVD(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_CAS_INTRLVD_SHIFT)) & XSPI_SFACR_CAS_INTRLVD_MASK)

#define XSPI_SFACR_WA_4B_EN_MASK                 (0x200000U)
#define XSPI_SFACR_WA_4B_EN_SHIFT                (21U)
/*! WA_4B_EN - 32-Bit Address Mode Enable
 *  0b0..Disables.
 *  0b1..32-bit mode
 */
#define XSPI_SFACR_WA_4B_EN(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_WA_4B_EN_SHIFT)) & XSPI_SFACR_WA_4B_EN_MASK)

#define XSPI_SFACR_FORCE_A10_MASK                (0x400000U)
#define XSPI_SFACR_FORCE_A10_SHIFT               (22U)
/*! FORCE_A10 - 10th Bit Status
 *  0b0..Force
 *  0b1..Do not force
 */
#define XSPI_SFACR_FORCE_A10(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_FORCE_A10_SHIFT)) & XSPI_SFACR_FORCE_A10_MASK)

#define XSPI_SFACR_X16_DLLA_SLVFINE_OFFSET_MASK  (0xF000000U)
#define XSPI_SFACR_X16_DLLA_SLVFINE_OFFSET_SHIFT (24U)
/*! X16_DLLA_SLVFINE_OFFSET - Fine Offset Delay Elements in Incoming DQS1 Flash Memory A */
#define XSPI_SFACR_X16_DLLA_SLVFINE_OFFSET(x)    (((uint32_t)(((uint32_t)(x)) << XSPI_SFACR_X16_DLLA_SLVFINE_OFFSET_SHIFT)) & XSPI_SFACR_X16_DLLA_SLVFINE_OFFSET_MASK)
/*! @} */

/*! @name SMPR - Sampling */
/*! @{ */

#define XSPI_SMPR_FSPHS_MASK                     (0x20U)
#define XSPI_SMPR_FSPHS_SHIFT                    (5U)
/*! FSPHS - Full-Speed Phase
 *  0b0..Sampling at non-inverted clock
 *  0b1..Sampling at inverted clock
 */
#define XSPI_SMPR_FSPHS(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SMPR_FSPHS_SHIFT)) & XSPI_SMPR_FSPHS_MASK)

#define XSPI_SMPR_FSDLY_MASK                     (0x40U)
#define XSPI_SMPR_FSDLY_SHIFT                    (6U)
/*! FSDLY - Full-Speed Delay For Internal/Pad Loopback
 *  0b0..Same DQS
 *  0b1..Half cycle early DQS
 */
#define XSPI_SMPR_FSDLY(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SMPR_FSDLY_SHIFT)) & XSPI_SMPR_FSDLY_MASK)

#define XSPI_SMPR_DLLFSMPFA_MASK                 (0x7000000U)
#define XSPI_SMPR_DLLFSMPFA_SHIFT                (24U)
/*! DLLFSMPFA - DLL Nth Tap Flash Memory A */
#define XSPI_SMPR_DLLFSMPFA(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_SMPR_DLLFSMPFA_SHIFT)) & XSPI_SMPR_DLLFSMPFA_MASK)
/*! @} */

/*! @name RBSR - RX Buffer Status */
/*! @{ */

#define XSPI_RBSR_RDBFL_MASK                     (0xFFU)
#define XSPI_RBSR_RDBFL_SHIFT                    (0U)
/*! RDBFL - RX Buffer Fill Level */
#define XSPI_RBSR_RDBFL(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RBSR_RDBFL_SHIFT)) & XSPI_RBSR_RDBFL_MASK)

#define XSPI_RBSR_RDCTR_MASK                     (0xFFFF0000U)
#define XSPI_RBSR_RDCTR_SHIFT                    (16U)
/*! RDCTR - Read Counter */
#define XSPI_RBSR_RDCTR(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RBSR_RDCTR_SHIFT)) & XSPI_RBSR_RDCTR_MASK)
/*! @} */

/*! @name RBCT - RX Buffer Control */
/*! @{ */

#define XSPI_RBCT_WMRK_MASK                      (0x7FU)
#define XSPI_RBCT_WMRK_SHIFT                     (0U)
/*! WMRK - RX Buffer Watermark */
#define XSPI_RBCT_WMRK(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_RBCT_WMRK_SHIFT)) & XSPI_RBCT_WMRK_MASK)
/*! @} */

/*! @name AWRSR - AHB Write Status */
/*! @{ */

#define XSPI_AWRSR_SEQAUJOIN_MASK                (0x4U)
#define XSPI_AWRSR_SEQAUJOIN_SHIFT               (2U)
/*! SEQAUJOIN - Sequence Auto Join
 *  0b0..Not auto-joined
 *  0b1..Auto-joined
 */
#define XSPI_AWRSR_SEQAUJOIN(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_AWRSR_SEQAUJOIN_SHIFT)) & XSPI_AWRSR_SEQAUJOIN_MASK)
/*! @} */

/*! @name DLLSR - DLL Status */
/*! @{ */

#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK      (0xFU)
#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT     (0U)
/*! DLLA_SLV_COARSE_VAL - Coarse Delay Cells in Subordinate Delay Chain - Flash Memory A */
#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL(x)        (((uint32_t)(((uint32_t)(x)) << XSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT)) & XSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK)

#define XSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK        (0xF0U)
#define XSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT       (4U)
/*! DLLA_SLV_FINE_VAL - Fine Delay Cells in Subordinate Delay Chain */
#define XSPI_DLLSR_DLLA_SLV_FINE_VAL(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT)) & XSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK)

#define XSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK      (0x1000U)
#define XSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT     (12U)
/*! DLLA_FINE_UNDERFLOW - Fine Delay Chain Underflow - Flash Memory A
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_DLLSR_DLLA_FINE_UNDERFLOW(x)        (((uint32_t)(((uint32_t)(x)) << XSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT)) & XSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK)

#define XSPI_DLLSR_DLLA_RANGE_ERR_MASK           (0x2000U)
#define XSPI_DLLSR_DLLA_RANGE_ERR_SHIFT          (13U)
/*! DLLA_RANGE_ERR - DLL Manager Delay Chain Range Error - Flash Memory A
 *  0b0..In range
 *  0b1..Out of range
 */
#define XSPI_DLLSR_DLLA_RANGE_ERR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_DLLSR_DLLA_RANGE_ERR_SHIFT)) & XSPI_DLLSR_DLLA_RANGE_ERR_MASK)

#define XSPI_DLLSR_SLVA_LOCK_MASK                (0x4000U)
#define XSPI_DLLSR_SLVA_LOCK_SHIFT               (14U)
/*! SLVA_LOCK - Subordinate High Lock Status - Flash Memory A
 *  0b0..Not locked
 *  0b1..Locked
 */
#define XSPI_DLLSR_SLVA_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_DLLSR_SLVA_LOCK_SHIFT)) & XSPI_DLLSR_SLVA_LOCK_MASK)

#define XSPI_DLLSR_DLLA_LOCK_MASK                (0x8000U)
#define XSPI_DLLSR_DLLA_LOCK_SHIFT               (15U)
/*! DLLA_LOCK - DLL A Lock Status
 *  0b0..Not locked
 *  0b1..Locked
 */
#define XSPI_DLLSR_DLLA_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_DLLSR_DLLA_LOCK_SHIFT)) & XSPI_DLLSR_DLLA_LOCK_MASK)
/*! @} */

/*! @name DLCR - Data Learning Configuration */
/*! @{ */

#define XSPI_DLCR_DLP_SEL_FA_MASK                (0xC000U)
#define XSPI_DLCR_DLP_SEL_FA_SHIFT               (14U)
/*! DLP_SEL_FA - DLP Selection Flash Memory A
 *  0b00..Ignore pattern matching
 *  0b01..IO1
 *  0b10..IO3
 *  0b11..Both IO1 and IO3
 */
#define XSPI_DLCR_DLP_SEL_FA(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_DLCR_DLP_SEL_FA_SHIFT)) & XSPI_DLCR_DLP_SEL_FA_MASK)

#define XSPI_DLCR_DL_NONDLP_FLSH_MASK            (0x1000000U)
#define XSPI_DLCR_DL_NONDLP_FLSH_SHIFT           (24U)
/*! DL_NONDLP_FLSH - DLP Non-DLP Flash Memory Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_DLCR_DL_NONDLP_FLSH(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_DLCR_DL_NONDLP_FLSH_SHIFT)) & XSPI_DLCR_DL_NONDLP_FLSH_MASK)
/*! @} */

/*! @name DLSR_F - Data Learning Status Flash Memory */
/*! @{ */

#define XSPI_DLSR_F_NEG_EDGE_MASK                (0xFFU)
#define XSPI_DLSR_F_NEG_EDGE_SHIFT               (0U)
/*! NEG_EDGE - DLP Negative Edge Match */
#define XSPI_DLSR_F_NEG_EDGE(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_DLSR_F_NEG_EDGE_SHIFT)) & XSPI_DLSR_F_NEG_EDGE_MASK)

#define XSPI_DLSR_F_POS_EDGE_MASK                (0xFF00U)
#define XSPI_DLSR_F_POS_EDGE_SHIFT               (8U)
/*! POS_EDGE - DLP Positive Edge Match */
#define XSPI_DLSR_F_POS_EDGE(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_DLSR_F_POS_EDGE_SHIFT)) & XSPI_DLSR_F_POS_EDGE_MASK)

#define XSPI_DLSR_F_DLPFF_MASK                   (0x80000000U)
#define XSPI_DLSR_F_DLPFF_SHIFT                  (31U)
/*! DLPFF - DLP Failure Flag
 *  0b0..No failure
 *  0b1..Failure
 */
#define XSPI_DLSR_F_DLPFF(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_DLSR_F_DLPFF_SHIFT)) & XSPI_DLSR_F_DLPFF_MASK)
/*! @} */

/* The count of XSPI_DLSR_F */
#define XSPI_DLSR_F_COUNT                        (1U)

/*! @name TBSR - TX Buffer Status */
/*! @{ */

#define XSPI_TBSR_TRBFL_MASK                     (0x1FFU)
#define XSPI_TBSR_TRBFL_SHIFT                    (0U)
/*! TRBFL - TX Buffer Fill Level */
#define XSPI_TBSR_TRBFL(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_TBSR_TRBFL_SHIFT)) & XSPI_TBSR_TRBFL_MASK)

#define XSPI_TBSR_TRCTR_MASK                     (0xFFFF0000U)
#define XSPI_TBSR_TRCTR_SHIFT                    (16U)
/*! TRCTR - Transmit Counter */
#define XSPI_TBSR_TRCTR(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_TBSR_TRCTR_SHIFT)) & XSPI_TBSR_TRCTR_MASK)
/*! @} */

/*! @name TBDR - TX Buffer Data */
/*! @{ */

#define XSPI_TBDR_TXDATA_MASK                    (0xFFFFFFFFU)
#define XSPI_TBDR_TXDATA_SHIFT                   (0U)
/*! TXDATA - TX Data */
#define XSPI_TBDR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TBDR_TXDATA_SHIFT)) & XSPI_TBDR_TXDATA_MASK)
/*! @} */

/*! @name TBCT - TX Buffer Control */
/*! @{ */

#define XSPI_TBCT_WMRK_MASK                      (0xFFU)
#define XSPI_TBCT_WMRK_SHIFT                     (0U)
/*! WMRK - TX Buffer Watermark */
#define XSPI_TBCT_WMRK(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_TBCT_WMRK_SHIFT)) & XSPI_TBCT_WMRK_MASK)
/*! @} */

/*! @name SR - Status */
/*! @{ */

#define XSPI_SR_BUSY_MASK                        (0x1U)
#define XSPI_SR_BUSY_SHIFT                       (0U)
/*! BUSY - Module Busy
 *  0b0..Not busy
 *  0b1..Busy
 */
#define XSPI_SR_BUSY(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_SR_BUSY_SHIFT)) & XSPI_SR_BUSY_MASK)

#define XSPI_SR_IP_ACC_MASK                      (0x2U)
#define XSPI_SR_IP_ACC_SHIFT                     (1U)
/*! IP_ACC - IP Access
 *  0b0..Not initiated by IP bus
 *  0b1..Initiated by IP bus
 */
#define XSPI_SR_IP_ACC(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_IP_ACC_SHIFT)) & XSPI_SR_IP_ACC_MASK)

#define XSPI_SR_AHB_ACC_MASK                     (0x4U)
#define XSPI_SR_AHB_ACC_SHIFT                    (2U)
/*! AHB_ACC - AHB Read Access
 *  0b0..Not initiated by AHB bus
 *  0b1..Initiated by AHB bus
 */
#define XSPI_SR_AHB_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB_ACC_SHIFT)) & XSPI_SR_AHB_ACC_MASK)

#define XSPI_SR_AWRACC_MASK                      (0x10U)
#define XSPI_SR_AWRACC_SHIFT                     (4U)
/*! AWRACC - AHB Write Access
 *  0b0..No AHB write access
 *  0b1..AHB write access
 */
#define XSPI_SR_AWRACC(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AWRACC_SHIFT)) & XSPI_SR_AWRACC_MASK)

#define XSPI_SR_AHBTRN_MASK                      (0x40U)
#define XSPI_SR_AHBTRN_SHIFT                     (6U)
/*! AHBTRN - AHB Access Transaction Pending
 *  0b0..No pending request
 *  0b1..Request is pending
 */
#define XSPI_SR_AHBTRN(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHBTRN_SHIFT)) & XSPI_SR_AHBTRN_MASK)

#define XSPI_SR_AHB0NE_MASK                      (0x80U)
#define XSPI_SR_AHB0NE_SHIFT                     (7U)
/*! AHB0NE - AHB Buffer 0 Not Empty
 *  0b0..Empty
 *  0b1..Not empty
 */
#define XSPI_SR_AHB0NE(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB0NE_SHIFT)) & XSPI_SR_AHB0NE_MASK)

#define XSPI_SR_AHB1NE_MASK                      (0x100U)
#define XSPI_SR_AHB1NE_SHIFT                     (8U)
/*! AHB1NE - AHB Buffer 1 Not Empty
 *  0b0..Empty
 *  0b1..Not empty
 */
#define XSPI_SR_AHB1NE(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB1NE_SHIFT)) & XSPI_SR_AHB1NE_MASK)

#define XSPI_SR_AHB2NE_MASK                      (0x200U)
#define XSPI_SR_AHB2NE_SHIFT                     (9U)
/*! AHB2NE - AHB Buffer 2 Not Empty
 *  0b0..Empty
 *  0b1..Not empty
 */
#define XSPI_SR_AHB2NE(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB2NE_SHIFT)) & XSPI_SR_AHB2NE_MASK)

#define XSPI_SR_AHB3NE_MASK                      (0x400U)
#define XSPI_SR_AHB3NE_SHIFT                     (10U)
/*! AHB3NE - AHB Buffer 3 Not Empty
 *  0b0..Empty
 *  0b1..Not empty
 */
#define XSPI_SR_AHB3NE(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB3NE_SHIFT)) & XSPI_SR_AHB3NE_MASK)

#define XSPI_SR_AHB0FUL_MASK                     (0x800U)
#define XSPI_SR_AHB0FUL_SHIFT                    (11U)
/*! AHB0FUL - AHB Buffer 0 Full
 *  0b0..Not full
 *  0b1..Full
 */
#define XSPI_SR_AHB0FUL(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB0FUL_SHIFT)) & XSPI_SR_AHB0FUL_MASK)

#define XSPI_SR_AHB1FUL_MASK                     (0x1000U)
#define XSPI_SR_AHB1FUL_SHIFT                    (12U)
/*! AHB1FUL - AHB Buffer 1 Full
 *  0b0..Not full
 *  0b1..Full
 */
#define XSPI_SR_AHB1FUL(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB1FUL_SHIFT)) & XSPI_SR_AHB1FUL_MASK)

#define XSPI_SR_AHB2FUL_MASK                     (0x2000U)
#define XSPI_SR_AHB2FUL_SHIFT                    (13U)
/*! AHB2FUL - AHB Buffer 2 Full
 *  0b0..Not full
 *  0b1..Full
 */
#define XSPI_SR_AHB2FUL(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB2FUL_SHIFT)) & XSPI_SR_AHB2FUL_MASK)

#define XSPI_SR_AHB3FUL_MASK                     (0x4000U)
#define XSPI_SR_AHB3FUL_SHIFT                    (14U)
/*! AHB3FUL - AHB Buffer 3 Full
 *  0b0..Not full
 *  0b1..Full
 */
#define XSPI_SR_AHB3FUL(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SR_AHB3FUL_SHIFT)) & XSPI_SR_AHB3FUL_MASK)

#define XSPI_SR_ARB_LCK_MASK                     (0x8000U)
#define XSPI_SR_ARB_LCK_SHIFT                    (15U)
/*! ARB_LCK - Arbitration Lock Status
 *  0b0..Not locked
 *  0b1..Locked
 */
#define XSPI_SR_ARB_LCK(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_SR_ARB_LCK_SHIFT)) & XSPI_SR_ARB_LCK_MASK)

#define XSPI_SR_RXWE_MASK                        (0x10000U)
#define XSPI_SR_RXWE_SHIFT                       (16U)
/*! RXWE - RX Buffer Watermark Exceeded
 *  0b0..Not exceeded
 *  0b1..Exceeded
 */
#define XSPI_SR_RXWE(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_SR_RXWE_SHIFT)) & XSPI_SR_RXWE_MASK)

#define XSPI_SR_RXFULL_MASK                      (0x80000U)
#define XSPI_SR_RXFULL_SHIFT                     (19U)
/*! RXFULL - RX Buffer Full
 *  0b0..Not full
 *  0b1..Full
 */
#define XSPI_SR_RXFULL(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_RXFULL_SHIFT)) & XSPI_SR_RXFULL_MASK)

#define XSPI_SR_ARB_STATE_MASK                   (0x700000U)
#define XSPI_SR_ARB_STATE_SHIFT                  (20U)
/*! ARB_STATE - XSPI Arbitration State
 *  0b000..Idle
 *  0b001..ARB - Arbitration
 *  0b010..AHBWR_PROC - AHB write processing
 *  0b011..AHBRD_PROC - AHB read processing
 *  0b101..TG_PROC - IP command processing
 *  0b110..PROC_FIN - XSPI processing finish wait
 *  0b111..RDSR_PROC - RDSR read processing
 *  *..
 */
#define XSPI_SR_ARB_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_SR_ARB_STATE_SHIFT)) & XSPI_SR_ARB_STATE_MASK)

#define XSPI_SR_RXDMA_MASK                       (0x800000U)
#define XSPI_SR_RXDMA_SHIFT                      (23U)
/*! RXDMA - RX Buffer DMA
 *  0b0..Not active
 *  0b1..Active
 */
#define XSPI_SR_RXDMA(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_SR_RXDMA_SHIFT)) & XSPI_SR_RXDMA_MASK)

#define XSPI_SR_TXNE_MASK                        (0x1000000U)
#define XSPI_SR_TXNE_SHIFT                       (24U)
/*! TXNE - TX Buffer Not Empty
 *  0b0..Empty
 *  0b1..Not empty
 */
#define XSPI_SR_TXNE(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_SR_TXNE_SHIFT)) & XSPI_SR_TXNE_MASK)

#define XSPI_SR_TXWA_MASK                        (0x2000000U)
#define XSPI_SR_TXWA_SHIFT                       (25U)
/*! TXWA - TX Buffer Watermark Available
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_SR_TXWA(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_SR_TXWA_SHIFT)) & XSPI_SR_TXWA_MASK)

#define XSPI_SR_TXDMA_MASK                       (0x4000000U)
#define XSPI_SR_TXDMA_SHIFT                      (26U)
/*! TXDMA - TX DMA
 *  0b0..Disabled or not processing the DMA request
 *  0b1..Enabled and processing DMA request
 */
#define XSPI_SR_TXDMA(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_SR_TXDMA_SHIFT)) & XSPI_SR_TXDMA_MASK)

#define XSPI_SR_TXFULL_MASK                      (0x8000000U)
#define XSPI_SR_TXFULL_SHIFT                     (27U)
/*! TXFULL - TX Buffer Full
 *  0b0..Not full
 *  0b1..Full
 */
#define XSPI_SR_TXFULL(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SR_TXFULL_SHIFT)) & XSPI_SR_TXFULL_MASK)
/*! @} */

/*! @name FR - Flag */
/*! @{ */

#define XSPI_FR_TFF_MASK                         (0x1U)
#define XSPI_FR_TFF_SHIFT                        (0U)
/*! TFF - IP Command Transaction Finished Flag
 *  0b0..Not completed
 *  0b0..No action
 *  0b1..Completed
 *  0b1..Clears flag
 */
#define XSPI_FR_TFF(x)                           (((uint32_t)(((uint32_t)(x)) << XSPI_FR_TFF_SHIFT)) & XSPI_FR_TFF_MASK)

#define XSPI_FR_RDADDR_MASK                      (0x2U)
#define XSPI_FR_RDADDR_SHIFT                     (1U)
/*! RDADDR - AHB Read Address Error Flag
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears flag
 */
#define XSPI_FR_RDADDR(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_FR_RDADDR_SHIFT)) & XSPI_FR_RDADDR_MASK)

#define XSPI_FR_PERFOVF_MASK                     (0x4U)
#define XSPI_FR_PERFOVF_SHIFT                    (2U)
/*! PERFOVF - AHB Performance Monitor Overflow Flag
 *  0b0..No overflow
 *  0b0..No action
 *  0b1..Overflow
 *  0b1..Clears flags
 */
#define XSPI_FR_PERFOVF(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_FR_PERFOVF_SHIFT)) & XSPI_FR_PERFOVF_MASK)

#define XSPI_FR_IPEDERR_MASK                     (0x20U)
#define XSPI_FR_IPEDERR_SHIFT                    (5U)
/*! IPEDERR - IPED RX Decryption Error Flag
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears error flag
 */
#define XSPI_FR_IPEDERR(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_FR_IPEDERR_SHIFT)) & XSPI_FR_IPEDERR_MASK)

#define XSPI_FR_IPIEF_MASK                       (0x40U)
#define XSPI_FR_IPIEF_SHIFT                      (6U)
/*! IPIEF - IP Command Trigger Fail Error Flag
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears error flag
 */
#define XSPI_FR_IPIEF(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_FR_IPIEF_SHIFT)) & XSPI_FR_IPIEF_MASK)

#define XSPI_FR_PPWF_MASK                        (0x100U)
#define XSPI_FR_PPWF_SHIFT                       (8U)
/*! PPWF - Page-Program Wait Flag
 *  0b0..No page program wait
 *  0b0..No action
 *  0b1..Page program wait in effect
 *  0b1..Clears flag
 */
#define XSPI_FR_PPWF(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_FR_PPWF_SHIFT)) & XSPI_FR_PPWF_MASK)

#define XSPI_FR_ABOF_MASK                        (0x1000U)
#define XSPI_FR_ABOF_SHIFT                       (12U)
/*! ABOF - AHB Buffer Overflow Flag
 *  0b0..No overflow
 *  0b0..No action
 *  0b1..Overflow
 *  0b1..Clears overflow flag
 */
#define XSPI_FR_ABOF(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_FR_ABOF_SHIFT)) & XSPI_FR_ABOF_MASK)

#define XSPI_FR_AIBSEF_MASK                      (0x2000U)
#define XSPI_FR_AIBSEF_SHIFT                     (13U)
/*! AIBSEF - AHB Illegal Burst Size Error Flag
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears error flag
 */
#define XSPI_FR_AIBSEF(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_FR_AIBSEF_SHIFT)) & XSPI_FR_AIBSEF_MASK)

#define XSPI_FR_AITEF_MASK                       (0x4000U)
#define XSPI_FR_AITEF_SHIFT                      (14U)
/*! AITEF - AHB Illegal Transaction Error Flag
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears error flag
 */
#define XSPI_FR_AITEF(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_FR_AITEF_SHIFT)) & XSPI_FR_AITEF_MASK)

#define XSPI_FR_AAEF_MASK                        (0x8000U)
#define XSPI_FR_AAEF_SHIFT                       (15U)
/*! AAEF - AHB Abort Error Flag
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears error flag
 */
#define XSPI_FR_AAEF(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_FR_AAEF_SHIFT)) & XSPI_FR_AAEF_MASK)

#define XSPI_FR_RBDF_MASK                        (0x10000U)
#define XSPI_FR_RBDF_SHIFT                       (16U)
/*! RBDF - RX Buffer Drain Flag
 *  0b0..RX buffer is not over the watermark
 *  0b0..No action
 *  0b1..RX buffer is over the watermark
 *  0b1..Clears flag if RX buffer is not over the watermark after POP
 */
#define XSPI_FR_RBDF(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_FR_RBDF_SHIFT)) & XSPI_FR_RBDF_MASK)

#define XSPI_FR_RBOF_MASK                        (0x20000U)
#define XSPI_FR_RBOF_SHIFT                       (17U)
/*! RBOF - RX Buffer Overflow Flag
 *  0b0..No overflow
 *  0b0..No action
 *  0b1..Overflow
 *  0b1..Clears flag
 */
#define XSPI_FR_RBOF(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_FR_RBOF_SHIFT)) & XSPI_FR_RBOF_MASK)

#define XSPI_FR_ILLINE_MASK                      (0x800000U)
#define XSPI_FR_ILLINE_SHIFT                     (23U)
/*! ILLINE - Illegal Instruction Error Flag
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears error flag
 */
#define XSPI_FR_ILLINE(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_FR_ILLINE_SHIFT)) & XSPI_FR_ILLINE_MASK)

#define XSPI_FR_DLLUNLCK_MASK                    (0x1000000U)
#define XSPI_FR_DLLUNLCK_SHIFT                   (24U)
/*! DLLUNLCK - DLL Unlock
 *  0b0..No unlock event
 *  0b0..No action
 *  0b1..Unlock event has occurred
 *  0b1..Clears the flag
 */
#define XSPI_FR_DLLUNLCK(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_FR_DLLUNLCK_SHIFT)) & XSPI_FR_DLLUNLCK_MASK)

#define XSPI_FR_TBUF_MASK                        (0x4000000U)
#define XSPI_FR_TBUF_SHIFT                       (26U)
/*! TBUF - TX Buffer Underrun Flag
 *  0b0..No underrun
 *  0b0..No action
 *  0b1..Underrun
 *  0b1..Clears flag
 */
#define XSPI_FR_TBUF(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_FR_TBUF_SHIFT)) & XSPI_FR_TBUF_MASK)

#define XSPI_FR_TBFF_MASK                        (0x8000000U)
#define XSPI_FR_TBFF_SHIFT                       (27U)
/*! TBFF - TX Buffer Fill Flag
 *  0b0..No room in the TX buffer
 *  0b0..No action
 *  0b1..TX buffer has room
 *  0b1..Clears flag
 */
#define XSPI_FR_TBFF(x)                          (((uint32_t)(((uint32_t)(x)) << XSPI_FR_TBFF_SHIFT)) & XSPI_FR_TBFF_MASK)

#define XSPI_FR_DLLABRT_MASK                     (0x10000000U)
#define XSPI_FR_DLLABRT_SHIFT                    (28U)
/*! DLLABRT - DLL Terminate
 *  0b0..No lock has occurred
 *  0b0..No action
 *  0b1..DLL unlock occurred
 *  0b1..Clears flag
 */
#define XSPI_FR_DLLABRT(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_FR_DLLABRT_SHIFT)) & XSPI_FR_DLLABRT_MASK)

#define XSPI_FR_DLPFF_MASK                       (0x80000000U)
#define XSPI_FR_DLPFF_SHIFT                      (31U)
/*! DLPFF - Data Learning Pattern Failure Flag
 *  0b0..No failure
 *  0b0..No action
 *  0b1..Failure
 *  0b1..Clears flag
 */
#define XSPI_FR_DLPFF(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_FR_DLPFF_SHIFT)) & XSPI_FR_DLPFF_MASK)
/*! @} */

/*! @name RSER - Interrupt and DMA Request Enable */
/*! @{ */

#define XSPI_RSER_TFIE_MASK                      (0x1U)
#define XSPI_RSER_TFIE_SHIFT                     (0U)
/*! TFIE - Transaction Finished Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_TFIE(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_TFIE_SHIFT)) & XSPI_RSER_TFIE_MASK)

#define XSPI_RSER_RDADDRIE_MASK                  (0x2U)
#define XSPI_RSER_RDADDRIE_SHIFT                 (1U)
/*! RDADDRIE - AHB Read Address Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_RDADDRIE(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_RDADDRIE_SHIFT)) & XSPI_RSER_RDADDRIE_MASK)

#define XSPI_RSER_PERFOVIE_MASK                  (0x4U)
#define XSPI_RSER_PERFOVIE_SHIFT                 (2U)
/*! PERFOVIE - AHB Performance Monitor Overflow Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_PERFOVIE(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_PERFOVIE_SHIFT)) & XSPI_RSER_PERFOVIE_MASK)

#define XSPI_RSER_IPEDIE_MASK                    (0x20U)
#define XSPI_RSER_IPEDIE_SHIFT                   (5U)
/*! IPEDIE - IPED RX Decryption Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_IPEDIE(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_IPEDIE_SHIFT)) & XSPI_RSER_IPEDIE_MASK)

#define XSPI_RSER_IPIEIE_MASK                    (0x40U)
#define XSPI_RSER_IPIEIE_SHIFT                   (6U)
/*! IPIEIE - IP Command Trigger Fail Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_IPIEIE(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_IPIEIE_SHIFT)) & XSPI_RSER_IPIEIE_MASK)

#define XSPI_RSER_PPWIE_MASK                     (0x100U)
#define XSPI_RSER_PPWIE_SHIFT                    (8U)
/*! PPWIE - Page-Program Wait Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_PPWIE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_PPWIE_SHIFT)) & XSPI_RSER_PPWIE_MASK)

#define XSPI_RSER_ABOIE_MASK                     (0x1000U)
#define XSPI_RSER_ABOIE_SHIFT                    (12U)
/*! ABOIE - AHB Buffer Overflow Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_ABOIE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_ABOIE_SHIFT)) & XSPI_RSER_ABOIE_MASK)

#define XSPI_RSER_AIBSIE_MASK                    (0x2000U)
#define XSPI_RSER_AIBSIE_SHIFT                   (13U)
/*! AIBSIE - AHB Illegal Burst Size Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_AIBSIE(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_AIBSIE_SHIFT)) & XSPI_RSER_AIBSIE_MASK)

#define XSPI_RSER_AITIE_MASK                     (0x4000U)
#define XSPI_RSER_AITIE_SHIFT                    (14U)
/*! AITIE - AHB Illegal Transaction Error Interrupt Enable flag
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_AITIE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_AITIE_SHIFT)) & XSPI_RSER_AITIE_MASK)

#define XSPI_RSER_AAIE_MASK                      (0x8000U)
#define XSPI_RSER_AAIE_SHIFT                     (15U)
/*! AAIE - AHB Abort Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_AAIE(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_AAIE_SHIFT)) & XSPI_RSER_AAIE_MASK)

#define XSPI_RSER_RBDIE_MASK                     (0x10000U)
#define XSPI_RSER_RBDIE_SHIFT                    (16U)
/*! RBDIE - RX Buffer Drain Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_RBDIE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_RBDIE_SHIFT)) & XSPI_RSER_RBDIE_MASK)

#define XSPI_RSER_RBOIE_MASK                     (0x20000U)
#define XSPI_RSER_RBOIE_SHIFT                    (17U)
/*! RBOIE - RX Buffer Overflow Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_RBOIE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_RBOIE_SHIFT)) & XSPI_RSER_RBOIE_MASK)

#define XSPI_RSER_RBDDE_MASK                     (0x200000U)
#define XSPI_RSER_RBDDE_SHIFT                    (21U)
/*! RBDDE - RX Buffer Drain DMA Enable
 *  0b0..Disabled
 *  0b1..Enables
 */
#define XSPI_RSER_RBDDE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_RBDDE_SHIFT)) & XSPI_RSER_RBDDE_MASK)

#define XSPI_RSER_ILLINIE_MASK                   (0x800000U)
#define XSPI_RSER_ILLINIE_SHIFT                  (23U)
/*! ILLINIE - Illegal Instruction Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_ILLINIE(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_ILLINIE_SHIFT)) & XSPI_RSER_ILLINIE_MASK)

#define XSPI_RSER_DLLULIE_MASK                   (0x1000000U)
#define XSPI_RSER_DLLULIE_SHIFT                  (24U)
/*! DLLULIE - DLL unlock interrupt enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_DLLULIE(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_DLLULIE_SHIFT)) & XSPI_RSER_DLLULIE_MASK)

#define XSPI_RSER_TBFDE_MASK                     (0x2000000U)
#define XSPI_RSER_TBFDE_SHIFT                    (25U)
/*! TBFDE - TX Buffer Fill DMA Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_TBFDE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_TBFDE_SHIFT)) & XSPI_RSER_TBFDE_MASK)

#define XSPI_RSER_TBUIE_MASK                     (0x4000000U)
#define XSPI_RSER_TBUIE_SHIFT                    (26U)
/*! TBUIE - TX Buffer Underrun Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_TBUIE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_TBUIE_SHIFT)) & XSPI_RSER_TBUIE_MASK)

#define XSPI_RSER_TBFIE_MASK                     (0x8000000U)
#define XSPI_RSER_TBFIE_SHIFT                    (27U)
/*! TBFIE - TX Buffer Fill Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_TBFIE(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_TBFIE_SHIFT)) & XSPI_RSER_TBFIE_MASK)

#define XSPI_RSER_DLPFIE_MASK                    (0x80000000U)
#define XSPI_RSER_DLPFIE_SHIFT                   (31U)
/*! DLPFIE - Data Learning Pattern Failure Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_RSER_DLPFIE(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_RSER_DLPFIE_SHIFT)) & XSPI_RSER_DLPFIE_MASK)
/*! @} */

/*! @name SPNDST - Sequence Suspend Status */
/*! @{ */

#define XSPI_SPNDST_STATE_MASK                   (0x3U)
#define XSPI_SPNDST_STATE_SHIFT                  (0U)
/*! STATE - Suspended Resume State
 *  0b00..No suspended transaction pending
 *  0b01..Suspended transaction waiting to be resumed
 *  0b10..Not applicable
 *  0b11..Suspended transaction is resumed
 */
#define XSPI_SPNDST_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_SPNDST_STATE_SHIFT)) & XSPI_SPNDST_STATE_MASK)

#define XSPI_SPNDST_SPDSBUF_MASK                 (0x30U)
#define XSPI_SPNDST_SPDSBUF_SHIFT                (4U)
/*! SPDSBUF - Suspended Sub-Buffer */
#define XSPI_SPNDST_SPDSBUF(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_SPNDST_SPDSBUF_SHIFT)) & XSPI_SPNDST_SPDSBUF_MASK)

#define XSPI_SPNDST_SPDBUF_MASK                  (0xC0U)
#define XSPI_SPNDST_SPDBUF_SHIFT                 (6U)
/*! SPDBUF - Suspended Buffer */
#define XSPI_SPNDST_SPDBUF(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_SPNDST_SPDBUF_SHIFT)) & XSPI_SPNDST_SPDBUF_MASK)

#define XSPI_SPNDST_DATLFT_MASK                  (0x3FE00U)
#define XSPI_SPNDST_DATLFT_SHIFT                 (9U)
/*! DATLFT - Data Left */
#define XSPI_SPNDST_DATLFT(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_SPNDST_DATLFT_SHIFT)) & XSPI_SPNDST_DATLFT_MASK)
/*! @} */

/*! @name SPTRCLR - Sequence Pointer Clear */
/*! @{ */

#define XSPI_SPTRCLR_BFPTRC_MASK                 (0x1U)
#define XSPI_SPTRCLR_BFPTRC_SHIFT                (0U)
/*! BFPTRC - Buffer Pointer Clear
 *  0b0..Conveys no useful information
 *  0b0..No action
 *  0b1..Clears the sequence pointer
 */
#define XSPI_SPTRCLR_BFPTRC(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_BFPTRC_SHIFT)) & XSPI_SPTRCLR_BFPTRC_MASK)

#define XSPI_SPTRCLR_IPPTRC_MASK                 (0x100U)
#define XSPI_SPTRCLR_IPPTRC_SHIFT                (8U)
/*! IPPTRC - IP Pointer Clear
 *  0b0..Conveys no useful information
 *  0b0..No action
 *  0b1..Clears the sequence pointer
 */
#define XSPI_SPTRCLR_IPPTRC(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_IPPTRC_SHIFT)) & XSPI_SPTRCLR_IPPTRC_MASK)

#define XSPI_SPTRCLR_ABRT_CLR_MASK               (0x10000U)
#define XSPI_SPTRCLR_ABRT_CLR_SHIFT              (16U)
/*! ABRT_CLR - Flash Memory Abort-AHB Buffer Clear
 *  0b0..No action
 *  0b1..Clears pointers and terminates transaction
 */
#define XSPI_SPTRCLR_ABRT_CLR(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)

#define XSPI_SPTRCLR_PREFETCH_DIS_MASK           (0x20000U)
#define XSPI_SPTRCLR_PREFETCH_DIS_SHIFT          (17U)
/*! PREFETCH_DIS - Prefetch Disable
 *  0b0..Enables
 *  0b1..Disables
 */
#define XSPI_SPTRCLR_PREFETCH_DIS(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_PREFETCH_DIS_SHIFT)) & XSPI_SPTRCLR_PREFETCH_DIS_MASK)

#define XSPI_SPTRCLR_STREAM_EN_MASK              (0x40000U)
#define XSPI_SPTRCLR_STREAM_EN_SHIFT             (18U)
/*! STREAM_EN - Enable Streaming Port
 *  0b0..Enables
 *  0b1..Disables
 */
#define XSPI_SPTRCLR_STREAM_EN(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_STREAM_EN_SHIFT)) & XSPI_SPTRCLR_STREAM_EN_MASK)

#define XSPI_SPTRCLR_OTFAD_BNDRY_MASK            (0x3000000U)
#define XSPI_SPTRCLR_OTFAD_BNDRY_SHIFT           (24U)
/*! OTFAD_BNDRY - OTFAD Prefetch Address Boundary
 *  0b00..No prefetch address boundary
 *  0b01..Prefetch address boundary is 1K.
 *  *..
 */
#define XSPI_SPTRCLR_OTFAD_BNDRY(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_OTFAD_BNDRY_SHIFT)) & XSPI_SPTRCLR_OTFAD_BNDRY_MASK)
/*! @} */

/*! @name SFAD - Serial Flash Memory Top Address */
/*! @{ */

#define XSPI_SFAD_TPAD_MASK                      (0xFFFFFC00U)
#define XSPI_SFAD_TPAD_SHIFT                     (10U)
/*! TPAD - Top Address */
#define XSPI_SFAD_TPAD(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_SFAD_TPAD_SHIFT)) & XSPI_SFAD_TPAD_MASK)
/*! @} */

/* The count of XSPI_SFAD */
#define XSPI_SFAD_COUNT                          (1U)

/* The count of XSPI_SFAD */
#define XSPI_SFAD_COUNT2                         (2U)

/*! @name DLPR - Data Learning Pattern */
/*! @{ */

#define XSPI_DLPR_DLPV_MASK                      (0xFFFFFFFFU)
#define XSPI_DLPR_DLPV_SHIFT                     (0U)
/*! DLPV - Data Learning Pattern */
#define XSPI_DLPR_DLPV(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_DLPR_DLPV_SHIFT)) & XSPI_DLPR_DLPV_MASK)
/*! @} */

/*! @name FAIL_ADDR - Flash Memory A Failing Address Status */
/*! @{ */

#define XSPI_FAIL_ADDR_ADDR_MASK                 (0xFFFFFFFFU)
#define XSPI_FAIL_ADDR_ADDR_SHIFT                (0U)
/*! ADDR - Failing Address */
#define XSPI_FAIL_ADDR_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_FAIL_ADDR_ADDR_SHIFT)) & XSPI_FAIL_ADDR_ADDR_MASK)
/*! @} */

/* The count of XSPI_FAIL_ADDR */
#define XSPI_FAIL_ADDR_COUNT                     (1U)

/*! @name RBDR - RX Buffer Data */
/*! @{ */

#define XSPI_RBDR_RXDATA_MASK                    (0xFFFFFFFFU)
#define XSPI_RBDR_RXDATA_SHIFT                   (0U)
/*! RXDATA - RX Data */
#define XSPI_RBDR_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_RBDR_RXDATA_SHIFT)) & XSPI_RBDR_RXDATA_MASK)
/*! @} */

/* The count of XSPI_RBDR */
#define XSPI_RBDR_COUNT                          (64U)

/*! @name LUTKEY - LUT Key */
/*! @{ */

#define XSPI_LUTKEY_KEY_MASK                     (0xFFFFFFFFU)
#define XSPI_LUTKEY_KEY_SHIFT                    (0U)
/*! KEY - Key */
#define XSPI_LUTKEY_KEY(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_LUTKEY_KEY_SHIFT)) & XSPI_LUTKEY_KEY_MASK)
/*! @} */

/*! @name LCKCR - LUT Lock Configuration */
/*! @{ */

#define XSPI_LCKCR_LOCK_MASK                     (0x1U)
#define XSPI_LCKCR_LOCK_SHIFT                    (0U)
/*! LOCK - Lock LUT
 *  0b0..No action
 *  0b1..Locks
 */
#define XSPI_LCKCR_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_LCKCR_LOCK_SHIFT)) & XSPI_LCKCR_LOCK_MASK)

#define XSPI_LCKCR_UNLOCK_MASK                   (0x2U)
#define XSPI_LCKCR_UNLOCK_SHIFT                  (1U)
/*! UNLOCK - Unlock LUT
 *  0b0..No action
 *  0b1..Unlocks
 */
#define XSPI_LCKCR_UNLOCK(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_LCKCR_UNLOCK_SHIFT)) & XSPI_LCKCR_UNLOCK_MASK)
/*! @} */

/*! @name LUT - Lookup Table */
/*! @{ */

#define XSPI_LUT_OPRND0_MASK                     (0xFFU)
#define XSPI_LUT_OPRND0_SHIFT                    (0U)
/*! OPRND0 - Operand for INSTR0 */
#define XSPI_LUT_OPRND0(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_LUT_OPRND0_SHIFT)) & XSPI_LUT_OPRND0_MASK)

#define XSPI_LUT_PAD0_MASK                       (0x300U)
#define XSPI_LUT_PAD0_SHIFT                      (8U)
/*! PAD0 - Pads for INSTR0
 *  0b00..1
 *  0b01..2
 *  0b10..4
 *  0b11..8
 */
#define XSPI_LUT_PAD0(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_LUT_PAD0_SHIFT)) & XSPI_LUT_PAD0_MASK)

#define XSPI_LUT_INSTR0_MASK                     (0xFC00U)
#define XSPI_LUT_INSTR0_SHIFT                    (10U)
/*! INSTR0 - Instruction 0 */
#define XSPI_LUT_INSTR0(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_LUT_INSTR0_SHIFT)) & XSPI_LUT_INSTR0_MASK)

#define XSPI_LUT_OPRND1_MASK                     (0xFF0000U)
#define XSPI_LUT_OPRND1_SHIFT                    (16U)
/*! OPRND1 - Operand for INSTR1 */
#define XSPI_LUT_OPRND1(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_LUT_OPRND1_SHIFT)) & XSPI_LUT_OPRND1_MASK)

#define XSPI_LUT_PAD1_MASK                       (0x3000000U)
#define XSPI_LUT_PAD1_SHIFT                      (24U)
/*! PAD1 - Pads for INSTR1
 *  0b00..1
 *  0b01..2
 *  0b10..4
 *  0b11..8
 */
#define XSPI_LUT_PAD1(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_LUT_PAD1_SHIFT)) & XSPI_LUT_PAD1_MASK)

#define XSPI_LUT_INSTR1_MASK                     (0xFC000000U)
#define XSPI_LUT_INSTR1_SHIFT                    (26U)
/*! INSTR1 - Instruction 1 */
#define XSPI_LUT_INSTR1(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_LUT_INSTR1_SHIFT)) & XSPI_LUT_INSTR1_MASK)
/*! @} */

/* The count of XSPI_LUT */
#define XSPI_LUT_COUNT                           (80U)

/*! @name BUF_ADDR_RANGE - AHB Buffer 0 Sub Buffer 0 Start and End Address Range..AHB Buffer 3 Sub Buffer 3 Start and End Address Range */
/*! @{ */

#define XSPI_BUF_ADDR_RANGE_STARTADR_MASK        (0xFFFFU)
#define XSPI_BUF_ADDR_RANGE_STARTADR_SHIFT       (0U)
/*! STARTADR - Start Address */
#define XSPI_BUF_ADDR_RANGE_STARTADR(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_BUF_ADDR_RANGE_STARTADR_SHIFT)) & XSPI_BUF_ADDR_RANGE_STARTADR_MASK)

#define XSPI_BUF_ADDR_RANGE_ENDADR_MASK          (0xFFFF0000U)
#define XSPI_BUF_ADDR_RANGE_ENDADR_SHIFT         (16U)
/*! ENDADR - End Address */
#define XSPI_BUF_ADDR_RANGE_ENDADR(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_BUF_ADDR_RANGE_ENDADR_SHIFT)) & XSPI_BUF_ADDR_RANGE_ENDADR_MASK)
/*! @} */

/* The count of XSPI_BUF_ADDR_RANGE */
#define XSPI_BUF_ADDR_RANGE_COUNT                (4U)

/* The count of XSPI_BUF_ADDR_RANGE */
#define XSPI_BUF_ADDR_RANGE_COUNT2               (4U)

/*! @name AHB_BUF_STATUS - AHB Buffer Status */
/*! @{ */

#define XSPI_AHB_BUF_STATUS_BUF0_0_MASK          (0x3U)
#define XSPI_AHB_BUF_STATUS_BUF0_0_SHIFT         (0U)
/*! BUF0_0 - AHB Buffer 0 Sub Buffer 0 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF0_0(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF0_0_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF0_0_MASK)

#define XSPI_AHB_BUF_STATUS_BUF0_1_MASK          (0xCU)
#define XSPI_AHB_BUF_STATUS_BUF0_1_SHIFT         (2U)
/*! BUF0_1 - AHB Buffer 0 Sub Buffer 1 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF0_1(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF0_1_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF0_1_MASK)

#define XSPI_AHB_BUF_STATUS_BUF0_2_MASK          (0x30U)
#define XSPI_AHB_BUF_STATUS_BUF0_2_SHIFT         (4U)
/*! BUF0_2 - AHB Buffer 0 Sub Buffer 2 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF0_2(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF0_2_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF0_2_MASK)

#define XSPI_AHB_BUF_STATUS_BUF0_3_MASK          (0xC0U)
#define XSPI_AHB_BUF_STATUS_BUF0_3_SHIFT         (6U)
/*! BUF0_3 - AHB Buffer 0 Sub Buffer 3 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF0_3(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF0_3_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF0_3_MASK)

#define XSPI_AHB_BUF_STATUS_BUF1_0_MASK          (0x300U)
#define XSPI_AHB_BUF_STATUS_BUF1_0_SHIFT         (8U)
/*! BUF1_0 - AHB Buffer 1 Sub Buffer 0 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF1_0(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF1_0_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF1_0_MASK)

#define XSPI_AHB_BUF_STATUS_BUF1_1_MASK          (0xC00U)
#define XSPI_AHB_BUF_STATUS_BUF1_1_SHIFT         (10U)
/*! BUF1_1 - AHB Buffer 1 Sub Buffer 1 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF1_1(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF1_1_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF1_1_MASK)

#define XSPI_AHB_BUF_STATUS_BUF1_2_MASK          (0x3000U)
#define XSPI_AHB_BUF_STATUS_BUF1_2_SHIFT         (12U)
/*! BUF1_2 - AHB Buffer 1 Sub Buffer 2 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF1_2(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF1_2_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF1_2_MASK)

#define XSPI_AHB_BUF_STATUS_BUF1_3_MASK          (0xC000U)
#define XSPI_AHB_BUF_STATUS_BUF1_3_SHIFT         (14U)
/*! BUF1_3 - AHB Buffer 1 Sub Buffer 3 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF1_3(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF1_3_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF1_3_MASK)

#define XSPI_AHB_BUF_STATUS_BUF2_0_MASK          (0x30000U)
#define XSPI_AHB_BUF_STATUS_BUF2_0_SHIFT         (16U)
/*! BUF2_0 - AHB Buffer 2 Sub Buffer 0 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF2_0(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF2_0_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF2_0_MASK)

#define XSPI_AHB_BUF_STATUS_BUF2_1_MASK          (0xC0000U)
#define XSPI_AHB_BUF_STATUS_BUF2_1_SHIFT         (18U)
/*! BUF2_1 - AHB Buffer 2 Sub Buffer 1 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF2_1(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF2_1_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF2_1_MASK)

#define XSPI_AHB_BUF_STATUS_BUF2_2_MASK          (0x300000U)
#define XSPI_AHB_BUF_STATUS_BUF2_2_SHIFT         (20U)
/*! BUF2_2 - AHB Buffer 2 Sub Buffer 2 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF2_2(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF2_2_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF2_2_MASK)

#define XSPI_AHB_BUF_STATUS_BUF2_3_MASK          (0xC00000U)
#define XSPI_AHB_BUF_STATUS_BUF2_3_SHIFT         (22U)
/*! BUF2_3 - AHB Buffer 2 Sub Buffer 3 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF2_3(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF2_3_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF2_3_MASK)

#define XSPI_AHB_BUF_STATUS_BUF3_0_MASK          (0x3000000U)
#define XSPI_AHB_BUF_STATUS_BUF3_0_SHIFT         (24U)
/*! BUF3_0 - AHB Buffer 3 Sub Buffer 0 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF3_0(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF3_0_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF3_0_MASK)

#define XSPI_AHB_BUF_STATUS_BUF3_1_MASK          (0xC000000U)
#define XSPI_AHB_BUF_STATUS_BUF3_1_SHIFT         (26U)
/*! BUF3_1 - AHB Buffer 3 Sub Buffer 1 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF3_1(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF3_1_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF3_1_MASK)

#define XSPI_AHB_BUF_STATUS_BUF3_2_MASK          (0x30000000U)
#define XSPI_AHB_BUF_STATUS_BUF3_2_SHIFT         (28U)
/*! BUF3_2 - AHB Buffer 3 Sub Buffer 2 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF3_2(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF3_2_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF3_2_MASK)

#define XSPI_AHB_BUF_STATUS_BUF3_3_MASK          (0xC0000000U)
#define XSPI_AHB_BUF_STATUS_BUF3_3_SHIFT         (30U)
/*! BUF3_3 - AHB Buffer 3 Sub Buffer 3 Status
 *  0b00..Empty
 *  0b01..Full
 *  0b10..Partially full
 *  *..
 */
#define XSPI_AHB_BUF_STATUS_BUF3_3(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_BUF_STATUS_BUF3_3_SHIFT)) & XSPI_AHB_BUF_STATUS_BUF3_3_MASK)
/*! @} */

/*! @name AHB_PERF_CTRL - AHB Buffer Hit/Miss Performance Monitor Control */
/*! @{ */

#define XSPI_AHB_PERF_CTRL_BUF0_EN_MASK          (0x1U)
#define XSPI_AHB_PERF_CTRL_BUF0_EN_SHIFT         (0U)
/*! BUF0_EN - Buffer 0 Counter Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_AHB_PERF_CTRL_BUF0_EN(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF0_EN_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF0_EN_MASK)

#define XSPI_AHB_PERF_CTRL_BUF1_EN_MASK          (0x2U)
#define XSPI_AHB_PERF_CTRL_BUF1_EN_SHIFT         (1U)
/*! BUF1_EN - Buffer 1 Counter Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_AHB_PERF_CTRL_BUF1_EN(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF1_EN_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF1_EN_MASK)

#define XSPI_AHB_PERF_CTRL_BUF2_EN_MASK          (0x4U)
#define XSPI_AHB_PERF_CTRL_BUF2_EN_SHIFT         (2U)
/*! BUF2_EN - Buffer 2 Counter Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_AHB_PERF_CTRL_BUF2_EN(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF2_EN_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF2_EN_MASK)

#define XSPI_AHB_PERF_CTRL_BUF3_EN_MASK          (0x8U)
#define XSPI_AHB_PERF_CTRL_BUF3_EN_SHIFT         (3U)
/*! BUF3_EN - Buffer 3 Counter Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_AHB_PERF_CTRL_BUF3_EN(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF3_EN_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF3_EN_MASK)

#define XSPI_AHB_PERF_CTRL_CNTSTP_MASK           (0x10U)
#define XSPI_AHB_PERF_CTRL_CNTSTP_SHIFT          (4U)
/*! CNTSTP - Performance Counter Stop
 *  0b0..No effect
 *  0b1..Stops counter
 */
#define XSPI_AHB_PERF_CTRL_CNTSTP(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_CNTSTP_SHIFT)) & XSPI_AHB_PERF_CTRL_CNTSTP_MASK)

#define XSPI_AHB_PERF_CTRL_CNTSTART_MASK         (0x20U)
#define XSPI_AHB_PERF_CTRL_CNTSTART_SHIFT        (5U)
/*! CNTSTART - Performance Counter Start
 *  0b0..No effect
 *  0b1..Starts
 */
#define XSPI_AHB_PERF_CTRL_CNTSTART(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_CNTSTART_SHIFT)) & XSPI_AHB_PERF_CTRL_CNTSTART_MASK)

#define XSPI_AHB_PERF_CTRL_BUF0_MISS_OVF_MASK    (0x1000U)
#define XSPI_AHB_PERF_CTRL_BUF0_MISS_OVF_SHIFT   (12U)
/*! BUF0_MISS_OVF - Buffer 0 Miss Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_BUF0_MISS_OVF(x)      (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF0_MISS_OVF_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF0_MISS_OVF_MASK)

#define XSPI_AHB_PERF_CTRL_BUF1_MISS_OVF_MASK    (0x2000U)
#define XSPI_AHB_PERF_CTRL_BUF1_MISS_OVF_SHIFT   (13U)
/*! BUF1_MISS_OVF - Buffer 1 Miss Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_BUF1_MISS_OVF(x)      (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF1_MISS_OVF_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF1_MISS_OVF_MASK)

#define XSPI_AHB_PERF_CTRL_BUF2_MISS_OVF_MASK    (0x4000U)
#define XSPI_AHB_PERF_CTRL_BUF2_MISS_OVF_SHIFT   (14U)
/*! BUF2_MISS_OVF - Buffer 2 Miss Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_BUF2_MISS_OVF(x)      (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF2_MISS_OVF_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF2_MISS_OVF_MASK)

#define XSPI_AHB_PERF_CTRL_BUF3_MISS_OVF_MASK    (0x8000U)
#define XSPI_AHB_PERF_CTRL_BUF3_MISS_OVF_SHIFT   (15U)
/*! BUF3_MISS_OVF - Buffer 3 Miss Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_BUF3_MISS_OVF(x)      (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF3_MISS_OVF_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF3_MISS_OVF_MASK)

#define XSPI_AHB_PERF_CTRL_BUF0_HIT_OVF_MASK     (0x10000U)
#define XSPI_AHB_PERF_CTRL_BUF0_HIT_OVF_SHIFT    (16U)
/*! BUF0_HIT_OVF - Buffer 0 Hit Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_BUF0_HIT_OVF(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF0_HIT_OVF_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF0_HIT_OVF_MASK)

#define XSPI_AHB_PERF_CTRL_BUF1_HIT_OVF_MASK     (0x20000U)
#define XSPI_AHB_PERF_CTRL_BUF1_HIT_OVF_SHIFT    (17U)
/*! BUF1_HIT_OVF - Buffer 1 Hit Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_BUF1_HIT_OVF(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF1_HIT_OVF_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF1_HIT_OVF_MASK)

#define XSPI_AHB_PERF_CTRL_BUF2_HIT_OVF_MASK     (0x40000U)
#define XSPI_AHB_PERF_CTRL_BUF2_HIT_OVF_SHIFT    (18U)
/*! BUF2_HIT_OVF - Buffer 2 Hit Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_BUF2_HIT_OVF(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF2_HIT_OVF_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF2_HIT_OVF_MASK)

#define XSPI_AHB_PERF_CTRL_BUF3_HIT_OVF_MASK     (0x80000U)
#define XSPI_AHB_PERF_CTRL_BUF3_HIT_OVF_SHIFT    (19U)
/*! BUF3_HIT_OVF - Buffer 3 Hit Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_BUF3_HIT_OVF(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_BUF3_HIT_OVF_SHIFT)) & XSPI_AHB_PERF_CTRL_BUF3_HIT_OVF_MASK)

#define XSPI_AHB_PERF_CTRL_TCNTO_MASK            (0x100000U)
#define XSPI_AHB_PERF_CTRL_TCNTO_SHIFT           (20U)
/*! TCNTO - Time Counter Overflow
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define XSPI_AHB_PERF_CTRL_TCNTO(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_TCNTO_SHIFT)) & XSPI_AHB_PERF_CTRL_TCNTO_MASK)

#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL0_MASK     (0x3000000U)
#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL0_SHIFT    (24U)
/*! SUB_BUF_SEL0 - Sub-buffer Selection for Buffer 0 Performance Monitoring
 *  0b00..0
 *  0b01..1
 *  0b10..2
 *  0b11..3
 */
#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL0(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_SUB_BUF_SEL0_SHIFT)) & XSPI_AHB_PERF_CTRL_SUB_BUF_SEL0_MASK)

#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL1_MASK     (0xC000000U)
#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL1_SHIFT    (26U)
/*! SUB_BUF_SEL1 - Sub-buffer Selection for Buffer 1 Performance Monitoring
 *  0b00..0
 *  0b01..1
 *  0b10..2
 *  0b11..3
 */
#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL1(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_SUB_BUF_SEL1_SHIFT)) & XSPI_AHB_PERF_CTRL_SUB_BUF_SEL1_MASK)

#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL2_MASK     (0x30000000U)
#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL2_SHIFT    (28U)
/*! SUB_BUF_SEL2 - Sub-buffer Selection for Buffer 2 Performance Monitoring
 *  0b00..0
 *  0b01..1
 *  0b10..2
 *  0b11..3
 */
#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL2(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_SUB_BUF_SEL2_SHIFT)) & XSPI_AHB_PERF_CTRL_SUB_BUF_SEL2_MASK)

#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL3_MASK     (0xC0000000U)
#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL3_SHIFT    (30U)
/*! SUB_BUF_SEL3 - Sub-buffer Selection for Buffer 3 Performance Monitoring
 *  0b00..0
 *  0b01..1
 *  0b10..2
 *  0b11..3
 */
#define XSPI_AHB_PERF_CTRL_SUB_BUF_SEL3(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_CTRL_SUB_BUF_SEL3_SHIFT)) & XSPI_AHB_PERF_CTRL_SUB_BUF_SEL3_MASK)
/*! @} */

/*! @name AHB_PERF_TIME_CNT - AHB Performance Monitor Time Counter */
/*! @{ */

#define XSPI_AHB_PERF_TIME_CNT_PERF_TIME_COUNT_MASK (0xFFFFFFFFU)
#define XSPI_AHB_PERF_TIME_CNT_PERF_TIME_COUNT_SHIFT (0U)
/*! PERF_TIME_COUNT - Time Count */
#define XSPI_AHB_PERF_TIME_CNT_PERF_TIME_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_TIME_CNT_PERF_TIME_COUNT_SHIFT)) & XSPI_AHB_PERF_TIME_CNT_PERF_TIME_COUNT_MASK)
/*! @} */

/*! @name AHB_PERF_BUF - AHB Buffer 0 Performance Monitor..AHB Buffer 3 Performance Monitor */
/*! @{ */

#define XSPI_AHB_PERF_BUF_PERF_MISS_CNT_MASK     (0xFFFFU)
#define XSPI_AHB_PERF_BUF_PERF_MISS_CNT_SHIFT    (0U)
/*! PERF_MISS_CNT - Performance Miss Count */
#define XSPI_AHB_PERF_BUF_PERF_MISS_CNT(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_BUF_PERF_MISS_CNT_SHIFT)) & XSPI_AHB_PERF_BUF_PERF_MISS_CNT_MASK)

#define XSPI_AHB_PERF_BUF_PERF_HIT_CNT_MASK      (0xFFFF0000U)
#define XSPI_AHB_PERF_BUF_PERF_HIT_CNT_SHIFT     (16U)
/*! PERF_HIT_CNT - Performance Hit Count */
#define XSPI_AHB_PERF_BUF_PERF_HIT_CNT(x)        (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_PERF_BUF_PERF_HIT_CNT_SHIFT)) & XSPI_AHB_PERF_BUF_PERF_HIT_CNT_MASK)
/*! @} */

/* The count of XSPI_AHB_PERF_BUF */
#define XSPI_AHB_PERF_BUF_COUNT                  (4U)

/*! @name AHRDYTO - AHB HREADY Timeout */
/*! @{ */

#define XSPI_AHRDYTO_HREADY_TO_MASK              (0xFFFFU)
#define XSPI_AHRDYTO_HREADY_TO_SHIFT             (0U)
/*! HREADY_TO - AHB HREADY Low Timeout Counter Value */
#define XSPI_AHRDYTO_HREADY_TO(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_AHRDYTO_HREADY_TO_SHIFT)) & XSPI_AHRDYTO_HREADY_TO_MASK)
/*! @} */

/*! @name AHB_ERR_PAYLOAD_HI - AHB Error Payload High */
/*! @{ */

#define XSPI_AHB_ERR_PAYLOAD_HI_ERR_PAYLOAD_H_MASK (0xFFFFFFFFU)
#define XSPI_AHB_ERR_PAYLOAD_HI_ERR_PAYLOAD_H_SHIFT (0U)
/*! ERR_PAYLOAD_H - Error Payload High */
#define XSPI_AHB_ERR_PAYLOAD_HI_ERR_PAYLOAD_H(x) (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_ERR_PAYLOAD_HI_ERR_PAYLOAD_H_SHIFT)) & XSPI_AHB_ERR_PAYLOAD_HI_ERR_PAYLOAD_H_MASK)
/*! @} */

/*! @name AHB_ERR_PAYLOAD_LO - AHB Error Payload Low */
/*! @{ */

#define XSPI_AHB_ERR_PAYLOAD_LO_ERR_PAYLOAD_L_MASK (0xFFFFFFFFU)
#define XSPI_AHB_ERR_PAYLOAD_LO_ERR_PAYLOAD_L_SHIFT (0U)
/*! ERR_PAYLOAD_L - Error Payload Low */
#define XSPI_AHB_ERR_PAYLOAD_LO_ERR_PAYLOAD_L(x) (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_ERR_PAYLOAD_LO_ERR_PAYLOAD_L_SHIFT)) & XSPI_AHB_ERR_PAYLOAD_LO_ERR_PAYLOAD_L_MASK)
/*! @} */

/*! @name AHB_RD_ERR_ADDR - AHB Read Error Address */
/*! @{ */

#define XSPI_AHB_RD_ERR_ADDR_READDR_MASK         (0xFFFFFFFFU)
#define XSPI_AHB_RD_ERR_ADDR_READDR_SHIFT        (0U)
/*! READDR - Read Error Address */
#define XSPI_AHB_RD_ERR_ADDR_READDR(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_RD_ERR_ADDR_READDR_SHIFT)) & XSPI_AHB_RD_ERR_ADDR_READDR_MASK)
/*! @} */

/*! @name AHB_RD_ERR_MID - AHB Read Error Manager ID */
/*! @{ */

#define XSPI_AHB_RD_ERR_MID_REMID_MASK           (0x1FU)
#define XSPI_AHB_RD_ERR_MID_REMID_SHIFT          (0U)
/*! REMID - Read Error Manager ID */
#define XSPI_AHB_RD_ERR_MID_REMID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_RD_ERR_MID_REMID_SHIFT)) & XSPI_AHB_RD_ERR_MID_REMID_MASK)
/*! @} */

/*! @name SPNDST_ADDR - Suspend Transaction Address */
/*! @{ */

#define XSPI_SPNDST_ADDR_ASAHBR_MASK             (0xFFFFFFF8U)
#define XSPI_SPNDST_ADDR_ASAHBR_SHIFT            (3U)
/*! ASAHBR - Address of Suspended AHB Read Transaction */
#define XSPI_SPNDST_ADDR_ASAHBR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_SPNDST_ADDR_ASAHBR_SHIFT)) & XSPI_SPNDST_ADDR_ASAHBR_MASK)
/*! @} */

/*! @name PPWF_TCNT - Page Program Wait Time Counter */
/*! @{ */

#define XSPI_PPWF_TCNT_PPWTC_MASK                (0xFFFFFFFFU)
#define XSPI_PPWF_TCNT_PPWTC_SHIFT               (0U)
/*! PPWTC - Page Program Wait Time Counter Value */
#define XSPI_PPWF_TCNT_PPWTC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_PPWF_TCNT_PPWTC_SHIFT)) & XSPI_PPWF_TCNT_PPWTC_MASK)
/*! @} */

/*! @name PPW_RDSR - Page Program Wait Read Status */
/*! @{ */

#define XSPI_PPW_RDSR_RDSR_MASK                  (0xFFFFU)
#define XSPI_PPW_RDSR_RDSR_SHIFT                 (0U)
/*! RDSR - Value of Flash Status Register Read */
#define XSPI_PPW_RDSR_RDSR(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_PPW_RDSR_RDSR_SHIFT)) & XSPI_PPW_RDSR_RDSR_MASK)

#define XSPI_PPW_RDSR_RDSR_VAL_CHK_MASK          (0x400000U)
#define XSPI_PPW_RDSR_RDSR_VAL_CHK_SHIFT         (22U)
/*! RDSR_VAL_CHK - RDSR Value Check
 *  0b0..Check for 0
 *  0b1..Check for 1
 */
#define XSPI_PPW_RDSR_RDSR_VAL_CHK(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_PPW_RDSR_RDSR_VAL_CHK_SHIFT)) & XSPI_PPW_RDSR_RDSR_VAL_CHK_MASK)

#define XSPI_PPW_RDSR_RDSR_HWORD_SEL_MASK        (0x800000U)
#define XSPI_PPW_RDSR_RDSR_HWORD_SEL_SHIFT       (23U)
/*! RDSR_HWORD_SEL - RDSR Half Word Select
 *  0b0..RDSR contains 16 least significant bits (15:0) of RDSR read from flash.
 *  0b1..RDSR contains 16 most significant bits (31:16) of RDSR read from flash.
 */
#define XSPI_PPW_RDSR_RDSR_HWORD_SEL(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_PPW_RDSR_RDSR_HWORD_SEL_SHIFT)) & XSPI_PPW_RDSR_RDSR_HWORD_SEL_MASK)

#define XSPI_PPW_RDSR_LOC_MASK                   (0xF000000U)
#define XSPI_PPW_RDSR_LOC_SHIFT                  (24U)
/*! LOC - Location of RDSR */
#define XSPI_PPW_RDSR_LOC(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_PPW_RDSR_LOC_SHIFT)) & XSPI_PPW_RDSR_LOC_MASK)

#define XSPI_PPW_RDSR_VALID_MASK                 (0x80000000U)
#define XSPI_PPW_RDSR_VALID_SHIFT                (31U)
/*! VALID - Valid
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_PPW_RDSR_VALID(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_PPW_RDSR_VALID_SHIFT)) & XSPI_PPW_RDSR_VALID_MASK)
/*! @} */

/*! @name IPEDCTXIV - IPED Context Initial Vector */
/*! @{ */

#define XSPI_IPEDCTXIV_CTX_IV_MASK               (0xFFFFFFFFU)
#define XSPI_IPEDCTXIV_CTX_IV_SHIFT              (0U)
/*! CTX_IV - 32 bits of IV for the context region */
#define XSPI_IPEDCTXIV_CTX_IV(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXIV_CTX_IV_SHIFT)) & XSPI_IPEDCTXIV_CTX_IV_MASK)
/*! @} */

/* The count of XSPI_IPEDCTXIV */
#define XSPI_IPEDCTXIV_COUNT                     (16U)

/* The count of XSPI_IPEDCTXIV */
#define XSPI_IPEDCTXIV_COUNT2                    (2U)

/*! @name IPEDCTXSTART - IPED Start Address Region */
/*! @{ */

#define XSPI_IPEDCTXSTART_GCM_MASK               (0x1U)
#define XSPI_IPEDCTXSTART_GCM_SHIFT              (0U)
/*! GCM - GCM Mode Region
 *  0b0..CTR
 *  0b1..GCM
 */
#define XSPI_IPEDCTXSTART_GCM(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXSTART_GCM_SHIFT)) & XSPI_IPEDCTXSTART_GCM_MASK)

#define XSPI_IPEDCTXSTART_SADD_MASK              (0xFFFFFF00U)
#define XSPI_IPEDCTXSTART_SADD_SHIFT             (8U)
/*! SADD - Start Address */
#define XSPI_IPEDCTXSTART_SADD(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXSTART_SADD_SHIFT)) & XSPI_IPEDCTXSTART_SADD_MASK)
/*! @} */

/* The count of XSPI_IPEDCTXSTART */
#define XSPI_IPEDCTXSTART_COUNT                  (16U)

/*! @name IPEDCTXEND - IPED End Address Region */
/*! @{ */

#define XSPI_IPEDCTXEND_END_ADDRESS_MASK         (0xFFFFFF00U)
#define XSPI_IPEDCTXEND_END_ADDRESS_SHIFT        (8U)
/*! END_ADDRESS - End Address */
#define XSPI_IPEDCTXEND_END_ADDRESS(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXEND_END_ADDRESS_SHIFT)) & XSPI_IPEDCTXEND_END_ADDRESS_MASK)
/*! @} */

/* The count of XSPI_IPEDCTXEND */
#define XSPI_IPEDCTXEND_COUNT                    (16U)

/*! @name IPEDCTXAAD - IPED Context Additional Authentication Data */
/*! @{ */

#define XSPI_IPEDCTXAAD_CTX_AAD_MASK             (0xFFFFFFFFU)
#define XSPI_IPEDCTXAAD_CTX_AAD_SHIFT            (0U)
/*! CTX_AAD - 32 bits of AAD for the region */
#define XSPI_IPEDCTXAAD_CTX_AAD(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXAAD_CTX_AAD_SHIFT)) & XSPI_IPEDCTXAAD_CTX_AAD_MASK)
/*! @} */

/* The count of XSPI_IPEDCTXAAD */
#define XSPI_IPEDCTXAAD_COUNT                    (16U)

/* The count of XSPI_IPEDCTXAAD */
#define XSPI_IPEDCTXAAD_COUNT2                   (2U)

/*! @name IPEDCTRL - IPED Function Control */
/*! @{ */

#define XSPI_IPEDCTRL_CONFIG_MASK                (0x1U)
#define XSPI_IPEDCTRL_CONFIG_SHIFT               (0U)
/*! CONFIG - IPED CTR/GCM Interface Configure
 *  0b0..Prince 12 rounds
 *  0b1..Prince 22 rounds
 */
#define XSPI_IPEDCTRL_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_CONFIG_SHIFT)) & XSPI_IPEDCTRL_CONFIG_MASK)

#define XSPI_IPEDCTRL_IPED_EN_MASK               (0x2U)
#define XSPI_IPEDCTRL_IPED_EN_SHIFT              (1U)
/*! IPED_EN - IPED CTR-GCM Interface Enable
 *  0b0..Bypasses IPED logic and allows writing of unencrypted or undecrypted data
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_IPED_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_IPED_EN_SHIFT)) & XSPI_IPEDCTRL_IPED_EN_MASK)

#define XSPI_IPEDCTRL_IPWR_EN_MASK               (0x4U)
#define XSPI_IPEDCTRL_IPWR_EN_SHIFT              (2U)
/*! IPWR_EN - IP Write IPED XEX or CTR Mode Enable
 *  0b0..Bypasses IPS-based data and writes unencrypted data
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_IPWR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_IPWR_EN_SHIFT)) & XSPI_IPEDCTRL_IPWR_EN_MASK)

#define XSPI_IPEDCTRL_AHBWR_EN_MASK              (0x8U)
#define XSPI_IPEDCTRL_AHBWR_EN_SHIFT             (3U)
/*! AHBWR_EN - AHB Write IPED XEX or CTR Mode Encryption Enable
 *  0b0..Bypasses AHB-based data and writes unencrypted
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_AHBWR_EN(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_AHBWR_EN_SHIFT)) & XSPI_IPEDCTRL_AHBWR_EN_MASK)

#define XSPI_IPEDCTRL_AHBRD_EN_MASK              (0x10U)
#define XSPI_IPEDCTRL_AHBRD_EN_SHIFT             (4U)
/*! AHBRD_EN - AHB Read IPED XEX or CTR Mode Decryption Enable
 *  0b0..Bypasses AHB-based data and reads unencrypted
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_AHBRD_EN(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_AHBRD_EN_SHIFT)) & XSPI_IPEDCTRL_AHBRD_EN_MASK)

#define XSPI_IPEDCTRL_IPGCMWR_MASK               (0x40U)
#define XSPI_IPEDCTRL_IPGCMWR_SHIFT              (6U)
/*! IPGCMWR - IP Write GCM Enable
 *  0b0..Bypasses IPS-based data and writes unencrypted data
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_IPGCMWR(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_IPGCMWR_SHIFT)) & XSPI_IPEDCTRL_IPGCMWR_MASK)

#define XSPI_IPEDCTRL_AHGCMWR_MASK               (0x80U)
#define XSPI_IPEDCTRL_AHGCMWR_SHIFT              (7U)
/*! AHGCMWR - AHB Write IPED GCM Encryption Enable
 *  0b0..Bypasses AHB data and writes unencrypted data
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_AHGCMWR(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_AHGCMWR_SHIFT)) & XSPI_IPEDCTRL_AHGCMWR_MASK)

#define XSPI_IPEDCTRL_AHBGCMRD_MASK              (0x100U)
#define XSPI_IPEDCTRL_AHBGCMRD_SHIFT             (8U)
/*! AHBGCMRD - AHB Read IPED GCM Decryption Enable
 *  0b0..Bypasses AHB data and reads unencrypted data
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_AHBGCMRD(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_AHBGCMRD_SHIFT)) & XSPI_IPEDCTRL_AHBGCMRD_MASK)

#define XSPI_IPEDCTRL_IPED_PROTECT_MASK          (0x200U)
#define XSPI_IPEDCTRL_IPED_PROTECT_SHIFT         (9U)
/*! IPED_PROTECT - IPED Protection
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_IPED_PROTECT(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_IPED_PROTECT_SHIFT)) & XSPI_IPEDCTRL_IPED_PROTECT_MASK)

#define XSPI_IPEDCTRL_IPED_SWRESET_MASK          (0x400U)
#define XSPI_IPEDCTRL_IPED_SWRESET_SHIFT         (10U)
/*! IPED_SWRESET - IPED CTR/GCM and XEX Interface Software Reset
 *  0b0..No reset
 *  0b1..Resets
 */
#define XSPI_IPEDCTRL_IPED_SWRESET(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_IPED_SWRESET_SHIFT)) & XSPI_IPEDCTRL_IPED_SWRESET_MASK)

#define XSPI_IPEDCTRL_IPED_XEX_EN_MASK           (0x800U)
#define XSPI_IPEDCTRL_IPED_XEX_EN_SHIFT          (11U)
/*! IPED_XEX_EN - IPED XEX Interface Enable
 *  0b0..Bypasses IPED logic and writes unencrypted or undecrypted data
 *  0b1..Enables
 */
#define XSPI_IPEDCTRL_IPED_XEX_EN(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_IPED_XEX_EN_SHIFT)) & XSPI_IPEDCTRL_IPED_XEX_EN_MASK)

#define XSPI_IPEDCTRL_IPS_GCM_MASK               (0x10000U)
#define XSPI_IPEDCTRL_IPS_GCM_SHIFT              (16U)
/*! IPS_GCM - IPS Transaction Region Status
 *  0b0..Non-GCM region, either CTR or bypass
 *  0b1..GCM region
 */
#define XSPI_IPEDCTRL_IPS_GCM(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTRL_IPS_GCM_SHIFT)) & XSPI_IPEDCTRL_IPS_GCM_MASK)
/*! @} */

/*! @name IPEDCTXCTRL - IPED Context Control 0..IPED Context Control 1 */
/*! @{ */

#define XSPI_IPEDCTXCTRL_CTX0_FREEZE_MASK        (0x3U)
#define XSPI_IPEDCTXCTRL_CTX0_FREEZE_SHIFT       (0U)
/*! CTX0_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX0_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX0_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX0_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX1_FREEZE_MASK        (0xCU)
#define XSPI_IPEDCTXCTRL_CTX1_FREEZE_SHIFT       (2U)
/*! CTX1_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX1_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX1_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX1_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX2_FREEZE_MASK        (0x30U)
#define XSPI_IPEDCTXCTRL_CTX2_FREEZE_SHIFT       (4U)
/*! CTX2_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX2_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX2_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX2_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX3_FREEZE_MASK        (0xC0U)
#define XSPI_IPEDCTXCTRL_CTX3_FREEZE_SHIFT       (6U)
/*! CTX3_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX3_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX3_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX3_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX4_FREEZE_MASK        (0x300U)
#define XSPI_IPEDCTXCTRL_CTX4_FREEZE_SHIFT       (8U)
/*! CTX4_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX4_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX4_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX4_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX5_FREEZE_MASK        (0xC00U)
#define XSPI_IPEDCTXCTRL_CTX5_FREEZE_SHIFT       (10U)
/*! CTX5_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX5_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX5_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX5_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX6_FREEZE_MASK        (0x3000U)
#define XSPI_IPEDCTXCTRL_CTX6_FREEZE_SHIFT       (12U)
/*! CTX6_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX6_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX6_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX6_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX7_FREEZE_MASK        (0xC000U)
#define XSPI_IPEDCTXCTRL_CTX7_FREEZE_SHIFT       (14U)
/*! CTX7_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX7_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX7_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX7_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX8_FREEZE_MASK        (0x30000U)
#define XSPI_IPEDCTXCTRL_CTX8_FREEZE_SHIFT       (16U)
/*! CTX8_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX8_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX8_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX8_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX9_FREEZE_MASK        (0xC0000U)
#define XSPI_IPEDCTXCTRL_CTX9_FREEZE_SHIFT       (18U)
/*! CTX9_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX9_FREEZE(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX9_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX9_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX10_FREEZE_MASK       (0x300000U)
#define XSPI_IPEDCTXCTRL_CTX10_FREEZE_SHIFT      (20U)
/*! CTX10_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX10_FREEZE(x)         (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX10_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX10_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX11_FREEZE_MASK       (0xC00000U)
#define XSPI_IPEDCTXCTRL_CTX11_FREEZE_SHIFT      (22U)
/*! CTX11_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX11_FREEZE(x)         (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX11_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX11_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX12_FREEZE_MASK       (0x3000000U)
#define XSPI_IPEDCTXCTRL_CTX12_FREEZE_SHIFT      (24U)
/*! CTX12_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX12_FREEZE(x)         (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX12_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX12_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX13_FREEZE_MASK       (0xC000000U)
#define XSPI_IPEDCTXCTRL_CTX13_FREEZE_SHIFT      (26U)
/*! CTX13_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX13_FREEZE(x)         (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX13_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX13_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX14_FREEZE_MASK       (0x30000000U)
#define XSPI_IPEDCTXCTRL_CTX14_FREEZE_SHIFT      (28U)
/*! CTX14_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX14_FREEZE(x)         (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX14_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX14_FREEZE_MASK)

#define XSPI_IPEDCTXCTRL_CTX15_FREEZE_MASK       (0xC0000000U)
#define XSPI_IPEDCTXCTRL_CTX15_FREEZE_SHIFT      (30U)
/*! CTX15_FREEZE - CTX Freeze */
#define XSPI_IPEDCTXCTRL_CTX15_FREEZE(x)         (((uint32_t)(((uint32_t)(x)) << XSPI_IPEDCTXCTRL_CTX15_FREEZE_SHIFT)) & XSPI_IPEDCTXCTRL_CTX15_FREEZE_MASK)
/*! @} */

/* The count of XSPI_IPEDCTXCTRL */
#define XSPI_IPEDCTXCTRL_COUNT                   (2U)

/*! @name FRAD0_WORD0 - Flash Region Word 0 - Start Address */
/*! @{ */

#define XSPI_FRAD0_WORD0_STARTADR_MASK           (0xFFFF0000U)
#define XSPI_FRAD0_WORD0_STARTADR_SHIFT          (16U)
/*! STARTADR - Start Address */
#define XSPI_FRAD0_WORD0_STARTADR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD0_STARTADR_SHIFT)) & XSPI_FRAD0_WORD0_STARTADR_MASK)
/*! @} */

/*! @name FRAD0_WORD1 - Flash Region Word 1 - End Address */
/*! @{ */

#define XSPI_FRAD0_WORD1_ENDADR_MASK             (0xFFFF0000U)
#define XSPI_FRAD0_WORD1_ENDADR_SHIFT            (16U)
/*! ENDADR - End Address */
#define XSPI_FRAD0_WORD1_ENDADR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD1_ENDADR_SHIFT)) & XSPI_FRAD0_WORD1_ENDADR_MASK)
/*! @} */

/*! @name FRAD0_WORD2 - Flash Region Word 2 - Privileges */
/*! @{ */

#define XSPI_FRAD0_WORD2_MD0ACP_MASK             (0x7U)
#define XSPI_FRAD0_WORD2_MD0ACP_SHIFT            (0U)
/*! MD0ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD0_WORD2_MD0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD0_WORD2_MD0ACP_MASK)

#define XSPI_FRAD0_WORD2_MD1ACP_MASK             (0x38U)
#define XSPI_FRAD0_WORD2_MD1ACP_SHIFT            (3U)
/*! MD1ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD0_WORD2_MD1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD0_WORD2_MD1ACP_MASK)

#define XSPI_FRAD0_WORD2_EALO_MASK               (0x3F000000U)
#define XSPI_FRAD0_WORD2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XSPI_FRAD0_WORD2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD2_EALO_SHIFT)) & XSPI_FRAD0_WORD2_EALO_MASK)
/*! @} */

/*! @name FRAD0_WORD3 - Flash Region Word 3 - Lock Control */
/*! @{ */

#define XSPI_FRAD0_WORD3_EAL_MASK                (0x3000000U)
#define XSPI_FRAD0_WORD3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..No lock
 *  0b01..No action
 *  0b10..Enables lock
 *  0b11..Enables exclusive access lock
 */
#define XSPI_FRAD0_WORD3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD3_EAL_SHIFT)) & XSPI_FRAD0_WORD3_EAL_MASK)

#define XSPI_FRAD0_WORD3_LOCK_MASK               (0x60000000U)
#define XSPI_FRAD0_WORD3_LOCK_SHIFT              (29U)
/*! LOCK - Descriptor Lock
 *  0b00..Unlocks
 *  0b01..Locks until hard reset
 *  0b10..Locks except for manager
 *  0b11..Locks
 */
#define XSPI_FRAD0_WORD3_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD3_LOCK_SHIFT)) & XSPI_FRAD0_WORD3_LOCK_MASK)

#define XSPI_FRAD0_WORD3_VLD_MASK                (0x80000000U)
#define XSPI_FRAD0_WORD3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Invalid
 *  0b1..Valid
 */
#define XSPI_FRAD0_WORD3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD3_VLD_SHIFT)) & XSPI_FRAD0_WORD3_VLD_MASK)
/*! @} */

/*! @name FRAD0_WORD4 - Flash Region Word 4 - Compare Address Status */
/*! @{ */

#define XSPI_FRAD0_WORD4_CMP_ADDR_MASK           (0xFFFFFFFFU)
#define XSPI_FRAD0_WORD4_CMP_ADDR_SHIFT          (0U)
/*! CMP_ADDR - Capture Address */
#define XSPI_FRAD0_WORD4_CMP_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD4_CMP_ADDR_SHIFT)) & XSPI_FRAD0_WORD4_CMP_ADDR_MASK)
/*! @} */

/*! @name FRAD0_WORD5 - Flash Region Word 5 - Compare Status Data */
/*! @{ */

#define XSPI_FRAD0_WORD5_CMP_MDID_MASK           (0x3FU)
#define XSPI_FRAD0_WORD5_CMP_MDID_SHIFT          (0U)
/*! CMP_MDID - Captured Manager Value */
#define XSPI_FRAD0_WORD5_CMP_MDID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD0_WORD5_CMP_MDID_MASK)

#define XSPI_FRAD0_WORD5_CMP_SA_MASK             (0x40U)
#define XSPI_FRAD0_WORD5_CMP_SA_SHIFT            (6U)
/*! CMP_SA - Captured Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FRAD0_WORD5_CMP_SA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD5_CMP_SA_SHIFT)) & XSPI_FRAD0_WORD5_CMP_SA_MASK)

#define XSPI_FRAD0_WORD5_CMP_PA_MASK             (0x80U)
#define XSPI_FRAD0_WORD5_CMP_PA_SHIFT            (7U)
/*! CMP_PA - Captured Privilege Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_FRAD0_WORD5_CMP_PA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD5_CMP_PA_SHIFT)) & XSPI_FRAD0_WORD5_CMP_PA_MASK)

#define XSPI_FRAD0_WORD5_CMP_ERR_MASK            (0x20000000U)
#define XSPI_FRAD0_WORD5_CMP_ERR_SHIFT           (29U)
/*! CMP_ERR - Comparison Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FRAD0_WORD5_CMP_ERR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD5_CMP_ERR_SHIFT)) & XSPI_FRAD0_WORD5_CMP_ERR_MASK)

#define XSPI_FRAD0_WORD5_CMPVALID_MASK           (0x40000000U)
#define XSPI_FRAD0_WORD5_CMPVALID_SHIFT          (30U)
/*! CMPVALID - Comparison Valid
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_FRAD0_WORD5_CMPVALID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD5_CMPVALID_SHIFT)) & XSPI_FRAD0_WORD5_CMPVALID_MASK)
/*! @} */

/*! @name FRAD1_WORD0 - Flash Region Word 0 - Start Address */
/*! @{ */

#define XSPI_FRAD1_WORD0_STARTADR_MASK           (0xFFFF0000U)
#define XSPI_FRAD1_WORD0_STARTADR_SHIFT          (16U)
/*! STARTADR - Start Address */
#define XSPI_FRAD1_WORD0_STARTADR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD0_STARTADR_SHIFT)) & XSPI_FRAD1_WORD0_STARTADR_MASK)
/*! @} */

/*! @name FRAD1_WORD1 - Flash Region Word 1 - End Address */
/*! @{ */

#define XSPI_FRAD1_WORD1_ENDADR_MASK             (0xFFFF0000U)
#define XSPI_FRAD1_WORD1_ENDADR_SHIFT            (16U)
/*! ENDADR - End Address */
#define XSPI_FRAD1_WORD1_ENDADR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD1_ENDADR_SHIFT)) & XSPI_FRAD1_WORD1_ENDADR_MASK)
/*! @} */

/*! @name FRAD1_WORD2 - Flash Region Word 2 - Privileges */
/*! @{ */

#define XSPI_FRAD1_WORD2_MD0ACP_MASK             (0x7U)
#define XSPI_FRAD1_WORD2_MD0ACP_SHIFT            (0U)
/*! MD0ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD1_WORD2_MD0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD1_WORD2_MD0ACP_MASK)

#define XSPI_FRAD1_WORD2_MD1ACP_MASK             (0x38U)
#define XSPI_FRAD1_WORD2_MD1ACP_SHIFT            (3U)
/*! MD1ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD1_WORD2_MD1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD1_WORD2_MD1ACP_MASK)

#define XSPI_FRAD1_WORD2_EALO_MASK               (0x3F000000U)
#define XSPI_FRAD1_WORD2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XSPI_FRAD1_WORD2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD2_EALO_SHIFT)) & XSPI_FRAD1_WORD2_EALO_MASK)
/*! @} */

/*! @name FRAD1_WORD3 - Flash Region Word 3 - Lock Control */
/*! @{ */

#define XSPI_FRAD1_WORD3_EAL_MASK                (0x3000000U)
#define XSPI_FRAD1_WORD3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..No lock
 *  0b01..No action
 *  0b10..Enables lock
 *  0b11..Enables exclusive access lock
 */
#define XSPI_FRAD1_WORD3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD3_EAL_SHIFT)) & XSPI_FRAD1_WORD3_EAL_MASK)

#define XSPI_FRAD1_WORD3_LOCK_MASK               (0x60000000U)
#define XSPI_FRAD1_WORD3_LOCK_SHIFT              (29U)
/*! LOCK - Descriptor Lock
 *  0b00..Unlocks
 *  0b01..Locks until hard reset
 *  0b10..Locks except for manager
 *  0b11..Locks
 */
#define XSPI_FRAD1_WORD3_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD3_LOCK_SHIFT)) & XSPI_FRAD1_WORD3_LOCK_MASK)

#define XSPI_FRAD1_WORD3_VLD_MASK                (0x80000000U)
#define XSPI_FRAD1_WORD3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Invalid
 *  0b1..Valid
 */
#define XSPI_FRAD1_WORD3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD3_VLD_SHIFT)) & XSPI_FRAD1_WORD3_VLD_MASK)
/*! @} */

/*! @name FRAD1_WORD4 - Flash Region Word 4 - Compare Address Status */
/*! @{ */

#define XSPI_FRAD1_WORD4_CMP_ADDR_MASK           (0xFFFFFFFFU)
#define XSPI_FRAD1_WORD4_CMP_ADDR_SHIFT          (0U)
/*! CMP_ADDR - Capture Address */
#define XSPI_FRAD1_WORD4_CMP_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD4_CMP_ADDR_SHIFT)) & XSPI_FRAD1_WORD4_CMP_ADDR_MASK)
/*! @} */

/*! @name FRAD1_WORD5 - Flash Region Word 5 - Compare Status Data */
/*! @{ */

#define XSPI_FRAD1_WORD5_CMP_MDID_MASK           (0x3FU)
#define XSPI_FRAD1_WORD5_CMP_MDID_SHIFT          (0U)
/*! CMP_MDID - Captured Manager Value */
#define XSPI_FRAD1_WORD5_CMP_MDID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD1_WORD5_CMP_MDID_MASK)

#define XSPI_FRAD1_WORD5_CMP_SA_MASK             (0x40U)
#define XSPI_FRAD1_WORD5_CMP_SA_SHIFT            (6U)
/*! CMP_SA - Captured Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FRAD1_WORD5_CMP_SA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD5_CMP_SA_SHIFT)) & XSPI_FRAD1_WORD5_CMP_SA_MASK)

#define XSPI_FRAD1_WORD5_CMP_PA_MASK             (0x80U)
#define XSPI_FRAD1_WORD5_CMP_PA_SHIFT            (7U)
/*! CMP_PA - Captured Privilege Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_FRAD1_WORD5_CMP_PA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD5_CMP_PA_SHIFT)) & XSPI_FRAD1_WORD5_CMP_PA_MASK)

#define XSPI_FRAD1_WORD5_CMP_ERR_MASK            (0x20000000U)
#define XSPI_FRAD1_WORD5_CMP_ERR_SHIFT           (29U)
/*! CMP_ERR - Comparison Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FRAD1_WORD5_CMP_ERR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD5_CMP_ERR_SHIFT)) & XSPI_FRAD1_WORD5_CMP_ERR_MASK)

#define XSPI_FRAD1_WORD5_CMPVALID_MASK           (0x40000000U)
#define XSPI_FRAD1_WORD5_CMPVALID_SHIFT          (30U)
/*! CMPVALID - Comparison Valid
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_FRAD1_WORD5_CMPVALID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD5_CMPVALID_SHIFT)) & XSPI_FRAD1_WORD5_CMPVALID_MASK)
/*! @} */

/*! @name FRAD2_WORD0 - Flash Region Word 0 - Start Address */
/*! @{ */

#define XSPI_FRAD2_WORD0_STARTADR_MASK           (0xFFFF0000U)
#define XSPI_FRAD2_WORD0_STARTADR_SHIFT          (16U)
/*! STARTADR - Start Address */
#define XSPI_FRAD2_WORD0_STARTADR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD0_STARTADR_SHIFT)) & XSPI_FRAD2_WORD0_STARTADR_MASK)
/*! @} */

/*! @name FRAD2_WORD1 - Flash Region Word 1 - End Address */
/*! @{ */

#define XSPI_FRAD2_WORD1_ENDADR_MASK             (0xFFFF0000U)
#define XSPI_FRAD2_WORD1_ENDADR_SHIFT            (16U)
/*! ENDADR - End Address */
#define XSPI_FRAD2_WORD1_ENDADR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD1_ENDADR_SHIFT)) & XSPI_FRAD2_WORD1_ENDADR_MASK)
/*! @} */

/*! @name FRAD2_WORD2 - Flash Region Word 2 - Privileges */
/*! @{ */

#define XSPI_FRAD2_WORD2_MD0ACP_MASK             (0x7U)
#define XSPI_FRAD2_WORD2_MD0ACP_SHIFT            (0U)
/*! MD0ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD2_WORD2_MD0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD2_WORD2_MD0ACP_MASK)

#define XSPI_FRAD2_WORD2_MD1ACP_MASK             (0x38U)
#define XSPI_FRAD2_WORD2_MD1ACP_SHIFT            (3U)
/*! MD1ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD2_WORD2_MD1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD2_WORD2_MD1ACP_MASK)

#define XSPI_FRAD2_WORD2_EALO_MASK               (0x3F000000U)
#define XSPI_FRAD2_WORD2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XSPI_FRAD2_WORD2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD2_EALO_SHIFT)) & XSPI_FRAD2_WORD2_EALO_MASK)
/*! @} */

/*! @name FRAD2_WORD3 - Flash Region Word 3 - Lock Control */
/*! @{ */

#define XSPI_FRAD2_WORD3_EAL_MASK                (0x3000000U)
#define XSPI_FRAD2_WORD3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..No lock
 *  0b01..No action
 *  0b10..Enables lock
 *  0b11..Enables exclusive access lock
 */
#define XSPI_FRAD2_WORD3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD3_EAL_SHIFT)) & XSPI_FRAD2_WORD3_EAL_MASK)

#define XSPI_FRAD2_WORD3_LOCK_MASK               (0x60000000U)
#define XSPI_FRAD2_WORD3_LOCK_SHIFT              (29U)
/*! LOCK - Descriptor Lock
 *  0b00..Unlocks
 *  0b01..Locks until hard reset
 *  0b10..Locks except for manager
 *  0b11..Locks
 */
#define XSPI_FRAD2_WORD3_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD3_LOCK_SHIFT)) & XSPI_FRAD2_WORD3_LOCK_MASK)

#define XSPI_FRAD2_WORD3_VLD_MASK                (0x80000000U)
#define XSPI_FRAD2_WORD3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Invalid
 *  0b1..Valid
 */
#define XSPI_FRAD2_WORD3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD3_VLD_SHIFT)) & XSPI_FRAD2_WORD3_VLD_MASK)
/*! @} */

/*! @name FRAD2_WORD4 - Flash Region Word 4 - Compare Address Status */
/*! @{ */

#define XSPI_FRAD2_WORD4_CMP_ADDR_MASK           (0xFFFFFFFFU)
#define XSPI_FRAD2_WORD4_CMP_ADDR_SHIFT          (0U)
/*! CMP_ADDR - Capture Address */
#define XSPI_FRAD2_WORD4_CMP_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD4_CMP_ADDR_SHIFT)) & XSPI_FRAD2_WORD4_CMP_ADDR_MASK)
/*! @} */

/*! @name FRAD2_WORD5 - Flash Region Word 5 - Compare Status Data */
/*! @{ */

#define XSPI_FRAD2_WORD5_CMP_MDID_MASK           (0x3FU)
#define XSPI_FRAD2_WORD5_CMP_MDID_SHIFT          (0U)
/*! CMP_MDID - Captured Manager Value */
#define XSPI_FRAD2_WORD5_CMP_MDID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD2_WORD5_CMP_MDID_MASK)

#define XSPI_FRAD2_WORD5_CMP_SA_MASK             (0x40U)
#define XSPI_FRAD2_WORD5_CMP_SA_SHIFT            (6U)
/*! CMP_SA - Captured Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FRAD2_WORD5_CMP_SA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD5_CMP_SA_SHIFT)) & XSPI_FRAD2_WORD5_CMP_SA_MASK)

#define XSPI_FRAD2_WORD5_CMP_PA_MASK             (0x80U)
#define XSPI_FRAD2_WORD5_CMP_PA_SHIFT            (7U)
/*! CMP_PA - Captured Privilege Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_FRAD2_WORD5_CMP_PA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD5_CMP_PA_SHIFT)) & XSPI_FRAD2_WORD5_CMP_PA_MASK)

#define XSPI_FRAD2_WORD5_CMP_ERR_MASK            (0x20000000U)
#define XSPI_FRAD2_WORD5_CMP_ERR_SHIFT           (29U)
/*! CMP_ERR - Comparison Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FRAD2_WORD5_CMP_ERR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD5_CMP_ERR_SHIFT)) & XSPI_FRAD2_WORD5_CMP_ERR_MASK)

#define XSPI_FRAD2_WORD5_CMPVALID_MASK           (0x40000000U)
#define XSPI_FRAD2_WORD5_CMPVALID_SHIFT          (30U)
/*! CMPVALID - Comparison Valid
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_FRAD2_WORD5_CMPVALID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD5_CMPVALID_SHIFT)) & XSPI_FRAD2_WORD5_CMPVALID_MASK)
/*! @} */

/*! @name FRAD3_WORD0 - Flash Region Word 0 - Start Address */
/*! @{ */

#define XSPI_FRAD3_WORD0_STARTADR_MASK           (0xFFFF0000U)
#define XSPI_FRAD3_WORD0_STARTADR_SHIFT          (16U)
/*! STARTADR - Start Address */
#define XSPI_FRAD3_WORD0_STARTADR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD0_STARTADR_SHIFT)) & XSPI_FRAD3_WORD0_STARTADR_MASK)
/*! @} */

/*! @name FRAD3_WORD1 - Flash Region Word 1 - End Address */
/*! @{ */

#define XSPI_FRAD3_WORD1_ENDADR_MASK             (0xFFFF0000U)
#define XSPI_FRAD3_WORD1_ENDADR_SHIFT            (16U)
/*! ENDADR - End Address */
#define XSPI_FRAD3_WORD1_ENDADR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD1_ENDADR_SHIFT)) & XSPI_FRAD3_WORD1_ENDADR_MASK)
/*! @} */

/*! @name FRAD3_WORD2 - Flash Region Word 2 - Privileges */
/*! @{ */

#define XSPI_FRAD3_WORD2_MD0ACP_MASK             (0x7U)
#define XSPI_FRAD3_WORD2_MD0ACP_SHIFT            (0U)
/*! MD0ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD3_WORD2_MD0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD3_WORD2_MD0ACP_MASK)

#define XSPI_FRAD3_WORD2_MD1ACP_MASK             (0x38U)
#define XSPI_FRAD3_WORD2_MD1ACP_SHIFT            (3U)
/*! MD1ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD3_WORD2_MD1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD3_WORD2_MD1ACP_MASK)

#define XSPI_FRAD3_WORD2_EALO_MASK               (0x3F000000U)
#define XSPI_FRAD3_WORD2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XSPI_FRAD3_WORD2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD2_EALO_SHIFT)) & XSPI_FRAD3_WORD2_EALO_MASK)
/*! @} */

/*! @name FRAD3_WORD3 - Flash Region Word 3 - Lock Control */
/*! @{ */

#define XSPI_FRAD3_WORD3_EAL_MASK                (0x3000000U)
#define XSPI_FRAD3_WORD3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..No lock
 *  0b01..No action
 *  0b10..Enables lock
 *  0b11..Enables exclusive access lock
 */
#define XSPI_FRAD3_WORD3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD3_EAL_SHIFT)) & XSPI_FRAD3_WORD3_EAL_MASK)

#define XSPI_FRAD3_WORD3_LOCK_MASK               (0x60000000U)
#define XSPI_FRAD3_WORD3_LOCK_SHIFT              (29U)
/*! LOCK - Descriptor Lock
 *  0b00..Unlocks
 *  0b01..Locks until hard reset
 *  0b10..Locks except for manager
 *  0b11..Locks
 */
#define XSPI_FRAD3_WORD3_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD3_LOCK_SHIFT)) & XSPI_FRAD3_WORD3_LOCK_MASK)

#define XSPI_FRAD3_WORD3_VLD_MASK                (0x80000000U)
#define XSPI_FRAD3_WORD3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Invalid
 *  0b1..Valid
 */
#define XSPI_FRAD3_WORD3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD3_VLD_SHIFT)) & XSPI_FRAD3_WORD3_VLD_MASK)
/*! @} */

/*! @name FRAD3_WORD4 - Flash Region Word 4 - Compare Address Status */
/*! @{ */

#define XSPI_FRAD3_WORD4_CMP_ADDR_MASK           (0xFFFFFFFFU)
#define XSPI_FRAD3_WORD4_CMP_ADDR_SHIFT          (0U)
/*! CMP_ADDR - Capture Address */
#define XSPI_FRAD3_WORD4_CMP_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD4_CMP_ADDR_SHIFT)) & XSPI_FRAD3_WORD4_CMP_ADDR_MASK)
/*! @} */

/*! @name FRAD3_WORD5 - Flash Region Word 5 - Compare Status Data */
/*! @{ */

#define XSPI_FRAD3_WORD5_CMP_MDID_MASK           (0x3FU)
#define XSPI_FRAD3_WORD5_CMP_MDID_SHIFT          (0U)
/*! CMP_MDID - Captured Manager Value */
#define XSPI_FRAD3_WORD5_CMP_MDID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD3_WORD5_CMP_MDID_MASK)

#define XSPI_FRAD3_WORD5_CMP_SA_MASK             (0x40U)
#define XSPI_FRAD3_WORD5_CMP_SA_SHIFT            (6U)
/*! CMP_SA - Captured Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FRAD3_WORD5_CMP_SA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD5_CMP_SA_SHIFT)) & XSPI_FRAD3_WORD5_CMP_SA_MASK)

#define XSPI_FRAD3_WORD5_CMP_PA_MASK             (0x80U)
#define XSPI_FRAD3_WORD5_CMP_PA_SHIFT            (7U)
/*! CMP_PA - Captured Privilege Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_FRAD3_WORD5_CMP_PA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD5_CMP_PA_SHIFT)) & XSPI_FRAD3_WORD5_CMP_PA_MASK)

#define XSPI_FRAD3_WORD5_CMP_ERR_MASK            (0x20000000U)
#define XSPI_FRAD3_WORD5_CMP_ERR_SHIFT           (29U)
/*! CMP_ERR - Comparison Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FRAD3_WORD5_CMP_ERR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD5_CMP_ERR_SHIFT)) & XSPI_FRAD3_WORD5_CMP_ERR_MASK)

#define XSPI_FRAD3_WORD5_CMPVALID_MASK           (0x40000000U)
#define XSPI_FRAD3_WORD5_CMPVALID_SHIFT          (30U)
/*! CMPVALID - Comparison Valid
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_FRAD3_WORD5_CMPVALID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD5_CMPVALID_SHIFT)) & XSPI_FRAD3_WORD5_CMPVALID_MASK)
/*! @} */

/*! @name FRAD4_WORD0 - Flash Region Word 0 - Start Address */
/*! @{ */

#define XSPI_FRAD4_WORD0_STARTADR_MASK           (0xFFFF0000U)
#define XSPI_FRAD4_WORD0_STARTADR_SHIFT          (16U)
/*! STARTADR - Start Address */
#define XSPI_FRAD4_WORD0_STARTADR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD0_STARTADR_SHIFT)) & XSPI_FRAD4_WORD0_STARTADR_MASK)
/*! @} */

/*! @name FRAD4_WORD1 - Flash Region Word 1 - End Address */
/*! @{ */

#define XSPI_FRAD4_WORD1_ENDADR_MASK             (0xFFFF0000U)
#define XSPI_FRAD4_WORD1_ENDADR_SHIFT            (16U)
/*! ENDADR - End Address */
#define XSPI_FRAD4_WORD1_ENDADR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD1_ENDADR_SHIFT)) & XSPI_FRAD4_WORD1_ENDADR_MASK)
/*! @} */

/*! @name FRAD4_WORD2 - Flash Region Word 2 - Privileges */
/*! @{ */

#define XSPI_FRAD4_WORD2_MD0ACP_MASK             (0x7U)
#define XSPI_FRAD4_WORD2_MD0ACP_SHIFT            (0U)
/*! MD0ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD4_WORD2_MD0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD4_WORD2_MD0ACP_MASK)

#define XSPI_FRAD4_WORD2_MD1ACP_MASK             (0x38U)
#define XSPI_FRAD4_WORD2_MD1ACP_SHIFT            (3U)
/*! MD1ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD4_WORD2_MD1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD4_WORD2_MD1ACP_MASK)

#define XSPI_FRAD4_WORD2_EALO_MASK               (0x3F000000U)
#define XSPI_FRAD4_WORD2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XSPI_FRAD4_WORD2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD2_EALO_SHIFT)) & XSPI_FRAD4_WORD2_EALO_MASK)
/*! @} */

/*! @name FRAD4_WORD3 - Flash Region Word 3 - Lock Control */
/*! @{ */

#define XSPI_FRAD4_WORD3_EAL_MASK                (0x3000000U)
#define XSPI_FRAD4_WORD3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..No lock
 *  0b01..No action
 *  0b10..Enables lock
 *  0b11..Enables exclusive access lock
 */
#define XSPI_FRAD4_WORD3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD3_EAL_SHIFT)) & XSPI_FRAD4_WORD3_EAL_MASK)

#define XSPI_FRAD4_WORD3_LOCK_MASK               (0x60000000U)
#define XSPI_FRAD4_WORD3_LOCK_SHIFT              (29U)
/*! LOCK - Descriptor Lock
 *  0b00..Unlocks
 *  0b01..Locks until hard reset
 *  0b10..Locks except for manager
 *  0b11..Locks
 */
#define XSPI_FRAD4_WORD3_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD3_LOCK_SHIFT)) & XSPI_FRAD4_WORD3_LOCK_MASK)

#define XSPI_FRAD4_WORD3_VLD_MASK                (0x80000000U)
#define XSPI_FRAD4_WORD3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Invalid
 *  0b1..Valid
 */
#define XSPI_FRAD4_WORD3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD3_VLD_SHIFT)) & XSPI_FRAD4_WORD3_VLD_MASK)
/*! @} */

/*! @name FRAD4_WORD4 - Flash Region Word 4 - Compare Address Status */
/*! @{ */

#define XSPI_FRAD4_WORD4_CMP_ADDR_MASK           (0xFFFFFFFFU)
#define XSPI_FRAD4_WORD4_CMP_ADDR_SHIFT          (0U)
/*! CMP_ADDR - Capture Address */
#define XSPI_FRAD4_WORD4_CMP_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD4_CMP_ADDR_SHIFT)) & XSPI_FRAD4_WORD4_CMP_ADDR_MASK)
/*! @} */

/*! @name FRAD4_WORD5 - Flash Region Word 5 - Compare Status Data */
/*! @{ */

#define XSPI_FRAD4_WORD5_CMP_MDID_MASK           (0x3FU)
#define XSPI_FRAD4_WORD5_CMP_MDID_SHIFT          (0U)
/*! CMP_MDID - Captured Manager Value */
#define XSPI_FRAD4_WORD5_CMP_MDID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD4_WORD5_CMP_MDID_MASK)

#define XSPI_FRAD4_WORD5_CMP_SA_MASK             (0x40U)
#define XSPI_FRAD4_WORD5_CMP_SA_SHIFT            (6U)
/*! CMP_SA - Captured Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FRAD4_WORD5_CMP_SA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD5_CMP_SA_SHIFT)) & XSPI_FRAD4_WORD5_CMP_SA_MASK)

#define XSPI_FRAD4_WORD5_CMP_PA_MASK             (0x80U)
#define XSPI_FRAD4_WORD5_CMP_PA_SHIFT            (7U)
/*! CMP_PA - Captured Privilege Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_FRAD4_WORD5_CMP_PA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD5_CMP_PA_SHIFT)) & XSPI_FRAD4_WORD5_CMP_PA_MASK)

#define XSPI_FRAD4_WORD5_CMP_ERR_MASK            (0x20000000U)
#define XSPI_FRAD4_WORD5_CMP_ERR_SHIFT           (29U)
/*! CMP_ERR - Comparison Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FRAD4_WORD5_CMP_ERR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD5_CMP_ERR_SHIFT)) & XSPI_FRAD4_WORD5_CMP_ERR_MASK)

#define XSPI_FRAD4_WORD5_CMPVALID_MASK           (0x40000000U)
#define XSPI_FRAD4_WORD5_CMPVALID_SHIFT          (30U)
/*! CMPVALID - Comparison Valid
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_FRAD4_WORD5_CMPVALID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD5_CMPVALID_SHIFT)) & XSPI_FRAD4_WORD5_CMPVALID_MASK)
/*! @} */

/*! @name FRAD5_WORD0 - Flash Region Word 0 - Start Address */
/*! @{ */

#define XSPI_FRAD5_WORD0_STARTADR_MASK           (0xFFFF0000U)
#define XSPI_FRAD5_WORD0_STARTADR_SHIFT          (16U)
/*! STARTADR - Start Address */
#define XSPI_FRAD5_WORD0_STARTADR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD0_STARTADR_SHIFT)) & XSPI_FRAD5_WORD0_STARTADR_MASK)
/*! @} */

/*! @name FRAD5_WORD1 - Flash Region Word 1 - End Address */
/*! @{ */

#define XSPI_FRAD5_WORD1_ENDADR_MASK             (0xFFFF0000U)
#define XSPI_FRAD5_WORD1_ENDADR_SHIFT            (16U)
/*! ENDADR - End Address */
#define XSPI_FRAD5_WORD1_ENDADR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD1_ENDADR_SHIFT)) & XSPI_FRAD5_WORD1_ENDADR_MASK)
/*! @} */

/*! @name FRAD5_WORD2 - Flash Region Word 2 - Privileges */
/*! @{ */

#define XSPI_FRAD5_WORD2_MD0ACP_MASK             (0x7U)
#define XSPI_FRAD5_WORD2_MD0ACP_SHIFT            (0U)
/*! MD0ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD5_WORD2_MD0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD5_WORD2_MD0ACP_MASK)

#define XSPI_FRAD5_WORD2_MD1ACP_MASK             (0x38U)
#define XSPI_FRAD5_WORD2_MD1ACP_SHIFT            (3U)
/*! MD1ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD5_WORD2_MD1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD5_WORD2_MD1ACP_MASK)

#define XSPI_FRAD5_WORD2_EALO_MASK               (0x3F000000U)
#define XSPI_FRAD5_WORD2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XSPI_FRAD5_WORD2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD2_EALO_SHIFT)) & XSPI_FRAD5_WORD2_EALO_MASK)
/*! @} */

/*! @name FRAD5_WORD3 - Flash Region Word 3 - Lock Control */
/*! @{ */

#define XSPI_FRAD5_WORD3_EAL_MASK                (0x3000000U)
#define XSPI_FRAD5_WORD3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..No lock
 *  0b01..No action
 *  0b10..Enables lock
 *  0b11..Enables exclusive access lock
 */
#define XSPI_FRAD5_WORD3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD3_EAL_SHIFT)) & XSPI_FRAD5_WORD3_EAL_MASK)

#define XSPI_FRAD5_WORD3_LOCK_MASK               (0x60000000U)
#define XSPI_FRAD5_WORD3_LOCK_SHIFT              (29U)
/*! LOCK - Descriptor Lock
 *  0b00..Unlocks
 *  0b01..Locks until hard reset
 *  0b10..Locks except for manager
 *  0b11..Locks
 */
#define XSPI_FRAD5_WORD3_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD3_LOCK_SHIFT)) & XSPI_FRAD5_WORD3_LOCK_MASK)

#define XSPI_FRAD5_WORD3_VLD_MASK                (0x80000000U)
#define XSPI_FRAD5_WORD3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Invalid
 *  0b1..Valid
 */
#define XSPI_FRAD5_WORD3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD3_VLD_SHIFT)) & XSPI_FRAD5_WORD3_VLD_MASK)
/*! @} */

/*! @name FRAD5_WORD4 - Flash Region Word 4 - Compare Address Status */
/*! @{ */

#define XSPI_FRAD5_WORD4_CMP_ADDR_MASK           (0xFFFFFFFFU)
#define XSPI_FRAD5_WORD4_CMP_ADDR_SHIFT          (0U)
/*! CMP_ADDR - Capture Address */
#define XSPI_FRAD5_WORD4_CMP_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD4_CMP_ADDR_SHIFT)) & XSPI_FRAD5_WORD4_CMP_ADDR_MASK)
/*! @} */

/*! @name FRAD5_WORD5 - Flash Region Word 5 - Compare Status Data */
/*! @{ */

#define XSPI_FRAD5_WORD5_CMP_MDID_MASK           (0x3FU)
#define XSPI_FRAD5_WORD5_CMP_MDID_SHIFT          (0U)
/*! CMP_MDID - Captured Manager Value */
#define XSPI_FRAD5_WORD5_CMP_MDID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD5_WORD5_CMP_MDID_MASK)

#define XSPI_FRAD5_WORD5_CMP_SA_MASK             (0x40U)
#define XSPI_FRAD5_WORD5_CMP_SA_SHIFT            (6U)
/*! CMP_SA - Captured Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FRAD5_WORD5_CMP_SA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD5_CMP_SA_SHIFT)) & XSPI_FRAD5_WORD5_CMP_SA_MASK)

#define XSPI_FRAD5_WORD5_CMP_PA_MASK             (0x80U)
#define XSPI_FRAD5_WORD5_CMP_PA_SHIFT            (7U)
/*! CMP_PA - Captured Privilege Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_FRAD5_WORD5_CMP_PA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD5_CMP_PA_SHIFT)) & XSPI_FRAD5_WORD5_CMP_PA_MASK)

#define XSPI_FRAD5_WORD5_CMP_ERR_MASK            (0x20000000U)
#define XSPI_FRAD5_WORD5_CMP_ERR_SHIFT           (29U)
/*! CMP_ERR - Comparison Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FRAD5_WORD5_CMP_ERR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD5_CMP_ERR_SHIFT)) & XSPI_FRAD5_WORD5_CMP_ERR_MASK)

#define XSPI_FRAD5_WORD5_CMPVALID_MASK           (0x40000000U)
#define XSPI_FRAD5_WORD5_CMPVALID_SHIFT          (30U)
/*! CMPVALID - Comparison Valid
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_FRAD5_WORD5_CMPVALID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD5_CMPVALID_SHIFT)) & XSPI_FRAD5_WORD5_CMPVALID_MASK)
/*! @} */

/*! @name FRAD6_WORD0 - Flash Region Word 0 - Start Address */
/*! @{ */

#define XSPI_FRAD6_WORD0_STARTADR_MASK           (0xFFFF0000U)
#define XSPI_FRAD6_WORD0_STARTADR_SHIFT          (16U)
/*! STARTADR - Start Address */
#define XSPI_FRAD6_WORD0_STARTADR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD0_STARTADR_SHIFT)) & XSPI_FRAD6_WORD0_STARTADR_MASK)
/*! @} */

/*! @name FRAD6_WORD1 - Flash Region Word 1 - End Address */
/*! @{ */

#define XSPI_FRAD6_WORD1_ENDADR_MASK             (0xFFFF0000U)
#define XSPI_FRAD6_WORD1_ENDADR_SHIFT            (16U)
/*! ENDADR - End Address */
#define XSPI_FRAD6_WORD1_ENDADR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD1_ENDADR_SHIFT)) & XSPI_FRAD6_WORD1_ENDADR_MASK)
/*! @} */

/*! @name FRAD6_WORD2 - Flash Region Word 2 - Privileges */
/*! @{ */

#define XSPI_FRAD6_WORD2_MD0ACP_MASK             (0x7U)
#define XSPI_FRAD6_WORD2_MD0ACP_SHIFT            (0U)
/*! MD0ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD6_WORD2_MD0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD6_WORD2_MD0ACP_MASK)

#define XSPI_FRAD6_WORD2_MD1ACP_MASK             (0x38U)
#define XSPI_FRAD6_WORD2_MD1ACP_SHIFT            (3U)
/*! MD1ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD6_WORD2_MD1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD6_WORD2_MD1ACP_MASK)

#define XSPI_FRAD6_WORD2_EALO_MASK               (0x3F000000U)
#define XSPI_FRAD6_WORD2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XSPI_FRAD6_WORD2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD2_EALO_SHIFT)) & XSPI_FRAD6_WORD2_EALO_MASK)
/*! @} */

/*! @name FRAD6_WORD3 - Flash Region Word 3 - Lock Control */
/*! @{ */

#define XSPI_FRAD6_WORD3_EAL_MASK                (0x3000000U)
#define XSPI_FRAD6_WORD3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..No lock
 *  0b01..No action
 *  0b10..Enables lock
 *  0b11..Enables exclusive access lock
 */
#define XSPI_FRAD6_WORD3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD3_EAL_SHIFT)) & XSPI_FRAD6_WORD3_EAL_MASK)

#define XSPI_FRAD6_WORD3_LOCK_MASK               (0x60000000U)
#define XSPI_FRAD6_WORD3_LOCK_SHIFT              (29U)
/*! LOCK - Descriptor Lock
 *  0b00..Unlocks
 *  0b01..Locks until hard reset
 *  0b10..Locks except for manager
 *  0b11..Locks
 */
#define XSPI_FRAD6_WORD3_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD3_LOCK_SHIFT)) & XSPI_FRAD6_WORD3_LOCK_MASK)

#define XSPI_FRAD6_WORD3_VLD_MASK                (0x80000000U)
#define XSPI_FRAD6_WORD3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Invalid
 *  0b1..Valid
 */
#define XSPI_FRAD6_WORD3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD3_VLD_SHIFT)) & XSPI_FRAD6_WORD3_VLD_MASK)
/*! @} */

/*! @name FRAD6_WORD4 - Flash Region Word 4 - Compare Address Status */
/*! @{ */

#define XSPI_FRAD6_WORD4_CMP_ADDR_MASK           (0xFFFFFFFFU)
#define XSPI_FRAD6_WORD4_CMP_ADDR_SHIFT          (0U)
/*! CMP_ADDR - Capture Address */
#define XSPI_FRAD6_WORD4_CMP_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD4_CMP_ADDR_SHIFT)) & XSPI_FRAD6_WORD4_CMP_ADDR_MASK)
/*! @} */

/*! @name FRAD6_WORD5 - Flash Region Word 5 - Compare Status Data */
/*! @{ */

#define XSPI_FRAD6_WORD5_CMP_MDID_MASK           (0x3FU)
#define XSPI_FRAD6_WORD5_CMP_MDID_SHIFT          (0U)
/*! CMP_MDID - Captured Manager Value */
#define XSPI_FRAD6_WORD5_CMP_MDID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD6_WORD5_CMP_MDID_MASK)

#define XSPI_FRAD6_WORD5_CMP_SA_MASK             (0x40U)
#define XSPI_FRAD6_WORD5_CMP_SA_SHIFT            (6U)
/*! CMP_SA - Captured Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FRAD6_WORD5_CMP_SA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD5_CMP_SA_SHIFT)) & XSPI_FRAD6_WORD5_CMP_SA_MASK)

#define XSPI_FRAD6_WORD5_CMP_PA_MASK             (0x80U)
#define XSPI_FRAD6_WORD5_CMP_PA_SHIFT            (7U)
/*! CMP_PA - Captured Privilege Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_FRAD6_WORD5_CMP_PA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD5_CMP_PA_SHIFT)) & XSPI_FRAD6_WORD5_CMP_PA_MASK)

#define XSPI_FRAD6_WORD5_CMP_ERR_MASK            (0x20000000U)
#define XSPI_FRAD6_WORD5_CMP_ERR_SHIFT           (29U)
/*! CMP_ERR - Comparison Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FRAD6_WORD5_CMP_ERR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD5_CMP_ERR_SHIFT)) & XSPI_FRAD6_WORD5_CMP_ERR_MASK)

#define XSPI_FRAD6_WORD5_CMPVALID_MASK           (0x40000000U)
#define XSPI_FRAD6_WORD5_CMPVALID_SHIFT          (30U)
/*! CMPVALID - Comparison Valid
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_FRAD6_WORD5_CMPVALID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD5_CMPVALID_SHIFT)) & XSPI_FRAD6_WORD5_CMPVALID_MASK)
/*! @} */

/*! @name FRAD7_WORD0 - Flash Region Word 0 - Start Address */
/*! @{ */

#define XSPI_FRAD7_WORD0_STARTADR_MASK           (0xFFFF0000U)
#define XSPI_FRAD7_WORD0_STARTADR_SHIFT          (16U)
/*! STARTADR - Start Address */
#define XSPI_FRAD7_WORD0_STARTADR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD0_STARTADR_SHIFT)) & XSPI_FRAD7_WORD0_STARTADR_MASK)
/*! @} */

/*! @name FRAD7_WORD1 - Flash Region Word 1 - End Address */
/*! @{ */

#define XSPI_FRAD7_WORD1_ENDADR_MASK             (0xFFFF0000U)
#define XSPI_FRAD7_WORD1_ENDADR_SHIFT            (16U)
/*! ENDADR - End Address */
#define XSPI_FRAD7_WORD1_ENDADR(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD1_ENDADR_SHIFT)) & XSPI_FRAD7_WORD1_ENDADR_MASK)
/*! @} */

/*! @name FRAD7_WORD2 - Flash Region Word 2 - Privileges */
/*! @{ */

#define XSPI_FRAD7_WORD2_MD0ACP_MASK             (0x7U)
#define XSPI_FRAD7_WORD2_MD0ACP_SHIFT            (0U)
/*! MD0ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD7_WORD2_MD0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD7_WORD2_MD0ACP_MASK)

#define XSPI_FRAD7_WORD2_MD1ACP_MASK             (0x38U)
#define XSPI_FRAD7_WORD2_MD1ACP_SHIFT            (3U)
/*! MD1ACP - Manager Domain Access Control Policy */
#define XSPI_FRAD7_WORD2_MD1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD7_WORD2_MD1ACP_MASK)

#define XSPI_FRAD7_WORD2_EALO_MASK               (0x3F000000U)
#define XSPI_FRAD7_WORD2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XSPI_FRAD7_WORD2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD2_EALO_SHIFT)) & XSPI_FRAD7_WORD2_EALO_MASK)
/*! @} */

/*! @name FRAD7_WORD3 - Flash Region Word 3 - Lock Control */
/*! @{ */

#define XSPI_FRAD7_WORD3_EAL_MASK                (0x3000000U)
#define XSPI_FRAD7_WORD3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..No lock
 *  0b01..No action
 *  0b10..Enables lock
 *  0b11..Enables exclusive access lock
 */
#define XSPI_FRAD7_WORD3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD3_EAL_SHIFT)) & XSPI_FRAD7_WORD3_EAL_MASK)

#define XSPI_FRAD7_WORD3_LOCK_MASK               (0x60000000U)
#define XSPI_FRAD7_WORD3_LOCK_SHIFT              (29U)
/*! LOCK - Descriptor Lock
 *  0b00..Unlocks
 *  0b01..Locks until hard reset
 *  0b10..Locks except for manager
 *  0b11..Locks
 */
#define XSPI_FRAD7_WORD3_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD3_LOCK_SHIFT)) & XSPI_FRAD7_WORD3_LOCK_MASK)

#define XSPI_FRAD7_WORD3_VLD_MASK                (0x80000000U)
#define XSPI_FRAD7_WORD3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Invalid
 *  0b1..Valid
 */
#define XSPI_FRAD7_WORD3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD3_VLD_SHIFT)) & XSPI_FRAD7_WORD3_VLD_MASK)
/*! @} */

/*! @name FRAD7_WORD4 - Flash Region Word 4 - Compare Address Status */
/*! @{ */

#define XSPI_FRAD7_WORD4_CMP_ADDR_MASK           (0xFFFFFFFFU)
#define XSPI_FRAD7_WORD4_CMP_ADDR_SHIFT          (0U)
/*! CMP_ADDR - Capture Address */
#define XSPI_FRAD7_WORD4_CMP_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD4_CMP_ADDR_SHIFT)) & XSPI_FRAD7_WORD4_CMP_ADDR_MASK)
/*! @} */

/*! @name FRAD7_WORD5 - Flash Region Word 5 - Compare Status Data */
/*! @{ */

#define XSPI_FRAD7_WORD5_CMP_MDID_MASK           (0x3FU)
#define XSPI_FRAD7_WORD5_CMP_MDID_SHIFT          (0U)
/*! CMP_MDID - Captured Manager Value */
#define XSPI_FRAD7_WORD5_CMP_MDID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD7_WORD5_CMP_MDID_MASK)

#define XSPI_FRAD7_WORD5_CMP_SA_MASK             (0x40U)
#define XSPI_FRAD7_WORD5_CMP_SA_SHIFT            (6U)
/*! CMP_SA - Captured Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FRAD7_WORD5_CMP_SA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD5_CMP_SA_SHIFT)) & XSPI_FRAD7_WORD5_CMP_SA_MASK)

#define XSPI_FRAD7_WORD5_CMP_PA_MASK             (0x80U)
#define XSPI_FRAD7_WORD5_CMP_PA_SHIFT            (7U)
/*! CMP_PA - Captured Privilege Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_FRAD7_WORD5_CMP_PA(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD5_CMP_PA_SHIFT)) & XSPI_FRAD7_WORD5_CMP_PA_MASK)

#define XSPI_FRAD7_WORD5_CMP_ERR_MASK            (0x20000000U)
#define XSPI_FRAD7_WORD5_CMP_ERR_SHIFT           (29U)
/*! CMP_ERR - Comparison Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FRAD7_WORD5_CMP_ERR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD5_CMP_ERR_SHIFT)) & XSPI_FRAD7_WORD5_CMP_ERR_MASK)

#define XSPI_FRAD7_WORD5_CMPVALID_MASK           (0x40000000U)
#define XSPI_FRAD7_WORD5_CMPVALID_SHIFT          (30U)
/*! CMPVALID - Comparison Valid
 *  0b0..Not available
 *  0b1..Available
 */
#define XSPI_FRAD7_WORD5_CMPVALID(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD5_CMPVALID_SHIFT)) & XSPI_FRAD7_WORD5_CMPVALID_MASK)
/*! @} */

/*! @name SFP_ARB_TIMEOUT - SFP Arbitration Lock Timeout Counter */
/*! @{ */

#define XSPI_SFP_ARB_TIMEOUT_SFP_ARB_TOC_MASK    (0xFFFFFFFFU)
#define XSPI_SFP_ARB_TIMEOUT_SFP_ARB_TOC_SHIFT   (0U)
/*! SFP_ARB_TOC - SFP Arbitration Timeout Value */
#define XSPI_SFP_ARB_TIMEOUT_SFP_ARB_TOC(x)      (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_ARB_TIMEOUT_SFP_ARB_TOC_SHIFT)) & XSPI_SFP_ARB_TIMEOUT_SFP_ARB_TOC_MASK)
/*! @} */

/*! @name TG0MDAD - Target Group Manager Domain Access Descriptor */
/*! @{ */

#define XSPI_TG0MDAD_MIDMATCH_MASK               (0x3FU)
#define XSPI_TG0MDAD_MIDMATCH_SHIFT              (0U)
/*! MIDMATCH - Manager ID Reference */
#define XSPI_TG0MDAD_MIDMATCH(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_TG0MDAD_MIDMATCH_SHIFT)) & XSPI_TG0MDAD_MIDMATCH_MASK)

#define XSPI_TG0MDAD_MASK_MASK                   (0xFC0U)
#define XSPI_TG0MDAD_MASK_SHIFT                  (6U)
/*! MASK - Mask */
#define XSPI_TG0MDAD_MASK(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_TG0MDAD_MASK_SHIFT)) & XSPI_TG0MDAD_MASK_MASK)

#define XSPI_TG0MDAD_MASKTYPE_MASK               (0x1000U)
#define XSPI_TG0MDAD_MASKTYPE_SHIFT              (12U)
/*! MASKTYPE - Mask Type
 *  0b0..AND
 *  0b1..OR
 */
#define XSPI_TG0MDAD_MASKTYPE(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_TG0MDAD_MASKTYPE_SHIFT)) & XSPI_TG0MDAD_MASKTYPE_MASK)

#define XSPI_TG0MDAD_SA_MASK                     (0xC000U)
#define XSPI_TG0MDAD_SA_SHIFT                    (14U)
/*! SA - Secure Attribute
 *  0b00..
 *  0b01..Non-secure only
 *  0b10..Secure only
 *  0b11..Both secure and non-secure
 */
#define XSPI_TG0MDAD_SA(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_TG0MDAD_SA_SHIFT)) & XSPI_TG0MDAD_SA_MASK)

#define XSPI_TG0MDAD_LCK_MASK                    (0x20000000U)
#define XSPI_TG0MDAD_LCK_SHIFT                   (29U)
/*! LCK - Descriptor Lock
 *  0b0..No action
 *  0b1..Locks
 */
#define XSPI_TG0MDAD_LCK(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TG0MDAD_LCK_SHIFT)) & XSPI_TG0MDAD_LCK_MASK)

#define XSPI_TG0MDAD_VLD_MASK                    (0x80000000U)
#define XSPI_TG0MDAD_VLD_SHIFT                   (31U)
/*! VLD - Valid
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_TG0MDAD_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TG0MDAD_VLD_SHIFT)) & XSPI_TG0MDAD_VLD_MASK)
/*! @} */

/*! @name TGSFAR - Target Group SFAR Address */
/*! @{ */

#define XSPI_TGSFAR_SFARADDR_MASK                (0xFFFFFFFFU)
#define XSPI_TGSFAR_SFARADDR_SHIFT               (0U)
/*! SFARADDR - SFAR Address */
#define XSPI_TGSFAR_SFARADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFAR_SFARADDR_SHIFT)) & XSPI_TGSFAR_SFARADDR_MASK)
/*! @} */

/*! @name TGSFARS - Target Group SFAR Status */
/*! @{ */

#define XSPI_TGSFARS_TG_MID_MASK                 (0x3FU)
#define XSPI_TGSFARS_TG_MID_SHIFT                (0U)
/*! TG_MID - Transaction Manager ID */
#define XSPI_TGSFARS_TG_MID(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_TG_MID_SHIFT)) & XSPI_TGSFARS_TG_MID_MASK)

#define XSPI_TGSFARS_SA_MASK                     (0x400U)
#define XSPI_TGSFARS_SA_SHIFT                    (10U)
/*! SA - Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_TGSFARS_SA(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_SA_SHIFT)) & XSPI_TGSFARS_SA_MASK)

#define XSPI_TGSFARS_PA_MASK                     (0x1000U)
#define XSPI_TGSFARS_PA_SHIFT                    (12U)
/*! PA - Privileged Attribute
 *  0b0..Not privileged
 *  0b1..Privileged
 */
#define XSPI_TGSFARS_PA(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_PA_SHIFT)) & XSPI_TGSFARS_PA_MASK)

#define XSPI_TGSFARS_CLR_MASK                    (0x20000000U)
#define XSPI_TGSFARS_CLR_SHIFT                   (29U)
/*! CLR - Clear
 *  0b0..Conveys no useful information
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_TGSFARS_CLR(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_CLR_SHIFT)) & XSPI_TGSFARS_CLR_MASK)

#define XSPI_TGSFARS_ERR_MASK                    (0x40000000U)
#define XSPI_TGSFARS_ERR_SHIFT                   (30U)
/*! ERR - Error
 *  0b0..With required attributes
 *  0b1..Without required attributes
 */
#define XSPI_TGSFARS_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_ERR_SHIFT)) & XSPI_TGSFARS_ERR_MASK)

#define XSPI_TGSFARS_VLD_MASK                    (0x80000000U)
#define XSPI_TGSFARS_VLD_SHIFT                   (31U)
/*! VLD - Valid
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_TGSFARS_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_VLD_SHIFT)) & XSPI_TGSFARS_VLD_MASK)
/*! @} */

/*! @name TGIPCRS - Target Group IP Configuration Status */
/*! @{ */

#define XSPI_TGIPCRS_IDATSZ_MASK                 (0xFFFFU)
#define XSPI_TGIPCRS_IDATSZ_SHIFT                (0U)
/*! IDATSZ - IP Data Transfer Size */
#define XSPI_TGIPCRS_IDATSZ(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_IDATSZ_SHIFT)) & XSPI_TGIPCRS_IDATSZ_MASK)

#define XSPI_TGIPCRS_SEQID_MASK                  (0xF0000U)
#define XSPI_TGIPCRS_SEQID_SHIFT                 (16U)
/*! SEQID - SEQID Value */
#define XSPI_TGIPCRS_SEQID(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_SEQID_SHIFT)) & XSPI_TGIPCRS_SEQID_MASK)

#define XSPI_TGIPCRS_ARB_LOCK_MASK               (0x200000U)
#define XSPI_TGIPCRS_ARB_LOCK_SHIFT              (21U)
/*! ARB_LOCK - Arbitration Lock
 *  0b0..Not requested
 *  0b1..Requested
 */
#define XSPI_TGIPCRS_ARB_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_ARB_LOCK_SHIFT)) & XSPI_TGIPCRS_ARB_LOCK_MASK)

#define XSPI_TGIPCRS_ARB_UNLOCK_MASK             (0x400000U)
#define XSPI_TGIPCRS_ARB_UNLOCK_SHIFT            (22U)
/*! ARB_UNLOCK - Arbitration Unlock
 *  0b0..Not requested
 *  0b1..Requested
 */
#define XSPI_TGIPCRS_ARB_UNLOCK(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_ARB_UNLOCK_SHIFT)) & XSPI_TGIPCRS_ARB_UNLOCK_MASK)

#define XSPI_TGIPCRS_CLR_MASK                    (0x10000000U)
#define XSPI_TGIPCRS_CLR_SHIFT                   (28U)
/*! CLR - Clear
 *  0b0..Conveys no useful information
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_TGIPCRS_CLR(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_CLR_SHIFT)) & XSPI_TGIPCRS_CLR_MASK)

#define XSPI_TGIPCRS_ERR_MASK                    (0x60000000U)
#define XSPI_TGIPCRS_ERR_SHIFT                   (29U)
/*! ERR - Error
 *  0b00..Required attributes
 *  0b01..IPCR DATZ without required attributes
 *  0b10..IPCR SEQID without required attributes
 *  0b11..IPCR IDATSZ and SEQID without required attributes
 */
#define XSPI_TGIPCRS_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_ERR_SHIFT)) & XSPI_TGIPCRS_ERR_MASK)

#define XSPI_TGIPCRS_VLD_MASK                    (0x80000000U)
#define XSPI_TGIPCRS_VLD_SHIFT                   (31U)
/*! VLD - Valid
 *  0b0..Not valid
 *  0b1..Valid and queue is locked
 */
#define XSPI_TGIPCRS_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_VLD_SHIFT)) & XSPI_TGIPCRS_VLD_MASK)
/*! @} */

/*! @name TG1MDAD - Target Group Manager Domain Access Descriptor */
/*! @{ */

#define XSPI_TG1MDAD_MIDMATCH_MASK               (0x3FU)
#define XSPI_TG1MDAD_MIDMATCH_SHIFT              (0U)
/*! MIDMATCH - Manager ID Reference */
#define XSPI_TG1MDAD_MIDMATCH(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_TG1MDAD_MIDMATCH_SHIFT)) & XSPI_TG1MDAD_MIDMATCH_MASK)

#define XSPI_TG1MDAD_MASK_MASK                   (0xFC0U)
#define XSPI_TG1MDAD_MASK_SHIFT                  (6U)
/*! MASK - Mask */
#define XSPI_TG1MDAD_MASK(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_TG1MDAD_MASK_SHIFT)) & XSPI_TG1MDAD_MASK_MASK)

#define XSPI_TG1MDAD_MASKTYPE_MASK               (0x1000U)
#define XSPI_TG1MDAD_MASKTYPE_SHIFT              (12U)
/*! MASKTYPE - Mask Type
 *  0b0..AND
 *  0b1..OR
 */
#define XSPI_TG1MDAD_MASKTYPE(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_TG1MDAD_MASKTYPE_SHIFT)) & XSPI_TG1MDAD_MASKTYPE_MASK)

#define XSPI_TG1MDAD_SA_MASK                     (0xC000U)
#define XSPI_TG1MDAD_SA_SHIFT                    (14U)
/*! SA - Secure Attribute
 *  0b00..
 *  0b01..Non-secure only
 *  0b10..Secure only
 *  0b11..Both secure and non-secure
 */
#define XSPI_TG1MDAD_SA(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_TG1MDAD_SA_SHIFT)) & XSPI_TG1MDAD_SA_MASK)

#define XSPI_TG1MDAD_LCK_MASK                    (0x20000000U)
#define XSPI_TG1MDAD_LCK_SHIFT                   (29U)
/*! LCK - Descriptor Lock
 *  0b0..No action
 *  0b1..Locks
 */
#define XSPI_TG1MDAD_LCK(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TG1MDAD_LCK_SHIFT)) & XSPI_TG1MDAD_LCK_MASK)

#define XSPI_TG1MDAD_VLD_MASK                    (0x80000000U)
#define XSPI_TG1MDAD_VLD_SHIFT                   (31U)
/*! VLD - Valid
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_TG1MDAD_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_TG1MDAD_VLD_SHIFT)) & XSPI_TG1MDAD_VLD_MASK)
/*! @} */

/*! @name MGC - Manager Global Configuration */
/*! @{ */

#define XSPI_MGC_GCLCKMID_MASK                   (0x3FU)
#define XSPI_MGC_GCLCKMID_SHIFT                  (0U)
/*! GCLCKMID - Global Configuration Lock Owner */
#define XSPI_MGC_GCLCKMID(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_MGC_GCLCKMID_SHIFT)) & XSPI_MGC_GCLCKMID_MASK)

#define XSPI_MGC_GCLCK_MASK                      (0xC00U)
#define XSPI_MGC_GCLCK_SHIFT                     (10U)
/*! GCLCK - Global Configuration Lock
 *  0b00..Unlocks
 *  0b01..Locks
 *  0b10..Locks
 *  0b11..Locks
 */
#define XSPI_MGC_GCLCK(x)                        (((uint32_t)(((uint32_t)(x)) << XSPI_MGC_GCLCK_SHIFT)) & XSPI_MGC_GCLCK_MASK)

#define XSPI_MGC_TG1_FIX_PRIO_MASK               (0x10000U)
#define XSPI_MGC_TG1_FIX_PRIO_SHIFT              (16U)
/*! TG1_FIX_PRIO - Target Group Queue 1 Fixed Priority Enable
 *  *..TG1 always has fixed priority regardless of this value.
 */
#define XSPI_MGC_TG1_FIX_PRIO(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_MGC_TG1_FIX_PRIO_SHIFT)) & XSPI_MGC_TG1_FIX_PRIO_MASK)

#define XSPI_MGC_GVLDFRAD_MASK                   (0x8000000U)
#define XSPI_MGC_GVLDFRAD_SHIFT                  (27U)
/*! GVLDFRAD - Global Valid FRAD
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_MGC_GVLDFRAD(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_MGC_GVLDFRAD_SHIFT)) & XSPI_MGC_GVLDFRAD_MASK)

#define XSPI_MGC_GVLDMDAD_MASK                   (0x20000000U)
#define XSPI_MGC_GVLDMDAD_SHIFT                  (29U)
/*! GVLDMDAD - Global Valid MDAD
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_MGC_GVLDMDAD(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_MGC_GVLDMDAD_SHIFT)) & XSPI_MGC_GVLDMDAD_MASK)

#define XSPI_MGC_GVLD_MASK                       (0x80000000U)
#define XSPI_MGC_GVLD_SHIFT                      (31U)
/*! GVLD - Global Valid Access Control
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_MGC_GVLD(x)                         (((uint32_t)(((uint32_t)(x)) << XSPI_MGC_GVLD_SHIFT)) & XSPI_MGC_GVLD_MASK)
/*! @} */

/*! @name MRC - Manager Read Command */
/*! @{ */

#define XSPI_MRC_READ_CMD0_MASK                  (0x3FU)
#define XSPI_MRC_READ_CMD0_SHIFT                 (0U)
/*! READ_CMD0 - Read Command 0 */
#define XSPI_MRC_READ_CMD0(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_MRC_READ_CMD0_SHIFT)) & XSPI_MRC_READ_CMD0_MASK)

#define XSPI_MRC_READ_CMD1_MASK                  (0x3F00U)
#define XSPI_MRC_READ_CMD1_SHIFT                 (8U)
/*! READ_CMD1 - Read Command 1 */
#define XSPI_MRC_READ_CMD1(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_MRC_READ_CMD1_SHIFT)) & XSPI_MRC_READ_CMD1_MASK)

#define XSPI_MRC_READ_CMD2_MASK                  (0x3F0000U)
#define XSPI_MRC_READ_CMD2_SHIFT                 (16U)
/*! READ_CMD2 - Read Command 2 */
#define XSPI_MRC_READ_CMD2(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_MRC_READ_CMD2_SHIFT)) & XSPI_MRC_READ_CMD2_MASK)

#define XSPI_MRC_VLDCMD02_MASK                   (0x400000U)
#define XSPI_MRC_VLDCMD02_SHIFT                  (22U)
/*! VLDCMD02 - Valid Command 2
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_MRC_VLDCMD02(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_MRC_VLDCMD02_SHIFT)) & XSPI_MRC_VLDCMD02_MASK)

#define XSPI_MRC_READ_CMD3_MASK                  (0x3F000000U)
#define XSPI_MRC_READ_CMD3_SHIFT                 (24U)
/*! READ_CMD3 - Read Command 3 */
#define XSPI_MRC_READ_CMD3(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_MRC_READ_CMD3_SHIFT)) & XSPI_MRC_READ_CMD3_MASK)

#define XSPI_MRC_VLDCMD03_MASK                   (0x40000000U)
#define XSPI_MRC_VLDCMD03_SHIFT                  (30U)
/*! VLDCMD03 - Valid Command 3
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_MRC_VLDCMD03(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_MRC_VLDCMD03_SHIFT)) & XSPI_MRC_VLDCMD03_MASK)
/*! @} */

/*! @name MTO - Manager Timeout */
/*! @{ */

#define XSPI_MTO_SFP_ACC_TO_MASK                 (0xFFFFFFFFU)
#define XSPI_MTO_SFP_ACC_TO_SHIFT                (0U)
/*! SFP_ACC_TO - SFP Access Timeout */
#define XSPI_MTO_SFP_ACC_TO(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_MTO_SFP_ACC_TO_SHIFT)) & XSPI_MTO_SFP_ACC_TO_MASK)
/*! @} */

/*! @name FLSEQREQ - Flash Sequence Request */
/*! @{ */

#define XSPI_FLSEQREQ_REQ_MID_MASK               (0x3FU)
#define XSPI_FLSEQREQ_REQ_MID_SHIFT              (0U)
/*! REQ_MID - Flash Sequence Request Manager ID */
#define XSPI_FLSEQREQ_REQ_MID(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_REQ_MID_SHIFT)) & XSPI_FLSEQREQ_REQ_MID_MASK)

#define XSPI_FLSEQREQ_REQ_TG_MASK                (0x40U)
#define XSPI_FLSEQREQ_REQ_TG_SHIFT               (6U)
/*! REQ_TG - FlashSeq Request Target Group
 *  0b0..TG0
 *  0b1..TG1
 */
#define XSPI_FLSEQREQ_REQ_TG(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_REQ_TG_SHIFT)) & XSPI_FLSEQREQ_REQ_TG_MASK)

#define XSPI_FLSEQREQ_SA_MASK                    (0x100U)
#define XSPI_FLSEQREQ_SA_SHIFT                   (8U)
/*! SA - Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_FLSEQREQ_SA(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_SA_SHIFT)) & XSPI_FLSEQREQ_SA_MASK)

#define XSPI_FLSEQREQ_PA_MASK                    (0x200U)
#define XSPI_FLSEQREQ_PA_SHIFT                   (9U)
/*! PA - Privilege Attribute
 *  0b0..Non-privilege
 *  0b1..Privilege
 */
#define XSPI_FLSEQREQ_PA(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_PA_SHIFT)) & XSPI_FLSEQREQ_PA_MASK)

#define XSPI_FLSEQREQ_ARB_LOCK_MASK              (0x400U)
#define XSPI_FLSEQREQ_ARB_LOCK_SHIFT             (10U)
/*! ARB_LOCK - Arbitration Lock
 *  0b0..Not locked
 *  0b1..Locked
 */
#define XSPI_FLSEQREQ_ARB_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_ARB_LOCK_SHIFT)) & XSPI_FLSEQREQ_ARB_LOCK_MASK)

#define XSPI_FLSEQREQ_FRAD_MASK                  (0x7000U)
#define XSPI_FLSEQREQ_FRAD_SHIFT                 (12U)
/*! FRAD - Flash Region Descriptor Number */
#define XSPI_FLSEQREQ_FRAD(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_FRAD_SHIFT)) & XSPI_FLSEQREQ_FRAD_MASK)

#define XSPI_FLSEQREQ_SEQID_MASK                 (0xF0000U)
#define XSPI_FLSEQREQ_SEQID_SHIFT                (16U)
/*! SEQID - Sequence ID */
#define XSPI_FLSEQREQ_SEQID(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_SEQID_SHIFT)) & XSPI_FLSEQREQ_SEQID_MASK)

#define XSPI_FLSEQREQ_CMD_MASK                   (0x400000U)
#define XSPI_FLSEQREQ_CMD_SHIFT                  (22U)
/*! CMD - Instruction Type
 *  0b0..Read
 *  0b1..Non-read
 */
#define XSPI_FLSEQREQ_CMD(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_CMD_SHIFT)) & XSPI_FLSEQREQ_CMD_MASK)

#define XSPI_FLSEQREQ_TIMEOUT_MASK               (0x8000000U)
#define XSPI_FLSEQREQ_TIMEOUT_SHIFT              (27U)
/*! TIMEOUT - Timeout Error Status
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_FLSEQREQ_TIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_TIMEOUT_SHIFT)) & XSPI_FLSEQREQ_TIMEOUT_MASK)

#define XSPI_FLSEQREQ_VLD_MASK                   (0x80000000U)
#define XSPI_FLSEQREQ_VLD_SHIFT                  (31U)
/*! VLD - Valid
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_FLSEQREQ_VLD(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_VLD_SHIFT)) & XSPI_FLSEQREQ_VLD_MASK)
/*! @} */

/*! @name FSMSTAT - FSM Status */
/*! @{ */

#define XSPI_FSMSTAT_STATE_MASK                  (0x3U)
#define XSPI_FSMSTAT_STATE_SHIFT                 (0U)
/*! STATE - FSM State
 *  0b00..Transaction granted
 *  0b01..TBDR lock open
 *  0b10..Write transfer triggered
 *  0b11..Read transfer triggered
 */
#define XSPI_FSMSTAT_STATE(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_FSMSTAT_STATE_SHIFT)) & XSPI_FSMSTAT_STATE_MASK)

#define XSPI_FSMSTAT_MID_MASK                    (0x3F00U)
#define XSPI_FSMSTAT_MID_SHIFT                   (8U)
/*! MID - Manager ID */
#define XSPI_FSMSTAT_MID(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_FSMSTAT_MID_SHIFT)) & XSPI_FSMSTAT_MID_MASK)

#define XSPI_FSMSTAT_CMD_MASK                    (0x10000U)
#define XSPI_FSMSTAT_CMD_SHIFT                   (16U)
/*! CMD - Command
 *  0b0..Read instruction sequence
 *  0b1..Non-read instruction sequence
 */
#define XSPI_FSMSTAT_CMD(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_FSMSTAT_CMD_SHIFT)) & XSPI_FSMSTAT_CMD_MASK)

#define XSPI_FSMSTAT_ARB_LOCK_MASK               (0x20000U)
#define XSPI_FSMSTAT_ARB_LOCK_SHIFT              (17U)
/*! ARB_LOCK - Arbitration Lock
 *  0b0..Not locked
 *  0b1..Locked
 */
#define XSPI_FSMSTAT_ARB_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_FSMSTAT_ARB_LOCK_SHIFT)) & XSPI_FSMSTAT_ARB_LOCK_MASK)

#define XSPI_FSMSTAT_VLD_MASK                    (0x80000000U)
#define XSPI_FSMSTAT_VLD_SHIFT                   (31U)
/*! VLD - Valid
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_FSMSTAT_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << XSPI_FSMSTAT_VLD_SHIFT)) & XSPI_FSMSTAT_VLD_MASK)
/*! @} */

/*! @name IPSERROR - IPS Error */
/*! @{ */

#define XSPI_IPSERROR_MID_MASK                   (0x3FU)
#define XSPI_IPSERROR_MID_SHIFT                  (0U)
/*! MID - IPS Manager ID */
#define XSPI_IPSERROR_MID(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_MID_SHIFT)) & XSPI_IPSERROR_MID_MASK)

#define XSPI_IPSERROR_TG0LCK_MASK                (0x100U)
#define XSPI_IPSERROR_TG0LCK_SHIFT               (8U)
/*! TG0LCK - TG0 Lock
 *  0b0..SEQID not written yet
 *  0b1..SEQID written and queue locked
 */
#define XSPI_IPSERROR_TG0LCK(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_TG0LCK_SHIFT)) & XSPI_IPSERROR_TG0LCK_MASK)

#define XSPI_IPSERROR_TG1LCK_MASK                (0x200U)
#define XSPI_IPSERROR_TG1LCK_SHIFT               (9U)
/*! TG1LCK - TG1 Lock
 *  0b0..SEQID not written yet
 *  0b1..SEQID written and queue locked
 */
#define XSPI_IPSERROR_TG1LCK(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_TG1LCK_SHIFT)) & XSPI_IPSERROR_TG1LCK_MASK)

#define XSPI_IPSERROR_TG0SEC_MASK                (0x400U)
#define XSPI_IPSERROR_TG0SEC_SHIFT               (10U)
/*! TG0SEC - TG Security Status
 *  0b0..Security attribute check passed
 *  0b1..Security attribute check failed
 */
#define XSPI_IPSERROR_TG0SEC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_TG0SEC_SHIFT)) & XSPI_IPSERROR_TG0SEC_MASK)

#define XSPI_IPSERROR_TG1SEC_MASK                (0x800U)
#define XSPI_IPSERROR_TG1SEC_SHIFT               (11U)
/*! TG1SEC - TG Security Status
 *  0b0..Security attribute check passed
 *  0b1..Security attribute check failed
 */
#define XSPI_IPSERROR_TG1SEC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_TG1SEC_SHIFT)) & XSPI_IPSERROR_TG1SEC_MASK)

#define XSPI_IPSERROR_TG0MID_MASK                (0x1000U)
#define XSPI_IPSERROR_TG0MID_SHIFT               (12U)
/*! TG0MID - TGn Manager-ID Status
 *  0b0..Passed
 *  0b1..Failed
 */
#define XSPI_IPSERROR_TG0MID(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_TG0MID_SHIFT)) & XSPI_IPSERROR_TG0MID_MASK)

#define XSPI_IPSERROR_TG1MID_MASK                (0x2000U)
#define XSPI_IPSERROR_TG1MID_SHIFT               (13U)
/*! TG1MID - TGn Manager-ID Status
 *  0b0..Passed
 *  0b1..Failed
 */
#define XSPI_IPSERROR_TG1MID(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_TG1MID_SHIFT)) & XSPI_IPSERROR_TG1MID_MASK)

#define XSPI_IPSERROR_MDADPROG_MASK              (0x4000U)
#define XSPI_IPSERROR_MDADPROG_SHIFT             (14U)
/*! MDADPROG - TG/MDA Descriptor Program Status
 *  0b0..One or both target group descriptors programmed
 *  0b1..None of the target group descriptors are programmed or valid
 */
#define XSPI_IPSERROR_MDADPROG(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_MDADPROG_SHIFT)) & XSPI_IPSERROR_MDADPROG_MASK)

#define XSPI_IPSERROR_FRADPROG_MASK              (0x8000U)
#define XSPI_IPSERROR_FRADPROG_SHIFT             (15U)
/*! FRADPROG - FRAD Program Status
 *  0b0..Some or all FRADs programmed
 *  0b1..No FRADs programmed
 */
#define XSPI_IPSERROR_FRADPROG(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_FRADPROG_SHIFT)) & XSPI_IPSERROR_FRADPROG_MASK)

#define XSPI_IPSERROR_CLR_MASK                   (0x20000000U)
#define XSPI_IPSERROR_CLR_SHIFT                  (29U)
/*! CLR - Clear
 *  0b0..Conveys no useful information
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_IPSERROR_CLR(x)                     (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_CLR_SHIFT)) & XSPI_IPSERROR_CLR_MASK)
/*! @} */

/*! @name ERRSTAT - Error Status */
/*! @{ */

#define XSPI_ERRSTAT_FRADMTCH_MASK               (0x1U)
#define XSPI_ERRSTAT_FRADMTCH_SHIFT              (0U)
/*! FRADMTCH - No FRAD Match Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRADMTCH(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRADMTCH_SHIFT)) & XSPI_ERRSTAT_FRADMTCH_MASK)

#define XSPI_ERRSTAT_FRAD0ACC_MASK               (0x2U)
#define XSPI_ERRSTAT_FRAD0ACC_SHIFT              (1U)
/*! FRAD0ACC - FRAD Access Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRAD0ACC(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD0ACC_SHIFT)) & XSPI_ERRSTAT_FRAD0ACC_MASK)

#define XSPI_ERRSTAT_FRAD1ACC_MASK               (0x4U)
#define XSPI_ERRSTAT_FRAD1ACC_SHIFT              (2U)
/*! FRAD1ACC - FRAD Access Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRAD1ACC(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD1ACC_SHIFT)) & XSPI_ERRSTAT_FRAD1ACC_MASK)

#define XSPI_ERRSTAT_FRAD2ACC_MASK               (0x8U)
#define XSPI_ERRSTAT_FRAD2ACC_SHIFT              (3U)
/*! FRAD2ACC - FRAD Access Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRAD2ACC(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD2ACC_SHIFT)) & XSPI_ERRSTAT_FRAD2ACC_MASK)

#define XSPI_ERRSTAT_FRAD3ACC_MASK               (0x10U)
#define XSPI_ERRSTAT_FRAD3ACC_SHIFT              (4U)
/*! FRAD3ACC - FRAD Access Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRAD3ACC(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD3ACC_SHIFT)) & XSPI_ERRSTAT_FRAD3ACC_MASK)

#define XSPI_ERRSTAT_FRAD4ACC_MASK               (0x20U)
#define XSPI_ERRSTAT_FRAD4ACC_SHIFT              (5U)
/*! FRAD4ACC - FRAD Access Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRAD4ACC(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD4ACC_SHIFT)) & XSPI_ERRSTAT_FRAD4ACC_MASK)

#define XSPI_ERRSTAT_FRAD5ACC_MASK               (0x40U)
#define XSPI_ERRSTAT_FRAD5ACC_SHIFT              (6U)
/*! FRAD5ACC - FRAD Access Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRAD5ACC(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD5ACC_SHIFT)) & XSPI_ERRSTAT_FRAD5ACC_MASK)

#define XSPI_ERRSTAT_FRAD6ACC_MASK               (0x80U)
#define XSPI_ERRSTAT_FRAD6ACC_SHIFT              (7U)
/*! FRAD6ACC - FRAD Access Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRAD6ACC(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD6ACC_SHIFT)) & XSPI_ERRSTAT_FRAD6ACC_MASK)

#define XSPI_ERRSTAT_FRAD7ACC_MASK               (0x100U)
#define XSPI_ERRSTAT_FRAD7ACC_SHIFT              (8U)
/*! FRAD7ACC - FRAD Access Error
 *  0b0..No error
 *  0b1..Error
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_FRAD7ACC(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD7ACC_SHIFT)) & XSPI_ERRSTAT_FRAD7ACC_MASK)

#define XSPI_ERRSTAT_IPS_ERR_MASK                (0x200U)
#define XSPI_ERRSTAT_IPS_ERR_SHIFT               (9U)
/*! IPS_ERR - IPS Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_ERRSTAT_IPS_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_IPS_ERR_SHIFT)) & XSPI_ERRSTAT_IPS_ERR_MASK)

#define XSPI_ERRSTAT_TG0SFAR_MASK                (0x400U)
#define XSPI_ERRSTAT_TG0SFAR_SHIFT               (10U)
/*! TG0SFAR - TG SFAR Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_ERRSTAT_TG0SFAR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_TG0SFAR_SHIFT)) & XSPI_ERRSTAT_TG0SFAR_MASK)

#define XSPI_ERRSTAT_TG1SFAR_MASK                (0x800U)
#define XSPI_ERRSTAT_TG1SFAR_SHIFT               (11U)
/*! TG1SFAR - TG SFAR Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_ERRSTAT_TG1SFAR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_TG1SFAR_SHIFT)) & XSPI_ERRSTAT_TG1SFAR_MASK)

#define XSPI_ERRSTAT_TG0IPCR_MASK                (0x1000U)
#define XSPI_ERRSTAT_TG0IPCR_SHIFT               (12U)
/*! TG0IPCR - TG IPCR Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_ERRSTAT_TG0IPCR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_TG0IPCR_SHIFT)) & XSPI_ERRSTAT_TG0IPCR_MASK)

#define XSPI_ERRSTAT_TG1IPCR_MASK                (0x2000U)
#define XSPI_ERRSTAT_TG1IPCR_SHIFT               (13U)
/*! TG1IPCR - TG IPCR Error
 *  0b0..No error
 *  0b1..Error
 */
#define XSPI_ERRSTAT_TG1IPCR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_TG1IPCR_SHIFT)) & XSPI_ERRSTAT_TG1IPCR_MASK)

#define XSPI_ERRSTAT_TO_ERR_MASK                 (0x4000U)
#define XSPI_ERRSTAT_TO_ERR_SHIFT                (14U)
/*! TO_ERR - Timeout Error
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_TO_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_TO_ERR_SHIFT)) & XSPI_ERRSTAT_TO_ERR_MASK)

#define XSPI_ERRSTAT_ARB_WIN_MASK                (0x10000000U)
#define XSPI_ERRSTAT_ARB_WIN_SHIFT               (28U)
/*! ARB_WIN - Arbitration Win Event Status
 *  0b0..Request not granted or the interrupt is already cleared
 *  0b0..No action
 *  0b1..Request granted and interrupt generated
 *  0b1..Clears interrupt
 */
#define XSPI_ERRSTAT_ARB_WIN(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_ARB_WIN_SHIFT)) & XSPI_ERRSTAT_ARB_WIN_MASK)

#define XSPI_ERRSTAT_ARB_LOCK_TO_MASK            (0x20000000U)
#define XSPI_ERRSTAT_ARB_LOCK_TO_SHIFT           (29U)
/*! ARB_LOCK_TO - Arbitration Lock Timeout Error
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears flag
 */
#define XSPI_ERRSTAT_ARB_LOCK_TO(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_ARB_LOCK_TO_SHIFT)) & XSPI_ERRSTAT_ARB_LOCK_TO_MASK)

#define XSPI_ERRSTAT_LOCK_ERR_MASK               (0x40000000U)
#define XSPI_ERRSTAT_LOCK_ERR_SHIFT              (30U)
/*! LOCK_ERR - Lock Register Error
 *  0b0..No error
 *  0b0..No action
 *  0b1..Error
 *  0b1..Clears
 */
#define XSPI_ERRSTAT_LOCK_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_LOCK_ERR_SHIFT)) & XSPI_ERRSTAT_LOCK_ERR_MASK)
/*! @} */

/*! @name INT_EN - Interrupt Enable */
/*! @{ */

#define XSPI_INT_EN_FRADMTCH_MASK                (0x1U)
#define XSPI_INT_EN_FRADMTCH_SHIFT               (0U)
/*! FRADMTCH - No FRAD Match Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRADMTCH(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRADMTCH_SHIFT)) & XSPI_INT_EN_FRADMTCH_MASK)

#define XSPI_INT_EN_FRAD0ACC_MASK                (0x2U)
#define XSPI_INT_EN_FRAD0ACC_SHIFT               (1U)
/*! FRAD0ACC - FRAD Access Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRAD0ACC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRAD0ACC_SHIFT)) & XSPI_INT_EN_FRAD0ACC_MASK)

#define XSPI_INT_EN_FRAD1ACC_MASK                (0x4U)
#define XSPI_INT_EN_FRAD1ACC_SHIFT               (2U)
/*! FRAD1ACC - FRAD Access Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRAD1ACC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRAD1ACC_SHIFT)) & XSPI_INT_EN_FRAD1ACC_MASK)

#define XSPI_INT_EN_FRAD2ACC_MASK                (0x8U)
#define XSPI_INT_EN_FRAD2ACC_SHIFT               (3U)
/*! FRAD2ACC - FRAD Access Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRAD2ACC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRAD2ACC_SHIFT)) & XSPI_INT_EN_FRAD2ACC_MASK)

#define XSPI_INT_EN_FRAD3ACC_MASK                (0x10U)
#define XSPI_INT_EN_FRAD3ACC_SHIFT               (4U)
/*! FRAD3ACC - FRAD Access Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRAD3ACC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRAD3ACC_SHIFT)) & XSPI_INT_EN_FRAD3ACC_MASK)

#define XSPI_INT_EN_FRAD4ACC_MASK                (0x20U)
#define XSPI_INT_EN_FRAD4ACC_SHIFT               (5U)
/*! FRAD4ACC - FRAD Access Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRAD4ACC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRAD4ACC_SHIFT)) & XSPI_INT_EN_FRAD4ACC_MASK)

#define XSPI_INT_EN_FRAD5ACC_MASK                (0x40U)
#define XSPI_INT_EN_FRAD5ACC_SHIFT               (6U)
/*! FRAD5ACC - FRAD Access Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRAD5ACC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRAD5ACC_SHIFT)) & XSPI_INT_EN_FRAD5ACC_MASK)

#define XSPI_INT_EN_FRAD6ACC_MASK                (0x80U)
#define XSPI_INT_EN_FRAD6ACC_SHIFT               (7U)
/*! FRAD6ACC - FRAD Access Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRAD6ACC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRAD6ACC_SHIFT)) & XSPI_INT_EN_FRAD6ACC_MASK)

#define XSPI_INT_EN_FRAD7ACC_MASK                (0x100U)
#define XSPI_INT_EN_FRAD7ACC_SHIFT               (8U)
/*! FRAD7ACC - FRAD Access Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_FRAD7ACC(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_FRAD7ACC_SHIFT)) & XSPI_INT_EN_FRAD7ACC_MASK)

#define XSPI_INT_EN_IPS_ERR_MASK                 (0x200U)
#define XSPI_INT_EN_IPS_ERR_SHIFT                (9U)
/*! IPS_ERR - IPS Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_IPS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_IPS_ERR_SHIFT)) & XSPI_INT_EN_IPS_ERR_MASK)

#define XSPI_INT_EN_TG0SFAR_MASK                 (0x400U)
#define XSPI_INT_EN_TG0SFAR_SHIFT                (10U)
/*! TG0SFAR - TG SFAR Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_TG0SFAR(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_TG0SFAR_SHIFT)) & XSPI_INT_EN_TG0SFAR_MASK)

#define XSPI_INT_EN_TG1SFAR_MASK                 (0x800U)
#define XSPI_INT_EN_TG1SFAR_SHIFT                (11U)
/*! TG1SFAR - TG SFAR Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_TG1SFAR(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_TG1SFAR_SHIFT)) & XSPI_INT_EN_TG1SFAR_MASK)

#define XSPI_INT_EN_TG0IPCR_MASK                 (0x1000U)
#define XSPI_INT_EN_TG0IPCR_SHIFT                (12U)
/*! TG0IPCR - TGn IPCR Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_TG0IPCR(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_TG0IPCR_SHIFT)) & XSPI_INT_EN_TG0IPCR_MASK)

#define XSPI_INT_EN_TG1IPCR_MASK                 (0x2000U)
#define XSPI_INT_EN_TG1IPCR_SHIFT                (13U)
/*! TG1IPCR - TGn IPCR Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_TG1IPCR(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_TG1IPCR_SHIFT)) & XSPI_INT_EN_TG1IPCR_MASK)

#define XSPI_INT_EN_TO_ERR_MASK                  (0x4000U)
#define XSPI_INT_EN_TO_ERR_SHIFT                 (14U)
/*! TO_ERR - Timeout Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_TO_ERR(x)                    (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_TO_ERR_SHIFT)) & XSPI_INT_EN_TO_ERR_MASK)

#define XSPI_INT_EN_ARB_WIN_IE_MASK              (0x10000000U)
#define XSPI_INT_EN_ARB_WIN_IE_SHIFT             (28U)
/*! ARB_WIN_IE - Arbitration Win Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_ARB_WIN_IE(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_ARB_WIN_IE_SHIFT)) & XSPI_INT_EN_ARB_WIN_IE_MASK)

#define XSPI_INT_EN_ARB_TO_IE_MASK               (0x20000000U)
#define XSPI_INT_EN_ARB_TO_IE_SHIFT              (29U)
/*! ARB_TO_IE - Arbitration Lock Timeout Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_ARB_TO_IE(x)                 (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_ARB_TO_IE_SHIFT)) & XSPI_INT_EN_ARB_TO_IE_MASK)

#define XSPI_INT_EN_LCK_ERR_IE_MASK              (0x40000000U)
#define XSPI_INT_EN_LCK_ERR_IE_SHIFT             (30U)
/*! LCK_ERR_IE - Lock Register Write Error Interrupt Enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define XSPI_INT_EN_LCK_ERR_IE(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_LCK_ERR_IE_SHIFT)) & XSPI_INT_EN_LCK_ERR_IE_MASK)

#define XSPI_INT_EN_LCK_MASK                     (0x80000000U)
#define XSPI_INT_EN_LCK_SHIFT                    (31U)
/*! LCK - Lock
 *  0b0..Unlocks
 *  0b1..Locks
 */
#define XSPI_INT_EN_LCK(x)                       (((uint32_t)(((uint32_t)(x)) << XSPI_INT_EN_LCK_SHIFT)) & XSPI_INT_EN_LCK_MASK)
/*! @} */

/*! @name SFP_TG_IPCR - IP Configuration */
/*! @{ */

#define XSPI_SFP_TG_IPCR_IDATSZ_MASK             (0xFFFFU)
#define XSPI_SFP_TG_IPCR_IDATSZ_SHIFT            (0U)
/*! IDATSZ - IP Data Transfer Size */
#define XSPI_SFP_TG_IPCR_IDATSZ(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_IPCR_IDATSZ_SHIFT)) & XSPI_SFP_TG_IPCR_IDATSZ_MASK)

#define XSPI_SFP_TG_IPCR_ARB_LOCK_MASK           (0x400000U)
#define XSPI_SFP_TG_IPCR_ARB_LOCK_SHIFT          (22U)
/*! ARB_LOCK - Arbitration Lock
 *  0b0..No effect. Always reads 0.
 *  0b1..Locks
 */
#define XSPI_SFP_TG_IPCR_ARB_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_IPCR_ARB_LOCK_SHIFT)) & XSPI_SFP_TG_IPCR_ARB_LOCK_MASK)

#define XSPI_SFP_TG_IPCR_ARB_UNLOCK_MASK         (0x800000U)
#define XSPI_SFP_TG_IPCR_ARB_UNLOCK_SHIFT        (23U)
/*! ARB_UNLOCK - Arbitration Unlock
 *  0b0..No effect. Always reads 0.
 *  0b1..Unlocks
 */
#define XSPI_SFP_TG_IPCR_ARB_UNLOCK(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_IPCR_ARB_UNLOCK_SHIFT)) & XSPI_SFP_TG_IPCR_ARB_UNLOCK_MASK)

#define XSPI_SFP_TG_IPCR_SEQID_MASK              (0xF000000U)
#define XSPI_SFP_TG_IPCR_SEQID_SHIFT             (24U)
/*! SEQID - Sequence ID */
#define XSPI_SFP_TG_IPCR_SEQID(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_IPCR_SEQID_SHIFT)) & XSPI_SFP_TG_IPCR_SEQID_MASK)
/*! @} */

/*! @name SFP_TG_SFAR - Serial Flash Memory Address */
/*! @{ */

#define XSPI_SFP_TG_SFAR_SFADR_MASK              (0xFFFFFFFFU)
#define XSPI_SFP_TG_SFAR_SFADR_SHIFT             (0U)
/*! SFADR - Serial Flash Memory Address */
#define XSPI_SFP_TG_SFAR_SFADR(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_SFAR_SFADR_SHIFT)) & XSPI_SFP_TG_SFAR_SFADR_MASK)
/*! @} */

/*! @name SFP_LUT_EN - LUT Access Enable */
/*! @{ */

#define XSPI_SFP_LUT_EN_LUT_SEQ0_EN_MASK         (0x1U)
#define XSPI_SFP_LUT_EN_LUT_SEQ0_EN_SHIFT        (0U)
/*! LUT_SEQ0_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ0_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ0_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ0_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ1_EN_MASK         (0x2U)
#define XSPI_SFP_LUT_EN_LUT_SEQ1_EN_SHIFT        (1U)
/*! LUT_SEQ1_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ1_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ1_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ1_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ2_EN_MASK         (0x4U)
#define XSPI_SFP_LUT_EN_LUT_SEQ2_EN_SHIFT        (2U)
/*! LUT_SEQ2_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ2_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ2_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ2_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ3_EN_MASK         (0x8U)
#define XSPI_SFP_LUT_EN_LUT_SEQ3_EN_SHIFT        (3U)
/*! LUT_SEQ3_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ3_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ3_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ3_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ4_EN_MASK         (0x10U)
#define XSPI_SFP_LUT_EN_LUT_SEQ4_EN_SHIFT        (4U)
/*! LUT_SEQ4_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ4_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ4_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ4_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ5_EN_MASK         (0x20U)
#define XSPI_SFP_LUT_EN_LUT_SEQ5_EN_SHIFT        (5U)
/*! LUT_SEQ5_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ5_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ5_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ5_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ6_EN_MASK         (0x40U)
#define XSPI_SFP_LUT_EN_LUT_SEQ6_EN_SHIFT        (6U)
/*! LUT_SEQ6_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ6_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ6_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ6_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ7_EN_MASK         (0x80U)
#define XSPI_SFP_LUT_EN_LUT_SEQ7_EN_SHIFT        (7U)
/*! LUT_SEQ7_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ7_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ7_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ7_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ8_EN_MASK         (0x100U)
#define XSPI_SFP_LUT_EN_LUT_SEQ8_EN_SHIFT        (8U)
/*! LUT_SEQ8_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ8_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ8_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ8_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ9_EN_MASK         (0x200U)
#define XSPI_SFP_LUT_EN_LUT_SEQ9_EN_SHIFT        (9U)
/*! LUT_SEQ9_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ9_EN(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ9_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ9_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ10_EN_MASK        (0x400U)
#define XSPI_SFP_LUT_EN_LUT_SEQ10_EN_SHIFT       (10U)
/*! LUT_SEQ10_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ10_EN(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ10_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ10_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ11_EN_MASK        (0x800U)
#define XSPI_SFP_LUT_EN_LUT_SEQ11_EN_SHIFT       (11U)
/*! LUT_SEQ11_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ11_EN(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ11_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ11_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ12_EN_MASK        (0x1000U)
#define XSPI_SFP_LUT_EN_LUT_SEQ12_EN_SHIFT       (12U)
/*! LUT_SEQ12_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ12_EN(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ12_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ12_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ13_EN_MASK        (0x2000U)
#define XSPI_SFP_LUT_EN_LUT_SEQ13_EN_SHIFT       (13U)
/*! LUT_SEQ13_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ13_EN(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ13_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ13_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ14_EN_MASK        (0x4000U)
#define XSPI_SFP_LUT_EN_LUT_SEQ14_EN_SHIFT       (14U)
/*! LUT_SEQ14_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ14_EN(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ14_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ14_EN_MASK)

#define XSPI_SFP_LUT_EN_LUT_SEQ15_EN_MASK        (0x8000U)
#define XSPI_SFP_LUT_EN_LUT_SEQ15_EN_SHIFT       (15U)
/*! LUT_SEQ15_EN - LUT Sequence Enable
 *  0b1..Disables
 *  0b0..Enables
 */
#define XSPI_SFP_LUT_EN_LUT_SEQ15_EN(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LUT_SEQ15_EN_SHIFT)) & XSPI_SFP_LUT_EN_LUT_SEQ15_EN_MASK)

#define XSPI_SFP_LUT_EN_LOCK_MASK                (0x80000000U)
#define XSPI_SFP_LUT_EN_LOCK_SHIFT               (31U)
/*! LOCK
 *  0b0..No effect
 *  0b1..Locks
 */
#define XSPI_SFP_LUT_EN_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LUT_EN_LOCK_SHIFT)) & XSPI_SFP_LUT_EN_LOCK_MASK)
/*! @} */

/* The count of XSPI_SFP_LUT_EN */
#define XSPI_SFP_LUT_EN_COUNT                    (2U)

/*! @name SFP_LOCK_ERR_ADDR - SFP Lock Error Address */
/*! @{ */

#define XSPI_SFP_LOCK_ERR_ADDR_ADDRW_MASK        (0x7FFFU)
#define XSPI_SFP_LOCK_ERR_ADDR_ADDRW_SHIFT       (0U)
/*! ADDRW - Address */
#define XSPI_SFP_LOCK_ERR_ADDR_ADDRW(x)          (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_LOCK_ERR_ADDR_ADDRW_SHIFT)) & XSPI_SFP_LOCK_ERR_ADDR_ADDRW_MASK)
/*! @} */

/*! @name SFP_TG_SUB_IPCR - IP Configuration */
/*! @{ */

#define XSPI_SFP_TG_SUB_IPCR_IDATSZ_MASK         (0xFFFFU)
#define XSPI_SFP_TG_SUB_IPCR_IDATSZ_SHIFT        (0U)
/*! IDATSZ - IP Data Transfer Size */
#define XSPI_SFP_TG_SUB_IPCR_IDATSZ(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_SUB_IPCR_IDATSZ_SHIFT)) & XSPI_SFP_TG_SUB_IPCR_IDATSZ_MASK)

#define XSPI_SFP_TG_SUB_IPCR_ARB_LOCK_MASK       (0x400000U)
#define XSPI_SFP_TG_SUB_IPCR_ARB_LOCK_SHIFT      (22U)
/*! ARB_LOCK - Arbitration Lock
 *  0b0..No effect. Always reads 0.
 *  0b1..Locks
 */
#define XSPI_SFP_TG_SUB_IPCR_ARB_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_SUB_IPCR_ARB_LOCK_SHIFT)) & XSPI_SFP_TG_SUB_IPCR_ARB_LOCK_MASK)

#define XSPI_SFP_TG_SUB_IPCR_ARB_UNLOCK_MASK     (0x800000U)
#define XSPI_SFP_TG_SUB_IPCR_ARB_UNLOCK_SHIFT    (23U)
/*! ARB_UNLOCK - Arbitration Unlock
 *  0b0..No effect. Always reads 0.
 *  0b1..Unlocks
 */
#define XSPI_SFP_TG_SUB_IPCR_ARB_UNLOCK(x)       (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_SUB_IPCR_ARB_UNLOCK_SHIFT)) & XSPI_SFP_TG_SUB_IPCR_ARB_UNLOCK_MASK)

#define XSPI_SFP_TG_SUB_IPCR_SEQID_MASK          (0xF000000U)
#define XSPI_SFP_TG_SUB_IPCR_SEQID_SHIFT         (24U)
/*! SEQID - Points to a sequence in the LUT */
#define XSPI_SFP_TG_SUB_IPCR_SEQID(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_SUB_IPCR_SEQID_SHIFT)) & XSPI_SFP_TG_SUB_IPCR_SEQID_MASK)
/*! @} */

/* The count of XSPI_SFP_TG_SUB_IPCR */
#define XSPI_SFP_TG_SUB_IPCR_COUNT               (1U)

/*! @name SFP_TG_SUB_SFAR - Serial Flash Memory Address */
/*! @{ */

#define XSPI_SFP_TG_SUB_SFAR_SFADR_MASK          (0xFFFFFFFFU)
#define XSPI_SFP_TG_SUB_SFAR_SFADR_SHIFT         (0U)
/*! SFADR - Serial flash memory address */
#define XSPI_SFP_TG_SUB_SFAR_SFADR(x)            (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_TG_SUB_SFAR_SFADR_SHIFT)) & XSPI_SFP_TG_SUB_SFAR_SFADR_MASK)
/*! @} */

/* The count of XSPI_SFP_TG_SUB_SFAR */
#define XSPI_SFP_TG_SUB_SFAR_COUNT               (1U)

/*! @name TGSFAR_SUB - Target Group SFAR Address */
/*! @{ */

#define XSPI_TGSFAR_SUB_SFARADDR_MASK            (0xFFFFFFFFU)
#define XSPI_TGSFAR_SUB_SFARADDR_SHIFT           (0U)
/*! SFARADDR - SFAR Address */
#define XSPI_TGSFAR_SUB_SFARADDR(x)              (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFAR_SUB_SFARADDR_SHIFT)) & XSPI_TGSFAR_SUB_SFARADDR_MASK)
/*! @} */

/* The count of XSPI_TGSFAR_SUB */
#define XSPI_TGSFAR_SUB_COUNT                    (1U)

/*! @name TGSFARS_SUB - Target Group SFAR Status */
/*! @{ */

#define XSPI_TGSFARS_SUB_TG_MID_MASK             (0x3FU)
#define XSPI_TGSFARS_SUB_TG_MID_SHIFT            (0U)
/*! TG_MID - Transaction Manager ID */
#define XSPI_TGSFARS_SUB_TG_MID(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_SUB_TG_MID_SHIFT)) & XSPI_TGSFARS_SUB_TG_MID_MASK)

#define XSPI_TGSFARS_SUB_SA_MASK                 (0x400U)
#define XSPI_TGSFARS_SUB_SA_SHIFT                (10U)
/*! SA - Secure Attribute
 *  0b0..Non-secure
 *  0b1..Secure
 */
#define XSPI_TGSFARS_SUB_SA(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_SUB_SA_SHIFT)) & XSPI_TGSFARS_SUB_SA_MASK)

#define XSPI_TGSFARS_SUB_PA_MASK                 (0x1000U)
#define XSPI_TGSFARS_SUB_PA_SHIFT                (12U)
/*! PA - Privileged Attribute
 *  0b0..Non-privileged
 *  0b1..Privileged
 */
#define XSPI_TGSFARS_SUB_PA(x)                   (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_SUB_PA_SHIFT)) & XSPI_TGSFARS_SUB_PA_MASK)

#define XSPI_TGSFARS_SUB_CLR_MASK                (0x20000000U)
#define XSPI_TGSFARS_SUB_CLR_SHIFT               (29U)
/*! CLR - Clear
 *  0b0..Conveys no useful information
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_TGSFARS_SUB_CLR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_SUB_CLR_SHIFT)) & XSPI_TGSFARS_SUB_CLR_MASK)

#define XSPI_TGSFARS_SUB_ERR_MASK                (0x40000000U)
#define XSPI_TGSFARS_SUB_ERR_SHIFT               (30U)
/*! ERR - Error
 *  0b0..With required attributes
 *  0b1..Without required attributes
 */
#define XSPI_TGSFARS_SUB_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_SUB_ERR_SHIFT)) & XSPI_TGSFARS_SUB_ERR_MASK)

#define XSPI_TGSFARS_SUB_VLD_MASK                (0x80000000U)
#define XSPI_TGSFARS_SUB_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Not valid
 *  0b1..Valid
 */
#define XSPI_TGSFARS_SUB_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_SUB_VLD_SHIFT)) & XSPI_TGSFARS_SUB_VLD_MASK)
/*! @} */

/* The count of XSPI_TGSFARS_SUB */
#define XSPI_TGSFARS_SUB_COUNT                   (1U)

/*! @name TGIPCRS_SUB - Target Group n IP Configuration Status */
/*! @{ */

#define XSPI_TGIPCRS_SUB_IDATSZ_MASK             (0xFFFFU)
#define XSPI_TGIPCRS_SUB_IDATSZ_SHIFT            (0U)
/*! IDATSZ - IP Data Transfer Size */
#define XSPI_TGIPCRS_SUB_IDATSZ(x)               (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_SUB_IDATSZ_SHIFT)) & XSPI_TGIPCRS_SUB_IDATSZ_MASK)

#define XSPI_TGIPCRS_SUB_SEQID_MASK              (0xF0000U)
#define XSPI_TGIPCRS_SUB_SEQID_SHIFT             (16U)
/*! SEQID - SEQID Value */
#define XSPI_TGIPCRS_SUB_SEQID(x)                (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_SUB_SEQID_SHIFT)) & XSPI_TGIPCRS_SUB_SEQID_MASK)

#define XSPI_TGIPCRS_SUB_ARB_LOCK_MASK           (0x200000U)
#define XSPI_TGIPCRS_SUB_ARB_LOCK_SHIFT          (21U)
/*! ARB_LOCK - Arbitration Lock
 *  0b0..Not requested
 *  0b1..Requested
 */
#define XSPI_TGIPCRS_SUB_ARB_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_SUB_ARB_LOCK_SHIFT)) & XSPI_TGIPCRS_SUB_ARB_LOCK_MASK)

#define XSPI_TGIPCRS_SUB_ARB_UNLOCK_MASK         (0x400000U)
#define XSPI_TGIPCRS_SUB_ARB_UNLOCK_SHIFT        (22U)
/*! ARB_UNLOCK - Arbitration Unlock
 *  0b0..Not requested
 *  0b1..Requested
 */
#define XSPI_TGIPCRS_SUB_ARB_UNLOCK(x)           (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_SUB_ARB_UNLOCK_SHIFT)) & XSPI_TGIPCRS_SUB_ARB_UNLOCK_MASK)

#define XSPI_TGIPCRS_SUB_CLR_MASK                (0x10000000U)
#define XSPI_TGIPCRS_SUB_CLR_SHIFT               (28U)
/*! CLR - Clear
 *  0b0..Conveys no useful information
 *  0b0..No action
 *  0b1..Clears
 */
#define XSPI_TGIPCRS_SUB_CLR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_SUB_CLR_SHIFT)) & XSPI_TGIPCRS_SUB_CLR_MASK)

#define XSPI_TGIPCRS_SUB_ERR_MASK                (0x60000000U)
#define XSPI_TGIPCRS_SUB_ERR_SHIFT               (29U)
/*! ERR - Error
 *  0b00..Required attributes
 *  0b01..IPCR DATZ without required attributes
 *  0b10..IPCR SEQID without required attributes
 *  0b11..IPCR DATZ and SEQID without required attributes
 */
#define XSPI_TGIPCRS_SUB_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_SUB_ERR_SHIFT)) & XSPI_TGIPCRS_SUB_ERR_MASK)

#define XSPI_TGIPCRS_SUB_VLD_MASK                (0x80000000U)
#define XSPI_TGIPCRS_SUB_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..Not valid
 *  0b1..Valid and queue is locked
 */
#define XSPI_TGIPCRS_SUB_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_SUB_VLD_SHIFT)) & XSPI_TGIPCRS_SUB_VLD_MASK)
/*! @} */

/* The count of XSPI_TGIPCRS_SUB */
#define XSPI_TGIPCRS_SUB_COUNT                   (1U)


/*!
 * @}
 */ /* end of group XSPI_Register_Masks */


/* XSPI - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XSPI0 base address */
  #define XSPI0_BASE                               (0x50184000u)
  /** Peripheral XSPI0 base address */
  #define XSPI0_BASE_NS                            (0x40184000u)
  /** Peripheral XSPI0 base pointer */
  #define XSPI0                                    ((XSPI_Type *)XSPI0_BASE)
  /** Peripheral XSPI0 base pointer */
  #define XSPI0_NS                                 ((XSPI_Type *)XSPI0_BASE_NS)
  /** Peripheral XSPI1 base address */
  #define XSPI1_BASE                               (0x50185000u)
  /** Peripheral XSPI1 base address */
  #define XSPI1_BASE_NS                            (0x40185000u)
  /** Peripheral XSPI1 base pointer */
  #define XSPI1                                    ((XSPI_Type *)XSPI1_BASE)
  /** Peripheral XSPI1 base pointer */
  #define XSPI1_NS                                 ((XSPI_Type *)XSPI1_BASE_NS)
  /** Peripheral XSPI2 base address */
  #define XSPI2_BASE                               (0x50411000u)
  /** Peripheral XSPI2 base address */
  #define XSPI2_BASE_NS                            (0x40411000u)
  /** Peripheral XSPI2 base pointer */
  #define XSPI2                                    ((XSPI_Type *)XSPI2_BASE)
  /** Peripheral XSPI2 base pointer */
  #define XSPI2_NS                                 ((XSPI_Type *)XSPI2_BASE_NS)
  /** Array initializer of XSPI peripheral base addresses */
  #define XSPI_BASE_ADDRS                          { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
  /** Array initializer of XSPI peripheral base pointers */
  #define XSPI_BASE_PTRS                           { XSPI0, XSPI1, XSPI2 }
  /** Array initializer of XSPI peripheral base addresses */
  #define XSPI_BASE_ADDRS_NS                       { XSPI0_BASE_NS, XSPI1_BASE_NS, XSPI2_BASE_NS }
  /** Array initializer of XSPI peripheral base pointers */
  #define XSPI_BASE_PTRS_NS                        { XSPI0_NS, XSPI1_NS, XSPI2_NS }
#else
  /** Peripheral XSPI0 base address */
  #define XSPI0_BASE                               (0x40184000u)
  /** Peripheral XSPI0 base pointer */
  #define XSPI0                                    ((XSPI_Type *)XSPI0_BASE)
  /** Peripheral XSPI1 base address */
  #define XSPI1_BASE                               (0x40185000u)
  /** Peripheral XSPI1 base pointer */
  #define XSPI1                                    ((XSPI_Type *)XSPI1_BASE)
  /** Peripheral XSPI2 base address */
  #define XSPI2_BASE                               (0x40411000u)
  /** Peripheral XSPI2 base pointer */
  #define XSPI2                                    ((XSPI_Type *)XSPI2_BASE)
  /** Array initializer of XSPI peripheral base addresses */
  #define XSPI_BASE_ADDRS                          { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
  /** Array initializer of XSPI peripheral base pointers */
  #define XSPI_BASE_PTRS                           { XSPI0, XSPI1, XSPI2 }
#endif

/*!
 * @}
 */ /* end of group XSPI_Peripheral_Access_Layer */


/*
** End of section using anonymous unions
*/

#if defined(__XTENSA__)
  /* leave anonymous unions enabled */
#else
  #error Not supported compiler type
#endif

/*!
 * @}
 */ /* end of group Peripheral_access_layer */


/* ----------------------------------------------------------------------------
   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
 * @{
 */

/**
 * @brief Mask and left-shift a bit field value for use in a register bit range.
 * @param field Name of the register bit field.
 * @param value Value of the bit field.
 * @return Masked and shifted value.
 */
#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
 * @brief Mask and right-shift a register value to extract a bit field value.
 * @param field Name of the register bit field.
 * @param value Value of the register.
 * @return Masked and shifted bit field value.
 */
#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))

/*!
 * @}
 */ /* end of group Bit_Field_Generic_Macros */


/* ----------------------------------------------------------------------------
   -- SDK Compatibility
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
 * @{
 */

/**  Used for get the base address of ROM API */
#define FSL_ROM_API_BASE_ADDR 0x1302F000U

/*!
 * @}
 */ /* end of group SDK_Compatibility_Symbols */


#endif  /* MIMXRT798S_HIFI4_H_ */